; -------------------------------------------------------------------------------- ; @Title: TDA3x On-Chip Peripherals ; @Props: Released ; @Author: ASK, KMB, PIW ; @Changelog: 2016-03-29 ASK ; 2021-09-02 KMB ; 2022-04-27 PIW ; @Manufacturer: TI - Texas Instruments ; @Doc: XML generated (TIXML2PER 2.0.4), based on: TDA3x.xml (Rev. SR2.0, SR1.0A, SR1.0) ; @Core: Cortex-M4, C66x ; @Chip: TDA3XIPU-CORE0, TDA3XIPU-CORE1, TDA3XDSP*, TDA3XEVE ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: pertda3x.per 17736 2024-04-08 09:26:07Z kwisniewski $ sif (CORENAME()=="CORTEXM4") tree.close "Core Registers (Cortex-M4)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end else AUTOINDENT.PUSH AUTOINDENT.OFF tree "Core Registers (c66x)" config 16. 8. width 0x0b tree.open "Cache" tree "L1P Cache" base d:0x01840000 width 9. group.long 0x20++0x7 "L1P Cache Control Registers" line.long 0x00 "L1PCFG,L1P Configuration Register" bitfld.long 0x00 0.--2. " L1PMODE ,Size of the L1P cache" "Disabled,4K,8K,16K,32K,Maximal,Maximal,Maximal" line.long 0x04 "L1PCC,L1P Cache Control Register" bitfld.long 0x04 16. " POPER ,Holds the previous value of the OPER field" "0,1" bitfld.long 0x04 0. " OPER ,Controls the L1P freeze mode" "Disabled,Enabled" wgroup.long 0x4020++0x3 line.long 0x00 "L1PIBAR,L1P Invalidate Base Address Register" hexmask.long 0x00 0.--31. 1. " L1PIBAR ,32-bit base address for block invalidation" group.long 0x4024++0x3 line.long 0x00 "L1PIWC,L1P Invalidate Word Count" hexmask.long.word 0x00 0.--15. 1. " L1PIWC ,Word count for block invalidation" group.long 0x5028++0x3 line.long 0x00 "L1PINV,L1P Invalidate Register" bitfld.long 0x00 0. " I ,Controls the global invalidation of L1P cache" "Normal,Invalidate" //width 13. //wgroup.long 0xD00++0x13 "Memory Protection Lock Registers" // line.long 0x00 "L1PMPLK0,Memory Protection Lock Register 0" // hexmask.long 0x00 0.--31. 1. " LB ,Lock Bits 31:0" // line.long 0x04 "L1PMPLK1,Memory Protection Lock Register 1" // hexmask.long 0x04 0.--31. 1. " LB ,Lock Bits 63:32" // line.long 0x08 "L1PMPLK2,Memory Protection Lock Register 2" // hexmask.long 0x08 0.--31. 1. " LB ,Lock Bits 95:64" // line.long 0x0c "L1PMPLK3,Memory Protection Lock Register 3" // hexmask.long 0x0c 0.--31. 1. " LB ,Lock Bits 127:96" // line.long 0x10 "L1PMPLKCMD,Memory Protection Lock Command Register" // bitfld.long 0x10 2. " KEYR ,Reset status" "No effect,Reset" // bitfld.long 0x10 1. " LOCK ,Interface to complete a lock sequence" "No effect,Locked" // bitfld.long 0x10 0. " UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked" //rgroup.long 0xD14++0x3 // line.long 0x00 "L1PMPLKSTAT,Memory Protection Lock Status Register" // bitfld.long 0x00 0. " LK ,Indicates the lock's current status" "Disengaged,Engaged" base d:0x0184a000 width 12. tree "Memory Page Protection Attribute Registers" group.long 0x640++0x3f line.long 0x0 "L1PMPPA16,Level 1 Memory Page Protection Attribute Register 16" bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x0 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x0 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x0 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x0 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x0 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x0 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x0 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x0 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x0 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x0 2. " UR ,User read access type" "Normal,User" bitfld.long 0x0 1. " UW ,User write access type" "Normal,User" bitfld.long 0x0 0. " UX ,User execute access type" "Normal,User" line.long 0x4 "L1PMPPA17,Level 1 Memory Page Protection Attribute Register 17" bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x4 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x4 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x4 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x4 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x4 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x4 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x4 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x4 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x4 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x4 2. " UR ,User read access type" "Normal,User" bitfld.long 0x4 1. " UW ,User write access type" "Normal,User" bitfld.long 0x4 0. " UX ,User execute access type" "Normal,User" line.long 0x8 "L1PMPPA18,Level 1 Memory Page Protection Attribute Register 18" bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x8 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x8 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x8 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x8 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x8 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x8 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x8 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x8 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x8 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x8 2. " UR ,User read access type" "Normal,User" bitfld.long 0x8 1. " UW ,User write access type" "Normal,User" bitfld.long 0x8 0. " UX ,User execute access type" "Normal,User" line.long 0xC "L1PMPPA19,Level 1 Memory Page Protection Attribute Register 19" bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0xC 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0xC 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0xC 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0xC 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0xC 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0xC 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0xC 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0xC 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0xC 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0xC 2. " UR ,User read access type" "Normal,User" bitfld.long 0xC 1. " UW ,User write access type" "Normal,User" bitfld.long 0xC 0. " UX ,User execute access type" "Normal,User" line.long 0x10 "L1PMPPA20,Level 1 Memory Page Protection Attribute Register 20" bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x10 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x10 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x10 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x10 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x10 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x10 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x10 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x10 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x10 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x10 2. " UR ,User read access type" "Normal,User" bitfld.long 0x10 1. " UW ,User write access type" "Normal,User" bitfld.long 0x10 0. " UX ,User execute access type" "Normal,User" line.long 0x14 "L1PMPPA21,Level 1 Memory Page Protection Attribute Register 21" bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x14 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x14 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x14 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x14 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x14 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x14 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x14 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x14 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x14 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x14 2. " UR ,User read access type" "Normal,User" bitfld.long 0x14 1. " UW ,User write access type" "Normal,User" bitfld.long 0x14 0. " UX ,User execute access type" "Normal,User" line.long 0x18 "L1PMPPA22,Level 1 Memory Page Protection Attribute Register 22" bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x18 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x18 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x18 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x18 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x18 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x18 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x18 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x18 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x18 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x18 2. " UR ,User read access type" "Normal,User" bitfld.long 0x18 1. " UW ,User write access type" "Normal,User" bitfld.long 0x18 0. " UX ,User execute access type" "Normal,User" line.long 0x1C "L1PMPPA23,Level 1 Memory Page Protection Attribute Register 23" bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x1C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x1C 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x1C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x1C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x1C 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x1C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x1C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x1C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x1C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x1C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x1C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x1C 0. " UX ,User execute access type" "Normal,User" line.long 0x20 "L1PMPPA24,Level 1 Memory Page Protection Attribute Register 24" bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x20 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x20 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x20 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x20 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x20 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x20 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x20 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x20 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x20 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x20 2. " UR ,User read access type" "Normal,User" bitfld.long 0x20 1. " UW ,User write access type" "Normal,User" bitfld.long 0x20 0. " UX ,User execute access type" "Normal,User" line.long 0x24 "L1PMPPA25,Level 1 Memory Page Protection Attribute Register 25" bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x24 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x24 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x24 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x24 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x24 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x24 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x24 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x24 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x24 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x24 2. " UR ,User read access type" "Normal,User" bitfld.long 0x24 1. " UW ,User write access type" "Normal,User" bitfld.long 0x24 0. " UX ,User execute access type" "Normal,User" line.long 0x28 "L1PMPPA26,Level 1 Memory Page Protection Attribute Register 26" bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x28 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x28 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x28 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x28 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x28 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x28 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x28 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x28 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x28 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x28 2. " UR ,User read access type" "Normal,User" bitfld.long 0x28 1. " UW ,User write access type" "Normal,User" bitfld.long 0x28 0. " UX ,User execute access type" "Normal,User" line.long 0x2C "L1PMPPA27,Level 1 Memory Page Protection Attribute Register 27" bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x2C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x2C 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x2C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x2C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x2C 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x2C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x2C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x2C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x2C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x2C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x2C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x2C 0. " UX ,User execute access type" "Normal,User" line.long 0x30 "L1PMPPA28,Level 1 Memory Page Protection Attribute Register 28" bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x30 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x30 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x30 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x30 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x30 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x30 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x30 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x30 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x30 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x30 2. " UR ,User read access type" "Normal,User" bitfld.long 0x30 1. " UW ,User write access type" "Normal,User" bitfld.long 0x30 0. " UX ,User execute access type" "Normal,User" line.long 0x34 "L1PMPPA29,Level 1 Memory Page Protection Attribute Register 29" bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x34 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x34 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x34 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x34 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x34 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x34 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x34 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x34 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x34 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x34 2. " UR ,User read access type" "Normal,User" bitfld.long 0x34 1. " UW ,User write access type" "Normal,User" bitfld.long 0x34 0. " UX ,User execute access type" "Normal,User" line.long 0x38 "L1PMPPA30,Level 1 Memory Page Protection Attribute Register 30" bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x38 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x38 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x38 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x38 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x38 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x38 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x38 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x38 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x38 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x38 2. " UR ,User read access type" "Normal,User" bitfld.long 0x38 1. " UW ,User write access type" "Normal,User" bitfld.long 0x38 0. " UX ,User execute access type" "Normal,User" line.long 0x3C "L1PMPPA31,Level 1 Memory Page Protection Attribute Register 31" bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x3C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x3C 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x3C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x3C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x3C 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x3C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x3C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x3C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x3C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x3C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x3C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x3C 0. " UX ,User execute access type" "Normal,User" tree.end width 11. rgroup.long 0x400++0x7 "Memory Protection Fault Registers" line.long 0x00 "L1PMPFAR,L1P Memory Protection Fault Address" hexmask.long 0x00 0.--31. 1. " FA ,Fault Address" line.long 0x04 "L1PMPFSR,L1P Memory Protection Fault Set Register" hexmask.long.byte 0x04 9.--15. 1. " FID ,Bit 6:0 of faulting requestor" bitfld.long 0x04 8. " LOCAL ,Local access" "Normal,Local" bitfld.long 0x04 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x04 4. " SW ,Supervisor write access type" "Normal,Supervisor" textline " " bitfld.long 0x04 2. " UR ,User read access type" "Normal,User" bitfld.long 0x04 1. " UW ,User write access type" "Normal,User" group.long 0x408++0x3 line.long 0x00 "L1PMPFCLR,L1P Memory Protection Fault Clear" bitfld.long 0x00 0. " MPFCLR ,Command to clear the L1DMPFAR and L1DMPFCR" "No effect,Clear" AUTOINDENT.ON right tree rgroup.long 0x6404++0x3 "Error Detection Registers" line.long 0x0 "L1PEDSTAT,L1P Error Detection Status Register" bitfld.long 0x0 6. "DMAERR,DMA/IDMA access to L1P memory resulted in parity check error" "False,True" bitfld.long 0x0 5. "PERR,Program fetch resulted in parity check error" "False,True" bitfld.long 0x0 3. "SUSP,Error detection logic is suspended" "False,True" bitfld.long 0x0 2. "DIS,Error detection logic is disabled" "False,True" bitfld.long 0x0 0. "EN,Error detection logic is enabled" "False,True" group.long 0x6408++0x3 line.long 0x0 "L1PEDCMD, L1P Error Detection Command Register" bitfld.long 0x0 6. "DMACLR,Clears the DMA/IDMA read parity error status" "No effect,Clear" bitfld.long 0x0 5. "PCLR,Clears the program fetch parity error status" "No effect,Clear" bitfld.long 0x0 3. "SUSP,Suspends the error detection logic" "No effect,Suspend" bitfld.long 0x0 2. "DIS,Disables the error detection logic" "No effect,Disable" bitfld.long 0x0 0. "EN,Enables the error detection logic" "No effect,Enable" rgroup.long 0x640C++0x3 line.long 0x0 "L1PEDADDR, L1P Error Detection Address Register" hexmask.long.long 0x0 5.--31. 32. "ADDR,Contains the upper 27 bit of error location" bitfld.long 0x0 0. "RAM,Location where error was detected" "L1P cache,L1P RAM" AUTOINDENT.OFF width 0xb tree.end tree "L1D Cache" base d:0x01840000 width 10. group.long 0x40++0x7 "L1D Cache Control Registers" line.long 0x00 "L1DCFG,L1D Cache Configuration" bitfld.long 0x00 0.--2. " L1DMODE ,Size of the L1D cache" "Disabled,4K,8K,16K,32K,Maximal,Maximal,Maximal" line.long 0x04 "L1DCC,L1D Cache Control Register" bitfld.long 0x04 16. " POPER ,Holds the previous value of the OPER field" "0,1" bitfld.long 0x04 0. " OPER ,Controls the L1D freeze mode" "Disabled,Enabled" wgroup.long 0x4030++0x3 line.long 0x00 "L1DWIBAR,L1D Writeback-Invalidated Base Address" hexmask.long 0x00 0.--31. 1. " L1DWIBAR ,L1D Writeback-Invalidated Base Address" group.long 0x4034++0x3 line.long 0x00 "L1DWIWC,L1D Writeback-Invalidated Word Count" hexmask.long.word 0x00 0.--15. 1. " L1DWIWC ,L1D Writeback-Invalidated Word Count" wgroup.long 0x4040++0x3 line.long 0x00 "L1DWBAR,L1D Writeback Base Address" hexmask.long 0x00 0.--31. 1. " L1DWBAR ,L1D Writeback Base Address" group.long 0x4044++0x3 line.long 0x00 "L1DWWC,L1D Writeback Word Count" hexmask.long.word 0x00 0.--15. 1. " L1DWWC ,L1D Writeback Word Count" wgroup.long 0x4048++0x3 line.long 0x00 "L1DIBAR,L1D Invalidate Base Address" hexmask.long 0x00 0.--31. 1. " L1DIBAR ,L1D Invalidate Base Address" group.long 0x404c++0x3 line.long 0x00 "L1DIWC,L1D Invalidate Word Count" hexmask.long.word 0x00 0.--15. 1. " L1DIWC ,L1D Invalidate Word Count" group.long 0x5048++0x3 line.long 0x00 "L1DINV,L1D Invalidate Register" bitfld.long 0x00 0. " I ,Controls the global invalidation of L1D cache" "Normal,Invalidate" group.long 0x5040++0x3 line.long 0x00 "L1DWB,L1P Writeback Register" bitfld.long 0x00 0. " C ,Controls the global writeback operation of L1D cache" "Normal,Write back" group.long 0x5044++0x3 line.long 0x00 "L1DWBINV,L1D Writeback-Invalidate Register" bitfld.long 0x00 0. " C ,Controls the global writeback-invalidate operation of L1D cache" "Normal,Invalidate" width 11. base d:0x0184a000 tree "Memory Protection Attribute Registers" group.long 0xe40++0x3f line.long 0x0 "MPPA16,Memory Protection Attribute Register" bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x0 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x0 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x0 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x0 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x0 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x0 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x0 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x0 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x0 2. " UR ,User read access type" "Normal,User" bitfld.long 0x0 1. " UW ,User write access type" "Normal,User" line.long 0x4 "MPPA17,Memory Protection Attribute Register" bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x4 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x4 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x4 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x4 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x4 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x4 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x4 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x4 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x4 2. " UR ,User read access type" "Normal,User" bitfld.long 0x4 1. " UW ,User write access type" "Normal,User" line.long 0x8 "MPPA18,Memory Protection Attribute Register" bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x8 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x8 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x8 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x8 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x8 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x8 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x8 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x8 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x8 2. " UR ,User read access type" "Normal,User" bitfld.long 0x8 1. " UW ,User write access type" "Normal,User" line.long 0xC "MPPA19,Memory Protection Attribute Register" bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0xC 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0xC 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0xC 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0xC 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0xC 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0xC 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0xC 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0xC 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0xC 2. " UR ,User read access type" "Normal,User" bitfld.long 0xC 1. " UW ,User write access type" "Normal,User" line.long 0x10 "MPPA20,Memory Protection Attribute Register" bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x10 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x10 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x10 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x10 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x10 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x10 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x10 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x10 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x10 2. " UR ,User read access type" "Normal,User" bitfld.long 0x10 1. " UW ,User write access type" "Normal,User" line.long 0x14 "MPPA21,Memory Protection Attribute Register" bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x14 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x14 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x14 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x14 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x14 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x14 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x14 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x14 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x14 2. " UR ,User read access type" "Normal,User" bitfld.long 0x14 1. " UW ,User write access type" "Normal,User" line.long 0x18 "MPPA22,Memory Protection Attribute Register" bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x18 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x18 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x18 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x18 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x18 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x18 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x18 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x18 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x18 2. " UR ,User read access type" "Normal,User" bitfld.long 0x18 1. " UW ,User write access type" "Normal,User" line.long 0x1C "MPPA23,Memory Protection Attribute Register" bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x1C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x1C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x1C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x1C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x1C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x1C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x1C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x1C 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x1C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x1C 1. " UW ,User write access type" "Normal,User" line.long 0x20 "MPPA24,Memory Protection Attribute Register" bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x20 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x20 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x20 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x20 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x20 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x20 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x20 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x20 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x20 2. " UR ,User read access type" "Normal,User" bitfld.long 0x20 1. " UW ,User write access type" "Normal,User" line.long 0x24 "MPPA25,Memory Protection Attribute Register" bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x24 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x24 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x24 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x24 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x24 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x24 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x24 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x24 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x24 2. " UR ,User read access type" "Normal,User" bitfld.long 0x24 1. " UW ,User write access type" "Normal,User" line.long 0x28 "MPPA26,Memory Protection Attribute Register" bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x28 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x28 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x28 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x28 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x28 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x28 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x28 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x28 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x28 2. " UR ,User read access type" "Normal,User" bitfld.long 0x28 1. " UW ,User write access type" "Normal,User" line.long 0x2C "MPPA27,Memory Protection Attribute Register" bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x2C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x2C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x2C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x2C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x2C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x2C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x2C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x2C 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x2C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x2C 1. " UW ,User write access type" "Normal,User" line.long 0x30 "MPPA28,Memory Protection Attribute Register" bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x30 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x30 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x30 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x30 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x30 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x30 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x30 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x30 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x30 2. " UR ,User read access type" "Normal,User" bitfld.long 0x30 1. " UW ,User write access type" "Normal,User" line.long 0x34 "MPPA29,Memory Protection Attribute Register" bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x34 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x34 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x34 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x34 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x34 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x34 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x34 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x34 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x34 2. " UR ,User read access type" "Normal,User" bitfld.long 0x34 1. " UW ,User write access type" "Normal,User" line.long 0x38 "MPPA30,Memory Protection Attribute Register" bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x38 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x38 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x38 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x38 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x38 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x38 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x38 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x38 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x38 2. " UR ,User read access type" "Normal,User" bitfld.long 0x38 1. " UW ,User write access type" "Normal,User" line.long 0x3C "MPPA31,Memory Protection Attribute Register" bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x3C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x3C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x3C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x3C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x3C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x3C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x3C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x3C 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x3C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x3C 1. " UW ,User write access type" "Normal,User" tree.end base d:0x0184a000 width 10. rgroup.long 0xc00++0x7 "Memory Protection Fault Registers" line.long 0x00 "L1DMPFAR,Memory Protection Fault Address Register" hexmask.long 0x00 0.--31. 1. " FA ,Fault Address" line.long 0x04 "L1DMPFSR,Memory Protection Fault Set Register" hexmask.long.byte 0x04 9.--15. 1. " FID ,Bit 6:0 of ID of faulting requestor" bitfld.long 0x04 8. " LOCAL ,Local access" "Normal,Supervisor" bitfld.long 0x04 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x04 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x04 2. " UR ,User read access type" "Normal,User" bitfld.long 0x04 1. " UW ,User write access type" "Normal,User" group.long 0xc08++0x3 line.long 0x00 "L1DMPFCR,Memory Protection Fault Clear Register" eventfld.long 0x00 0. " MPFCLR ,Clear L1DMPFAR and L1DMPFCR" "No effect,Cleared" width 13. wgroup.long 0xd00++0xf "Memory Protection Lock Registers" line.long 0x00 "L1DMPLK0,Level 1 Data Memory Protection Lock Register 0" hexmask.long 0x00 0.--31. 1. " LB ,Lock Bits 31:0" line.long 0x04 "L1DMPLK1,Level 1 Data Memory Protection Lock Register 1" hexmask.long 0x04 0.--31. 1. " LB ,Lock Bits 63:32" line.long 0x08 "L1DMPLK2,Level 1 Data Memory Protection Lock Register 2" line.long 0x0c "L1DMPLK3,Level 1 Data Memory Protection Lock Register 3" wgroup.long 0xd10++0x3 line.long 0x00 "L1DMPLKCMD,Level 1 Data Memory Protection Lock Command Register" bitfld.long 0x00 2. " KEYR ,Reset status" "No effect,Reset" bitfld.long 0x00 1. " LOCK ,Interface to complete a lock sequence" "No effect,Locked" bitfld.long 0x00 0. " UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked" rgroup.long 0xd14++0x3 line.long 0x00 "L1DMPLKSTAT,Level 1 Data Memory Protection Lock Status Register" bitfld.long 0x00 0. " LK ,Indicates the lock's current status" "Disengaged,Engaged" width 0xb tree.end tree "L2 Cache" base d:0x01840000 width 9. group.long 0x00++0x3 "L2 Cache Control Registers" line.long 0x00 "L2CFG,L2 Configuration Register" hexmask.long.byte 0x00 24.--27. 1. " NUM_MM ,Number of megamodules minus one" hexmask.long.byte 0x00 16.--19. 1. " MMID ,Contains the Megamodule ID number" bitfld.long 0x00 9. " IP ,L1P global invalidate bit" "Normal,Invalidate" textline " " bitfld.long 0x00 8. " ID ,L1D global invalidate bit" "Normal,Invalidate" bitfld.long 0x00 3. " L2CC ,Freeze mode" "Normal,Frozen" bitfld.long 0x00 0.--2. " L2MODE ,Size of L2 cache" "Disabled,32K,64K,128K,256K,512K,1024K,Maximum" wgroup.long 0x4000++0x3 line.long 0x00 "L2WBAR,L2 Writeback Base Address Register" hexmask.long 0x00 0.--31. 1. " L2WBAR ,L2 Writeback Base Address" group.long 0x4004++0x3 line.long 0x00 "L2WWC,L2 Writeback Word Count Register" hexmask.long.word 0x00 0.--15. 1. " L2WWC ,L2 Writeback Word Count" wgroup.long 0x4010++0x3 line.long 0x00 "L2WIBAR,L2 Writeback-Invalidate Base Address" hexmask.long 0x00 0.--31. 1. " L2WIBAR ,L2 Writeback Invalidate Base Address" group.long 0x4014++0x3 line.long 0x00 "L2WIWC,L2 Writeback Invalidate Word Count Register" hexmask.long.word 0x00 0.--15. 1. " L2WIWC ,L2 Writeback Invalidate Word Count" wgroup.long 0x4018++0x3 line.long 0x00 "L2IBAR,L2 Invalidate Base Address Register" hexmask.long 0x00 0.--31. 1. " L2IBAR ,L2 Invalidate Base Address" group.long 0x401c++0x3 line.long 0x00 "L2IWC,L2 Invalidate Word Count Register" hexmask.long.word 0x00 0.--15. 1. " L2IWC ,L2 Invalidate Word Count" group.long 0x5000++0xb line.long 0x00 "L2WB,L2 Writeback Register" bitfld.long 0x00 0. " C ,Controls the global writeback operation of L2 cache" "Normal,Writeback" line.long 0x04 "L2WBINV,L2 Writeback-Invalidate Register" bitfld.long 0x04 0. " C ,Controls the global writeback-invalidate operation of L2 cache" "Normal,Writeback" line.long 0x08 "L2INV,L2 Invalidate Register" bitfld.long 0x08 0. " I ,Controls the global invalidation of L2 cache" "Normal,Invalidate" tree "Memory Attribute Registers" width 8. base d:0x01848000 rgroup.long 0x00++0x2f line.long 0x0 "MAR0,Memory Attribute Register 0" bitfld.long 0x0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x4 "MAR1,Memory Attribute Register 1" bitfld.long 0x4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x8 "MAR2,Memory Attribute Register 2" bitfld.long 0x8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xC "MAR3,Memory Attribute Register 3" bitfld.long 0xC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x10 "MAR4,Memory Attribute Register 4" bitfld.long 0x10 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x10 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x14 "MAR5,Memory Attribute Register 5" bitfld.long 0x14 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x14 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x18 "MAR6,Memory Attribute Register 6" bitfld.long 0x18 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x18 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1C "MAR7,Memory Attribute Register 7" bitfld.long 0x1C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x20 "MAR8,Memory Attribute Register 8" bitfld.long 0x20 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x20 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x24 "MAR9,Memory Attribute Register 9" bitfld.long 0x24 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x24 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x28 "MAR10,Memory Attribute Register 10" bitfld.long 0x28 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x28 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2C "MAR11,Memory Attribute Register 11" bitfld.long 0x2C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" group.long 0x30++0x3cf line.long 0x0 "MAR12,Memory Attribute Register 12" bitfld.long 0x0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x4 "MAR13,Memory Attribute Register 13" bitfld.long 0x4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x8 "MAR14,Memory Attribute Register 14" bitfld.long 0x8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xC "MAR15,Memory Attribute Register 15" bitfld.long 0xC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x10 "MAR16,Memory Attribute Register 16" bitfld.long 0x10 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x10 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x14 "MAR17,Memory Attribute Register 17" bitfld.long 0x14 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x14 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x18 "MAR18,Memory Attribute Register 18" bitfld.long 0x18 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x18 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1C "MAR19,Memory Attribute Register 19" bitfld.long 0x1C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x20 "MAR20,Memory Attribute Register 20" bitfld.long 0x20 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x20 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x24 "MAR21,Memory Attribute Register 21" bitfld.long 0x24 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x24 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x28 "MAR22,Memory Attribute Register 22" bitfld.long 0x28 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x28 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2C "MAR23,Memory Attribute Register 23" bitfld.long 0x2C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x30 "MAR24,Memory Attribute Register 24" bitfld.long 0x30 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x30 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x34 "MAR25,Memory Attribute Register 25" bitfld.long 0x34 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x34 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x38 "MAR26,Memory Attribute Register 26" bitfld.long 0x38 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x38 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3C "MAR27,Memory Attribute Register 27" bitfld.long 0x3C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x40 "MAR28,Memory Attribute Register 28" bitfld.long 0x40 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x40 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x44 "MAR29,Memory Attribute Register 29" bitfld.long 0x44 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x44 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x48 "MAR30,Memory Attribute Register 30" bitfld.long 0x48 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x48 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x4C "MAR31,Memory Attribute Register 31" bitfld.long 0x4C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x4C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x50 "MAR32,Memory Attribute Register 32" bitfld.long 0x50 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x50 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x54 "MAR33,Memory Attribute Register 33" bitfld.long 0x54 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x54 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x58 "MAR34,Memory Attribute Register 34" bitfld.long 0x58 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x58 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x5C "MAR35,Memory Attribute Register 35" bitfld.long 0x5C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x5C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x60 "MAR36,Memory Attribute Register 36" bitfld.long 0x60 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x60 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x64 "MAR37,Memory Attribute Register 37" bitfld.long 0x64 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x64 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x68 "MAR38,Memory Attribute Register 38" bitfld.long 0x68 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x68 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x6C "MAR39,Memory Attribute Register 39" bitfld.long 0x6C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x6C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x70 "MAR40,Memory Attribute Register 40" bitfld.long 0x70 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x70 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x74 "MAR41,Memory Attribute Register 41" bitfld.long 0x74 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x74 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x78 "MAR42,Memory Attribute Register 42" bitfld.long 0x78 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x78 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x7C "MAR43,Memory Attribute Register 43" bitfld.long 0x7C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x7C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x80 "MAR44,Memory Attribute Register 44" bitfld.long 0x80 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x80 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x84 "MAR45,Memory Attribute Register 45" bitfld.long 0x84 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x84 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x88 "MAR46,Memory Attribute Register 46" bitfld.long 0x88 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x88 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x8C "MAR47,Memory Attribute Register 47" bitfld.long 0x8C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x8C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x90 "MAR48,Memory Attribute Register 48" bitfld.long 0x90 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x90 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x94 "MAR49,Memory Attribute Register 49" bitfld.long 0x94 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x94 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x98 "MAR50,Memory Attribute Register 50" bitfld.long 0x98 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x98 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x9C "MAR51,Memory Attribute Register 51" bitfld.long 0x9C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x9C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xA0 "MAR52,Memory Attribute Register 52" bitfld.long 0xA0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xA0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xA4 "MAR53,Memory Attribute Register 53" bitfld.long 0xA4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xA4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xA8 "MAR54,Memory Attribute Register 54" bitfld.long 0xA8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xA8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xAC "MAR55,Memory Attribute Register 55" bitfld.long 0xAC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xAC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xB0 "MAR56,Memory Attribute Register 56" bitfld.long 0xB0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xB0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xB4 "MAR57,Memory Attribute Register 57" bitfld.long 0xB4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xB4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xB8 "MAR58,Memory Attribute Register 58" bitfld.long 0xB8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xB8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xBC "MAR59,Memory Attribute Register 59" bitfld.long 0xBC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xBC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xC0 "MAR60,Memory Attribute Register 60" bitfld.long 0xC0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xC0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xC4 "MAR61,Memory Attribute Register 61" bitfld.long 0xC4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xC4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xC8 "MAR62,Memory Attribute Register 62" bitfld.long 0xC8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xC8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xCC "MAR63,Memory Attribute Register 63" bitfld.long 0xCC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xCC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xD0 "MAR64,Memory Attribute Register 64" bitfld.long 0xD0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xD0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xD4 "MAR65,Memory Attribute Register 65" bitfld.long 0xD4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xD4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xD8 "MAR66,Memory Attribute Register 66" bitfld.long 0xD8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xD8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xDC "MAR67,Memory Attribute Register 67" bitfld.long 0xDC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xDC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xE0 "MAR68,Memory Attribute Register 68" bitfld.long 0xE0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xE0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xE4 "MAR69,Memory Attribute Register 69" bitfld.long 0xE4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xE4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xE8 "MAR70,Memory Attribute Register 70" bitfld.long 0xE8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xE8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xEC "MAR71,Memory Attribute Register 71" bitfld.long 0xEC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xEC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xF0 "MAR72,Memory Attribute Register 72" bitfld.long 0xF0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xF0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xF4 "MAR73,Memory Attribute Register 73" bitfld.long 0xF4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xF4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xF8 "MAR74,Memory Attribute Register 74" bitfld.long 0xF8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xF8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xFC "MAR75,Memory Attribute Register 75" bitfld.long 0xFC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xFC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x100 "MAR76,Memory Attribute Register 76" bitfld.long 0x100 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x100 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x104 "MAR77,Memory Attribute Register 77" bitfld.long 0x104 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x104 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x108 "MAR78,Memory Attribute Register 78" bitfld.long 0x108 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x108 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x10C "MAR79,Memory Attribute Register 79" bitfld.long 0x10C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x10C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x110 "MAR80,Memory Attribute Register 80" bitfld.long 0x110 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x110 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x114 "MAR81,Memory Attribute Register 81" bitfld.long 0x114 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x114 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x118 "MAR82,Memory Attribute Register 82" bitfld.long 0x118 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x118 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x11C "MAR83,Memory Attribute Register 83" bitfld.long 0x11C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x11C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x120 "MAR84,Memory Attribute Register 84" bitfld.long 0x120 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x120 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x124 "MAR85,Memory Attribute Register 85" bitfld.long 0x124 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x124 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x128 "MAR86,Memory Attribute Register 86" bitfld.long 0x128 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x128 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x12C "MAR87,Memory Attribute Register 87" bitfld.long 0x12C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x12C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x130 "MAR88,Memory Attribute Register 88" bitfld.long 0x130 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x130 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x134 "MAR89,Memory Attribute Register 89" bitfld.long 0x134 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x134 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x138 "MAR90,Memory Attribute Register 90" bitfld.long 0x138 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x138 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x13C "MAR91,Memory Attribute Register 91" bitfld.long 0x13C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x13C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x140 "MAR92,Memory Attribute Register 92" bitfld.long 0x140 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x140 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x144 "MAR93,Memory Attribute Register 93" bitfld.long 0x144 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x144 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x148 "MAR94,Memory Attribute Register 94" bitfld.long 0x148 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x148 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x14C "MAR95,Memory Attribute Register 95" bitfld.long 0x14C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x14C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x150 "MAR96,Memory Attribute Register 96" bitfld.long 0x150 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x150 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x154 "MAR97,Memory Attribute Register 97" bitfld.long 0x154 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x154 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x158 "MAR98,Memory Attribute Register 98" bitfld.long 0x158 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x158 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x15C "MAR99,Memory Attribute Register 99" bitfld.long 0x15C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x15C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x160 "MAR100,Memory Attribute Register 100" bitfld.long 0x160 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x160 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x164 "MAR101,Memory Attribute Register 101" bitfld.long 0x164 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x164 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x168 "MAR102,Memory Attribute Register 102" bitfld.long 0x168 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x168 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x16C "MAR103,Memory Attribute Register 103" bitfld.long 0x16C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x16C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x170 "MAR104,Memory Attribute Register 104" bitfld.long 0x170 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x170 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x174 "MAR105,Memory Attribute Register 105" bitfld.long 0x174 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x174 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x178 "MAR106,Memory Attribute Register 106" bitfld.long 0x178 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x178 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x17C "MAR107,Memory Attribute Register 107" bitfld.long 0x17C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x17C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x180 "MAR108,Memory Attribute Register 108" bitfld.long 0x180 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x180 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x184 "MAR109,Memory Attribute Register 109" bitfld.long 0x184 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x184 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x188 "MAR110,Memory Attribute Register 110" bitfld.long 0x188 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x188 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x18C "MAR111,Memory Attribute Register 111" bitfld.long 0x18C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x18C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x190 "MAR112,Memory Attribute Register 112" bitfld.long 0x190 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x190 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x194 "MAR113,Memory Attribute Register 113" bitfld.long 0x194 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x194 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x198 "MAR114,Memory Attribute Register 114" bitfld.long 0x198 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x198 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x19C "MAR115,Memory Attribute Register 115" bitfld.long 0x19C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x19C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1A0 "MAR116,Memory Attribute Register 116" bitfld.long 0x1A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1A0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1A4 "MAR117,Memory Attribute Register 117" bitfld.long 0x1A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1A4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1A8 "MAR118,Memory Attribute Register 118" bitfld.long 0x1A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1A8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1AC "MAR119,Memory Attribute Register 119" bitfld.long 0x1AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1AC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1B0 "MAR120,Memory Attribute Register 120" bitfld.long 0x1B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1B0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1B4 "MAR121,Memory Attribute Register 121" bitfld.long 0x1B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1B4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1B8 "MAR122,Memory Attribute Register 122" bitfld.long 0x1B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1B8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1BC "MAR123,Memory Attribute Register 123" bitfld.long 0x1BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1BC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1C0 "MAR124,Memory Attribute Register 124" bitfld.long 0x1C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1C0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1C4 "MAR125,Memory Attribute Register 125" bitfld.long 0x1C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1C4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1C8 "MAR126,Memory Attribute Register 126" bitfld.long 0x1C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1C8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1CC "MAR127,Memory Attribute Register 127" bitfld.long 0x1CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1CC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1D0 "MAR128,Memory Attribute Register 128" bitfld.long 0x1D0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1D0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1D4 "MAR129,Memory Attribute Register 129" bitfld.long 0x1D4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1D4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1D8 "MAR130,Memory Attribute Register 130" bitfld.long 0x1D8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1D8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1DC "MAR131,Memory Attribute Register 131" bitfld.long 0x1DC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1DC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1E0 "MAR132,Memory Attribute Register 132" bitfld.long 0x1E0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1E0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1E4 "MAR133,Memory Attribute Register 133" bitfld.long 0x1E4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1E4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1E8 "MAR134,Memory Attribute Register 134" bitfld.long 0x1E8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1E8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1EC "MAR135,Memory Attribute Register 135" bitfld.long 0x1EC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1EC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1F0 "MAR136,Memory Attribute Register 136" bitfld.long 0x1F0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1F0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1F4 "MAR137,Memory Attribute Register 137" bitfld.long 0x1F4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1F4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1F8 "MAR138,Memory Attribute Register 138" bitfld.long 0x1F8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1F8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1FC "MAR139,Memory Attribute Register 139" bitfld.long 0x1FC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1FC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x200 "MAR140,Memory Attribute Register 140" bitfld.long 0x200 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x200 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x204 "MAR141,Memory Attribute Register 141" bitfld.long 0x204 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x204 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x208 "MAR142,Memory Attribute Register 142" bitfld.long 0x208 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x208 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x20C "MAR143,Memory Attribute Register 143" bitfld.long 0x20C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x20C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x210 "MAR144,Memory Attribute Register 144" bitfld.long 0x210 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x210 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x214 "MAR145,Memory Attribute Register 145" bitfld.long 0x214 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x214 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x218 "MAR146,Memory Attribute Register 146" bitfld.long 0x218 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x218 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x21C "MAR147,Memory Attribute Register 147" bitfld.long 0x21C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x21C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x220 "MAR148,Memory Attribute Register 148" bitfld.long 0x220 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x220 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x224 "MAR149,Memory Attribute Register 149" bitfld.long 0x224 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x224 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x228 "MAR150,Memory Attribute Register 150" bitfld.long 0x228 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x228 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x22C "MAR151,Memory Attribute Register 151" bitfld.long 0x22C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x22C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x230 "MAR152,Memory Attribute Register 152" bitfld.long 0x230 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x230 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x234 "MAR153,Memory Attribute Register 153" bitfld.long 0x234 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x234 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x238 "MAR154,Memory Attribute Register 154" bitfld.long 0x238 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x238 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x23C "MAR155,Memory Attribute Register 155" bitfld.long 0x23C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x23C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x240 "MAR156,Memory Attribute Register 156" bitfld.long 0x240 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x240 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x244 "MAR157,Memory Attribute Register 157" bitfld.long 0x244 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x244 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x248 "MAR158,Memory Attribute Register 158" bitfld.long 0x248 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x248 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x24C "MAR159,Memory Attribute Register 159" bitfld.long 0x24C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x24C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x250 "MAR160,Memory Attribute Register 160" bitfld.long 0x250 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x250 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x254 "MAR161,Memory Attribute Register 161" bitfld.long 0x254 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x254 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x258 "MAR162,Memory Attribute Register 162" bitfld.long 0x258 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x258 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x25C "MAR163,Memory Attribute Register 163" bitfld.long 0x25C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x25C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x260 "MAR164,Memory Attribute Register 164" bitfld.long 0x260 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x260 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x264 "MAR165,Memory Attribute Register 165" bitfld.long 0x264 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x264 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x268 "MAR166,Memory Attribute Register 166" bitfld.long 0x268 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x268 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x26C "MAR167,Memory Attribute Register 167" bitfld.long 0x26C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x26C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x270 "MAR168,Memory Attribute Register 168" bitfld.long 0x270 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x270 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x274 "MAR169,Memory Attribute Register 169" bitfld.long 0x274 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x274 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x278 "MAR170,Memory Attribute Register 170" bitfld.long 0x278 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x278 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x27C "MAR171,Memory Attribute Register 171" bitfld.long 0x27C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x27C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x280 "MAR172,Memory Attribute Register 172" bitfld.long 0x280 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x280 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x284 "MAR173,Memory Attribute Register 173" bitfld.long 0x284 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x284 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x288 "MAR174,Memory Attribute Register 174" bitfld.long 0x288 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x288 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x28C "MAR175,Memory Attribute Register 175" bitfld.long 0x28C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x28C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x290 "MAR176,Memory Attribute Register 176" bitfld.long 0x290 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x290 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x294 "MAR177,Memory Attribute Register 177" bitfld.long 0x294 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x294 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x298 "MAR178,Memory Attribute Register 178" bitfld.long 0x298 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x298 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x29C "MAR179,Memory Attribute Register 179" bitfld.long 0x29C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x29C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2A0 "MAR180,Memory Attribute Register 180" bitfld.long 0x2A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2A0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2A4 "MAR181,Memory Attribute Register 181" bitfld.long 0x2A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2A4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2A8 "MAR182,Memory Attribute Register 182" bitfld.long 0x2A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2A8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2AC "MAR183,Memory Attribute Register 183" bitfld.long 0x2AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2AC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2B0 "MAR184,Memory Attribute Register 184" bitfld.long 0x2B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2B0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2B4 "MAR185,Memory Attribute Register 185" bitfld.long 0x2B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2B4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2B8 "MAR186,Memory Attribute Register 186" bitfld.long 0x2B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2B8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2BC "MAR187,Memory Attribute Register 187" bitfld.long 0x2BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2BC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2C0 "MAR188,Memory Attribute Register 188" bitfld.long 0x2C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2C0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2C4 "MAR189,Memory Attribute Register 189" bitfld.long 0x2C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2C4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2C8 "MAR190,Memory Attribute Register 190" bitfld.long 0x2C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2C8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2CC "MAR191,Memory Attribute Register 191" bitfld.long 0x2CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2CC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2D0 "MAR192,Memory Attribute Register 192" bitfld.long 0x2D0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2D0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2D4 "MAR193,Memory Attribute Register 193" bitfld.long 0x2D4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2D4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2D8 "MAR194,Memory Attribute Register 194" bitfld.long 0x2D8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2D8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2DC "MAR195,Memory Attribute Register 195" bitfld.long 0x2DC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2DC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2E0 "MAR196,Memory Attribute Register 196" bitfld.long 0x2E0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2E0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2E4 "MAR197,Memory Attribute Register 197" bitfld.long 0x2E4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2E4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2E8 "MAR198,Memory Attribute Register 198" bitfld.long 0x2E8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2E8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2EC "MAR199,Memory Attribute Register 199" bitfld.long 0x2EC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2EC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2F0 "MAR200,Memory Attribute Register 200" bitfld.long 0x2F0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2F0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2F4 "MAR201,Memory Attribute Register 201" bitfld.long 0x2F4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2F4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2F8 "MAR202,Memory Attribute Register 202" bitfld.long 0x2F8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2F8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2FC "MAR203,Memory Attribute Register 203" bitfld.long 0x2FC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2FC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x300 "MAR204,Memory Attribute Register 204" bitfld.long 0x300 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x300 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x304 "MAR205,Memory Attribute Register 205" bitfld.long 0x304 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x304 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x308 "MAR206,Memory Attribute Register 206" bitfld.long 0x308 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x308 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x30C "MAR207,Memory Attribute Register 207" bitfld.long 0x30C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x30C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x310 "MAR208,Memory Attribute Register 208" bitfld.long 0x310 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x310 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x314 "MAR209,Memory Attribute Register 209" bitfld.long 0x314 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x314 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x318 "MAR210,Memory Attribute Register 210" bitfld.long 0x318 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x318 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x31C "MAR211,Memory Attribute Register 211" bitfld.long 0x31C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x31C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x320 "MAR212,Memory Attribute Register 212" bitfld.long 0x320 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x320 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x324 "MAR213,Memory Attribute Register 213" bitfld.long 0x324 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x324 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x328 "MAR214,Memory Attribute Register 214" bitfld.long 0x328 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x328 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x32C "MAR215,Memory Attribute Register 215" bitfld.long 0x32C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x32C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x330 "MAR216,Memory Attribute Register 216" bitfld.long 0x330 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x330 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x334 "MAR217,Memory Attribute Register 217" bitfld.long 0x334 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x334 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x338 "MAR218,Memory Attribute Register 218" bitfld.long 0x338 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x338 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x33C "MAR219,Memory Attribute Register 219" bitfld.long 0x33C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x33C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x340 "MAR220,Memory Attribute Register 220" bitfld.long 0x340 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x340 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x344 "MAR221,Memory Attribute Register 221" bitfld.long 0x344 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x344 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x348 "MAR222,Memory Attribute Register 222" bitfld.long 0x348 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x348 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x34C "MAR223,Memory Attribute Register 223" bitfld.long 0x34C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x34C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x350 "MAR224,Memory Attribute Register 224" bitfld.long 0x350 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x350 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x354 "MAR225,Memory Attribute Register 225" bitfld.long 0x354 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x354 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x358 "MAR226,Memory Attribute Register 226" bitfld.long 0x358 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x358 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x35C "MAR227,Memory Attribute Register 227" bitfld.long 0x35C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x35C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x360 "MAR228,Memory Attribute Register 228" bitfld.long 0x360 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x360 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x364 "MAR229,Memory Attribute Register 229" bitfld.long 0x364 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x364 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x368 "MAR230,Memory Attribute Register 230" bitfld.long 0x368 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x368 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x36C "MAR231,Memory Attribute Register 231" bitfld.long 0x36C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x36C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x370 "MAR232,Memory Attribute Register 232" bitfld.long 0x370 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x370 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x374 "MAR233,Memory Attribute Register 233" bitfld.long 0x374 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x374 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x378 "MAR234,Memory Attribute Register 234" bitfld.long 0x378 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x378 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x37C "MAR235,Memory Attribute Register 235" bitfld.long 0x37C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x37C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x380 "MAR236,Memory Attribute Register 236" bitfld.long 0x380 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x380 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x384 "MAR237,Memory Attribute Register 237" bitfld.long 0x384 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x384 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x388 "MAR238,Memory Attribute Register 238" bitfld.long 0x388 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x388 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x38C "MAR239,Memory Attribute Register 239" bitfld.long 0x38C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x38C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x390 "MAR240,Memory Attribute Register 240" bitfld.long 0x390 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x390 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x394 "MAR241,Memory Attribute Register 241" bitfld.long 0x394 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x394 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x398 "MAR242,Memory Attribute Register 242" bitfld.long 0x398 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x398 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x39C "MAR243,Memory Attribute Register 243" bitfld.long 0x39C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x39C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3A0 "MAR244,Memory Attribute Register 244" bitfld.long 0x3A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3A0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3A4 "MAR245,Memory Attribute Register 245" bitfld.long 0x3A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3A4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3A8 "MAR246,Memory Attribute Register 246" bitfld.long 0x3A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3A8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3AC "MAR247,Memory Attribute Register 247" bitfld.long 0x3AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3AC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3B0 "MAR248,Memory Attribute Register 248" bitfld.long 0x3B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3B0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3B4 "MAR249,Memory Attribute Register 249" bitfld.long 0x3B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3B4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3B8 "MAR250,Memory Attribute Register 250" bitfld.long 0x3B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3B8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3BC "MAR251,Memory Attribute Register 251" bitfld.long 0x3BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3BC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3C0 "MAR252,Memory Attribute Register 252" bitfld.long 0x3C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3C0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3C4 "MAR253,Memory Attribute Register 253" bitfld.long 0x3C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3C4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3C8 "MAR254,Memory Attribute Register 254" bitfld.long 0x3C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3C8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3CC "MAR255,Memory Attribute Register 255" bitfld.long 0x3CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3CC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" tree.end width 10. base d:0x0184a000 tree "Memory Protection Page Attribute Registers" group.long 0x200++0x7f line.long 0x0 "L2MPPA0,Level 2 Memory Protection Page Attribute Register 0" bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x0 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x0 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x0 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x0 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x0 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x0 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x0 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x0 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x0 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x0 2. " UR ,User read access type" "Normal,User" bitfld.long 0x0 1. " UW ,User write access type" "Normal,User" bitfld.long 0x0 0. " UX ,User execute access type" "Normal,User" line.long 0x4 "L2MPPA1,Level 2 Memory Protection Page Attribute Register 1" bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x4 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x4 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x4 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x4 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x4 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x4 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x4 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x4 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x4 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x4 2. " UR ,User read access type" "Normal,User" bitfld.long 0x4 1. " UW ,User write access type" "Normal,User" bitfld.long 0x4 0. " UX ,User execute access type" "Normal,User" line.long 0x8 "L2MPPA2,Level 2 Memory Protection Page Attribute Register 2" bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x8 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x8 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x8 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x8 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x8 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x8 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x8 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x8 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x8 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x8 2. " UR ,User read access type" "Normal,User" bitfld.long 0x8 1. " UW ,User write access type" "Normal,User" bitfld.long 0x8 0. " UX ,User execute access type" "Normal,User" line.long 0xC "L2MPPA3,Level 2 Memory Protection Page Attribute Register 3" bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0xC 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0xC 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0xC 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0xC 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0xC 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0xC 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0xC 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0xC 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0xC 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0xC 2. " UR ,User read access type" "Normal,User" bitfld.long 0xC 1. " UW ,User write access type" "Normal,User" bitfld.long 0xC 0. " UX ,User execute access type" "Normal,User" line.long 0x10 "L2MPPA4,Level 2 Memory Protection Page Attribute Register 4" bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x10 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x10 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x10 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x10 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x10 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x10 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x10 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x10 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x10 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x10 2. " UR ,User read access type" "Normal,User" bitfld.long 0x10 1. " UW ,User write access type" "Normal,User" bitfld.long 0x10 0. " UX ,User execute access type" "Normal,User" line.long 0x14 "L2MPPA5,Level 2 Memory Protection Page Attribute Register 5" bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x14 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x14 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x14 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x14 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x14 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x14 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x14 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x14 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x14 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x14 2. " UR ,User read access type" "Normal,User" bitfld.long 0x14 1. " UW ,User write access type" "Normal,User" bitfld.long 0x14 0. " UX ,User execute access type" "Normal,User" line.long 0x18 "L2MPPA6,Level 2 Memory Protection Page Attribute Register 6" bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x18 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x18 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x18 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x18 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x18 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x18 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x18 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x18 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x18 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x18 2. " UR ,User read access type" "Normal,User" bitfld.long 0x18 1. " UW ,User write access type" "Normal,User" bitfld.long 0x18 0. " UX ,User execute access type" "Normal,User" line.long 0x1C "L2MPPA7,Level 2 Memory Protection Page Attribute Register 7" bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x1C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x1C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x1C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x1C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x1C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x1C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x1C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x1C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x1C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x1C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x1C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x1C 0. " UX ,User execute access type" "Normal,User" line.long 0x20 "L2MPPA8,Level 2 Memory Protection Page Attribute Register 8" bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x20 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x20 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x20 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x20 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x20 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x20 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x20 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x20 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x20 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x20 2. " UR ,User read access type" "Normal,User" bitfld.long 0x20 1. " UW ,User write access type" "Normal,User" bitfld.long 0x20 0. " UX ,User execute access type" "Normal,User" line.long 0x24 "L2MPPA9,Level 2 Memory Protection Page Attribute Register 9" bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x24 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x24 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x24 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x24 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x24 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x24 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x24 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x24 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x24 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x24 2. " UR ,User read access type" "Normal,User" bitfld.long 0x24 1. " UW ,User write access type" "Normal,User" bitfld.long 0x24 0. " UX ,User execute access type" "Normal,User" line.long 0x28 "L2MPPA10,Level 2 Memory Protection Page Attribute Register 10" bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x28 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x28 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x28 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x28 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x28 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x28 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x28 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x28 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x28 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x28 2. " UR ,User read access type" "Normal,User" bitfld.long 0x28 1. " UW ,User write access type" "Normal,User" bitfld.long 0x28 0. " UX ,User execute access type" "Normal,User" line.long 0x2C "L2MPPA11,Level 2 Memory Protection Page Attribute Register 11" bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x2C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x2C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x2C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x2C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x2C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x2C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x2C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x2C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x2C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x2C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x2C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x2C 0. " UX ,User execute access type" "Normal,User" line.long 0x30 "L2MPPA12,Level 2 Memory Protection Page Attribute Register 12" bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x30 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x30 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x30 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x30 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x30 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x30 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x30 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x30 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x30 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x30 2. " UR ,User read access type" "Normal,User" bitfld.long 0x30 1. " UW ,User write access type" "Normal,User" bitfld.long 0x30 0. " UX ,User execute access type" "Normal,User" line.long 0x34 "L2MPPA13,Level 2 Memory Protection Page Attribute Register 13" bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x34 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x34 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x34 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x34 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x34 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x34 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x34 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x34 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x34 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x34 2. " UR ,User read access type" "Normal,User" bitfld.long 0x34 1. " UW ,User write access type" "Normal,User" bitfld.long 0x34 0. " UX ,User execute access type" "Normal,User" line.long 0x38 "L2MPPA14,Level 2 Memory Protection Page Attribute Register 14" bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x38 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x38 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x38 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x38 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x38 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x38 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x38 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x38 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x38 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x38 2. " UR ,User read access type" "Normal,User" bitfld.long 0x38 1. " UW ,User write access type" "Normal,User" bitfld.long 0x38 0. " UX ,User execute access type" "Normal,User" line.long 0x3C "L2MPPA15,Level 2 Memory Protection Page Attribute Register 15" bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x3C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x3C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x3C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x3C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x3C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x3C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x3C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x3C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x3C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x3C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x3C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x3C 0. " UX ,User execute access type" "Normal,User" line.long 0x40 "L2MPPA16,Level 2 Memory Protection Page Attribute Register 16" bitfld.long 0x40 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x40 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x40 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x40 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x40 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x40 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x40 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x40 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x40 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x40 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x40 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x40 2. " UR ,User read access type" "Normal,User" bitfld.long 0x40 1. " UW ,User write access type" "Normal,User" bitfld.long 0x40 0. " UX ,User execute access type" "Normal,User" line.long 0x44 "L2MPPA17,Level 2 Memory Protection Page Attribute Register 17" bitfld.long 0x44 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x44 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x44 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x44 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x44 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x44 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x44 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x44 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x44 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x44 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x44 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x44 2. " UR ,User read access type" "Normal,User" bitfld.long 0x44 1. " UW ,User write access type" "Normal,User" bitfld.long 0x44 0. " UX ,User execute access type" "Normal,User" line.long 0x48 "L2MPPA18,Level 2 Memory Protection Page Attribute Register 18" bitfld.long 0x48 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x48 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x48 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x48 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x48 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x48 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x48 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x48 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x48 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x48 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x48 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x48 2. " UR ,User read access type" "Normal,User" bitfld.long 0x48 1. " UW ,User write access type" "Normal,User" bitfld.long 0x48 0. " UX ,User execute access type" "Normal,User" line.long 0x4C "L2MPPA19,Level 2 Memory Protection Page Attribute Register 19" bitfld.long 0x4C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x4C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x4C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x4C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x4C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x4C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x4C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x4C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x4C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x4C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x4C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x4C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x4C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x4C 0. " UX ,User execute access type" "Normal,User" line.long 0x50 "L2MPPA20,Level 2 Memory Protection Page Attribute Register 20" bitfld.long 0x50 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x50 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x50 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x50 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x50 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x50 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x50 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x50 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x50 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x50 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x50 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x50 2. " UR ,User read access type" "Normal,User" bitfld.long 0x50 1. " UW ,User write access type" "Normal,User" bitfld.long 0x50 0. " UX ,User execute access type" "Normal,User" line.long 0x54 "L2MPPA21,Level 2 Memory Protection Page Attribute Register 21" bitfld.long 0x54 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x54 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x54 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x54 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x54 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x54 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x54 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x54 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x54 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x54 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x54 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x54 2. " UR ,User read access type" "Normal,User" bitfld.long 0x54 1. " UW ,User write access type" "Normal,User" bitfld.long 0x54 0. " UX ,User execute access type" "Normal,User" line.long 0x58 "L2MPPA22,Level 2 Memory Protection Page Attribute Register 22" bitfld.long 0x58 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x58 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x58 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x58 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x58 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x58 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x58 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x58 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x58 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x58 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x58 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x58 2. " UR ,User read access type" "Normal,User" bitfld.long 0x58 1. " UW ,User write access type" "Normal,User" bitfld.long 0x58 0. " UX ,User execute access type" "Normal,User" line.long 0x5C "L2MPPA23,Level 2 Memory Protection Page Attribute Register 23" bitfld.long 0x5C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x5C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x5C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x5C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x5C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x5C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x5C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x5C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x5C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x5C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x5C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x5C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x5C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x5C 0. " UX ,User execute access type" "Normal,User" line.long 0x60 "L2MPPA24,Level 2 Memory Protection Page Attribute Register 24" bitfld.long 0x60 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x60 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x60 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x60 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x60 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x60 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x60 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x60 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x60 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x60 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x60 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x60 2. " UR ,User read access type" "Normal,User" bitfld.long 0x60 1. " UW ,User write access type" "Normal,User" bitfld.long 0x60 0. " UX ,User execute access type" "Normal,User" line.long 0x64 "L2MPPA25,Level 2 Memory Protection Page Attribute Register 25" bitfld.long 0x64 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x64 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x64 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x64 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x64 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x64 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x64 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x64 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x64 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x64 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x64 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x64 2. " UR ,User read access type" "Normal,User" bitfld.long 0x64 1. " UW ,User write access type" "Normal,User" bitfld.long 0x64 0. " UX ,User execute access type" "Normal,User" line.long 0x68 "L2MPPA26,Level 2 Memory Protection Page Attribute Register 26" bitfld.long 0x68 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x68 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x68 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x68 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x68 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x68 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x68 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x68 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x68 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x68 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x68 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x68 2. " UR ,User read access type" "Normal,User" bitfld.long 0x68 1. " UW ,User write access type" "Normal,User" bitfld.long 0x68 0. " UX ,User execute access type" "Normal,User" line.long 0x6C "L2MPPA27,Level 2 Memory Protection Page Attribute Register 27" bitfld.long 0x6C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x6C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x6C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x6C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x6C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x6C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x6C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x6C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x6C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x6C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x6C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x6C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x6C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x6C 0. " UX ,User execute access type" "Normal,User" line.long 0x70 "L2MPPA28,Level 2 Memory Protection Page Attribute Register 28" bitfld.long 0x70 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x70 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x70 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x70 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x70 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x70 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x70 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x70 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x70 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x70 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x70 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x70 2. " UR ,User read access type" "Normal,User" bitfld.long 0x70 1. " UW ,User write access type" "Normal,User" bitfld.long 0x70 0. " UX ,User execute access type" "Normal,User" line.long 0x74 "L2MPPA29,Level 2 Memory Protection Page Attribute Register 29" bitfld.long 0x74 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x74 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x74 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x74 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x74 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x74 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x74 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x74 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x74 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x74 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x74 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x74 2. " UR ,User read access type" "Normal,User" bitfld.long 0x74 1. " UW ,User write access type" "Normal,User" bitfld.long 0x74 0. " UX ,User execute access type" "Normal,User" line.long 0x78 "L2MPPA30,Level 2 Memory Protection Page Attribute Register 30" bitfld.long 0x78 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x78 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x78 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x78 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x78 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x78 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x78 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x78 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x78 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x78 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x78 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x78 2. " UR ,User read access type" "Normal,User" bitfld.long 0x78 1. " UW ,User write access type" "Normal,User" bitfld.long 0x78 0. " UX ,User execute access type" "Normal,User" line.long 0x7C "L2MPPA31,Level 2 Memory Protection Page Attribute Register 31" bitfld.long 0x7C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x7C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x7C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x7C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x7C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x7C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x7C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x7C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x7C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x7C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x7C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x7C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x7C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x7C 0. " UX ,User execute access type" "Normal,User" tree.end width 9. rgroup.long 0x000++0x7 "Memory Protection Fault Registers" line.long 0x00 "L2MPFAR,Level 2 Memory Protection Fault Address Register" hexmask.long 0x00 0.--31. 1. " FA ,Fault Address" line.long 0x04 "L2MPFSR,Level 2 Memory Protection Fault Set Register" hexmask.long.byte 0x04 9.--15. 1. " FID ,Bit 6:0 of ID of faulting requestor" bitfld.long 0x04 8. " LOCAL ,Local access" "Normal,Supervisor" bitfld.long 0x04 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x04 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x04 2. " UR ,User read access type" "Normal,User" bitfld.long 0x04 1. " UW ,User write access type" "Normal,User" group.long 0x008++0x3 line.long 0x00 "L2MPFCR,Level 2 Memory Protection Fault Clear Register" eventfld.long 0x00 0. " MPFCLR ,Clear L1DMPFAR and L1DMPFCR" "No effect,Clear" width 12. wgroup.long 0x100++0xf "Memory Protection Lock Registers" line.long 0x00 "L2MPLK0,Level 2 Memory Protection Lock 0" hexmask.long 0x00 0.--31. 1. " LB ,Lock Bits 31:0" line.long 0x04 "L2MPLK1,Level 2 Memory Protection Lock 1" hexmask.long 0x04 0.--31. 1. " LB ,Lock Bits 63:32" line.long 0x08 "L2MPLK2,Level 2 Memory Protection Lock 2" hexmask.long 0x08 0.--31. 1. " LB ,Lock Bits 95:64" line.long 0x0c "L2MPLK3,Level 2 Memory Protection Lock 3" hexmask.long 0x0c 0.--31. 1. " LB ,Lock Bits 127:96" wgroup.long 0x110++0x3 line.long 0x00 "L2MPLKCMD,Level 2 Memory Protection Lock Command Register" bitfld.long 0x00 2. " KEYR ,Reset status" "No effect,Reset" bitfld.long 0x00 1. " LOCK ,Interface to complete a lock sequence" "No effect,Locked" bitfld.long 0x00 0. " UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked" rgroup.long 0x114++0x3 line.long 0x00 "L2MPLKSTAT,Level 2 Memory Protection Lock Status Register" bitfld.long 0x00 0. " LK ,Indicates the lock's current status" "Disengaged,Engaged" AUTOINDENT.ON right tree base d:0x01846000 rgroup.long 0x4++0x3 "Error Detection Registers" line.long 0x0 "L2EDSTAT,L2 Error Detection Status Register" decmask.long.byte 0x0 16.--23. "BITPOS,Single Bit error position" bitfld.long 0x0 8.--9. "NERR" "Single Bit error,Double Bit error,,Error in parity value" newline bitfld.long 0x0 7. "VERR,Error occurred on L2 victims" "False,True" bitfld.long 0x0 6. "DMAERR,DMA/IDMA access to L1P memory resulted in parity check error" "False,True" bitfld.long 0x0 5. "PERR,Program fetch resulted in parity check error" "False,True" newline bitfld.long 0x0 3. "SUSP,Error detection logic is suspended" "False,True" bitfld.long 0x0 2. "DIS,Error detection logic is disabled" "False,True" bitfld.long 0x0 0. "EN,Error detection logic is enabled" "False,True" group.long 0x8++0x3 line.long 0x0 "L2EDCMD, L2 Error Detection Command Register" bitfld.long 0x0 7. "VCLR,Clears the victim parity error status" "No effect,Clear" bitfld.long 0x0 6. "DMACLR,Clears the DMA/IDMA read parity error status" "No effect,Clear" bitfld.long 0x0 5. "PCLR,Clears the program fetch parity error status" "No effect,Clear" bitfld.long 0x0 4. "DCLR,Clears the data fetch parity error status" "No effect,Clear" newline bitfld.long 0x0 3. "SUSP,Suspends the error detection logic" "No effect,Suspend" bitfld.long 0x0 2. "DIS,Disables the error detection logic" "No effect,Disable" bitfld.long 0x0 0. "EN,Enables the error detection logic" "No effect,Enable" rgroup.long 0xC++0x3 line.long 0x0 "L2EDADDR,L2 Error Detection Address Register" hexmask.long.long 0x0 5.--31. 32. "ADDR,Address of parity error (5 LSBs assumed to be 00000b)" bitfld.long 0x0 8.--9. "L2WAY,Error detected in Way" "Way 0,Way 1,Way 2,Way 3" bitfld.long 0x0 0. "RAM,Location where error was detected" "L2,RAM" rgroup.long 0x18++0x3 line.long 0x0 "L2EDCPEC,L2 Error Detection Correctable Parity Error Counter Register" hexmask.long.byte 0x0 0.--7. "CNT,Counter value" rgroup.long 0x1C++0x3 line.long 0x0 "L2EDNPEC,L2 Error Detection Non-correctable Parity Error Counter Register" hexmask.long.byte 0x0 0.--7. "CNT,Counter value" group.long 0x30++0x3 line.long 0x0 "L2EDCEN,L2 Error Detection and Correction Enable Register" bitfld.long 0x0 0. "SDMAEN,EDC on SDMA read from L2 RAM" "Disabled,Enabled" bitfld.long 0x0 0. "PL2SEN,EDC on L1P memory controller read from L2 RAM" "Disabled,Enabled" bitfld.long 0x0 0. "DL2SEN,EDC on L1D memory controller read from L2 RAM" "Disabled,Enabled" bitfld.long 0x0 0. "PL2CEN,EDC on L1P memory controller reads from an external address (Hits L2 cache)" "Disabled,Enabled" bitfld.long 0x0 0. "DL2CEN,EDC on L1D memory controller reads from an external address (Hits L2 cache)" "Disabled,Enabled" AUTOINDENT.OFF width 0xb tree.end tree.end tree "IDMA (Internal Direct Memory Access Controller)" width 14. base d:0x01820000 rgroup.long 0x00++0x3 "Channel 0" line.long 0x00 "IDMA0_STAT,IDMA Channel 0 Status Register" bitfld.long 0x00 1. " PEND ,Pending transfer" "Not pending,Pending" bitfld.long 0x00 0. " ACTV ,Active transfer" "Not active,Active" group.long 0x04++0xf line.long 0x00 "IDMA0_MASK,IDMA Channel 0 Mask Register" bitfld.long 0x00 31. " M31 ,Mask bit 31" "Not masked,Masked" bitfld.long 0x00 30. " M30 ,Mask bit 30" "Not masked,Masked" bitfld.long 0x00 29. " M29 ,Mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x00 28. " M28 ,Mask bit 28" "Not masked,Masked" bitfld.long 0x00 27. " M27 ,Mask bit 27" "Not masked,Masked" bitfld.long 0x00 26. " M26 ,Mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x00 25. " M25 ,Mask bit 25" "Not masked,Masked" bitfld.long 0x00 24. " M24 ,Mask bit 24" "Not masked,Masked" bitfld.long 0x00 23. " M23 ,Mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x00 22. " M22 ,Mask bit 22" "Not masked,Masked" bitfld.long 0x00 21. " M21 ,Mask bit 21" "Not masked,Masked" bitfld.long 0x00 20. " M20 ,Mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " M19 ,Mask bit 19" "Not masked,Masked" bitfld.long 0x00 18. " M18 ,Mask bit 18" "Not masked,Masked" bitfld.long 0x00 17. " M17 ,Mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x00 16. " M16 ,Mask bit 16" "Not masked,Masked" bitfld.long 0x00 15. " M15 ,Mask bit 15" "Not masked,Masked" bitfld.long 0x00 14. " M14 ,Mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " M13 ,Mask bit 13" "Not masked,Masked" bitfld.long 0x00 12. " M12 ,Mask bit 12" "Not masked,Masked" bitfld.long 0x00 11. " M11 ,Mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x00 10. " M10 ,Mask bit 10" "Not masked,Masked" bitfld.long 0x00 9. " M9 ,Mask bit 9" "Not masked,Masked" bitfld.long 0x00 8. " M8 ,Mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " M7 ,Mask bit 7" "Not masked,Masked" bitfld.long 0x00 6. " M6 ,Mask bit 6" "Not masked,Masked" bitfld.long 0x00 5. " M5 ,Mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x00 4. " M4 ,Mask bit 4" "Not masked,Masked" bitfld.long 0x00 3. " M3 ,Mask bit 3" "Not masked,Masked" bitfld.long 0x00 2. " M2 ,Mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " M1 ,Mask bit 1" "Not masked,Masked" bitfld.long 0x00 0. " M0 ,Mask bit 0" "Not masked,Masked" line.long 0x04 "IDMA0_SOURCE,IDMA Channel 0 Source Address Register" hexmask.long 0x04 5.--31. 0x20 " SOURCEADDR ,Source address" line.long 0x08 "IDMA0_DEST,IDMA Channel 0 Destination Address Register" hexmask.long 0x08 5.--31. 0x20 " DESTADDR ,Destination address" line.long 0x0c "IDMA0_COUNT,IDMA Channel 0 Count Register" bitfld.long 0x0c 28. " INT ,CPU interrupt enable" "Disabled,Enabled" bitfld.long 0x0c 0.--3. " COUNT ,4-bit block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.long 0x100++0x3 "Channel 1" line.long 0x00 "IDMA1_STAT,IDMA Channel 1 Status Register" bitfld.long 0x00 1. " PEND ,Pending transfer" "Not pending,Pending" bitfld.long 0x00 0. " ACTV ,Active transfer" "Not active,Active" group.long 0x108++0xb line.long 0x00 "IDMA1_SOURCE,IDMA Channel 1 Source Address Register" hexmask.long 0x00 0.--31. 1. " SOURCEADDR ,Source address" line.long 0x04 "IDMA1_DEST,IDMA Channel 1 Destination Address Register" hexmask.long 0x04 2.--31. 0x4 " DESTADDR ,Destination address" line.long 0x08 "IDMA1_COUNT,IDMA Channel 1 Count Register" bitfld.long 0x08 29.--31. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x08 28. " INT ,CPU interrupt enable" "Disabled,Enabled" bitfld.long 0x08 16. " FILL ,Block fill" "0,1" textline " " hexmask.long.word 0x08 0.--15. 1. " COUNT ,Byte count" width 0xb tree.end tree "XMC (Extended Memory Controller)" width 14. AUTOINDENT.ON right tree base d:0x08000000 group.long 0x00++0x7F "XMC MPAX Segment Registers" line.long 0x0 "XMPAXL0,MPAX segment 0 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x0 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x0 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x0 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x0 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x0 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x0 0. "UX,User mode may execute from segment" "False,True" line.long 0x0+0x4 "XMPAXH0,MPAX segment 0 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x0 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x8 "XMPAXL1,MPAX segment 1 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x8 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x8 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x8 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x8 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x8 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x8 0. "UX,User mode may execute from segment" "False,True" line.long 0x8+0x4 "XMPAXH1,MPAX segment 1 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x8 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x10 "XMPAXL2,MPAX segment 2 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x10 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x10 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x10 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x10 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x10 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x10 0. "UX,User mode may execute from segment" "False,True" line.long 0x10+0x4 "XMPAXH2,MPAX segment 2 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x10 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x18 "XMPAXL3,MPAX segment 3 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x18 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x18 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x18 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x18 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x18 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x18 0. "UX,User mode may execute from segment" "False,True" line.long 0x18+0x4 "XMPAXH3,MPAX segment 3 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x18 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x20 "XMPAXL4,MPAX segment 4 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x20 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x20 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x20 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x20 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x20 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x20 0. "UX,User mode may execute from segment" "False,True" line.long 0x20+0x4 "XMPAXH4,MPAX segment 4 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x20 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x28 "XMPAXL5,MPAX segment 5 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x28 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x28 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x28 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x28 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x28 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x28 0. "UX,User mode may execute from segment" "False,True" line.long 0x28+0x4 "XMPAXH5,MPAX segment 5 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x28 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x30 "XMPAXL6,MPAX segment 6 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x30 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x30 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x30 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x30 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x30 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x30 0. "UX,User mode may execute from segment" "False,True" line.long 0x30+0x4 "XMPAXH6,MPAX segment 6 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x30 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x38 "XMPAXL7,MPAX segment 7 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x38 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x38 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x38 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x38 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x38 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x38 0. "UX,User mode may execute from segment" "False,True" line.long 0x38+0x4 "XMPAXH7,MPAX segment 7 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x38 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x40 "XMPAXL8,MPAX segment 8 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x40 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x40 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x40 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x40 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x40 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x40 0. "UX,User mode may execute from segment" "False,True" line.long 0x40+0x4 "XMPAXH8,MPAX segment 8 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x40 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x48 "XMPAXL9,MPAX segment 9 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x48 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x48 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x48 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x48 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x48 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x48 0. "UX,User mode may execute from segment" "False,True" line.long 0x48+0x4 "XMPAXH9,MPAX segment 9 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x48 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x50 "XMPAXL10,MPAX segment 10 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x50 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x50 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x50 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x50 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x50 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x50 0. "UX,User mode may execute from segment" "False,True" line.long 0x50+0x4 "XMPAXH10,MPAX segment 10 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x50 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x58 "XMPAXL11,MPAX segment 11 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x58 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x58 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x58 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x58 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x58 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x58 0. "UX,User mode may execute from segment" "False,True" line.long 0x58+0x4 "XMPAXH11,MPAX segment 11 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x58 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x60 "XMPAXL12,MPAX segment 12 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x60 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x60 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x60 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x60 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x60 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x60 0. "UX,User mode may execute from segment" "False,True" line.long 0x60+0x4 "XMPAXH12,MPAX segment 12 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x60 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x68 "XMPAXL13,MPAX segment 13 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x68 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x68 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x68 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x68 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x68 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x68 0. "UX,User mode may execute from segment" "False,True" line.long 0x68+0x4 "XMPAXH13,MPAX segment 13 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x68 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x70 "XMPAXL14,MPAX segment 14 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x70 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x70 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x70 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x70 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x70 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x70 0. "UX,User mode may execute from segment" "False,True" line.long 0x70+0x4 "XMPAXH14,MPAX segment 14 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x70 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x78 "XMPAXL15,MPAX segment 15 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x78 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x78 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x78 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x78 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x78 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x78 0. "UX,User mode may execute from segment" "False,True" line.long 0x78+0x4 "XMPAXH15,MPAX segment 15 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x78 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" textline "" rgroup.long 0x200++0x3 "Memory Protection Fault Reporting Registers" line.long 0. "XMPFAR,Memory Protection Fault Address Register" hexmask.long 0x0 0.--31. "Fault Address,Fault Address" rgroup.long 0x204++0x3 line.long 0. "XMPFSR,Memory Protection Fault Status Register" bitfld.long 0. 8. "LOCAL,Access was a LOCAL access" "False,True" bitfld.long 0. 5. "SR,When set, indicates a supervisor read request" "False,True" bitfld.long 0. 4. "SW,When set, indicates a supervisor write request" "False,True" bitfld.long 0. 3. "SX,When set, indicates a supervisor program fetch request" "False,True" bitfld.long 0. 2. "UR,When set, indicates a user read request" "False,True" bitfld.long 0. 1. "UW,When set, indicates a user write request" "False,True" bitfld.long 0. 0. "UX,When set, indicates a user program fetch request" "False,True" group.long 0x208++0x3 line.long 0. "XMPFCR,Memory Protection Fault Clear Register" bitfld.long 0. 0. "MPFCLR,Clear fault" "No effect,Clear" group.long 0x280++0x3 "Prefetch Priority Register" line.long 0. "MDMAARBX,MDMA Arbitration Priority Register" bitfld.long 0. 16.--18. "PRI,Priority" "0 (highest),1,2,3,4,5,6,7 (lowest)" rgroup.long 0x300++0x3 "Prefetch Buffer Registers" line.long 0. "XPFCMD,Prefetch Command Register" bitfld.long 0. 4. "ACRST,Analysis Counter Reset" "No effect,Reset" hexmask.long.byte 0. 2.--3. "ACEN,Analysis Counter Enable" bitfld.long 0. 1. "ACENL,Analysis Counter ENable (ACEN) Load" "False,True" bitfld.long 0. 0. "INV,Invalidate prefetch buffer contents" "No effect,Invalidate" rgroup.long 0x304++0x3 "Prefetch Buffer Performance Analysis Registers" line.long 0. "XPFACS,Prefetch Analysis Counter Status" rgroup.long 0x310++0xF line.long 0x0 "XPFAC0,Prefetch Analysis Counter 0" line.long 0x4 "XPFAC1,Prefetch Analysis Counter 1" line.long 0x8 "XPFAC2,Prefetch Analysis Counter 2" line.long 0xC "XPFAC3,Prefetch Analysis Counter 3" rgroup.long 0x400++0x1F line.long 0x0 "XPFADDR0,Prefetch Address for Slot 0" line.long 0x4 "XPFADDR1,Prefetch Address for Slot 1" line.long 0x8 "XPFADDR2,Prefetch Address for Slot 2" line.long 0xC "XPFADDR3,Prefetch Address for Slot 3" line.long 0x10 "XPFADDR4,Prefetch Address for Slot 4" line.long 0x14 "XPFADDR5,Prefetch Address for Slot 5" line.long 0x18 "XPFADDR6,Prefetch Address for Slot 6" line.long 0x1C "XPFADDR7,Prefetch Address for Slot 7" AUTOINDENT.OFF width 0xb tree.end tree "Bandwith Management" width 13. base d:0x01841000 group.long 0x40++0xf "L1D" line.long 0x00 "CPUARBD,L1D CPU Arbitration Control Register" bitfld.long 0x00 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest" bitfld.long 0x00 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x04 "IDMAARBD,L1D IDMA Arbitration Control Register" bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x08 "SDMAARBD,L1D Slave DMA Arbitration Control Register" bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x0c "UCARBD,L1D User Coherence Arbitration Control Register" bitfld.long 0x0c 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." width 13. group.long 0x00++0xf "L2" line.long 0x00 "CPUARBU,L2D CPU Arbitration Control Register" bitfld.long 0x00 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest" bitfld.long 0x00 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x04 "IDMAARBU,L1D IDMA Arbitration Control Register" bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x08 "SDMAARBU,L1D Slave DMA Arbitration Control Register" bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x0c "UCARBU,L1D User Coherence Arbitration Control Register" bitfld.long 0x0c 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." width 13. base d:0x01820000 group.long 0x200++0xf "EMC" line.long 0x00 "CPUARBE,EMC CPU Arbitration Control Register" bitfld.long 0x00 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest" bitfld.long 0x00 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x04 "IDMAARBE,EMC IDMA Arbitration Control Register" bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x08 "SDMAARBE,EMC Slave DMA Arbitration Control Register" bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x0c "MDMAARBE,EMC Master DMA Arbitration Control Register" bitfld.long 0x0c 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest" width 0xb tree.end tree "Interrupt Controller" width 11. base d:0x01800000 group.long 0x00++0xf line.long 0x00 "EVTFLAG0,Event Flag Register 0" setclrfld.long 0x00 14. 0x20 14. 0x40 14. " EF14_set/clr ,State of event EVT14" "Not occurred,Occurred" setclrfld.long 0x00 13. 0x20 13. 0x40 13. " EF13_set/clr ,State of event EVT13" "Not occurred,Occurred" textline " " setclrfld.long 0x00 12. 0x20 12. 0x40 12. " EF12_set/clr ,State of event EVT12" "Not occurred,Occurred" setclrfld.long 0x00 11. 0x20 11. 0x40 11. " EF11_set/clr ,State of event EVT11" "Not occurred,Occurred" textline " " setclrfld.long 0x00 9. 0x20 9. 0x40 9. " EF9_set/clr ,State of event EVT9" "Not occurred,Occurred" setclrfld.long 0x00 8. 0x20 8. 0x40 8. " EF8_set/clr ,State of event EVT8" "Not occurred,Occurred" textline " " setclrfld.long 0x00 7. 0x20 7. 0x40 7. " EF7_set/clr ,State of event EVT7" "Not occurred,Occurred" setclrfld.long 0x00 6. 0x20 6. 0x40 6. " EF6_set/clr ,State of event EVT6" "Not occurred,Occurred" textline " " setclrfld.long 0x00 5. 0x20 5. 0x40 5. " EF5_set/clr ,State of event EVT5" "Not occurred,Occurred" setclrfld.long 0x00 4. 0x20 4. 0x40 4. " EF4_set/clr ,State of event EVT4" "Not occurred,Occurred" textline " " setclrfld.long 0x00 3. 0x20 3. 0x40 3. " EF3_set/clr ,State of event EVT3" "Not occurred,Occurred" setclrfld.long 0x00 2. 0x20 2. 0x40 2. " EF2_set/clr ,State of event EVT2" "Not occurred,Occurred" textline " " setclrfld.long 0x00 1. 0x20 1. 0x40 1. " EF1_set/clr ,State of event EVT1" "Not occurred,Occurred" setclrfld.long 0x00 0. 0x20 0. 0x40 0. " EF0_set/clr ,State of event EVT0" "Not occurred,Occurred" line.long 0x04 "EVTFLAG1,Event Flag Register 1" setclrfld.long 0x04 28. 0x24 28. 0x44 28. " EF60_set/clr ,State of event EVT60" "Not occurred,Occurred" setclrfld.long 0x04 27. 0x24 27. 0x44 27. " EF59_set/clr ,State of event EVT59" "Not occurred,Occurred" textline " " setclrfld.long 0x04 24. 0x24 24. 0x44 24. " EF56_set/clr ,State of event EVT56" "Not occurred,Occurred" setclrfld.long 0x04 23. 0x24 23. 0x44 23. " EF55_set/clr ,State of event EVT55" "Not occurred,Occurred" textline " " setclrfld.long 0x04 22. 0x24 22. 0x44 22. " EF54_set/clr ,State of event EVT54" "Not occurred,Occurred" setclrfld.long 0x04 21. 0x24 21. 0x44 21. " EF53_set/clr ,State of event EVT53" "Not occurred,Occurred" textline " " setclrfld.long 0x04 19. 0x24 19. 0x44 19. " EF51_set/clr ,State of event EVT51" "Not occurred,Occurred" setclrfld.long 0x04 18. 0x24 18. 0x44 18. " EF50_set/clr ,State of event EVT50" "Not occurred,Occurred" textline " " setclrfld.long 0x04 17. 0x24 17. 0x44 17. " EF49_set/clr ,State of event EVT49" "Not occurred,Occurred" setclrfld.long 0x04 16. 0x24 16. 0x44 16. " EF48_set/clr ,State of event EVT48" "Not occurred,Occurred" textline " " setclrfld.long 0x04 15. 0x24 15. 0x44 15. " EF47_set/clr ,State of event EVT47" "Not occurred,Occurred" setclrfld.long 0x04 11. 0x24 11. 0x44 11. " EF43_set/clr ,State of event EVT43" "Not occurred,Occurred" textline " " setclrfld.long 0x04 9. 0x24 9. 0x44 9. " EF41_set/clr ,State of event EVT41" "Not occurred,Occurred" setclrfld.long 0x04 8. 0x24 8. 0x44 8. " EF40_set/clr ,State of event EVT40" "Not occurred,Occurred" textline " " setclrfld.long 0x04 7. 0x24 7. 0x44 7. " EF39_set/clr ,State of event EVT39" "Not occurred,Occurred" setclrfld.long 0x04 6. 0x24 6. 0x44 6. " EF38_set/clr ,State of event EVT38" "Not occurred,Occurred" textline " " setclrfld.long 0x04 5. 0x24 5. 0x44 5. " EF37_set/clr ,State of event EVT37" "Not occurred,Occurred" setclrfld.long 0x04 4. 0x24 4. 0x44 4. " EF36_set/clr ,State of event EVT36" "Not occurred,Occurred" textline " " setclrfld.long 0x04 3. 0x24 3. 0x44 3. " EF35_set/clr ,State of event EVT35" "Not occurred,Occurred" setclrfld.long 0x04 2. 0x24 2. 0x44 2. " EF34_set/clr ,State of event EVT34" "Not occurred,Occurred" line.long 0x08 "EVTFLAG2,Event Flag Register 2" setclrfld.long 0x08 21. 0x28 21. 0x48 21. " EF85_set/clr ,State of event EVT85" "Not occurred,Occurred" setclrfld.long 0x08 20. 0x28 20. 0x48 20. " EF84_set/clr ,State of event EVT84" "Not occurred,Occurred" textline " " setclrfld.long 0x08 19. 0x28 19. 0x48 19. " EF83_set/clr ,State of event EVT83" "Not occurred,Occurred" setclrfld.long 0x08 18. 0x28 18. 0x48 18. " EF82_set/clr ,State of event EVT82" "Not occurred,Occurred" textline " " setclrfld.long 0x08 17. 0x28 17. 0x48 17. " EF81_set/clr ,State of event EVT81" "Not occurred,Occurred" setclrfld.long 0x08 16. 0x28 16. 0x48 16. " EF80_set/clr ,State of event EVT80" "Not occurred,Occurred" textline " " setclrfld.long 0x08 14. 0x28 14. 0x48 14. " EF78_set/clr ,State of event EVT78" "Not occurred,Occurred" setclrfld.long 0x08 13. 0x28 13. 0x48 13. " EF77_set/clr ,State of event EVT77" "Not occurred,Occurred" textline " " setclrfld.long 0x08 12. 0x28 12. 0x48 12. " EF76_set/clr ,State of event EVT76" "Not occurred,Occurred" setclrfld.long 0x08 11. 0x28 11. 0x48 11. " EF75_set/clr ,State of event EVT75" "Not occurred,Occurred" textline " " setclrfld.long 0x08 10. 0x28 10. 0x48 10. " EF74_set/clr ,State of event EVT74" "Not occurred,Occurred" setclrfld.long 0x08 9. 0x28 9. 0x48 9. " EF73_set/clr ,State of event EVT73" "Not occurred,Occurred" textline " " setclrfld.long 0x08 8. 0x28 8. 0x48 8. " EF72_set/clr ,State of event EVT72" "Not occurred,Occurred" setclrfld.long 0x08 7. 0x28 7. 0x48 7. " EF71_set/clr ,State of event EVT71" "Not occurred,Occurred" textline " " setclrfld.long 0x08 6. 0x28 6. 0x48 6. " EF70_set/clr ,State of event EVT70" "Not occurred,Occurred" setclrfld.long 0x08 5. 0x28 5. 0x48 5. " EF69_set/clr ,State of event EVT69" "Not occurred,Occurred" textline " " setclrfld.long 0x08 4. 0x28 4. 0x48 4. " EF68_set/clr ,State of event EVT68" "Not occurred,Occurred" setclrfld.long 0x08 3. 0x28 3. 0x48 3. " EF67_set/clr ,State of event EVT67" "Not occurred,Occurred" textline " " setclrfld.long 0x08 2. 0x28 2. 0x48 2. " EF66_set/clr ,State of event EVT66" "Not occurred,Occurred" setclrfld.long 0x08 1. 0x28 1. 0x48 1. " EF65_set/clr ,State of event EVT65" "Not occurred,Occurred" textline " " setclrfld.long 0x08 0. 0x28 0. 0x48 0. " EF64_set/clr ,State of event EVT64" "Not occurred,Occurred" line.long 0x0c "EVTFLAG3,Event Flag Register 3" setclrfld.long 0x0c 31. 0x2c 31. 0x4c 31. " EF127_set/clr ,State of event EVT127" "Not occurred,Occurred" setclrfld.long 0x0c 30. 0x2c 30. 0x4c 30. " EF126_set/clr ,State of event EVT126" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 29. 0x2c 29. 0x4c 29. " EF125_set/clr ,State of event EVT125" "Not occurred,Occurred" setclrfld.long 0x0c 28. 0x2c 28. 0x4c 28. " EF124_set/clr ,State of event EVT124" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 27. 0x2c 27. 0x4c 27. " EF123_set/clr ,State of event EVT123" "Not occurred,Occurred" setclrfld.long 0x0c 26. 0x2c 26. 0x4c 26. " EF122_set/clr ,State of event EVT122" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 25. 0x2c 25. 0x4c 25. " EF121_set/clr ,State of event EVT121" "Not occurred,Occurred" setclrfld.long 0x0c 24. 0x2c 24. 0x4c 24. " EF120_set/clr ,State of event EVT120" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 23. 0x2c 23. 0x4c 23. " EF119_set/clr ,State of event EVT119" "Not occurred,Occurred" setclrfld.long 0x0c 22. 0x2c 22. 0x4c 22. " EF118_set/clr ,State of event EVT118" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 21. 0x2c 21. 0x4c 21. " EF117_set/clr ,State of event EVT117" "Not occurred,Occurred" setclrfld.long 0x0c 20. 0x2c 20. 0x4c 20. " EF116_set/clr ,State of event EVT116" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 17. 0x2c 17. 0x4c 17. " EF113_set/clr ,State of event EVT113" "Not occurred,Occurred" setclrfld.long 0x0c 1. 0x2c 1. 0x4c 1. " EF97_set/clr ,State of event EVT97" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 0. 0x2c 0. 0x4c 0. " EF96_set/clr ,State of event EVT96" "Not occurred,Occurred" width 11. group.long 0x80++0xf line.long 0x00 "EVTMASK0,Event Mask Register 0" bitfld.long 0x00 14. " EM14 ,Disables event EVT14 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 13. " EM13 ,Disables event EVT13 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 12. " EM12 ,Disables event EVT12 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x00 11. " EM11 ,Disables event EVT11 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 9. " EM9 ,Disables event EVT9 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 8. " EM8 ,Disables event EVT8 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x00 7. " EM7 ,Disables event EVT7 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 6. " EM6 ,Disables event EVT6 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 5. " EM5 ,Disables event EVT5 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x00 4. " EM4 ,Disables event EVT4 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 3. " EM3 ,Disables event EVT3 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 2. " EM2 ,Disables event EVT2 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x00 1. " EM1 ,Disables event EVT1 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 0. " EM0 ,Disables event EVT0 from being used as input to the event combiner" "Combined,Disabled" line.long 0x04 "EVTMASK1,Event Mask Register 1" bitfld.long 0x04 28. " EM60 ,Disables event EVT60 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 27. " EM59 ,Disables event EVT59 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 24. " EM56 ,Disables event EVT56 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 23. " EM55 ,Disables event EVT55 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 22. " EM54 ,Disables event EVT54 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 21. " EM53 ,Disables event EVT53 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 19. " EM51 ,Disables event EVT51 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 18. " EM50 ,Disables event EVT50 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 17. " EM49 ,Disables event EVT49 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 16. " EM48 ,Disables event EVT48 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 15. " EM47 ,Disables event EVT47 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 11. " EM43 ,Disables event EVT43 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 9. " EM41 ,Disables event EVT41 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 8. " EM40 ,Disables event EVT40 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 7. " EM39 ,Disables event EVT39 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 6. " EM38 ,Disables event EVT38 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 5. " EM37 ,Disables event EVT37 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 4. " EM36 ,Disables event EVT36 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 3. " EM35 ,Disables event EVT35 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 2. " EM34 ,Disables event EVT34 from being used as input to the event combiner" "Combined,Disabled" line.long 0x08 "EVTMASK2,Event Mask Register 2" bitfld.long 0x08 21. " EM85 ,Disables event EVT85 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 20. " EM84 ,Disables event EVT84 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 19. " EM83 ,Disables event EVT83 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 18. " EM82 ,Disables event EVT82 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 17. " EM81 ,Disables event EVT81 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 16. " EM80 ,Disables event EVT80 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 14. " EM78 ,Disables event EVT78 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 13. " EM77 ,Disables event EVT77 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 12. " EM76 ,Disables event EVT76 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 11. " EM75 ,Disables event EVT75 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 10. " EM74 ,Disables event EVT74 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 9. " EM73 ,Disables event EVT73 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 8. " EM72 ,Disables event EVT72 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 7. " EM71 ,Disables event EVT71 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 6. " EM70 ,Disables event EVT70 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 5. " EM69 ,Disables event EVT69 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 4. " EM68 ,Disables event EVT68 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 3. " EM67 ,Disables event EVT67 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 2. " EM66 ,Disables event EVT66 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 1. " EM65 ,Disables event EVT65 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 0. " EM64 ,Disables event EVT64 from being used as input to the event combiner" "Combined,Disabled" line.long 0x0c "EVTMASK3,Event Mask Register 3" bitfld.long 0x0c 31. " EM127 ,Disables event EVT127 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 30. " EM126 ,Disables event EVT126 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 29. " EM125 ,Disables event EVT125 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 28. " EM124 ,Disables event EVT124 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 27. " EM123 ,Disables event EVT123 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 26. " EM122 ,Disables event EVT122 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 25. " EM121 ,Disables event EVT121 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 24. " EM120 ,Disables event EVT120 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 23. " EM119 ,Disables event EVT119 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 22. " EM118 ,Disables event EVT118 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 21. " EM117 ,Disables event EVT117 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 20. " EM116 ,Disables event EVT116 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 17. " EM113 ,Disables event EVT113 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 1. " EM97 ,Disables event EVT97 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 0. " EM96 ,Disables event EVT96 from being used as input to the event combiner" "Combined,Disabled" group.long 0xc0++0xf line.long 0x00 "EXPMASK0,Exception Mask Register 0" bitfld.long 0x00 14. " XM14 ,Event EVT14 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 13. " XM13 ,Event EVT13 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 12. " XM12 ,Event EVT12 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x00 11. " XM11 ,Event EVT11 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 9. " XM9 ,Event EVT9 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 8. " XM8 ,Event EVT8 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x00 7. " XM7 ,Event EVT7 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 6. " XM6 ,Event EVT6 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 5. " XM5 ,Event EVT5 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x00 4. " XM4 ,Event EVT4 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 3. " XM3 ,Event EVT3 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 2. " XM2 ,Event EVT2 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x00 1. " XM1 ,Event EVT1 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 0. " XM0 ,Event EVT0 disabled from being used in the exception combiner" "Combined,Disabled" line.long 0x04 "EXPMASK1,Exception Mask Register 1" bitfld.long 0x04 28. " XM60 ,Event EVT60 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 27. " XM59 ,Event EVT59 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 24. " XM56 ,Event EVT56 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 23. " XM55 ,Event EVT55 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 22. " XM54 ,Event EVT54 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 21. " XM53 ,Event EVT53 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 19. " XM51 ,Event EVT51 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 18. " XM50 ,Event EVT50 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 17. " XM49 ,Event EVT49 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 16. " XM48 ,Event EVT48 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 15. " XM47 ,Event EVT47 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 11. " XM43 ,Event EVT43 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 9. " XM41 ,Event EVT41 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 8. " XM40 ,Event EVT40 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 7. " XM39 ,Event EVT39 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 6. " XM38 ,Event EVT38 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 5. " XM37 ,Event EVT37 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 4. " XM36 ,Event EVT36 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 3. " XM35 ,Event EVT35 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 2. " XM34 ,Event EVT34 disabled from being used in the exception combiner" "Combined,Disabled" line.long 0x08 "EXPMASK2,Exception Mask Register 2" bitfld.long 0x08 21. " XM85 ,Event EVT85 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 20. " XM84 ,Event EVT84 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 19. " XM83 ,Event EVT83 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 18. " XM82 ,Event EVT82 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 17. " XM81 ,Event EVT81 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 16. " XM80 ,Event EVT80 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 14. " XM78 ,Event EVT78 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 13. " XM77 ,Event EVT77 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 12. " XM76 ,Event EVT76 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 11. " XM75 ,Event EVT75 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 10. " XM74 ,Event EVT74 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 9. " XM73 ,Event EVT73 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 8. " XM72 ,Event EVT72 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 7. " XM71 ,Event EVT71 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 6. " XM70 ,Event EVT70 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 5. " XM69 ,Event EVT69 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 4. " XM68 ,Event EVT68 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 3. " XM67 ,Event EVT67 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 2. " XM66 ,Event EVT66 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 1. " XM65 ,Event EVT65 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 0. " XM64 ,Event EVT64 disabled from being used in the exception combiner" "Combined,Disabled" line.long 0x0c "EXPMASK3,Exception Mask Register 3" bitfld.long 0x0c 31. " XM127 ,Event EVT127 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 30. " XM126 ,Event EVT126 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 29. " XM125 ,Event EVT125 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 28. " XM124 ,Event EVT124 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 27. " XM123 ,Event EVT123 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 26. " XM122 ,Event EVT122 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 25. " XM121 ,Event EVT121 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 24. " XM120 ,Event EVT120 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 23. " XM119 ,Event EVT119 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 22. " XM118 ,Event EVT118 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 21. " XM117 ,Event EVT117 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 20. " XM116 ,Event EVT116 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 17. " XM113 ,Event EVT113 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 1. " XM97 ,Event EVT97 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 0. " XM96 ,Event EVT96 disabled from being used in the exception combiner" "Combined,Disabled" width 11. rgroup.long 0xa0++0xf line.long 0x00 "MEVTFLAG0,Masked Event Flag Register 0" hexmask.long 0x00 0.--31. 1. " MEF[31:0] ,Displays content of EF when EM=0" line.long 0x04 "MEVTFLAG1,Masked Event Flag Register 1" hexmask.long 0x04 0.--31. 1. " MEF[63:32] ,Displays content of EF when EM=0" line.long 0x08 "MEVTFLAG2,Masked Event Flag Register 2" hexmask.long 0x08 0.--31. 1. " MEF[95:64] ,Displays content of EF when EM=0" line.long 0x0c "MEVTFLAG3,Masked Event Flag Register 3" hexmask.long 0x0c 0.--31. 1. " MEF[127:96] ,Displays content of EF when EM=0" rgroup.long 0xe0++0xf line.long 0x00 "MEXPFLAG0,Masked Exception Flag Register 0" line.long 0x04 "MEXPFLAG1,Masked ExceptionFlag Register 1" line.long 0x08 "MEXPFLAG2,Masked Exception Flag Register 2" line.long 0x0c "MEXPFLAG3,Masked Exception Flag Register 3" width 11. group.long 0x104++0xb line.long 0x00 "INTMUX1,Interrupt Mux Register 1" hexmask.long.byte 0x00 24.--30. 1. " INTSEL7 ,Number of the event that maps to CPUINT7" hexmask.long.byte 0x00 16.--22. 1. " INTSEL6 ,Number of the event that maps to CPUINT6" hexmask.long.byte 0x00 8.--14. 1. " INTSEL5 ,Number of the event that maps to CPUINT5" hexmask.long.byte 0x00 0.--6. 1. " INTSEL4 ,Number of the event that maps to CPUINT4" line.long 0x04 "INTMUX2,Interrupt Mux Register 2" hexmask.long.byte 0x04 24.--30. 1. " INTSEL11 ,Number of the event that maps to CPUINT11" hexmask.long.byte 0x04 16.--22. 1. " INTSEL10 ,Number of the event that maps to CPUINT10" hexmask.long.byte 0x04 8.--14. 1. " INTSEL9 ,Number of the event that maps to CPUINT9" hexmask.long.byte 0x04 0.--6. 1. " INTSEL8 ,Number of the event that maps to CPUINT8" line.long 0x08 "INTMUX3,Interrupt Mux Register 3" hexmask.long.byte 0x08 24.--30. 1. " INTSEL15 ,Number of the event that maps to CPUINT15" hexmask.long.byte 0x08 16.--22. 1. " INTSEL14 ,Number of the event that maps to CPUINT14" hexmask.long.byte 0x08 8.--14. 1. " INTSEL13 ,Number of the event that maps to CPUINT13" hexmask.long.byte 0x08 0.--6. 1. " INTSEL12 ,Number of the event that maps to CPUINT12" rgroup.long 0x180++0x3 line.long 0x00 "INTXSTAT,Interrupt Exception Status Register" hexmask.long.byte 0x00 24.--31. 1. " SYSINT ,System Event number" hexmask.long.byte 0x00 16.--23. 1. " CPUINT ,CPU interrupt number" bitfld.long 0x00 0. " DROP ,Dropped event flag" "No event dropped,Event dropped" width 11. wgroup.long 0x184++0x3 line.long 0x00 "INTXCLR,Interrupt Exception Clear Register" bitfld.long 0x00 0. " CLEAR ,Clears the interrupt exception status" "No effect,Cleared" rgroup.long 0x188++0x3 line.long 0x00 "INTDMASK,Dropped Interrupt Mask Register" bitfld.long 0x00 15. " IDM15 ,Disables CPUINT15 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 14. " IDM14 ,Disables CPUINT14 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 13. " IDM13 ,Disables CPUINT13 from being detected by the drop detection hardware" "No effect,Ignored" textline " " bitfld.long 0x00 12. " IDM12 ,Disables CPUINT12 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 11. " IDM11 ,Disables CPUINT11 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 10. " IDM10 ,Disables CPUINT10 from being detected by the drop detection hardware" "No effect,Ignored" textline " " bitfld.long 0x00 9. " IDM9 ,Disables CPUINT9 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 8. " IDM8 ,Disables CPUINT8 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 7. " IDM7 ,Disables CPUINT7 from being detected by the drop detection hardware" "No effect,Ignored" textline " " bitfld.long 0x00 6. " IDM6 ,Disables CPUINT6 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 5. " IDM5 ,Disables CPUINT5 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 4. " IDM4 ,Disables CPUINT4 from being detected by the drop detection hardware" "No effect,Ignored" width 11. group.long 0x140++0x07 line.long 0x00 "AEGMUX0,Advanced Event Generator Mux Registers" hexmask.long.byte 0x00 24.--31. 1. " AEGSEL3 ,Advanced Event Generator Select" hexmask.long.byte 0x00 16.--23. 1. " AEGSEL2 ,Advanced Event Generator Select" hexmask.long.byte 0x00 8.--15. 1. " AEGSEL1 ,Advanced Event Generator Select" hexmask.long.byte 0x00 0.--7. 1. " AEGSEL0 ,Advanced Event Generator Select" line.long 0x04 "AEGMUX1,Advanced Event Generator Mux Registers" hexmask.long.byte 0x04 24.--31. 1. " AEGSEL7 ,Advanced Event Generator Select" hexmask.long.byte 0x04 16.--23. 1. " AEGSEL6 ,Advanced Event Generator Select" hexmask.long.byte 0x04 8.--15. 1. " AEGSEL5 ,Advanced Event Generator Select" hexmask.long.byte 0x04 0.--7. 1. " AEGSEL4 ,Advanced Event Generator Select" width 0xb tree.end tree "Power-Down Controller" width 8. base d:0x01810000 group.long 0x00++0x3 line.long 0x00 "PDCCMD,Power-Down Controller Command Register" bitfld.long 0x00 16. " MEGPD ,Power-down during IDLE" "Normal,Sleep mode" width 0xb tree.end tree.end AUTOINDENT.POP endif AUTOINDENT.ON center tree sif (cpuis("TDA3XIPU*")) tree "ADC" base ad:0x4A264000 rgroup.long 0x00++0x03 line.long 0x00 "ADC_REVISION,Revision identifier" group.long 0x10++0x03 line.long 0x00 "ADC_SYSCONFIG,System configuration register" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--3. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x20++0x13 line.long 0x00 "ADC_IRQ_EOI,Software end of interrupt" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_w,?" line.long 0x04 "ADC_IRQSTATUS_RAW,Per-event raw interrupt status vector. showing all active events (enabled and not enabled)" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 8. "OUT_OF_RANGE,Status raw for interrupt" "No event pending,Event pending" newline bitfld.long 0x04 7. "FIFO1_UNDERFLOW,Status raw for interrupt" "No event pending,Event pending" newline bitfld.long 0x04 6. "FIFO1_OVERRUN,Status raw for interrupt" "No event pending,Event pending" newline bitfld.long 0x04 5. "FIFO1_THRESHOLD,Status raw for interrupt" "No event pending,Event pending" newline bitfld.long 0x04 4. "FIFO0_UNDERFLOW,Status raw for interrupt" "No event pending,Event pending" newline bitfld.long 0x04 3. "FIFO0_OVERRUN,Status raw for interrupt" "No event pending,Event pending" newline bitfld.long 0x04 2. "FIFO0_THRESHOLD,Status raw for interrupt" "No event pending,Event pending" newline bitfld.long 0x04 1. "END_OF_SEQUENCE,Status raw for interrupt" "No event pending,Event pending" newline bitfld.long 0x04 0. "RESERVED,Reserved" "0,1" line.long 0x08 "ADC_IRQSTATUS,Per-event 'enabled' status register vector" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x08 8. "OUT_OF_RANGE,Enabled status for interrupt" "No (enabled) event pending,Event pending" newline bitfld.long 0x08 7. "FIFO1_UNDERFLOW,Enabled status for interrupt" "No (enabled) event pending,Event pending" newline bitfld.long 0x08 6. "FIFO1_OVERRUN,Enabled status for interrupt" "No (enabled) event pending,Event pending" newline bitfld.long 0x08 5. "FIFO1_THRESHOLD,Enabled status for interrupt" "No (enabled) event pending,Event pending" newline bitfld.long 0x08 4. "FIFO0_UNDERFLOW,Enabled status for interrupt" "No (enabled) event pending,Event pending" newline bitfld.long 0x08 3. "FIFO0_OVERRUN,Enabled status for interrupt" "No (enabled) event pending,Event pending" newline bitfld.long 0x08 2. "FIFO0_THRESHOLD,Enabled status for interrupt" "No (enabled) event pending,Event pending" newline bitfld.long 0x08 1. "END_OF_SEQUENCE,Enabled status for interrupt" "No (enabled) event pending,Event pending" newline bitfld.long 0x08 0. "RESERVED,Reserved" "0,1" line.long 0x0C "ADC_IRQENABLE_SET,Per-event interrupt enable bit vector" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 8. "OUT_OF_RANGE,Interrupt enable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x0C 7. "FIFO1_UNDERFLOW,Interrupt enable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x0C 6. "FIFO1_OVERRUN,Interrupt enable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x0C 5. "FIFO1_THRESHOLD,Interrupt enable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x0C 4. "FIFO0_UNDERFLOW,Interrupt enable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x0C 3. "FIFO0_OVERRUN,Interrupt enable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x0C 2. "FIFO0_THRESHOLD,Interrupt enable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x0C 1. "END_OF_SEQUENCE,Interrupt enable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x0C 0. "RESERVED,Reserved" "0,1" line.long 0x10 "ADC_IRQENABLE_CLR,Per-event interrupt disable bit vector" hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 8. "OUT_OF_RANGE,Interrupt disable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x10 7. "FIFO1_UNDERFLOW,Interrupt disable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x10 6. "FIFO1_OVERRUN,Interrupt disable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x10 5. "FIFO1_THRESHOLD,Interrupt disable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x10 4. "FIFO0_UNDERFLOW,Interrupt disable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x10 3. "FIFO0_OVERRUN,Interrupt disable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x10 2. "FIFO0_THRESHOLD,Interrupt disable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x10 1. "END_OF_SEQUENCE,Interrupt disable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x10 0. "RESERVED,Reserved" "0,1" group.long 0x38++0x1F line.long 0x00 "ADC_DMAENABLE_SET,Per-line DMA enable bit vector" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "ENABLE_1,Enable DMA request FIFO 1" "DMA line disabled,DMA line enabled" newline bitfld.long 0x00 0. "ENABLE_0,Enable DMA request FIFO 0" "DMA line disabled,DMA line enabled" line.long 0x04 "ADC_DMAENABLE_CLR,Per-line DMA disable bit vector" hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 1. "ENABLE_1,Disable DMA request FIFO 1" "DMA line disabled,DMA line enabled" newline bitfld.long 0x04 0. "ENABLE_0,Disable DMA request FIFO 0" "DMA line disabled,DMA line enabled" line.long 0x08 "ADC_CTRL,ADC control register" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x08 9. "HW_PREEMPT," "0,1" newline bitfld.long 0x08 5.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 4. "POWER_DOWN,ADC Power Down control" "AFE is powered up,AFE is powered down (default) At default AFE is.." newline bitfld.long 0x08 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 1. "STEP_ID_TAG,Writing 1 to this bit will store the Step ID number with the captured ADC data in the FIFO" "write zeros,store the channel id tag" newline bitfld.long 0x08 0. "ADC_MODULE_ENABLE,ADC module enable bit" "0,1" line.long 0x0C "ADC_ADCSTAT,ADC sequencer status" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 8. "AFE_BUSY,Monitor the AFE internal calibration (busy bit)" "0,1" newline bitfld.long 0x0C 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 5. "FSM_BUSY,Status of OCP FSM and ADC FSM" "idle,busy.." newline bitfld.long 0x0C 0.--4. "STEP_ID," "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Step 1 - Step 16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Reserved" line.long 0x10 "ADC_ADCRANGE,ADC range check register" rbitfld.long 0x10 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x10 16.--27. 1. "HIGH_RANGE_DATA,Sampled ADC data is compared to this value" newline rbitfld.long 0x10 12.--15. "RESERVED,Reseved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x10 0.--11. 1. "LOW_RANGE_DATA,Sampled ADC data is compared to this value" line.long 0x14 "ADC_ADC_CLKDIV,The ADC_CLK input will go through this clock divider first before being sent to the AFE clock input" hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x14 0.--11. 1. "ADC_CLKDIV,The input ADC clock will be divided by this value and sent to the AFE" line.long 0x18 "ADC_ADC_MISC,Zero Offset Correction Using Efuse: Pro: - Covers the ground bounce due to package routing" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 8.--15. 1. "AFE_SPARE_OUTPUT,Connected to AFE Spare Output pins" newline abitfld.long 0x18 0.--7. "AFE_SPARE_INPUT,Connected to AFE Spare Input pins" "0x00=No action,0x01=Start internal calibration,0x02=Internal calibration start (then monitor.." line.long 0x1C "ADC_STEPENABLE,This register contains the enable bit for each step in the sequencer" hexmask.long.word 0x1C 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 16. "STEP16,Enable step 16" "0,1" newline bitfld.long 0x1C 15. "STEP15,Enable step 15" "0,1" newline bitfld.long 0x1C 14. "STEP14,Enable step 14" "0,1" newline bitfld.long 0x1C 13. "STEP13,Enable step 13" "0,1" newline bitfld.long 0x1C 12. "STEP12,Enable step 12" "0,1" newline bitfld.long 0x1C 11. "STEP11,Enable step 11" "0,1" newline bitfld.long 0x1C 10. "STEP10,Enable step 10" "0,1" newline bitfld.long 0x1C 9. "STEP9,Enable step 9" "0,1" newline bitfld.long 0x1C 8. "STEP8,Enable step 8" "0,1" newline bitfld.long 0x1C 7. "STEP7,Enable step 7" "0,1" newline bitfld.long 0x1C 6. "STEP6,Enable step 6" "0,1" newline bitfld.long 0x1C 5. "STEP5,Enable step 5" "0,1" newline bitfld.long 0x1C 4. "STEP4,Enable step 4" "0,1" newline bitfld.long 0x1C 3. "STEP3,Enable step 3" "0,1" newline bitfld.long 0x1C 2. "STEP2,Enable step 2" "0,1" newline bitfld.long 0x1C 1. "STEP1,Enable step 1" "0,1" newline bitfld.long 0x1C 0. "RESERVED,Reserved" "0,1" group.long 0x64++0x03 line.long 0x00 "ADC_STEPCONFIGi_0,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0x6C++0x03 line.long 0x00 "ADC_STEPCONFIGi_1,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0x74++0x03 line.long 0x00 "ADC_STEPCONFIGi_2,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0x7C++0x03 line.long 0x00 "ADC_STEPCONFIGi_3,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0x84++0x03 line.long 0x00 "ADC_STEPCONFIGi_4,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0x8C++0x03 line.long 0x00 "ADC_STEPCONFIGi_5,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0x94++0x03 line.long 0x00 "ADC_STEPCONFIGi_6,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0x9C++0x03 line.long 0x00 "ADC_STEPCONFIGi_7,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0xA4++0x03 line.long 0x00 "ADC_STEPCONFIGi_8,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0xAC++0x03 line.long 0x00 "ADC_STEPCONFIGi_9,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0xB4++0x03 line.long 0x00 "ADC_STEPCONFIGi_10,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0xBC++0x03 line.long 0x00 "ADC_STEPCONFIGi_11,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0xC4++0x03 line.long 0x00 "ADC_STEPCONFIGi_12,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0xCC++0x03 line.long 0x00 "ADC_STEPCONFIGi_13,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0xD4++0x03 line.long 0x00 "ADC_STEPCONFIGi_14,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0xDC++0x03 line.long 0x00 "ADC_STEPCONFIGi_15,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0x68++0x03 line.long 0x00 "ADC_STEPDELAYi_0,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0x70++0x03 line.long 0x00 "ADC_STEPDELAYi_1,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0x78++0x03 line.long 0x00 "ADC_STEPDELAYi_2,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0x80++0x03 line.long 0x00 "ADC_STEPDELAYi_3,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0x88++0x03 line.long 0x00 "ADC_STEPDELAYi_4,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0x90++0x03 line.long 0x00 "ADC_STEPDELAYi_5,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0x98++0x03 line.long 0x00 "ADC_STEPDELAYi_6,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xA0++0x03 line.long 0x00 "ADC_STEPDELAYi_7,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xA8++0x03 line.long 0x00 "ADC_STEPDELAYi_8,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xB0++0x03 line.long 0x00 "ADC_STEPDELAYi_9,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xB8++0x03 line.long 0x00 "ADC_STEPDELAYi_10,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xC0++0x03 line.long 0x00 "ADC_STEPDELAYi_11,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xC8++0x03 line.long 0x00 "ADC_STEPDELAYi_12,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xD0++0x03 line.long 0x00 "ADC_STEPDELAYi_13,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xD8++0x03 line.long 0x00 "ADC_STEPDELAYi_14,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xE0++0x1B line.long 0x00 "ADC_STEPDELAYi_15,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" line.long 0x04 "ADC_FIFO0COUNT,FIFO0 word count register" hexmask.long 0x04 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x04 0.--6. 1. "WORDS_IN_FIFO,Number of words currently in the FIFO0" line.long 0x08 "ADC_FIFO0THRESHOLD,FIFO0 threshold level register" hexmask.long 0x08 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x08 0.--5. "FIFO_THRESHOLD_LEVEL,Program the desired FIFO0 data sample level to reach before generating interrupt to CPU (program to value minus 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "ADC_DMA0REQ,FIFO0 DMA request level register" hexmask.long 0x0C 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 0.--5. "DMA_REQUEST_LEVEL,Number of words in FIFO0 before generating a DMA request (program to value minus 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "ADC_FIFO1COUNT,FIFO1 word count register" hexmask.long 0x10 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--6. 1. "WORDS_IN_FIFO,Number of words currently in the FIFO1" line.long 0x14 "ADC_FIFO1THRESHOLD,FIFO1 threshold level register" hexmask.long 0x14 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0.--5. "FIFO_THRESHOLD_LEVEL,Program the desired FIFO1 data sample level to reach before generating interrupt to CPU (program to value minus 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "ADC_DMA1REQ,FIFO1 DMA request level register" hexmask.long 0x18 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x18 0.--5. "DMA_REQUEST_LEVEL,Number of words in FIFO1 before generating a DMA request (program to value minus 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x100++0x03 line.long 0x00 "ADC_FIFO0DATA,The CPU can read from this register to read data in FIFO 0" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--19. "ADCCHNLID,Optional ID tag of channel that captured the data" "Step 1,Step2;,?,?,?,?,?,?,?,?,?,?,?,?,?,Step 16" newline bitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--11. 1. "ADCDATA,12 bit sampled ADC converted data value stored in FIFO 0" rgroup.long 0x200++0x03 line.long 0x00 "ADC_FIFO1DATA,The CPU can read from this register to read data in FIFO 1" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--19. "ADCCHNLID,Optional ID tag of channel that captured the data" "Step 1,Step2;,?,?,?,?,?,?,?,?,?,?,?,?,?,Step 16" newline bitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--11. 1. "ADCDATA,12 bit sampled ADC converted data value stored in FIFO 1" width 0x0B tree.end tree "ALE" base ad:0x48484D00 rgroup.long 0x00++0x03 line.long 0x00 "ALE_IDVER,ADDRESS LOOKUP ENGINE revision register" group.long 0x08++0x03 line.long 0x00 "ALE_CONTROL,Address lookup engine control register" bitfld.long 0x00 31. "ENABLE_ALE,Enable ALE" "Drop all packets,Enable ALE packet processing" newline bitfld.long 0x00 30. "CLEAR_TABLE,Clear ALE address table - Setting this bit causes the ALE hardware to write all table bit values to zero" "0,1" newline bitfld.long 0x00 29. "AGE_OUT_NOW,Age Out Address Table Now - Setting this bit causes the ALE hardware to remove (free up) any ageable table entry that does not have a set touch bit" "0,1" newline hexmask.long.tbyte 0x00 9.--28. 1. "RESERVED," newline bitfld.long 0x00 8. "EN_P0_UNI_FLOOD,Enable Port 0 (Host Port) unicast flood" "do not flood unknown unicast packets to host..,flood unknown unicast packets to host port (p0)" newline bitfld.long 0x00 7. "LEARN_NO_VID,Learn No VID" "VID is learned with the source address,VID is not learned with the source address.." newline bitfld.long 0x00 6. "EN_VID0_MODE,Enable VLAN ID = 0 Mode" "Process the packet with VID = PORT_VLAN[11:0],Process the packet with VID = 0" newline bitfld.long 0x00 5. "ENABLE_OUI_DENY,Enable OUI Deny Mode - When set this bit indicates that a packet with a non OUI table entry matching source address will be dropped to the host unless the destination address matches a multicast table entry with the super bit set" "0,1" newline bitfld.long 0x00 4. "BYPASS,ALE Bypass - When set all packets received on ports 0 and 1 are sent to the host (only to the host)" "0,1" newline bitfld.long 0x00 3. "RATE_LIMIT_TX,Rate Limit Transmit mode" "Broadcast and multicast rate limit counters are..,Broadcast and multicast rate limit counters are.." newline bitfld.long 0x00 2. "VLAN_AWARE,ALE VLAN Aware - Determines what is done if VLAN not found" "Flood if VLAN not found,Drop packet if VLAN not found" newline bitfld.long 0x00 1. "ENABLE_AUTH_MODE,Enable MAC Authorization Mode - Mac authorization mode requires that all table entries be made by the host software" "The ALE is not in MAC authorization mode,The ALE is in MAC authorization mode" newline bitfld.long 0x00 0. "ENABLE_RATE_LIMIT,Enable Broadcast and Multicast Rate Limit" "Broadcast/Multicast rates not limited,Broadcast/Multicast packet reception limited to.." group.long 0x10++0x03 line.long 0x00 "ALE_PRESCALE,Address lookup engine prescale register" hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--19. 1. "PRESCALE,ALE Prescale Register - The input clock is divided by this value for use in the multicast/broadcast rate limiters" group.long 0x18++0x03 line.long 0x00 "ALE_UNKNOWN_VLAN,Address lookup engine unknown vlan register" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 24.--29. "UNKNOWN_FORCE_UNTAGGED_EGRESS,Unknown VLAN Force Untagged Egress" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 16.--21. "UNKNOWN_REG_MCAST_FLOOD_MASK,Unknown VLAN Registered Multicast Flood Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 8.--13. "UNKNOWN_MCAST_FLOOD_MASK,Unknown VLAN Multicast Flood Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 0.--5. "UNKNOWN_VLAN_MEMBER_LIST,Unknown VLAN Member List" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x20++0x03 line.long 0x00 "ALE_TBLCTL,Address lookup engine table control" bitfld.long 0x00 31. "WRITE_RDZ,Write Bit - This bit is always read as zero" "0,1" newline hexmask.long.tbyte 0x00 10.--30. 1. "RESERVED," newline hexmask.long.word 0x00 0.--9. 1. "ENTRY_POINTER,Table Entry Pointer - The entry_pointer contains the table entry value that will be read/written with accesses to the table word registers" group.long 0x34++0x23 line.long 0x00 "ALE_TBLW2,Address lookup engine table word 2 register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--7. 1. "ENTRY71_64,Table entry bits 71:64" line.long 0x04 "ALE_TBLW1,Address lookup engine table word 1 register" line.long 0x08 "ALE_TBLW0,Address lookup engine table word 0 register" line.long 0x0C "ALE_PORTCTL0,Address lookup engine port 0 control register" hexmask.long.byte 0x0C 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x0C 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline hexmask.long.word 0x0C 6.--15. 1. "RESERVED," newline bitfld.long 0x0C 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x0C 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x0C 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x0C 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x0C 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x10 "ALE_PORTCTL1,Address lookup engine port 1 control register" hexmask.long.byte 0x10 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x10 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline hexmask.long.word 0x10 6.--15. 1. "RESERVED," newline bitfld.long 0x10 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x10 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x10 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x10 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x10 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x14 "ALE_PORTCTL2,Address lookup engine port 2 control register" hexmask.long.byte 0x14 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x14 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline hexmask.long.word 0x14 6.--15. 1. "RESERVED," newline bitfld.long 0x14 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x14 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x14 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x14 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x14 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x18 "ALE_PORTCTL3,Address lookup engine port 3 control register" hexmask.long.byte 0x18 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x18 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline hexmask.long.word 0x18 6.--15. 1. "RESERVED," newline bitfld.long 0x18 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x18 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x18 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x18 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x18 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x1C "ALE_PORTCTL4,Address lookup engine port 4 control register" hexmask.long.byte 0x1C 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x1C 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline hexmask.long.word 0x1C 6.--15. 1. "RESERVED," newline bitfld.long 0x1C 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x1C 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x1C 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x1C 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x1C 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x20 "ALE_PORTCTL5,Address lookup engine port 5 control register" hexmask.long.byte 0x20 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x20 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline hexmask.long.word 0x20 6.--15. 1. "RESERVED," newline bitfld.long 0x20 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x20 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x20 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x20 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x20 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" width 0x0B tree.end tree "CAL_A" base ad:0x52012000 rgroup.long 0x00++0x07 line.long 0x00 "CAL_HL_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "CAL_HL_HWINFO,Information about the IP module's hardware configuration. i.e" bitfld.long 0x04 30.--31. "NPPI_CONTEXTS1,Number of contexts for PPI interface #0" "NPPI_CONTEXTS1_0_r,NPPI_CONTEXTS1_1_r,NPPI_CONTEXTS1_2_r,NPPI_CONTEXTS1_3_r" newline bitfld.long 0x04 28.--29. "NPPI_CONTEXTS0,Number of contexts for PPI interface #0" "NPPI_CONTEXTS0_0_r,NPPI_CONTEXTS0_1_r,NPPI_CONTEXTS0_2_r,NPPI_CONTEXTS0_3_r" newline bitfld.long 0x04 23.--27. "NCPORT,Number of supported CPORTs (including CPORT #0) minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 19.--22. "VFIFO,Video port FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 13.--18. "WCTX,Number of implemented DMA write contexts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--12. "PCTX,Number of implemented pixel processing contexts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 4.--7. "RFIFO,Read FIFO size 2^RFIFO words of 16 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. "WFIFO,Write FIFO size 2^WFIFO words of 16 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x03 line.long 0x00 "CAL_HL_SYSCONFIG,Clock management configuration" hexmask.long 0x00 4.--31. 1. "RESERVED," newline bitfld.long 0x00 2.--3. "IDLEMODE,IDLE protocol configuration" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline rbitfld.long 0x00 1. "RESERVED," "0,1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_r" group.long 0x1C++0x07 line.long 0x00 "CAL_HL_IRQ_EOI,End Of Interrupt number specification" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "CAL_HL_IRQSTATUS_RAW_j_0,Per-event raw interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x04 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x04 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x04 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x04 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x04 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x04 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x04 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x04 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x04 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x04 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x04 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x04 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x04 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x04 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x04 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x04 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x04 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x04 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x04 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x04 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x04 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x04 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x04 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x04 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x30++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_1,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x40++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_2,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x50++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_3,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x60++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_4,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x70++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_5,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x80++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_6,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x90++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_7,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0xA0++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_8,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0xB0++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_9,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x24++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_0,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x34++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_1,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x44++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_2,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x54++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_3,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x64++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_4,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x74++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_5,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x84++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_6,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x94++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_7,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0xA4++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_8,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0xB4++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_9,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x28++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_0,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x38++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_1,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x48++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_2,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x58++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_3,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x68++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_4,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x78++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_5,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x88++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_6,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x98++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_7,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0xA8++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_8,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0xB8++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_9,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x2C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_0,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x3C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_1,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x4C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_2,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x5C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_3,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x6C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_4,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x7C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_5,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x8C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_6,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x9C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_7,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0xAC++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_8,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0xBC++0x13 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_9,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_PIX_PROC_i_0,Pixel processing control" hexmask.long.byte 0x04 24.--31. 1. "RESERVED," newline bitfld.long 0x04 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 16.--18. "PACK,Control pixel packing" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" newline bitfld.long 0x04 11.--15. "DPCME,DPCM encoder" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" newline rbitfld.long 0x04 10. "RESERVED," "0,1" newline bitfld.long 0x04 5.--9. "DPCMD,DPCM Decoder" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 1.--4. "EXTRACT,Control pixel extraction from the byte stream" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" newline bitfld.long 0x04 0. "EN,Enable the pixel processing context" "EN_0,EN_1" line.long 0x08 "CAL_PIX_PROC_i_1,Pixel processing control" hexmask.long.byte 0x08 24.--31. 1. "RESERVED," newline bitfld.long 0x08 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 16.--18. "PACK,Control pixel packing" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" newline bitfld.long 0x08 11.--15. "DPCME,DPCM encoder" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" newline rbitfld.long 0x08 10. "RESERVED," "0,1" newline bitfld.long 0x08 5.--9. "DPCMD,DPCM Decoder" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x08 1.--4. "EXTRACT,Control pixel extraction from the byte stream" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" newline bitfld.long 0x08 0. "EN,Enable the pixel processing context" "EN_0,EN_1" line.long 0x0C "CAL_PIX_PROC_i_2,Pixel processing control" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," newline bitfld.long 0x0C 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 16.--18. "PACK,Control pixel packing" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" newline bitfld.long 0x0C 11.--15. "DPCME,DPCM encoder" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" newline rbitfld.long 0x0C 10. "RESERVED," "0,1" newline bitfld.long 0x0C 5.--9. "DPCMD,DPCM Decoder" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x0C 1.--4. "EXTRACT,Control pixel extraction from the byte stream" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" newline bitfld.long 0x0C 0. "EN,Enable the pixel processing context" "EN_0,EN_1" line.long 0x10 "CAL_PIX_PROC_i_3,Pixel processing control" hexmask.long.byte 0x10 24.--31. 1. "RESERVED," newline bitfld.long 0x10 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x10 16.--18. "PACK,Control pixel packing" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" newline bitfld.long 0x10 11.--15. "DPCME,DPCM encoder" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" newline rbitfld.long 0x10 10. "RESERVED," "0,1" newline bitfld.long 0x10 5.--9. "DPCMD,DPCM Decoder" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x10 1.--4. "EXTRACT,Control pixel extraction from the byte stream" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" newline bitfld.long 0x10 0. "EN,Enable the pixel processing context" "EN_0,EN_1" group.long 0x100++0x0B line.long 0x00 "CAL_CTRL,Global control register" hexmask.long.byte 0x00 24.--31. 1. "MFLAGH,refer to real time traffic section of the spec" newline rbitfld.long 0x00 23. "RESERVED," "0,1" newline bitfld.long 0x00 22. "RD_DMA_STALL,Controls if the pixel stream from the RD DMA's FIFO to the internal pipeline shall be stalled when MFlag/=0" "RD_DMA_STALL_0,RD_DMA_STALL_1" newline bitfld.long 0x00 21. "PWRSCPCLK,Controls autogating of the PWRSCP clock" "PWRSCPCLK_0,PWRSCPCLK_1" newline hexmask.long.byte 0x00 13.--20. 1. "MFLAGL,refer to real time traffic section of the spec" newline bitfld.long 0x00 7.--12. "LL_FORCE_STATE,Forces the state of the CSI-3 low level protocol state machine" "the next OCPI transaction for this CPORT will..,the next OCPI transaction for this CPORT will..,?..." newline bitfld.long 0x00 5.--6. "BURSTSIZE,Maximum allowed burst size for the write DMA" "BURSTSIZE_0,BURSTSIZE_1,BURSTSIZE_2,BURSTSIZE_3" newline bitfld.long 0x00 1.--4. "TAGCNT,Maximum number of outstanding OCP transactions = TAGCNT+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "POSTED_WRITES," "POSTED_WRITES_0,POSTED_WRITES_1" line.long 0x04 "CAL_CTRL1,CAL global control register" hexmask.long 0x04 6.--31. 1. "RESERVED," newline bitfld.long 0x04 4.--5. "INTERLEAVE23,Controls stream interleaving Context #2 and #3" "INTERLEAVE23_0,INTERLEAVE23_1,INTERLEAVE23_2,INTERLEAVE23_3" newline bitfld.long 0x04 2.--3. "INTERLEAVE01,Controls stream interleaving Context #0 and #1" "INTERLEAVE01_0,INTERLEAVE01_1,INTERLEAVE01_2,INTERLEAVE01_3" newline bitfld.long 0x04 0.--1. "PPI_GROUPING,Controls PPI grouping" "PPI_GROUPING_0,PPI_GROUPING_1,PPI_GROUPING_2,PPI_GROUPING_3" line.long 0x08 "CAL_LINE_NUMBER_EVT,Controls generation of the line number event" rbitfld.long 0x08 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x08 16.--29. 1. "LINE," newline hexmask.long.word 0x08 5.--15. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "CPORT,CPort ID to monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x120++0x07 line.long 0x00 "CAL_VPORT_CTRL1,Video port control register" bitfld.long 0x00 31. "WIDTH,Video port width" "WIDTH_0,WIDTH_1" newline bitfld.long 0x00 25.--30. "YBLK,Vertical blanking = YBLK lines Valid range : 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 17.--24. 1. "XBLK,Horizontal blanking = 8*XBLK cycles Valid range = 0..2040 cycles" newline hexmask.long.tbyte 0x00 0.--16. 1. "PCLK,Video port pixel clock = FCLK * PCLK / 2^16 Valid range: 0" line.long 0x04 "CAL_VPORT_CTRL2,Video port control register" hexmask.long.word 0x04 18.--31. 1. "RDY_THR,Data shall be send to the video port after frame start only when (RDY_THR+1)*4 pixels are ready and the 4 PCLK cycles (require before each frame start) have been sent" newline bitfld.long 0x04 17. "FSM_RESET,Forces a reset of the video port FSM" "FSM_RESET_0_w,FSM_RESET_1_w" newline bitfld.long 0x04 16. "FS_RESETS,Controls the behavior of the timing generator when a data tagged as PIX_DAT_FS is received" "FS_RESETS_0,FS_RESETS_1" newline bitfld.long 0x04 15. "FREERUNNING,Controls PCLK generation during IDLE" "FREERUNNING_0,FREERUNNING_1" newline hexmask.long.word 0x04 5.--14. 1. "RESERVED," newline bitfld.long 0x04 0.--4. "CPORT,Cport ID Valid range=0..(CAL_HL_HWINFO.NCPORT-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x130++0x07 line.long 0x00 "CAL_BYS_CTRL1,BYS port control register" bitfld.long 0x00 31. "BYSINEN,Enable/disable the BYS input port Note: the BYS output port is disabled by setting PCLK=0" "BYSINEN_0,BYSINEN_1" newline bitfld.long 0x00 25.--30. "YBLK,Vertical blanking = YBLK lines Valid range : 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 17.--24. 1. "XBLK,Horizontal blanking = 8*XBLK cycles Valid range = 0..2040 cycles" newline hexmask.long.tbyte 0x00 0.--16. 1. "PCLK,BYSout port pixel clock = FCLK * PCLK / 2^16 Valid range: 0" line.long 0x04 "CAL_BYS_CTRL2,BYS port control register" hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED," newline bitfld.long 0x04 11. "FREERUNNING,Controls PCLK generation when the BYSout state machine is in the IDLE state" "FREERUNNING_0,FREERUNNING_1" newline bitfld.long 0x04 10. "DUPLICATEDDATA,Control if data sent to the BYS output port should also be send to the DPCM encoder" "DUPLICATEDDATA_0,DUPLICATEDDATA_1" newline bitfld.long 0x04 5.--9. "CPORTOUT,BYS output port processes data received with the CPORT ID defined in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. "CPORTIN,Cport ID used for data received from the BYSin port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x140++0x17 line.long 0x00 "CAL_RD_DMA_CTRL,Read DMA control register" hexmask.long.tbyte 0x00 15.--31. 1. "PCLK,Controls the data rate at which data is read from the read DMA FIFO and sent to the internal processing pipeline" newline bitfld.long 0x00 11.--14. "OCP_TAG_CNT,Maximum allowed number of outstanding OCP read requests minus 1 (i.e. 0xF meand up to 16 outstanding requests)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 2.--10. 1. "BW_LIMITER,Defines a minimum cycle count between to consecutive read requests issued by the RD DMA" newline bitfld.long 0x00 1. "INIT,Enable reading of DPCM decoder initialization data from SDRAM" "INIT_0,INIT_1" newline bitfld.long 0x00 0. "GO,Start data read from memory" "GO_0_r,GO_1_r" line.long 0x04 "CAL_RD_DMA_PIX_ADDR,Byte address of the top left corner of the buffer to read in system memory" hexmask.long 0x04 3.--31. 1. "ADDR,Address in words of 8 bytes" newline rbitfld.long 0x04 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x08 "CAL_RD_DMA_PIX_OFST,Byte offset between two consecutive line starts Shall be 16 byte aligned for YUV420" hexmask.long 0x08 4.--31. 1. "OFST,Offset in words of 16 bytes" newline rbitfld.long 0x08 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "CAL_RD_DMA_XSIZE,Number of bytes to read per line" hexmask.long.word 0x0C 19.--31. 1. "XSIZE,Words of 64-bits to read per line" newline hexmask.long.tbyte 0x0C 0.--18. 1. "RESERVED," line.long 0x10 "CAL_RD_DMA_YSIZE,Number of lines to" rbitfld.long 0x10 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x10 16.--29. 1. "YSIZE," newline hexmask.long.word 0x10 0.--15. 1. "RESERVED," line.long 0x14 "CAL_RD_DMA_INIT_ADDR,Read address" hexmask.long 0x14 3.--31. 1. "ADDR,Address in words of 8 bytes" newline rbitfld.long 0x14 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x168++0x07 line.long 0x00 "CAL_RD_DMA_INIT_OFST,Byte offset between two consecutive line starts" hexmask.long 0x00 3.--31. 1. "OFST,Offset in words of 8 bytes" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x04 "CAL_RD_DMA_CTRL2,Read DMA control register" rbitfld.long 0x04 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x04 16.--29. 1. "CIRC_SIZE,Circular buffer size minus one" newline hexmask.long.word 0x04 7.--15. 1. "RESERVED," newline bitfld.long 0x04 6. "BYSOUT_LE_WAIT,Controls the behavior of the RD DMA when the line end is reached" "BYSOUT_LE_WAIT_0,BYSOUT_LE_WAIT_1" newline bitfld.long 0x04 4.--5. "RD_PATTERN,Data read pattern" "RD_PATTERN_0,RD_PATTERN_1,RD_PATTERN_2,RD_PATTERN_3" newline bitfld.long 0x04 3. "ICM_CSTART,Enables monitoring of the ICM_CSTART signal" "ICM_CSTART_0,ICM_CSTART_1" newline bitfld.long 0x04 0.--2. "CIRC_MODE,Circular mode control" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3,CIRC_MODE_4,CIRC_MODE_5,?,?" group.long 0x200++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_0,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" newline rbitfld.long 0x00 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal" "ICM_PSTART_0,ICM_PSTART_1" newline bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x210++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_1,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" newline rbitfld.long 0x00 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal" "ICM_PSTART_0,ICM_PSTART_1" newline bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x220++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_2,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" newline rbitfld.long 0x00 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal" "ICM_PSTART_0,ICM_PSTART_1" newline bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x230++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_3,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" newline rbitfld.long 0x00 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal" "ICM_PSTART_0,ICM_PSTART_1" newline bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x240++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_4,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" newline rbitfld.long 0x00 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal" "ICM_PSTART_0,ICM_PSTART_1" newline bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x250++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_5,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" newline rbitfld.long 0x00 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal" "ICM_PSTART_0,ICM_PSTART_1" newline bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x260++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_6,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" newline rbitfld.long 0x00 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal" "ICM_PSTART_0,ICM_PSTART_1" newline bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x270++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_7,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" newline rbitfld.long 0x00 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal" "ICM_PSTART_0,ICM_PSTART_1" newline bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x204++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_0,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x214++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_1,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x224++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_2,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x234++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_3,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x244++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_4,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x254++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_5,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x264++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_6,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x274++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_7,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x208++0x03 line.long 0x00 "CAL_WR_DMA_OFST_k_0,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" newline bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x218++0x03 line.long 0x00 "CAL_WR_DMA_OFST_k_1,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" newline bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x228++0x03 line.long 0x00 "CAL_WR_DMA_OFST_k_2,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" newline bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x238++0x03 line.long 0x00 "CAL_WR_DMA_OFST_k_3,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" newline bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x248++0x03 line.long 0x00 "CAL_WR_DMA_OFST_k_4,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" newline bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x258++0x03 line.long 0x00 "CAL_WR_DMA_OFST_k_5,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" newline bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x268++0x03 line.long 0x00 "CAL_WR_DMA_OFST_k_6,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" newline bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x278++0x03 line.long 0x00 "CAL_WR_DMA_OFST_k_7,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" newline bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20C++0x03 line.long 0x00 "CAL_WR_DMA_XSIZE_k_0,Defines the size of a line written to memory" hexmask.long.word 0x00 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" newline rbitfld.long 0x00 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x21C++0x03 line.long 0x00 "CAL_WR_DMA_XSIZE_k_1,Defines the size of a line written to memory" hexmask.long.word 0x00 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" newline rbitfld.long 0x00 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x22C++0x03 line.long 0x00 "CAL_WR_DMA_XSIZE_k_2,Defines the size of a line written to memory" hexmask.long.word 0x00 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" newline rbitfld.long 0x00 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x23C++0x03 line.long 0x00 "CAL_WR_DMA_XSIZE_k_3,Defines the size of a line written to memory" hexmask.long.word 0x00 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" newline rbitfld.long 0x00 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x24C++0x03 line.long 0x00 "CAL_WR_DMA_XSIZE_k_4,Defines the size of a line written to memory" hexmask.long.word 0x00 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" newline rbitfld.long 0x00 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x25C++0x03 line.long 0x00 "CAL_WR_DMA_XSIZE_k_5,Defines the size of a line written to memory" hexmask.long.word 0x00 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" newline rbitfld.long 0x00 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x26C++0x03 line.long 0x00 "CAL_WR_DMA_XSIZE_k_6,Defines the size of a line written to memory" hexmask.long.word 0x00 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" newline rbitfld.long 0x00 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x27C++0x03 line.long 0x00 "CAL_WR_DMA_XSIZE_k_7,Defines the size of a line written to memory" hexmask.long.word 0x00 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" newline rbitfld.long 0x00 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x300++0x03 line.long 0x00 "CAL_CSI2_PPI_CTRL_l_0,Controls the low level CSI-2 protocol interface (PPI)" hexmask.long 0x00 4.--31. 1. "RESERVED," newline bitfld.long 0x00 3. "FRAME,Set the modality in which IF_EN works" "FRAME_0,FRAME_1" newline bitfld.long 0x00 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids)" "ECC_EN_0,ECC_EN_1" newline rbitfld.long 0x00 1. "RESERVED," "0,1" newline bitfld.long 0x00 0. "IF_EN,Enables the physical interface to the module" "IF_EN_0,IF_EN_1" group.long 0x380++0x03 line.long 0x00 "CAL_CSI2_PPI_CTRL_l_1,Controls the low level CSI-2 protocol interface (PPI)" hexmask.long 0x00 4.--31. 1. "RESERVED," newline bitfld.long 0x00 3. "FRAME,Set the modality in which IF_EN works" "FRAME_0,FRAME_1" newline bitfld.long 0x00 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids)" "ECC_EN_0,ECC_EN_1" newline rbitfld.long 0x00 1. "RESERVED," "0,1" newline bitfld.long 0x00 0. "IF_EN,Enables the physical interface to the module" "IF_EN_0,IF_EN_1" group.long 0x304++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_CFG_l_0,COMPLEXIO CONFIGURATION REGISTER This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in addition to the.." rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 30. "RESET_CTRL,Controls the reset of the complex IO" "RESET_CTRL_0,RESET_CTRL_1" newline rbitfld.long 0x00 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io" "RESET_DONE_0_r,RESET_DONE_1_r" newline bitfld.long 0x00 27.--28. "PWR_CMD,Command for power control of the complex io" "PWR_CMD_0,PWR_CMD_1,PWR_CMD_2,?" newline rbitfld.long 0x00 25.--26. "PWR_STATUS,Status of the power control of the complex io" "PWR_STATUS_0_r,PWR_STATUS_1_r,PWR_STATUS_2_r,?" newline bitfld.long 0x00 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO" "PWR_AUTO_0,PWR_AUTO_1" newline rbitfld.long 0x00 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19. "DATA4_POL,+/- differential pin order of DATA lane 4" "DATA4_POL_0,DATA4_POL_1" newline bitfld.long 0x00 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4" "DATA4_POSITION_0,DATA4_POSITION_1,DATA4_POSITION_2,DATA4_POSITION_3,DATA4_POSITION_4,DATA4_POSITION_5,?,?" newline bitfld.long 0x00 15. "DATA3_POL,+/- differential pin order of DATA lane 3" "DATA3_POL_0,DATA3_POL_1" newline bitfld.long 0x00 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3" "DATA3_POSITION_0,DATA3_POSITION_1,DATA3_POSITION_2,DATA3_POSITION_3,DATA3_POSITION_4,DATA3_POSITION_5,?,?" newline bitfld.long 0x00 11. "DATA2_POL,+/- differential pin order of DATA lane 2" "DATA2_POL_0,DATA2_POL_1" newline bitfld.long 0x00 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2" "DATA2_POSITION_0,DATA2_POSITION_1,DATA2_POSITION_2,DATA2_POSITION_3,DATA2_POSITION_4,DATA2_POSITION_5,?,?" newline bitfld.long 0x00 7. "DATA1_POL,+/- differential pin order of DATA lane 1" "DATA1_POL_0,DATA1_POL_1" newline bitfld.long 0x00 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1" "?,DATA1_POSITION_1,DATA1_POSITION_2,DATA1_POSITION_3,DATA1_POSITION_4,DATA1_POSITION_5,?,?" newline bitfld.long 0x00 3. "CLOCK_POL,+/- differential pin order of CLOCK lane" "CLOCK_POL_0,CLOCK_POL_1" newline bitfld.long 0x00 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane" "?,CLOCK_POSITION_1,CLOCK_POSITION_2,CLOCK_POSITION_3,CLOCK_POSITION_4,CLOCK_POSITION_5,?,?" group.long 0x384++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_CFG_l_1,COMPLEXIO CONFIGURATION REGISTER This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in addition to the.." rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 30. "RESET_CTRL,Controls the reset of the complex IO" "RESET_CTRL_0,RESET_CTRL_1" newline rbitfld.long 0x00 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io" "RESET_DONE_0_r,RESET_DONE_1_r" newline bitfld.long 0x00 27.--28. "PWR_CMD,Command for power control of the complex io" "PWR_CMD_0,PWR_CMD_1,PWR_CMD_2,?" newline rbitfld.long 0x00 25.--26. "PWR_STATUS,Status of the power control of the complex io" "PWR_STATUS_0_r,PWR_STATUS_1_r,PWR_STATUS_2_r,?" newline bitfld.long 0x00 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO" "PWR_AUTO_0,PWR_AUTO_1" newline rbitfld.long 0x00 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19. "DATA4_POL,+/- differential pin order of DATA lane 4" "DATA4_POL_0,DATA4_POL_1" newline bitfld.long 0x00 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4" "DATA4_POSITION_0,DATA4_POSITION_1,DATA4_POSITION_2,DATA4_POSITION_3,DATA4_POSITION_4,DATA4_POSITION_5,?,?" newline bitfld.long 0x00 15. "DATA3_POL,+/- differential pin order of DATA lane 3" "DATA3_POL_0,DATA3_POL_1" newline bitfld.long 0x00 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3" "DATA3_POSITION_0,DATA3_POSITION_1,DATA3_POSITION_2,DATA3_POSITION_3,DATA3_POSITION_4,DATA3_POSITION_5,?,?" newline bitfld.long 0x00 11. "DATA2_POL,+/- differential pin order of DATA lane 2" "DATA2_POL_0,DATA2_POL_1" newline bitfld.long 0x00 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2" "DATA2_POSITION_0,DATA2_POSITION_1,DATA2_POSITION_2,DATA2_POSITION_3,DATA2_POSITION_4,DATA2_POSITION_5,?,?" newline bitfld.long 0x00 7. "DATA1_POL,+/- differential pin order of DATA lane 1" "DATA1_POL_0,DATA1_POL_1" newline bitfld.long 0x00 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1" "?,DATA1_POSITION_1,DATA1_POSITION_2,DATA1_POSITION_3,DATA1_POSITION_4,DATA1_POSITION_5,?,?" newline bitfld.long 0x00 3. "CLOCK_POL,+/- differential pin order of CLOCK lane" "CLOCK_POL_0,CLOCK_POL_1" newline bitfld.long 0x00 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane" "?,CLOCK_POSITION_1,CLOCK_POSITION_2,CLOCK_POSITION_3,CLOCK_POSITION_4,CLOCK_POSITION_5,?,?" group.long 0x308++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQSTATUS_l_0,INTERRUPT STATUS REGISTER - All errors from complex IO #1" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" newline rbitfld.long 0x00 29. "RESERVED," "0,1" newline bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow" "FIFO_OVR_0,FIFO_OVR_1" newline bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" newline bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "STATEULPM4_0,STATEULPM4_1" newline bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "STATEULPM2_0,STATEULPM2_1" newline bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5" "ERRCONTROL5_0,ERRCONTROL5_1" newline bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3" "ERRCONTROL3_0,ERRCONTROL3_1" newline bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1" "ERRCONTROL1_0,ERRCONTROL1_1" newline bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4" "ERRESC4_0,ERRESC4_1" newline bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2" "ERRESC2_0,ERRESC2_1" newline bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" newline bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" newline bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" newline bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4" "ERRSOTHS4_0,ERRSOTHS4_1" newline bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2" "ERRSOTHS2_0,ERRSOTHS2_1" newline bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x388++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQSTATUS_l_1,INTERRUPT STATUS REGISTER - All errors from complex IO #1" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" newline rbitfld.long 0x00 29. "RESERVED," "0,1" newline bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow" "FIFO_OVR_0,FIFO_OVR_1" newline bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" newline bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "STATEULPM4_0,STATEULPM4_1" newline bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "STATEULPM2_0,STATEULPM2_1" newline bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5" "ERRCONTROL5_0,ERRCONTROL5_1" newline bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3" "ERRCONTROL3_0,ERRCONTROL3_1" newline bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1" "ERRCONTROL1_0,ERRCONTROL1_1" newline bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4" "ERRESC4_0,ERRESC4_1" newline bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2" "ERRESC2_0,ERRESC2_1" newline bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" newline bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" newline bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" newline bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4" "ERRSOTHS4_0,ERRSOTHS4_1" newline bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2" "ERRSOTHS2_0,ERRSOTHS2_1" newline bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1" "ERRSOTHS1_0,ERRSOTHS1_1" rgroup.long 0x30C++0x03 line.long 0x00 "CAL_CSI2_SHORT_PACKET_l_0,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads returns 0" newline hexmask.long.tbyte 0x00 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD" rgroup.long 0x38C++0x03 line.long 0x00 "CAL_CSI2_SHORT_PACKET_l_1,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads returns 0" newline hexmask.long.tbyte 0x00 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD" group.long 0x310++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQENABLE_l_0,INTERRUPT ENABLE REGISTER - All errors from complex IO #1" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" newline rbitfld.long 0x00 29. "RESERVED," "0,1" newline bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow" "FIFO_OVR_0,FIFO_OVR_1" newline bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" newline bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "STATEULPM4_0,STATEULPM4_1" newline bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "STATEULPM2_0,STATEULPM2_1" newline bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5" "ERRCONTROL5_0,ERRCONTROL5_1" newline bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3" "ERRCONTROL3_0,ERRCONTROL3_1" newline bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1" "ERRCONTROL1_0,ERRCONTROL1_1" newline bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4" "ERRESC4_0,ERRESC4_1" newline bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2" "ERRESC2_0,ERRESC2_1" newline bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" newline bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" newline bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" newline bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4" "ERRSOTHS4_0,ERRSOTHS4_1" newline bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2" "ERRSOTHS2_0,ERRSOTHS2_1" newline bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x390++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQENABLE_l_1,INTERRUPT ENABLE REGISTER - All errors from complex IO #1" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" newline rbitfld.long 0x00 29. "RESERVED," "0,1" newline bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow" "FIFO_OVR_0,FIFO_OVR_1" newline bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" newline bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "STATEULPM4_0,STATEULPM4_1" newline bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "STATEULPM2_0,STATEULPM2_1" newline bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5" "ERRCONTROL5_0,ERRCONTROL5_1" newline bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3" "ERRCONTROL3_0,ERRCONTROL3_1" newline bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1" "ERRCONTROL1_0,ERRCONTROL1_1" newline bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4" "ERRESC4_0,ERRESC4_1" newline bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2" "ERRESC2_0,ERRESC2_1" newline bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" newline bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" newline bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" newline bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4" "ERRSOTHS4_0,ERRSOTHS4_1" newline bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2" "ERRSOTHS2_0,ERRSOTHS2_1" newline bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x314++0x03 line.long 0x00 "CAL_CSI2_TIMING_l_0,TIMING REGISTER This register shall not be =modified when .IF_EN=1 It is used to indicate the number of functional clock cycles for the Stop State monitoring" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline bitfld.long 0x00 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal" "FORCE_RX_MODE_IO1_0,FORCE_RX_MODE_IO1_1" newline bitfld.long 0x00 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "STOP_STATE_X16_IO1_0,STOP_STATE_X16_IO1_1" newline bitfld.long 0x00 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "STOP_STATE_X4_IO1_0,STOP_STATE_X4_IO1_1" newline hexmask.long.word 0x00 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring" group.long 0x394++0x03 line.long 0x00 "CAL_CSI2_TIMING_l_1,TIMING REGISTER This register shall not be =modified when .IF_EN=1 It is used to indicate the number of functional clock cycles for the Stop State monitoring" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline bitfld.long 0x00 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal" "FORCE_RX_MODE_IO1_0,FORCE_RX_MODE_IO1_1" newline bitfld.long 0x00 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "STOP_STATE_X16_IO1_0,STOP_STATE_X16_IO1_1" newline bitfld.long 0x00 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "STOP_STATE_X4_IO1_0,STOP_STATE_X4_IO1_1" newline hexmask.long.word 0x00 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring" group.long 0x318++0x03 line.long 0x00 "CAL_CSI2_VC_IRQENABLE_l_0,INTERRUPT ENABLE REGISTER - Virtual channels" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 29. "ECC_CORRECTION0_IRQ_3,ECC has been used to correct the only 1-bit error" "ECC_CORRECTION0_IRQ_3_0,ECC_CORRECTION0_IRQ_3_1" newline bitfld.long 0x00 28. "CS_IRQ_3,Check-Sum of the payload mismatch detection" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x00 27. "LE_IRQ_3,Line end sync code detection" "LE_IRQ_3_0,LE_IRQ_3_1" newline bitfld.long 0x00 26. "LS_IRQ_3,Line start sync code detection" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x00 25. "FE_IRQ_3,Frame end sync code detection" "FE_IRQ_3_0,FE_IRQ_3_1" newline bitfld.long 0x00 24. "FS_IRQ_3,Frame start sync code detection" "FS_IRQ_3_0,FS_IRQ_3_1" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 21. "ECC_CORRECTION0_IRQ_2,ECC has been used to correct the only 1-bit error" "ECC_CORRECTION0_IRQ_2_0,ECC_CORRECTION0_IRQ_2_1" newline bitfld.long 0x00 20. "CS_IRQ_2,Check-Sum of the payload mismatch detection" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x00 19. "LE_IRQ_2,Line end sync code detection" "LE_IRQ_2_0,LE_IRQ_2_1" newline bitfld.long 0x00 18. "LS_IRQ_2,Line start sync code detection" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x00 17. "FE_IRQ_2,Frame end sync code detection" "FE_IRQ_2_0,FE_IRQ_2_1" newline bitfld.long 0x00 16. "FS_IRQ_2,Frame start sync code detection" "FS_IRQ_2_0,FS_IRQ_2_1" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 13. "ECC_CORRECTION0_IRQ_1,ECC has been used to correct the only 1-bit error" "ECC_CORRECTION0_IRQ_1_0,ECC_CORRECTION0_IRQ_1_1" newline bitfld.long 0x00 12. "CS_IRQ_1,Check-Sum of the payload mismatch detection" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x00 11. "LE_IRQ_1,Line end sync code detection" "LE_IRQ_1_0,LE_IRQ_1_1" newline bitfld.long 0x00 10. "LS_IRQ_1,Line start sync code detection" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x00 9. "FE_IRQ_1,Frame end sync code detection" "FE_IRQ_1_0,FE_IRQ_1_1" newline bitfld.long 0x00 8. "FS_IRQ_1,Frame start sync code detection" "FS_IRQ_1_0,FS_IRQ_1_1" newline rbitfld.long 0x00 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 5. "ECC_CORRECTION0_IRQ_0,ECC has been used to correct the only 1-bit error" "ECC_CORRECTION0_IRQ_0_0,ECC_CORRECTION0_IRQ_0_1" newline bitfld.long 0x00 4. "CS_IRQ_0,Check-Sum of the payload mismatch detection" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x00 3. "LE_IRQ_0,Line end sync code detection" "LE_IRQ_0_0,LE_IRQ_0_1" newline bitfld.long 0x00 2. "LS_IRQ_0,Line start sync code detection" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x00 1. "FE_IRQ_0,Frame end sync code detection" "FE_IRQ_0_0,FE_IRQ_0_1" newline bitfld.long 0x00 0. "FS_IRQ_0,Frame start sync code detection" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x398++0x03 line.long 0x00 "CAL_CSI2_VC_IRQENABLE_l_1,INTERRUPT ENABLE REGISTER - Virtual channels" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 29. "ECC_CORRECTION0_IRQ_3,ECC has been used to correct the only 1-bit error" "ECC_CORRECTION0_IRQ_3_0,ECC_CORRECTION0_IRQ_3_1" newline bitfld.long 0x00 28. "CS_IRQ_3,Check-Sum of the payload mismatch detection" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x00 27. "LE_IRQ_3,Line end sync code detection" "LE_IRQ_3_0,LE_IRQ_3_1" newline bitfld.long 0x00 26. "LS_IRQ_3,Line start sync code detection" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x00 25. "FE_IRQ_3,Frame end sync code detection" "FE_IRQ_3_0,FE_IRQ_3_1" newline bitfld.long 0x00 24. "FS_IRQ_3,Frame start sync code detection" "FS_IRQ_3_0,FS_IRQ_3_1" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 21. "ECC_CORRECTION0_IRQ_2,ECC has been used to correct the only 1-bit error" "ECC_CORRECTION0_IRQ_2_0,ECC_CORRECTION0_IRQ_2_1" newline bitfld.long 0x00 20. "CS_IRQ_2,Check-Sum of the payload mismatch detection" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x00 19. "LE_IRQ_2,Line end sync code detection" "LE_IRQ_2_0,LE_IRQ_2_1" newline bitfld.long 0x00 18. "LS_IRQ_2,Line start sync code detection" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x00 17. "FE_IRQ_2,Frame end sync code detection" "FE_IRQ_2_0,FE_IRQ_2_1" newline bitfld.long 0x00 16. "FS_IRQ_2,Frame start sync code detection" "FS_IRQ_2_0,FS_IRQ_2_1" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 13. "ECC_CORRECTION0_IRQ_1,ECC has been used to correct the only 1-bit error" "ECC_CORRECTION0_IRQ_1_0,ECC_CORRECTION0_IRQ_1_1" newline bitfld.long 0x00 12. "CS_IRQ_1,Check-Sum of the payload mismatch detection" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x00 11. "LE_IRQ_1,Line end sync code detection" "LE_IRQ_1_0,LE_IRQ_1_1" newline bitfld.long 0x00 10. "LS_IRQ_1,Line start sync code detection" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x00 9. "FE_IRQ_1,Frame end sync code detection" "FE_IRQ_1_0,FE_IRQ_1_1" newline bitfld.long 0x00 8. "FS_IRQ_1,Frame start sync code detection" "FS_IRQ_1_0,FS_IRQ_1_1" newline rbitfld.long 0x00 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 5. "ECC_CORRECTION0_IRQ_0,ECC has been used to correct the only 1-bit error" "ECC_CORRECTION0_IRQ_0_0,ECC_CORRECTION0_IRQ_0_1" newline bitfld.long 0x00 4. "CS_IRQ_0,Check-Sum of the payload mismatch detection" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x00 3. "LE_IRQ_0,Line end sync code detection" "LE_IRQ_0_0,LE_IRQ_0_1" newline bitfld.long 0x00 2. "LS_IRQ_0,Line start sync code detection" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x00 1. "FE_IRQ_0,Frame end sync code detection" "FE_IRQ_0_0,FE_IRQ_0_1" newline bitfld.long 0x00 0. "FS_IRQ_0,Frame start sync code detection" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x328++0x03 line.long 0x00 "CAL_CSI2_VC_IRQSTATUS_l_0,INTERRUPT STATUS REGISTER - Virtual channels This register regroups all the events related to Context" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 29. "ECC_CORRECTION_IRQ_3,ECC has been used to do the correction of the only 1-bit error status" "ECC_CORRECTION_IRQ_3_0,ECC_CORRECTION_IRQ_3_1" newline bitfld.long 0x00 28. "CS_IRQ_3,Check-Sum mismatch status" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x00 27. "LE_IRQ_3,Line end sync code detection status" "LE_IRQ_3_0,LE_IRQ_3_1" newline bitfld.long 0x00 26. "LS_IRQ_3,Line start sync code detection status" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x00 25. "FE_IRQ_3,Frame end sync code detection status" "FE_IRQ_3_0,FE_IRQ_3_1" newline bitfld.long 0x00 24. "FS_IRQ_3,Frame start sync code detection status" "FS_IRQ_3_0,FS_IRQ_3_1" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 21. "ECC_CORRECTION_IRQ_2,ECC has been used to do the correction of the only 1-bit error status" "ECC_CORRECTION_IRQ_2_0,ECC_CORRECTION_IRQ_2_1" newline bitfld.long 0x00 20. "CS_IRQ_2,Check-Sum mismatch status" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x00 19. "LE_IRQ_2,Line end sync code detection status" "LE_IRQ_2_0,LE_IRQ_2_1" newline bitfld.long 0x00 18. "LS_IRQ_2,Line start sync code detection status" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x00 17. "FE_IRQ_2,Frame end sync code detection status" "FE_IRQ_2_0,FE_IRQ_2_1" newline bitfld.long 0x00 16. "FS_IRQ_2,Frame start sync code detection status" "FS_IRQ_2_0,FS_IRQ_2_1" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 13. "ECC_CORRECTION_IRQ_1,ECC has been used to do the correction of the only 1-bit error status" "ECC_CORRECTION_IRQ_1_0,ECC_CORRECTION_IRQ_1_1" newline bitfld.long 0x00 12. "CS_IRQ_1,Check-Sum mismatch status" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x00 11. "LE_IRQ_1,Line end sync code detection status" "LE_IRQ_1_0,LE_IRQ_1_1" newline bitfld.long 0x00 10. "LS_IRQ_1,Line start sync code detection status" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x00 9. "FE_IRQ_1,Frame end sync code detection status" "FE_IRQ_1_0,FE_IRQ_1_1" newline bitfld.long 0x00 8. "FS_IRQ_1,Frame start sync code detection status" "FS_IRQ_1_0,FS_IRQ_1_1" newline rbitfld.long 0x00 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 5. "ECC_CORRECTION_IRQ_0,ECC has been used to do the correction of the only 1-bit error status" "ECC_CORRECTION_IRQ_0_0,ECC_CORRECTION_IRQ_0_1" newline bitfld.long 0x00 4. "CS_IRQ_0,Check-Sum mismatch status" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x00 3. "LE_IRQ_0,Line end sync code detection status" "LE_IRQ_0_0,LE_IRQ_0_1" newline bitfld.long 0x00 2. "LS_IRQ_0,Line start sync code detection status" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x00 1. "FE_IRQ_0,Frame end sync code detection status" "FE_IRQ_0_0,FE_IRQ_0_1" newline bitfld.long 0x00 0. "FS_IRQ_0,Frame start sync code detection status" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x3A8++0x03 line.long 0x00 "CAL_CSI2_VC_IRQSTATUS_l_1,INTERRUPT STATUS REGISTER - Virtual channels This register regroups all the events related to Context" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 29. "ECC_CORRECTION_IRQ_3,ECC has been used to do the correction of the only 1-bit error status" "ECC_CORRECTION_IRQ_3_0,ECC_CORRECTION_IRQ_3_1" newline bitfld.long 0x00 28. "CS_IRQ_3,Check-Sum mismatch status" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x00 27. "LE_IRQ_3,Line end sync code detection status" "LE_IRQ_3_0,LE_IRQ_3_1" newline bitfld.long 0x00 26. "LS_IRQ_3,Line start sync code detection status" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x00 25. "FE_IRQ_3,Frame end sync code detection status" "FE_IRQ_3_0,FE_IRQ_3_1" newline bitfld.long 0x00 24. "FS_IRQ_3,Frame start sync code detection status" "FS_IRQ_3_0,FS_IRQ_3_1" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 21. "ECC_CORRECTION_IRQ_2,ECC has been used to do the correction of the only 1-bit error status" "ECC_CORRECTION_IRQ_2_0,ECC_CORRECTION_IRQ_2_1" newline bitfld.long 0x00 20. "CS_IRQ_2,Check-Sum mismatch status" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x00 19. "LE_IRQ_2,Line end sync code detection status" "LE_IRQ_2_0,LE_IRQ_2_1" newline bitfld.long 0x00 18. "LS_IRQ_2,Line start sync code detection status" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x00 17. "FE_IRQ_2,Frame end sync code detection status" "FE_IRQ_2_0,FE_IRQ_2_1" newline bitfld.long 0x00 16. "FS_IRQ_2,Frame start sync code detection status" "FS_IRQ_2_0,FS_IRQ_2_1" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 13. "ECC_CORRECTION_IRQ_1,ECC has been used to do the correction of the only 1-bit error status" "ECC_CORRECTION_IRQ_1_0,ECC_CORRECTION_IRQ_1_1" newline bitfld.long 0x00 12. "CS_IRQ_1,Check-Sum mismatch status" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x00 11. "LE_IRQ_1,Line end sync code detection status" "LE_IRQ_1_0,LE_IRQ_1_1" newline bitfld.long 0x00 10. "LS_IRQ_1,Line start sync code detection status" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x00 9. "FE_IRQ_1,Frame end sync code detection status" "FE_IRQ_1_0,FE_IRQ_1_1" newline bitfld.long 0x00 8. "FS_IRQ_1,Frame start sync code detection status" "FS_IRQ_1_0,FS_IRQ_1_1" newline rbitfld.long 0x00 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 5. "ECC_CORRECTION_IRQ_0,ECC has been used to do the correction of the only 1-bit error status" "ECC_CORRECTION_IRQ_0_0,ECC_CORRECTION_IRQ_0_1" newline bitfld.long 0x00 4. "CS_IRQ_0,Check-Sum mismatch status" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x00 3. "LE_IRQ_0,Line end sync code detection status" "LE_IRQ_0_0,LE_IRQ_0_1" newline bitfld.long 0x00 2. "LS_IRQ_0,Line start sync code detection status" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x00 1. "FE_IRQ_0,Frame end sync code detection status" "FE_IRQ_0_0,FE_IRQ_0_1" newline bitfld.long 0x00 0. "FS_IRQ_0,Frame start sync code detection status" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x330++0x03 line.long 0x00 "CAL_CSI2_CTX0_l_0,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x3B0++0x03 line.long 0x00 "CAL_CSI2_CTX0_l_1,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x334++0x03 line.long 0x00 "CAL_CSI2_CTX1_l_0,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x3B4++0x03 line.long 0x00 "CAL_CSI2_CTX1_l_1,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x338++0x03 line.long 0x00 "CAL_CSI2_CTX2_l_0,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x3B8++0x03 line.long 0x00 "CAL_CSI2_CTX2_l_1,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x33C++0x03 line.long 0x00 "CAL_CSI2_CTX3_l_0,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x3BC++0x03 line.long 0x00 "CAL_CSI2_CTX3_l_1,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x340++0x03 line.long 0x00 "CAL_CSI2_CTX4_l_0,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x3C0++0x03 line.long 0x00 "CAL_CSI2_CTX4_l_1,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x344++0x03 line.long 0x00 "CAL_CSI2_CTX5_l_0,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x3C4++0x03 line.long 0x00 "CAL_CSI2_CTX5_l_1,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x348++0x03 line.long 0x00 "CAL_CSI2_CTX6_l_0,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x3C8++0x03 line.long 0x00 "CAL_CSI2_CTX6_l_1,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x34C++0x03 line.long 0x00 "CAL_CSI2_CTX7_l_0,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x3CC++0x03 line.long 0x00 "CAL_CSI2_CTX7_l_1,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" rgroup.long 0x350++0x03 line.long 0x00 "CAL_CSI2_STATUS0_l_0,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x3D0++0x03 line.long 0x00 "CAL_CSI2_STATUS0_l_1,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x354++0x03 line.long 0x00 "CAL_CSI2_STATUS1_l_0,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x3D4++0x03 line.long 0x00 "CAL_CSI2_STATUS1_l_1,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x358++0x03 line.long 0x00 "CAL_CSI2_STATUS2_l_0,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x3D8++0x03 line.long 0x00 "CAL_CSI2_STATUS2_l_1,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x35C++0x03 line.long 0x00 "CAL_CSI2_STATUS3_l_0,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x3DC++0x03 line.long 0x00 "CAL_CSI2_STATUS3_l_1,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x360++0x03 line.long 0x00 "CAL_CSI2_STATUS4_l_0,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x3E0++0x03 line.long 0x00 "CAL_CSI2_STATUS4_l_1,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x364++0x03 line.long 0x00 "CAL_CSI2_STATUS5_l_0,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x3E4++0x03 line.long 0x00 "CAL_CSI2_STATUS5_l_1,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x368++0x03 line.long 0x00 "CAL_CSI2_STATUS6_l_0,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x3E8++0x03 line.long 0x00 "CAL_CSI2_STATUS6_l_1,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x36C++0x03 line.long 0x00 "CAL_CSI2_STATUS7_l_0,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x3EC++0x03 line.long 0x00 "CAL_CSI2_STATUS7_l_1,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" width 0x0B tree.end tree "CAL_B" base ad:0x52013000 rgroup.long 0x00++0x07 line.long 0x00 "CAL_HL_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "CAL_HL_HWINFO,Information about the IP module's hardware configuration. i.e" bitfld.long 0x04 30.--31. "NPPI_CONTEXTS1,Number of contexts for PPI interface #0" "NPPI_CONTEXTS1_0_r,NPPI_CONTEXTS1_1_r,NPPI_CONTEXTS1_2_r,NPPI_CONTEXTS1_3_r" newline bitfld.long 0x04 28.--29. "NPPI_CONTEXTS0,Number of contexts for PPI interface #0" "NPPI_CONTEXTS0_0_r,NPPI_CONTEXTS0_1_r,NPPI_CONTEXTS0_2_r,NPPI_CONTEXTS0_3_r" newline bitfld.long 0x04 23.--27. "NCPORT,Number of supported CPORTs (including CPORT #0) minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 19.--22. "VFIFO,Video port FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 13.--18. "WCTX,Number of implemented DMA write contexts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--12. "PCTX,Number of implemented pixel processing contexts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 4.--7. "RFIFO,Read FIFO size 2^RFIFO words of 16 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. "WFIFO,Write FIFO size 2^WFIFO words of 16 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x03 line.long 0x00 "CAL_HL_SYSCONFIG,Clock management configuration" hexmask.long 0x00 4.--31. 1. "RESERVED," newline bitfld.long 0x00 2.--3. "IDLEMODE,IDLE protocol configuration" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline rbitfld.long 0x00 1. "RESERVED," "0,1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_r" group.long 0x1C++0x07 line.long 0x00 "CAL_HL_IRQ_EOI,End Of Interrupt number specification" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "CAL_HL_IRQSTATUS_RAW_j_0,Per-event raw interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x04 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x04 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x04 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x04 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x04 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x04 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x04 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x04 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x04 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x04 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x04 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x04 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x04 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x04 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x04 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x04 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x04 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x04 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x04 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x04 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x04 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x04 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x04 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x04 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x30++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_1,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x40++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_2,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x50++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_3,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x60++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_4,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x70++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_5,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x80++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_6,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x90++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_7,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0xA0++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_8,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0xB0++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_9,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x24++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_0,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x34++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_1,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x44++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_2,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x54++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_3,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x64++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_4,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x74++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_5,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x84++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_6,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x94++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_7,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0xA4++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_8,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0xB4++0x03 line.long 0x00 "CAL_HL_IRQSTATUS_j_9,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x28++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_0,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x38++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_1,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x48++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_2,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x58++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_3,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x68++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_4,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x78++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_5,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x88++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_6,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x98++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_7,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0xA8++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_8,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0xB8++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_9,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x2C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_0,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x3C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_1,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x4C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_2,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x5C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_3,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x6C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_4,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x7C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_5,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x8C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_6,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0x9C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_7,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0xAC++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_8,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" group.long 0xBC++0x13 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_9,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details" "IRQ31_0_r,IRQ31_1_r" newline bitfld.long 0x00 30. "IRQ30,Check spec for details" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details" "IRQ29_0_r,IRQ29_1_r" newline bitfld.long 0x00 28. "IRQ28,Check spec for details" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details" "IRQ27_0_r,IRQ27_1_r" newline bitfld.long 0x00 26. "IRQ26,Check spec for details" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details" "IRQ23_0_r,IRQ23_1_r" newline bitfld.long 0x00 22. "IRQ22,Check spec for details" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details" "IRQ21_0_r,IRQ21_1_r" newline bitfld.long 0x00 20. "IRQ20,Check spec for details" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details" "IRQ19_0_r,IRQ19_1_r" newline bitfld.long 0x00 18. "IRQ18,Check spec for details" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details" "IRQ17_0_r,IRQ17_1_r" newline bitfld.long 0x00 16. "IRQ16,Check spec for details" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details" "IRQ15_0_r,IRQ15_1_r" newline bitfld.long 0x00 14. "IRQ14,Check spec for details" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details" "IRQ13_0_r,IRQ13_1_r" newline bitfld.long 0x00 12. "IRQ12,Check spec for details" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details" "IRQ9_0_r,IRQ9_1_r" newline bitfld.long 0x00 8. "IRQ8,Check spec for details" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details" "IRQ7_0_r,IRQ7_1_r" newline bitfld.long 0x00 6. "IRQ6,Check spec for details" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details" "IRQ5_0_r,IRQ5_1_r" newline bitfld.long 0x00 4. "IRQ4,Check spec for details" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details" "IRQ3_0_r,IRQ3_1_r" newline bitfld.long 0x00 2. "IRQ2,Check spec for details" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details" "IRQ1_0_r,IRQ1_1_r" newline bitfld.long 0x00 0. "IRQ0,Check spec for details" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_PIX_PROC_i_0,Pixel processing control" hexmask.long.byte 0x04 24.--31. 1. "RESERVED," newline bitfld.long 0x04 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 16.--18. "PACK,Control pixel packing" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" newline bitfld.long 0x04 11.--15. "DPCME,DPCM encoder" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" newline rbitfld.long 0x04 10. "RESERVED," "0,1" newline bitfld.long 0x04 5.--9. "DPCMD,DPCM Decoder" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 1.--4. "EXTRACT,Control pixel extraction from the byte stream" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" newline bitfld.long 0x04 0. "EN,Enable the pixel processing context" "EN_0,EN_1" line.long 0x08 "CAL_PIX_PROC_i_1,Pixel processing control" hexmask.long.byte 0x08 24.--31. 1. "RESERVED," newline bitfld.long 0x08 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 16.--18. "PACK,Control pixel packing" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" newline bitfld.long 0x08 11.--15. "DPCME,DPCM encoder" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" newline rbitfld.long 0x08 10. "RESERVED," "0,1" newline bitfld.long 0x08 5.--9. "DPCMD,DPCM Decoder" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x08 1.--4. "EXTRACT,Control pixel extraction from the byte stream" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" newline bitfld.long 0x08 0. "EN,Enable the pixel processing context" "EN_0,EN_1" line.long 0x0C "CAL_PIX_PROC_i_2,Pixel processing control" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," newline bitfld.long 0x0C 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 16.--18. "PACK,Control pixel packing" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" newline bitfld.long 0x0C 11.--15. "DPCME,DPCM encoder" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" newline rbitfld.long 0x0C 10. "RESERVED," "0,1" newline bitfld.long 0x0C 5.--9. "DPCMD,DPCM Decoder" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x0C 1.--4. "EXTRACT,Control pixel extraction from the byte stream" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" newline bitfld.long 0x0C 0. "EN,Enable the pixel processing context" "EN_0,EN_1" line.long 0x10 "CAL_PIX_PROC_i_3,Pixel processing control" hexmask.long.byte 0x10 24.--31. 1. "RESERVED," newline bitfld.long 0x10 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x10 16.--18. "PACK,Control pixel packing" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" newline bitfld.long 0x10 11.--15. "DPCME,DPCM encoder" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" newline rbitfld.long 0x10 10. "RESERVED," "0,1" newline bitfld.long 0x10 5.--9. "DPCMD,DPCM Decoder" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x10 1.--4. "EXTRACT,Control pixel extraction from the byte stream" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" newline bitfld.long 0x10 0. "EN,Enable the pixel processing context" "EN_0,EN_1" group.long 0x100++0x0B line.long 0x00 "CAL_CTRL,Global control register" hexmask.long.byte 0x00 24.--31. 1. "MFLAGH,refer to real time traffic section of the spec" newline rbitfld.long 0x00 23. "RESERVED," "0,1" newline bitfld.long 0x00 22. "RD_DMA_STALL,Controls if the pixel stream from the RD DMA's FIFO to the internal pipeline shall be stalled when MFlag/=0" "RD_DMA_STALL_0,RD_DMA_STALL_1" newline bitfld.long 0x00 21. "PWRSCPCLK,Controls autogating of the PWRSCP clock" "PWRSCPCLK_0,PWRSCPCLK_1" newline hexmask.long.byte 0x00 13.--20. 1. "MFLAGL,refer to real time traffic section of the spec" newline bitfld.long 0x00 7.--12. "LL_FORCE_STATE,Forces the state of the CSI-3 low level protocol state machine" "the next OCPI transaction for this CPORT will..,the next OCPI transaction for this CPORT will..,?..." newline bitfld.long 0x00 5.--6. "BURSTSIZE,Maximum allowed burst size for the write DMA" "BURSTSIZE_0,BURSTSIZE_1,BURSTSIZE_2,BURSTSIZE_3" newline bitfld.long 0x00 1.--4. "TAGCNT,Maximum number of outstanding OCP transactions = TAGCNT+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "POSTED_WRITES," "POSTED_WRITES_0,POSTED_WRITES_1" line.long 0x04 "CAL_CTRL1,CAL global control register" hexmask.long 0x04 6.--31. 1. "RESERVED," newline bitfld.long 0x04 4.--5. "INTERLEAVE23,Controls stream interleaving Context #2 and #3" "INTERLEAVE23_0,INTERLEAVE23_1,INTERLEAVE23_2,INTERLEAVE23_3" newline bitfld.long 0x04 2.--3. "INTERLEAVE01,Controls stream interleaving Context #0 and #1" "INTERLEAVE01_0,INTERLEAVE01_1,INTERLEAVE01_2,INTERLEAVE01_3" newline bitfld.long 0x04 0.--1. "PPI_GROUPING,Controls PPI grouping" "PPI_GROUPING_0,PPI_GROUPING_1,PPI_GROUPING_2,PPI_GROUPING_3" line.long 0x08 "CAL_LINE_NUMBER_EVT,Controls generation of the line number event" rbitfld.long 0x08 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x08 16.--29. 1. "LINE," newline hexmask.long.word 0x08 5.--15. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "CPORT,CPort ID to monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x120++0x07 line.long 0x00 "CAL_VPORT_CTRL1,Video port control register" bitfld.long 0x00 31. "WIDTH,Video port width" "WIDTH_0,WIDTH_1" newline bitfld.long 0x00 25.--30. "YBLK,Vertical blanking = YBLK lines Valid range : 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 17.--24. 1. "XBLK,Horizontal blanking = 8*XBLK cycles Valid range = 0..2040 cycles" newline hexmask.long.tbyte 0x00 0.--16. 1. "PCLK,Video port pixel clock = FCLK * PCLK / 2^16 Valid range: 0" line.long 0x04 "CAL_VPORT_CTRL2,Video port control register" hexmask.long.word 0x04 18.--31. 1. "RDY_THR,Data shall be send to the video port after frame start only when (RDY_THR+1)*4 pixels are ready and the 4 PCLK cycles (require before each frame start) have been sent" newline bitfld.long 0x04 17. "FSM_RESET,Forces a reset of the video port FSM" "FSM_RESET_0_w,FSM_RESET_1_w" newline bitfld.long 0x04 16. "FS_RESETS,Controls the behavior of the timing generator when a data tagged as PIX_DAT_FS is received" "FS_RESETS_0,FS_RESETS_1" newline bitfld.long 0x04 15. "FREERUNNING,Controls PCLK generation during IDLE" "FREERUNNING_0,FREERUNNING_1" newline hexmask.long.word 0x04 5.--14. 1. "RESERVED," newline bitfld.long 0x04 0.--4. "CPORT,Cport ID Valid range=0..(CAL_HL_HWINFO.NCPORT-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x130++0x07 line.long 0x00 "CAL_BYS_CTRL1,BYS port control register" bitfld.long 0x00 31. "BYSINEN,Enable/disable the BYS input port Note: the BYS output port is disabled by setting PCLK=0" "BYSINEN_0,BYSINEN_1" newline bitfld.long 0x00 25.--30. "YBLK,Vertical blanking = YBLK lines Valid range : 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 17.--24. 1. "XBLK,Horizontal blanking = 8*XBLK cycles Valid range = 0..2040 cycles" newline hexmask.long.tbyte 0x00 0.--16. 1. "PCLK,BYSout port pixel clock = FCLK * PCLK / 2^16 Valid range: 0" line.long 0x04 "CAL_BYS_CTRL2,BYS port control register" hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED," newline bitfld.long 0x04 11. "FREERUNNING,Controls PCLK generation when the BYSout state machine is in the IDLE state" "FREERUNNING_0,FREERUNNING_1" newline bitfld.long 0x04 10. "DUPLICATEDDATA,Control if data sent to the BYS output port should also be send to the DPCM encoder" "DUPLICATEDDATA_0,DUPLICATEDDATA_1" newline bitfld.long 0x04 5.--9. "CPORTOUT,BYS output port processes data received with the CPORT ID defined in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. "CPORTIN,Cport ID used for data received from the BYSin port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x140++0x17 line.long 0x00 "CAL_RD_DMA_CTRL,Read DMA control register" hexmask.long.tbyte 0x00 15.--31. 1. "PCLK,Controls the data rate at which data is read from the read DMA FIFO and sent to the internal processing pipeline" newline bitfld.long 0x00 11.--14. "OCP_TAG_CNT,Maximum allowed number of outstanding OCP read requests minus 1 (i.e. 0xF meand up to 16 outstanding requests)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 2.--10. 1. "BW_LIMITER,Defines a minimum cycle count between to consecutive read requests issued by the RD DMA" newline bitfld.long 0x00 1. "INIT,Enable reading of DPCM decoder initialization data from SDRAM" "INIT_0,INIT_1" newline bitfld.long 0x00 0. "GO,Start data read from memory" "GO_0_r,GO_1_r" line.long 0x04 "CAL_RD_DMA_PIX_ADDR,Byte address of the top left corner of the buffer to read in system memory" hexmask.long 0x04 3.--31. 1. "ADDR,Address in words of 8 bytes" newline rbitfld.long 0x04 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x08 "CAL_RD_DMA_PIX_OFST,Byte offset between two consecutive line starts Shall be 16 byte aligned for YUV420" hexmask.long 0x08 4.--31. 1. "OFST,Offset in words of 16 bytes" newline rbitfld.long 0x08 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "CAL_RD_DMA_XSIZE,Number of bytes to read per line" hexmask.long.word 0x0C 19.--31. 1. "XSIZE,Words of 64-bits to read per line" newline hexmask.long.tbyte 0x0C 0.--18. 1. "RESERVED," line.long 0x10 "CAL_RD_DMA_YSIZE,Number of lines to" rbitfld.long 0x10 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x10 16.--29. 1. "YSIZE," newline hexmask.long.word 0x10 0.--15. 1. "RESERVED," line.long 0x14 "CAL_RD_DMA_INIT_ADDR,Read address" hexmask.long 0x14 3.--31. 1. "ADDR,Address in words of 8 bytes" newline rbitfld.long 0x14 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x168++0x07 line.long 0x00 "CAL_RD_DMA_INIT_OFST,Byte offset between two consecutive line starts" hexmask.long 0x00 3.--31. 1. "OFST,Offset in words of 8 bytes" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x04 "CAL_RD_DMA_CTRL2,Read DMA control register" rbitfld.long 0x04 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x04 16.--29. 1. "CIRC_SIZE,Circular buffer size minus one" newline hexmask.long.word 0x04 7.--15. 1. "RESERVED," newline bitfld.long 0x04 6. "BYSOUT_LE_WAIT,Controls the behavior of the RD DMA when the line end is reached" "BYSOUT_LE_WAIT_0,BYSOUT_LE_WAIT_1" newline bitfld.long 0x04 4.--5. "RD_PATTERN,Data read pattern" "RD_PATTERN_0,RD_PATTERN_1,RD_PATTERN_2,RD_PATTERN_3" newline bitfld.long 0x04 3. "ICM_CSTART,Enables monitoring of the ICM_CSTART signal" "ICM_CSTART_0,ICM_CSTART_1" newline bitfld.long 0x04 0.--2. "CIRC_MODE,Circular mode control" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3,CIRC_MODE_4,CIRC_MODE_5,?,?" group.long 0x200++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_0,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" newline rbitfld.long 0x00 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal" "ICM_PSTART_0,ICM_PSTART_1" newline bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x210++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_1,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" newline rbitfld.long 0x00 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal" "ICM_PSTART_0,ICM_PSTART_1" newline bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x220++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_2,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" newline rbitfld.long 0x00 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal" "ICM_PSTART_0,ICM_PSTART_1" newline bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x230++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_3,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" newline rbitfld.long 0x00 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal" "ICM_PSTART_0,ICM_PSTART_1" newline bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x240++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_4,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" newline rbitfld.long 0x00 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal" "ICM_PSTART_0,ICM_PSTART_1" newline bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x250++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_5,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" newline rbitfld.long 0x00 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal" "ICM_PSTART_0,ICM_PSTART_1" newline bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x260++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_6,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" newline rbitfld.long 0x00 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal" "ICM_PSTART_0,ICM_PSTART_1" newline bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x270++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_7,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" newline rbitfld.long 0x00 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal" "ICM_PSTART_0,ICM_PSTART_1" newline bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x204++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_0,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x214++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_1,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x224++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_2,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x234++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_3,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x244++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_4,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x254++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_5,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x264++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_6,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x274++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_7,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x208++0x03 line.long 0x00 "CAL_WR_DMA_OFST_k_0,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" newline bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x218++0x03 line.long 0x00 "CAL_WR_DMA_OFST_k_1,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" newline bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x228++0x03 line.long 0x00 "CAL_WR_DMA_OFST_k_2,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" newline bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x238++0x03 line.long 0x00 "CAL_WR_DMA_OFST_k_3,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" newline bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x248++0x03 line.long 0x00 "CAL_WR_DMA_OFST_k_4,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" newline bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x258++0x03 line.long 0x00 "CAL_WR_DMA_OFST_k_5,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" newline bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x268++0x03 line.long 0x00 "CAL_WR_DMA_OFST_k_6,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" newline bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x278++0x03 line.long 0x00 "CAL_WR_DMA_OFST_k_7,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" newline bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20C++0x03 line.long 0x00 "CAL_WR_DMA_XSIZE_k_0,Defines the size of a line written to memory" hexmask.long.word 0x00 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" newline rbitfld.long 0x00 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x21C++0x03 line.long 0x00 "CAL_WR_DMA_XSIZE_k_1,Defines the size of a line written to memory" hexmask.long.word 0x00 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" newline rbitfld.long 0x00 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x22C++0x03 line.long 0x00 "CAL_WR_DMA_XSIZE_k_2,Defines the size of a line written to memory" hexmask.long.word 0x00 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" newline rbitfld.long 0x00 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x23C++0x03 line.long 0x00 "CAL_WR_DMA_XSIZE_k_3,Defines the size of a line written to memory" hexmask.long.word 0x00 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" newline rbitfld.long 0x00 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x24C++0x03 line.long 0x00 "CAL_WR_DMA_XSIZE_k_4,Defines the size of a line written to memory" hexmask.long.word 0x00 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" newline rbitfld.long 0x00 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x25C++0x03 line.long 0x00 "CAL_WR_DMA_XSIZE_k_5,Defines the size of a line written to memory" hexmask.long.word 0x00 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" newline rbitfld.long 0x00 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x26C++0x03 line.long 0x00 "CAL_WR_DMA_XSIZE_k_6,Defines the size of a line written to memory" hexmask.long.word 0x00 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" newline rbitfld.long 0x00 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x27C++0x03 line.long 0x00 "CAL_WR_DMA_XSIZE_k_7,Defines the size of a line written to memory" hexmask.long.word 0x00 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" newline rbitfld.long 0x00 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" newline rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.long 0x300++0x03 line.long 0x00 "CAL_CSI2_PPI_CTRL_l_0,Controls the low level CSI-2 protocol interface (PPI)" hexmask.long 0x00 4.--31. 1. "RESERVED," newline bitfld.long 0x00 3. "FRAME,Set the modality in which IF_EN works" "FRAME_0,FRAME_1" newline bitfld.long 0x00 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids)" "ECC_EN_0,ECC_EN_1" newline rbitfld.long 0x00 1. "RESERVED," "0,1" newline bitfld.long 0x00 0. "IF_EN,Enables the physical interface to the module" "IF_EN_0,IF_EN_1" group.long 0x380++0x03 line.long 0x00 "CAL_CSI2_PPI_CTRL_l_1,Controls the low level CSI-2 protocol interface (PPI)" hexmask.long 0x00 4.--31. 1. "RESERVED," newline bitfld.long 0x00 3. "FRAME,Set the modality in which IF_EN works" "FRAME_0,FRAME_1" newline bitfld.long 0x00 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids)" "ECC_EN_0,ECC_EN_1" newline rbitfld.long 0x00 1. "RESERVED," "0,1" newline bitfld.long 0x00 0. "IF_EN,Enables the physical interface to the module" "IF_EN_0,IF_EN_1" group.long 0x304++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_CFG_l_0,COMPLEXIO CONFIGURATION REGISTER This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in addition to the.." rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 30. "RESET_CTRL,Controls the reset of the complex IO" "RESET_CTRL_0,RESET_CTRL_1" newline rbitfld.long 0x00 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io" "RESET_DONE_0_r,RESET_DONE_1_r" newline bitfld.long 0x00 27.--28. "PWR_CMD,Command for power control of the complex io" "PWR_CMD_0,PWR_CMD_1,PWR_CMD_2,?" newline rbitfld.long 0x00 25.--26. "PWR_STATUS,Status of the power control of the complex io" "PWR_STATUS_0_r,PWR_STATUS_1_r,PWR_STATUS_2_r,?" newline bitfld.long 0x00 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO" "PWR_AUTO_0,PWR_AUTO_1" newline rbitfld.long 0x00 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19. "DATA4_POL,+/- differential pin order of DATA lane 4" "DATA4_POL_0,DATA4_POL_1" newline bitfld.long 0x00 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4" "DATA4_POSITION_0,DATA4_POSITION_1,DATA4_POSITION_2,DATA4_POSITION_3,DATA4_POSITION_4,DATA4_POSITION_5,?,?" newline bitfld.long 0x00 15. "DATA3_POL,+/- differential pin order of DATA lane 3" "DATA3_POL_0,DATA3_POL_1" newline bitfld.long 0x00 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3" "DATA3_POSITION_0,DATA3_POSITION_1,DATA3_POSITION_2,DATA3_POSITION_3,DATA3_POSITION_4,DATA3_POSITION_5,?,?" newline bitfld.long 0x00 11. "DATA2_POL,+/- differential pin order of DATA lane 2" "DATA2_POL_0,DATA2_POL_1" newline bitfld.long 0x00 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2" "DATA2_POSITION_0,DATA2_POSITION_1,DATA2_POSITION_2,DATA2_POSITION_3,DATA2_POSITION_4,DATA2_POSITION_5,?,?" newline bitfld.long 0x00 7. "DATA1_POL,+/- differential pin order of DATA lane 1" "DATA1_POL_0,DATA1_POL_1" newline bitfld.long 0x00 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1" "?,DATA1_POSITION_1,DATA1_POSITION_2,DATA1_POSITION_3,DATA1_POSITION_4,DATA1_POSITION_5,?,?" newline bitfld.long 0x00 3. "CLOCK_POL,+/- differential pin order of CLOCK lane" "CLOCK_POL_0,CLOCK_POL_1" newline bitfld.long 0x00 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane" "?,CLOCK_POSITION_1,CLOCK_POSITION_2,CLOCK_POSITION_3,CLOCK_POSITION_4,CLOCK_POSITION_5,?,?" group.long 0x384++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_CFG_l_1,COMPLEXIO CONFIGURATION REGISTER This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in addition to the.." rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 30. "RESET_CTRL,Controls the reset of the complex IO" "RESET_CTRL_0,RESET_CTRL_1" newline rbitfld.long 0x00 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io" "RESET_DONE_0_r,RESET_DONE_1_r" newline bitfld.long 0x00 27.--28. "PWR_CMD,Command for power control of the complex io" "PWR_CMD_0,PWR_CMD_1,PWR_CMD_2,?" newline rbitfld.long 0x00 25.--26. "PWR_STATUS,Status of the power control of the complex io" "PWR_STATUS_0_r,PWR_STATUS_1_r,PWR_STATUS_2_r,?" newline bitfld.long 0x00 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO" "PWR_AUTO_0,PWR_AUTO_1" newline rbitfld.long 0x00 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19. "DATA4_POL,+/- differential pin order of DATA lane 4" "DATA4_POL_0,DATA4_POL_1" newline bitfld.long 0x00 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4" "DATA4_POSITION_0,DATA4_POSITION_1,DATA4_POSITION_2,DATA4_POSITION_3,DATA4_POSITION_4,DATA4_POSITION_5,?,?" newline bitfld.long 0x00 15. "DATA3_POL,+/- differential pin order of DATA lane 3" "DATA3_POL_0,DATA3_POL_1" newline bitfld.long 0x00 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3" "DATA3_POSITION_0,DATA3_POSITION_1,DATA3_POSITION_2,DATA3_POSITION_3,DATA3_POSITION_4,DATA3_POSITION_5,?,?" newline bitfld.long 0x00 11. "DATA2_POL,+/- differential pin order of DATA lane 2" "DATA2_POL_0,DATA2_POL_1" newline bitfld.long 0x00 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2" "DATA2_POSITION_0,DATA2_POSITION_1,DATA2_POSITION_2,DATA2_POSITION_3,DATA2_POSITION_4,DATA2_POSITION_5,?,?" newline bitfld.long 0x00 7. "DATA1_POL,+/- differential pin order of DATA lane 1" "DATA1_POL_0,DATA1_POL_1" newline bitfld.long 0x00 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1" "?,DATA1_POSITION_1,DATA1_POSITION_2,DATA1_POSITION_3,DATA1_POSITION_4,DATA1_POSITION_5,?,?" newline bitfld.long 0x00 3. "CLOCK_POL,+/- differential pin order of CLOCK lane" "CLOCK_POL_0,CLOCK_POL_1" newline bitfld.long 0x00 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane" "?,CLOCK_POSITION_1,CLOCK_POSITION_2,CLOCK_POSITION_3,CLOCK_POSITION_4,CLOCK_POSITION_5,?,?" group.long 0x308++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQSTATUS_l_0,INTERRUPT STATUS REGISTER - All errors from complex IO #1" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" newline rbitfld.long 0x00 29. "RESERVED," "0,1" newline bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow" "FIFO_OVR_0,FIFO_OVR_1" newline bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" newline bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "STATEULPM4_0,STATEULPM4_1" newline bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "STATEULPM2_0,STATEULPM2_1" newline bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5" "ERRCONTROL5_0,ERRCONTROL5_1" newline bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3" "ERRCONTROL3_0,ERRCONTROL3_1" newline bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1" "ERRCONTROL1_0,ERRCONTROL1_1" newline bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4" "ERRESC4_0,ERRESC4_1" newline bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2" "ERRESC2_0,ERRESC2_1" newline bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" newline bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" newline bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" newline bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4" "ERRSOTHS4_0,ERRSOTHS4_1" newline bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2" "ERRSOTHS2_0,ERRSOTHS2_1" newline bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x388++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQSTATUS_l_1,INTERRUPT STATUS REGISTER - All errors from complex IO #1" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" newline rbitfld.long 0x00 29. "RESERVED," "0,1" newline bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow" "FIFO_OVR_0,FIFO_OVR_1" newline bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" newline bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "STATEULPM4_0,STATEULPM4_1" newline bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "STATEULPM2_0,STATEULPM2_1" newline bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5" "ERRCONTROL5_0,ERRCONTROL5_1" newline bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3" "ERRCONTROL3_0,ERRCONTROL3_1" newline bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1" "ERRCONTROL1_0,ERRCONTROL1_1" newline bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4" "ERRESC4_0,ERRESC4_1" newline bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2" "ERRESC2_0,ERRESC2_1" newline bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" newline bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" newline bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" newline bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4" "ERRSOTHS4_0,ERRSOTHS4_1" newline bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2" "ERRSOTHS2_0,ERRSOTHS2_1" newline bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1" "ERRSOTHS1_0,ERRSOTHS1_1" rgroup.long 0x30C++0x03 line.long 0x00 "CAL_CSI2_SHORT_PACKET_l_0,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads returns 0" newline hexmask.long.tbyte 0x00 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD" rgroup.long 0x38C++0x03 line.long 0x00 "CAL_CSI2_SHORT_PACKET_l_1,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads returns 0" newline hexmask.long.tbyte 0x00 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD" group.long 0x310++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQENABLE_l_0,INTERRUPT ENABLE REGISTER - All errors from complex IO #1" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" newline rbitfld.long 0x00 29. "RESERVED," "0,1" newline bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow" "FIFO_OVR_0,FIFO_OVR_1" newline bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" newline bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "STATEULPM4_0,STATEULPM4_1" newline bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "STATEULPM2_0,STATEULPM2_1" newline bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5" "ERRCONTROL5_0,ERRCONTROL5_1" newline bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3" "ERRCONTROL3_0,ERRCONTROL3_1" newline bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1" "ERRCONTROL1_0,ERRCONTROL1_1" newline bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4" "ERRESC4_0,ERRESC4_1" newline bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2" "ERRESC2_0,ERRESC2_1" newline bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" newline bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" newline bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" newline bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4" "ERRSOTHS4_0,ERRSOTHS4_1" newline bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2" "ERRSOTHS2_0,ERRSOTHS2_1" newline bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x390++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQENABLE_l_1,INTERRUPT ENABLE REGISTER - All errors from complex IO #1" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" newline rbitfld.long 0x00 29. "RESERVED," "0,1" newline bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow" "FIFO_OVR_0,FIFO_OVR_1" newline bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" newline bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "STATEULPM4_0,STATEULPM4_1" newline bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "STATEULPM2_0,STATEULPM2_1" newline bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5" "ERRCONTROL5_0,ERRCONTROL5_1" newline bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3" "ERRCONTROL3_0,ERRCONTROL3_1" newline bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1" "ERRCONTROL1_0,ERRCONTROL1_1" newline bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4" "ERRESC4_0,ERRESC4_1" newline bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2" "ERRESC2_0,ERRESC2_1" newline bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" newline bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" newline bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" newline bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4" "ERRSOTHS4_0,ERRSOTHS4_1" newline bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2" "ERRSOTHS2_0,ERRSOTHS2_1" newline bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x314++0x03 line.long 0x00 "CAL_CSI2_TIMING_l_0,TIMING REGISTER This register shall not be =modified when .IF_EN=1 It is used to indicate the number of functional clock cycles for the Stop State monitoring" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline bitfld.long 0x00 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal" "FORCE_RX_MODE_IO1_0,FORCE_RX_MODE_IO1_1" newline bitfld.long 0x00 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "STOP_STATE_X16_IO1_0,STOP_STATE_X16_IO1_1" newline bitfld.long 0x00 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "STOP_STATE_X4_IO1_0,STOP_STATE_X4_IO1_1" newline hexmask.long.word 0x00 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring" group.long 0x394++0x03 line.long 0x00 "CAL_CSI2_TIMING_l_1,TIMING REGISTER This register shall not be =modified when .IF_EN=1 It is used to indicate the number of functional clock cycles for the Stop State monitoring" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline bitfld.long 0x00 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal" "FORCE_RX_MODE_IO1_0,FORCE_RX_MODE_IO1_1" newline bitfld.long 0x00 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "STOP_STATE_X16_IO1_0,STOP_STATE_X16_IO1_1" newline bitfld.long 0x00 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "STOP_STATE_X4_IO1_0,STOP_STATE_X4_IO1_1" newline hexmask.long.word 0x00 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring" group.long 0x318++0x03 line.long 0x00 "CAL_CSI2_VC_IRQENABLE_l_0,INTERRUPT ENABLE REGISTER - Virtual channels" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 29. "ECC_CORRECTION0_IRQ_3,ECC has been used to correct the only 1-bit error" "ECC_CORRECTION0_IRQ_3_0,ECC_CORRECTION0_IRQ_3_1" newline bitfld.long 0x00 28. "CS_IRQ_3,Check-Sum of the payload mismatch detection" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x00 27. "LE_IRQ_3,Line end sync code detection" "LE_IRQ_3_0,LE_IRQ_3_1" newline bitfld.long 0x00 26. "LS_IRQ_3,Line start sync code detection" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x00 25. "FE_IRQ_3,Frame end sync code detection" "FE_IRQ_3_0,FE_IRQ_3_1" newline bitfld.long 0x00 24. "FS_IRQ_3,Frame start sync code detection" "FS_IRQ_3_0,FS_IRQ_3_1" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 21. "ECC_CORRECTION0_IRQ_2,ECC has been used to correct the only 1-bit error" "ECC_CORRECTION0_IRQ_2_0,ECC_CORRECTION0_IRQ_2_1" newline bitfld.long 0x00 20. "CS_IRQ_2,Check-Sum of the payload mismatch detection" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x00 19. "LE_IRQ_2,Line end sync code detection" "LE_IRQ_2_0,LE_IRQ_2_1" newline bitfld.long 0x00 18. "LS_IRQ_2,Line start sync code detection" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x00 17. "FE_IRQ_2,Frame end sync code detection" "FE_IRQ_2_0,FE_IRQ_2_1" newline bitfld.long 0x00 16. "FS_IRQ_2,Frame start sync code detection" "FS_IRQ_2_0,FS_IRQ_2_1" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 13. "ECC_CORRECTION0_IRQ_1,ECC has been used to correct the only 1-bit error" "ECC_CORRECTION0_IRQ_1_0,ECC_CORRECTION0_IRQ_1_1" newline bitfld.long 0x00 12. "CS_IRQ_1,Check-Sum of the payload mismatch detection" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x00 11. "LE_IRQ_1,Line end sync code detection" "LE_IRQ_1_0,LE_IRQ_1_1" newline bitfld.long 0x00 10. "LS_IRQ_1,Line start sync code detection" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x00 9. "FE_IRQ_1,Frame end sync code detection" "FE_IRQ_1_0,FE_IRQ_1_1" newline bitfld.long 0x00 8. "FS_IRQ_1,Frame start sync code detection" "FS_IRQ_1_0,FS_IRQ_1_1" newline rbitfld.long 0x00 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 5. "ECC_CORRECTION0_IRQ_0,ECC has been used to correct the only 1-bit error" "ECC_CORRECTION0_IRQ_0_0,ECC_CORRECTION0_IRQ_0_1" newline bitfld.long 0x00 4. "CS_IRQ_0,Check-Sum of the payload mismatch detection" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x00 3. "LE_IRQ_0,Line end sync code detection" "LE_IRQ_0_0,LE_IRQ_0_1" newline bitfld.long 0x00 2. "LS_IRQ_0,Line start sync code detection" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x00 1. "FE_IRQ_0,Frame end sync code detection" "FE_IRQ_0_0,FE_IRQ_0_1" newline bitfld.long 0x00 0. "FS_IRQ_0,Frame start sync code detection" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x398++0x03 line.long 0x00 "CAL_CSI2_VC_IRQENABLE_l_1,INTERRUPT ENABLE REGISTER - Virtual channels" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 29. "ECC_CORRECTION0_IRQ_3,ECC has been used to correct the only 1-bit error" "ECC_CORRECTION0_IRQ_3_0,ECC_CORRECTION0_IRQ_3_1" newline bitfld.long 0x00 28. "CS_IRQ_3,Check-Sum of the payload mismatch detection" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x00 27. "LE_IRQ_3,Line end sync code detection" "LE_IRQ_3_0,LE_IRQ_3_1" newline bitfld.long 0x00 26. "LS_IRQ_3,Line start sync code detection" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x00 25. "FE_IRQ_3,Frame end sync code detection" "FE_IRQ_3_0,FE_IRQ_3_1" newline bitfld.long 0x00 24. "FS_IRQ_3,Frame start sync code detection" "FS_IRQ_3_0,FS_IRQ_3_1" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 21. "ECC_CORRECTION0_IRQ_2,ECC has been used to correct the only 1-bit error" "ECC_CORRECTION0_IRQ_2_0,ECC_CORRECTION0_IRQ_2_1" newline bitfld.long 0x00 20. "CS_IRQ_2,Check-Sum of the payload mismatch detection" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x00 19. "LE_IRQ_2,Line end sync code detection" "LE_IRQ_2_0,LE_IRQ_2_1" newline bitfld.long 0x00 18. "LS_IRQ_2,Line start sync code detection" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x00 17. "FE_IRQ_2,Frame end sync code detection" "FE_IRQ_2_0,FE_IRQ_2_1" newline bitfld.long 0x00 16. "FS_IRQ_2,Frame start sync code detection" "FS_IRQ_2_0,FS_IRQ_2_1" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 13. "ECC_CORRECTION0_IRQ_1,ECC has been used to correct the only 1-bit error" "ECC_CORRECTION0_IRQ_1_0,ECC_CORRECTION0_IRQ_1_1" newline bitfld.long 0x00 12. "CS_IRQ_1,Check-Sum of the payload mismatch detection" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x00 11. "LE_IRQ_1,Line end sync code detection" "LE_IRQ_1_0,LE_IRQ_1_1" newline bitfld.long 0x00 10. "LS_IRQ_1,Line start sync code detection" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x00 9. "FE_IRQ_1,Frame end sync code detection" "FE_IRQ_1_0,FE_IRQ_1_1" newline bitfld.long 0x00 8. "FS_IRQ_1,Frame start sync code detection" "FS_IRQ_1_0,FS_IRQ_1_1" newline rbitfld.long 0x00 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 5. "ECC_CORRECTION0_IRQ_0,ECC has been used to correct the only 1-bit error" "ECC_CORRECTION0_IRQ_0_0,ECC_CORRECTION0_IRQ_0_1" newline bitfld.long 0x00 4. "CS_IRQ_0,Check-Sum of the payload mismatch detection" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x00 3. "LE_IRQ_0,Line end sync code detection" "LE_IRQ_0_0,LE_IRQ_0_1" newline bitfld.long 0x00 2. "LS_IRQ_0,Line start sync code detection" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x00 1. "FE_IRQ_0,Frame end sync code detection" "FE_IRQ_0_0,FE_IRQ_0_1" newline bitfld.long 0x00 0. "FS_IRQ_0,Frame start sync code detection" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x328++0x03 line.long 0x00 "CAL_CSI2_VC_IRQSTATUS_l_0,INTERRUPT STATUS REGISTER - Virtual channels This register regroups all the events related to Context" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 29. "ECC_CORRECTION_IRQ_3,ECC has been used to do the correction of the only 1-bit error status" "ECC_CORRECTION_IRQ_3_0,ECC_CORRECTION_IRQ_3_1" newline bitfld.long 0x00 28. "CS_IRQ_3,Check-Sum mismatch status" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x00 27. "LE_IRQ_3,Line end sync code detection status" "LE_IRQ_3_0,LE_IRQ_3_1" newline bitfld.long 0x00 26. "LS_IRQ_3,Line start sync code detection status" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x00 25. "FE_IRQ_3,Frame end sync code detection status" "FE_IRQ_3_0,FE_IRQ_3_1" newline bitfld.long 0x00 24. "FS_IRQ_3,Frame start sync code detection status" "FS_IRQ_3_0,FS_IRQ_3_1" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 21. "ECC_CORRECTION_IRQ_2,ECC has been used to do the correction of the only 1-bit error status" "ECC_CORRECTION_IRQ_2_0,ECC_CORRECTION_IRQ_2_1" newline bitfld.long 0x00 20. "CS_IRQ_2,Check-Sum mismatch status" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x00 19. "LE_IRQ_2,Line end sync code detection status" "LE_IRQ_2_0,LE_IRQ_2_1" newline bitfld.long 0x00 18. "LS_IRQ_2,Line start sync code detection status" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x00 17. "FE_IRQ_2,Frame end sync code detection status" "FE_IRQ_2_0,FE_IRQ_2_1" newline bitfld.long 0x00 16. "FS_IRQ_2,Frame start sync code detection status" "FS_IRQ_2_0,FS_IRQ_2_1" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 13. "ECC_CORRECTION_IRQ_1,ECC has been used to do the correction of the only 1-bit error status" "ECC_CORRECTION_IRQ_1_0,ECC_CORRECTION_IRQ_1_1" newline bitfld.long 0x00 12. "CS_IRQ_1,Check-Sum mismatch status" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x00 11. "LE_IRQ_1,Line end sync code detection status" "LE_IRQ_1_0,LE_IRQ_1_1" newline bitfld.long 0x00 10. "LS_IRQ_1,Line start sync code detection status" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x00 9. "FE_IRQ_1,Frame end sync code detection status" "FE_IRQ_1_0,FE_IRQ_1_1" newline bitfld.long 0x00 8. "FS_IRQ_1,Frame start sync code detection status" "FS_IRQ_1_0,FS_IRQ_1_1" newline rbitfld.long 0x00 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 5. "ECC_CORRECTION_IRQ_0,ECC has been used to do the correction of the only 1-bit error status" "ECC_CORRECTION_IRQ_0_0,ECC_CORRECTION_IRQ_0_1" newline bitfld.long 0x00 4. "CS_IRQ_0,Check-Sum mismatch status" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x00 3. "LE_IRQ_0,Line end sync code detection status" "LE_IRQ_0_0,LE_IRQ_0_1" newline bitfld.long 0x00 2. "LS_IRQ_0,Line start sync code detection status" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x00 1. "FE_IRQ_0,Frame end sync code detection status" "FE_IRQ_0_0,FE_IRQ_0_1" newline bitfld.long 0x00 0. "FS_IRQ_0,Frame start sync code detection status" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x3A8++0x03 line.long 0x00 "CAL_CSI2_VC_IRQSTATUS_l_1,INTERRUPT STATUS REGISTER - Virtual channels This register regroups all the events related to Context" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 29. "ECC_CORRECTION_IRQ_3,ECC has been used to do the correction of the only 1-bit error status" "ECC_CORRECTION_IRQ_3_0,ECC_CORRECTION_IRQ_3_1" newline bitfld.long 0x00 28. "CS_IRQ_3,Check-Sum mismatch status" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x00 27. "LE_IRQ_3,Line end sync code detection status" "LE_IRQ_3_0,LE_IRQ_3_1" newline bitfld.long 0x00 26. "LS_IRQ_3,Line start sync code detection status" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x00 25. "FE_IRQ_3,Frame end sync code detection status" "FE_IRQ_3_0,FE_IRQ_3_1" newline bitfld.long 0x00 24. "FS_IRQ_3,Frame start sync code detection status" "FS_IRQ_3_0,FS_IRQ_3_1" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 21. "ECC_CORRECTION_IRQ_2,ECC has been used to do the correction of the only 1-bit error status" "ECC_CORRECTION_IRQ_2_0,ECC_CORRECTION_IRQ_2_1" newline bitfld.long 0x00 20. "CS_IRQ_2,Check-Sum mismatch status" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x00 19. "LE_IRQ_2,Line end sync code detection status" "LE_IRQ_2_0,LE_IRQ_2_1" newline bitfld.long 0x00 18. "LS_IRQ_2,Line start sync code detection status" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x00 17. "FE_IRQ_2,Frame end sync code detection status" "FE_IRQ_2_0,FE_IRQ_2_1" newline bitfld.long 0x00 16. "FS_IRQ_2,Frame start sync code detection status" "FS_IRQ_2_0,FS_IRQ_2_1" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 13. "ECC_CORRECTION_IRQ_1,ECC has been used to do the correction of the only 1-bit error status" "ECC_CORRECTION_IRQ_1_0,ECC_CORRECTION_IRQ_1_1" newline bitfld.long 0x00 12. "CS_IRQ_1,Check-Sum mismatch status" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x00 11. "LE_IRQ_1,Line end sync code detection status" "LE_IRQ_1_0,LE_IRQ_1_1" newline bitfld.long 0x00 10. "LS_IRQ_1,Line start sync code detection status" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x00 9. "FE_IRQ_1,Frame end sync code detection status" "FE_IRQ_1_0,FE_IRQ_1_1" newline bitfld.long 0x00 8. "FS_IRQ_1,Frame start sync code detection status" "FS_IRQ_1_0,FS_IRQ_1_1" newline rbitfld.long 0x00 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 5. "ECC_CORRECTION_IRQ_0,ECC has been used to do the correction of the only 1-bit error status" "ECC_CORRECTION_IRQ_0_0,ECC_CORRECTION_IRQ_0_1" newline bitfld.long 0x00 4. "CS_IRQ_0,Check-Sum mismatch status" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x00 3. "LE_IRQ_0,Line end sync code detection status" "LE_IRQ_0_0,LE_IRQ_0_1" newline bitfld.long 0x00 2. "LS_IRQ_0,Line start sync code detection status" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x00 1. "FE_IRQ_0,Frame end sync code detection status" "FE_IRQ_0_0,FE_IRQ_0_1" newline bitfld.long 0x00 0. "FS_IRQ_0,Frame start sync code detection status" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x330++0x03 line.long 0x00 "CAL_CSI2_CTX0_l_0,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x3B0++0x03 line.long 0x00 "CAL_CSI2_CTX0_l_1,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x334++0x03 line.long 0x00 "CAL_CSI2_CTX1_l_0,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x3B4++0x03 line.long 0x00 "CAL_CSI2_CTX1_l_1,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x338++0x03 line.long 0x00 "CAL_CSI2_CTX2_l_0,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x3B8++0x03 line.long 0x00 "CAL_CSI2_CTX2_l_1,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x33C++0x03 line.long 0x00 "CAL_CSI2_CTX3_l_0,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x3BC++0x03 line.long 0x00 "CAL_CSI2_CTX3_l_1,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x340++0x03 line.long 0x00 "CAL_CSI2_CTX4_l_0,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x3C0++0x03 line.long 0x00 "CAL_CSI2_CTX4_l_1,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x344++0x03 line.long 0x00 "CAL_CSI2_CTX5_l_0,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x3C4++0x03 line.long 0x00 "CAL_CSI2_CTX5_l_1,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x348++0x03 line.long 0x00 "CAL_CSI2_CTX6_l_0,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x3C8++0x03 line.long 0x00 "CAL_CSI2_CTX6_l_1,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x34C++0x03 line.long 0x00 "CAL_CSI2_CTX7_l_0,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x3CC++0x03 line.long 0x00 "CAL_CSI2_CTX7_l_1,Context control" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "PACK_MODE,Controls the data packing behavior" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline" "ATT_0,ATT_1" newline bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" newline bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" rgroup.long 0x350++0x03 line.long 0x00 "CAL_CSI2_STATUS0_l_0,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x3D0++0x03 line.long 0x00 "CAL_CSI2_STATUS0_l_1,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x354++0x03 line.long 0x00 "CAL_CSI2_STATUS1_l_0,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x3D4++0x03 line.long 0x00 "CAL_CSI2_STATUS1_l_1,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x358++0x03 line.long 0x00 "CAL_CSI2_STATUS2_l_0,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x3D8++0x03 line.long 0x00 "CAL_CSI2_STATUS2_l_1,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x35C++0x03 line.long 0x00 "CAL_CSI2_STATUS3_l_0,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x3DC++0x03 line.long 0x00 "CAL_CSI2_STATUS3_l_1,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x360++0x03 line.long 0x00 "CAL_CSI2_STATUS4_l_0,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x3E0++0x03 line.long 0x00 "CAL_CSI2_STATUS4_l_1,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x364++0x03 line.long 0x00 "CAL_CSI2_STATUS5_l_0,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x3E4++0x03 line.long 0x00 "CAL_CSI2_STATUS5_l_1,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x368++0x03 line.long 0x00 "CAL_CSI2_STATUS6_l_0,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x3E8++0x03 line.long 0x00 "CAL_CSI2_STATUS6_l_1,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x36C++0x03 line.long 0x00 "CAL_CSI2_STATUS7_l_0,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" rgroup.long 0x3EC++0x03 line.long 0x00 "CAL_CSI2_STATUS7_l_1,Context status register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" width 0x0B tree.end tree "CAM_CM_CORE" base ad:0x4A009000 group.long 0x00++0x07 line.long 0x00 "CM_CAM_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED," rbitfld.long 0x00 12. "CLKACTIVITY_LVDSRX_96M_GFCLK,This field indicates the state of the LVDSRX_96M_GFCLK clock input of the domain" "CLKACTIVITY_LVDSRX_96M_GFCLK_0,CLKACTIVITY_LVDSRX_96M_GFCLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_LVDSRX_L4_GICLK,This field indicates the state of the LVDSRX_L4_GICLK clock input of the domain" "CLKACTIVITY_LVDSRX_L4_GICLK_0,CLKACTIVITY_LVDSRX_L4_GICLK_1" rbitfld.long 0x00 10. "CLKACTIVITY_VIP3_GCLK,This field indicates the state of the VIP3_GCLK clock input of the domain" "CLKACTIVITY_VIP3_GCLK_0,CLKACTIVITY_VIP3_GCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_VIP2_GCLK,This field indicates the state of the VIP2_GCLK clock input of the domain" "CLKACTIVITY_VIP2_GCLK_0,CLKACTIVITY_VIP2_GCLK_1" rbitfld.long 0x00 8. "CLKACTIVITY_VIP1_GCLK,This field indicates the state of the VIP1_GCLK clock input of the domain" "CLKACTIVITY_VIP1_GCLK_0,CLKACTIVITY_VIP1_GCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the CAM clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_CAM_STATICDEP,This register controls the static domain depedencies from CAM domain towards 'target' domains" rbitfld.long 0x04 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 28. "ISS_STATDEP,Static dependency towards ISS clock domain" "ISS_STATDEP_0,ISS_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" rbitfld.long 0x04 26. "RESERVED," "0,1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain" "GMAC_STATDEP_0,GMAC_STATDEP_1" rbitfld.long 0x04 23.--24. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain" "EVE2_STATDEP_0,EVE2_STATDEP_1" bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain" "EVE1_STATDEP_0,EVE1_STATDEP_1" newline rbitfld.long 0x04 13.--18. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,?" newline rbitfld.long 0x04 6.--11. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" group.long 0x20++0x03 line.long 0x00 "CM_CAM_VIP1_CLKCTRL,This register manages the VIP1 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for VIP between L3_ICLK and CORE_ISS_MAIN_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x28++0x03 line.long 0x00 "CM_CAM_VIP2_CLKCTRL,This register manages the VIP2 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for VIP between L3_ICLK and CORE_ISS_MAIN_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x30++0x03 line.long 0x00 "CM_CAM_VIP3_CLKCTRL,This register manages the VIP3 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for VIP between L3_ICLK and CORE_ISS_MAIN_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x38++0x03 line.long 0x00 "CM_CAM_LVDSRX_CLKCTRL,This register manages the LVDSRX clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x40++0x03 line.long 0x00 "CM_CAM_CSI1_CLKCTRL,This register manages the CSI1 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x48++0x03 line.long 0x00 "CM_CAM_CSI2_CLKCTRL,This register manages the CSI2 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" width 0x0B tree.end tree "CAM_PRM" base ad:0x4AE07000 group.long 0x00++0x07 line.long 0x00 "PM_CAM_PWRSTCTRL,This register controls the CAM power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "VIP_BANK_ONSTATE,VIP_BANK memory state when domain is ON" "?,?,?,VIP_BANK_ONSTATE_3" newline hexmask.long.word 0x00 5.--15. 1. "RESERVED," bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_CAM_PWRSTST,This register provides a status on the current CAM power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "VIP_BANK_STATEST,VIP_BANK memory state status" "VIP_BANK_STATEST_0,VIP_BANK_STATEST_1,VIP_BANK_STATEST_2,VIP_BANK_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x20++0x17 line.long 0x00 "PM_CAM_VIP1_WKDEP,This register controls wakeup dependency based on VIP1 service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_VIP1_EVE4,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_EVE4_0,WKUPDEP_VIP1_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_VIP1_EVE3,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_EVE3_0,WKUPDEP_VIP1_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_VIP1_EVE2,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_EVE2_0,WKUPDEP_VIP1_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_VIP1_EVE1,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_EVE1_0,WKUPDEP_VIP1_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_VIP1_DSP2,Wakeup dependency from VIP1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_DSP2_0,WKUPDEP_VIP1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_VIP1_IPU1,Wakeup dependency from VIP1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_IPU1_0,WKUPDEP_VIP1_IPU1_1" rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_VIP1_DSP1,Wakeup dependency from VIP1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_DSP1_0,WKUPDEP_VIP1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_VIP1_IPU2,Wakeup dependency from vip1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_IPU2_0,WKUPDEP_VIP1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_VIP1_MPU,Wakeup dependency from VIP1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_MPU_0,WKUPDEP_VIP1_MPU_1" line.long 0x04 "RM_CAM_VIP1_CONTEXT,This register contains dedicated VIP1 context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_VIP_BANK,Specify if memory-based context in VIP_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VIP_BANK_0,LOSTMEM_VIP_BANK_1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_CAM_VIP2_WKDEP,This register controls wakeup dependency based on VIP2 service requests" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "WKUPDEP_VIP2_EVE4,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_EVE4_0,WKUPDEP_VIP2_EVE4_1" newline bitfld.long 0x08 8. "WKUPDEP_VIP2_EVE3,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_EVE3_0,WKUPDEP_VIP2_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_VIP2_EVE2,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_EVE2_0,WKUPDEP_VIP2_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_VIP2_EVE1,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_EVE1_0,WKUPDEP_VIP2_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_VIP2_DSP2,Wakeup dependency from VIP1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_DSP2_0,WKUPDEP_VIP2_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_VIP2_IPU1,Wakeup dependency from VIP2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_IPU1_0,WKUPDEP_VIP2_IPU1_1" rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 2. "WKUPDEP_VIP2_DSP1,Wakeup dependency from VIP2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_DSP1_0,WKUPDEP_VIP2_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_VIP2_IPU2,Wakeup dependency from VIP2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_IPU2_0,WKUPDEP_VIP2_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_VIP2_MPU,Wakeup dependency from VIP2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_MPU_0,WKUPDEP_VIP2_MPU_1" line.long 0x0C "RM_CAM_VIP2_CONTEXT,This register contains dedicated VIP2 context statuses" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED," bitfld.long 0x0C 8. "LOSTMEM_VIP_BANK,Specify if memory-based context in VIP_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VIP_BANK_0,LOSTMEM_VIP_BANK_1" newline hexmask.long.byte 0x0C 1.--7. 1. "RESERVED," bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_CAM_VIP3_WKDEP,This register controls wakeup dependency based on VIP3 service requests" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED," bitfld.long 0x10 9. "WKUPDEP_VIP3_EVE4,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_EVE4_0,WKUPDEP_VIP3_EVE4_1" newline bitfld.long 0x10 8. "WKUPDEP_VIP3_EVE3,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_EVE3_0,WKUPDEP_VIP3_EVE3_1" bitfld.long 0x10 7. "WKUPDEP_VIP3_EVE2,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_EVE2_0,WKUPDEP_VIP3_EVE2_1" newline bitfld.long 0x10 6. "WKUPDEP_VIP3_EVE1,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_EVE1_0,WKUPDEP_VIP3_EVE1_1" bitfld.long 0x10 5. "WKUPDEP_VIP3_DSP2,Wakeup dependency from VIP3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_DSP2_0,WKUPDEP_VIP3_DSP2_1" newline bitfld.long 0x10 4. "WKUPDEP_VIP3_IPU1,Wakeup dependency from VIP3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_IPU1_0,WKUPDEP_VIP3_IPU1_1" rbitfld.long 0x10 3. "RESERVED," "0,1" newline bitfld.long 0x10 2. "WKUPDEP_VIP3_DSP1,Wakeup dependency from VIP3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_DSP1_0,WKUPDEP_VIP3_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_VIP3_IPU2,Wakeup dependency from vip3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_IPU2_0,WKUPDEP_VIP3_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_VIP3_MPU,Wakeup dependency from VIP3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_MPU_0,WKUPDEP_VIP3_MPU_1" line.long 0x14 "RM_CAM_VIP3_CONTEXT,This register contains dedicated VIP3 context statuses" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED," bitfld.long 0x14 8. "LOSTMEM_VIP_BANK,Specify if memory-based context in VIP_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VIP_BANK_0,LOSTMEM_VIP_BANK_1" newline hexmask.long.byte 0x14 1.--7. 1. "RESERVED," bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x3C++0x03 line.long 0x00 "RM_CAM_LVDSRX_CONTEXT,This register contains dedicated LVDSRX context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x44++0x03 line.long 0x00 "RM_CAM_CSI1_CONTEXT,This register contains dedicated CSI1 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x4C++0x03 line.long 0x00 "RM_CAM_CSI2_CONTEXT,This register contains dedicated CSI2 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "CAMERARX_CORE_0" base ad:0x52012800 group.long 0x00++0x0F line.long 0x00 "REG0,First register" hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved fields" bitfld.long 0x00 24. "HSCLOCKCONFIG,Disable clock missing detector" "0,1" newline hexmask.long.byte 0x00 16.--23. 1. "RESERVED,Read returns zero" hexmask.long.byte 0x00 8.--15. 1. "THS_TERM,THS_TERM timing parameter in multiples of DDR clock frequency" newline hexmask.long.byte 0x00 0.--7. 1. "THS_SETTLE,THS_SETTLE timing parameter in multiples of DDR clock frequency" line.long 0x04 "REG1,Second register" bitfld.long 0x04 30.--31. "RESVD_READ_BIT,Reserved bit" "0,1,2,3" rbitfld.long 0x04 28.--29. "RESET_DONE_STATUS,Reset done read bits" "?,?,?,?" newline bitfld.long 0x04 26.--27. "RESERVED,Write 0 for future compatibility" "0,1,2,3" rbitfld.long 0x04 25. "CLOCK_MISS_DETECTOR_STATUS,Clock missing detector status" "CLOCK_MISS_DETECTOR_STATUS_0,?" newline hexmask.long.byte 0x04 18.--24. 1. "TCLK_TERM,TCLK_TERM timing parameter in multiples of CTRLCLK Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1-2)* CTRLCLK + TCLK_TERM + ~ (1-15) ns Programmed value = ceil(9.5.." hexmask.long.byte 0x04 10.--17. 1. "DPHY_HS_SYNC_PATTERN,DPHY mode HS sync pattern in byte order (reverse of received order) See " newline bitfld.long 0x04 8.--9. "TCLK_DIV,CTRLCLK_DIV_FACTOR Divide factor for CTRLCLK for CLKMISS detector Programmed value = ceil (15ns/CTRLCLK Period) - 1 Default value: 1 (for 96 MHz) CLKMISS detection time = (5*TCLK_DIV+1)*(CTRLCLK period) < 60ns Note: Only the CTRLCLK.." "0,1,2,3" hexmask.long.byte 0x04 0.--7. 1. "TCLK_SETTLE,TCLK_SETTLE timing parameter in multiples of CTRLCLK Clock Effective TCLK_SETTLE = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1-2)* CTRLCLK + Tclk-settle + ~ (1 -15) ns Programmed value = max[3 ceil(155.." line.long 0x08 "REG2,Third register" bitfld.long 0x08 30.--31. "TRIGGER_CMD_RXTRIGESC0,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC0" "'01100010','01011101','00100001','10100000'" bitfld.long 0x08 28.--29. "TRIGGER_CMD_RXTRIGESC1,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC1" "'01011101','00100001','10100000','01100010'" newline bitfld.long 0x08 26.--27. "TRIGGER_CMD_RXTRIGESC2,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC2" "'00100001','01100010','01100010','01011101'" bitfld.long 0x08 24.--25. "TRIGGER_CMD_RXTRIGESC3,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC3" "'10100000','01100010','01011101','00100001'" newline hexmask.long.tbyte 0x08 0.--23. 1. "CCP2_SYNC_PATTERN,CCP2 mode sync pattern in byte order (reverse of received order) See " line.long 0x0C "REG3,Forth register" bitfld.long 0x0C 31. "OVRD_HSRXEN,Override with register bit" "0,1" bitfld.long 0x0C 26.--30. "ENHSRX,HSRX Enable on LANE5-0.1:Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 25. "OVRD_HSRXTERM,Override with register bit.1:Override" "0,1" bitfld.long 0x0C 20.--24. "ENRXTERM,HS-RX Termination enable on LANE5-0.1:Enable.0:Default" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 19. "OVRD_LPRXEN_ULPRXEN,Override LP-RX and ULP-RX Enable.1:Override" "0,1" bitfld.long 0x0C 14.--18. "ENLPRX,Enable for LP-RX on LANE5-01 : Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 9.--13. "ENULPRX,Enable for ULP-RX on LANE5-01 : Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 8. "LDO_EN_OVRD,LDO Enable Override.1:Override" "0,1" newline bitfld.long 0x0C 7. "EN_LDO,Enable LDO.1:Enable.0:Default" "0,1" bitfld.long 0x0C 6. "BIAS_EN_OVRD,BIAS Enable Override.1 :Override with register bit" "0,1" newline bitfld.long 0x0C 5. "ENABLE_BIAS,Enable BIAS.1:Enable" "0,1" bitfld.long 0x0C 4. "OVERRIDE_ENCCP,Override ENCCP to anatop.1: Override with register bit0:Default" "0,1" newline bitfld.long 0x0C 3. "ENCCP_OVRRD_HSRX,ENCCP override to HSRX.1: Enable0: Disable" "0,1" bitfld.long 0x0C 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 1. "RECALIB_HSRX_COMP_OFFSET,Recalibrate HS-RX comparator offset.Make this bit 0'1 to restart offset calibration" "0,1" bitfld.long 0x0C 0. "RECALIB_BIAS_CURRENT,Recalibrate biasgen.Make this bit 0'1 to restart bias calibration" "0,1" group.long 0x18++0x13 line.long 0x00 "REG6,Seventh register" bitfld.long 0x00 31. "RESERVED,Reserved" "0,1" bitfld.long 0x00 30. "BGAP_EN_OVRRD,BGAP enable override0: Default" "0,1" newline bitfld.long 0x00 29. "BGAP_EN,BANDGAP enable0: Disable" "0,1" bitfld.long 0x00 28. "HS_SYNC_BYPASS,To bypass HS Sync sequence0: Normal" "0,1" newline bitfld.long 0x00 27. "LP_SOT_BYPASS_LPBK,To bypass the LP SoT sequence in loopback mode0: Normal" "0,1" bitfld.long 0x00 26. "LDO_RDY_OVRRD,LDO_RDY override0: Default" "0,1" newline bitfld.long 0x00 25. "LDO_RDY,LDO_RDY makes internal LDO_RDY=1" "0,1" bitfld.long 0x00 24. "ENCALIB_OVRRD,ENCALIB override0: Default" "0,1" newline bitfld.long 0x00 23. "ENCALIB,ENCALIB* Override ENCALIBA and ENCALIBB with the register bit" "0,1" bitfld.long 0x00 22. "ENBIASCALIB_OVRRD,ENBIASCALIB override0: Default" "0,1" newline bitfld.long 0x00 21. "ENBIASCALIB,Override ENBIASCALIB with this register bit" "0,1" bitfld.long 0x00 20. "OVRD_AFE_INPUTS,Override LANEENABLE and POLARITY AFE inputs.0:Normal" "0,1" newline hexmask.long.byte 0x00 12.--19. 1. "AFE_LANE_SELECT,Selects clock lane and data lane mapping for AFE" bitfld.long 0x00 11. "SEL_AFE_LANE_POLARITY,Select AFE lane polarity" "0,1" newline bitfld.long 0x00 10. "HSCOMPOUT_FAR,Select FAR lane HSCOMP output to HSCOMOOUT in AFE" "0,1" bitfld.long 0x00 9. "BYPASS_LDO_REF," "0,1" newline bitfld.long 0x00 8. "LDO_VLTG_DYA,Observe LDO voltage on DYA pad.0:Normal" "0,1" bitfld.long 0x00 7. "BIAS_CRNT_DXA,Observe bias current on DXA pad.0:Normal" "0,1" newline bitfld.long 0x00 6. "RESERVED,Reserved" "0,1" bitfld.long 0x00 5. "OVRD_BIASGEN_CALIB," "0,1" newline bitfld.long 0x00 0.--4. "BIAS_CALIB_OVRD_VAL,Biasgen calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "REG7,Eight register" bitfld.long 0x04 31. "BGAP_TRIM_OVRRD,Bandgap trim bits override" "Normal (default mode),Override Bandgap trim bits with SCP register bits" abitfld.long 0x04 23.--30. "BGAP_TRIM,Bandgap trim bits" "0x00=Minimum bandgap voltage,0xFF=Maximum bandgap voltage" newline bitfld.long 0x04 22. "BGAP_MAGTRIM_OVRRD,Bandgap magnitude trim bits override0: Normal (default mode)" "0,1" hexmask.long.byte 0x04 14.--21. 1. "BGAP_MAGTRIM,Bandgap magnitude trim bits00000000 : Minimum bandgap voltage" newline bitfld.long 0x04 12.--13. "DTCY_MEAS_HSRX,Duty cycle measurement in HSRX mode00: Default" "0,1,2,3" bitfld.long 0x04 7.--11. "RESERVED,Write 0 for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 6. "BIASCALIB_OVRRD,BIASCALIB override" "Default,Override BIASCALIB.." bitfld.long 0x04 5. "BIASCALIB,BIASCALIB bit from SCP reg" "0,1" newline bitfld.long 0x04 0.--4. "CDISABLE_HS_TERM,Disable HS Termination" "Normal,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Disable Lane4 3.." line.long 0x08 "REG8,Ninth register" bitfld.long 0x08 31. "CCP_OVRRD,CCP override0: Normal" "0,1" bitfld.long 0x08 30. "CCPF,Override CCPF from analog with this register bit" "0,1" newline bitfld.long 0x08 29. "CCPR,Override CCPR from analog with this register bit" "0,1" bitfld.long 0x08 28. "HSRX_OVRRD,HSRX override" "Normal,Override HSRX.." newline bitfld.long 0x08 24.--27. "CSI2R3_0,Override CSI2R[3:0] for 4 lanes from analog with these register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 20.--23. "CSI2F3_0,Override CSI2F[3:0] for 4 lanes from analog with these register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 19. "HSCOMPOUT,Override HSCOMPOUT from analog with this register bit" "0,1" bitfld.long 0x08 18. "SELDX_Y_OVRRD,SELDX*/Y* override0: Overrides the control to bypass of LPRX delay on DX/DY pads depending on testmode_sel_reg[6] and WPI_PMT[0] for DX pads and WPI_PMT[1] for DY pads" "0,1" newline bitfld.long 0x08 13.--17. "SELDY,SELDY*controls bypass of LPRY delay on DY pads (5 lanes) Bit Mapping: 17 -> ADDON3 16 -> ADDON2 17 -> LaneB 14 -> LaneA 13 -> ADDON1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 8.--12. "SELDX,SELDX*controls bypass of LPRX delay on DX pads (5 lanes) Bit Mapping: 12 -> ADDON3 11 -> ADDON2 10 -> LaneB 9 -> LaneA 8 -> ADDON1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 7. "ENLOOPBACK_OVRRD,ENLOOPBACK Override0: Normal" "0,1" bitfld.long 0x08 6. "ENLOOPBACK,ENLOOPBACK transmitter enable (in self or internal loopback mode) from SCP register bit" "0,1" newline bitfld.long 0x08 5. "IE_OVRRD,IE override" "Normal,Override IE (4.." bitfld.long 0x08 4. "IE3_0,Override IE[3:0] (4 lanes) with this single bit" "0,1" newline bitfld.long 0x08 3. "PIPU_OVRRD,PIPU override0: Normal" "0,1" bitfld.long 0x08 2. "PIPU3_0,Override PIPU[3:0] (4 lanes) with this single bit" "0,1" newline bitfld.long 0x08 1. "PIPD_OVRRD,PIPD override" "Normal,Override PIPD (4.." bitfld.long 0x08 0. "PIPD3_0,Override PIPD[3:0] (4 lanes) with this single bit" "0,1" line.long 0x0C "REG9,Tenth register" bitfld.long 0x0C 31. "LPRX_OVRRD,LPRX override0: Normal (defautlt mode)" "0,1" bitfld.long 0x0C 30. "LPRXDXA,Bypass LPRXD* comparator output with this bit" "0,1" newline bitfld.long 0x0C 29. "LPRXDYA,Bypass LPRXD* comparator output with this bit" "0,1" bitfld.long 0x0C 28. "LPRXDXB,Bypass LPRXD* comparator output with this bit" "0,1" newline bitfld.long 0x0C 27. "LPRXDYB,Bypass LPRXD* comparator output with this bit" "0,1" bitfld.long 0x0C 26. "LPRXDX_ADDON1,Bypass LPRXD* comparator output with this bit" "0,1" newline bitfld.long 0x0C 25. "LPRXDY_ADDON1,Bypass LPRXD* comparator output with this bit" "0,1" bitfld.long 0x0C 24. "LPRXDX_ADDON2,Bypass LPRXD* comparator output with this bit" "0,1" newline bitfld.long 0x0C 23. "LPRXDY_ADDON2,Bypass LPRXD* comparator output with this bit" "0,1" bitfld.long 0x0C 22. "LPRXDX_ADDON3,Bypass LPRXD* comparator output with this bit" "0,1" newline bitfld.long 0x0C 21. "LPRXDY_ADDON3,Bypass LPRXD* comparator output with this bit" "0,1" bitfld.long 0x0C 20. "ULPRX_OVRRD,ULPRX Override0: Normal (default mode)" "0,1" newline bitfld.long 0x0C 19. "ULPRXDXA,Bypass ULPRXD* comparator output with this bit" "0,1" bitfld.long 0x0C 18. "ULPRXDYA,Bypass ULPRXD* comparator output with this bit" "0,1" newline bitfld.long 0x0C 17. "ULPRXDXB,Bypass ULPRXD* comparator output with this bit" "0,1" bitfld.long 0x0C 16. "ULPRXDYB,Bypass ULPRXD* comparator output with this bit" "0,1" newline bitfld.long 0x0C 15. "ULPRXDX_ADDON1,Bypass ULPRXD* comparator output with this bit" "0,1" bitfld.long 0x0C 14. "ULPRXDY_ADDON1,Bypass ULPRXD* comparator output with this bit" "0,1" newline bitfld.long 0x0C 13. "ULPRXDX_ADDON2,Bypass ULPRXD* comparator output with this bit" "0,1" bitfld.long 0x0C 12. "ULPRXDY_ADDON2,Bypass ULPRXD* comparator output with this bit" "0,1" newline bitfld.long 0x0C 11. "ULPRXDX_ADDON3,Bypass ULPRXD* comparator output with this bit" "0,1" bitfld.long 0x0C 10. "ULPRXDY_ADDON3,Bypass ULPRXD* comparator output with this bit" "0,1" newline bitfld.long 0x0C 8.--9. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0C 7. "HISPI_MODE_EN,This bit enables the PHY in HiSPi mode0: HiSPi mode disabled (Default)" "0,1" newline bitfld.long 0x0C 6. "ENCCP_HSRX_ADDON1,ENCCP override to HSRX of ADDON1.1: Enable0: Disable" "0,1" bitfld.long 0x0C 5. "ENCCP_HSRX_ADDON2,ENCCP override to HSRX of ADDON2.1: Enable" "0,1" newline bitfld.long 0x0C 4. "ENCCP_HSRX_ADDON_FAR,ENCCP override to HSRX of ADDON_FAR.1: Enable0: Disable" "0,1" bitfld.long 0x0C 0.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "REG10,Eleventh register" hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10 0.--15. 1. "SPAREIN_ANATOP,Sparein AnatopThese bits are directly mapped to SPAREIN* pins of Analog (both LDO and Core voltage domains) and ADDONs for future use" width 0x0B tree.end tree "CKGEN_CM_CORE" base ad:0x4A008104 group.long 0x00++0x03 line.long 0x00 "CM_CLKSEL_USB_60MHZ,Selects the configuration of the divider generating 60MHz clock for USB from the DPLL_USB o/p" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "CLKSEL,Select the configuration of the divider" "CLKSEL_0,CLKSEL_1" group.long 0x3C++0x2F line.long 0x00 "CM_CLKMODE_DPLL_PER,This register allows controlling the DPLL modes" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x00 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x00 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x00 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x00 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x00 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x00 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x00 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x00 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x00 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_PER,This register allows monitoring DPLL activity" hexmask.long 0x04 5.--31. 1. "RESERVED," bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_PER,This register provides automatic control over the DPLL activity" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_PER,This register provides controls over the DPLL" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" rbitfld.long 0x0C 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0C 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x0C 7. "RESERVED," "0,1" newline hexmask.long.byte 0x0C 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_PER,This register provides controls over the M2 divider of DPLL_PER" hexmask.long.tbyte 0x10 12.--31. 1. "RESERVED," rbitfld.long 0x10 11. "CLKX2ST,DPLL CLKOUTX2 status" "CLKX2ST_0,CLKX2ST_1" newline rbitfld.long 0x10 10. "RESERVED," "0,1" rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x10 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "CM_DIV_M3_DPLL_PER,This register provides controls over the M3 divider of the DPLL_PER" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," rbitfld.long 0x14 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x14 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x18 "CM_DIV_H11_DPLL_PER,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1 DPLL_PER" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," rbitfld.long 0x18 9. "CLKST,HSDIVIDER1 CLKOUT1 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x18 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--5. "DIVHS,DPLL (H11+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x1C "CM_DIV_H12_DPLL_PER,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER1 DPLL_PER" hexmask.long.tbyte 0x1C 10.--31. 1. "RESERVED," rbitfld.long 0x1C 9. "CLKST,HSDIVIDER1 CLKOUT2 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x1C 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--5. "DIVHS,DPLL (H12+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x20 "CM_DIV_H13_DPLL_PER,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER1 DPLL_PER" hexmask.long.tbyte 0x20 10.--31. 1. "RESERVED," rbitfld.long 0x20 9. "CLKST,HSDIVIDER1 CLKOUT3 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x20 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x20 0.--5. "DIVHS,DPLL (H13+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x24 "CM_DIV_H14_DPLL_PER,This register provides controls over the CLKOUT4 o/p of the HSDIVIDER1" hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED," rbitfld.long 0x24 9. "CLKST,HSDIVIDER1 CLKOUT4 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x24 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--5. "DIVHS,DPLL (H14+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x28 "CM_SSC_DELTAMSTEP_DPLL_PER,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x28 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x28 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x2C "CM_SSC_MODFREQDIV_DPLL_PER,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x2C 11.--31. 1. "RESERVED," bitfld.long 0x2C 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x2C 7. "RESERVED," "0,1" hexmask.long.byte 0x2C 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" group.long 0x7C++0x13 line.long 0x00 "CM_CLKMODE_DPLL_USB,This register allows controlling the DPLL modes" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x00 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x00 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x00 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" hexmask.long.word 0x00 3.--11. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_USB,This register allows monitoring DPLL activity" hexmask.long 0x04 5.--31. 1. "RESERVED," bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_USB,This register provides automatic control over the DPLL activity" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_USB,This register provides controls over the DPLL" hexmask.long.byte 0x0C 24.--31. 1. "DPLL_SD_DIV,Sigma-Delta divider select (2-255)" bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for CLKOUT,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" bitfld.long 0x0C 21. "DPLL_SELFREQDCO,select DCO output according to required frequency" "DPLL_SELFREQDCO_0,DPLL_SELFREQDCO_1" newline rbitfld.long 0x0C 20. "RESERVED," "0,1" hexmask.long.word 0x0C 8.--19. 1. "DPLL_MULT,DPLL multiplier factor (2 to 4095)" newline hexmask.long.byte 0x0C 0.--7. 1. "DPLL_DIV,DPLL divider factor (0 to 255) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_USB,This register provides controls over the M2 divider of the DPLL" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED," rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x10 7.--8. "RESERVED," "0,1,2,3" hexmask.long.byte 0x10 0.--6. 1. "DIVHS,DPLL M2 post-divider factor (1 to 127)" group.long 0xA4++0x07 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_USB,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x00 21.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--20. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_USB,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED," bitfld.long 0x04 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED," "0,1" hexmask.long.byte 0x04 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" rgroup.long 0xB0++0x03 line.long 0x00 "CM_CLKDCOLDO_DPLL_USB,This register provides status over CLKDCOLDO output of the DPLL" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "ST_DPLL_CLKDCOLDO,DPLL CLKDCOLDO status" "ST_DPLL_CLKDCOLDO_0,ST_DPLL_CLKDCOLDO_1" newline hexmask.long.word 0x00 0.--8. 1. "RESERVED," group.long 0xFC++0x2B line.long 0x00 "CM_CLKMODE_DPLL_PCIE_REF,This register allows controlling the DPLL modes" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x00 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x00 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x00 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" hexmask.long.word 0x00 3.--11. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_PCIE_REF,This register allows monitoring DPLL activity" hexmask.long 0x04 5.--31. 1. "RESERVED," bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_PCIE_REF,This register provides automatic control over the DPLL activity" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_PCIE_REF,This register provides controls over the DPLL" hexmask.long.byte 0x0C 24.--31. 1. "DPLL_SD_DIV,Sigma-Delta divider select (2-255)" bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for CLKOUT,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" bitfld.long 0x0C 21. "DPLL_SELFREQDCO,select DCO output according to required frequency" "DPLL_SELFREQDCO_0,DPLL_SELFREQDCO_1" newline rbitfld.long 0x0C 20. "RESERVED," "0,1" hexmask.long.word 0x0C 8.--19. 1. "DPLL_MULT,DPLL multiplier factor (2 to 4095)" newline hexmask.long.byte 0x0C 0.--7. 1. "DPLL_DIV,DPLL divider factor (0 to 255) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_PCIE_REF,This register provides controls over the M2 divider of the DPLL" hexmask.long.tbyte 0x10 11.--31. 1. "RESERVED," rbitfld.long 0x10 10. "CLKLDOST,DPLL CLKOUTLDO status" "CLKLDOST_0,CLKLDOST_1" newline rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" rbitfld.long 0x10 7.--8. "RESERVED," "0,1,2,3" newline hexmask.long.byte 0x10 0.--6. 1. "DIVHS,DPLL M2 post-divider factor (1 to 127)" line.long 0x14 "CM_SSC_DELTAMSTEP_DPLL_PCIE_REF,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x14 21.--31. 1. "RESERVED," hexmask.long.tbyte 0x14 0.--20. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x18 "CM_SSC_MODFREQDIV_DPLL_PCIE_REF,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x18 11.--31. 1. "RESERVED," bitfld.long 0x18 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED," "0,1" hexmask.long.byte 0x18 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x1C "CM_CLKMODE_APLL_PCIE,This register allows controlling the APLL modes" hexmask.long.tbyte 0x1C 9.--31. 1. "RESERVED," bitfld.long 0x1C 8. "CLKDIV_BYPASS," "CLKDIV_BYPASS_0,CLKDIV_BYPASS_1" newline bitfld.long 0x1C 7. "REFSEL,Select source of reference input clock" "REFSEL_0,REFSEL_1" rbitfld.long 0x1C 6. "RESERVED," "0,1" newline rbitfld.long 0x1C 3.--5. "INPSEL,Reference clock is 100MHz" "0,1,2,3,4,5,6,7" rbitfld.long 0x1C 2. "MODE,APLLPCIE Mode Status" "MODE_0,?" newline bitfld.long 0x1C 0.--1. "MODE_SELECT,Control APLL mode" "MODE_SELECT_0,MODE_SELECT_1,MODE_SELECT_2,MODE_SELECT_3" line.long 0x20 "CM_IDLEST_APLL_PCIE,This register allows monitoring APLL activity" hexmask.long 0x20 1.--31. 1. "RESERVED," bitfld.long 0x20 0. "ST_APLL_CLK,APLL lock status" "ST_APLL_CLK_0,ST_APLL_CLK_1" line.long 0x24 "CM_DIV_M2_APLL_PCIE,This register provides controls over the M2 divider of the DPLL" hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED," bitfld.long 0x24 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline bitfld.long 0x24 7.--8. "RESERVED," "0,1,2,3" hexmask.long.byte 0x24 0.--6. 1. "DIVHS,DPLL M2 post-divider factor (1 to 127)" line.long 0x28 "CM_CLKVCOLDO_APLL_PCIE,This register provides status over CLKVCOLDO and CLKVCOLDO_DIV outputs of the APLL" hexmask.long.tbyte 0x28 11.--31. 1. "RESERVED," bitfld.long 0x28 10. "CLK_DIVST,APLL CLKVCOLDO_DIV status" "CLK_DIVST_0,CLK_DIVST_1" newline bitfld.long 0x28 9. "CLKST,APLL CLKVCOLDO status" "CLKST_0,CLKST_1" hexmask.long.word 0x28 0.--8. 1. "RESERVED," width 0x0B tree.end tree "CKGEN_CM_CORE_AON" base ad:0x4A005100 group.long 0x00++0x03 line.long 0x00 "CM_CLKSEL_CORE,CORE module clock selection" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKSEL_L4,Selects L4 interconnect clock (L4_clk)" "CLKSEL_L4_0,CLKSEL_L4_1" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "CLKSEL_L3,Selects L3 interconnect clock (L3_clk)" "CLKSEL_L3_0,CLKSEL_L3_1" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x08++0x03 line.long 0x00 "CM_CLKSEL_ABE,ABE module clock selection" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," bitfld.long 0x00 10. "SLIMBUS1_CLK_GATE,Gating control for SLIMBUS_CLK clock tree in ABE" "SLIMBUS1_CLK_GATE_0,SLIMBUS1_CLK_GATE_1" newline rbitfld.long 0x00 9. "RESERVED," "0,1" bitfld.long 0x00 8. "PAD_CLKS_GATE,Gating control for PAD_CLKS clock tree in ABE" "PAD_CLKS_GATE_0,PAD_CLKS_GATE_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKSEL_OPP,Selects the OPP divider ABE domain" "CLKSEL_OPP_0,CLKSEL_OPP_1,CLKSEL_OPP_2,CLKSEL_OPP_3" group.long 0x10++0x03 line.long 0x00 "CM_DLL_CTRL,Special register for DLL control" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "DLL_OVERRIDE,Control if DLL lock and code outputs are overriden or not" "DLL_OVERRIDE_0,DLL_OVERRIDE_1" group.long 0x20++0x53 line.long 0x00 "CM_CLKMODE_DPLL_CORE,This register allows controlling the DPLL modes" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x00 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x00 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x00 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x00 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x00 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x00 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x00 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x00 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x00 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_CORE,This register allows monitoring DPLL activity" hexmask.long 0x04 5.--31. 1. "RESERVED," bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_CORE,This register provides automatic control over the DPLL activity" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_CORE,This register provides controls over the DPLL" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" rbitfld.long 0x0C 21. "RESERVED," "0,1" newline bitfld.long 0x0C 20. "DPLL_CLKOUTHIF_CLKSEL,Selects the source of the DPLL CLKOUTHIF clock" "DPLL_CLKOUTHIF_CLKSEL_0,DPLL_CLKOUTHIF_CLKSEL_1" rbitfld.long 0x0C 19. "RESERVED," "0,1" newline hexmask.long.word 0x0C 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x0C 7. "RESERVED," "0,1" newline hexmask.long.byte 0x0C 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_CORE,This register provides controls over the M2 divider of DPLL_CORE" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED," rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x10 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "CM_DIV_M3_DPLL_CORE,This register provides controls over the M3 divider of the DPLL" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," rbitfld.long 0x14 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x14 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x18 "CM_DIV_H11_DPLL_CORE,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," rbitfld.long 0x18 9. "CLKST,HSDIVIDER1 CLKOUT1 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x18 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--5. "DIVHS,DPLL (H11+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x1C "CM_DIV_H12_DPLL_CORE,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER1 DPLL_CORE" hexmask.long.tbyte 0x1C 10.--31. 1. "RESERVED,Reserved" rbitfld.long 0x1C 9. "CLKST,HSDIVIDER1 CLKOUT2 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x1C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--5. "DIVHS,DPLL (H12+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x20 "CM_DIV_H13_DPLL_CORE,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER1" hexmask.long.tbyte 0x20 10.--31. 1. "RESERVED,Reserved" rbitfld.long 0x20 9. "CLKST,HSDIVIDER1 CLKOUT3 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x20 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x20 0.--5. "DIVHS,DPLL (H13+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x24 "CM_DIV_H14_DPLL_CORE,This register provides controls over the CLKOUT4 o/p of the HSDIVIDER1 DPLL_CORE" hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED," rbitfld.long 0x24 9. "CLKST,HSDIVIDER1 CLKOUT4 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x24 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--5. "DIVHS,DPLL (H14+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x28 "CM_SSC_DELTAMSTEP_DPLL_CORE,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x28 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x28 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x2C "CM_SSC_MODFREQDIV_DPLL_CORE,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x2C 11.--31. 1. "RESERVED," bitfld.long 0x2C 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x2C 7. "RESERVED," "0,1" hexmask.long.byte 0x2C 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x30 "CM_DIV_H21_DPLL_CORE,This register provides controls over the CLKOUT1 o/p of the 2nd HSDIVIDER" hexmask.long.tbyte 0x30 10.--31. 1. "RESERVED," rbitfld.long 0x30 9. "CLKST,HSDIVIDER2 CLKOUT2 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x30 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x30 0.--5. "DIVHS,DPLL (H21+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x34 "CM_DIV_H22_DPLL_CORE,This register provides controls over the CLKOUT2 o/p of the 2nd HSDIVIDER DPLL_CORE" hexmask.long.tbyte 0x34 10.--31. 1. "RESERVED," rbitfld.long 0x34 9. "CLKST,HSDIVIDER2 CLKOUT2 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x34 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x34 0.--5. "DIVHS,DPLL (H22+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x38 "CM_DIV_H23_DPLL_CORE,This register provides controls over the CLKOUT3 o/p of the 2nd HSDIVIDER DPLL_CORE" hexmask.long.tbyte 0x38 10.--31. 1. "RESERVED," rbitfld.long 0x38 9. "CLKST,HSDIVIDER2 CLKOUT3 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x38 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x38 0.--5. "DIVHS,DPLL (H23+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x3C "CM_DIV_H24_DPLL_CORE,This register provides controls over the CLKOUT4 o/p of the 2nd HSDIVIDER DPLL_CORE" hexmask.long.tbyte 0x3C 10.--31. 1. "RESERVED," rbitfld.long 0x3C 9. "CLKST,HSDIVIDER2 CLKOUT4 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x3C 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x3C 0.--5. "DIVHS,DPLL (H24+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x40 "CM_CLKMODE_DPLL_MPU,This register allows controlling the DPLL modes" hexmask.long.word 0x40 16.--31. 1. "RESERVED," bitfld.long 0x40 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x40 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x40 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x40 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x40 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x40 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x40 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x40 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x40 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x40 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x40 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x44 "CM_IDLEST_DPLL_MPU,This register allows monitoring DPLL activity" hexmask.long 0x44 5.--31. 1. "RESERVED," bitfld.long 0x44 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x44 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x44 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x48 "CM_AUTOIDLE_DPLL_MPU,This register provides automatic control over the DPLL activity" hexmask.long 0x48 3.--31. 1. "RESERVED," bitfld.long 0x48 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x4C "CM_CLKSEL_DPLL_MPU,This register provides controls over the DPLL" hexmask.long.byte 0x4C 24.--31. 1. "RESERVED," rbitfld.long 0x4C 23. "DPLL_BYP_CLKSEL,Only CLKINPULOW bypass clock supported for this PLL" "0,1" newline bitfld.long 0x4C 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,DCC_EN_1" rbitfld.long 0x4C 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4C 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x4C 7. "RESERVED," "0,1" newline hexmask.long.byte 0x4C 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x50 "CM_DIV_M2_DPLL_MPU,This register provides controls over the M2 divider of the DPLL" hexmask.long.tbyte 0x50 10.--31. 1. "RESERVED," rbitfld.long 0x50 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x50 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x50 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x88++0x07 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_MPU,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x00 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_MPU,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED," bitfld.long 0x04 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED," "0,1" hexmask.long.byte 0x04 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" group.long 0x9C++0x1B line.long 0x00 "CM_BYPCLK_DPLL_MPU,Control MPU PLL BYPASS clock" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 0.--1. "CLKSEL,Select the DPLL MPU bypass clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" line.long 0x04 "CM_CLKMODE_DPLL_IVA,This register allows controlling the DPLL modes" hexmask.long.word 0x04 16.--31. 1. "RESERVED," bitfld.long 0x04 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x04 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x04 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x04 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x04 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x04 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x04 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x04 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x04 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x04 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x04 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x08 "CM_IDLEST_DPLL_IVA,This register allows monitoring DPLL activity" hexmask.long 0x08 5.--31. 1. "RESERVED," bitfld.long 0x08 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x08 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x08 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x0C "CM_AUTOIDLE_DPLL_IVA,This register provides automatic control over the DPLL activity" hexmask.long 0x0C 3.--31. 1. "RESERVED," bitfld.long 0x0C 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x10 "CM_CLKSEL_DPLL_IVA,This register provides controls over the DPLL" hexmask.long.byte 0x10 24.--31. 1. "RESERVED," bitfld.long 0x10 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x10 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" rbitfld.long 0x10 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x10 7. "RESERVED," "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x14 "CM_DIV_M2_DPLL_IVA,This register provides controls over the M2 divider of the DPLL" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," rbitfld.long 0x14 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x14 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x18 "CM_DIV_M3_DPLL_IVA,This register provides controls over the M3 divider of the DPLL" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," rbitfld.long 0x18 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x18 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0xC8++0x07 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_IVA,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x00 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_IVA,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED," bitfld.long 0x04 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED," "0,1" hexmask.long.byte 0x04 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" group.long 0xDC++0x1B line.long 0x00 "CM_BYPCLK_DPLL_IVA,Control IVA PLL BYPASS clock" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 0.--1. "CLKSEL,Select the DPLL IVA bypass clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" line.long 0x04 "CM_CLKMODE_DPLL_ABE,This register allows controlling the DPLL modes" hexmask.long.word 0x04 16.--31. 1. "RESERVED," bitfld.long 0x04 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x04 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x04 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x04 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" bitfld.long 0x04 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,DPLL_REGM4XEN_1" newline bitfld.long 0x04 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x04 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x04 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x04 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x04 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x04 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x08 "CM_IDLEST_DPLL_ABE,This register allows monitoring DPLL activity" hexmask.long 0x08 5.--31. 1. "RESERVED," bitfld.long 0x08 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x08 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x08 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x0C "CM_AUTOIDLE_DPLL_ABE,This register provides automatic control over the DPLL activity" hexmask.long 0x0C 3.--31. 1. "RESERVED," bitfld.long 0x0C 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x10 "CM_CLKSEL_DPLL_ABE,This register provides controls over the DPLL" hexmask.long.byte 0x10 24.--31. 1. "RESERVED," rbitfld.long 0x10 23. "DPLL_BYP_CLKSEL,Only CLKINPULOW bypass clock supported for this PLL" "0,1" newline rbitfld.long 0x10 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" rbitfld.long 0x10 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x10 7. "RESERVED," "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x14 "CM_DIV_M2_DPLL_ABE,This register provides controls over the H12 divider of the DPLL_DDR" hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED," rbitfld.long 0x14 11. "CLKX2ST,DPLL CLKOUTX2 status" "CLKX2ST_0,CLKX2ST_1" newline rbitfld.long 0x14 10. "RESERVED," "0,1" rbitfld.long 0x14 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x14 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x18 "CM_DIV_M3_DPLL_ABE,This register provides controls over the M3 divider of the DPLL" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," rbitfld.long 0x18 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x18 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x108++0x4F line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_ABE,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x00 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_ABE,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED," bitfld.long 0x04 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED," "0,1" hexmask.long.byte 0x04 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x08 "CM_CLKMODE_DPLL_DDR,This register allows controlling the DPLL modes" hexmask.long.word 0x08 16.--31. 1. "RESERVED," bitfld.long 0x08 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x08 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x08 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x08 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x08 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x08 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x08 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x08 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x08 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x08 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x08 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x0C "CM_IDLEST_DPLL_DDR,This register allows monitoring DPLL activity" hexmask.long 0x0C 5.--31. 1. "RESERVED," bitfld.long 0x0C 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x0C 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x0C 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x10 "CM_AUTOIDLE_DPLL_DDR,This register provides automatic control over the DPLL activity" hexmask.long 0x10 3.--31. 1. "RESERVED," bitfld.long 0x10 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x14 "CM_CLKSEL_DPLL_DDR,This register provides controls over the DPLL" hexmask.long.byte 0x14 24.--31. 1. "RESERVED," bitfld.long 0x14 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline bitfld.long 0x14 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,DCC_EN_1" rbitfld.long 0x14 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x14 7. "RESERVED," "0,1" newline hexmask.long.byte 0x14 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x18 "CM_DIV_M2_DPLL_DDR,This register provides controls over the M2 divider of DPLL_DDR" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," rbitfld.long 0x18 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x18 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x1C "CM_DIV_M3_DPLL_DDR,This register provides controls over the M3 divider of DPLL_DDR" hexmask.long.tbyte 0x1C 10.--31. 1. "RESERVED," rbitfld.long 0x1C 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x1C 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x20 "CM_DIV_H11_DPLL_DDR,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1 DPLL_DDR" hexmask.long.tbyte 0x20 10.--31. 1. "RESERVED," rbitfld.long 0x20 9. "CLKST,HSDIVIDER1 CLKOUT1 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x20 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x20 0.--5. "DIVHS,DPLL (H11+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x24 "CM_SSC_DELTAMSTEP_DPLL_DDR,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x24 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x24 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x28 "CM_SSC_MODFREQDIV_DPLL_DDR,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x28 11.--31. 1. "RESERVED," bitfld.long 0x28 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x28 7. "RESERVED," "0,1" hexmask.long.byte 0x28 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x2C "CM_CLKMODE_DPLL_DSP,This register allows controlling the DPLL modes" hexmask.long.word 0x2C 16.--31. 1. "RESERVED," bitfld.long 0x2C 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x2C 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x2C 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x2C 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x2C 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x2C 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x2C 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x2C 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x2C 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x2C 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x2C 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x30 "CM_IDLEST_DPLL_DSP,This register allows monitoring DPLL activity" hexmask.long 0x30 5.--31. 1. "RESERVED," bitfld.long 0x30 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x30 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x30 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x34 "CM_AUTOIDLE_DPLL_DSP,This register provides automatic control over the DPLL activity" hexmask.long 0x34 3.--31. 1. "RESERVED," bitfld.long 0x34 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x38 "CM_CLKSEL_DPLL_DSP,This register provides controls over the DPLL" hexmask.long.byte 0x38 24.--31. 1. "RESERVED," bitfld.long 0x38 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x38 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" rbitfld.long 0x38 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x38 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x38 7. "RESERVED," "0,1" newline hexmask.long.byte 0x38 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x3C "CM_DIV_M2_DPLL_DSP,This register provides controls over the M3 divider of DPLL_EVE_VID_DSP" hexmask.long.tbyte 0x3C 10.--31. 1. "RESERVED," rbitfld.long 0x3C 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x3C 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x3C 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x40 "CM_DIV_M3_DPLL_DSP,This register provides controls over the M3 divider of DPLL_CORE" hexmask.long.tbyte 0x40 10.--31. 1. "RESERVED," rbitfld.long 0x40 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x40 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x40 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x44 "CM_SSC_DELTAMSTEP_DPLL_DSP,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x44 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x44 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x48 "CM_SSC_MODFREQDIV_DPLL_DSP,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x48 11.--31. 1. "RESERVED," bitfld.long 0x48 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x48 7. "RESERVED," "0,1" hexmask.long.byte 0x48 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x4C "CM_BYPCLK_DPLL_DSP,Control IVA PLL BYPASS clock" hexmask.long 0x4C 2.--31. 1. "RESERVED," bitfld.long 0x4C 0.--1. "CLKSEL,Select the DPLL IVA bypass clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" group.long 0x160++0x07 line.long 0x00 "CM_SHADOW_FREQ_CONFIG1,Shadow register to program new DPLL configuration affecting EMIF and GPMC (L3 clock) functional frequency during DVFS" hexmask.long.word 0x00 19.--31. 1. "RESERVED," bitfld.long 0x00 16.--18. "DPLL_DDR_DPLL_EN,Shadow register forCM_CLKMODE_DPLL_DDR.DPLL_EN" "DPLL_DDR_DPLL_EN_0,DPLL_DDR_DPLL_EN_1,DPLL_DDR_DPLL_EN_2,DPLL_DDR_DPLL_EN_3,DPLL_DDR_DPLL_EN_4,DPLL_DDR_DPLL_EN_5,DPLL_DDR_DPLL_EN_6,DPLL_DDR_DPLL_EN_7" newline bitfld.long 0x00 11.--15. "DPLL_DDR_M2_DIV,Shadow register forCM_DIV_M2_DPLL_DDR.DIVHS" "DPLL_DDR_M2_DIV_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" hexmask.long.byte 0x00 4.--10. 1. "RESERVED," newline bitfld.long 0x00 3. "DLL_RESET,Specify if DLL should be reset or not during the frequency change hardware sequence" "DLL_RESET_0,DLL_RESET_1" bitfld.long 0x00 2. "DLL_OVERRIDE,Shadow register forCM_DLL_CTRL.DLL_OVERRIDE.The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to '1'" "DLL_OVERRIDE_0,DLL_OVERRIDE_1" newline rbitfld.long 0x00 1. "RESERVED," "0,1" bitfld.long 0x00 0. "FREQ_UPDATE,Writing '1' indicates that a new configuration is available" "0,1" line.long 0x04 "CM_SHADOW_FREQ_CONFIG2,Shadow register to program new DPLL configuration affecting GPMC (L3 clock) functional frequency during DVFS" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," bitfld.long 0x04 2.--7. "DPLL_CORE_H12_DIV,Shadow register forCM_DIV_H12_DPLL_CORE.DIVHS" "DPLL_CORE_H12_DIV_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 1. "CLKSEL_L3,Shadow register forCM_CLKSEL_CORE.CLKSEL_L3" "CLKSEL_L3_0,CLKSEL_L3_1" bitfld.long 0x04 0. "GPMC_FREQ_UPDATE,Controls whether or not GPMC has to be put automatically into idle during the frequency change operation" "GPMC_FREQ_UPDATE_0,GPMC_FREQ_UPDATE_1" group.long 0x170++0x03 line.long 0x00 "CM_DYN_DEP_PRESCAL,Control the time unit of the sliding window for dynamic dependencies (auto-sleep feature)" hexmask.long 0x00 6.--31. 1. "RESERVED," bitfld.long 0x00 0.--5. "PRESCAL,Time unit is equal to (PRESCAL + 1) L4 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x180++0x77 line.long 0x00 "CM_RESTORE_ST,Automatic restore status" hexmask.long 0x00 3.--31. 1. "RESERVED," bitfld.long 0x00 2. "PHASE2B_COMPLETED,Indicates if restore phase 2b is completed" "0,1" newline bitfld.long 0x00 1. "PHASE2A_COMPLETED,Indicates if restore phase 2a is completed" "0,1" bitfld.long 0x00 0. "PHASE1_COMPLETED,Indicates if restore phase 1 is completed" "0,1" line.long 0x04 "CM_CLKMODE_DPLL_EVE,This register allows controlling the DPLL modes" hexmask.long.word 0x04 16.--31. 1. "RESERVED," bitfld.long 0x04 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x04 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x04 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x04 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x04 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x04 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x04 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x04 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x04 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x04 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x04 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x08 "CM_IDLEST_DPLL_EVE,This register allows monitoring DPLL activity" hexmask.long 0x08 5.--31. 1. "RESERVED," bitfld.long 0x08 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x08 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x08 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x0C "CM_AUTOIDLE_DPLL_EVE,This register provides automatic control over the DPLL activity" hexmask.long 0x0C 3.--31. 1. "RESERVED," bitfld.long 0x0C 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x10 "CM_CLKSEL_DPLL_EVE,This register provides controls over the DPLL" hexmask.long.byte 0x10 24.--31. 1. "RESERVED," bitfld.long 0x10 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x10 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" rbitfld.long 0x10 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x10 7. "RESERVED," "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x14 "CM_DIV_M2_DPLL_EVE,This register provides controls over the M2 divider of the DPLL" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," rbitfld.long 0x14 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x14 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x18 "CM_DIV_M3_DPLL_EVE,This register provides controls over the M3 divider of the DPLL" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," rbitfld.long 0x18 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x18 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x1C "CM_SSC_DELTAMSTEP_DPLL_EVE,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x1C 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x1C 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x20 "CM_SSC_MODFREQDIV_DPLL_EVE,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x20 11.--31. 1. "RESERVED," bitfld.long 0x20 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 7. "RESERVED," "0,1" hexmask.long.byte 0x20 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x24 "CM_BYPCLK_DPLL_EVE,Control IVA PLL BYPASS clock" hexmask.long 0x24 2.--31. 1. "RESERVED," bitfld.long 0x24 0.--1. "CLKSEL,Select the DPLL IVA bypass clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" line.long 0x28 "CM_CLKMODE_DPLL_GMAC,This register allows controlling the DPLL modes" hexmask.long.word 0x28 16.--31. 1. "RESERVED," bitfld.long 0x28 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x28 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x28 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x28 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x28 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x28 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x28 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x28 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x28 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x28 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x28 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x2C "CM_IDLEST_DPLL_GMAC,This register allows monitoring DPLL activity" hexmask.long 0x2C 5.--31. 1. "RESERVED," bitfld.long 0x2C 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x2C 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x2C 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x30 "CM_AUTOIDLE_DPLL_GMAC,This register provides automatic control over the DPLL activity" hexmask.long 0x30 3.--31. 1. "RESERVED," bitfld.long 0x30 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x34 "CM_CLKSEL_DPLL_GMAC,This register provides controls over the DPLL" hexmask.long.byte 0x34 24.--31. 1. "RESERVED," bitfld.long 0x34 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline bitfld.long 0x34 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,DCC_EN_1" rbitfld.long 0x34 21. "RESERVED," "0,1" newline bitfld.long 0x34 20. "DPLL_CLKOUTHIF_CLKSEL,Selects the source of the DPLL CLKOUTHIF clock" "DPLL_CLKOUTHIF_CLKSEL_0,DPLL_CLKOUTHIF_CLKSEL_1" rbitfld.long 0x34 19. "RESERVED," "0,1" newline hexmask.long.word 0x34 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x34 7. "RESERVED," "0,1" newline hexmask.long.byte 0x34 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x38 "CM_DIV_M2_DPLL_GMAC,This register provides controls over the M2 divider of DPLL_GMAC_DSP" hexmask.long.tbyte 0x38 10.--31. 1. "RESERVED," rbitfld.long 0x38 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x38 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x38 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x3C "CM_DIV_M3_DPLL_GMAC,This register provides controls over the M3 divider of DPLL_GMAC_DSP" hexmask.long.tbyte 0x3C 10.--31. 1. "RESERVED," rbitfld.long 0x3C 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x3C 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x3C 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x40 "CM_DIV_H11_DPLL_GMAC,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1 DPLL_GMAC_DSP" hexmask.long.tbyte 0x40 10.--31. 1. "RESERVED," rbitfld.long 0x40 9. "CLKST,HSDIVIDER1 CLKOUT1 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x40 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x40 0.--5. "DIVHS,DPLL (H11+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x44 "CM_DIV_H12_DPLL_GMAC,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER1 DPLL_GMAC_DSP" hexmask.long.tbyte 0x44 10.--31. 1. "RESERVED,Reserved" rbitfld.long 0x44 9. "CLKST,HSDIVIDER1 CLKOUT2 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x44 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x44 0.--5. "DIVHS,DPLL (H12+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x48 "CM_DIV_H13_DPLL_GMAC,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER1 DPLL_GMAC_DSP" hexmask.long.tbyte 0x48 10.--31. 1. "RESERVED,Reserved" rbitfld.long 0x48 9. "CLKST,HSDIVIDER1 CLKOUT3 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x48 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x48 0.--5. "DIVHS,DPLL (H13+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x4C "CM_DIV_H14_DPLL_GMAC,This register provides controls over the CLKOUT4 o/p of the HSDIVIDER1 DPLL_GMAC_DSP" hexmask.long.tbyte 0x4C 10.--31. 1. "RESERVED," rbitfld.long 0x4C 9. "CLKST,HSDIVIDER1 CLKOUT4 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x4C 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x4C 0.--5. "DIVHS,DPLL (H14+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x50 "CM_SSC_DELTAMSTEP_DPLL_GMAC,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x50 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x50 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x54 "CM_SSC_MODFREQDIV_DPLL_GMAC,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x54 11.--31. 1. "RESERVED," bitfld.long 0x54 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x54 7. "RESERVED," "0,1" hexmask.long.byte 0x54 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x58 "CM_CLKMODE_DPLL_GPU,This register allows controlling the DPLL modes" hexmask.long.word 0x58 16.--31. 1. "RESERVED," bitfld.long 0x58 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x58 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x58 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x58 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x58 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x58 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x58 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x58 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x58 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x58 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x58 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x5C "CM_IDLEST_DPLL_GPU,This register allows monitoring DPLL activity" hexmask.long 0x5C 5.--31. 1. "RESERVED," bitfld.long 0x5C 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x5C 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x5C 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x60 "CM_AUTOIDLE_DPLL_GPU,This register provides automatic control over the DPLL activity" hexmask.long 0x60 3.--31. 1. "RESERVED," bitfld.long 0x60 0.--2. "AUTO_DPLL_MODE,DPLL automatic control" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x64 "CM_CLKSEL_DPLL_GPU,This register provides controls over the DPLL" hexmask.long.byte 0x64 24.--31. 1. "RESERVED," bitfld.long 0x64 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x64 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" rbitfld.long 0x64 21. "RESERVED," "0,1" newline bitfld.long 0x64 20. "DPLL_CLKOUTHIF_CLKSEL,Selects the source of the DPLL CLKOUTHIF clock" "DPLL_CLKOUTHIF_CLKSEL_0,DPLL_CLKOUTHIF_CLKSEL_1" rbitfld.long 0x64 19. "RESERVED," "0,1" newline hexmask.long.word 0x64 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x64 7. "RESERVED," "0,1" newline hexmask.long.byte 0x64 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x68 "CM_DIV_M2_DPLL_GPU,This register provides controls over the M2 divider of the DPLL" hexmask.long.tbyte 0x68 10.--31. 1. "RESERVED," rbitfld.long 0x68 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x68 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x68 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x6C "CM_DIV_M3_DPLL_GPU,This register provides controls over the M3 divider of the DPLL" hexmask.long.tbyte 0x6C 10.--31. 1. "RESERVED," rbitfld.long 0x6C 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x6C 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x6C 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x70 "CM_SSC_DELTAMSTEP_DPLL_GPU,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x70 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x70 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x74 "CM_SSC_MODFREQDIV_DPLL_GPU,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x74 11.--31. 1. "RESERVED," bitfld.long 0x74 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x74 7. "RESERVED," "0,1" hexmask.long.byte 0x74 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" width 0x0B tree.end tree "CKGEN_PRM" base ad:0x4AE06100 group.long 0x00++0x03 line.long 0x00 "CM_CLKSEL_SYSCLK1,Select the SYS CLK for SYSCLK1_32K_CLK" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1" group.long 0x08++0x33 line.long 0x00 "CM_CLKSEL_WKUPAON,Control the functional clock source of WKUPAON. PRM and Smart Reflex functional clock" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "CLKSEL,Select the clock source for WKUPAON_ICLK clock" "CLKSEL_0,CLKSEL_1" line.long 0x04 "CM_CLKSEL_ABE_PLL_REF,Control the source of the reference clock for DPLL_ABE" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "CLKSEL,Select the source for the DPLL_ABE reference clock" "CLKSEL_0,CLKSEL_1" line.long 0x08 "CM_CLKSEL_SYS,Software (ROM Code) sets the SYS_CLK configuration corresponding to the frequency of SYS_CLK" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 0.--2. "SYS_CLKSEL,System clock input selection" "SYS_CLKSEL_0,SYS_CLKSEL_1,SYS_CLKSEL_2,SYS_CLKSEL_3,SYS_CLKSEL_4,SYS_CLKSEL_5,SYS_CLKSEL_6,SYS_CLKSEL_7" line.long 0x0C "CM_CLKSEL_ABE_PLL_BYPAS,Control the source of the bypass clock for DPLL_ABE" hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "CLKSEL,Control the source of the bypass clock for DPLL_ABE" "CLKSEL_0,CLKSEL_1" line.long 0x10 "CM_CLKSEL_ABE_PLL_SYS,Control the source of the SYS clock for DPLL_ABE" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "CLKSEL,Select the SYS clock for the DPLL_ABE reference and bypass clock" "CLKSEL_0,CLKSEL_1" line.long 0x14 "CM_CLKSEL_ABE_24M,Select the ABE_24M_FCLK for TIMERS subsystems" hexmask.long 0x14 1.--31. 1. "RESERVED," bitfld.long 0x14 0. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1" line.long 0x18 "CM_CLKSEL_ABE_SYS,Select the ABE_SYS_CLK" hexmask.long 0x18 1.--31. 1. "RESERVED," bitfld.long 0x18 0. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1" line.long 0x1C "CM_CLKSEL_HDMI_MCASP_AUX,Select the SYS_CLK1 for MCASP modules" hexmask.long 0x1C 3.--31. 1. "RESERVED," bitfld.long 0x1C 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x20 "CM_CLKSEL_HDMI_TIMER,Select the SYS_CLK1 for TIMER subsystems" hexmask.long 0x20 3.--31. 1. "RESERVED," bitfld.long 0x20 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x24 "CM_CLKSEL_MCASP_SYS,Select the SYS CLK for ABE_24M_FCLK" hexmask.long 0x24 1.--31. 1. "RESERVED," bitfld.long 0x24 0. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1" line.long 0x28 "CM_CLKSEL_MLBP_MCASP,Select the MLBP_CLK for MCASP subsystems" hexmask.long 0x28 3.--31. 1. "RESERVED," bitfld.long 0x28 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x2C "CM_CLKSEL_MLB_MCASP,Select the SYS_CLK1 for MCASP" hexmask.long 0x2C 3.--31. 1. "RESERVED," bitfld.long 0x2C 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x30 "CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX,Select the L4_ICLK (SR2.0) for MCASP modules" hexmask.long 0x30 3.--31. 1. "RESERVED," bitfld.long 0x30 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" group.long 0x40++0x3B line.long 0x00 "CM_CLKSEL_SYS_CLK1_32K,Control the source of the FUNC_32K_CLK clock for GPIO. WD_TIMER. KBD. etc" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "CLKSEL,Select the FUNC_32K_CLK clock" "CLKSEL_0,CLKSEL_1" line.long 0x04 "CM_CLKSEL_TIMER_SYS,Select the TIMER_SYS_CLK for TIMER modules" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1" line.long 0x08 "CM_CLKSEL_VIDEO1_MCASP_AUX,Select the SYS_CLK1 for MCASP modules" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x0C "CM_CLKSEL_VIDEO1_TIMER,Select the SYS_CLK1 for TIMER subsystems" hexmask.long 0x0C 3.--31. 1. "RESERVED," bitfld.long 0x0C 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x10 "CM_CLKSEL_VIDEO2_MCASP_AUX,Select the SYS_CLK1 for MCASP modules" hexmask.long 0x10 3.--31. 1. "RESERVED," bitfld.long 0x10 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x14 "CM_CLKSEL_VIDEO2_TIMER,Select the SYS_CLK1 for TIMER subsystems" hexmask.long 0x14 3.--31. 1. "RESERVED," bitfld.long 0x14 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x18 "CM_CLKSEL_CLKOUTMUX0,Control the source of the CLKOUTMUX0" hexmask.long 0x18 5.--31. 1. "RESERVED," bitfld.long 0x18 0.--4. "CLKSEL,Select the source of" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15,CLKSEL_16,CLKSEL_17,CLKSEL_18,CLKSEL_19,CLKSEL_20,?,?,?,?,?,?,?,?,?,?,?" line.long 0x1C "CM_CLKSEL_CLKOUTMUX1,Control the source of the CLKOUTMUX1" hexmask.long 0x1C 5.--31. 1. "RESERVED," bitfld.long 0x1C 0.--4. "CLKSEL,Select the source of" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15,CLKSEL_16,CLKSEL_17,CLKSEL_18,CLKSEL_19,CLKSEL_20,CLKSEL_21,?,?,?,?,?,?,?,?,?,?" line.long 0x20 "CM_CLKSEL_CLKOUTMUX2,Control the source of the CLKOUTMUX2" hexmask.long 0x20 5.--31. 1. "RESERVED," bitfld.long 0x20 0.--4. "CLKSEL,Select the source of" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15,CLKSEL_16,CLKSEL_17,CLKSEL_18,CLKSEL_19,CLKSEL_20,CLKSEL_21,?,?,?,?,?,?,?,?,?,?" line.long 0x24 "CM_CLKSEL_HDMI_PLL_SYS,Control the source of the SYS clock for DPLL_HDMI" hexmask.long 0x24 1.--31. 1. "RESERVED," bitfld.long 0x24 0. "CLKSEL,Select the SYS clock for the DPLL_HDMI" "CLKSEL_0,CLKSEL_1" line.long 0x28 "CM_CLKSEL_VIDEO1_PLL_SYS,Control the source of the SYS clock for DPLL_VIDEO1" hexmask.long 0x28 1.--31. 1. "RESERVED," bitfld.long 0x28 0. "CLKSEL,Select the SYS clock for the DPLL_VIDEO1" "CLKSEL_0,CLKSEL_1" line.long 0x2C "CM_CLKSEL_VIDEO2_PLL_SYS,Control the source of the SYS clock for DPLL_VIDEO1" hexmask.long 0x2C 1.--31. 1. "RESERVED," bitfld.long 0x2C 0. "CLKSEL,Select the SYS clock for the DPLL_VIDEO2" "CLKSEL_0,CLKSEL_1" line.long 0x30 "CM_CLKSEL_ABE_CLK_DIV,Select the ABE_CLK" hexmask.long 0x30 3.--31. 1. "RESERVED," bitfld.long 0x30 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x34 "CM_CLKSEL_ABE_GICLK_DIV,Select the ABE_GICLK" hexmask.long 0x34 1.--31. 1. "RESERVED," bitfld.long 0x34 0. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1" line.long 0x38 "CM_CLKSEL_AESS_FCLK_DIV,Select the AESS_FCLK" hexmask.long 0x38 1.--31. 1. "RESERVED," bitfld.long 0x38 0. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1" group.long 0x80++0x63 line.long 0x00 "CM_CLKSEL_EVE_CLK,Controls the source of the EVE_CLK for EVE" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "CLKSEL,Selects the EVE_CLK for EVE" "CLKSEL_0,CLKSEL_1" line.long 0x04 "CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX,Select the USB_OTG_CLK" hexmask.long 0x04 3.--31. 1. "RESERVED," bitfld.long 0x04 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x08 "CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX,Select the CORE_DPLL_OUT_CLK" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x0C "CM_CLKSEL_DSP_GFCLK_CLKOUTMUX,Select the DSP_GFCLK" hexmask.long 0x0C 3.--31. 1. "RESERVED," bitfld.long 0x0C 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x10 "CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX,Select the EMIF_PHY_GCLK" hexmask.long 0x10 3.--31. 1. "RESERVED," bitfld.long 0x10 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x14 "CM_CLKSEL_EMU_CLK_CLKOUTMUX,Select the EMU_CLK" hexmask.long 0x14 3.--31. 1. "RESERVED," bitfld.long 0x14 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x18 "CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX,Select the FUNC_96M_AON_CLK" hexmask.long 0x18 3.--31. 1. "RESERVED," bitfld.long 0x18 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x1C "CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX,Select the GMAC_250M_CLK" hexmask.long 0x1C 3.--31. 1. "RESERVED," bitfld.long 0x1C 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x20 "CM_CLKSEL_GPU_GCLK_CLKOUTMUX,Select the GPU_GCLK" hexmask.long 0x20 3.--31. 1. "RESERVED," bitfld.long 0x20 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x24 "CM_CLKSEL_HDMI_CLK_CLKOUTMUX,Select the HDMI_CLK" hexmask.long 0x24 3.--31. 1. "RESERVED," bitfld.long 0x24 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x28 "CM_CLKSEL_IVA_GCLK_CLKOUTMUX,Select the IVA_GCLK" hexmask.long 0x28 3.--31. 1. "RESERVED," bitfld.long 0x28 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x2C "CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX,Select the L3INIT_480M_GFCLK" hexmask.long 0x2C 3.--31. 1. "RESERVED," bitfld.long 0x2C 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x30 "CM_CLKSEL_MPU_GCLK_CLKOUTMUX,Select the MPU_GCLK" hexmask.long 0x30 3.--31. 1. "RESERVED," bitfld.long 0x30 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x34 "CM_CLKSEL_PCIE1_CLK_CLKOUTMUX,Select the PCIE1_CLK" hexmask.long 0x34 3.--31. 1. "RESERVED," bitfld.long 0x34 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x38 "CM_CLKSEL_PCIE2_CLK_CLKOUTMUX,Select the PCIE2_CLK" hexmask.long 0x38 3.--31. 1. "RESERVED," bitfld.long 0x38 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x3C "CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX,Select the PER_ABE_X1_CLK" hexmask.long 0x3C 3.--31. 1. "RESERVED," bitfld.long 0x3C 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x40 "CM_CLKSEL_SATA_CLK_CLKOUTMUX,Select the SATA_CLK" hexmask.long 0x40 3.--31. 1. "RESERVED," bitfld.long 0x40 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x44 "CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX,Select the RCOSC_32K_CLK" hexmask.long 0x44 3.--31. 1. "RESERVED," bitfld.long 0x44 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x48 "CM_CLKSEL_SYS_CLK1_CLKOUTMUX,Select the SYS_CLK1" hexmask.long 0x48 3.--31. 1. "RESERVED," bitfld.long 0x48 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x4C "CM_CLKSEL_SYS_CLK2_CLKOUTMUX,Select the SYS_CLK2" hexmask.long 0x4C 3.--31. 1. "RESERVED," bitfld.long 0x4C 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x50 "CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX,Select the VIDEO1_CLK" hexmask.long 0x50 3.--31. 1. "RESERVED," bitfld.long 0x50 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x54 "CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX,Select the VIDEO2_CLK" hexmask.long 0x54 3.--31. 1. "RESERVED," bitfld.long 0x54 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x58 "CM_CLKSEL_ABE_LP_CLK,Select the ABE_LP_CLK" hexmask.long 0x58 1.--31. 1. "RESERVED," bitfld.long 0x58 0. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1" line.long 0x5C "CM_CLKSEL_ADC_GFCLK,Control the source of the ADC_GFCLK clock for" hexmask.long 0x5C 2.--31. 1. "RESERVED," bitfld.long 0x5C 0.--1. "CLKSEL,Select the SYS clock for the DPLL_ABE reference and bypass clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" line.long 0x60 "CM_CLKSEL_EVE_GFCLK_CLKOUTMUX,Select the EVE_GFCLK" hexmask.long 0x60 3.--31. 1. "RESERVED," bitfld.long 0x60 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" width 0x0B tree.end tree "CLK1_DSP1_EDMA_BW_LIMITER" base ad:0x44804B00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_DSP1_MDMA_BW_LIMITER" base ad:0x44806A00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_DSP1_MDMA_BW_REGULATOR" base ad:0x44804C00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_DSP2_EDMA_BW_LIMITER" base ad:0x44804A00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_DSP2_MDMA_BW_LIMITER" base ad:0x44806B00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_DSP2_MDMA_BW_REGULATOR" base ad:0x44804D00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_EVE_TC0_BW_LIMITER" base ad:0x44806C00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_EVE_TC0_BW_REGULATOR" base ad:0x44804200 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_EVE_TC1_BW_LIMITER" base ad:0x44806D00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_EVE_TC1_BW_REGULATOR" base ad:0x44804600 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_FLAGMUX_CLK1" base ad:0x44805700 rgroup.long 0x00++0x0F line.long 0x00 "L3_FLAGMUX_TIMEOUT1_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_TIMEOUT1_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_TIMEOUT1_MASK0," hexmask.long.word 0x08 18.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x08 0.--17. 1. "MASK0,mask flag inputs 0 Type: Control" line.long 0x0C "L3_FLAGMUX_TIMEOUT1_REGERR0," hexmask.long.word 0x0C 18.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x0C 0.--17. 1. "REGERR0,flag inputs 0 Type: Status" rgroup.long 0x100++0x0F line.long 0x00 "L3_FLAGMUX_TIMEOUT2_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_TIMEOUT2_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_TIMEOUT2_MASK0," hexmask.long.word 0x08 16.--31. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "MASK0,mask flag inputs 0 Type: Control" line.long 0x0C "L3_FLAGMUX_TIMEOUT2_REGERR0," hexmask.long.word 0x0C 16.--31. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--15. 1. "REGERR0,flag inputs 0 Type: Status" width 0x0B tree.end tree "CLK1_FLAGMUX_CLK1_1" base ad:0x44803500 rgroup.long 0x00++0x17 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_MASK0," hexmask.long.word 0x08 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x08 0.--19. 1. "MASK0,Mask flag inputs 0 Type: Control" line.long 0x0C "L3_FLAGMUX_REGERR0," line.long 0x10 "L3_FLAGMUX_MASK1," hexmask.long.word 0x10 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x10 0.--19. 1. "MASK1,Mask flag inputs 1 Type: Control" line.long 0x14 "L3_FLAGMUX_REGERR1," width 0x0B tree.end tree "CLK1_FLAGMUX_CLK1_2" base ad:0x44803600 rgroup.long 0x00++0x17 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_MASK0," hexmask.long.word 0x08 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x08 0.--19. 1. "MASK0,Mask flag inputs 0 Type: Control" line.long 0x0C "L3_FLAGMUX_REGERR0," line.long 0x10 "L3_FLAGMUX_MASK1," hexmask.long.word 0x10 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x10 0.--19. 1. "MASK1,Mask flag inputs 1 Type: Control" line.long 0x14 "L3_FLAGMUX_REGERR1," width 0x0B tree.end tree "CLK1_FLAGMUX_CLK1MERGE" base ad:0x44800400 rgroup.long 0x00++0x17 line.long 0x00 "L3_FLAGMUX_CLK1MERGE_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_CLK1MERGE_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_CLK1MERGE_MASK0," hexmask.long 0x08 2.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--1. "MASK0,Mask flag inputs 0 Type: Control" "0,1,2,3" line.long 0x0C "L3_FLAGMUX_CLK1MERGE_REGERR0," hexmask.long 0x0C 2.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--1. "REGERR0,Flag inputs 0 Type: Control" "0,1,2,3" line.long 0x10 "L3_FLAGMUX_CLK1MERGE_MASK1," hexmask.long 0x10 2.--31. 1. "RESERVED," newline bitfld.long 0x10 0.--1. "MASK1,Mask flag inputs 0 Type: Control" "0,1,2,3" line.long 0x14 "L3_FLAGMUX_CLK1MERGE_REGERR1," hexmask.long 0x14 2.--31. 1. "RESERVED," newline bitfld.long 0x14 0.--1. "REGERR1,Flag inputs 0 Type: Control" "0,1,2,3" width 0x0B tree.end tree "CLK1_GMAC_SW_BW_REGULATOR" base ad:0x44805600 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_HOST_CLK1_1" base ad:0x44000000 rgroup.long 0x00++0x0B line.long 0x00 "L3_HOST_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_HOST_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_HOST_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 3.--31. 1. "RESERVED," newline bitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Fault is asserted when the Fault Control register field indicates a Fault and de-asserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0.--1. "RESERVED," "0,1,2,3" group.long 0x40++0x37 line.long 0x00 "L3_HOST_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_HOST_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED," newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED," newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_HOST_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_HOST_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_HOST_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_HOST_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_HOST_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_HOST_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED," newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,Type: Status" line.long 0x28 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Type: Status" line.long 0x2C "L3_HOST_STDERRLOG_CUSTOMINFO_WR," hexmask.long 0x2C 1.--31. 1. "RESERVED," newline bitfld.long 0x2C 0. "STDERRLOG_CUSTOMINFO_WR,Type: Status" "0,1" line.long 0x30 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR," hexmask.long.word 0x30 21.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x30 0.--20. 1. "STDERRLOG_CUSTOMINFO_ADDR,Type: Status" line.long 0x34 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR," hexmask.long 0x34 1.--31. 1. "RESERVED," newline bitfld.long 0x34 0. "STDERRLOG_CUSTOMINFO_DECERR,Type: Status" "0,1" width 0x0B tree.end tree "CLK1_HOST_CLK1_2" base ad:0x44800000 rgroup.long 0x00++0x0B line.long 0x00 "L3_HOST_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_HOST_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_HOST_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 3.--31. 1. "RESERVED," newline bitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Fault is asserted when the Fault Control register field indicates a Fault and de-asserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0.--1. "RESERVED," "0,1,2,3" group.long 0x40++0x37 line.long 0x00 "L3_HOST_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_HOST_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED," newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED," newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_HOST_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_HOST_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_HOST_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_HOST_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_HOST_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_HOST_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED," newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,Type: Status" line.long 0x28 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Type: Status" line.long 0x2C "L3_HOST_STDERRLOG_CUSTOMINFO_WR," hexmask.long 0x2C 1.--31. 1. "RESERVED," newline bitfld.long 0x2C 0. "STDERRLOG_CUSTOMINFO_WR,Type: Status" "0,1" line.long 0x30 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR," hexmask.long.word 0x30 21.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x30 0.--20. 1. "STDERRLOG_CUSTOMINFO_ADDR,Type: Status" line.long 0x34 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR," hexmask.long 0x34 1.--31. 1. "RESERVED," newline bitfld.long 0x34 0. "STDERRLOG_CUSTOMINFO_DECERR,Type: Status" "0,1" width 0x0B tree.end tree "CLK1_IPU_BW_LIMITER" base ad:0x44803C00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_IPU_BW_REGULATOR" base ad:0x44804E00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_ISS_NRT1_BW_LIMITER" base ad:0x44806F00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_ISS_NRT2_BW_LIMITER" base ad:0x44806E00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_MMU_BW_LIMITER" base ad:0x44803A00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_TPTC1_RD_BW_LIMITER" base ad:0x44807000 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_TPTC1_WR_BW_LIMITER" base ad:0x44807100 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_TPTC2_RD_BW_LIMITER" base ad:0x44807200 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_TPTC2_WR_BW_LIMITER" base ad:0x44807300 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK2_FLAGMUX_CLK2" base ad:0x45000400 rgroup.long 0x00++0x0F line.long 0x00 "L3_FLAGMUX_TIMEOUT_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_TIMEOUT_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_TIMEOUT_MASK0," hexmask.long 0x08 2.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--1. "MASK0,mask flag inputs 0 Type: Control" "0,1,2,3" line.long 0x0C "L3_FLAGMUX_TIMEOUT_REGERR0," hexmask.long 0x0C 2.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--1. "REGERR0,flag inputs 0 Type: Status" "0,1,2,3" width 0x0B tree.end tree "CLK2_FLAGMUX_CLK2_1" base ad:0x45000200 rgroup.long 0x00++0x17 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_MASK0," hexmask.long.word 0x08 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x08 0.--19. 1. "MASK0,Mask flag inputs 0 Type: Control" line.long 0x0C "L3_FLAGMUX_REGERR0," line.long 0x10 "L3_FLAGMUX_MASK1," hexmask.long.word 0x10 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x10 0.--19. 1. "MASK1,Mask flag inputs 1 Type: Control" line.long 0x14 "L3_FLAGMUX_REGERR1," width 0x0B tree.end tree "CLK2_FLAGMUX_STATCOLL" base ad:0x45000500 group.long 0x00++0x0F line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_STCOL_MASK0," hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," newline hexmask.long.word 0x08 0.--9. 1. "MASK0,mask flag inputs 0 Type: Control" line.long 0x0C "L3_STCOL_REGERR0," hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--9. 1. "REGERR0,flag inputs 0 Type: Status" width 0x0B tree.end tree "CLK2_HOST_CLK2_1" base ad:0x45000000 rgroup.long 0x00++0x0B line.long 0x00 "L3_HOST_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_HOST_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_HOST_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 3.--31. 1. "RESERVED," newline bitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Fault is asserted when the Fault Control register field indicates a Fault and de-asserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0.--1. "RESERVED," "0,1,2,3" group.long 0x40++0x37 line.long 0x00 "L3_HOST_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_HOST_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED," newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED," newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_HOST_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_HOST_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_HOST_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_HOST_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_HOST_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_HOST_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED," newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,Type: Status" line.long 0x28 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Type: Status" line.long 0x2C "L3_HOST_STDERRLOG_CUSTOMINFO_WR," hexmask.long 0x2C 1.--31. 1. "RESERVED," newline bitfld.long 0x2C 0. "STDERRLOG_CUSTOMINFO_WR,Type: Status" "0,1" line.long 0x30 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR," hexmask.long.word 0x30 21.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x30 0.--20. 1. "STDERRLOG_CUSTOMINFO_ADDR,Type: Status" line.long 0x34 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR," hexmask.long 0x34 1.--31. 1. "RESERVED," newline bitfld.long 0x34 0. "STDERRLOG_CUSTOMINFO_DECERR,Type: Status" "0,1" width 0x0B tree.end repeat 4. (list 1. 3. 2. 4. )(list ad:0x45002000 ad:0x45003000 ad:0x45004000 ad:0x45005000 ) tree "CLK2_STATCOLL$1" base $2 group.long 0x00++0x2F line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_STCOL_EN," hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x08 0. "EN,Enable performance monitoring this will also shut down the clock if En = 0 Type: Control" "0,1" line.long 0x0C "L3_STCOL_SOFTEN," hexmask.long 0x0C 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 0. "SOFTEN,Software enable for performance monitoring Type: Control" "0,1" line.long 0x10 "L3_STCOL_IGNORESUSPEND," hexmask.long 0x10 1.--31. 1. "RESERVED," newline bitfld.long 0x10 0. "IGNORESUSPEND,Ignore suspend if set to one for suspend mechanism Type: Control" "0,1" line.long 0x14 "L3_STCOL_TRIGEN," hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "TRIGEN,TrigEn when set it enable the external trigger start and stop Type: Control" "0,1" line.long 0x18 "L3_STCOL_REQEVT," hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x18 0.--3. "REQEVT,Req event select Type: Control" "REQEVT_0,REQEVT_1,REQEVT_2,REQEVT_3,REQEVT_4,REQEVT_5,REQEVT_6,REQEVT_7,REQEVT_8,?,?,?,?,?,?,?" line.long 0x1C "L3_STCOL_RSPEVT," hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 0.--3. "RSPEVT,Rsp event select Type: Control" "RSPEVT_0,RSPEVT_1,RSPEVT_2,RSPEVT_3,RSPEVT_4,RSPEVT_5,RSPEVT_6,RSPEVT_7,RSPEVT_8,?,?,?,?,?,?,?" line.long 0x20 "L3_STCOL_EVTMUX_SEL0," hexmask.long 0x20 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0.--2. "EVTMUX_SEL0,The select of the mux 0 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x24 "L3_STCOL_EVTMUX_SEL1," hexmask.long 0x24 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x24 0.--2. "EVTMUX_SEL1,The select of the mux 1 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x28 "L3_STCOL_EVTMUX_SEL2," hexmask.long 0x28 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x28 0.--2. "EVTMUX_SEL2,The select of the mux 2 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x2C "L3_STCOL_EVTMUX_SEL3," hexmask.long 0x2C 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--2. "EVTMUX_SEL3,The select of the mux 3 Type: Control" "0,1,2,3,4,5,6,7" rgroup.long 0x40++0x3B line.long 0x00 "L3_STCOL_DUMP_IDENTIFIER," hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--3. "DUMP_IDENTIFIER,Probe identifier Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "L3_STCOL_DUMP_COLLECTTIME," line.long 0x08 "L3_STCOL_DUMP_SLVADDR," hexmask.long 0x08 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x08 0.--6. 1. "DUMP_SLVADDR,Dump slave address Type: Control" line.long 0x0C "L3_STCOL_DUMP_MSTADDR," hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0C 0.--7. 1. "DUMP_MSTADDR,Dump master address Type: Control" line.long 0x10 "L3_STCOL_DUMP_SLVOFS," line.long 0x14 "L3_STCOL_DUMP_MODE," hexmask.long 0x14 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 1. "DUMP_MODE_CONDITIONAL,Define the stat conditional dump if one a dump will be generated when alarm is trigged Type: Control" "0,1" newline bitfld.long 0x14 0. "DUMP_MODE_MANUAL,Define the dump mode: if != 0 the dump is controlled by the Send register" "0,1" line.long 0x18 "L3_STCOL_DUMP_SEND," hexmask.long 0x18 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x18 0. "DUMP_SEND,In manual mode is used to send the dump content and initialize the counters" "0,1" line.long 0x1C "L3_STCOL_DUMP_DISABLE," hexmask.long 0x1C 1.--31. 1. "RESERVED," newline bitfld.long 0x1C 0. "DUMP_DISABLE,If 1 the dump frame will be disabled but counters still active.This is typically used when counters monitoring is enabled Type: Control" "0,1" line.long 0x20 "L3_STCOL_DUMP_ALARM_TRIG," hexmask.long 0x20 1.--31. 1. "RESERVED," newline bitfld.long 0x20 0. "DUMP_ALARM_TRIG,In Alarm Mode is used to reset Alarm Type: Take" "0,1" line.long 0x24 "L3_STCOL_DUMP_ALARM_MINVAL," line.long 0x28 "L3_STCOL_DUMP_ALARM_MAXVAL," line.long 0x2C "L3_STCOL_DUMP_ALARM_MODE0," hexmask.long 0x2C 2.--31. 1. "RESERVED," newline bitfld.long 0x2C 0.--1. "DUMP_ALARM_MODE0,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE0_0,DUMP_ALARM_MODE0_1,DUMP_ALARM_MODE0_2,DUMP_ALARM_MODE0_3" line.long 0x30 "L3_STCOL_DUMP_ALARM_MODE1," hexmask.long 0x30 2.--31. 1. "RESERVED," newline bitfld.long 0x30 0.--1. "DUMP_ALARM_MODE1,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE1_0,DUMP_ALARM_MODE1_1,DUMP_ALARM_MODE1_2,DUMP_ALARM_MODE1_3" line.long 0x34 "L3_STCOL_DUMP_ALARM_MODE2," hexmask.long 0x34 2.--31. 1. "RESERVED," newline bitfld.long 0x34 0.--1. "DUMP_ALARM_MODE2,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE2_0,DUMP_ALARM_MODE2_1,DUMP_ALARM_MODE2_2,DUMP_ALARM_MODE2_3" line.long 0x38 "L3_STCOL_DUMP_ALARM_MODE3," hexmask.long 0x38 2.--31. 1. "RESERVED," newline bitfld.long 0x38 0.--1. "DUMP_ALARM_MODE3,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE3_0,DUMP_ALARM_MODE3_1,DUMP_ALARM_MODE3_2,DUMP_ALARM_MODE3_3" group.long 0xAC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_0," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x204++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_1," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x35C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_2," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x4B4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_3," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0xB0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_0," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x208++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_1," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x360++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_2," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x4B8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_3," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0xB4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_0," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x20C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_1," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x364++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_2," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x4BC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_3," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0xB8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_0," hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x210++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_1," hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x368++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_2," hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x4C0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_3," hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0xBC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN0_0," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x214++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN0_1," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x36C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN0_2," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x4C4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN0_3," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0xC0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_RD_0," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x218++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_RD_1," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x370++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_RD_2," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x4C8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_RD_3," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xC4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_WR_0," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x21C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_WR_1," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x374++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_WR_2," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x4CC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_WR_3," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xC8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_MSTADDR_0," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK0_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x220++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_MSTADDR_1," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK0_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x378++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_MSTADDR_2," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK0_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x4D0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_MSTADDR_3," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK0_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xCC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_SLVADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK0_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x224++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_SLVADDR_1," hexmask.long 0x00 7.--31. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK0_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x37C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_SLVADDR_2," hexmask.long 0x00 7.--31. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK0_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x4D4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_SLVADDR_3," hexmask.long 0x00 7.--31. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK0_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0xD0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_ERR_0," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x228++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_ERR_1," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x380++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_ERR_2," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x4D8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_ERR_3," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xD4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_REQUSERINFO_0," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK0_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0x22C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_REQUSERINFO_1," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK0_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0x384++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_REQUSERINFO_2," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK0_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0x4DC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_REQUSERINFO_3," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK0_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0xD8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_RSPUSERINFO_0," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "FILTER_i_MASK0_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x230++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_RSPUSERINFO_1," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "FILTER_i_MASK0_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x388++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_RSPUSERINFO_2," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "FILTER_i_MASK0_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x4E0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_RSPUSERINFO_3," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "FILTER_i_MASK0_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xE0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_RD_0," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x238++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_RD_1," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x390++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_RD_2," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x4E8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_RD_3," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xE4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_WR_0," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x23C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_WR_1," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x394++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_WR_2," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x4EC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_WR_3," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xE8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_MSTADDR_0," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH0_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x240++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_MSTADDR_1," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH0_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x398++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_MSTADDR_2," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH0_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x4F0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_MSTADDR_3," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH0_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xEC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_SLVADDR_0," hexmask.long 0x00 5.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x244++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_SLVADDR_1," hexmask.long 0x00 5.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x39C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_SLVADDR_2," hexmask.long 0x00 5.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4F4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_SLVADDR_3," hexmask.long 0x00 5.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xF0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_ERR_0," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x248++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_ERR_1," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x3A0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_ERR_2," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x4F8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_ERR_3," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xF4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_REQUSERINFO_0," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK0_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0x24C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_REQUSERINFO_1," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK0_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0x3A4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_REQUSERINFO_2," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK0_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0x4FC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_REQUSERINFO_3," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK0_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0xF8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_RSPUSERINFO_0," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "FILTER_i_MASK0_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x250++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_RSPUSERINFO_1," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "FILTER_i_MASK0_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x3A8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_RSPUSERINFO_2," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "FILTER_i_MASK0_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x500++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_RSPUSERINFO_3," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "FILTER_i_MASK0_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x1F0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0," hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" group.long 0x348++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_1," hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" group.long 0x4A0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_2," hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" group.long 0x5F8++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_3," hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" group.long 0x1F4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0," hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x34C++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_1," hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x4A4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_2," hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x5FC++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_3," hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x1F8++0x03 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_0," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" group.long 0x350++0x03 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_1," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" group.long 0x4A8++0x03 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_2," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" group.long 0x600++0x03 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_3," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" group.long 0x1FC++0x03 line.long 0x00 "L3_STCOL_OP_i_SEL_0," hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x354++0x03 line.long 0x00 "L3_STCOL_OP_i_SEL_1," hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x4AC++0x03 line.long 0x00 "L3_STCOL_OP_i_SEL_2," hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x604++0x03 line.long 0x00 "L3_STCOL_OP_i_SEL_3," hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C ) rgroup.long ($2+0x8C)++0x03 line.long 0x00 "L3_STCOL_DUMP_CNT$1," repeat.end width 0x0B tree.end repeat.end tree "CM_CORE_AON_TARG" base ad:0x4A006000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CM_CORE_TARG" base ad:0x4A00A000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CORE_CM_CORE" base ad:0x4A008700 group.long 0x00++0x03 line.long 0x00 "CM_L3MAIN1_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline rbitfld.long 0x00 9. "CLKACTIVITY_L3MAIN1_L4_GICLK,This field indicates the state of the L3MAIN1_L4_GICLK clock in the domain" "CLKACTIVITY_L3MAIN1_L4_GICLK_0,CLKACTIVITY_L3MAIN1_L4_GICLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_L3MAIN1_L3_GICLK,This field indicates the state of the L3MAIN1_L3_GICLK clock in the domain" "CLKACTIVITY_L3MAIN1_L3_GICLK_0,CLKACTIVITY_L3MAIN1_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L3MAIN1 clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x08++0x03 line.long 0x00 "CM_L3MAIN1_DYNAMICDEP,This register controls the dynamic domain depedencies from L3MAIN1 domain towards 'target' domains" rbitfld.long 0x00 31. "EVE4_DYNDEP,Dynamic dependency towards EVE4 clock domain" "?,EVE4_DYNDEP_1" newline rbitfld.long 0x00 30. "EVE3_DYNDEP,Dynamic dependency towards EVE3 clock domain" "?,EVE3_DYNDEP_1" newline rbitfld.long 0x00 29. "EVE2_DYNDEP,Dynamic dependency towards EVE2 clock domain" "?,EVE2_DYNDEP_1" newline rbitfld.long 0x00 28. "EVE1_DYNDEP,Dynamic dependency towards EVE1 clock domain" "?,EVE1_DYNDEP_1" newline bitfld.long 0x00 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 23. "L4PER3_DYNDEP,Dynamic dependency towards L4PER3 clock domain" "?,L4PER3_DYNDEP_1" newline rbitfld.long 0x00 22. "L4PER2_DYNDEP,Dynamic dependency towards L4PER2 clock domain" "?,L4PER2_DYNDEP_1" newline rbitfld.long 0x00 21. "PCIE_DYNDEP,Dynamic dependency towards PCIE clock domain" "?,PCIE_DYNDEP_1" newline rbitfld.long 0x00 20. "DSP2_DYNDEP,Dynamic dependency towards DSP2 clock domain" "?,DSP2_DYNDEP_1" newline rbitfld.long 0x00 19. "RESERVED," "0,1" newline rbitfld.long 0x00 18. "IPU1_DYNDEP,Dynamic dependency towards IPU1 clock domain" "?,IPU1_DYNDEP_1" newline rbitfld.long 0x00 16.--17. "RESERVED," "0,1,2,3" newline rbitfld.long 0x00 15. "WKUPAON_DYNDEP,Dynamic dependency towards WKUPAON clock domain" "?,WKUPAON_DYNDEP_1" newline rbitfld.long 0x00 14. "L4SEC_DYNDEP,Dynamic dependency towards L4SEC clock domain" "?,L4SEC_DYNDEP_1" newline rbitfld.long 0x00 13. "L4PER_DYNDEP,Dynamic dependency towards L4PER1 clock domain" "?,L4PER_DYNDEP_1" newline rbitfld.long 0x00 12. "L4CFG_DYNDEP,Dynamic dependency towards L4CFG clock domain" "?,L4CFG_DYNDEP_1" newline rbitfld.long 0x00 11. "RESERVED," "0,1" newline rbitfld.long 0x00 10. "GPU_DYNDEP,Dynamic dependency towards GPU clock domain" "?,GPU_DYNDEP_1" newline rbitfld.long 0x00 9. "RESERVED," "0,1" newline rbitfld.long 0x00 8. "DSS_DYNDEP,Dynamic dependency towards DSS clock domain" "?,DSS_DYNDEP_1" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4. "EMIF_DYNDEP,Dynamic dependency towards EMIF clock domain" "?,EMIF_DYNDEP_1" newline rbitfld.long 0x00 3. "IPU_DYNDEP,Dynamic dependency towards IPU clock domain" "?,IPU_DYNDEP_1" newline rbitfld.long 0x00 2. "IVA_DYNDEP,Dynamic dependency towards IVA clock domain" "?,IVA_DYNDEP_1" newline rbitfld.long 0x00 1. "DSP1_DYNDEP,Dynamic dependency towards DSP1 clock domain" "?,DSP1_DYNDEP_1" newline rbitfld.long 0x00 0. "IPU2_DYNDEP,Dynamic dependency towards IPU2 clock domain" "?,IPU2_DYNDEP_1" rgroup.long 0x20++0x03 line.long 0x00 "CM_L3MAIN1_L3_MAIN_1_CLKCTRL,This register manages the L3_MAIN_1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x28++0x03 line.long 0x00 "CM_L3MAIN1_GPMC_CLKCTRL,This register manages the GPMC clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x30++0x03 line.long 0x00 "CM_L3MAIN1_MMU_EDMA_CLKCTRL,This register manages the MMU_L4_EDMA clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x48++0x03 line.long 0x00 "CM_L3MAIN1_MMU_PCIESS_CLKCTRL,This register manages the MMU_L4_PCIESS clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x50++0x03 line.long 0x00 "CM_L3MAIN1_OCMC_RAM1_CLKCTRL,This register manages the OCMC_RAM1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x58++0x03 line.long 0x00 "CM_L3MAIN1_TESOC_CLKCTRL,This register manages the TESOC clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x60++0x03 line.long 0x00 "CM_L3MAIN1_OCMC_RAM3_CLKCTRL,This register manages the OCMC_RAM3 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x68++0x03 line.long 0x00 "CM_L3MAIN1_OCMC_ROM_CLKCTRL,This register manages the OCMC_RAM clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x70++0x03 line.long 0x00 "CM_L3MAIN1_TPCC_CLKCTRL,This register manages the TPCC clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x78++0x03 line.long 0x00 "CM_L3MAIN1_TPTC1_CLKCTRL,This register manages the TPTC1 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x80++0x03 line.long 0x00 "CM_L3MAIN1_TPTC2_CLKCTRL,This register manages the TPTC2 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x88++0x03 line.long 0x00 "CM_L3MAIN1_VCP1_CLKCTRL,This register manages the VCP1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x90++0x03 line.long 0x00 "CM_L3MAIN1_VCP2_CLKCTRL,This register manages the VCP2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x98++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_CME_CLKCTRL,This register manages the SPARE_CME clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xA0++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_HDMI_CLKCTRL,This register manages the SPARE_HDMI clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xA8++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_ICM_CLKCTRL,This register manages the SPARE_ICM clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xB0++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_IVA2_CLKCTRL,This register manages the SPARE_IVA2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xB8++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_SATA2_CLKCTRL,This register manages the SPARE_SATA2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xC0++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL,This register manages the SPARE_UNKNOWN4 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xC8++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL,This register manages the SPARE_UNKNOWN5 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xD0++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL,This register manages the SPARE_UNKNOWN6 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xD8++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL,This register manages the SPARE_VIDEOPLL1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xF0++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL,This register manages the SPARE_VIDEOPLL2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xF8++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL,This register manages the SPARE_VIDEOPLL3 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x200++0x0B line.long 0x00 "CM_IPU2_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline rbitfld.long 0x00 8. "CLKACTIVITY_IPU2_GFCLK,This field indicates the state of the IPU2_GCLK clock in the domain" "CLKACTIVITY_IPU2_GFCLK_0,CLKACTIVITY_IPU2_GFCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the IPU2 clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_IPU2_STATICDEP,This register controls the static domain depedencies from IPU domain towards 'target' domains" rbitfld.long 0x04 31. "RESERVED," "0,1" newline bitfld.long 0x04 30. "CRC_STATDEP,Static dependency towards CRC clock domain" "CRC_STATDEP_0,CRC_STATDEP_1" newline bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE clock domain" "PCIE_STATDEP_0,PCIE_STATDEP_1" newline bitfld.long 0x04 28. "ISS_STATDEP,Static dependency towards ISS clock domain" "ISS_STATDEP_0,ISS_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain" "GMAC_STATDEP_0,GMAC_STATDEP_1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" newline bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain" "EVE1_STATDEP_0,EVE1_STATDEP_1" newline bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain" "CUSTEFUSE_STATDEP_0,?" newline rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 11. "SDMA_STATDEP,Static dependency towards DMA clock domain" "SDMA_STATDEP_0,?" newline bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU clock domain" "GPU_STATDEP_0,GPU_STATDEP_1" newline rbitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain" "CAM_STATDEP_0,?" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline rbitfld.long 0x04 6. "RESERVED," "0,1" newline bitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "L3MAIN1_STATDEP_0,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP clock domain" "DSP1_STATDEP_0,DSP1_STATDEP_1" newline rbitfld.long 0x04 0. "RESERVED," "0,1" line.long 0x08 "CM_IPU2_DYNAMICDEP,This register controls the dynamic domain depedencies from IPU domain towards 'target' domains" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 10.--23. 1. "RESERVED," newline rbitfld.long 0x08 9. "CAM_DYNDEP,Dynamic dependency towards CAM clock domain" "CAM_DYNDEP_0,?" newline rbitfld.long 0x08 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x220++0x03 line.long 0x00 "CM_IPU2_IPU2_CLKCTRL,This register manages the IPU2 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x300++0x0B line.long 0x00 "CM_DMA_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline rbitfld.long 0x00 8. "CLKACTIVITY_DMA_L3_GICLK,This field indicates the state of the DMA_L3_GICLK clock in the domain" "CLKACTIVITY_DMA_L3_GICLK_0,CLKACTIVITY_DMA_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DMA clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_DMA_STATICDEP,This register controls the static domain depedencies from DMA domain towards 'target' domains" rbitfld.long 0x04 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE clock domain" "PCIE_STATDEP_0,PCIE_STATDEP_1" newline rbitfld.long 0x04 28. "RESERVED," "0,1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline rbitfld.long 0x04 25. "RESERVED," "0,1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline hexmask.long.byte 0x04 16.--22. 1. "RESERVED," newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 10.--11. "RESERVED," "0,1,2,3" newline rbitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain" "CAM_STATDEP_0,?" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline rbitfld.long 0x04 6. "RESERVED," "0,1" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline rbitfld.long 0x04 1. "RESERVED," "0,1" newline bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_DMA_DYNAMICDEP,This register controls the dynamic domain depedencies from SDMA domain towards 'target' domains" hexmask.long 0x08 6.--31. 1. "RESERVED," newline bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "L3MAIN1_DYNDEP_0,?" newline bitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x320++0x03 line.long 0x00 "CM_DMA_DMA_SYSTEM_CLKCTRL,This register manages the DMA_SYSTEM clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x400++0x03 line.long 0x00 "CM_EMIF_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," newline rbitfld.long 0x00 10. "CLKACTIVITY_EMIF_PHY_GCLK,This field indicates the state of the EMIF_PHY_GCLK clock in the domain" "CLKACTIVITY_EMIF_PHY_GCLK_0,CLKACTIVITY_EMIF_PHY_GCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_EMIF_DLL_GCLK,This field indicates the state of the DLL_GCLK clock in the domain" "CLKACTIVITY_EMIF_DLL_GCLK_0,CLKACTIVITY_EMIF_DLL_GCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_EMIF_L3_GICLK,This field indicates the state of the EMIF_L3_GICLK clock in the domain" "CLKACTIVITY_EMIF_L3_GICLK_0,CLKACTIVITY_EMIF_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the EMIF clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" rgroup.long 0x420++0x03 line.long 0x00 "CM_EMIF_DMM_CLKCTRL,This register manages the DMM clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x428++0x03 line.long 0x00 "CM_EMIF_EMIF_OCP_FW_CLKCTRL,This register manages the EMIF_OCP_FW clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x430++0x03 line.long 0x00 "CM_EMIF_EMIF1_CLKCTRL,This register manages the EMIF1 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," newline rbitfld.long 0x00 24. "CLKSEL_LL,Source of EMIF1 External Low Latency interface clock EMIF_LL_GCLK Value is provided by LLI_C2C_SELECT input pin" "CLKSEL_LL_0,CLKSEL_LL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x438++0x03 line.long 0x00 "CM_EMIF_EMIF2_CLKCTRL,This register manages the EMIF2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x440++0x03 line.long 0x00 "CM_EMIF_EMIF_DLL_CLKCTRL,This register manages the DLL clock" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_DLL_CLK,Optional functional clock control" "OPTFCLKEN_DLL_CLK_0,OPTFCLKEN_DLL_CLK_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0x500++0x03 line.long 0x00 "CM_CRC_CRC_CLKCTRL,This register manages the CRC clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 26.--27. "CLKSEL_SOURCE2,Selects source for CRC clock" "CLKSEL_SOURCE2_0,CLKSEL_SOURCE2_1,CLKSEL_SOURCE2_2,CLKSEL_SOURCE2_3" newline bitfld.long 0x00 24.--25. "CLKSEL_SOURCE1,Selects source for CRC clock" "CLKSEL_SOURCE1_0,CLKSEL_SOURCE1_1,CLKSEL_SOURCE1_2,CLKSEL_SOURCE1_3" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x520++0x03 line.long 0x00 "CM_CRC_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline rbitfld.long 0x00 9. "CLKACTIVITY_CRC_GFCLK,This field indicates the state of the CRC_GFCLK clock in the domain" "CLKACTIVITY_CRC_GFCLK_0,CLKACTIVITY_CRC_GFCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_CRC_L3_GICLK,This field indicates the state of the CRC_L3_GICLK clock in the domain" "CLKACTIVITY_CRC_L3_GICLK_0,CLKACTIVITY_CRC_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the C2C clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x600++0x03 line.long 0x00 "CM_L4CFG_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline rbitfld.long 0x00 9. "CLKACTIVITY_L4CFG_L3_GICLK,This field indicates the state of the L4CFG_L3_GICLK clock in the domain" "CLKACTIVITY_L4CFG_L3_GICLK_0,CLKACTIVITY_L4CFG_L3_GICLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_L4CFG_L4_GICLK,This field indicates the state of the L4CFG_L4_GICLK clock in the domain" "CLKACTIVITY_L4CFG_L4_GICLK_0,CLKACTIVITY_L4CFG_L4_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4CFG clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x608++0x03 line.long 0x00 "CM_L4CFG_DYNAMICDEP,This register controls the dynamic domain depedencies from L4CFG domain towards 'target' domains" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 19. "MPU_DYNDEP,Dynamic dependency towards MPU clock domain" "?,MPU_DYNDEP_1" newline rbitfld.long 0x00 18. "RESERVED," "0,1" newline rbitfld.long 0x00 17. "CUSTEFUSE_DYNDEP,Dynamic dependency towards CUSTEFUSE clock domain" "?,CUSTEFUSE_DYNDEP_1" newline rbitfld.long 0x00 16. "COREAON_DYNDEP,Dynamic dependency towards COREAON clock domain" "?,COREAON_DYNDEP_1" newline rbitfld.long 0x00 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 11. "SDMA_DYNDEP,Dynamic dependency towards DMA clock domain" "?,SDMA_DYNDEP_1" newline rbitfld.long 0x00 8.--10. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "L3INIT_DYNDEP,Dynamic dependency towards L3INIT clock domain" "?,L3INIT_DYNDEP_1" newline rbitfld.long 0x00 6. "RESERVED," "0,1" newline rbitfld.long 0x00 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x00 4. "EMIF_DYNDEP,Dynamic dependency towards EMIF clock domain" "?,EMIF_DYNDEP_1" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x620++0x03 line.long 0x00 "CM_L4CFG_L4_CFG_CLKCTRL,This register manages the L4_CFG clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x628++0x03 line.long 0x00 "CM_L4CFG_SPINLOCK_CLKCTRL,This register manages the SPINLOCK clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x630++0x03 line.long 0x00 "CM_L4CFG_MAILBOX1_CLKCTRL,This register manages the MAILBOX1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x638++0x03 line.long 0x00 "CM_L4CFG_SAR_ROM_CLKCTRL,This register manages the SAR_ROM clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x640++0x03 line.long 0x00 "CM_L4CFG_OCP2SCP2_CLKCTRL,This register manages the OCP2SCP2 clocks and the optional clock of USB PHY" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x648++0x03 line.long 0x00 "CM_L4CFG_MAILBOX2_CLKCTRL,This register manages the MAILBOX2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x650++0x03 line.long 0x00 "CM_L4CFG_MAILBOX3_CLKCTRL,This register manages the MAILBOX3 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x658++0x03 line.long 0x00 "CM_L4CFG_MAILBOX4_CLKCTRL,This register manages the MAILBOX4 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x660++0x03 line.long 0x00 "CM_L4CFG_MAILBOX5_CLKCTRL,This register manages the MAILBOX5 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x668++0x03 line.long 0x00 "CM_L4CFG_MAILBOX6_CLKCTRL,This register manages the MAILBOX6 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x670++0x03 line.long 0x00 "CM_L4CFG_MAILBOX7_CLKCTRL,This register manages the MAILBOX7 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x678++0x03 line.long 0x00 "CM_L4CFG_MAILBOX8_CLKCTRL,This register manages the MAILBOX8 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x680++0x03 line.long 0x00 "CM_L4CFG_MAILBOX9_CLKCTRL,This register manages the MAILBOX9 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x688++0x03 line.long 0x00 "CM_L4CFG_MAILBOX10_CLKCTRL,This register manages the MAILBOX10 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x690++0x03 line.long 0x00 "CM_L4CFG_MAILBOX11_CLKCTRL,This register manages the MAILBOX11 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x698++0x03 line.long 0x00 "CM_L4CFG_MAILBOX12_CLKCTRL,This register manages the MAILBOX12 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x6A0++0x03 line.long 0x00 "CM_L4CFG_MAILBOX13_CLKCTRL,This register manages the MAILBOX13 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x6A8++0x03 line.long 0x00 "CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL,This register manages the SPARE_SMARTREFLEX_RTC clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x6B0++0x03 line.long 0x00 "CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL,This register manages the SPARE_SMARTREFLEX_SDRAM clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x6B8++0x03 line.long 0x00 "CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL,This register manages the SPARE_SMARTREFLEX_WKUP clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x6C0++0x03 line.long 0x00 "CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL,This register manages the IO_DELAY_BLOCK clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x700++0x03 line.long 0x00 "CM_L3INSTR_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," newline bitfld.long 0x00 10. "CLKACTIVITY_L3INSTR_TS_GCLK,This field indicates the state of the L3INSTR_TS_GCLK clock in the domain" "CLKACTIVITY_L3INSTR_TS_GCLK_0,CLKACTIVITY_L3INSTR_TS_GCLK_1" newline bitfld.long 0x00 9. "CLKACTIVITY_L3INSTR_DLL_AGING_GCLK,This field indicates the state of the L3INSTR_DLL_AGING_GCLK clock in the domain" "CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_0,CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_1" newline bitfld.long 0x00 8. "CLKACTIVITY_L3INSTR_L3_GICLK,This field indicates the state of the L3INSTR_L3_GICLK clock in the domain" "CLKACTIVITY_L3INSTR_L3_GICLK_0,CLKACTIVITY_L3INSTR_L3_GICLK_1" newline bitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L3INSTR clock domain" "?,?,?,CLKTRCTRL_3" group.long 0x720++0x03 line.long 0x00 "CM_L3INSTR_L3_MAIN_2_CLKCTRL,This register manages the L3_MAIN_2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x728++0x03 line.long 0x00 "CM_L3INSTR_L3_INSTR_CLKCTRL,This register manages the L3 INSTRUMENTATION clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x740++0x03 line.long 0x00 "CM_L3INSTR_OCP_WP_NOC_CLKCTRL,This register manages the OCP_WP_NOC clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x748++0x03 line.long 0x00 "CM_L3INSTR_DLL_AGING_CLKCTRL,This register manages the DLL_AGING clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x750++0x03 line.long 0x00 "CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,This register manages the CTRL_MODULE_BANDGAP clock" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 24.--25. "CLKSEL,Selects the divider value for generating the Thermal Sensor clock from WKUPAON_ICLK source" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline rbitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" width 0x0B tree.end tree "CORE_PRM" base ad:0x4AE06700 group.long 0x00++0x07 line.long 0x00 "PM_CORE_PWRSTCTRL,This register controls the CORE power state to reach upon a domain sleep transition" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 24.--25. "OCP_NRET_BANK_ONSTATE,OCP_WP bank and DMM bank2 state when domain is ON" "?,?,?,OCP_NRET_BANK_ONSTATE_3" newline rbitfld.long 0x00 22.--23. "IPU_UNICACHE_ONSTATE,IPU UNICACHE bank state when domain is ON" "?,?,?,IPU_UNICACHE_ONSTATE_3" rbitfld.long 0x00 20.--21. "IPU_L2RAM_ONSTATE,IPU L2 bank state when domain is ON" "?,?,?,IPU_L2RAM_ONSTATE_3" newline rbitfld.long 0x00 18.--19. "CORE_OCMRAM_ONSTATE,OCMRAM bank state when domain is ON" "?,?,?,CORE_OCMRAM_ONSTATE_3" rbitfld.long 0x00 16.--17. "CORE_OTHER_BANK_ONSTATE,DMA/ICR bank and DMM bank1 state when domain is ON" "?,?,?,CORE_OTHER_BANK_ONSTATE_3" newline rbitfld.long 0x00 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x00 12. "OCP_NRET_BANK_RETSTATE,OCP_WP bank and DMM bank2 state when domain is RETENTION" "OCP_NRET_BANK_RETSTATE_0,?" newline bitfld.long 0x00 11. "IPU_UNICACHE_RETSTATE,IPU UNICACHE bank state when domain is RETENTION" "IPU_UNICACHE_RETSTATE_0,IPU_UNICACHE_RETSTATE_1" bitfld.long 0x00 10. "IPU_L2RAM_RETSTATE,IPU L2 bank state when domain is RETENTION" "IPU_L2RAM_RETSTATE_0,IPU_L2RAM_RETSTATE_1" newline rbitfld.long 0x00 9. "CORE_OCMRAM_RETSTATE,OCMRAM bank state when domain is RETENTION" "?,CORE_OCMRAM_RETSTATE_1" rbitfld.long 0x00 8. "CORE_OTHER_BANK_RETSTATE,DMA/ICR bank and DMM bank1 state when domain is RETENTION" "?,CORE_OTHER_BANK_RETSTATE_1" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION" "LOGICRETSTATE_0,LOGICRETSTATE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_CORE_PWRSTST,This register provides a status on the current CORE power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 14.--19. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x04 12.--13. "OCP_NRET_BANK_STATEST,OCP_WP bank and DMM bank2 state status" "OCP_NRET_BANK_STATEST_0,OCP_NRET_BANK_STATEST_1,OCP_NRET_BANK_STATEST_2,OCP_NRET_BANK_STATEST_3" newline rbitfld.long 0x04 10.--11. "IPU_UNICACHE_STATEST,IPU UNICACHE bank state status" "IPU_UNICACHE_STATEST_0,IPU_UNICACHE_STATEST_1,IPU_UNICACHE_STATEST_2,IPU_UNICACHE_STATEST_3" rbitfld.long 0x04 8.--9. "IPU_L2RAM_STATEST,IPU L2 bank state status" "IPU_L2RAM_STATEST_0,IPU_L2RAM_STATEST_1,IPU_L2RAM_STATEST_2,IPU_L2RAM_STATEST_3" newline rbitfld.long 0x04 6.--7. "CORE_OCMRAM_STATEST,OCMRAM bank state status" "CORE_OCMRAM_STATEST_0,CORE_OCMRAM_STATEST_1,CORE_OCMRAM_STATEST_2,CORE_OCMRAM_STATEST_3" rbitfld.long 0x04 4.--5. "CORE_OTHER_BANK_STATEST,DMA/ICR bank and DMM bank1 state status" "CORE_OTHER_BANK_STATEST_0,CORE_OTHER_BANK_STATEST_1,CORE_OTHER_BANK_STATEST_2,CORE_OTHER_BANK_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_L3MAIN1_L3_MAIN_1_CONTEXT,This register contains dedicated L3_MAIN_1 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x2C++0x03 line.long 0x00 "RM_L3MAIN1_GPMC_CONTEXT,This register contains dedicated GPMC context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x34++0x03 line.long 0x00 "RM_L3MAIN1_MMU_EDMA_CONTEXT,This register contains dedicated MMU context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x4C++0x1B line.long 0x00 "RM_L3MAIN1_MMU_PCIESS_CONTEXT,This register contains dedicated MMU context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" line.long 0x04 "PM_L3MAIN1_OCMC_RAM1_WKDEP,This register controls wakeup dependency based on OCMC_RAM1 service requests" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "WKUPDEP_OCMC_RAM1_EVE4,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_EVE4_0,WKUPDEP_OCMC_RAM1_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_OCMC_RAM1_EVE3,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_EVE3_0,WKUPDEP_OCMC_RAM1_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_OCMC_RAM1_EVE2,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_EVE2_0,WKUPDEP_OCMC_RAM1_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_OCMC_RAM1_EVE1,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_EVE1_0,WKUPDEP_OCMC_RAM1_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_OCMC_RAM1_DSP2,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_DSP2_0,WKUPDEP_OCMC_RAM1_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_OCMC_RAM1_IPU1,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_IPU1_0,WKUPDEP_OCMC_RAM1_IPU1_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "WKUPDEP_OCMC_RAM1_DSP1,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_DSP1_0,WKUPDEP_OCMC_RAM1_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_OCMC_RAM1_IPU2,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_IPU2_0,WKUPDEP_OCMC_RAM1_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_OCMC_RAM1_MPU,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_MPU_0,WKUPDEP_OCMC_RAM1_MPU_1" line.long 0x08 "RM_L3MAIN1_OCMC_RAM1_CONTEXT,This register contains dedicated OCMC_RAM context statuses" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," bitfld.long 0x08 8. "LOSTMEM_CORE_OCMRAM,Specify if memory-based context in CORE_OCMRAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_CORE_OCMRAM_0,LOSTMEM_CORE_OCMRAM_1" newline hexmask.long.byte 0x08 1.--7. 1. "RESERVED," bitfld.long 0x08 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x0C "PM_L3MAIN1_TESOC_WKDEP,This register controls wakeup dependency based on TESOC service requests" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED," bitfld.long 0x0C 9. "WKUPDEP_TESOC_EVE4,Wakeup dependency from TESOC module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_EVE4_0,WKUPDEP_TESOC_EVE4_1" newline bitfld.long 0x0C 8. "WKUPDEP_TESOC_EVE3,Wakeup dependency from TESOC module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_EVE3_0,WKUPDEP_TESOC_EVE3_1" bitfld.long 0x0C 7. "WKUPDEP_TESOC_EVE2,Wakeup dependency from TESOC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_EVE2_0,WKUPDEP_TESOC_EVE2_1" newline bitfld.long 0x0C 6. "WKUPDEP_TESOC_EVE1,Wakeup dependency from TESOC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_EVE1_0,WKUPDEP_TESOC_EVE1_1" bitfld.long 0x0C 5. "WKUPDEP_TESOC_DSP2,Wakeup dependency from TESOC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_DSP2_0,WKUPDEP_TESOC_DSP2_1" newline bitfld.long 0x0C 4. "WKUPDEP_TESOC_IPU1,Wakeup dependency from TESOC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_IPU1_0,WKUPDEP_TESOC_IPU1_1" rbitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "WKUPDEP_TESOC_DSP1,Wakeup dependency from TESOC module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_DSP1_0,WKUPDEP_TESOC_DSP1_1" bitfld.long 0x0C 1. "WKUPDEP_TESOC_IPU2,Wakeup dependency from TESOC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_IPU2_0,WKUPDEP_TESOC_IPU2_1" newline bitfld.long 0x0C 0. "WKUPDEP_TESOC_MPU,Wakeup dependency from TESOC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_MPU_0,WKUPDEP_TESOC_MPU_1" line.long 0x10 "RM_L3MAIN1_TESOC_CONTEXT,This register contains dedicated TESOC context statuses" hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED," bitfld.long 0x10 8. "LOSTMEM_CORE_OCMRAM,Specify if memory-based context in CORE_OCMRAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_CORE_OCMRAM_0,LOSTMEM_CORE_OCMRAM_1" newline hexmask.long.byte 0x10 1.--7. 1. "RESERVED," bitfld.long 0x10 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x14 "PM_L3MAIN1_OCMC_RAM3_WKDEP,This register controls wakeup dependency based on OCMC_RAM3 service requests" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," bitfld.long 0x14 9. "WKUPDEP_OCMC_RAM3_EVE4,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_EVE4_0,WKUPDEP_OCMC_RAM3_EVE4_1" newline bitfld.long 0x14 8. "WKUPDEP_OCMC_RAM3_EVE3,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_EVE3_0,WKUPDEP_OCMC_RAM3_EVE3_1" bitfld.long 0x14 7. "WKUPDEP_OCMC_RAM3_EVE2,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_EVE2_0,WKUPDEP_OCMC_RAM3_EVE2_1" newline bitfld.long 0x14 6. "WKUPDEP_OCMC_RAM3_EVE1,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_EVE1_0,WKUPDEP_OCMC_RAM3_EVE1_1" bitfld.long 0x14 5. "WKUPDEP_OCMC_RAM3_DSP2,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_DSP2_0,WKUPDEP_OCMC_RAM3_DSP2_1" newline bitfld.long 0x14 4. "WKUPDEP_OCMC_RAM3_IPU1,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_IPU1_0,WKUPDEP_OCMC_RAM3_IPU1_1" rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 2. "WKUPDEP_OCMC_RAM3_DSP1,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_DSP1_0,WKUPDEP_OCMC_RAM3_DSP1_1" bitfld.long 0x14 1. "WKUPDEP_OCMC_RAM3_IPU2,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_IPU2_0,WKUPDEP_OCMC_RAM3_IPU2_1" newline bitfld.long 0x14 0. "WKUPDEP_OCMC_RAM3_MPU,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_MPU_0,WKUPDEP_OCMC_RAM3_MPU_1" line.long 0x18 "RM_L3MAIN1_OCMC_RAM3_CONTEXT,This register contains dedicated OCMC_RAM3 context statuses" hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED," bitfld.long 0x18 8. "LOSTMEM_CORE_OCMRAM,Specify if memory-based context in CORE_OCMRAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_CORE_OCMRAM_0,LOSTMEM_CORE_OCMRAM_1" newline hexmask.long.byte 0x18 1.--7. 1. "RESERVED," bitfld.long 0x18 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x6C++0x1B line.long 0x00 "RM_L3MAIN1_OCMC_ROM_CONTEXT,This register contains dedicated OCMC_ROM context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_CORE_OCMROM,Specify if memory-based context in CORE_OCMROM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_CORE_OCMROM_0,LOSTMEM_CORE_OCMROM_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_L3MAIN1_TPCC_WKDEP,This register controls wakeup dependency based on TPCC service requests" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "WKUPDEP_TPCC_EVE4,Wakeup dependency from TPCC module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_EVE4_0,WKUPDEP_TPCC_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_TPCC_EVE3,Wakeup dependency from TPCC module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_EVE3_0,WKUPDEP_TPCC_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_TPCC_EVE2,Wakeup dependency from TPCC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_EVE2_0,WKUPDEP_TPCC_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_TPCC_EVE1,Wakeup dependency from TPCC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_EVE1_0,WKUPDEP_TPCC_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_TPCC_DSP2,Wakeup dependency from TPCC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_DSP2_0,WKUPDEP_TPCC_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_TPCC_IPU1,Wakeup dependency from TPCC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_IPU1_0,WKUPDEP_TPCC_IPU1_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "WKUPDEP_TPCC_DSP1,Wakeup dependency from TPCC module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_DSP1_0,WKUPDEP_TPCC_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_TPCC_IPU2,Wakeup dependency from TPCC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_IPU2_0,WKUPDEP_TPCC_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_TPCC_MPU,Wakeup dependency from TPCC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_MPU_0,WKUPDEP_TPCC_MPU_1" line.long 0x08 "RM_L3MAIN1_TPCC_CONTEXT,This register contains dedicated TPCC context statuses" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," bitfld.long 0x08 8. "LOSTMEM_TPCC_BANK,Specify if memory-based context in TPCC_MEM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_TPCC_BANK_0,LOSTMEM_TPCC_BANK_1" newline rbitfld.long 0x08 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x08 0. "RESERVED," "0,1" line.long 0x0C "PM_L3MAIN1_TPTC1_WKDEP,This register controls wakeup dependency based on TPTC service requests" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED," bitfld.long 0x0C 9. "WKUPDEP_TPTC1_EVE4,Wakeup dependency from TPTC module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_EVE4_0,WKUPDEP_TPTC1_EVE4_1" newline bitfld.long 0x0C 8. "WKUPDEP_TPTC1_EVE3,Wakeup dependency from TPTC module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_EVE3_0,WKUPDEP_TPTC1_EVE3_1" bitfld.long 0x0C 7. "WKUPDEP_TPTC1_EVE2,Wakeup dependency from TPTC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_EVE2_0,WKUPDEP_TPTC1_EVE2_1" newline bitfld.long 0x0C 6. "WKUPDEP_TPTC1_EVE1,Wakeup dependency from TPTC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_EVE1_0,WKUPDEP_TPTC1_EVE1_1" bitfld.long 0x0C 5. "WKUPDEP_TPTC1_DSP2,Wakeup dependency from TPTC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_DSP2_0,WKUPDEP_TPTC1_DSP2_1" newline bitfld.long 0x0C 4. "WKUPDEP_TPTC1_IPU1,Wakeup dependency from TPTC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_IPU1_0,WKUPDEP_TPTC1_IPU1_1" rbitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "WKUPDEP_TPTC1_DSP1,Wakeup dependency from TPTC module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_DSP1_0,WKUPDEP_TPTC1_DSP1_1" bitfld.long 0x0C 1. "WKUPDEP_TPTC1_IPU2,Wakeup dependency from TPTC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_IPU2_0,WKUPDEP_TPTC1_IPU2_1" newline bitfld.long 0x0C 0. "WKUPDEP_TPTC1_MPU,Wakeup dependency from TPTC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_MPU_0,WKUPDEP_TPTC1_MPU_1" line.long 0x10 "RM_L3MAIN1_TPTC1_CONTEXT,This register contains dedicated TPTC1 context statuses" hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED," bitfld.long 0x10 8. "LOSTMEM_TPTC_BANK,Specify if memory-based context in TPTC_MEM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_TPTC_BANK_0,LOSTMEM_TPTC_BANK_1" newline rbitfld.long 0x10 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x10 0. "RESERVED," "0,1" line.long 0x14 "PM_L3MAIN1_TPTC2_WKDEP,This register controls wakeup dependency based on TPTC service requests" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," bitfld.long 0x14 9. "WKUPDEP_TPTC2_EVE4,Wakeup dependency from TPTC module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_EVE4_0,WKUPDEP_TPTC2_EVE4_1" newline bitfld.long 0x14 8. "WKUPDEP_TPTC2_EVE3,Wakeup dependency from TPTC module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_EVE3_0,WKUPDEP_TPTC2_EVE3_1" bitfld.long 0x14 7. "WKUPDEP_TPTC2_EVE2,Wakeup dependency from TPTC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_EVE2_0,WKUPDEP_TPTC2_EVE2_1" newline bitfld.long 0x14 6. "WKUPDEP_TPTC2_EVE1,Wakeup dependency from TPTC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_EVE1_0,WKUPDEP_TPTC2_EVE1_1" bitfld.long 0x14 5. "WKUPDEP_TPTC2_DSP2,Wakeup dependency from TPTC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_DSP2_0,WKUPDEP_TPTC2_DSP2_1" newline bitfld.long 0x14 4. "WKUPDEP_TPTC2_IPU1,Wakeup dependency from TPTC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_IPU1_0,WKUPDEP_TPTC2_IPU1_1" rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 2. "WKUPDEP_TPTC2_DSP1,Wakeup dependency from TPTC module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_DSP1_0,WKUPDEP_TPTC2_DSP1_1" bitfld.long 0x14 1. "WKUPDEP_TPTC2_IPU2,Wakeup dependency from TPTC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_IPU2_0,WKUPDEP_TPTC2_IPU2_1" newline bitfld.long 0x14 0. "WKUPDEP_TPTC2_MPU,Wakeup dependency from TPTC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_MPU_0,WKUPDEP_TPTC2_MPU_1" line.long 0x18 "RM_L3MAIN1_TPTC2_CONTEXT,This register contains dedicated TPTC2 context statuses" hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED," bitfld.long 0x18 8. "LOSTMEM_TPTC_BANK,Specify if memory-based context in TPTC_MEM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_TPTC_BANK_0,LOSTMEM_TPTC_BANK_1" newline rbitfld.long 0x18 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x18 0. "RESERVED," "0,1" group.long 0x8C++0x03 line.long 0x00 "RM_L3MAIN1_VCP1_CONTEXT,This register contains dedicated VCP1 context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_VCP_BANK,Specify if memory-based context in VCP memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VCP_BANK_0,LOSTMEM_VCP_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x94++0x03 line.long 0x00 "RM_L3MAIN1_VCP2_CONTEXT,This register contains dedicated VCP2 context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_VCP_BANK,Specify if memory-based context in VCP memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VCP_BANK_0,LOSTMEM_VCP_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x9C++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_CME_CONTEXT,This register contains dedicated SPARE_CME context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xA4++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_HDMI_CONTEXT,This register contains dedicated SPARE_HDMI context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xAC++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_ICM_CONTEXT,This register contains dedicated SPARE_ICM context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xB4++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_IVA2_CONTEXT,This register contains dedicated SPARE_IVA2 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xBC++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_SATA2_CONTEXT,This register contains dedicated SPARE_SATA2 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xC4++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT,This register contains dedicated SPARE_UNKNOWN4 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xCC++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT,This register contains dedicated SPARE_UNKNOWN5 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xD4++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT,This register contains dedicated SPARE_UNKNOWN6 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xDC++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT,This register contains dedicated SPARE_VIDEOPLL1 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xF4++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT,This register contains dedicated SPARE_VIDEOPLL2 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xFC++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT,This register contains dedicated SPARE_VIDEOPLL3 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x210++0x07 line.long 0x00 "RM_IPU2_RSTCTRL,This register controls the release of the IPU2 sub-system resets" hexmask.long 0x00 3.--31. 1. "RESERVED," bitfld.long 0x00 2. "RST_IPU,IPU system reset control" "RST_IPU_0,RST_IPU_1" newline bitfld.long 0x00 1. "RST_CPU1,IPU Cortex M3 CPU1 reset control" "RST_CPU1_0,RST_CPU1_1" bitfld.long 0x00 0. "RST_CPU0,IPU Cortex M3 CPU0 reset control" "RST_CPU0_0,RST_CPU0_1" line.long 0x04 "RM_IPU2_RSTST,This register logs the different reset sources of the IPU2 SS" hexmask.long 0x04 7.--31. 1. "RESERVED," bitfld.long 0x04 6. "RST_ICECRUSHER_CPU1,Cortex M3 CPU1 has been reset due to IPU ICECRUSHER1 reset source" "RST_ICECRUSHER_CPU1_0,RST_ICECRUSHER_CPU1_1" newline bitfld.long 0x04 5. "RST_ICECRUSHER_CPU0,Cortex M3 CPU0 has been reset due to IPU ICECRUSHER0 reset source" "RST_ICECRUSHER_CPU0_0,RST_ICECRUSHER_CPU0_1" bitfld.long 0x04 4. "RST_EMULATION_CPU1,Cortex M3 CPU1 has been reset due to emulation reset source e.g" "RST_EMULATION_CPU1_0,RST_EMULATION_CPU1_1" newline bitfld.long 0x04 3. "RST_EMULATION_CPU0,Cortex M3 CPU0 has been reset due to emulation reset source e.g" "RST_EMULATION_CPU0_0,RST_EMULATION_CPU0_1" bitfld.long 0x04 2. "RST_IPU,IPU system SW reset status" "RST_IPU_0,RST_IPU_1" newline bitfld.long 0x04 1. "RST_CPU1,IPU Cortex-M3 CPU1 SW reset status" "RST_CPU1_0,RST_CPU1_1" bitfld.long 0x04 0. "RST_CPU0,IPU Cortex-M3 CPU0 SW reset status" "RST_CPU0_0,RST_CPU0_1" group.long 0x224++0x03 line.long 0x00 "RM_IPU2_IPU2_CONTEXT,This register contains dedicated BELLINI1 context statuses" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "LOSTMEM_IPU_L2RAM,Specify if memory-based context in IPU_L2RAM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_IPU_L2RAM_0,LOSTMEM_IPU_L2RAM_1" newline bitfld.long 0x00 8. "LOSTMEM_IPU_UNICACHE,Specify if memory-based context in IPU_UNICACHE memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_IPU_UNICACHE_0,LOSTMEM_IPU_UNICACHE_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x324++0x03 line.long 0x00 "RM_DMA_DMA_SYSTEM_CONTEXT,This register contains dedicated SDMA context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_CORE_OTHER_BANK,Specify if memory-based context in CORE_OTHER_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_CORE_OTHER_BANK_0,LOSTMEM_CORE_OTHER_BANK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x424++0x03 line.long 0x00 "RM_EMIF_DMM_CONTEXT,This register contains dedicated DMM context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x42C++0x03 line.long 0x00 "RM_EMIF_EMIF_OCP_FW_CONTEXT,This register contains dedicated EMIF_OCP_FW context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x434++0x03 line.long 0x00 "RM_EMIF_EMIF1_CONTEXT,This register contains dedicated EMIF_1 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x43C++0x03 line.long 0x00 "RM_EMIF_EMIF2_CONTEXT,This register contains dedicated EMIF_2 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x444++0x03 line.long 0x00 "RM_EMIF_EMIF_DLL_CONTEXT,This register contains dedicated DLL context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x524++0x03 line.long 0x00 "RM_CRC_CRC_CONTEXT,This register contains dedicated CRC context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_CRC_BANK,Specify if memory-based context in CRC_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_CRC_BANK_0,LOSTMEM_CRC_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x624++0x03 line.long 0x00 "RM_L4CFG_L4_CFG_CONTEXT,This register contains dedicated L4_CFG context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x62C++0x03 line.long 0x00 "RM_L4CFG_SPINLOCK_CONTEXT,This register contains dedicated HW_SEM context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x634++0x03 line.long 0x00 "RM_L4CFG_MAILBOX1_CONTEXT,This register contains dedicated MAILBOX1 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x63C++0x03 line.long 0x00 "RM_L4CFG_SAR_ROM_CONTEXT,This register contains dedicated SAR_ROM context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x644++0x03 line.long 0x00 "RM_L4CFG_OCP2SCP2_CONTEXT,This register contains dedicated OCP2SCP2 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x64C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX2_CONTEXT,This register contains dedicated MAILBOX2 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x654++0x03 line.long 0x00 "RM_L4CFG_MAILBOX3_CONTEXT,This register contains dedicated MAILBOX3 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x65C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX4_CONTEXT,This register contains dedicated MAILBOX4 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x664++0x03 line.long 0x00 "RM_L4CFG_MAILBOX5_CONTEXT,This register contains dedicated MAILBOX5 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x66C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX6_CONTEXT,This register contains dedicated MAILBOX6 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x674++0x03 line.long 0x00 "RM_L4CFG_MAILBOX7_CONTEXT,This register contains dedicated MAILBOX7 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x67C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX8_CONTEXT,This register contains dedicated MAILBOX8 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x684++0x03 line.long 0x00 "RM_L4CFG_MAILBOX9_CONTEXT,This register contains dedicated MAILBOX9 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x68C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX10_CONTEXT,This register contains dedicated MAILBOX10 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x694++0x03 line.long 0x00 "RM_L4CFG_MAILBOX11_CONTEXT,This register contains dedicated MAILBOX11 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x69C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX12_CONTEXT,This register contains dedicated MAILBOX12 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x6A4++0x03 line.long 0x00 "RM_L4CFG_MAILBOX13_CONTEXT,This register contains dedicated MAILBOX13 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x6AC++0x03 line.long 0x00 "RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT,This register contains dedicated SPARE_SMARTREFLEX_RTC context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x6B4++0x03 line.long 0x00 "RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT,This register contains dedicated SPARE_SMARTREFLEX_SDRAM context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x6BC++0x03 line.long 0x00 "RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT,This register contains dedicated SPARE_SMARTREFLEX_WKUP context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x6C4++0x03 line.long 0x00 "RM_L4CFG_IO_DELAY_BLOCK_CONTEXT,This register contains dedicated IO_DELAY_BLOCK context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x724++0x03 line.long 0x00 "RM_L3INSTR_L3_MAIN_2_CONTEXT,This register contains dedicated L3_3 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x72C++0x03 line.long 0x00 "RM_L3INSTR_L3_INSTR_CONTEXT,This register contains dedicated L3_INSTR context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x744++0x03 line.long 0x00 "RM_L3INSTR_OCP_WP_NOC_CONTEXT,This register contains dedicated OCP_WP1 context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_CORE_NRET_BANK,Specify if memory-based context in CORE_NRET_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_CORE_NRET_BANK_0,LOSTMEM_CORE_NRET_BANK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "COREAON_CM_CORE" base ad:0x4A008600 group.long 0x00++0x03 line.long 0x00 "CM_COREAON_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.word 0x00 17.--31. 1. "RESERVED," newline rbitfld.long 0x00 16. "CLKACTIVITY_ABE_GICLK,This field indicates the state of the ABE_GICLK clock input of the domain" "CLKACTIVITY_ABE_GICLK_0,CLKACTIVITY_ABE_GICLK_1" newline rbitfld.long 0x00 15. "CLKACTIVITY_SR_IVAHD_SYS_GFCLK,This field indicates the state of the SR_IVAHD_SYS_GFCLK clock input of the domain" "CLKACTIVITY_SR_IVAHD_SYS_GFCLK_0,CLKACTIVITY_SR_IVAHD_SYS_GFCLK_1" newline rbitfld.long 0x00 14. "CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK,This field indicates the state of the COREAON_IO_SRCOMP_GFCLK clock in the domain" "CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_0,CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_1" newline rbitfld.long 0x00 13. "CLKACTIVITY_SR_DSPEVE_SYS_GFCLK,This field indicates the state of the SR_DSPEVE_SYS_GFCLK clock input of the domain" "CLKACTIVITY_SR_DSPEVE_SYS_GFCLK_0,CLKACTIVITY_SR_DSPEVE_SYS_GFCLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_COREAON_32K_GFCLK,This field indicates the state of the COREAON_32K_GFCLK clock in the domain" "CLKACTIVITY_COREAON_32K_GFCLK_0,CLKACTIVITY_COREAON_32K_GFCLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_SR_CORE_SYS_GFCLK,This field indicates the state of the SR_CORE_SYS_GFCLK clock input of the domain" "CLKACTIVITY_SR_CORE_SYS_GFCLK_0,CLKACTIVITY_SR_CORE_SYS_GFCLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_SR_GPU_SYS_GFCLK,This field indicates the state of the SR_GPU_SYS_GFCLK clock input of the domain" "CLKACTIVITY_SR_GPU_SYS_GFCLK_0,CLKACTIVITY_SR_GPU_SYS_GFCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_SR_MPU_SYS_GFCLK,This field indicates the state of the SR_MPU_SYS_GFCLK clock input of the domain" "CLKACTIVITY_SR_MPU_SYS_GFCLK_0,CLKACTIVITY_SR_MPU_SYS_GFCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_COREAON_L4_GICLK,This field indicates the state of the COREAON_L4_GICLK clock of the domain" "CLKACTIVITY_COREAON_L4_GICLK_0,CLKACTIVITY_COREAON_L4_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the COREAON clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x28++0x03 line.long 0x00 "CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,This register manages the SR_MPU clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x38++0x03 line.long 0x00 "CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,This register manages the SR_CORE clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_COREAON_USB_PHY1_CORE_CLKCTRL,This register manages the USB PHY 32KHz clock" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,Optional functional clock control" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0x50++0x03 line.long 0x00 "CM_COREAON_IO_SRCOMP_CLKCTRL,This register manages the clock delivered to the IO Slew rate compensation cells" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "CLKEN_SRCOMP_FCLK,Functional clock control" "CLKEN_SRCOMP_FCLK_0,CLKEN_SRCOMP_FCLK_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0x58++0x03 line.long 0x00 "CM_COREAON_SMARTREFLEX_GPU_CLKCTRL,This register manages the SR_GPU clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x68++0x03 line.long 0x00 "CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL,This register manages the SR_DSPEVE clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x78++0x03 line.long 0x00 "CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL,This register manages the SR_IVAHD clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x88++0x03 line.long 0x00 "CM_COREAON_USB_PHY2_CORE_CLKCTRL,This register manages the USB PHY 32KHz clock" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,Optional functional clock control" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0x98++0x03 line.long 0x00 "CM_COREAON_USB_PHY3_CORE_CLKCTRL,This register manages the USB PHY 32KHz clock" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,Optional functional clock control" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0xA0++0x03 line.long 0x00 "CM_COREAON_DUMMY_MODULE1_CLKCTRL,Used for controlling the CLKOUTMUX1 gate" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLKOUTMUX1_CLK,Optional functional clock control" "OPTFCLKEN_CLKOUTMUX1_CLK_0,OPTFCLKEN_CLKOUTMUX1_CLK_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0xB0++0x03 line.long 0x00 "CM_COREAON_DUMMY_MODULE2_CLKCTRL,Used for controlling CLKOUTMUX2 gate" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLKOUTMUX2_CLK,Optional functional clock control" "OPTFCLKEN_CLKOUTMUX2_CLK_0,OPTFCLKEN_CLKOUTMUX2_CLK_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0xC0++0x03 line.long 0x00 "CM_COREAON_DUMMY_MODULE3_CLKCTRL,Used for controlling the L3INIT_60M_GFCLK gate" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_L3INIT_60M_GFCLK,Optional functional clock control" "OPTFCLKEN_L3INIT_60M_GFCLK_0,OPTFCLKEN_L3INIT_60M_GFCLK_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0xD0++0x03 line.long 0x00 "CM_COREAON_DUMMY_MODULE4_CLKCTRL,Used for controlling ABE_GICLK gate" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_ABE_GICLK,Optional functional clock control" "OPTFCLKEN_ABE_GICLK_0,OPTFCLKEN_ABE_GICLK_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," width 0x0B tree.end tree "COREAON_PRM" base ad:0x4AE06628 group.long 0x00++0x07 line.long 0x00 "PM_COREAON_SMARTREFLEX_MPU_WKDEP,This register controls wakeup dependency based on SR_MPU service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline bitfld.long 0x00 9. "WKUPDEP_SMARTREFLEX_MPU_EVE4,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_EVE4_0,WKUPDEP_SMARTREFLEX_MPU_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_SMARTREFLEX_MPU_EVE3,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_EVE3_0,WKUPDEP_SMARTREFLEX_MPU_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_SMARTREFLEX_MPU_EVE2,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_EVE2_0,WKUPDEP_SMARTREFLEX_MPU_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SMARTREFLEX_MPU_EVE1,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_EVE1_0,WKUPDEP_SMARTREFLEX_MPU_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SMARTREFLEX_MPU_DSP2,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_DSP2_0,WKUPDEP_SMARTREFLEX_MPU_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SMARTREFLEX_MPU_IPU1,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_IPU1_0,WKUPDEP_SMARTREFLEX_MPU_IPU1_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_SMARTREFLEX_MPU_DSP1,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_DSP1_0,WKUPDEP_SMARTREFLEX_MPU_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_SMARTREFLEX_MPU_IPU2,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_IPU2_0,WKUPDEP_SMARTREFLEX_MPU_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SMARTREFLEX_MPU_MPU,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_MPU_0,WKUPDEP_SMARTREFLEX_MPU_MPU_1" line.long 0x04 "RM_COREAON_SMARTREFLEX_MPU_CONTEXT,This register contains dedicated SR_MPU context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," newline bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x10++0x07 line.long 0x00 "PM_COREAON_SMARTREFLEX_CORE_WKDEP,This register controls wakeup dependency based on SR_CORE service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline bitfld.long 0x00 9. "WKUPDEP_SMARTREFLEX_CORE_EVE4,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_EVE4_0,WKUPDEP_SMARTREFLEX_CORE_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_SMARTREFLEX_CORE_EVE3,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_EVE3_0,WKUPDEP_SMARTREFLEX_CORE_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_SMARTREFLEX_CORE_EVE2,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_EVE2_0,WKUPDEP_SMARTREFLEX_CORE_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SMARTREFLEX_CORE_EVE1,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_EVE1_0,WKUPDEP_SMARTREFLEX_CORE_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SMARTREFLEX_CORE_DSP2,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_DSP2_0,WKUPDEP_SMARTREFLEX_CORE_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SMARTREFLEX_CORE_IPU1,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_IPU1_0,WKUPDEP_SMARTREFLEX_CORE_IPU1_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_SMARTREFLEX_CORE_DSP1,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_DSP1_0,WKUPDEP_SMARTREFLEX_CORE_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_SMARTREFLEX_CORE_IPU2,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_IPU2_0,WKUPDEP_SMARTREFLEX_CORE_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SMARTREFLEX_CORE_MPU,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_MPU_0,WKUPDEP_SMARTREFLEX_CORE_MPU_1" line.long 0x04 "RM_COREAON_SMARTREFLEX_CORE_CONTEXT,This register contains dedicated SR_CORE context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," newline bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x30++0x07 line.long 0x00 "PM_COREAON_SMARTREFLEX_GPU_WKDEP,This register controls wakeup dependency based on SMARTREFLEX_GPU service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline bitfld.long 0x00 9. "WKUPDEP_SMARTREFLEX_GPU_EVE4,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_EVE4_0,WKUPDEP_SMARTREFLEX_GPU_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_SMARTREFLEX_GPU_EVE3,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_EVE3_0,WKUPDEP_SMARTREFLEX_GPU_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_SMARTREFLEX_GPU_EVE2,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_EVE2_0,WKUPDEP_SMARTREFLEX_GPU_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SMARTREFLEX_GPU_EVE1,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_EVE1_0,WKUPDEP_SMARTREFLEX_GPU_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SMARTREFLEX_GPU_DSP2,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_DSP2_0,WKUPDEP_SMARTREFLEX_GPU_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SMARTREFLEX_GPU_IPU1,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_IPU1_0,WKUPDEP_SMARTREFLEX_GPU_IPU1_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_SMARTREFLEX_GPU_DSP1,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_DSP1_0,WKUPDEP_SMARTREFLEX_GPU_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_SMARTREFLEX_GPU_IPU2,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_IPU2_0,WKUPDEP_SMARTREFLEX_GPU_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SMARTREFLEX_GPU_MPU,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_MPU_0,WKUPDEP_SMARTREFLEX_GPU_MPU_1" line.long 0x04 "RM_COREAON_SMARTREFLEX_GPU_CONTEXT,This register contains dedicated SR_GPU context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," newline bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x40++0x07 line.long 0x00 "PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP,This register controls wakeup dependency based on SMARTREFLEX_DSPEVE service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline bitfld.long 0x00 9. "WKUPDEP_SMARTREFLEX_DSPEVE_EVE4,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_EVE4_0,WKUPDEP_SMARTREFLEX_DSPEVE_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_SMARTREFLEX_DSPEVE_EVE3,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_EVE3_0,WKUPDEP_SMARTREFLEX_DSPEVE_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_SMARTREFLEX_DSPEVE_EVE2,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_EVE2_0,WKUPDEP_SMARTREFLEX_DSPEVE_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SMARTREFLEX_DSPEVE_EVE1,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_EVE1_0,WKUPDEP_SMARTREFLEX_DSPEVE_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SMARTREFLEX_DSPEVE_DSP2,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_DSP2_0,WKUPDEP_SMARTREFLEX_DSPEVE_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SMARTREFLEX_DSPEVE_IPU1,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_IPU1_0,WKUPDEP_SMARTREFLEX_DSPEVE_IPU1_1" newline bitfld.long 0x00 3. "WKUPDEP_SMARTREFLEX_DSPEVE_SDMA,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_SDMA_0,WKUPDEP_SMARTREFLEX_DSPEVE_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_SMARTREFLEX_DSPEVE_DSP1,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_DSP1_0,WKUPDEP_SMARTREFLEX_DSPEVE_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_SMARTREFLEX_DSPEVE_IPU2,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_IPU2_0,WKUPDEP_SMARTREFLEX_DSPEVE_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SMARTREFLEX_DSPEVE_MPU,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_MPU_0,WKUPDEP_SMARTREFLEX_DSPEVE_MPU_1" line.long 0x04 "RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT,This register contains dedicated SR_DSPEVE context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," newline bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x50++0x07 line.long 0x00 "PM_COREAON_SMARTREFLEX_IVAHD_WKDEP,This register controls wakeup dependency based on SMARTREFLEX_IVAHD service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline bitfld.long 0x00 9. "WKUPDEP_SMARTREFLEX_IVAHD_EVE4,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_EVE4_0,WKUPDEP_SMARTREFLEX_IVAHD_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_SMARTREFLEX_IVAHD_EVE3,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_EVE3_0,WKUPDEP_SMARTREFLEX_IVAHD_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_SMARTREFLEX_IVAHD_EVE2,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_EVE2_0,WKUPDEP_SMARTREFLEX_IVAHD_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SMARTREFLEX_IVAHD_EVE1,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_EVE1_0,WKUPDEP_SMARTREFLEX_IVAHD_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SMARTREFLEX_IVAHD_DSP2,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_DSP2_0,WKUPDEP_SMARTREFLEX_IVAHD_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SMARTREFLEX_IVAHD_IPU1,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_IPU1_0,WKUPDEP_SMARTREFLEX_IVAHD_IPU1_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_SMARTREFLEX_IVAHD_DSP1,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_DSP1_0,WKUPDEP_SMARTREFLEX_IVAHD_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_SMARTREFLEX_IVAHD_IPU2,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_IPU2_0,WKUPDEP_SMARTREFLEX_IVAHD_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SMARTREFLEX_IVAHD_MPU,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_MPU_0,WKUPDEP_SMARTREFLEX_IVAHD_MPU_1" line.long 0x04 "RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT,This register contains dedicated SR_IVA context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," newline bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x84++0x03 line.long 0x00 "RM_COREAON_DUMMY_MODULE1_CONTEXT,This register contains dedicated DUMMY MODULE1 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x94++0x03 line.long 0x00 "RM_COREAON_DUMMY_MODULE2_CONTEXT,This register contains dedicated DUMMY MODULE2 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xA4++0x03 line.long 0x00 "RM_COREAON_DUMMY_MODULE3_CONTEXT,This register contains DUMMY MODULE USBSTUB context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xB4++0x03 line.long 0x00 "RM_COREAON_DUMMY_MODULE4_CONTEXT,This register contains dedicated DUMMY MODULE context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "COUNTER_32K_TARG" base ad:0x4AE05000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CPDMA" base ad:0x48484800 rgroup.long 0x00++0x0B line.long 0x00 "CPDMA_TX_IDVER,CPDMA_REGS TX revision register" line.long 0x04 "CPDMA_TX_CONTROL,CPDMA_REGS TX control register" hexmask.long 0x04 1.--31. 1. "RESERVED," newline bitfld.long 0x04 0. "TX_EN,TX Enable" "Disabled,Enabled" line.long 0x08 "CPDMA_TX_TEARDOWN,CPDMA_REGS TX teardown register" rbitfld.long 0x08 31. "TX_TDN_RDY,Tx Teardown Ready - read as zero but is always assumed to be one (unused)" "0,1" newline hexmask.long 0x08 3.--30. 1. "RESERVED," newline bitfld.long 0x08 0.--2. "TX_TDN_CH,Tx Teardown" "0,1,2,3,4,5,6,7" rgroup.long 0x10++0x3F line.long 0x00 "CPDMA_RX_IDVER,CPDMA_REGS RX revision register" line.long 0x04 "CPDMA_RX_CONTROL,CPDMA_REGS RX control register" hexmask.long 0x04 1.--31. 1. "RESERVED," newline bitfld.long 0x04 0. "RX_EN,RX DMA Enable" "Disabled,Enabled" line.long 0x08 "CPDMA_RX_TEARDOWN,CPDMA_REGS RX teardown register" rbitfld.long 0x08 31. "RX_TDN_RDY,Teardown Ready - read as zero but is always assumed to be one (unused)" "0,1" newline hexmask.long 0x08 3.--30. 1. "RESERVED," newline bitfld.long 0x08 0.--2. "RX_TDN_CH,Rx Teardown Channel -Receive channel teardown is commanded by writing the encoded value of the receive channel to be torn down" "0,1,2,3,4,5,6,7" line.long 0x0C "CPDMA_SOFT_RESET,CPDMA_REGS soft reset register" hexmask.long 0x0C 1.--31. 1. "RESERVED," newline bitfld.long 0x0C 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the CPDMA logic to be reset" "0,1" line.long 0x10 "CPDMA_DMACONTROL,CPDMA_REGS CPDMA control register" hexmask.long.word 0x10 16.--31. 1. "RESERVED," newline abitfld.long 0x10 8.--15. "TX_RLIM,Transmit Rate Limit Channel Bus" "0x00=no rate-limited channels,0x80=channel 7 is rate-limited,0xC0=channels 7 downto 6 are rate-limited,0xE0=channels 7 downto 5 are rate-limited,0xF0=channels 7 downto 4 are rate-limited,0xF8=channels 7 downto 3 are rate-limited,0xFC=channels 7 downto 2 are rate-limited,0xFE=channels 7 downto 1 are rate-limited,0xFF=channels 7 downto 0 are rate-limited all.." newline rbitfld.long 0x10 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 4. "RX_CEF,RX Copy Error Frames Enable - Enables DMA overrun frames to be transferred to memory (up to the point of overrun)" "Frames containing overrun errors are filtered,Frames containing overrun errors are transferred.." newline bitfld.long 0x10 3. "CMD_IDLE,Command Idle" "Idle not commanded,Idle Commanded (read IDLE in CPDMA_DMASTATUS)" newline bitfld.long 0x10 2. "RX_OFFLEN_BLOCK,Receive Offset/Length word write block" "Do not block the DMA writes to the receive..,Block all CPDMA DMA controller writes to the.." newline bitfld.long 0x10 1. "RX_OWNERSHIP,Receive Ownership Write Bit Value" "The CPDMA writes the receive ownership bit to..,The CPDMA writes the receive ownership bit to.." newline bitfld.long 0x10 0. "TX_PTYPE,Transmit Queue Priority Type" "The queue uses a round robin scheme to select..,The queue uses a fixed (channel 7 highest.." line.long 0x14 "CPDMA_DMASTATUS,CPDMA_REGS CPDMA status register" bitfld.long 0x14 31. "IDLE,Idle Status Bit - Indicates when set that the CPDMA is not transferring a packet on transmit or receive" "0,1" newline hexmask.long.byte 0x14 24.--30. 1. "RESERVED," newline bitfld.long 0x14 20.--23. "TX_HOST_ERR_CODE,TX Host Error Code - This field is set to indicate CPDMA detected TX DMA related host errors" "No error,SOP error,Ownership bit not set in SOP buffer,Zero Next Buffer Descriptor Pointer Without EOP,Zero Buffer Pointer,Zero Buffer Length,Packet Length Error (sum of buffers is less than..,?..." newline bitfld.long 0x14 19. "RESERVED," "0,1" newline bitfld.long 0x14 16.--18. "TX_ERR_CH,TX Host Error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--15. "RX_HOST_ERR_CODE,RX Host Error Code - This field is set to indicate CPDMA detected RX DMA related host errors" "No error,reserved,Ownership bit not set in input buffer,reserved,Zero Buffer Pointer,Zero buffer length on non-SOP descriptor,SOP buffer length not greater than offset 0x7 -..,?..." newline bitfld.long 0x14 11. "RESERVED," "0,1" newline bitfld.long 0x14 8.--10. "RX_ERR_CH,RX Host Error" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "RESERVED," line.long 0x18 "CPDMA_RX_BUFFER_OFFSET,CPDMA_REGS receive buffer offset" hexmask.long.word 0x18 16.--31. 1. "RESERVED," newline hexmask.long.word 0x18 0.--15. 1. "RX_BUFFER_OFFSET,Receive Buffer Offset Value - The RX_BUFFER_OFFSET will be written by the port into each frame SOP buffer descriptor buffer_offset field" line.long 0x1C "CPDMA_EMCONTROL,CPDMA_REGS emulation control" hexmask.long 0x1C 2.--31. 1. "RESERVED," newline bitfld.long 0x1C 1. "SOFT,Emulation Soft Bit" "0,1" newline bitfld.long 0x1C 0. "FREE,Emulation Free Bit" "0,1" line.long 0x20 "CPDMA_TX_PRI0_RATE,CPDMA_REGS transmit (ingress) priority 0 rate" rbitfld.long 0x20 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x20 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline rbitfld.long 0x20 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x20 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x24 "CPDMA_TX_PRI1_RATE,CPDMA_REGS transmit (ingress) priority 1 rate" rbitfld.long 0x24 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x24 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline rbitfld.long 0x24 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x24 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x28 "CPDMA_TX_PRI2_RATE,CPDMA_REGS transmit (ingress) priority 2 rate" rbitfld.long 0x28 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x28 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline rbitfld.long 0x28 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x28 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x2C "CPDMA_TX_PRI3_RATE,CPDMA_REGS transmit (ingress) priority 3 rate" rbitfld.long 0x2C 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x2C 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline rbitfld.long 0x2C 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x2C 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x30 "CPDMA_TX_PRI4_RATE,CPDMA_REGS transmit (ingress) priority 4 rate" rbitfld.long 0x30 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x30 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline rbitfld.long 0x30 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x30 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x34 "CPDMA_TX_PRI5_RATE,CPDMA_REGS transmit (ingress) priority 5 rate" rbitfld.long 0x34 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x34 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline rbitfld.long 0x34 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x34 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x38 "CPDMA_TX_PRI6_RATE,CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 6 RATE" rbitfld.long 0x38 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x38 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline rbitfld.long 0x38 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x38 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x3C "CPDMA_TX_PRI7_RATE,CPDMA_REGS transmit (ingress) priority 7 rate" rbitfld.long 0x3C 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x3C 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline rbitfld.long 0x3C 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x3C 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" rgroup.long 0x80++0x17 line.long 0x00 "CPDMA_TX_INTSTAT_RAW,CPDMA_INT TX interrupt status register (raw value)" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," newline bitfld.long 0x00 7. "TX7_PEND,TX7_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 6. "TX6_PEND,TX6_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 5. "TX5_PEND,TX5_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 4. "TX4_PEND,TX4_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 3. "TX3_PEND,TX3_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 2. "TX2_PEND,TX2_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 1. "TX1_PEND,TX1_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 0. "TX0_PEND,TX0_PEND raw int read (before mask)" "0,1" line.long 0x04 "CPDMA_TX_INTSTAT_MASKED,CPDMA_INT TX interrupt status register (masked value)" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," newline bitfld.long 0x04 7. "TX7_PEND,TX7_PEND masked interrupt" "0,1" newline bitfld.long 0x04 6. "TX6_PEND,TX6_PEND masked interrupt" "0,1" newline bitfld.long 0x04 5. "TX5_PEND,TX5_PEND masked interrupt" "0,1" newline bitfld.long 0x04 4. "TX4_PEND,TX4_PEND masked interrupt" "0,1" newline bitfld.long 0x04 3. "TX3_PEND,TX3_PEND masked interrupt" "0,1" newline bitfld.long 0x04 2. "TX2_PEND,TX2_PEND masked interrupt" "0,1" newline bitfld.long 0x04 1. "TX1_PEND,TX1_PEND masked interrupt" "0,1" newline bitfld.long 0x04 0. "TX0_PEND,TX0_PEND masked interrupt" "0,1" line.long 0x08 "CPDMA_TX_INTMASK_SET,CPDMA_INT TX interrupt mask set register" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED," newline bitfld.long 0x08 7. "TX7_MASK,TX Channel 7 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 6. "TX6_MASK,TX Channel 6 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 5. "TX5_MASK,TX Channel 5 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 4. "TX4_MASK,TX Channel 4 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 3. "TX3_MASK,TX Channel 3 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 2. "TX2_MASK,TX Channel 2 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 1. "TX1_MASK,TX Channel 1 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 0. "TX0_MASK,TX Channel 0 Mask - Write one to enable interrupt" "0,1" line.long 0x0C "CPDMA_TX_INTMASK_CLEAR,CPDMA_INT TX Interrupt mask clear register" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED," newline bitfld.long 0x0C 7. "TX7_MASK,TX Channel 7 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 6. "TX6_MASK,TX Channel 6 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 5. "TX5_MASK,TX Channel 5 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 4. "TX4_MASK,TX Channel 4 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 3. "TX3_MASK,TX Channel 3 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 2. "TX2_MASK,TX Channel 2 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 1. "TX1_MASK,TX Channel 1 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 0. "TX0_MASK,TX Channel 0 Mask - Write one to disable interrupt" "0,1" line.long 0x10 "CPDMA_IN_VECTOR,CPDMA_INT input vector (read only)" line.long 0x14 "CPDMA_EOI_VECTOR,CPDMA_INT end of interrupt vector" hexmask.long 0x14 5.--31. 1. "RESERVED," newline bitfld.long 0x14 0.--4. "DMA_EOI_VECTOR,DMA End of Interrupt Vector - The EOI_VECTOR( 4:0) pins reflect the value written to this location one MAIN_CLK cycle after a write to this location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA0++0x5F line.long 0x00 "CPDMA_RX_INTSTAT_RAW,CPDMA_INT RX Interrupt status register (raw value)" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline bitfld.long 0x00 15. "RX7_THRESH_PEND,RX7_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 14. "RX6_THRESH_PEND,RX6_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 13. "RX5_THRESH_PEND,RX5_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 12. "RX4_THRESH_PEND,RX4_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 11. "RX3_THRESH_PEND,RX3_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 10. "RX2_THRESH_PEND,RX2_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 9. "RX1_THRESH_PEND,RX1_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 8. "RX0_THRESH_PEND,RX0_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 7. "RX7_PEND,RX7_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 6. "RX6_PEND,RX6_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 5. "RX5_PEND,RX5_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 4. "RX4_PEND,RX4_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 3. "RX3_PEND,RX3_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 2. "RX2_PEND,RX2_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 1. "RX1_PEND,RX1_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 0. "RX0_PEND,RX0_PEND raw int read (before mask)" "0,1" line.long 0x04 "CPDMA_RX_INTSTAT_MASKED,CPDMA_INT RX interrupt status register (masked value)" hexmask.long.word 0x04 16.--31. 1. "RESERVED," newline bitfld.long 0x04 15. "RX7_THRESH_PEND,RX7_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 14. "RX6_THRESH_PEND,RX6_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 13. "RX5_THRESH_PEND,RX5_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 12. "RX4_THRESH_PEND,RX4_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 11. "RX3_THRESH_PEND,RX3_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 10. "RX2_THRESH_PEND,RX2_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 9. "RX1_THRESH_PEND,RX1_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 8. "RX0_THRESH_PEND,RX0_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 7. "RX7_PEND,RX7_PEND masked int" "0,1" newline bitfld.long 0x04 6. "RX6_PEND,RX6_PEND masked int" "0,1" newline bitfld.long 0x04 5. "RX5_PEND,RX5_PEND masked int" "0,1" newline bitfld.long 0x04 4. "RX4_PEND,RX4_PEND masked int" "0,1" newline bitfld.long 0x04 3. "RX3_PEND,RX3_PEND masked int" "0,1" newline bitfld.long 0x04 2. "RX2_PEND,RX2_PEND masked int" "0,1" newline bitfld.long 0x04 1. "RX1_PEND,RX1_PEND masked int" "0,1" newline bitfld.long 0x04 0. "RX0_PEND,RX0_PEND masked int" "0,1" line.long 0x08 "CPDMA_RX_INTMASK_SET,CPDMA_INT RX interrupt mask set register" hexmask.long.word 0x08 16.--31. 1. "RESERVED," newline bitfld.long 0x08 15. "RX7_THRESH_PEND_MASK,RX Channel 7 Threshold Pending Int" "0,1" newline bitfld.long 0x08 14. "RX6_THRESH_PEND_MASK,RX Channel 6 Threshold Pending Int" "0,1" newline bitfld.long 0x08 13. "RX5_THRESH_PEND_MASK,RX Channel 5 Threshold Pending Int" "0,1" newline bitfld.long 0x08 12. "RX4_THRESH_PEND_MASK,RX Channel 4 Threshold Pending Int" "0,1" newline bitfld.long 0x08 11. "RX3_THRESH_PEND_MASK,RX Channel 3 Threshold Pending Int" "0,1" newline bitfld.long 0x08 10. "RX2_THRESH_PEND_MASK,RX Channel 2 Threshold Pending Int" "0,1" newline bitfld.long 0x08 9. "RX1_THRESH_PEND_MASK,RX Channel 1 Threshold Pending Int" "0,1" newline bitfld.long 0x08 8. "RX0_THRESH_PEND_MASK,RX Channel 0 Threshold Pending Int" "0,1" newline bitfld.long 0x08 7. "RX7_PEND_MASK,RX Channel 7 Pending Int" "0,1" newline bitfld.long 0x08 6. "RX6_PEND_MASK,RX Channel 6 Pending Int" "0,1" newline bitfld.long 0x08 5. "RX5_PEND_MASK,RX Channel 5 Pending Int" "0,1" newline bitfld.long 0x08 4. "RX4_PEND_MASK,RX Channel 4 Pending Int" "0,1" newline bitfld.long 0x08 3. "RX3_PEND_MASK,RX Channel 3 Pending Int" "0,1" newline bitfld.long 0x08 2. "RX2_PEND_MASK,RX Channel 2 Pending Int" "0,1" newline bitfld.long 0x08 1. "RX1_PEND_MASK,RX Channel 1 Pending Int" "0,1" newline bitfld.long 0x08 0. "RX0_PEND_MASK,RX Channel 0 Pending Int" "0,1" line.long 0x0C "CPDMA_RX_INTMASK_CLEAR,CPDMA_INT RX interrupt mask clear register" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," newline bitfld.long 0x0C 15. "RX7_THRESH_PEND_MASK,RX Channel 7 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 14. "RX6_THRESH_PEND_MASK,RX Channel 6 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 13. "RX5_THRESH_PEND_MASK,RX Channel 5 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 12. "RX4_THRESH_PEND_MASK,RX Channel 4 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 11. "RX3_THRESH_PEND_MASK,RX Channel 3 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 10. "RX2_THRESH_PEND_MASK,RX Channel 2 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 9. "RX1_THRESH_PEND_MASK,RX Channel 1 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 8. "RX0_THRESH_PEND_MASK,RX Channel 0 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 7. "RX7_PEND_MASK,RX Channel 7 Pending Int" "0,1" newline bitfld.long 0x0C 6. "RX6_PEND_MASK,RX Channel 6 Pending Int" "0,1" newline bitfld.long 0x0C 5. "RX5_PEND_MASK,RX Channel 5 Pending Int" "0,1" newline bitfld.long 0x0C 4. "RX4_PEND_MASK,RX Channel 4 Pending Int" "0,1" newline bitfld.long 0x0C 3. "RX3_PEND_MASK,RX Channel 3 Pending Int" "0,1" newline bitfld.long 0x0C 2. "RX2_PEND_MASK,RX Channel 2 Pending Int" "0,1" newline bitfld.long 0x0C 1. "RX1_PEND_MASK,RX Channel 1 Pending Int" "0,1" newline bitfld.long 0x0C 0. "RX0_PEND_MASK,RX Channel 0 Pending Int" "0,1" line.long 0x10 "CPDMA_DMA_INTSTAT_RAW,CPDMA_INT DMA interrupt status register (raw value)" hexmask.long 0x10 2.--31. 1. "RESERVED," newline bitfld.long 0x10 1. "HOST_PEND,Host Pending Interrupt - raw int read (before mask)" "0,1" newline bitfld.long 0x10 0. "STAT_PEND,Statistics Pending Interrupt - raw int read (before mask)" "0,1" line.long 0x14 "CPDMA_DMA_INTSTAT_MASKED,CPDMA_INT DMA interrupt status register (masked value)" hexmask.long 0x14 2.--31. 1. "RESERVED," newline bitfld.long 0x14 1. "HOST_PEND,Host Pending Interrupt - masked interrupt" "0,1" newline bitfld.long 0x14 0. "STAT_PEND,Statistics Pending Interrupt - masked interrupt" "0,1" line.long 0x18 "CPDMA_DMA_INTMASK_SET,CPDMA_INT DMA interrupt mask set register" hexmask.long 0x18 2.--31. 1. "RESERVED," newline bitfld.long 0x18 1. "HOST_ERR_INT_MASK,Host Error Interrupt Mask - Write one to enable interrupt" "0,1" newline rbitfld.long 0x18 0. "STAT_INT_MASK,Statistics Interrupt Mask - Write one to enable interrupt" "0,1" line.long 0x1C "CPDMA_DMA_INTMASK_CLEAR,CPDMA_INT DMA interrupt mask clear register" hexmask.long 0x1C 2.--31. 1. "RESERVED," newline bitfld.long 0x1C 1. "HOST_ERR_INT_MASK,Host Error Interrupt Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x1C 0. "STAT_INT_MASK,Statistics Interrupt Mask - Write one to disable interrupt" "0,1" line.long 0x20 "CPDMA_RX0_PENDTHRESH,CPDMA_INT receive threshold pending register channel 0" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x20 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x24 "CPDMA_RX1_PENDTHRESH,CPDMA_INT receive threshold pending register channel 1" hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x24 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x28 "CPDMA_RX2_PENDTHRESH,CPDMA_INT receive threshold pending register channel 2" hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x28 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x2C "CPDMA_RX3_PENDTHRESH,CPDMA_INT receive threshold pending register channel 3" hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x2C 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x30 "CPDMA_RX4_PENDTHRESH,CPDMA_INT receive threshold pending register channel 4" hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x30 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x34 "CPDMA_RX5_PENDTHRESH,CPDMA_INT receive threshold pending register channel 5" hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x34 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x38 "CPDMA_RX6_PENDTHRESH,CPDMA_INT receive threshold pending register channel 6" hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x38 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x3C "CPDMA_RX7_PENDTHRESH,CPDMA_INT receive threshold pending register channel 7" hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x3C 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x40 "CPDMA_RX0_FREEBUFFER,CPDMA_INT receive free buffer register channel 0" hexmask.long.word 0x40 16.--31. 1. "RESERVED," newline hexmask.long.word 0x40 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x44 "CPDMA_RX1_FREEBUFFER,CPDMA_INT receive free buffer register channel 1" hexmask.long.word 0x44 16.--31. 1. "RESERVED," newline hexmask.long.word 0x44 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x48 "CPDMA_RX2_FREEBUFFER,CPDMA_INT receive free buffer register channel 2" hexmask.long.word 0x48 16.--31. 1. "RESERVED," newline hexmask.long.word 0x48 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x4C "CPDMA_RX3_FREEBUFFER,CPDMA_INT receive free buffer register channel 3" hexmask.long.word 0x4C 16.--31. 1. "RESERVED," newline hexmask.long.word 0x4C 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x50 "CPDMA_RX4_FREEBUFFER,CPDMA_INT receive free buffer register channel 4" hexmask.long.word 0x50 16.--31. 1. "RESERVED," newline hexmask.long.word 0x50 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x54 "CPDMA_RX5_FREEBUFFER,CPDMA_INT receive free buffer register channel 5" hexmask.long.word 0x54 16.--31. 1. "RESERVED," newline hexmask.long.word 0x54 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x58 "CPDMA_RX6_FREEBUFFER,CPDMA_INT receive free buffer register channel 6" hexmask.long.word 0x58 16.--31. 1. "RESERVED," newline hexmask.long.word 0x58 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x5C "CPDMA_RX7_FREEBUFFER,CPDMA_INT receive free buffer register channel 7" hexmask.long.word 0x5C 16.--31. 1. "RESERVED," newline hexmask.long.word 0x5C 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" width 0x0B tree.end tree "CPTS" base ad:0x48484C00 rgroup.long 0x00++0x07 line.long 0x00 "CPTS_IDVER,CPTS revision" line.long 0x04 "CPTS_CONTROL,Time sync control register" hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED," bitfld.long 0x04 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" bitfld.long 0x04 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x04 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x04 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" rbitfld.long 0x04 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 1. "INT_TEST,Interrupt Test - When set this bit allows the raw interrupt to be written to facilitate interrupt test" "0,1" bitfld.long 0x04 0. "CPTS_EN,Time Sync Enable - When disabled (cleared to zero) the RCLK domain is held in reset" "Time Sync Disabled,Time Sync Enabled" group.long 0x0C++0x0B line.long 0x00 "CPTS_TS_PUSH,Time stamp event push register" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "TS_PUSH,Time stamp event push - When a logic high is written to this bit a time stamp event is pushed onto the event FIFO" "0,1" line.long 0x04 "CPTS_TS_LOAD_VAL,Time stamp load value register" line.long 0x08 "CPTS_TS_LOAD_EN,Time stamp load enable register" hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "TS_LOAD_EN,Time Stamp Load - Writing a one to this bit enables the time stamp value to be written via theCPTS_TS_LOAD_VAL register" "0,1" group.long 0x20++0x0B line.long 0x00 "CPTS_INTSTAT_RAW,Time sync interrupt status raw register" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" line.long 0x04 "CPTS_INTSTAT_MASKED,Time sync interrupt status masked register" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" line.long 0x08 "CPTS_INT_ENABLE,Time sync interrupt enable register" hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" group.long 0x30++0x0B line.long 0x00 "CPTS_EVENT_POP,Event interrupt pop register" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "EVENT_POP,Event Pop - When a logic high is written to this bit an event is popped off the event FIFO" "0,1" line.long 0x04 "CPTS_EVENT_LOW,Lower 32-bits of the event value" line.long 0x08 "CPTS_EVENT_HIGH,Upper 32-bits of the event value" bitfld.long 0x08 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x08 24.--28. "PORT_NUMBER,Port Number - indicates the port number of an ethernet event or the hardware push pin number (1 to 4)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 20.--23. "EVENT_TYPE,Time Sync Event Type" "Time Stamp Push Event,Time Stamp Rollover Event,Time Stamp Half Rollover Event,Hardware Time Stamp Push Event,Ethernet Receive Event,Ethernet Transmit Event,?..." bitfld.long 0x08 16.--19. "MESSAGE_TYPE,Message type - The message type value that was contained in an ethernet transmit or receive time sync packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 0.--15. 1. "SEQUENCE_ID,Sequence ID - The 16-bit sequence id is the value that was contained in an ethernet transmit or receivetime sync packet" width 0x0B tree.end tree "CRC_CFG_TARG" base ad:0x4A261000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CRC_FW" base ad:0x4A244000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" newline rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "CRC_FW_CFG_TARG" base ad:0x4A245000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CRC_TARG" base ad:0x44000700 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "CTRL_MODULE_CORE" base ad:0x4A002000 group.long 0x114++0x0F line.long 0x00 "CTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1," rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 26. "MCASP1_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 23.--25. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 22. "IPU1_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 17.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16. "EVE1_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 13. "CT_TBR_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x00 12. "DEBUGSS_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x00 11. "EMIF_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 6.--10. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5. "ISS_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x00 4. "DSS_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x00 3. "L3RAM1_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 1.--2. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 0. "GPMC_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" line.long 0x04 "CTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1," rbitfld.long 0x04 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 26. "MCASP1_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 23.--25. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 22. "IPU1_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 17.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 16. "EVE1_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 13. "CT_TBR_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x04 12. "DEBUGSS_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x04 11. "EMIF_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 6.--10. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 5. "ISS_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x04 4. "DSS_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x04 3. "L3RAM1_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 1.--2. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 0. "GPMC_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" line.long 0x08 "CTRL_CORE_L4_HW_FW_EXPORTED_VALUES_CONF," rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 27. "L4PER3_AP_SECDBG_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 26. "RESERVED," "0,1" newline bitfld.long 0x08 25. "L4PER2_AP_SECDBG_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 24. "RESERVED," "0,1" newline bitfld.long 0x08 23. "L4WAKEUP_AP_SECDBG_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 21.--22. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 20. "L4CONFIG_AP_SECDBG_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 16. "L4PER1_AP_SECDBG_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 11. "L4PER3_AP_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 10. "RESERVED," "0,1" newline bitfld.long 0x08 9. "L4PER2_AP_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 8. "RESERVED," "0,1" newline bitfld.long 0x08 7. "L4WAKEUP_AP_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 5.--6. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 4. "L4CONFIG_AP_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 0. "L4PER1_AP_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" line.long 0x0C "CTRL_CORE_SEC_LOAD_FW_EXPORTED_VALUE," hexmask.long 0x0C 6.--31. 1. "RESERVED," newline bitfld.long 0x0C 5. "L4_PER3_LOAD_FW_EXPORTED_VALUE_REQN,LOAD FW exported values" "L4_PER3_LOAD_FW_EXPORTED_VALUE_REQN_0,L4_PER3_LOAD_FW_EXPORTED_VALUE_REQN_1" newline bitfld.long 0x0C 4. "L4_PER2_LOAD_FW_EXPORTED_VALUE_REQN,LOAD FW exported values" "L4_PER2_LOAD_FW_EXPORTED_VALUE_REQN_0,L4_PER2_LOAD_FW_EXPORTED_VALUE_REQN_1" newline bitfld.long 0x0C 3. "L4_PER1_LOAD_FW_EXPORTED_VALUE_REQN,LOAD FW exported values" "L4_PER1_LOAD_FW_EXPORTED_VALUE_REQN_0,L4_PER1_LOAD_FW_EXPORTED_VALUE_REQN_1" newline bitfld.long 0x0C 2. "L4_CONFIG_LOAD_FW_EXPORTED_VALUE_REQN,LOAD FW exported values" "L4_CONFIG_LOAD_FW_EXPORTED_VALUE_REQN_0,L4_CONFIG_LOAD_FW_EXPORTED_VALUE_REQN_1" newline bitfld.long 0x0C 1. "L4_WAKEUP_LOAD_FW_EXPORTED_VALUE_REQN,LOAD FW exported values" "L4_WAKEUP_LOAD_FW_EXPORTED_VALUE_REQN_0,L4_WAKEUP_LOAD_FW_EXPORTED_VALUE_REQN_1" newline rbitfld.long 0x0C 0. "RESERVED," "0,1" rgroup.long 0x134++0x03 line.long 0x00 "CTRL_CORE_STATUS,Control Module Status Register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 6.--8. "DEVICE_TYPE,Device type captured at reset time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--5. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x148++0x03 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_FUNC_1,Firewall Error Status functional Register 1" rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 28. "EVE1_FW_ERROR,EVE1 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 23.--27. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 22. "L4_WAKEUP_FW_ERROR,L4 wakeup firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18. "DEBUGSS_FW_ERROR,DebugSS firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 17. "L4_CONFIG_FW_ERROR,L4 config firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 16. "L4_PERIPH1_FW_ERROR,L4 periph1 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "DSS_FW_ERROR,DSS firewall" "No error from firewall,Error from firewall" newline hexmask.long.byte 0x00 6.--13. 1. "RESERVED," newline bitfld.long 0x00 5. "IPU1_FW_ERROR,IPU1 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 4. "RESERVED," "0,1" newline bitfld.long 0x00 3. "EMIF_FW_ERROR,EMIF firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 2. "GPMC_FW_ERROR,GPMC firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 1. "L3RAM1_FW_ERROR,L3RAM1 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x150++0x03 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_DEBUG_1,Firewall Error Status Debug Register 1" rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 28. "EVE1_DBGFW_ERROR,EVE1 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 23.--27. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 22. "L4_WAKEUP_DBGFW_ERROR,L4 wakeup firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18. "DEBUGSS_DBGFW_ERROR,DebugSS firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 17. "L4_CONFIG_DBGFW_ERROR,L4 config firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 16. "L4_PERIPH1_DBGFW_ERROR,L4 periph1 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "DSS_DBGFW_ERROR,DSS debug firewall" "No error from firewall,Error from firewall" newline hexmask.long.byte 0x00 6.--13. 1. "RESERVED," newline bitfld.long 0x00 5. "IPU1_DBGFW_ERROR,IPU1 debug firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 4. "RESERVED," "0,1" newline bitfld.long 0x00 3. "EMIF_DBGFW_ERROR,EMIF debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 2. "GPMC_DBGFW_ERROR,GPMC debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 1. "L3RAM1_DBGFW_ERROR,L3RAM1 debug firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 0. "RESERVED," "0,1" rgroup.long 0x1CC++0x13 line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_0,Standard Fuse OPP VDD_CORE [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_1,Standard Fuse OPP VDD_CORE [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_2,Standard Fuse OPP VDD_CORE [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_3,Standard Fuse OPP VDD_CORE [127:96]" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_4,Standard Fuse OPP VDD_CORE [159:128]" rgroup.long 0x1E8++0x03 line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_BGAP_CORE,Trim values for CORE associated temperature sensor and bandgap" hexmask.long.byte 0x00 24.--31. 1. "STD_FUSE_OPP_BGAP_CORE_0,Trim values for CORE associated temperature sensor and bandgap" newline hexmask.long.byte 0x00 16.--23. 1. "STD_FUSE_OPP_BGAP_CORE_1,Trim values for CORE associated temperature sensor and bandgap" newline hexmask.long.byte 0x00 8.--15. 1. "STD_FUSE_OPP_BGAP_CORE_2,Trim values for CORE associated temperature sensor and bandgap" newline hexmask.long.byte 0x00 0.--7. 1. "STD_FUSE_OPP_BGAP_CORE_3,Trim values for CORE associated temperature sensor and bandgap" rgroup.long 0x220++0x1F line.long 0x00 "CTRL_CORE_STD_FUSE_MPK_0,Standard Fuse keys" line.long 0x04 "CTRL_CORE_STD_FUSE_MPK_1,Standard Fuse keys" line.long 0x08 "CTRL_CORE_STD_FUSE_MPK_2,Standard Fuse keys" line.long 0x0C "CTRL_CORE_STD_FUSE_MPK_3,Standard Fuse keys" line.long 0x10 "CTRL_CORE_STD_FUSE_MPK_4,Standard Fuse keys" line.long 0x14 "CTRL_CORE_STD_FUSE_MPK_5,Standard Fuse keys" line.long 0x18 "CTRL_CORE_STD_FUSE_MPK_6,Standard Fuse keys" line.long 0x1C "CTRL_CORE_STD_FUSE_MPK_7,Standard Fuse keys" rgroup.long 0x2BC++0x1B line.long 0x00 "CTRL_CORE_CUST_FUSE_SWRV_0,Customer Fuse keys" line.long 0x04 "CTRL_CORE_CUST_FUSE_SWRV_1,Customer Fuse keys" line.long 0x08 "CTRL_CORE_CUST_FUSE_SWRV_2,Customer Fuse keys" line.long 0x0C "CTRL_CORE_CUST_FUSE_SWRV_3,Customer Fuse keys" line.long 0x10 "CTRL_CORE_CUST_FUSE_SWRV_4,Customer Fuse keys" line.long 0x14 "CTRL_CORE_CUST_FUSE_SWRV_5,Customer Fuse keys" line.long 0x18 "CTRL_CORE_CUST_FUSE_SWRV_6,Customer Fuse keys" group.long 0x2E0++0x0F line.long 0x00 "CTRL_CORE_BREG_SELECTION,DPLL selection" hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED," newline bitfld.long 0x00 14. "SEL_DDR,Selection ddr" "no dpll selected,rdpll selected" newline rbitfld.long 0x00 13. "RESERVED," "0,1" newline bitfld.long 0x00 12. "SEL_GMAC,Selection gmac" "no dpll selected,rdpll selected" newline bitfld.long 0x00 11. "SEL_DSP,Selection dsp" "no dpll selected,rdpll selected" newline bitfld.long 0x00 10. "SEL_EVE,Selection eve" "no dpll selected,rdpll selected" newline rbitfld.long 0x00 6.--9. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5. "SEL_PER,Selection per" "no dpll selected,rdpll selected" newline bitfld.long 0x00 4. "SEL_HDMI,Selection hdmi" "no dpll selected,rdpll selected" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 1. "SEL_CORE,Selection core" "no dpll selected,rdpll selected" newline bitfld.long 0x00 0. "SEL_IPU,Selection ipu" "no dpll selected,rdpll selected" line.long 0x04 "CTRL_CORE_DPLL_BCLK,DPPL obs" hexmask.long 0x04 2.--31. 1. "RESERVED," newline bitfld.long 0x04 1. "BRW,Reset" "no reset,reset" newline bitfld.long 0x04 0. "BCLK,clock" "0,1" line.long 0x08 "CTRL_CORE_DPLL_BADDR_BDATAW,DPLL addr and dataw" hexmask.long.word 0x08 20.--31. 1. "RESERVED," newline bitfld.long 0x08 16.--19. "BADDR,baddr" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 0.--15. 1. "BDATAW,bdataw" line.long 0x0C "CTRL_CORE_DPLL_BDATAR,DPLL datar" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--15. 1. "BDATAR,datar" rgroup.long 0x334++0x03 line.long 0x00 "CTRL_CORE_TEMP_SENSOR_CORE,Control VBGAPTS temperature sensor and thermal comparator shutdown register" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED," newline bitfld.long 0x00 11. "BGAP_TMPSOFF_CORE,This bit indicates the temperature sensor state" "0,1" newline bitfld.long 0x00 10. "BGAP_EOCZ_CORE,ADC End of Conversion" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "BGAP_DTEMP_CORE,Temperature data from the ADC" group.long 0x358++0x0B line.long 0x00 "CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR,Cortex M4 register" hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--19. 1. "CORTEX_M4_MMUADDRTRANSLTR,Used to save the mmu address boot" line.long 0x04 "CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR," hexmask.long.word 0x04 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x04 0.--19. 1. "CORTEX_M4_MMUADDRLOGICTR," line.long 0x08 "CTRL_CORE_HWOBS_CONTROL,HW observability control" hexmask.long.word 0x08 19.--31. 1. "RESERVED," newline bitfld.long 0x08 14.--18. "HWOBS_CLKDIV_SEL_2,Clock divider selection for obs2 line" "?,output is not divided,output is divided by 2,?,output is divided by 4,?,?,?,output is divided by 8,?,?,?,?,?,?,?,output is divided by 16,?..." newline bitfld.long 0x08 9.--13. "HWOBS_CLKDIV_SEL_1,Clock divider selection for obs1 line" "?,output is not divided,output is divided by 2,?,output is divided by 4,?,?,?,output is divided by 8,?,?,?,?,?,?,?,output is divided by 16,?..." newline rbitfld.long 0x08 8. "RESERVED," "0,1" newline bitfld.long 0x08 3.--7. "HWOBS_CLKDIV_SEL,Clock divider selection for obs0 line" "?,output is not divided,output is divided by 2,?,output is divided by 4,?,?,?,output is divided by 8,?,?,?,?,?,?,?,output is divided by 16,?..." newline bitfld.long 0x08 2. "HWOBS_ALL_ZERO_MODE,Used to gate observable signals" "hw observability ports are not gated,hw observability ports are all set to 0" newline bitfld.long 0x08 1. "HWOBS_ALL_ONE_MODE,Used to gate observable signals" "hw observability ports are not gated,hw observability ports are all set to 1" newline bitfld.long 0x08 0. "HWOBS_MACRO_ENABLE,Used to gate observable signals coming from macros using the 32-bit HWOBS bus definition" "hw observability ports from macros are gated and..,hw observability ports from macros are not gated" group.long 0x380++0x03 line.long 0x00 "CTRL_CORE_BANDGAP_MASK_1,bgap_mask" bitfld.long 0x00 30.--31. "SIDLEMODE,sidlemode for bandgap" "No Idle,Force Idle,Smart Idle,Reserved" newline bitfld.long 0x00 27.--29. "COUNTER_DELAY,Counter delay" "Imediat,Delay of 1ms,Delay of 10ms,Delay of 100ms,Delay of 250ms,Delay of 500ms,?..." newline rbitfld.long 0x00 24.--26. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 23. "FREEZE_CORE,Freeze the FIFO CORE" "No operation,Freeze the FIFO" newline rbitfld.long 0x00 21.--22. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 20. "CLEAR_CORE,Reset the FIFO CORE" "No operation,Reset the FIFO" newline hexmask.long.word 0x00 6.--19. 1. "RESERVED," newline bitfld.long 0x00 5. "MASK_HOT_CORE,Mask for hot event CORE" "hot event is masked,hot event is not masked" newline bitfld.long 0x00 4. "MASK_COLD_CORE,Mask for cold event CORE" "cold event is masked,cold event is not masked" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38C++0x03 line.long 0x00 "CTRL_CORE_BANDGAP_THRESHOLD_CORE,BGAP THRESHOLD CORE" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 16.--25. 1. "THOLD_HOT_CORE,Value for the high temperature threshold" newline rbitfld.long 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--9. 1. "THOLD_COLD_CORE,Value for the low temperature threshold" rgroup.long 0x398++0x03 line.long 0x00 "CTRL_CORE_BANDGAP_TSHUT_CORE,BGAP TSHUT THRESHOLD CORE" bitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 16.--25. 1. "TSHUT_HOT_CORE,tshut value hot" newline bitfld.long 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--9. 1. "TSHUT_COLD_CORE,tshut value cold" rgroup.long 0x3A8++0x03 line.long 0x00 "CTRL_CORE_BANDGAP_STATUS_1,BGAP STATUS" bitfld.long 0x00 31. "ALERT,Alert temperature when '1'" "0,1" newline hexmask.long 0x00 6.--30. 1. "RESERVED," newline bitfld.long 0x00 5. "HOT_CORE,Event for hot temperature mpu bandgap when '1'" "event not detected,event detected" newline bitfld.long 0x00 4. "COLD_CORE,Event for cold temperature mpu bandgap when '1'" "event not detected,event detected" newline bitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x3E8++0x17 line.long 0x00 "CTRL_CORE_DTEMP_CORE_0,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x00 10.--31. 1. "DTEMP_TAG_CORE_0,tag" newline hexmask.long.word 0x00 0.--9. 1. "DTEMP_TEMPERATURE_CORE_0,temperature" line.long 0x04 "CTRL_CORE_DTEMP_CORE_1,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x04 10.--31. 1. "DTEMP_TAG_CORE_1,tag" newline hexmask.long.word 0x04 0.--9. 1. "DTEMP_TEMPERATURE_CORE_1,temperature" line.long 0x08 "CTRL_CORE_DTEMP_CORE_2,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x08 10.--31. 1. "DTEMP_TAG_CORE_2,tag" newline hexmask.long.word 0x08 0.--9. 1. "DTEMP_TEMPERATURE_CORE_2,temperature" line.long 0x0C "CTRL_CORE_DTEMP_CORE_3,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x0C 10.--31. 1. "DTEMP_TAG_CORE_3,tag" newline hexmask.long.word 0x0C 0.--9. 1. "DTEMP_TEMPERATURE_CORE_3,temperature" line.long 0x10 "CTRL_CORE_DTEMP_CORE_4,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x10 10.--31. 1. "DTEMP_TAG_CORE_4,tag" newline hexmask.long.word 0x10 0.--9. 1. "DTEMP_TEMPERATURE_CORE_4,temperature" line.long 0x14 "CTRL_CORE_SMA_SW_0,Inversion control for SD_DAC input data - DIN[9:0]" hexmask.long 0x14 3.--31. 1. "RESERVED," newline bitfld.long 0x14 2. "INPUTINV,Inversion control for SD_DAC input data - DIN[9:0]" "This value should be used for inverted video..,This value should be used for non-inverted video.." newline rbitfld.long 0x14 1. "RESERVED," "0,1" newline bitfld.long 0x14 0. "CKE_ASSERTION,Forces the EMIF CKE pad to tri-state" "The CKE pad is not in tri-state and can be..,The CKE pad is in tri-state" group.long 0x408++0x07 line.long 0x00 "CTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline bitfld.long 0x00 19. "CRC_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 18. "RESERVED," "0,1" newline bitfld.long 0x00 17. "TESOC_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 16. "RESERVED," "0,1" newline bitfld.long 0x00 15. "MMU1_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11. "TSC_ADC_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x00 10. "EDMA_TPCC_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x00 9. "EDMA_TC_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x00 8. "QSPI_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 1. "DSP2_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x00 0. "DSP1_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" line.long 0x04 "CTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2," hexmask.long.word 0x04 20.--31. 1. "RESERVED," newline bitfld.long 0x04 19. "CRC_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 18. "RESERVED," "0,1" newline bitfld.long 0x04 17. "TESOC_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 16. "RESERVED," "0,1" newline bitfld.long 0x04 15. "MMU1_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 11. "TSC_ADC_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x04 10. "EDMA_TPCC_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x04 9. "EDMA_TC_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x04 8. "QSPI_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 1. "DSP2_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x04 0. "DSP1_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" group.long 0x414++0x03 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_FUNC_2,Firewall Error Status functional Register 2" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 26. "TC1_EDMA_FW_ERROR,EDMA TC1 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 23.--25. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 22. "QSPI_FW_ERROR,QSPI firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 17. "TPCC_EDMA_FW_ERROR,EDMA TPCC firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 16. "TC0_EDMA_FW_ERROR,EDMA TC0 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 11. "MCASP1_FW_ERROR,McASP1 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 6.--10. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5. "L4_PERIPH3_FW_ERROR,L4 periph3 init firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 4. "L4_PERIPH2_FW_ERROR,L4 periph2 init firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 1. "DSP2_FW_ERROR,DSP2 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 0. "DSP1_FW_ERROR,DSP1 firewall" "No error from firewall,Error from firewall" group.long 0x41C++0x1B line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_DEBUG_2,Firewall Error Status debug Register 2" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 26. "TC1_EDMA_DBGFW_ERROR,EDMA TC1 debug firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 23.--25. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 22. "QSPI_DBGFW_ERROR,QSPI debug firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 17. "TPCC_EDMA_DBGFW_ERROR,EDMA TPCC debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 16. "TC0_EDMA_DBGFW_ERROR,EDMA TC0 debug firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 11. "MCASP1_DBGFW_ERROR,McASP1 debug firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 6.--10. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5. "L4_PERIPH3_DBGFW_ERROR,L4 periph3 init firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 4. "L4_PERIPH2_DBGFW_ERROR,L4 periph2 init firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 1. "DSP2_DBGFW_ERROR,DSP2 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 0. "DSP1_DBGFW_ERROR,DSP1 firewall" "No error from firewall,Error from firewall" line.long 0x04 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_1,Register for priority settings for EMIF arbitration" hexmask.long.tbyte 0x04 15.--31. 1. "RESERVED," newline bitfld.long 0x04 12.--14. "DSP1_CFG_EMIF_PRIORITY,DSP1 CFG priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline rbitfld.long 0x04 11. "RESERVED," "0,1" newline bitfld.long 0x04 8.--10. "DSP1_EDMA_EMIF_PRIORITY,DSP1 EDMA priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline rbitfld.long 0x04 7. "RESERVED," "0,1" newline bitfld.long 0x04 4.--6. "DSP2_EDMA_EMIF_PRIORITY,DSP2 EDMA priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 0.--2. "DSP2_CFG_EMIF_PRIORITY,DSP2 CFG priority setting" "highest priority,?,?,?,?,?,?,lowest priority" line.long 0x08 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_2,Register for priority settings for EMIF arbitration" hexmask.long.word 0x08 19.--31. 1. "RESERVED," newline bitfld.long 0x08 16.--18. "EVE1_TC0_EMIF_PRIORITY,EVE1 TC0 priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline hexmask.long.word 0x08 0.--15. 1. "RESERVED," line.long 0x0C "CTRL_CORE_EMIF_INITIATOR_PRIORITY_3,Register for priority settings for EMIF arbitration" hexmask.long.word 0x0C 19.--31. 1. "RESERVED," newline bitfld.long 0x0C 16.--18. "IPU1_EMIF_PRIORITY,IPU1 priority setting" "highest prioroty,?,?,?,?,?,?,lowest priority" newline hexmask.long.word 0x0C 3.--15. 1. "RESERVED," newline bitfld.long 0x0C 0.--2. "EDMA_TC0_EMIF_PRIORITY,EDMA TC0 priority setting" "highest priority,?,?,?,?,?,?,lowest priority" line.long 0x10 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_4,Register for priority settings for EMIF arbitration" rbitfld.long 0x10 31. "RESERVED," "0,1" newline bitfld.long 0x10 28.--30. "EDMA_TC1_EMIF_PRIORITY,EDMA TC1 priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline rbitfld.long 0x10 27. "RESERVED," "0,1" newline bitfld.long 0x10 24.--26. "DSS_EMIF_PRIORITY,DSS priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline hexmask.long.word 0x10 11.--23. 1. "RESERVED," newline bitfld.long 0x10 8.--10. "VIP1_P1_P2_EMIF_PRIORITY,VIP1 priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline hexmask.long.byte 0x10 0.--7. 1. "RESERVED," line.long 0x14 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_5,Register for priority settings for EMIF arbitration" hexmask.long.tbyte 0x14 15.--31. 1. "RESERVED," newline bitfld.long 0x14 12.--14. "GMAC_SW_EMIF_PRIORITY,GMAC_SW priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline hexmask.long.word 0x14 0.--11. 1. "RESERVED," line.long 0x18 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_6,Register for priority settings for EMIF arbitration" hexmask.long.tbyte 0x18 11.--31. 1. "RESERVED," newline bitfld.long 0x18 8.--10. "EVE1_TC1_EMIF_PRIORITY,EVE1 TC1 priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline hexmask.long.byte 0x18 0.--7. 1. "RESERVED," group.long 0x43C++0x03 line.long 0x00 "CTRL_CORE_L3_INITIATOR_PRESSURE_1,Register for pressure settings for L3 arbitration" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline bitfld.long 0x00 17.--18. "DSP1_CFG_L3_PRESSURE,DSP1 CFG pressure setting" "lowest,?,?,highest" newline rbitfld.long 0x00 11.--16. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9.--10. "DSP2_CFG_L3_PRESSURE,DSP2 CFG pressure setting" "lowest,?,?,highest" newline hexmask.long.word 0x00 0.--8. 1. "RESERVED," rgroup.long 0x4E8++0x1B line.long 0x00 "CTRL_CORE_CUST_FUSE_UID_0,Customer Fuse keys" line.long 0x04 "CTRL_CORE_CUST_FUSE_UID_1,Customer Fuse keys" line.long 0x08 "CTRL_CORE_CUST_FUSE_UID_2,Customer Fuse keys" line.long 0x0C "CTRL_CORE_CUST_FUSE_UID_3,Customer Fuse keys" line.long 0x10 "CTRL_CORE_CUST_FUSE_UID_4,Customer Fuse keys" line.long 0x14 "CTRL_CORE_CUST_FUSE_UID_5,Customer Fuse keys" line.long 0x18 "CTRL_CORE_CUST_FUSE_UID_6,Customer Fuse keys" rgroup.long 0x514++0x0F line.long 0x00 "CTRL_CORE_MAC_ID_SW_0,Standard Fuse keys. MAC ID_1 [63:32]" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--23. 1. "STD_FUSE_MAC_ID_SW_0,This bit field contains the last three octets (NIC specific) of the MAC address of the GMAC_SW port 0" line.long 0x04 "CTRL_CORE_MAC_ID_SW_1,Standard Fuse keys. MAC ID_1 [31:0]" hexmask.long.byte 0x04 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x04 0.--23. 1. "STD_FUSE_MAC_ID_SW_1,This bit field contains the last three octets (the OUI) of the MAC address of the GMAC_SW port 0" line.long 0x08 "CTRL_CORE_MAC_ID_SW_2,Standard Fuse keys. MAC ID_2 [63:32]" hexmask.long.byte 0x08 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x08 0.--23. 1. "STD_FUSE_MAC_ID_SW_2,This bit field contains the last three octets (NIC specific) of the MAC address of the GMAC_SW port 1" line.long 0x0C "CTRL_CORE_MAC_ID_SW_3,Standard Fuse keys. MAC ID_2 [31:0]" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x0C 0.--23. 1. "STD_FUSE_MAC_ID_SW_3,This bit field contains the last three octets (the OUI) of the MAC address of the GMAC_SW port 1" group.long 0x534++0x03 line.long 0x00 "CTRL_CORE_SMA_SW_1,OCP Spare Register" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 26. "RGMII2_ID_MODE_N,Ethernet RGMII port 2 internal delay on transmit (SR2.0 Only)" "Internal delay enabled,Internal delay disabled" newline bitfld.long 0x00 25. "RGMII1_ID_MODE_N,Ethernet RGMII port 1 internal delay on transmit (SR2.0 Only)" "Internal delay enabled,Internal delay disabled" newline rbitfld.long 0x00 23.--24. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 22. "DSS_CH0_ON_OFF,DSS Channel 0 Pixel clock control On/Off" "HSYNC and VSYNC are driven on opposite edges of..,HSYNC and VSYNC are driven according to bit.." newline rbitfld.long 0x00 20.--21. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 19. "DSS_CH0_IPC,DSS Channel 0 IPC control" "Data is driven on the LCD data lines on the..,Data is driven on the LCD data lines on the.." newline rbitfld.long 0x00 17.--18. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 16. "DSS_CH0_RF,DSS Channel 0 Rise/Fall control" "HSYNC and VSYNC are driven on falling edge of..,HSYNC and VSYNC are driven on rising edge of.." newline hexmask.long.word 0x00 4.--15. 1. "RESERVED," newline bitfld.long 0x00 3. "VIP1_CLK_INV_PORT_2B,VIP1 Slice 1 Clock inversion for Port B enable" "Clock inversion is disabled,Clock inversion is enabled" newline bitfld.long 0x00 2. "VIP1_CLK_INV_PORT_1B,VIP1 Slice 0 Clock inversion for Port B enable" "Clock inversion is disabled,Clock inversion is enabled" newline bitfld.long 0x00 1. "VIP1_CLK_INV_PORT_2A,VIP1 Slice 1 Clock inversion for Port A enable" "Clock inversion is disabled,Clock inversion is enabled" newline bitfld.long 0x00 0. "VIP1_CLK_INV_PORT_1A,VIP1 Slice 0 Clock inversion for Port A enable" "Clock inversion is disabled,Clock inversion is enabled" group.long 0x53C++0x2B line.long 0x00 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_8,Register for priority settings for EMIF arbitration" hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED," newline bitfld.long 0x00 12.--14. "ISS_NRT_EMIF_PRIORITY,ISS NRT ports priority setting" "ISS_NRT_EMIF_PRIORITY_0,?,?,?,?,?,?,ISS_NRT_EMIF_PRIORITY_7" newline rbitfld.long 0x00 11. "RESERVED," "0,1" newline bitfld.long 0x00 8.--10. "ISS_RT_EMIF_PRIORITY,ISS RT port priority setting" "ISS_RT_EMIF_PRIORITY_0,?,?,?,?,?,?,ISS_RT_EMIF_PRIORITY_7" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," line.long 0x04 "CTRL_CORE_MMR_LOCK_1,Register to lock memory regions from 0x0000 0100 to 0x0000 079F and from 0x0000 1A00 to 0x0000 1FFF" line.long 0x08 "CTRL_CORE_MMR_LOCK_2,Register to lock memory region starting at address offset 0x0000 07A0 and ending at address offset 0x0000 0D9F" line.long 0x0C "CTRL_CORE_MMR_LOCK_3,Register to lock memory region starting at address offset 0x0000 0DA0 and ending at address offset 0x0000 0FFF" line.long 0x10 "CTRL_CORE_MMR_LOCK_4,Register to lock memory region starting at address offset 0x0000 1000 and ending at address offset 0x0000 13FF" line.long 0x14 "CTRL_CORE_MMR_LOCK_5,Register to lock memory region starting at address offset 0x0000 1400 and ending at address offset 0x0000 19FF" line.long 0x18 "CTRL_CORE_CONTROL_IO_1,Register to configure some IP level signals" hexmask.long.word 0x18 17.--31. 1. "RESERVED," newline bitfld.long 0x18 16. "MMU1_DISABLE,MMU1 DISABLE setting" "0,1" newline rbitfld.long 0x18 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x18 12.--13. "TC1_DEFAULT_BURST_SIZE,EDMA TC1 DEFAULT BURST SIZE setting" "0,1,2,3" newline rbitfld.long 0x18 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x18 8.--9. "TC0_DEFAULT_BURST_SIZE,EDMA TC0 DEFAULT BURST SIZE setting" "0,1,2,3" newline rbitfld.long 0x18 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x18 4.--5. "GMII2_SEL,GMII2 selection setting" "GMII/MII,RMII,RGMII,Reserved" newline rbitfld.long 0x18 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x18 0.--1. "GMII1_SEL,GMII1 selection setting" "GMII/MII,RMII,RGMII,Reserved" line.long 0x1C "CTRL_CORE_CONTROL_IO_2,Register to configure some IP level signals" rbitfld.long 0x1C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 24.--26. "RTI_RESET_SELECTION_TO_PRCM,RTI reset mux select value" "RTI1,RTI2,RTI3,RTI4,RTI5,?..." newline bitfld.long 0x1C 23. "GMAC_RESET_ISOLATION_ENABLE,Reset isolation enable setting" "Reset is not isolated,Reset is isolated" newline rbitfld.long 0x1C 21.--22. "RESERVED," "0,1,2,3" newline bitfld.long 0x1C 20. "PWMSS1_TBCLKEN,PWMSS1 CLOCK ENABLE setting" "0,1" newline rbitfld.long 0x1C 16.--19. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 15. "VIP1_VIN2_INPUT_SELECTION,VIP1 vin2 input selection setting" "Input from pins selected,Input from LVDSRX port2 selected" newline bitfld.long 0x1C 14. "VIP1_VIN1_INPUT_SELECTION,VIP1 vin1 input selection setting" "Input from pins selected,Input from LVDSRX port1 selected" newline rbitfld.long 0x1C 11.--13. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8.--10. "QSPI_MEMMAPPED_CS,QSPI CS MAPPING setting" "The QSPI configuration registers are accessed,An external device connected to CS0 is accessed,An external device connected to CS1 is accessed,An external device connected to CS2 is accessed..,?..." newline rbitfld.long 0x1C 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x1C 5. "DCAN2_RAMINIT_START,DCAN2 RAM INIT START setting (SR1.0 Only)" "0,1" newline bitfld.long 0x1C 4. "DSS_DESHDCP_DISABLE,DSS DESHDCP DISABLE setting" "0,1" newline bitfld.long 0x1C 3. "DCAN_RAMINIT_START,DCAN RAM INIT START setting To initialize DCAN RAM the bit should be set to 0x1" "0,1" newline bitfld.long 0x1C 2. "DCAN2_RAMINIT_DONE,DCAN2 RAM INIT DONE status (SR1.0 Only)" "0,1" newline bitfld.long 0x1C 1. "DCAN_RAMINIT_DONE,DCAN RAM INIT DONE status: is called on SR1.0 devices" "0,1" newline bitfld.long 0x1C 0. "DSS_DESHDCP_CLKEN,DSS DESHDCP CLOCK ENABLE setting" "0,1" line.long 0x20 "CTRL_CORE_CONTROL_DSP1_RST_VECT,Register for storing DSP1 reset vector" bitfld.long 0x20 27.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x20 24.--26. "DSP1_NUM_MM,Number of DSP instances in the SoC" "?,1,2,?..." newline rbitfld.long 0x20 22.--23. "RESERVED," "0,1,2,3" newline hexmask.long.tbyte 0x20 0.--21. 1. "DSP1_RST_VECT,DSP1 reset vector address" line.long 0x24 "CTRL_CORE_CONTROL_DSP2_RST_VECT,Register for storing DSP2 reset vector" bitfld.long 0x24 27.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x24 24.--26. "DSP2_NUM_MM,Number of DSP instances in the SoC" "?,1,2,?..." newline rbitfld.long 0x24 22.--23. "RESERVED," "0,1,2,3" newline hexmask.long.tbyte 0x24 0.--21. 1. "DSP2_RST_VECT,DSP2 reset vector address" line.long 0x28 "CTRL_CORE_STD_FUSE_OPP_BGAP_DSPEVE,Trim values for DSPEVE associated bandgap" hexmask.long.word 0x28 16.--31. 1. "RESERVED," newline hexmask.long.byte 0x28 8.--15. 1. "STD_FUSE_OPP_BGAP_DSPEVE_0,Trim values for DSPEVE associated bandgap" newline hexmask.long.byte 0x28 0.--7. 1. "STD_FUSE_OPP_BGAP_DSPEVE_1,Trim values for DSPEVE associated bandgap" group.long 0x56C++0x03 line.long 0x00 "CTRL_CORE_LDOSRAM_DSPEVE_VOLTAGE_CTRL,DSPEVE SRAM LDO Control register" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 26. "LDOSRAMDSPEVE_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value" "LDOSRAMDSPEVE_RETMODE_MUX_CTRL_0,LDOSRAMDSPEVE_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x00 21.--25. "LDOSRAMDSPEVE_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "LDOSRAMDSPEVE_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10. "LDOSRAMDSPEVE_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value" "LDOSRAMDSPEVE_ACTMODE_MUX_CTRL_0,LDOSRAMDSPEVE_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x00 5.--9. "LDOSRAMDSPEVE_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "LDOSRAMDSPEVE_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x5E0++0x0F line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_2,This register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_NOM" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--11. 1. "STD_FUSE_OPP_VMIN_DSPEVE_2,AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_NOM" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_3,This register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_OD" hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x04 0.--11. 1. "STD_FUSE_OPP_VMIN_DSPEVE_3,AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_OD" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_4,This register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_HIGH" hexmask.long.tbyte 0x08 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x08 0.--11. 1. "STD_FUSE_OPP_VMIN_DSPEVE_4,AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_HIGH" line.long 0x0C "CTRL_CORE_RC_OSC_FREQUENCY,This register is used only on SR2.0 devices" bitfld.long 0x0C 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long 0x0C 0.--25. 1. "RC_OSC_CALIBRATION_VALUE,Used only on SR2.0 devices" rgroup.long 0x5F4++0x03 line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_2,This register contains the AVS Class 0 voltage value for the vdd voltage rail when running at OPP_NOM" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--11. 1. "STD_FUSE_OPP_VMIN_CORE_2,AVS Class 0 voltage value for the vdd voltage rail when running at OPP_NOM" group.long 0x680++0x07 line.long 0x00 "CTRL_CORE_LDOSRAM_CORE_2_VOLTAGE_CTRL,CORE 2nd SRAM LDO Control register" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 26. "LDOSRAMCORE_2_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value" "LDOSRAMCORE_2_RETMODE_MUX_CTRL_0,LDOSRAMCORE_2_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x00 21.--25. "LDOSRAMCORE_2_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "LDOSRAMCORE_2_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10. "LDOSRAMCORE_2_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value" "LDOSRAMCORE_2_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_2_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x00 5.--9. "LDOSRAMCORE_2_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "LDOSRAMCORE_2_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "CTRL_CORE_LDOSRAM_CORE_3_VOLTAGE_CTRL,CORE 3rd SRAM LDO Control register" rbitfld.long 0x04 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 26. "LDOSRAMCORE_3_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value" "LDOSRAMCORE_3_RETMODE_MUX_CTRL_0,LDOSRAMCORE_3_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x04 21.--25. "LDOSRAMCORE_3_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 16.--20. "LDOSRAMCORE_3_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 10. "LDOSRAMCORE_3_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value" "LDOSRAMCORE_3_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_3_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x04 5.--9. "LDOSRAMCORE_3_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. "LDOSRAMCORE_3_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x68C++0x07 line.long 0x00 "CTRL_CORE_NMI_DESTINATION_1,Register for routing NMI interrupt to respective cores" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline abitfld.long 0x00 0.--7. "IPU1_C1,Enable IPU1 CORE1 to receive the NMI interrupt" "0x00=NMI disabled,0x01=NMI enabled" line.long 0x04 "CTRL_CORE_NMI_DESTINATION_2,Register for routing NMI interrupt to respective cores" abitfld.long 0x04 24.--31. "IPU1_C0,Enable IPU1 CORE0 to receive the NMI interrupt" "0x00=NMI disabled,0x01=NMI enabled" newline abitfld.long 0x04 16.--23. "DSP2,Enable DSP2 to receive the NMI interrupt" "0x00=NMI disabled,0x01=NMI enabled" newline abitfld.long 0x04 8.--15. "DSP1,Enable DSP1 to receive the NMI interrupt" "0x00=NMI disabled,0x01=NMI enabled" newline hexmask.long.byte 0x04 0.--7. 1. "RESERVED," rgroup.long 0x6A0++0x1F line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_0,Standard Fuse OPP VDD_DSPEVE [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_1,Standard Fuse OPP VDD_DSPEVE [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_2,Standard Fuse OPP VDD_DSPEVE [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_3,Standard Fuse OPP VDD_DSPEVE [127:96]" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_4,Standard Fuse OPP VDD_DSPEVE [159:128]" line.long 0x14 "CTRL_CORE_CUST_FUSE_SWRV_7,Customer Fuse keys" line.long 0x18 "CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0,Standard Fuse Calibration override value [31:0]" line.long 0x1C "CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1,Standard Fuse Calibration override value [63:32]" rgroup.long 0x6C4++0x03 line.long 0x00 "CTRL_CORE_BOOTSTRAP,Register to view all the sysboot settings" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline bitfld.long 0x00 15. "DSP_CLOCK_DIVIDER,Divide factor for DSP clock" "0,1" newline bitfld.long 0x00 14. "RESERVED," "0,1" newline bitfld.long 0x00 13. "BOOTDEVICESIZE,Select the size of the flash device on CS0" "8-bit,16-bit" newline bitfld.long 0x00 11.--12. "MUXCS0DEVICE,Select IC boot sequence to be executed from a multiplexed address and data device attached to CS0" "Non-muxed device attached,Addr-Data Mux device attached,Reserved,Reserved" newline bitfld.long 0x00 10. "BOOTWAITEN,Enable the monitoring on CS0 of the wait pin at IC reset release time for read accesses" "Wait pin is not monitored for read accesses,Wait pin is monitored for read accesses" newline bitfld.long 0x00 8.--9. "SPEEDSELECT,Indicates the SYS_CLK1 frequency (from osc0)" "Reserved,20 MHz,27 MHz,19.2 MHz" newline bitfld.long 0x00 7. "RESERVED," "0,1" newline bitfld.long 0x00 6. "HWOBS_IO_SELECTION," "0,1" newline bitfld.long 0x00 5. "ADC_CLOCK_DIVIDER," "0,1" newline bitfld.long 0x00 0.--4. "BOOTMODE,SYSBOOT mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x794++0x03 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_FUNC_3," hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "CRC_FW_ERROR,CRC firewall" "CRC_FW_ERROR_0,CRC_FW_ERROR_1" group.long 0x79C++0x13 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_DEBUG_3,Security Error Status functional Register" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "CRC_DBGFW_ERROR,CRC debug firewall" "CRC_DBGFW_ERROR_0,CRC_DBGFW_ERROR_1" line.long 0x04 "CTRL_CORE_EVE_IRQ_0_1," hexmask.long.byte 0x04 25.--31. 1. "RESERVED," newline hexmask.long.word 0x04 16.--24. 1. "EVE1_IRQ_1," newline hexmask.long.byte 0x04 9.--15. 1. "RESERVED," newline hexmask.long.word 0x04 0.--8. 1. "EVE1_IRQ_0," line.long 0x08 "CTRL_CORE_EVE_IRQ_2_3," hexmask.long.byte 0x08 25.--31. 1. "RESERVED," newline hexmask.long.word 0x08 16.--24. 1. "EVE1_IRQ_3," newline hexmask.long.byte 0x08 9.--15. 1. "RESERVED," newline hexmask.long.word 0x08 0.--8. 1. "EVE1_IRQ_2," line.long 0x0C "CTRL_CORE_EVE_IRQ_4_5," hexmask.long.byte 0x0C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x0C 16.--24. 1. "EVE1_IRQ_5," newline hexmask.long.byte 0x0C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--8. 1. "EVE1_IRQ_4," line.long 0x10 "CTRL_CORE_EVE_IRQ_6_7," hexmask.long.byte 0x10 25.--31. 1. "RESERVED," newline hexmask.long.word 0x10 16.--24. 1. "EVE1_IRQ_7," newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED," newline hexmask.long.word 0x10 0.--8. 1. "EVE1_IRQ_6," group.long 0x7E0++0x73 line.long 0x00 "CTRL_CORE_IPU_IRQ_23_24," hexmask.long.byte 0x00 25.--31. 1. "RESERVED," newline hexmask.long.word 0x00 16.--24. 1. "IPU1_IRQ_24," newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline hexmask.long.word 0x00 0.--8. 1. "IPU1_IRQ_23," line.long 0x04 "CTRL_CORE_IPU_IRQ_25_26," hexmask.long.byte 0x04 25.--31. 1. "RESERVED," newline hexmask.long.word 0x04 16.--24. 1. "IPU1_IRQ_26," newline hexmask.long.byte 0x04 9.--15. 1. "RESERVED," newline hexmask.long.word 0x04 0.--8. 1. "IPU1_IRQ_25," line.long 0x08 "CTRL_CORE_IPU_IRQ_27_28," hexmask.long.byte 0x08 25.--31. 1. "RESERVED," newline hexmask.long.word 0x08 16.--24. 1. "IPU1_IRQ_28," newline hexmask.long.byte 0x08 9.--15. 1. "RESERVED," newline hexmask.long.word 0x08 0.--8. 1. "IPU1_IRQ_27," line.long 0x0C "CTRL_CORE_IPU_IRQ_29_30," hexmask.long.byte 0x0C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x0C 16.--24. 1. "IPU1_IRQ_30," newline hexmask.long.byte 0x0C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--8. 1. "IPU1_IRQ_29," line.long 0x10 "CTRL_CORE_IPU_IRQ_31_32," hexmask.long.byte 0x10 25.--31. 1. "RESERVED," newline hexmask.long.word 0x10 16.--24. 1. "IPU1_IRQ_32," newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED," newline hexmask.long.word 0x10 0.--8. 1. "IPU1_IRQ_31," line.long 0x14 "CTRL_CORE_IPU_IRQ_33_34," hexmask.long.byte 0x14 25.--31. 1. "RESERVED," newline hexmask.long.word 0x14 16.--24. 1. "IPU1_IRQ_34," newline hexmask.long.byte 0x14 9.--15. 1. "RESERVED," newline hexmask.long.word 0x14 0.--8. 1. "IPU1_IRQ_33," line.long 0x18 "CTRL_CORE_IPU_IRQ_35_36," hexmask.long.byte 0x18 25.--31. 1. "RESERVED," newline hexmask.long.word 0x18 16.--24. 1. "IPU1_IRQ_36," newline hexmask.long.byte 0x18 9.--15. 1. "RESERVED," newline hexmask.long.word 0x18 0.--8. 1. "IPU1_IRQ_35," line.long 0x1C "CTRL_CORE_IPU_IRQ_37_38," hexmask.long.byte 0x1C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x1C 16.--24. 1. "IPU1_IRQ_38," newline hexmask.long.byte 0x1C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x1C 0.--8. 1. "IPU1_IRQ_37," line.long 0x20 "CTRL_CORE_IPU_IRQ_39_40," hexmask.long.byte 0x20 25.--31. 1. "RESERVED," newline hexmask.long.word 0x20 16.--24. 1. "IPU1_IRQ_40," newline hexmask.long.byte 0x20 9.--15. 1. "RESERVED," newline hexmask.long.word 0x20 0.--8. 1. "IPU1_IRQ_39," line.long 0x24 "CTRL_CORE_IPU_IRQ_41_42," hexmask.long.byte 0x24 25.--31. 1. "RESERVED," newline hexmask.long.word 0x24 16.--24. 1. "IPU1_IRQ_42," newline hexmask.long.byte 0x24 9.--15. 1. "RESERVED," newline hexmask.long.word 0x24 0.--8. 1. "IPU1_IRQ_41," line.long 0x28 "CTRL_CORE_IPU_IRQ_43_44," hexmask.long.byte 0x28 25.--31. 1. "RESERVED," newline hexmask.long.word 0x28 16.--24. 1. "IPU1_IRQ_44," newline hexmask.long.byte 0x28 9.--15. 1. "RESERVED," newline hexmask.long.word 0x28 0.--8. 1. "IPU1_IRQ_43," line.long 0x2C "CTRL_CORE_IPU_IRQ_45_46," hexmask.long.byte 0x2C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x2C 16.--24. 1. "IPU1_IRQ_46," newline hexmask.long.byte 0x2C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x2C 0.--8. 1. "IPU1_IRQ_45," line.long 0x30 "CTRL_CORE_IPU_IRQ_47_48," hexmask.long.byte 0x30 25.--31. 1. "RESERVED," newline hexmask.long.word 0x30 16.--24. 1. "IPU1_IRQ_48," newline hexmask.long.byte 0x30 9.--15. 1. "RESERVED," newline hexmask.long.word 0x30 0.--8. 1. "IPU1_IRQ_47," line.long 0x34 "CTRL_CORE_IPU_IRQ_49_50," hexmask.long.byte 0x34 25.--31. 1. "RESERVED," newline hexmask.long.word 0x34 16.--24. 1. "IPU1_IRQ_50," newline hexmask.long.byte 0x34 9.--15. 1. "RESERVED," newline hexmask.long.word 0x34 0.--8. 1. "IPU1_IRQ_49," line.long 0x38 "CTRL_CORE_IPU_IRQ_51_52," hexmask.long.byte 0x38 25.--31. 1. "RESERVED," newline hexmask.long.word 0x38 16.--24. 1. "IPU1_IRQ_52," newline hexmask.long.byte 0x38 9.--15. 1. "RESERVED," newline hexmask.long.word 0x38 0.--8. 1. "IPU1_IRQ_51," line.long 0x3C "CTRL_CORE_IPU_IRQ_53_54," hexmask.long.byte 0x3C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x3C 16.--24. 1. "IPU1_IRQ_54," newline hexmask.long.byte 0x3C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x3C 0.--8. 1. "IPU1_IRQ_53," line.long 0x40 "CTRL_CORE_IPU_IRQ_55_56," hexmask.long.byte 0x40 25.--31. 1. "RESERVED," newline hexmask.long.word 0x40 16.--24. 1. "IPU1_IRQ_56," newline hexmask.long.byte 0x40 9.--15. 1. "RESERVED," newline hexmask.long.word 0x40 0.--8. 1. "IPU1_IRQ_55," line.long 0x44 "CTRL_CORE_IPU_IRQ_57_58," hexmask.long.byte 0x44 25.--31. 1. "RESERVED," newline hexmask.long.word 0x44 16.--24. 1. "IPU1_IRQ_58," newline hexmask.long.byte 0x44 9.--15. 1. "RESERVED," newline hexmask.long.word 0x44 0.--8. 1. "IPU1_IRQ_57," line.long 0x48 "CTRL_CORE_IPU_IRQ_59_60," hexmask.long.byte 0x48 25.--31. 1. "RESERVED," newline hexmask.long.word 0x48 16.--24. 1. "IPU1_IRQ_60," newline hexmask.long.byte 0x48 9.--15. 1. "RESERVED," newline hexmask.long.word 0x48 0.--8. 1. "IPU1_IRQ_59," line.long 0x4C "CTRL_CORE_IPU_IRQ_61_62," hexmask.long.byte 0x4C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x4C 16.--24. 1. "IPU1_IRQ_62," newline hexmask.long.byte 0x4C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x4C 0.--8. 1. "IPU1_IRQ_61," line.long 0x50 "CTRL_CORE_IPU_IRQ_63_64," hexmask.long.byte 0x50 25.--31. 1. "RESERVED," newline hexmask.long.word 0x50 16.--24. 1. "IPU1_IRQ_64," newline hexmask.long.byte 0x50 9.--15. 1. "RESERVED," newline hexmask.long.word 0x50 0.--8. 1. "IPU1_IRQ_63," line.long 0x54 "CTRL_CORE_IPU_IRQ_65_66," hexmask.long.byte 0x54 25.--31. 1. "RESERVED," newline hexmask.long.word 0x54 16.--24. 1. "IPU1_IRQ_66," newline hexmask.long.byte 0x54 9.--15. 1. "RESERVED," newline hexmask.long.word 0x54 0.--8. 1. "IPU1_IRQ_65," line.long 0x58 "CTRL_CORE_IPU_IRQ_67_68," hexmask.long.byte 0x58 25.--31. 1. "RESERVED," newline hexmask.long.word 0x58 16.--24. 1. "IPU1_IRQ_68," newline hexmask.long.byte 0x58 9.--15. 1. "RESERVED," newline hexmask.long.word 0x58 0.--8. 1. "IPU1_IRQ_67," line.long 0x5C "CTRL_CORE_IPU_IRQ_69_70," hexmask.long.byte 0x5C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x5C 16.--24. 1. "IPU1_IRQ_70," newline hexmask.long.byte 0x5C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x5C 0.--8. 1. "IPU1_IRQ_69," line.long 0x60 "CTRL_CORE_IPU_IRQ_71_72," hexmask.long.byte 0x60 25.--31. 1. "RESERVED," newline hexmask.long.word 0x60 16.--24. 1. "IPU1_IRQ_72," newline hexmask.long.byte 0x60 9.--15. 1. "RESERVED," newline hexmask.long.word 0x60 0.--8. 1. "IPU1_IRQ_71," line.long 0x64 "CTRL_CORE_IPU_IRQ_73_74," hexmask.long.byte 0x64 25.--31. 1. "RESERVED," newline hexmask.long.word 0x64 16.--24. 1. "IPU1_IRQ_74," newline hexmask.long.byte 0x64 9.--15. 1. "RESERVED," newline hexmask.long.word 0x64 0.--8. 1. "IPU1_IRQ_73," line.long 0x68 "CTRL_CORE_IPU_IRQ_75_76," hexmask.long.byte 0x68 25.--31. 1. "RESERVED," newline hexmask.long.word 0x68 16.--24. 1. "IPU1_IRQ_76," newline hexmask.long.byte 0x68 9.--15. 1. "RESERVED," newline hexmask.long.word 0x68 0.--8. 1. "IPU1_IRQ_75," line.long 0x6C "CTRL_CORE_IPU_IRQ_77_78," hexmask.long.byte 0x6C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x6C 16.--24. 1. "IPU1_IRQ_78," newline hexmask.long.byte 0x6C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x6C 0.--8. 1. "IPU1_IRQ_77," line.long 0x70 "CTRL_CORE_IPU_IRQ_79_80," hexmask.long.tbyte 0x70 9.--31. 1. "RESERVED," newline hexmask.long.word 0x70 0.--8. 1. "IPU1_IRQ_79," group.long 0x948++0xFF line.long 0x00 "CTRL_CORE_DSP1_IRQ_32_33," hexmask.long.byte 0x00 25.--31. 1. "RESERVED," newline hexmask.long.word 0x00 16.--24. 1. "DSP1_IRQ_33," newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline hexmask.long.word 0x00 0.--8. 1. "DSP1_IRQ_32," line.long 0x04 "CTRL_CORE_DSP1_IRQ_34_35," hexmask.long.byte 0x04 25.--31. 1. "RESERVED," newline hexmask.long.word 0x04 16.--24. 1. "DSP1_IRQ_35," newline hexmask.long.byte 0x04 9.--15. 1. "RESERVED," newline hexmask.long.word 0x04 0.--8. 1. "DSP1_IRQ_34," line.long 0x08 "CTRL_CORE_DSP1_IRQ_36_37," hexmask.long.byte 0x08 25.--31. 1. "RESERVED," newline hexmask.long.word 0x08 16.--24. 1. "DSP1_IRQ_37," newline hexmask.long.byte 0x08 9.--15. 1. "RESERVED," newline hexmask.long.word 0x08 0.--8. 1. "DSP1_IRQ_36," line.long 0x0C "CTRL_CORE_DSP1_IRQ_38_39," hexmask.long.byte 0x0C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x0C 16.--24. 1. "DSP1_IRQ_39," newline hexmask.long.byte 0x0C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--8. 1. "DSP1_IRQ_38," line.long 0x10 "CTRL_CORE_DSP1_IRQ_40_41," hexmask.long.byte 0x10 25.--31. 1. "RESERVED," newline hexmask.long.word 0x10 16.--24. 1. "DSP1_IRQ_41," newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED," newline hexmask.long.word 0x10 0.--8. 1. "DSP1_IRQ_40," line.long 0x14 "CTRL_CORE_DSP1_IRQ_42_43," hexmask.long.byte 0x14 25.--31. 1. "RESERVED," newline hexmask.long.word 0x14 16.--24. 1. "DSP1_IRQ_43," newline hexmask.long.byte 0x14 9.--15. 1. "RESERVED," newline hexmask.long.word 0x14 0.--8. 1. "DSP1_IRQ_42," line.long 0x18 "CTRL_CORE_DSP1_IRQ_44_45," hexmask.long.byte 0x18 25.--31. 1. "RESERVED," newline hexmask.long.word 0x18 16.--24. 1. "DSP1_IRQ_45," newline hexmask.long.byte 0x18 9.--15. 1. "RESERVED," newline hexmask.long.word 0x18 0.--8. 1. "DSP1_IRQ_44," line.long 0x1C "CTRL_CORE_DSP1_IRQ_46_47," hexmask.long.byte 0x1C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x1C 16.--24. 1. "DSP1_IRQ_47," newline hexmask.long.byte 0x1C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x1C 0.--8. 1. "DSP1_IRQ_46," line.long 0x20 "CTRL_CORE_DSP1_IRQ_48_49," hexmask.long.byte 0x20 25.--31. 1. "RESERVED," newline hexmask.long.word 0x20 16.--24. 1. "DSP1_IRQ_49," newline hexmask.long.byte 0x20 9.--15. 1. "RESERVED," newline hexmask.long.word 0x20 0.--8. 1. "DSP1_IRQ_48," line.long 0x24 "CTRL_CORE_DSP1_IRQ_50_51," hexmask.long.byte 0x24 25.--31. 1. "RESERVED," newline hexmask.long.word 0x24 16.--24. 1. "DSP1_IRQ_51," newline hexmask.long.byte 0x24 9.--15. 1. "RESERVED," newline hexmask.long.word 0x24 0.--8. 1. "DSP1_IRQ_50," line.long 0x28 "CTRL_CORE_DSP1_IRQ_52_53," hexmask.long.byte 0x28 25.--31. 1. "RESERVED," newline hexmask.long.word 0x28 16.--24. 1. "DSP1_IRQ_53," newline hexmask.long.byte 0x28 9.--15. 1. "RESERVED," newline hexmask.long.word 0x28 0.--8. 1. "DSP1_IRQ_52," line.long 0x2C "CTRL_CORE_DSP1_IRQ_54_55," hexmask.long.byte 0x2C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x2C 16.--24. 1. "DSP1_IRQ_55," newline hexmask.long.byte 0x2C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x2C 0.--8. 1. "DSP1_IRQ_54," line.long 0x30 "CTRL_CORE_DSP1_IRQ_56_57," hexmask.long.byte 0x30 25.--31. 1. "RESERVED," newline hexmask.long.word 0x30 16.--24. 1. "DSP1_IRQ_57," newline hexmask.long.byte 0x30 9.--15. 1. "RESERVED," newline hexmask.long.word 0x30 0.--8. 1. "DSP1_IRQ_56," line.long 0x34 "CTRL_CORE_DSP1_IRQ_58_59," hexmask.long.byte 0x34 25.--31. 1. "RESERVED," newline hexmask.long.word 0x34 16.--24. 1. "DSP1_IRQ_59," newline hexmask.long.byte 0x34 9.--15. 1. "RESERVED," newline hexmask.long.word 0x34 0.--8. 1. "DSP1_IRQ_58," line.long 0x38 "CTRL_CORE_DSP1_IRQ_60_61," hexmask.long.byte 0x38 25.--31. 1. "RESERVED," newline hexmask.long.word 0x38 16.--24. 1. "DSP1_IRQ_61," newline hexmask.long.byte 0x38 9.--15. 1. "RESERVED," newline hexmask.long.word 0x38 0.--8. 1. "DSP1_IRQ_60," line.long 0x3C "CTRL_CORE_DSP1_IRQ_62_63," hexmask.long.byte 0x3C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x3C 16.--24. 1. "DSP1_IRQ_63," newline hexmask.long.byte 0x3C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x3C 0.--8. 1. "DSP1_IRQ_62," line.long 0x40 "CTRL_CORE_DSP1_IRQ_64_65," hexmask.long.byte 0x40 25.--31. 1. "RESERVED," newline hexmask.long.word 0x40 16.--24. 1. "DSP1_IRQ_65," newline hexmask.long.byte 0x40 9.--15. 1. "RESERVED," newline hexmask.long.word 0x40 0.--8. 1. "DSP1_IRQ_64," line.long 0x44 "CTRL_CORE_DSP1_IRQ_66_67," hexmask.long.byte 0x44 25.--31. 1. "RESERVED," newline hexmask.long.word 0x44 16.--24. 1. "DSP1_IRQ_67," newline hexmask.long.byte 0x44 9.--15. 1. "RESERVED," newline hexmask.long.word 0x44 0.--8. 1. "DSP1_IRQ_66," line.long 0x48 "CTRL_CORE_DSP1_IRQ_68_69," hexmask.long.byte 0x48 25.--31. 1. "RESERVED," newline hexmask.long.word 0x48 16.--24. 1. "DSP1_IRQ_69," newline hexmask.long.byte 0x48 9.--15. 1. "RESERVED," newline hexmask.long.word 0x48 0.--8. 1. "DSP1_IRQ_68," line.long 0x4C "CTRL_CORE_DSP1_IRQ_70_71," hexmask.long.byte 0x4C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x4C 16.--24. 1. "DSP1_IRQ_71," newline hexmask.long.byte 0x4C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x4C 0.--8. 1. "DSP1_IRQ_70," line.long 0x50 "CTRL_CORE_DSP1_IRQ_72_73," hexmask.long.byte 0x50 25.--31. 1. "RESERVED," newline hexmask.long.word 0x50 16.--24. 1. "DSP1_IRQ_73," newline hexmask.long.byte 0x50 9.--15. 1. "RESERVED," newline hexmask.long.word 0x50 0.--8. 1. "DSP1_IRQ_72," line.long 0x54 "CTRL_CORE_DSP1_IRQ_74_75," hexmask.long.byte 0x54 25.--31. 1. "RESERVED," newline hexmask.long.word 0x54 16.--24. 1. "DSP1_IRQ_75," newline hexmask.long.byte 0x54 9.--15. 1. "RESERVED," newline hexmask.long.word 0x54 0.--8. 1. "DSP1_IRQ_74," line.long 0x58 "CTRL_CORE_DSP1_IRQ_76_77," hexmask.long.byte 0x58 25.--31. 1. "RESERVED," newline hexmask.long.word 0x58 16.--24. 1. "DSP1_IRQ_77," newline hexmask.long.byte 0x58 9.--15. 1. "RESERVED," newline hexmask.long.word 0x58 0.--8. 1. "DSP1_IRQ_76," line.long 0x5C "CTRL_CORE_DSP1_IRQ_78_79," hexmask.long.byte 0x5C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x5C 16.--24. 1. "DSP1_IRQ_79," newline hexmask.long.byte 0x5C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x5C 0.--8. 1. "DSP1_IRQ_78," line.long 0x60 "CTRL_CORE_DSP1_IRQ_80_81," hexmask.long.byte 0x60 25.--31. 1. "RESERVED," newline hexmask.long.word 0x60 16.--24. 1. "DSP1_IRQ_81," newline hexmask.long.byte 0x60 9.--15. 1. "RESERVED," newline hexmask.long.word 0x60 0.--8. 1. "DSP1_IRQ_80," line.long 0x64 "CTRL_CORE_DSP1_IRQ_82_83," hexmask.long.byte 0x64 25.--31. 1. "RESERVED," newline hexmask.long.word 0x64 16.--24. 1. "DSP1_IRQ_83," newline hexmask.long.byte 0x64 9.--15. 1. "RESERVED," newline hexmask.long.word 0x64 0.--8. 1. "DSP1_IRQ_82," line.long 0x68 "CTRL_CORE_DSP1_IRQ_84_85," hexmask.long.byte 0x68 25.--31. 1. "RESERVED," newline hexmask.long.word 0x68 16.--24. 1. "DSP1_IRQ_85," newline hexmask.long.byte 0x68 9.--15. 1. "RESERVED," newline hexmask.long.word 0x68 0.--8. 1. "DSP1_IRQ_84," line.long 0x6C "CTRL_CORE_DSP1_IRQ_86_87," hexmask.long.byte 0x6C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x6C 16.--24. 1. "DSP1_IRQ_87," newline hexmask.long.byte 0x6C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x6C 0.--8. 1. "DSP1_IRQ_86," line.long 0x70 "CTRL_CORE_DSP1_IRQ_88_89," hexmask.long.byte 0x70 25.--31. 1. "RESERVED," newline hexmask.long.word 0x70 16.--24. 1. "DSP1_IRQ_89," newline hexmask.long.byte 0x70 9.--15. 1. "RESERVED," newline hexmask.long.word 0x70 0.--8. 1. "DSP1_IRQ_88," line.long 0x74 "CTRL_CORE_DSP1_IRQ_90_91," hexmask.long.byte 0x74 25.--31. 1. "RESERVED," newline hexmask.long.word 0x74 16.--24. 1. "DSP1_IRQ_91," newline hexmask.long.byte 0x74 9.--15. 1. "RESERVED," newline hexmask.long.word 0x74 0.--8. 1. "DSP1_IRQ_90," line.long 0x78 "CTRL_CORE_DSP1_IRQ_92_93," hexmask.long.byte 0x78 25.--31. 1. "RESERVED," newline hexmask.long.word 0x78 16.--24. 1. "DSP1_IRQ_93," newline hexmask.long.byte 0x78 9.--15. 1. "RESERVED," newline hexmask.long.word 0x78 0.--8. 1. "DSP1_IRQ_92," line.long 0x7C "CTRL_CORE_DSP1_IRQ_94_95," hexmask.long.byte 0x7C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x7C 16.--24. 1. "DSP1_IRQ_95," newline hexmask.long.byte 0x7C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x7C 0.--8. 1. "DSP1_IRQ_94," line.long 0x80 "CTRL_CORE_DSP2_IRQ_32_33," hexmask.long.byte 0x80 25.--31. 1. "RESERVED," newline hexmask.long.word 0x80 16.--24. 1. "DSP2_IRQ_33," newline hexmask.long.byte 0x80 9.--15. 1. "RESERVED," newline hexmask.long.word 0x80 0.--8. 1. "DSP2_IRQ_32," line.long 0x84 "CTRL_CORE_DSP2_IRQ_34_35," hexmask.long.byte 0x84 25.--31. 1. "RESERVED," newline hexmask.long.word 0x84 16.--24. 1. "DSP2_IRQ_35," newline hexmask.long.byte 0x84 9.--15. 1. "RESERVED," newline hexmask.long.word 0x84 0.--8. 1. "DSP2_IRQ_34," line.long 0x88 "CTRL_CORE_DSP2_IRQ_36_37," hexmask.long.byte 0x88 25.--31. 1. "RESERVED," newline hexmask.long.word 0x88 16.--24. 1. "DSP2_IRQ_37," newline hexmask.long.byte 0x88 9.--15. 1. "RESERVED," newline hexmask.long.word 0x88 0.--8. 1. "DSP2_IRQ_36," line.long 0x8C "CTRL_CORE_DSP2_IRQ_38_39," hexmask.long.byte 0x8C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x8C 16.--24. 1. "DSP2_IRQ_39," newline hexmask.long.byte 0x8C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x8C 0.--8. 1. "DSP2_IRQ_38," line.long 0x90 "CTRL_CORE_DSP2_IRQ_40_41," hexmask.long.byte 0x90 25.--31. 1. "RESERVED," newline hexmask.long.word 0x90 16.--24. 1. "DSP2_IRQ_41," newline hexmask.long.byte 0x90 9.--15. 1. "RESERVED," newline hexmask.long.word 0x90 0.--8. 1. "DSP2_IRQ_40," line.long 0x94 "CTRL_CORE_DSP2_IRQ_42_43," hexmask.long.byte 0x94 25.--31. 1. "RESERVED," newline hexmask.long.word 0x94 16.--24. 1. "DSP2_IRQ_43," newline hexmask.long.byte 0x94 9.--15. 1. "RESERVED," newline hexmask.long.word 0x94 0.--8. 1. "DSP2_IRQ_42," line.long 0x98 "CTRL_CORE_DSP2_IRQ_44_45," hexmask.long.byte 0x98 25.--31. 1. "RESERVED," newline hexmask.long.word 0x98 16.--24. 1. "DSP2_IRQ_45," newline hexmask.long.byte 0x98 9.--15. 1. "RESERVED," newline hexmask.long.word 0x98 0.--8. 1. "DSP2_IRQ_44," line.long 0x9C "CTRL_CORE_DSP2_IRQ_46_47," hexmask.long.byte 0x9C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x9C 16.--24. 1. "DSP2_IRQ_47," newline hexmask.long.byte 0x9C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x9C 0.--8. 1. "DSP2_IRQ_46," line.long 0xA0 "CTRL_CORE_DSP2_IRQ_48_49," hexmask.long.byte 0xA0 25.--31. 1. "RESERVED," newline hexmask.long.word 0xA0 16.--24. 1. "DSP2_IRQ_49," newline hexmask.long.byte 0xA0 9.--15. 1. "RESERVED," newline hexmask.long.word 0xA0 0.--8. 1. "DSP2_IRQ_48," line.long 0xA4 "CTRL_CORE_DSP2_IRQ_50_51," hexmask.long.byte 0xA4 25.--31. 1. "RESERVED," newline hexmask.long.word 0xA4 16.--24. 1. "DSP2_IRQ_51," newline hexmask.long.byte 0xA4 9.--15. 1. "RESERVED," newline hexmask.long.word 0xA4 0.--8. 1. "DSP2_IRQ_50," line.long 0xA8 "CTRL_CORE_DSP2_IRQ_52_53," hexmask.long.byte 0xA8 25.--31. 1. "RESERVED," newline hexmask.long.word 0xA8 16.--24. 1. "DSP2_IRQ_53," newline hexmask.long.byte 0xA8 9.--15. 1. "RESERVED," newline hexmask.long.word 0xA8 0.--8. 1. "DSP2_IRQ_52," line.long 0xAC "CTRL_CORE_DSP2_IRQ_54_55," hexmask.long.byte 0xAC 25.--31. 1. "RESERVED," newline hexmask.long.word 0xAC 16.--24. 1. "DSP2_IRQ_55," newline hexmask.long.byte 0xAC 9.--15. 1. "RESERVED," newline hexmask.long.word 0xAC 0.--8. 1. "DSP2_IRQ_54," line.long 0xB0 "CTRL_CORE_DSP2_IRQ_56_57," hexmask.long.byte 0xB0 25.--31. 1. "RESERVED," newline hexmask.long.word 0xB0 16.--24. 1. "DSP2_IRQ_57," newline hexmask.long.byte 0xB0 9.--15. 1. "RESERVED," newline hexmask.long.word 0xB0 0.--8. 1. "DSP2_IRQ_56," line.long 0xB4 "CTRL_CORE_DSP2_IRQ_58_59," hexmask.long.byte 0xB4 25.--31. 1. "RESERVED," newline hexmask.long.word 0xB4 16.--24. 1. "DSP2_IRQ_59," newline hexmask.long.byte 0xB4 9.--15. 1. "RESERVED," newline hexmask.long.word 0xB4 0.--8. 1. "DSP2_IRQ_58," line.long 0xB8 "CTRL_CORE_DSP2_IRQ_60_61," hexmask.long.byte 0xB8 25.--31. 1. "RESERVED," newline hexmask.long.word 0xB8 16.--24. 1. "DSP2_IRQ_61," newline hexmask.long.byte 0xB8 9.--15. 1. "RESERVED," newline hexmask.long.word 0xB8 0.--8. 1. "DSP2_IRQ_60," line.long 0xBC "CTRL_CORE_DSP2_IRQ_62_63," hexmask.long.byte 0xBC 25.--31. 1. "RESERVED," newline hexmask.long.word 0xBC 16.--24. 1. "DSP2_IRQ_63," newline hexmask.long.byte 0xBC 9.--15. 1. "RESERVED," newline hexmask.long.word 0xBC 0.--8. 1. "DSP2_IRQ_62," line.long 0xC0 "CTRL_CORE_DSP2_IRQ_64_65," hexmask.long.byte 0xC0 25.--31. 1. "RESERVED," newline hexmask.long.word 0xC0 16.--24. 1. "DSP2_IRQ_65," newline hexmask.long.byte 0xC0 9.--15. 1. "RESERVED," newline hexmask.long.word 0xC0 0.--8. 1. "DSP2_IRQ_64," line.long 0xC4 "CTRL_CORE_DSP2_IRQ_66_67," hexmask.long.byte 0xC4 25.--31. 1. "RESERVED," newline hexmask.long.word 0xC4 16.--24. 1. "DSP2_IRQ_67," newline hexmask.long.byte 0xC4 9.--15. 1. "RESERVED," newline hexmask.long.word 0xC4 0.--8. 1. "DSP2_IRQ_66," line.long 0xC8 "CTRL_CORE_DSP2_IRQ_68_69," hexmask.long.byte 0xC8 25.--31. 1. "RESERVED," newline hexmask.long.word 0xC8 16.--24. 1. "DSP2_IRQ_69," newline hexmask.long.byte 0xC8 9.--15. 1. "RESERVED," newline hexmask.long.word 0xC8 0.--8. 1. "DSP2_IRQ_68," line.long 0xCC "CTRL_CORE_DSP2_IRQ_70_71," hexmask.long.byte 0xCC 25.--31. 1. "RESERVED," newline hexmask.long.word 0xCC 16.--24. 1. "DSP2_IRQ_71," newline hexmask.long.byte 0xCC 9.--15. 1. "RESERVED," newline hexmask.long.word 0xCC 0.--8. 1. "DSP2_IRQ_70," line.long 0xD0 "CTRL_CORE_DSP2_IRQ_72_73," hexmask.long.byte 0xD0 25.--31. 1. "RESERVED," newline hexmask.long.word 0xD0 16.--24. 1. "DSP2_IRQ_73," newline hexmask.long.byte 0xD0 9.--15. 1. "RESERVED," newline hexmask.long.word 0xD0 0.--8. 1. "DSP2_IRQ_72," line.long 0xD4 "CTRL_CORE_DSP2_IRQ_74_75," hexmask.long.byte 0xD4 25.--31. 1. "RESERVED," newline hexmask.long.word 0xD4 16.--24. 1. "DSP2_IRQ_75," newline hexmask.long.byte 0xD4 9.--15. 1. "RESERVED," newline hexmask.long.word 0xD4 0.--8. 1. "DSP2_IRQ_74," line.long 0xD8 "CTRL_CORE_DSP2_IRQ_76_77," hexmask.long.byte 0xD8 25.--31. 1. "RESERVED," newline hexmask.long.word 0xD8 16.--24. 1. "DSP2_IRQ_77," newline hexmask.long.byte 0xD8 9.--15. 1. "RESERVED," newline hexmask.long.word 0xD8 0.--8. 1. "DSP2_IRQ_76," line.long 0xDC "CTRL_CORE_DSP2_IRQ_78_79," hexmask.long.byte 0xDC 25.--31. 1. "RESERVED," newline hexmask.long.word 0xDC 16.--24. 1. "DSP2_IRQ_79," newline hexmask.long.byte 0xDC 9.--15. 1. "RESERVED," newline hexmask.long.word 0xDC 0.--8. 1. "DSP2_IRQ_78," line.long 0xE0 "CTRL_CORE_DSP2_IRQ_80_81," hexmask.long.byte 0xE0 25.--31. 1. "RESERVED," newline hexmask.long.word 0xE0 16.--24. 1. "DSP2_IRQ_81," newline hexmask.long.byte 0xE0 9.--15. 1. "RESERVED," newline hexmask.long.word 0xE0 0.--8. 1. "DSP2_IRQ_80," line.long 0xE4 "CTRL_CORE_DSP2_IRQ_82_83," hexmask.long.byte 0xE4 25.--31. 1. "RESERVED," newline hexmask.long.word 0xE4 16.--24. 1. "DSP2_IRQ_83," newline hexmask.long.byte 0xE4 9.--15. 1. "RESERVED," newline hexmask.long.word 0xE4 0.--8. 1. "DSP2_IRQ_82," line.long 0xE8 "CTRL_CORE_DSP2_IRQ_84_85," hexmask.long.byte 0xE8 25.--31. 1. "RESERVED," newline hexmask.long.word 0xE8 16.--24. 1. "DSP2_IRQ_85," newline hexmask.long.byte 0xE8 9.--15. 1. "RESERVED," newline hexmask.long.word 0xE8 0.--8. 1. "DSP2_IRQ_84," line.long 0xEC "CTRL_CORE_DSP2_IRQ_86_87," hexmask.long.byte 0xEC 25.--31. 1. "RESERVED," newline hexmask.long.word 0xEC 16.--24. 1. "DSP2_IRQ_87," newline hexmask.long.byte 0xEC 9.--15. 1. "RESERVED," newline hexmask.long.word 0xEC 0.--8. 1. "DSP2_IRQ_86," line.long 0xF0 "CTRL_CORE_DSP2_IRQ_88_89," hexmask.long.byte 0xF0 25.--31. 1. "RESERVED," newline hexmask.long.word 0xF0 16.--24. 1. "DSP2_IRQ_89," newline hexmask.long.byte 0xF0 9.--15. 1. "RESERVED," newline hexmask.long.word 0xF0 0.--8. 1. "DSP2_IRQ_88," line.long 0xF4 "CTRL_CORE_DSP2_IRQ_90_91," hexmask.long.byte 0xF4 25.--31. 1. "RESERVED," newline hexmask.long.word 0xF4 16.--24. 1. "DSP2_IRQ_91," newline hexmask.long.byte 0xF4 9.--15. 1. "RESERVED," newline hexmask.long.word 0xF4 0.--8. 1. "DSP2_IRQ_90," line.long 0xF8 "CTRL_CORE_DSP2_IRQ_92_93," hexmask.long.byte 0xF8 25.--31. 1. "RESERVED," newline hexmask.long.word 0xF8 16.--24. 1. "DSP2_IRQ_93," newline hexmask.long.byte 0xF8 9.--15. 1. "RESERVED," newline hexmask.long.word 0xF8 0.--8. 1. "DSP2_IRQ_92," line.long 0xFC "CTRL_CORE_DSP2_IRQ_94_95," hexmask.long.byte 0xFC 25.--31. 1. "RESERVED," newline hexmask.long.word 0xFC 16.--24. 1. "DSP2_IRQ_95," newline hexmask.long.byte 0xFC 9.--15. 1. "RESERVED," newline hexmask.long.word 0xFC 0.--8. 1. "DSP2_IRQ_94," group.long 0xC78++0xCF line.long 0x00 "CTRL_CORE_DMA_EDMA_DREQ_0_1," hexmask.long.byte 0x00 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x00 16.--23. 1. "DMA_EDMA_DREQ_1_IRQ_1," newline hexmask.long.byte 0x00 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--7. 1. "DMA_EDMA_DREQ_0_IRQ_0," line.long 0x04 "CTRL_CORE_DMA_EDMA_DREQ_2_3," hexmask.long.byte 0x04 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x04 16.--23. 1. "DMA_EDMA_DREQ_3_IRQ_3," newline hexmask.long.byte 0x04 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x04 0.--7. 1. "DMA_EDMA_DREQ_2_IRQ_2," line.long 0x08 "CTRL_CORE_DMA_EDMA_DREQ_4_5," hexmask.long.byte 0x08 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x08 16.--23. 1. "DMA_EDMA_DREQ_5_IRQ_5," newline hexmask.long.byte 0x08 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x08 0.--7. 1. "DMA_EDMA_DREQ_4_IRQ_4," line.long 0x0C "CTRL_CORE_DMA_EDMA_DREQ_6_7," hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x0C 16.--23. 1. "DMA_EDMA_DREQ_7_IRQ_7," newline hexmask.long.byte 0x0C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x0C 0.--7. 1. "DMA_EDMA_DREQ_6_IRQ_6," line.long 0x10 "CTRL_CORE_DMA_EDMA_DREQ_8_9," hexmask.long.byte 0x10 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x10 16.--23. 1. "DMA_EDMA_DREQ_9_IRQ_9," newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x10 0.--7. 1. "DMA_EDMA_DREQ_8_IRQ_8," line.long 0x14 "CTRL_CORE_DMA_EDMA_DREQ_10_11," hexmask.long.byte 0x14 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 16.--23. 1. "DMA_EDMA_DREQ_11_IRQ_11," newline hexmask.long.byte 0x14 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--7. 1. "DMA_EDMA_DREQ_10_IRQ_10," line.long 0x18 "CTRL_CORE_DMA_EDMA_DREQ_12_13," hexmask.long.byte 0x18 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 16.--23. 1. "DMA_EDMA_DREQ_13_IRQ_13," newline hexmask.long.byte 0x18 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "DMA_EDMA_DREQ_12_IRQ_12," line.long 0x1C "CTRL_CORE_DMA_EDMA_DREQ_14_15," hexmask.long.byte 0x1C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x1C 16.--23. 1. "DMA_EDMA_DREQ_15_IRQ_15," newline hexmask.long.byte 0x1C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x1C 0.--7. 1. "DMA_EDMA_DREQ_14_IRQ_14," line.long 0x20 "CTRL_CORE_DMA_EDMA_DREQ_16_17," hexmask.long.byte 0x20 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x20 16.--23. 1. "DMA_EDMA_DREQ_17_IRQ_17," newline hexmask.long.byte 0x20 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x20 0.--7. 1. "DMA_EDMA_DREQ_16_IRQ_16," line.long 0x24 "CTRL_CORE_DMA_EDMA_DREQ_18_19," hexmask.long.byte 0x24 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x24 16.--23. 1. "DMA_EDMA_DREQ_19_IRQ_19," newline hexmask.long.byte 0x24 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x24 0.--7. 1. "DMA_EDMA_DREQ_18_IRQ_18," line.long 0x28 "CTRL_CORE_DMA_EDMA_DREQ_20_21," hexmask.long.byte 0x28 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x28 16.--23. 1. "DMA_EDMA_DREQ_21_IRQ_21," newline hexmask.long.byte 0x28 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x28 0.--7. 1. "DMA_EDMA_DREQ_20_IRQ_20," line.long 0x2C "CTRL_CORE_DMA_EDMA_DREQ_22_23," hexmask.long.byte 0x2C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x2C 16.--23. 1. "DMA_EDMA_DREQ_23_IRQ_23," newline hexmask.long.byte 0x2C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x2C 0.--7. 1. "DMA_EDMA_DREQ_22_IRQ_22," line.long 0x30 "CTRL_CORE_DMA_EDMA_DREQ_24_25," hexmask.long.byte 0x30 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x30 16.--23. 1. "DMA_EDMA_DREQ_25_IRQ_25," newline hexmask.long.byte 0x30 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x30 0.--7. 1. "DMA_EDMA_DREQ_24_IRQ_24," line.long 0x34 "CTRL_CORE_DMA_EDMA_DREQ_26_27," hexmask.long.byte 0x34 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x34 16.--23. 1. "DMA_EDMA_DREQ_27_IRQ_27," newline hexmask.long.byte 0x34 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x34 0.--7. 1. "DMA_EDMA_DREQ_26_IRQ_26," line.long 0x38 "CTRL_CORE_DMA_EDMA_DREQ_28_29," hexmask.long.byte 0x38 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x38 16.--23. 1. "DMA_EDMA_DREQ_29_IRQ_29," newline hexmask.long.byte 0x38 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x38 0.--7. 1. "DMA_EDMA_DREQ_28_IRQ_28," line.long 0x3C "CTRL_CORE_DMA_EDMA_DREQ_30_31," hexmask.long.byte 0x3C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x3C 16.--23. 1. "DMA_EDMA_DREQ_31_IRQ_31," newline hexmask.long.byte 0x3C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x3C 0.--7. 1. "DMA_EDMA_DREQ_30_IRQ_30," line.long 0x40 "CTRL_CORE_DMA_EDMA_DREQ_32_33," hexmask.long.byte 0x40 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x40 16.--23. 1. "DMA_EDMA_DREQ_33_IRQ_33," newline hexmask.long.byte 0x40 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x40 0.--7. 1. "DMA_EDMA_DREQ_32_IRQ_32," line.long 0x44 "CTRL_CORE_DMA_EDMA_DREQ_34_35," hexmask.long.byte 0x44 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x44 16.--23. 1. "DMA_EDMA_DREQ_35_IRQ_35," newline hexmask.long.byte 0x44 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x44 0.--7. 1. "DMA_EDMA_DREQ_34_IRQ_34," line.long 0x48 "CTRL_CORE_DMA_EDMA_DREQ_36_37," hexmask.long.byte 0x48 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x48 16.--23. 1. "DMA_EDMA_DREQ_37_IRQ_37," newline hexmask.long.byte 0x48 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x48 0.--7. 1. "DMA_EDMA_DREQ_36_IRQ_36," line.long 0x4C "CTRL_CORE_DMA_EDMA_DREQ_38_39," hexmask.long.byte 0x4C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x4C 16.--23. 1. "DMA_EDMA_DREQ_39_IRQ_39," newline hexmask.long.byte 0x4C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x4C 0.--7. 1. "DMA_EDMA_DREQ_38_IRQ_38," line.long 0x50 "CTRL_CORE_DMA_EDMA_DREQ_40_41," hexmask.long.byte 0x50 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x50 16.--23. 1. "DMA_EDMA_DREQ_41_IRQ_41," newline hexmask.long.byte 0x50 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x50 0.--7. 1. "DMA_EDMA_DREQ_40_IRQ_40," line.long 0x54 "CTRL_CORE_DMA_EDMA_DREQ_42_43," hexmask.long.byte 0x54 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x54 16.--23. 1. "DMA_EDMA_DREQ_43_IRQ_43," newline hexmask.long.byte 0x54 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x54 0.--7. 1. "DMA_EDMA_DREQ_42_IRQ_42," line.long 0x58 "CTRL_CORE_DMA_EDMA_DREQ_44_45," hexmask.long.byte 0x58 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x58 16.--23. 1. "DMA_EDMA_DREQ_45_IRQ_45," newline hexmask.long.byte 0x58 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x58 0.--7. 1. "DMA_EDMA_DREQ_44_IRQ_44," line.long 0x5C "CTRL_CORE_DMA_EDMA_DREQ_46_47," hexmask.long.byte 0x5C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x5C 16.--23. 1. "DMA_EDMA_DREQ_47_IRQ_47," newline hexmask.long.byte 0x5C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x5C 0.--7. 1. "DMA_EDMA_DREQ_46_IRQ_46," line.long 0x60 "CTRL_CORE_DMA_EDMA_DREQ_48_49," hexmask.long.byte 0x60 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x60 16.--23. 1. "DMA_EDMA_DREQ_49_IRQ_49," newline hexmask.long.byte 0x60 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x60 0.--7. 1. "DMA_EDMA_DREQ_48_IRQ_48," line.long 0x64 "CTRL_CORE_DMA_EDMA_DREQ_50_51," hexmask.long.byte 0x64 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x64 16.--23. 1. "DMA_EDMA_DREQ_51_IRQ_51," newline hexmask.long.byte 0x64 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x64 0.--7. 1. "DMA_EDMA_DREQ_50_IRQ_50," line.long 0x68 "CTRL_CORE_DMA_EDMA_DREQ_52_53," hexmask.long.byte 0x68 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x68 16.--23. 1. "DMA_EDMA_DREQ_53_IRQ_53," newline hexmask.long.byte 0x68 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x68 0.--7. 1. "DMA_EDMA_DREQ_52_IRQ_52," line.long 0x6C "CTRL_CORE_DMA_EDMA_DREQ_54_55," hexmask.long.byte 0x6C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x6C 16.--23. 1. "DMA_EDMA_DREQ_55_IRQ_55," newline hexmask.long.byte 0x6C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x6C 0.--7. 1. "DMA_EDMA_DREQ_54_IRQ_54," line.long 0x70 "CTRL_CORE_DMA_EDMA_DREQ_56_57," hexmask.long.byte 0x70 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x70 16.--23. 1. "DMA_EDMA_DREQ_57_IRQ_57," newline hexmask.long.byte 0x70 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x70 0.--7. 1. "DMA_EDMA_DREQ_56_IRQ_56," line.long 0x74 "CTRL_CORE_DMA_EDMA_DREQ_58_59," hexmask.long.byte 0x74 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x74 16.--23. 1. "DMA_EDMA_DREQ_59_IRQ_59," newline hexmask.long.byte 0x74 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x74 0.--7. 1. "DMA_EDMA_DREQ_58_IRQ_58," line.long 0x78 "CTRL_CORE_DMA_EDMA_DREQ_60_61," hexmask.long.byte 0x78 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x78 16.--23. 1. "DMA_EDMA_DREQ_61_IRQ_61," newline hexmask.long.byte 0x78 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x78 0.--7. 1. "DMA_EDMA_DREQ_60_IRQ_60," line.long 0x7C "CTRL_CORE_DMA_EDMA_DREQ_62_63," hexmask.long.byte 0x7C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x7C 16.--23. 1. "DMA_EDMA_DREQ_63_IRQ_63," newline hexmask.long.byte 0x7C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x7C 0.--7. 1. "DMA_EDMA_DREQ_62_IRQ_62," line.long 0x80 "CTRL_CORE_DMA_DSP1_DREQ_0_1," hexmask.long.byte 0x80 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x80 16.--23. 1. "DMA_DSP1_DREQ_1_IRQ_1," newline hexmask.long.byte 0x80 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x80 0.--7. 1. "DMA_DSP1_DREQ_0_IRQ_0," line.long 0x84 "CTRL_CORE_DMA_DSP1_DREQ_2_3," hexmask.long.byte 0x84 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x84 16.--23. 1. "DMA_DSP1_DREQ_3_IRQ_3," newline hexmask.long.byte 0x84 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x84 0.--7. 1. "DMA_DSP1_DREQ_2_IRQ_2," line.long 0x88 "CTRL_CORE_DMA_DSP1_DREQ_4_5," hexmask.long.byte 0x88 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x88 16.--23. 1. "DMA_DSP1_DREQ_5_IRQ_5," newline hexmask.long.byte 0x88 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x88 0.--7. 1. "DMA_DSP1_DREQ_4_IRQ_4," line.long 0x8C "CTRL_CORE_DMA_DSP1_DREQ_6_7," hexmask.long.byte 0x8C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x8C 16.--23. 1. "DMA_DSP1_DREQ_7_IRQ_7," newline hexmask.long.byte 0x8C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x8C 0.--7. 1. "DMA_DSP1_DREQ_6_IRQ_6," line.long 0x90 "CTRL_CORE_DMA_DSP1_DREQ_8_9," hexmask.long.byte 0x90 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x90 16.--23. 1. "DMA_DSP1_DREQ_9_IRQ_9," newline hexmask.long.byte 0x90 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x90 0.--7. 1. "DMA_DSP1_DREQ_8_IRQ_8," line.long 0x94 "CTRL_CORE_DMA_DSP1_DREQ_10_11," hexmask.long.byte 0x94 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x94 16.--23. 1. "DMA_DSP1_DREQ_11_IRQ_11," newline hexmask.long.byte 0x94 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x94 0.--7. 1. "DMA_DSP1_DREQ_10_IRQ_10," line.long 0x98 "CTRL_CORE_DMA_DSP1_DREQ_12_13," hexmask.long.byte 0x98 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x98 16.--23. 1. "DMA_DSP1_DREQ_13_IRQ_13," newline hexmask.long.byte 0x98 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x98 0.--7. 1. "DMA_DSP1_DREQ_12_IRQ_12," line.long 0x9C "CTRL_CORE_DMA_DSP1_DREQ_14_15," hexmask.long.byte 0x9C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x9C 16.--23. 1. "DMA_DSP1_DREQ_15_IRQ_15," newline hexmask.long.byte 0x9C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x9C 0.--7. 1. "DMA_DSP1_DREQ_14_IRQ_14," line.long 0xA0 "CTRL_CORE_DMA_DSP1_DREQ_16_17," hexmask.long.byte 0xA0 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xA0 16.--23. 1. "DMA_DSP1_DREQ_17_IRQ_17," newline hexmask.long.byte 0xA0 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xA0 0.--7. 1. "DMA_DSP1_DREQ_16_IRQ_16," line.long 0xA4 "CTRL_CORE_DMA_DSP1_DREQ_18_19," hexmask.long.byte 0xA4 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xA4 16.--23. 1. "DMA_DSP1_DREQ_19_IRQ_19," newline hexmask.long.byte 0xA4 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xA4 0.--7. 1. "DMA_DSP1_DREQ_18_IRQ_18," line.long 0xA8 "CTRL_CORE_DMA_DSP2_DREQ_0_1," hexmask.long.byte 0xA8 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xA8 16.--23. 1. "DMA_DSP2_DREQ_1_IRQ_1," newline hexmask.long.byte 0xA8 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xA8 0.--7. 1. "DMA_DSP2_DREQ_0_IRQ_0," line.long 0xAC "CTRL_CORE_DMA_DSP2_DREQ_2_3," hexmask.long.byte 0xAC 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xAC 16.--23. 1. "DMA_DSP2_DREQ_3_IRQ_3," newline hexmask.long.byte 0xAC 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xAC 0.--7. 1. "DMA_DSP2_DREQ_2_IRQ_2," line.long 0xB0 "CTRL_CORE_DMA_DSP2_DREQ_4_5," hexmask.long.byte 0xB0 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xB0 16.--23. 1. "DMA_DSP2_DREQ_5_IRQ_5," newline hexmask.long.byte 0xB0 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xB0 0.--7. 1. "DMA_DSP2_DREQ_4_IRQ_4," line.long 0xB4 "CTRL_CORE_DMA_DSP2_DREQ_6_7," hexmask.long.byte 0xB4 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xB4 16.--23. 1. "DMA_DSP2_DREQ_7_IRQ_7," newline hexmask.long.byte 0xB4 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xB4 0.--7. 1. "DMA_DSP2_DREQ_6_IRQ_6," line.long 0xB8 "CTRL_CORE_DMA_DSP2_DREQ_8_9," hexmask.long.byte 0xB8 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xB8 16.--23. 1. "DMA_DSP2_DREQ_9_IRQ_9," newline hexmask.long.byte 0xB8 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xB8 0.--7. 1. "DMA_DSP2_DREQ_8_IRQ_8," line.long 0xBC "CTRL_CORE_DMA_DSP2_DREQ_10_11," hexmask.long.byte 0xBC 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xBC 16.--23. 1. "DMA_DSP2_DREQ_11_IRQ_11," newline hexmask.long.byte 0xBC 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xBC 0.--7. 1. "DMA_DSP2_DREQ_10_IRQ_10," line.long 0xC0 "CTRL_CORE_DMA_DSP2_DREQ_12_13," hexmask.long.byte 0xC0 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xC0 16.--23. 1. "DMA_DSP2_DREQ_13_IRQ_13," newline hexmask.long.byte 0xC0 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xC0 0.--7. 1. "DMA_DSP2_DREQ_12_IRQ_12," line.long 0xC4 "CTRL_CORE_DMA_DSP2_DREQ_14_15," hexmask.long.byte 0xC4 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xC4 16.--23. 1. "DMA_DSP2_DREQ_15_IRQ_15," newline hexmask.long.byte 0xC4 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xC4 0.--7. 1. "DMA_DSP2_DREQ_14_IRQ_14," line.long 0xC8 "CTRL_CORE_DMA_DSP2_DREQ_16_17," hexmask.long.byte 0xC8 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xC8 16.--23. 1. "DMA_DSP2_DREQ_17_IRQ_17," newline hexmask.long.byte 0xC8 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xC8 0.--7. 1. "DMA_DSP2_DREQ_16_IRQ_16," line.long 0xCC "CTRL_CORE_DMA_DSP2_DREQ_18_19," hexmask.long.byte 0xCC 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xCC 16.--23. 1. "DMA_DSP2_DREQ_19_IRQ_19," newline hexmask.long.byte 0xCC 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xCC 0.--7. 1. "DMA_DSP2_DREQ_18_IRQ_18," group.long 0xD54++0x0F line.long 0x00 "CTRL_CORE_ESM_GROUP1_0," hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--8. 1. "ESM_GROUP1_0_IRQ_0," line.long 0x04 "CTRL_CORE_ESM_GROUP1_1," hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," newline hexmask.long.word 0x04 0.--8. 1. "ESM_GROUP1_1_IRQ_1," line.long 0x08 "CTRL_CORE_ESM_GROUP1_2," hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," newline hexmask.long.word 0x08 0.--8. 1. "ESM_GROUP1_2_IRQ_2," line.long 0x0C "CTRL_CORE_ESM_GROUP1_3," hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0C 0.--7. 1. "ESM_GROUP1_3_DMA_3," group.long 0xE30++0x03 line.long 0x00 "CTRL_CORE_CONTROL_DDRCACH1_0,ddrcaCH1 control" bitfld.long 0x00 29.--31. "DDRCH1_PART0_I,PART0 Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 26.--28. "DDRCH1_PART0_SR,PART0 Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 24.--25. "DDRCH1_PART0_WD,PART0 Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 21.--23. "DDRCH1_PART5A_I,PART5A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 18.--20. "DDRCH1_PART5A_SR,PART5A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 16.--17. "DDRCH1_PART5A_WD,PART5A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 13.--15. "DDRCH1_PART5B_I,PART5B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 10.--12. "DDRCH1_PART5B_SR,PART5B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 8.--9. "DDRCH1_PART5B_WD,PART5B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 5.--7. "DDRCH1_PART6_I,PART6 Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 2.--4. "DDRCH1_PART6_SR,PART6 Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 0.--1. "DDRCH1_PART6_WD,PART6 Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" group.long 0xE38++0x07 line.long 0x00 "CTRL_CORE_CONTROL_DDRCH1_0,DDRCH1 control 0" bitfld.long 0x00 29.--31. "DDRCH1_PART1A_I,PART1A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 26.--28. "DDRCH1_PART1A_SR,PART1A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 24.--25. "DDRCH1_PART1A_WD,PART1A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 21.--23. "DDRCH1_PART1B_I,PART1B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 18.--20. "DDRCH1_PART1B_SR,PART1B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 16.--17. "DDRCH1_PART1B_WD,PART1B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 13.--15. "DDRCH1_PART2A_I,PART2A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 10.--12. "DDRCH1_PART2A_SR,PART2A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 8.--9. "DDRCH1_PART2A_WD,PART2A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 5.--7. "DDRCH1_PART2B_I,PART2B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 2.--4. "DDRCH1_PART2B_SR,PART2B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 0.--1. "DDRCH1_PART2B_WD,PART2B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" line.long 0x04 "CTRL_CORE_CONTROL_DDRCH1_1,DDRCH1 control 1" bitfld.long 0x04 29.--31. "DDRCH1_PART3A_I,PART3A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x04 26.--28. "DDRCH1_PART3A_SR,PART3A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x04 24.--25. "DDRCH1_PART3A_WD,PART3A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x04 21.--23. "DDRCH1_PART3B_I,PART3B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x04 18.--20. "DDRCH1_PART3B_SR,PART3B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x04 16.--17. "DDRCH1_PART3B_WD,PART3B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x04 13.--15. "DDRCH1_PART4A_I,PART4A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x04 10.--12. "DDRCH1_PART4A_SR,PART4A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x04 8.--9. "DDRCH1_PART4A_WD,PART4A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x04 5.--7. "DDRCH1_PART4B_I,PART4B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x04 2.--4. "DDRCH1_PART4B_SR,PART4B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x04 0.--1. "DDRCH1_PART4B_WD,PART4B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" group.long 0xE48++0x03 line.long 0x00 "CTRL_CORE_CONTROL_DDRCH1_2," hexmask.long.byte 0x00 24.--31. 1. "RESERVED," newline bitfld.long 0x00 21.--23. "DDRCH1_PART7A_I,PART7A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 18.--20. "DDRCH1_PART7A_SR,PART7A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 16.--17. "DDRCH1_PART7A_WD,PART7A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 13.--15. "DDRCH1_PART7B_I,PART7B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 10.--12. "DDRCH1_PART7B_SR,PART7B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 8.--9. "DDRCH1_PART7B_WD,PART7B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0xE50++0x03 line.long 0x00 "CTRL_CORE_CONTROL_DDRIO_0," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline bitfld.long 0x00 19. "DDRCH1_VREF_DQ0_INT_CCAP0,Selection for coupling cap connection" "DDRCH1_VREF_DQ0_INT_CCAP0_0,DDRCH1_VREF_DQ0_INT_CCAP0_1" newline bitfld.long 0x00 18. "DDRCH1_VREF_DQ0_INT_CCAP1,Selection for coupling cap connection" "DDRCH1_VREF_DQ0_INT_CCAP1_0,DDRCH1_VREF_DQ0_INT_CCAP1_1" newline bitfld.long 0x00 17. "DDRCH1_VREF_DQ0_INT_TAP0,Selection for internal reference voltage drive" "DDRCH1_VREF_DQ0_INT_TAP0_0,DDRCH1_VREF_DQ0_INT_TAP0_1" newline bitfld.long 0x00 16. "DDRCH1_VREF_DQ0_INT_TAP1,Selection for internal reference voltage drive" "DDRCH1_VREF_DQ0_INT_TAP1_0,DDRCH1_VREF_DQ0_INT_TAP1_1" newline bitfld.long 0x00 15. "DDRCH1_VREF_DQ0_INT_EN,Enable" "DDRCH1_VREF_DQ0_INT_EN_0,DDRCH1_VREF_DQ0_INT_EN_1" newline bitfld.long 0x00 14. "DDRCH1_VREF_DQ1_INT_CCAP0,Selection for coupling cap connection" "DDRCH1_VREF_DQ1_INT_CCAP0_0,DDRCH1_VREF_DQ1_INT_CCAP0_1" newline bitfld.long 0x00 13. "DDRCH1_VREF_DQ1_INT_CCAP1,Selection for coupling cap connection" "DDRCH1_VREF_DQ1_INT_CCAP1_0,DDRCH1_VREF_DQ1_INT_CCAP1_1" newline bitfld.long 0x00 12. "DDRCH1_VREF_DQ1_INT_TAP0,Selection for internal reference voltage drive" "DDRCH1_VREF_DQ1_INT_TAP0_0,DDRCH1_VREF_DQ1_INT_TAP0_1" newline bitfld.long 0x00 11. "DDRCH1_VREF_DQ1_INT_TAP1,Selection for internal reference voltage drive" "DDRCH1_VREF_DQ1_INT_TAP1_0,DDRCH1_VREF_DQ1_INT_TAP1_1" newline bitfld.long 0x00 10. "DDRCH1_VREF_DQ1_INT_EN,Enable" "DDRCH1_VREF_DQ1_INT_EN_0,DDRCH1_VREF_DQ1_INT_EN_1" newline hexmask.long.word 0x00 0.--9. 1. "RESERVED," group.long 0x1000++0x03 line.long 0x00 "CTRL_CORE_HWOBS_FINAL_MUX_SEL,This register controls the final multiplexor which selects whether CORE or WKUP observable signals are mapped to the final observability bus. that is obs[31:0] bus" group.long 0x100C++0xBF line.long 0x00 "CTRL_CORE_CONF_DEBUG_SEL_TST_0,This register is used to select an observable signal for CORE observability line 0" hexmask.long 0x00 6.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 0" "?,?,?,?,?,?,?,MODE_7,?,?,?,MODE_11,?,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "CTRL_CORE_CONF_DEBUG_SEL_TST_1,This register is used to select an observable signal for CORE observability line 1" hexmask.long 0x04 6.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 1" "?,?,?,?,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x08 "CTRL_CORE_CONF_DEBUG_SEL_TST_2,This register is used to select an observable signal for CORE observability line 2" hexmask.long 0x08 6.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 2" "?,?,?,?,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x0C "CTRL_CORE_CONF_DEBUG_SEL_TST_3,This register is used to select an observable signal for CORE observability line 3" hexmask.long 0x0C 6.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 3" "?,MODE_1,?,MODE_3,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x10 "CTRL_CORE_CONF_DEBUG_SEL_TST_4,This register is used to select an observable signal for CORE observability line 4" hexmask.long 0x10 6.--31. 1. "RESERVED," newline bitfld.long 0x10 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 4" "?,MODE_1,?,MODE_3,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "CTRL_CORE_CONF_DEBUG_SEL_TST_5,This register is used to select an observable signal for CORE observability line 5" hexmask.long 0x14 6.--31. 1. "RESERVED," newline bitfld.long 0x14 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 5" "?,MODE_1,?,MODE_3,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x18 "CTRL_CORE_CONF_DEBUG_SEL_TST_6,This register is used to select an observable signal for CORE observability line 6" hexmask.long 0x18 6.--31. 1. "RESERVED," newline bitfld.long 0x18 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 6" "?,MODE_1,?,MODE_3,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x1C "CTRL_CORE_CONF_DEBUG_SEL_TST_7,This register is used to select an observable signal for CORE observability line 7" hexmask.long 0x1C 6.--31. 1. "RESERVED," newline bitfld.long 0x1C 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 7" "?,MODE_1,?,MODE_3,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x20 "CTRL_CORE_CONF_DEBUG_SEL_TST_8,This register is used to select an observable signal for CORE observability line 8" hexmask.long 0x20 6.--31. 1. "RESERVED," newline bitfld.long 0x20 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 8" "?,MODE_1,?,MODE_3,?,?,?,MODE_7,?,?,?,MODE_11,MODE_12,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x24 "CTRL_CORE_CONF_DEBUG_SEL_TST_9,This register is used to select an observable signal for CORE observability line 9" hexmask.long 0x24 6.--31. 1. "RESERVED," newline bitfld.long 0x24 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 9" "?,MODE_1,?,MODE_3,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x28 "CTRL_CORE_CONF_DEBUG_SEL_TST_10,This register is used to select an observable signal for CORE observability line 10" hexmask.long 0x28 6.--31. 1. "RESERVED," newline bitfld.long 0x28 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 10" "?,MODE_1,?,?,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x2C "CTRL_CORE_CONF_DEBUG_SEL_TST_11,This register is used to select an observable signal for CORE observability line 11" hexmask.long 0x2C 6.--31. 1. "RESERVED," newline bitfld.long 0x2C 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 11" "?,MODE_1,?,?,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x30 "CTRL_CORE_CONF_DEBUG_SEL_TST_12,This register is used to select an observable signal for CORE observability line 12" hexmask.long 0x30 6.--31. 1. "RESERVED," newline bitfld.long 0x30 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 12" "?,MODE_1,MODE_2,?,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,?,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x34 "CTRL_CORE_CONF_DEBUG_SEL_TST_13,This register is used to select an observable signal for CORE observability line 13" hexmask.long 0x34 6.--31. 1. "RESERVED," newline bitfld.long 0x34 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 13" "?,MODE_1,MODE_2,?,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,?,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x38 "CTRL_CORE_CONF_DEBUG_SEL_TST_14,This register is used to select an observable signal for CORE observability line 14" hexmask.long 0x38 6.--31. 1. "RESERVED," newline bitfld.long 0x38 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 14" "?,MODE_1,?,?,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,?,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x3C "CTRL_CORE_CONF_DEBUG_SEL_TST_15,This register is used to select an observable signal for CORE observability line 15" hexmask.long 0x3C 6.--31. 1. "RESERVED," newline bitfld.long 0x3C 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 15" "?,MODE_1,?,?,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,?,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x40 "CTRL_CORE_CONF_DEBUG_SEL_TST_16,This register is used to select an observable signal for CORE observability line 16" hexmask.long 0x40 6.--31. 1. "RESERVED," newline bitfld.long 0x40 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 16" "?,MODE_1,?,?,?,?,?,MODE_7,?,?,?,MODE_11,MODE_12,?,?,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x44 "CTRL_CORE_CONF_DEBUG_SEL_TST_17,This register is used to select an observable signal for CORE observability line 17" hexmask.long 0x44 6.--31. 1. "RESERVED," newline bitfld.long 0x44 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 17" "?,MODE_1,?,?,?,?,?,MODE_7,?,?,?,MODE_11,MODE_12,?,?,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x48 "CTRL_CORE_CONF_DEBUG_SEL_TST_18,This register is used to select an observable signal for CORE observability line 18" hexmask.long 0x48 6.--31. 1. "RESERVED," newline bitfld.long 0x48 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 18" "?,MODE_1,?,?,?,?,?,MODE_7,?,?,?,MODE_11,MODE_12,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x4C "CTRL_CORE_CONF_DEBUG_SEL_TST_19,This register is used to select an observable signal for CORE observability line 19" hexmask.long 0x4C 6.--31. 1. "RESERVED," newline bitfld.long 0x4C 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 19" "?,MODE_1,MODE_2,?,?,?,?,MODE_7,?,?,?,MODE_11,MODE_12,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x50 "CTRL_CORE_CONF_DEBUG_SEL_TST_20,This register is used to select an observable signal for CORE observability line 20" hexmask.long 0x50 6.--31. 1. "RESERVED," newline bitfld.long 0x50 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 20" "?,MODE_1,MODE_2,?,?,?,?,MODE_7,?,?,?,MODE_11,MODE_12,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x54 "CTRL_CORE_CONF_DEBUG_SEL_TST_21,This register is used to select an observable signal for CORE observability line 21" hexmask.long 0x54 6.--31. 1. "RESERVED," newline bitfld.long 0x54 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 21" "?,?,MODE_2,?,?,?,?,MODE_7,?,?,?,MODE_11,MODE_12,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x58 "CTRL_CORE_CONF_DEBUG_SEL_TST_22,This register is used to select an observable signal for CORE observability line 22" hexmask.long 0x58 6.--31. 1. "RESERVED," newline bitfld.long 0x58 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 22" "?,?,MODE_2,?,?,?,?,MODE_7,?,?,?,MODE_11,MODE_12,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,?,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x5C "CTRL_CORE_CONF_DEBUG_SEL_TST_23,This register is used to select an observable signal for CORE observability line 23" hexmask.long 0x5C 6.--31. 1. "RESERVED," newline bitfld.long 0x5C 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 23" "?,?,MODE_2,?,?,?,?,MODE_7,?,?,?,MODE_11,?,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,?,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x60 "CTRL_CORE_CONF_DEBUG_SEL_TST_24,This register is used to select an observable signal for CORE observability line 24" hexmask.long 0x60 6.--31. 1. "RESERVED," newline bitfld.long 0x60 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 24" "?,?,MODE_2,?,?,?,?,MODE_7,?,?,?,MODE_11,?,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,?,?,?,?,?,?,?,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x64 "CTRL_CORE_CONF_DEBUG_SEL_TST_25,This register is used to select an observable signal for CORE observability line 25" hexmask.long 0x64 6.--31. 1. "RESERVED," newline bitfld.long 0x64 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 25" "?,?,MODE_2,?,?,?,?,MODE_7,?,?,?,MODE_11,?,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,?,?,?,?,?,?,?,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,?,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x68 "CTRL_CORE_CONF_DEBUG_SEL_TST_26,This register is used to select an observable signal for CORE observability line 26" hexmask.long 0x68 6.--31. 1. "RESERVED," newline bitfld.long 0x68 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 26" "?,?,?,?,?,?,?,MODE_7,?,?,?,?,?,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,?,?,?,?,?,?,?,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,?,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x6C "CTRL_CORE_CONF_DEBUG_SEL_TST_27,This register is used to select an observable signal for CORE observability line 27" hexmask.long 0x6C 6.--31. 1. "RESERVED," newline bitfld.long 0x6C 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 27" "?,?,?,?,?,?,?,MODE_7,?,?,?,?,?,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,?,?,?,?,?,?,?,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,?,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x70 "CTRL_CORE_CONF_DEBUG_SEL_TST_28,This register is used to select an observable signal for CORE observability line 28" hexmask.long 0x70 6.--31. 1. "RESERVED," newline bitfld.long 0x70 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 28" "?,?,?,?,?,?,?,MODE_7,?,?,?,?,?,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,?,?,?,?,?,?,?,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,?,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x74 "CTRL_CORE_CONF_DEBUG_SEL_TST_29,This register is used to select an observable signal for CORE observability line 29" hexmask.long 0x74 6.--31. 1. "RESERVED," newline bitfld.long 0x74 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 29" "?,?,?,?,?,?,?,MODE_7,?,?,?,?,?,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,?,?,?,?,?,?,?,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,?,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x78 "CTRL_CORE_CONF_DEBUG_SEL_TST_30,This register is used to select an observable signal for CORE observability line 30" hexmask.long 0x78 6.--31. 1. "RESERVED," newline bitfld.long 0x78 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 30" "?,?,MODE_2,?,?,?,?,MODE_7,?,?,?,?,?,?,?,?,?,?,MODE_18,?,?,?,MODE_22,MODE_23,?,?,?,?,?,?,?,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,?,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x7C "CTRL_CORE_CONF_DEBUG_SEL_TST_31,This register is used to select an observable signal for CORE observability line 31" hexmask.long 0x7C 6.--31. 1. "RESERVED," newline bitfld.long 0x7C 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 31" "?,?,?,?,?,?,?,MODE_7,?,?,?,?,?,?,?,?,?,?,MODE_18,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,?,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x80 "CTRL_CORE_CONF_DEBUG_SEL_TST_32,This register is used to select a signal for observation using line 0 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0x80 3.--31. 1. "RESERVED," newline bitfld.long 0x80 0.--2. "MODE,Selects one of the following signals to be available on line 0 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0x84 "CTRL_CORE_CONF_DEBUG_SEL_TST_33,This register is used to select a signal for observation using line 1 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0x84 3.--31. 1. "RESERVED," newline bitfld.long 0x84 0.--2. "MODE,Selects one of the following signals to be available on line 1 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0x88 "CTRL_CORE_CONF_DEBUG_SEL_TST_34,This register is used to select a signal for observation using line 2 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0x88 3.--31. 1. "RESERVED," newline bitfld.long 0x88 0.--2. "MODE,Selects one of the following signals to be available on line 2 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0x8C "CTRL_CORE_CONF_DEBUG_SEL_TST_35,This register is used to select a signal for observation using line 3 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0x8C 3.--31. 1. "RESERVED," newline bitfld.long 0x8C 0.--2. "MODE,Selects one of the following signals to be available on line 3 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0x90 "CTRL_CORE_CONF_DEBUG_SEL_TST_36,This register is used to select a signal for observation using line 4 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0x90 3.--31. 1. "RESERVED," newline bitfld.long 0x90 0.--2. "MODE,Selects one of the following signals to be available on line 4 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0x94 "CTRL_CORE_CONF_DEBUG_SEL_TST_37,This register is used to select a signal for observation using line 5 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0x94 3.--31. 1. "RESERVED," newline bitfld.long 0x94 0.--2. "MODE,Selects one of the following signals to be available on line 5 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0x98 "CTRL_CORE_CONF_DEBUG_SEL_TST_38,This register is used to select a signal for observation using line 6 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0x98 3.--31. 1. "RESERVED," newline bitfld.long 0x98 0.--2. "MODE,Selects one of the following signals to be available on line 6 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0x9C "CTRL_CORE_CONF_DEBUG_SEL_TST_39,This register is used to select a signal for observation using line 7 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0x9C 3.--31. 1. "RESERVED," newline bitfld.long 0x9C 0.--2. "MODE,Selects one of the following signals to be available on line 7 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0xA0 "CTRL_CORE_CONF_DEBUG_SEL_TST_40,This register is used to select a signal for observation using line 8 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0xA0 3.--31. 1. "RESERVED," newline bitfld.long 0xA0 0.--2. "MODE,Selects one of the following signals to be available on line 8 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0xA4 "CTRL_CORE_CONF_DEBUG_SEL_TST_41,This register is used to select a signal for observation using line 9 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0xA4 3.--31. 1. "RESERVED," newline bitfld.long 0xA4 0.--2. "MODE,Selects one of the following signals to be available on line 9 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0xA8 "CTRL_CORE_CONF_DEBUG_SEL_TST_42,This register is used to select a signal for observation using line 10 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0xA8 3.--31. 1. "RESERVED," newline bitfld.long 0xA8 0.--2. "MODE,Selects one of the following signals to be available on line 10 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0xAC "CTRL_CORE_CONF_DEBUG_SEL_TST_43,This register is used to select a signal for observation using line 11 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0xAC 3.--31. 1. "RESERVED," newline bitfld.long 0xAC 0.--2. "MODE,Selects one of the following signals to be available on line 11 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0xB0 "CTRL_CORE_CONF_DEBUG_SEL_TST_44,This register is used to select a signal for observation using line 12 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0xB0 3.--31. 1. "RESERVED," newline bitfld.long 0xB0 0.--2. "MODE,Selects one of the following signals to be available on line 12 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0xB4 "CTRL_CORE_CONF_DEBUG_SEL_TST_45,This register is used to select a signal for observation using line 13 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0xB4 3.--31. 1. "RESERVED," newline bitfld.long 0xB4 0.--2. "MODE,Selects one of the following signals to be available on line 13 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0xB8 "CTRL_CORE_CONF_DEBUG_SEL_TST_46,This register is used to select a signal for observation using line 14 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0xB8 3.--31. 1. "RESERVED," newline bitfld.long 0xB8 0.--2. "MODE,Selects one of the following signals to be available on line 14 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0xBC "CTRL_CORE_CONF_DEBUG_SEL_TST_47,This register is used to select a signal for observation using line 15 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0xBC 3.--31. 1. "RESERVED," newline bitfld.long 0xBC 0.--2. "MODE,Selects one of the following signals to be available on line 15 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" group.long 0x1400++0x14F line.long 0x00 "CTRL_CORE_PAD_GPMC_CLK," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline bitfld.long 0x00 19. "GPMC_CLK_SLEWCONTROL," "GPMC_CLK_SLEWCONTROL_0,GPMC_CLK_SLEWCONTROL_1" newline bitfld.long 0x00 18. "GPMC_CLK_INPUTENABLE," "GPMC_CLK_INPUTENABLE_0,GPMC_CLK_INPUTENABLE_1" newline bitfld.long 0x00 17. "GPMC_CLK_PULLTYPESELECT," "GPMC_CLK_PULLTYPESELECT_0,GPMC_CLK_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "GPMC_CLK_PULLUDENABLE," "GPMC_CLK_PULLUDENABLE_0,GPMC_CLK_PULLUDENABLE_1" newline hexmask.long.word 0x00 4.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "GPMC_CLK_MUXMODE," "GPMC_CLK_MUXMODE_0,GPMC_CLK_MUXMODE_1,?,?,?,GPMC_CLK_MUXMODE_5,GPMC_CLK_MUXMODE_6,?,?,?,?,?,?,?,GPMC_CLK_MUXMODE_14,GPMC_CLK_MUXMODE_15" line.long 0x04 "CTRL_CORE_PAD_GPMC_BEN0," hexmask.long.word 0x04 20.--31. 1. "RESERVED," newline bitfld.long 0x04 19. "GPMC_BEN0_SLEWCONTROL," "GPMC_BEN0_SLEWCONTROL_0,GPMC_BEN0_SLEWCONTROL_1" newline bitfld.long 0x04 18. "GPMC_BEN0_INPUTENABLE," "GPMC_BEN0_INPUTENABLE_0,GPMC_BEN0_INPUTENABLE_1" newline bitfld.long 0x04 17. "GPMC_BEN0_PULLTYPESELECT," "GPMC_BEN0_PULLTYPESELECT_0,GPMC_BEN0_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "GPMC_BEN0_PULLUDENABLE," "GPMC_BEN0_PULLUDENABLE_0,GPMC_BEN0_PULLUDENABLE_1" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 0.--3. "GPMC_BEN0_MUXMODE," "GPMC_BEN0_MUXMODE_0,GPMC_BEN0_MUXMODE_1,?,?,GPMC_BEN0_MUXMODE_4,?,GPMC_BEN0_MUXMODE_6,?,?,?,?,?,?,?,GPMC_BEN0_MUXMODE_14,GPMC_BEN0_MUXMODE_15" line.long 0x08 "CTRL_CORE_PAD_GPMC_BEN1," hexmask.long.word 0x08 20.--31. 1. "RESERVED," newline bitfld.long 0x08 19. "GPMC_BEN1_SLEWCONTROL," "GPMC_BEN1_SLEWCONTROL_0,GPMC_BEN1_SLEWCONTROL_1" newline bitfld.long 0x08 18. "GPMC_BEN1_INPUTENABLE," "GPMC_BEN1_INPUTENABLE_0,GPMC_BEN1_INPUTENABLE_1" newline bitfld.long 0x08 17. "GPMC_BEN1_PULLTYPESELECT," "GPMC_BEN1_PULLTYPESELECT_0,GPMC_BEN1_PULLTYPESELECT_1" newline bitfld.long 0x08 16. "GPMC_BEN1_PULLUDENABLE," "GPMC_BEN1_PULLUDENABLE_0,GPMC_BEN1_PULLUDENABLE_1" newline hexmask.long.word 0x08 4.--15. 1. "RESERVED," newline bitfld.long 0x08 0.--3. "GPMC_BEN1_MUXMODE," "GPMC_BEN1_MUXMODE_0,GPMC_BEN1_MUXMODE_1,?,?,GPMC_BEN1_MUXMODE_4,?,GPMC_BEN1_MUXMODE_6,?,?,?,?,?,?,?,GPMC_BEN1_MUXMODE_14,GPMC_BEN1_MUXMODE_15" line.long 0x0C "CTRL_CORE_PAD_GPMC_ADVN_ALE," hexmask.long.word 0x0C 20.--31. 1. "RESERVED," newline bitfld.long 0x0C 19. "GPMC_ADVN_ALE_SLEWCONTROL," "GPMC_ADVN_ALE_SLEWCONTROL_0,GPMC_ADVN_ALE_SLEWCONTROL_1" newline bitfld.long 0x0C 18. "GPMC_ADVN_ALE_INPUTENABLE," "GPMC_ADVN_ALE_INPUTENABLE_0,GPMC_ADVN_ALE_INPUTENABLE_1" newline bitfld.long 0x0C 17. "GPMC_ADVN_ALE_PULLTYPESELECT," "GPMC_ADVN_ALE_PULLTYPESELECT_0,GPMC_ADVN_ALE_PULLTYPESELECT_1" newline bitfld.long 0x0C 16. "GPMC_ADVN_ALE_PULLUDENABLE," "GPMC_ADVN_ALE_PULLUDENABLE_0,GPMC_ADVN_ALE_PULLUDENABLE_1" newline hexmask.long.word 0x0C 4.--15. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "GPMC_ADVN_ALE_MUXMODE," "GPMC_ADVN_ALE_MUXMODE_0,GPMC_ADVN_ALE_MUXMODE_1,?,?,GPMC_ADVN_ALE_MUXMODE_4,GPMC_ADVN_ALE_MUXMODE_5,GPMC_ADVN_ALE_MUXMODE_6,?,?,?,?,?,?,?,GPMC_ADVN_ALE_MUXMODE_14,GPMC_ADVN_ALE_MUXMODE_15" line.long 0x10 "CTRL_CORE_PAD_GPMC_OEN_REN," hexmask.long.word 0x10 20.--31. 1. "RESERVED," newline bitfld.long 0x10 19. "GPMC_OEN_REN_SLEWCONTROL," "GPMC_OEN_REN_SLEWCONTROL_0,GPMC_OEN_REN_SLEWCONTROL_1" newline bitfld.long 0x10 18. "GPMC_OEN_REN_INPUTENABLE," "GPMC_OEN_REN_INPUTENABLE_0,GPMC_OEN_REN_INPUTENABLE_1" newline bitfld.long 0x10 17. "GPMC_OEN_REN_PULLTYPESELECT," "GPMC_OEN_REN_PULLTYPESELECT_0,GPMC_OEN_REN_PULLTYPESELECT_1" newline bitfld.long 0x10 16. "GPMC_OEN_REN_PULLUDENABLE," "GPMC_OEN_REN_PULLUDENABLE_0,GPMC_OEN_REN_PULLUDENABLE_1" newline hexmask.long.word 0x10 4.--15. 1. "RESERVED," newline bitfld.long 0x10 0.--3. "GPMC_OEN_REN_MUXMODE," "GPMC_OEN_REN_MUXMODE_0,GPMC_OEN_REN_MUXMODE_1,?,?,GPMC_OEN_REN_MUXMODE_4,GPMC_OEN_REN_MUXMODE_5,?,?,?,?,?,?,?,?,GPMC_OEN_REN_MUXMODE_14,GPMC_OEN_REN_MUXMODE_15" line.long 0x14 "CTRL_CORE_PAD_GPMC_WEN," hexmask.long.word 0x14 20.--31. 1. "RESERVED," newline bitfld.long 0x14 19. "GPMC_WEN_SLEWCONTROL," "GPMC_WEN_SLEWCONTROL_0,GPMC_WEN_SLEWCONTROL_1" newline bitfld.long 0x14 18. "GPMC_WEN_INPUTENABLE," "GPMC_WEN_INPUTENABLE_0,GPMC_WEN_INPUTENABLE_1" newline bitfld.long 0x14 17. "GPMC_WEN_PULLTYPESELECT," "GPMC_WEN_PULLTYPESELECT_0,GPMC_WEN_PULLTYPESELECT_1" newline bitfld.long 0x14 16. "GPMC_WEN_PULLUDENABLE," "GPMC_WEN_PULLUDENABLE_0,GPMC_WEN_PULLUDENABLE_1" newline hexmask.long.word 0x14 4.--15. 1. "RESERVED," newline bitfld.long 0x14 0.--3. "GPMC_WEN_MUXMODE," "GPMC_WEN_MUXMODE_0,GPMC_WEN_MUXMODE_1,?,?,GPMC_WEN_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_WEN_MUXMODE_14,GPMC_WEN_MUXMODE_15" line.long 0x18 "CTRL_CORE_PAD_GPMC_CS0," hexmask.long.word 0x18 20.--31. 1. "RESERVED," newline bitfld.long 0x18 19. "GPMC_CS0_SLEWCONTROL," "GPMC_CS0_SLEWCONTROL_0,GPMC_CS0_SLEWCONTROL_1" newline bitfld.long 0x18 18. "GPMC_CS0_INPUTENABLE," "GPMC_CS0_INPUTENABLE_0,GPMC_CS0_INPUTENABLE_1" newline bitfld.long 0x18 17. "GPMC_CS0_PULLTYPESELECT," "GPMC_CS0_PULLTYPESELECT_0,GPMC_CS0_PULLTYPESELECT_1" newline bitfld.long 0x18 16. "GPMC_CS0_PULLUDENABLE," "GPMC_CS0_PULLUDENABLE_0,GPMC_CS0_PULLUDENABLE_1" newline hexmask.long.word 0x18 4.--15. 1. "RESERVED," newline bitfld.long 0x18 0.--3. "GPMC_CS0_MUXMODE," "GPMC_CS0_MUXMODE_0,GPMC_CS0_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS0_MUXMODE_14,GPMC_CS0_MUXMODE_15" line.long 0x1C "CTRL_CORE_PAD_GPMC_CS1," hexmask.long.word 0x1C 20.--31. 1. "RESERVED," newline bitfld.long 0x1C 19. "GPMC_CS1_SLEWCONTROL," "GPMC_CS1_SLEWCONTROL_0,GPMC_CS1_SLEWCONTROL_1" newline bitfld.long 0x1C 18. "GPMC_CS1_INPUTENABLE," "GPMC_CS1_INPUTENABLE_0,GPMC_CS1_INPUTENABLE_1" newline bitfld.long 0x1C 17. "GPMC_CS1_PULLTYPESELECT," "GPMC_CS1_PULLTYPESELECT_0,GPMC_CS1_PULLTYPESELECT_1" newline bitfld.long 0x1C 16. "GPMC_CS1_PULLUDENABLE," "GPMC_CS1_PULLUDENABLE_0,GPMC_CS1_PULLUDENABLE_1" newline hexmask.long.word 0x1C 4.--15. 1. "RESERVED," newline bitfld.long 0x1C 0.--3. "GPMC_CS1_MUXMODE," "GPMC_CS1_MUXMODE_0,GPMC_CS1_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS1_MUXMODE_14,GPMC_CS1_MUXMODE_15" line.long 0x20 "CTRL_CORE_PAD_GPMC_CS2," hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline bitfld.long 0x20 19. "GPMC_CS2_SLEWCONTROL," "GPMC_CS2_SLEWCONTROL_0,GPMC_CS2_SLEWCONTROL_1" newline bitfld.long 0x20 18. "GPMC_CS2_INPUTENABLE," "GPMC_CS2_INPUTENABLE_0,GPMC_CS2_INPUTENABLE_1" newline bitfld.long 0x20 17. "GPMC_CS2_PULLTYPESELECT," "GPMC_CS2_PULLTYPESELECT_0,GPMC_CS2_PULLTYPESELECT_1" newline bitfld.long 0x20 16. "GPMC_CS2_PULLUDENABLE," "GPMC_CS2_PULLUDENABLE_0,GPMC_CS2_PULLUDENABLE_1" newline hexmask.long.word 0x20 4.--15. 1. "RESERVED," newline bitfld.long 0x20 0.--3. "GPMC_CS2_MUXMODE," "GPMC_CS2_MUXMODE_0,GPMC_CS2_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS2_MUXMODE_14,GPMC_CS2_MUXMODE_15" line.long 0x24 "CTRL_CORE_PAD_GPMC_CS3," hexmask.long.word 0x24 20.--31. 1. "RESERVED," newline bitfld.long 0x24 19. "GPMC_CS3_SLEWCONTROL," "GPMC_CS3_SLEWCONTROL_0,GPMC_CS3_SLEWCONTROL_1" newline bitfld.long 0x24 18. "GPMC_CS3_INPUTENABLE," "GPMC_CS3_INPUTENABLE_0,GPMC_CS3_INPUTENABLE_1" newline bitfld.long 0x24 17. "GPMC_CS3_PULLTYPESELECT," "GPMC_CS3_PULLTYPESELECT_0,GPMC_CS3_PULLTYPESELECT_1" newline bitfld.long 0x24 16. "GPMC_CS3_PULLUDENABLE," "GPMC_CS3_PULLUDENABLE_0,GPMC_CS3_PULLUDENABLE_1" newline hexmask.long.word 0x24 4.--15. 1. "RESERVED," newline bitfld.long 0x24 0.--3. "GPMC_CS3_MUXMODE," "GPMC_CS3_MUXMODE_0,GPMC_CS3_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS3_MUXMODE_14,GPMC_CS3_MUXMODE_15" line.long 0x28 "CTRL_CORE_PAD_GPMC_CS4," hexmask.long.word 0x28 20.--31. 1. "RESERVED," newline bitfld.long 0x28 19. "GPMC_CS4_SLEWCONTROL," "GPMC_CS4_SLEWCONTROL_0,GPMC_CS4_SLEWCONTROL_1" newline bitfld.long 0x28 18. "GPMC_CS4_INPUTENABLE," "GPMC_CS4_INPUTENABLE_0,GPMC_CS4_INPUTENABLE_1" newline bitfld.long 0x28 17. "GPMC_CS4_PULLTYPESELECT," "GPMC_CS4_PULLTYPESELECT_0,GPMC_CS4_PULLTYPESELECT_1" newline bitfld.long 0x28 16. "GPMC_CS4_PULLUDENABLE," "GPMC_CS4_PULLUDENABLE_0,GPMC_CS4_PULLUDENABLE_1" newline hexmask.long.word 0x28 4.--15. 1. "RESERVED," newline bitfld.long 0x28 0.--3. "GPMC_CS4_MUXMODE," "GPMC_CS4_MUXMODE_0,GPMC_CS4_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS4_MUXMODE_14,GPMC_CS4_MUXMODE_15" line.long 0x2C "CTRL_CORE_PAD_GPMC_CS5," hexmask.long.word 0x2C 20.--31. 1. "RESERVED," newline bitfld.long 0x2C 19. "GPMC_CS5_SLEWCONTROL," "GPMC_CS5_SLEWCONTROL_0,GPMC_CS5_SLEWCONTROL_1" newline bitfld.long 0x2C 18. "GPMC_CS5_INPUTENABLE," "GPMC_CS5_INPUTENABLE_0,GPMC_CS5_INPUTENABLE_1" newline bitfld.long 0x2C 17. "GPMC_CS5_PULLTYPESELECT," "GPMC_CS5_PULLTYPESELECT_0,GPMC_CS5_PULLTYPESELECT_1" newline bitfld.long 0x2C 16. "GPMC_CS5_PULLUDENABLE," "GPMC_CS5_PULLUDENABLE_0,GPMC_CS5_PULLUDENABLE_1" newline hexmask.long.word 0x2C 4.--15. 1. "RESERVED," newline bitfld.long 0x2C 0.--3. "GPMC_CS5_MUXMODE," "GPMC_CS5_MUXMODE_0,GPMC_CS5_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS5_MUXMODE_14,GPMC_CS5_MUXMODE_15" line.long 0x30 "CTRL_CORE_PAD_GPMC_CS6," hexmask.long.word 0x30 20.--31. 1. "RESERVED," newline bitfld.long 0x30 19. "GPMC_CS6_SLEWCONTROL," "GPMC_CS6_SLEWCONTROL_0,GPMC_CS6_SLEWCONTROL_1" newline bitfld.long 0x30 18. "GPMC_CS6_INPUTENABLE," "GPMC_CS6_INPUTENABLE_0,GPMC_CS6_INPUTENABLE_1" newline bitfld.long 0x30 17. "GPMC_CS6_PULLTYPESELECT," "GPMC_CS6_PULLTYPESELECT_0,GPMC_CS6_PULLTYPESELECT_1" newline bitfld.long 0x30 16. "GPMC_CS6_PULLUDENABLE," "GPMC_CS6_PULLUDENABLE_0,GPMC_CS6_PULLUDENABLE_1" newline hexmask.long.word 0x30 4.--15. 1. "RESERVED," newline bitfld.long 0x30 0.--3. "GPMC_CS6_MUXMODE," "GPMC_CS6_MUXMODE_0,GPMC_CS6_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS6_MUXMODE_14,GPMC_CS6_MUXMODE_15" line.long 0x34 "CTRL_CORE_PAD_GPMC_WAIT0," hexmask.long.word 0x34 20.--31. 1. "RESERVED," newline bitfld.long 0x34 19. "GPMC_WAIT0_SLEWCONTROL," "GPMC_WAIT0_SLEWCONTROL_0,GPMC_WAIT0_SLEWCONTROL_1" newline bitfld.long 0x34 18. "GPMC_WAIT0_INPUTENABLE," "GPMC_WAIT0_INPUTENABLE_0,GPMC_WAIT0_INPUTENABLE_1" newline bitfld.long 0x34 17. "GPMC_WAIT0_PULLTYPESELECT," "GPMC_WAIT0_PULLTYPESELECT_0,GPMC_WAIT0_PULLTYPESELECT_1" newline bitfld.long 0x34 16. "GPMC_WAIT0_PULLUDENABLE," "GPMC_WAIT0_PULLUDENABLE_0,GPMC_WAIT0_PULLUDENABLE_1" newline hexmask.long.word 0x34 4.--15. 1. "RESERVED," newline bitfld.long 0x34 0.--3. "GPMC_WAIT0_MUXMODE," "GPMC_WAIT0_MUXMODE_0,GPMC_WAIT0_MUXMODE_1,GPMC_WAIT0_MUXMODE_2,?,?,?,GPMC_WAIT0_MUXMODE_6,?,?,?,?,?,?,?,GPMC_WAIT0_MUXMODE_14,GPMC_WAIT0_MUXMODE_15" line.long 0x38 "CTRL_CORE_PAD_GPMC_AD0," hexmask.long.word 0x38 20.--31. 1. "RESERVED," newline bitfld.long 0x38 19. "GPMC_AD0_SLEWCONTROL," "GPMC_AD0_SLEWCONTROL_0,GPMC_AD0_SLEWCONTROL_1" newline bitfld.long 0x38 18. "GPMC_AD0_INPUTENABLE," "GPMC_AD0_INPUTENABLE_0,GPMC_AD0_INPUTENABLE_1" newline bitfld.long 0x38 17. "GPMC_AD0_PULLTYPESELECT," "GPMC_AD0_PULLTYPESELECT_0,GPMC_AD0_PULLTYPESELECT_1" newline bitfld.long 0x38 16. "GPMC_AD0_PULLUDENABLE," "GPMC_AD0_PULLUDENABLE_0,GPMC_AD0_PULLUDENABLE_1" newline hexmask.long.word 0x38 4.--15. 1. "RESERVED," newline bitfld.long 0x38 0.--3. "GPMC_AD0_MUXMODE," "GPMC_AD0_MUXMODE_0,GPMC_AD0_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_AD0_MUXMODE_14,GPMC_AD0_MUXMODE_15" line.long 0x3C "CTRL_CORE_PAD_GPMC_AD1," hexmask.long.word 0x3C 20.--31. 1. "RESERVED," newline bitfld.long 0x3C 19. "GPMC_AD1_SLEWCONTROL," "GPMC_AD1_SLEWCONTROL_0,GPMC_AD1_SLEWCONTROL_1" newline bitfld.long 0x3C 18. "GPMC_AD1_INPUTENABLE," "GPMC_AD1_INPUTENABLE_0,GPMC_AD1_INPUTENABLE_1" newline bitfld.long 0x3C 17. "GPMC_AD1_PULLTYPESELECT," "GPMC_AD1_PULLTYPESELECT_0,GPMC_AD1_PULLTYPESELECT_1" newline bitfld.long 0x3C 16. "GPMC_AD1_PULLUDENABLE," "GPMC_AD1_PULLUDENABLE_0,GPMC_AD1_PULLUDENABLE_1" newline hexmask.long.word 0x3C 4.--15. 1. "RESERVED," newline bitfld.long 0x3C 0.--3. "GPMC_AD1_MUXMODE," "GPMC_AD1_MUXMODE_0,GPMC_AD1_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_AD1_MUXMODE_14,GPMC_AD1_MUXMODE_15" line.long 0x40 "CTRL_CORE_PAD_GPMC_AD2," hexmask.long.word 0x40 20.--31. 1. "RESERVED," newline bitfld.long 0x40 19. "GPMC_AD2_SLEWCONTROL," "GPMC_AD2_SLEWCONTROL_0,GPMC_AD2_SLEWCONTROL_1" newline bitfld.long 0x40 18. "GPMC_AD2_INPUTENABLE," "GPMC_AD2_INPUTENABLE_0,GPMC_AD2_INPUTENABLE_1" newline bitfld.long 0x40 17. "GPMC_AD2_PULLTYPESELECT," "GPMC_AD2_PULLTYPESELECT_0,GPMC_AD2_PULLTYPESELECT_1" newline bitfld.long 0x40 16. "GPMC_AD2_PULLUDENABLE," "GPMC_AD2_PULLUDENABLE_0,GPMC_AD2_PULLUDENABLE_1" newline hexmask.long.word 0x40 4.--15. 1. "RESERVED," newline bitfld.long 0x40 0.--3. "GPMC_AD2_MUXMODE," "GPMC_AD2_MUXMODE_0,GPMC_AD2_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_AD2_MUXMODE_14,GPMC_AD2_MUXMODE_15" line.long 0x44 "CTRL_CORE_PAD_GPMC_AD3," hexmask.long.word 0x44 20.--31. 1. "RESERVED," newline bitfld.long 0x44 19. "GPMC_AD3_SLEWCONTROL," "GPMC_AD3_SLEWCONTROL_0,GPMC_AD3_SLEWCONTROL_1" newline bitfld.long 0x44 18. "GPMC_AD3_INPUTENABLE," "GPMC_AD3_INPUTENABLE_0,GPMC_AD3_INPUTENABLE_1" newline bitfld.long 0x44 17. "GPMC_AD3_PULLTYPESELECT," "GPMC_AD3_PULLTYPESELECT_0,GPMC_AD3_PULLTYPESELECT_1" newline bitfld.long 0x44 16. "GPMC_AD3_PULLUDENABLE," "GPMC_AD3_PULLUDENABLE_0,GPMC_AD3_PULLUDENABLE_1" newline hexmask.long.word 0x44 4.--15. 1. "RESERVED," newline bitfld.long 0x44 0.--3. "GPMC_AD3_MUXMODE," "GPMC_AD3_MUXMODE_0,GPMC_AD3_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_AD3_MUXMODE_14,GPMC_AD3_MUXMODE_15" line.long 0x48 "CTRL_CORE_PAD_GPMC_AD4," hexmask.long.word 0x48 20.--31. 1. "RESERVED," newline bitfld.long 0x48 19. "GPMC_AD4_SLEWCONTROL," "GPMC_AD4_SLEWCONTROL_0,GPMC_AD4_SLEWCONTROL_1" newline bitfld.long 0x48 18. "GPMC_AD4_INPUTENABLE," "GPMC_AD4_INPUTENABLE_0,GPMC_AD4_INPUTENABLE_1" newline bitfld.long 0x48 17. "GPMC_AD4_PULLTYPESELECT," "GPMC_AD4_PULLTYPESELECT_0,GPMC_AD4_PULLTYPESELECT_1" newline bitfld.long 0x48 16. "GPMC_AD4_PULLUDENABLE," "GPMC_AD4_PULLUDENABLE_0,GPMC_AD4_PULLUDENABLE_1" newline hexmask.long.word 0x48 4.--15. 1. "RESERVED," newline bitfld.long 0x48 0.--3. "GPMC_AD4_MUXMODE," "GPMC_AD4_MUXMODE_0,GPMC_AD4_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_AD4_MUXMODE_14,GPMC_AD4_MUXMODE_15" line.long 0x4C "CTRL_CORE_PAD_GPMC_AD5," hexmask.long.word 0x4C 20.--31. 1. "RESERVED," newline bitfld.long 0x4C 19. "GPMC_AD5_SLEWCONTROL," "GPMC_AD5_SLEWCONTROL_0,GPMC_AD5_SLEWCONTROL_1" newline bitfld.long 0x4C 18. "GPMC_AD5_INPUTENABLE," "GPMC_AD5_INPUTENABLE_0,GPMC_AD5_INPUTENABLE_1" newline bitfld.long 0x4C 17. "GPMC_AD5_PULLTYPESELECT," "GPMC_AD5_PULLTYPESELECT_0,GPMC_AD5_PULLTYPESELECT_1" newline bitfld.long 0x4C 16. "GPMC_AD5_PULLUDENABLE," "GPMC_AD5_PULLUDENABLE_0,GPMC_AD5_PULLUDENABLE_1" newline hexmask.long.word 0x4C 4.--15. 1. "RESERVED," newline bitfld.long 0x4C 0.--3. "GPMC_AD5_MUXMODE," "GPMC_AD5_MUXMODE_0,?,GPMC_AD5_MUXMODE_2,GPMC_AD5_MUXMODE_3,GPMC_AD5_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_AD5_MUXMODE_14,GPMC_AD5_MUXMODE_15" line.long 0x50 "CTRL_CORE_PAD_GPMC_AD6," hexmask.long.word 0x50 20.--31. 1. "RESERVED," newline bitfld.long 0x50 19. "GPMC_AD6_SLEWCONTROL," "GPMC_AD6_SLEWCONTROL_0,GPMC_AD6_SLEWCONTROL_1" newline bitfld.long 0x50 18. "GPMC_AD6_INPUTENABLE," "GPMC_AD6_INPUTENABLE_0,GPMC_AD6_INPUTENABLE_1" newline bitfld.long 0x50 17. "GPMC_AD6_PULLTYPESELECT," "GPMC_AD6_PULLTYPESELECT_0,GPMC_AD6_PULLTYPESELECT_1" newline bitfld.long 0x50 16. "GPMC_AD6_PULLUDENABLE," "GPMC_AD6_PULLUDENABLE_0,GPMC_AD6_PULLUDENABLE_1" newline hexmask.long.word 0x50 4.--15. 1. "RESERVED," newline bitfld.long 0x50 0.--3. "GPMC_AD6_MUXMODE," "GPMC_AD6_MUXMODE_0,?,GPMC_AD6_MUXMODE_2,GPMC_AD6_MUXMODE_3,GPMC_AD6_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_AD6_MUXMODE_14,GPMC_AD6_MUXMODE_15" line.long 0x54 "CTRL_CORE_PAD_GPMC_AD7," hexmask.long.word 0x54 20.--31. 1. "RESERVED," newline bitfld.long 0x54 19. "GPMC_AD7_SLEWCONTROL," "GPMC_AD7_SLEWCONTROL_0,GPMC_AD7_SLEWCONTROL_1" newline bitfld.long 0x54 18. "GPMC_AD7_INPUTENABLE," "GPMC_AD7_INPUTENABLE_0,GPMC_AD7_INPUTENABLE_1" newline bitfld.long 0x54 17. "GPMC_AD7_PULLTYPESELECT," "GPMC_AD7_PULLTYPESELECT_0,GPMC_AD7_PULLTYPESELECT_1" newline bitfld.long 0x54 16. "GPMC_AD7_PULLUDENABLE," "GPMC_AD7_PULLUDENABLE_0,GPMC_AD7_PULLUDENABLE_1" newline hexmask.long.word 0x54 4.--15. 1. "RESERVED," newline bitfld.long 0x54 0.--3. "GPMC_AD7_MUXMODE," "GPMC_AD7_MUXMODE_0,GPMC_AD7_MUXMODE_1,?,GPMC_AD7_MUXMODE_3,GPMC_AD7_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_AD7_MUXMODE_14,GPMC_AD7_MUXMODE_15" line.long 0x58 "CTRL_CORE_PAD_GPMC_AD8," hexmask.long.word 0x58 20.--31. 1. "RESERVED," newline bitfld.long 0x58 19. "GPMC_AD8_SLEWCONTROL," "GPMC_AD8_SLEWCONTROL_0,GPMC_AD8_SLEWCONTROL_1" newline bitfld.long 0x58 18. "GPMC_AD8_INPUTENABLE," "GPMC_AD8_INPUTENABLE_0,GPMC_AD8_INPUTENABLE_1" newline bitfld.long 0x58 17. "GPMC_AD8_PULLTYPESELECT," "GPMC_AD8_PULLTYPESELECT_0,GPMC_AD8_PULLTYPESELECT_1" newline bitfld.long 0x58 16. "GPMC_AD8_PULLUDENABLE," "GPMC_AD8_PULLUDENABLE_0,GPMC_AD8_PULLUDENABLE_1" newline hexmask.long.word 0x58 4.--15. 1. "RESERVED," newline bitfld.long 0x58 0.--3. "GPMC_AD8_MUXMODE," "GPMC_AD8_MUXMODE_0,?,?,GPMC_AD8_MUXMODE_3,GPMC_AD8_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_AD8_MUXMODE_14,GPMC_AD8_MUXMODE_15" line.long 0x5C "CTRL_CORE_PAD_GPMC_AD9," hexmask.long.word 0x5C 20.--31. 1. "RESERVED," newline bitfld.long 0x5C 19. "GPMC_AD9_SLEWCONTROL," "GPMC_AD9_SLEWCONTROL_0,GPMC_AD9_SLEWCONTROL_1" newline bitfld.long 0x5C 18. "GPMC_AD9_INPUTENABLE," "GPMC_AD9_INPUTENABLE_0,GPMC_AD9_INPUTENABLE_1" newline bitfld.long 0x5C 17. "GPMC_AD9_PULLTYPESELECT," "GPMC_AD9_PULLTYPESELECT_0,GPMC_AD9_PULLTYPESELECT_1" newline bitfld.long 0x5C 16. "GPMC_AD9_PULLUDENABLE," "GPMC_AD9_PULLUDENABLE_0,GPMC_AD9_PULLUDENABLE_1" newline hexmask.long.word 0x5C 4.--15. 1. "RESERVED," newline bitfld.long 0x5C 0.--3. "GPMC_AD9_MUXMODE," "GPMC_AD9_MUXMODE_0,?,?,GPMC_AD9_MUXMODE_3,GPMC_AD9_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_AD9_MUXMODE_14,GPMC_AD9_MUXMODE_15" line.long 0x60 "CTRL_CORE_PAD_GPMC_AD10," hexmask.long.word 0x60 20.--31. 1. "RESERVED," newline bitfld.long 0x60 19. "GPMC_AD10_SLEWCONTROL," "GPMC_AD10_SLEWCONTROL_0,GPMC_AD10_SLEWCONTROL_1" newline bitfld.long 0x60 18. "GPMC_AD10_INPUTENABLE," "GPMC_AD10_INPUTENABLE_0,GPMC_AD10_INPUTENABLE_1" newline bitfld.long 0x60 17. "GPMC_AD10_PULLTYPESELECT," "GPMC_AD10_PULLTYPESELECT_0,GPMC_AD10_PULLTYPESELECT_1" newline bitfld.long 0x60 16. "GPMC_AD10_PULLUDENABLE," "GPMC_AD10_PULLUDENABLE_0,GPMC_AD10_PULLUDENABLE_1" newline hexmask.long.word 0x60 4.--15. 1. "RESERVED," newline bitfld.long 0x60 0.--3. "GPMC_AD10_MUXMODE," "GPMC_AD10_MUXMODE_0,?,?,GPMC_AD10_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD10_MUXMODE_14,GPMC_AD10_MUXMODE_15" line.long 0x64 "CTRL_CORE_PAD_GPMC_AD11," hexmask.long.word 0x64 20.--31. 1. "RESERVED," newline bitfld.long 0x64 19. "GPMC_AD11_SLEWCONTROL," "GPMC_AD11_SLEWCONTROL_0,GPMC_AD11_SLEWCONTROL_1" newline bitfld.long 0x64 18. "GPMC_AD11_INPUTENABLE," "GPMC_AD11_INPUTENABLE_0,GPMC_AD11_INPUTENABLE_1" newline bitfld.long 0x64 17. "GPMC_AD11_PULLTYPESELECT," "GPMC_AD11_PULLTYPESELECT_0,GPMC_AD11_PULLTYPESELECT_1" newline bitfld.long 0x64 16. "GPMC_AD11_PULLUDENABLE," "GPMC_AD11_PULLUDENABLE_0,GPMC_AD11_PULLUDENABLE_1" newline hexmask.long.word 0x64 4.--15. 1. "RESERVED," newline bitfld.long 0x64 0.--3. "GPMC_AD11_MUXMODE," "GPMC_AD11_MUXMODE_0,?,?,GPMC_AD11_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD11_MUXMODE_14,GPMC_AD11_MUXMODE_15" line.long 0x68 "CTRL_CORE_PAD_GPMC_AD12," hexmask.long.word 0x68 20.--31. 1. "RESERVED," newline bitfld.long 0x68 19. "GPMC_AD12_SLEWCONTROL," "GPMC_AD12_SLEWCONTROL_0,GPMC_AD12_SLEWCONTROL_1" newline bitfld.long 0x68 18. "GPMC_AD12_INPUTENABLE," "GPMC_AD12_INPUTENABLE_0,GPMC_AD12_INPUTENABLE_1" newline bitfld.long 0x68 17. "GPMC_AD12_PULLTYPESELECT," "GPMC_AD12_PULLTYPESELECT_0,GPMC_AD12_PULLTYPESELECT_1" newline bitfld.long 0x68 16. "GPMC_AD12_PULLUDENABLE," "GPMC_AD12_PULLUDENABLE_0,GPMC_AD12_PULLUDENABLE_1" newline hexmask.long.word 0x68 4.--15. 1. "RESERVED," newline bitfld.long 0x68 0.--3. "GPMC_AD12_MUXMODE," "GPMC_AD12_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_AD12_MUXMODE_14,GPMC_AD12_MUXMODE_15" line.long 0x6C "CTRL_CORE_PAD_GPMC_AD13," hexmask.long.word 0x6C 20.--31. 1. "RESERVED," newline bitfld.long 0x6C 19. "GPMC_AD13_SLEWCONTROL," "GPMC_AD13_SLEWCONTROL_0,GPMC_AD13_SLEWCONTROL_1" newline bitfld.long 0x6C 18. "GPMC_AD13_INPUTENABLE," "GPMC_AD13_INPUTENABLE_0,GPMC_AD13_INPUTENABLE_1" newline bitfld.long 0x6C 17. "GPMC_AD13_PULLTYPESELECT," "GPMC_AD13_PULLTYPESELECT_0,GPMC_AD13_PULLTYPESELECT_1" newline bitfld.long 0x6C 16. "GPMC_AD13_PULLUDENABLE," "GPMC_AD13_PULLUDENABLE_0,GPMC_AD13_PULLUDENABLE_1" newline hexmask.long.word 0x6C 4.--15. 1. "RESERVED," newline bitfld.long 0x6C 0.--3. "GPMC_AD13_MUXMODE," "GPMC_AD13_MUXMODE_0,GPMC_AD13_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_AD13_MUXMODE_14,GPMC_AD13_MUXMODE_15" line.long 0x70 "CTRL_CORE_PAD_GPMC_AD14," hexmask.long.word 0x70 20.--31. 1. "RESERVED," newline bitfld.long 0x70 19. "GPMC_AD14_SLEWCONTROL," "GPMC_AD14_SLEWCONTROL_0,GPMC_AD14_SLEWCONTROL_1" newline bitfld.long 0x70 18. "GPMC_AD14_INPUTENABLE," "GPMC_AD14_INPUTENABLE_0,GPMC_AD14_INPUTENABLE_1" newline bitfld.long 0x70 17. "GPMC_AD14_PULLTYPESELECT," "GPMC_AD14_PULLTYPESELECT_0,GPMC_AD14_PULLTYPESELECT_1" newline bitfld.long 0x70 16. "GPMC_AD14_PULLUDENABLE," "GPMC_AD14_PULLUDENABLE_0,GPMC_AD14_PULLUDENABLE_1" newline hexmask.long.word 0x70 4.--15. 1. "RESERVED," newline bitfld.long 0x70 0.--3. "GPMC_AD14_MUXMODE," "GPMC_AD14_MUXMODE_0,?,?,?,GPMC_AD14_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_AD14_MUXMODE_14,GPMC_AD14_MUXMODE_15" line.long 0x74 "CTRL_CORE_PAD_GPMC_AD15," hexmask.long.word 0x74 20.--31. 1. "RESERVED," newline bitfld.long 0x74 19. "GPMC_AD15_SLEWCONTROL," "GPMC_AD15_SLEWCONTROL_0,GPMC_AD15_SLEWCONTROL_1" newline bitfld.long 0x74 18. "GPMC_AD15_INPUTENABLE," "GPMC_AD15_INPUTENABLE_0,GPMC_AD15_INPUTENABLE_1" newline bitfld.long 0x74 17. "GPMC_AD15_PULLTYPESELECT," "GPMC_AD15_PULLTYPESELECT_0,GPMC_AD15_PULLTYPESELECT_1" newline bitfld.long 0x74 16. "GPMC_AD15_PULLUDENABLE," "GPMC_AD15_PULLUDENABLE_0,GPMC_AD15_PULLUDENABLE_1" newline hexmask.long.word 0x74 4.--15. 1. "RESERVED," newline bitfld.long 0x74 0.--3. "GPMC_AD15_MUXMODE," "GPMC_AD15_MUXMODE_0,?,?,?,GPMC_AD15_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_AD15_MUXMODE_14,GPMC_AD15_MUXMODE_15" line.long 0x78 "CTRL_CORE_PAD_VIN1A_CLK0," hexmask.long.word 0x78 20.--31. 1. "RESERVED," newline bitfld.long 0x78 19. "VIN1A_CLK0_SLEWCONTROL," "VIN1A_CLK0_SLEWCONTROL_0,VIN1A_CLK0_SLEWCONTROL_1" newline bitfld.long 0x78 18. "VIN1A_CLK0_INPUTENABLE," "VIN1A_CLK0_INPUTENABLE_0,VIN1A_CLK0_INPUTENABLE_1" newline bitfld.long 0x78 17. "VIN1A_CLK0_PULLTYPESELECT," "VIN1A_CLK0_PULLTYPESELECT_0,VIN1A_CLK0_PULLTYPESELECT_1" newline bitfld.long 0x78 16. "VIN1A_CLK0_PULLUDENABLE," "VIN1A_CLK0_PULLUDENABLE_0,VIN1A_CLK0_PULLUDENABLE_1" newline hexmask.long.word 0x78 4.--15. 1. "RESERVED," newline bitfld.long 0x78 0.--3. "VIN1A_CLK0_MUXMODE," "VIN1A_CLK0_MUXMODE_0,VIN1A_CLK0_MUXMODE_1,?,?,VIN1A_CLK0_MUXMODE_4,?,?,?,?,?,?,?,?,?,VIN1A_CLK0_MUXMODE_14,VIN1A_CLK0_MUXMODE_15" line.long 0x7C "CTRL_CORE_PAD_VIN1A_DE0," hexmask.long.word 0x7C 20.--31. 1. "RESERVED," newline bitfld.long 0x7C 19. "VIN1A_DE0_SLEWCONTROL," "VIN1A_DE0_SLEWCONTROL_0,VIN1A_DE0_SLEWCONTROL_1" newline bitfld.long 0x7C 18. "VIN1A_DE0_INPUTENABLE," "VIN1A_DE0_INPUTENABLE_0,VIN1A_DE0_INPUTENABLE_1" newline bitfld.long 0x7C 17. "VIN1A_DE0_PULLTYPESELECT," "VIN1A_DE0_PULLTYPESELECT_0,VIN1A_DE0_PULLTYPESELECT_1" newline bitfld.long 0x7C 16. "VIN1A_DE0_PULLUDENABLE," "VIN1A_DE0_PULLUDENABLE_0,VIN1A_DE0_PULLUDENABLE_1" newline hexmask.long.word 0x7C 4.--15. 1. "RESERVED," newline bitfld.long 0x7C 0.--3. "VIN1A_DE0_MUXMODE," "VIN1A_DE0_MUXMODE_0,VIN1A_DE0_MUXMODE_1,VIN1A_DE0_MUXMODE_2,?,VIN1A_DE0_MUXMODE_4,?,?,?,?,?,?,?,?,?,VIN1A_DE0_MUXMODE_14,VIN1A_DE0_MUXMODE_15" line.long 0x80 "CTRL_CORE_PAD_VIN1A_FLD0," hexmask.long.word 0x80 20.--31. 1. "RESERVED," newline bitfld.long 0x80 19. "VIN1A_FLD0_SLEWCONTROL," "VIN1A_FLD0_SLEWCONTROL_0,VIN1A_FLD0_SLEWCONTROL_1" newline bitfld.long 0x80 18. "VIN1A_FLD0_INPUTENABLE," "VIN1A_FLD0_INPUTENABLE_0,VIN1A_FLD0_INPUTENABLE_1" newline bitfld.long 0x80 17. "VIN1A_FLD0_PULLTYPESELECT," "VIN1A_FLD0_PULLTYPESELECT_0,VIN1A_FLD0_PULLTYPESELECT_1" newline bitfld.long 0x80 16. "VIN1A_FLD0_PULLUDENABLE," "VIN1A_FLD0_PULLUDENABLE_0,VIN1A_FLD0_PULLUDENABLE_1" newline hexmask.long.word 0x80 4.--15. 1. "RESERVED," newline bitfld.long 0x80 0.--3. "VIN1A_FLD0_MUXMODE," "VIN1A_FLD0_MUXMODE_0,VIN1A_FLD0_MUXMODE_1,VIN1A_FLD0_MUXMODE_2,?,VIN1A_FLD0_MUXMODE_4,?,?,?,?,?,?,?,?,?,VIN1A_FLD0_MUXMODE_14,VIN1A_FLD0_MUXMODE_15" line.long 0x84 "CTRL_CORE_PAD_VIN1A_HSYNC0," hexmask.long.word 0x84 20.--31. 1. "RESERVED," newline bitfld.long 0x84 19. "VIN1A_HSYNC0_SLEWCONTROL," "VIN1A_HSYNC0_SLEWCONTROL_0,VIN1A_HSYNC0_SLEWCONTROL_1" newline bitfld.long 0x84 18. "VIN1A_HSYNC0_INPUTENABLE," "VIN1A_HSYNC0_INPUTENABLE_0,VIN1A_HSYNC0_INPUTENABLE_1" newline bitfld.long 0x84 17. "VIN1A_HSYNC0_PULLTYPESELECT," "VIN1A_HSYNC0_PULLTYPESELECT_0,VIN1A_HSYNC0_PULLTYPESELECT_1" newline bitfld.long 0x84 16. "VIN1A_HSYNC0_PULLUDENABLE," "VIN1A_HSYNC0_PULLUDENABLE_0,VIN1A_HSYNC0_PULLUDENABLE_1" newline hexmask.long.word 0x84 4.--15. 1. "RESERVED," newline bitfld.long 0x84 0.--3. "VIN1A_HSYNC0_MUXMODE," "VIN1A_HSYNC0_MUXMODE_0,VIN1A_HSYNC0_MUXMODE_1,VIN1A_HSYNC0_MUXMODE_2,?,?,?,?,?,?,?,?,?,?,?,VIN1A_HSYNC0_MUXMODE_14,VIN1A_HSYNC0_MUXMODE_15" line.long 0x88 "CTRL_CORE_PAD_VIN1A_VSYNC0," hexmask.long.word 0x88 20.--31. 1. "RESERVED," newline bitfld.long 0x88 19. "VIN1A_VSYNC0_SLEWCONTROL," "VIN1A_VSYNC0_SLEWCONTROL_0,VIN1A_VSYNC0_SLEWCONTROL_1" newline bitfld.long 0x88 18. "VIN1A_VSYNC0_INPUTENABLE," "VIN1A_VSYNC0_INPUTENABLE_0,VIN1A_VSYNC0_INPUTENABLE_1" newline bitfld.long 0x88 17. "VIN1A_VSYNC0_PULLTYPESELECT," "VIN1A_VSYNC0_PULLTYPESELECT_0,VIN1A_VSYNC0_PULLTYPESELECT_1" newline bitfld.long 0x88 16. "VIN1A_VSYNC0_PULLUDENABLE," "VIN1A_VSYNC0_PULLUDENABLE_0,VIN1A_VSYNC0_PULLUDENABLE_1" newline hexmask.long.word 0x88 4.--15. 1. "RESERVED," newline bitfld.long 0x88 0.--3. "VIN1A_VSYNC0_MUXMODE," "VIN1A_VSYNC0_MUXMODE_0,VIN1A_VSYNC0_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_VSYNC0_MUXMODE_14,VIN1A_VSYNC0_MUXMODE_15" line.long 0x8C "CTRL_CORE_PAD_VIN1A_D0," hexmask.long.word 0x8C 20.--31. 1. "RESERVED," newline bitfld.long 0x8C 19. "VIN1A_D0_SLEWCONTROL," "VIN1A_D0_SLEWCONTROL_0,VIN1A_D0_SLEWCONTROL_1" newline bitfld.long 0x8C 18. "VIN1A_D0_INPUTENABLE," "VIN1A_D0_INPUTENABLE_0,VIN1A_D0_INPUTENABLE_1" newline bitfld.long 0x8C 17. "VIN1A_D0_PULLTYPESELECT," "VIN1A_D0_PULLTYPESELECT_0,VIN1A_D0_PULLTYPESELECT_1" newline bitfld.long 0x8C 16. "VIN1A_D0_PULLUDENABLE," "VIN1A_D0_PULLUDENABLE_0,VIN1A_D0_PULLUDENABLE_1" newline hexmask.long.word 0x8C 4.--15. 1. "RESERVED," newline bitfld.long 0x8C 0.--3. "VIN1A_D0_MUXMODE," "VIN1A_D0_MUXMODE_0,VIN1A_D0_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_D0_MUXMODE_14,VIN1A_D0_MUXMODE_15" line.long 0x90 "CTRL_CORE_PAD_VIN1A_D1," hexmask.long.word 0x90 20.--31. 1. "RESERVED," newline bitfld.long 0x90 19. "VIN1A_D1_SLEWCONTROL," "VIN1A_D1_SLEWCONTROL_0,VIN1A_D1_SLEWCONTROL_1" newline bitfld.long 0x90 18. "VIN1A_D1_INPUTENABLE," "VIN1A_D1_INPUTENABLE_0,VIN1A_D1_INPUTENABLE_1" newline bitfld.long 0x90 17. "VIN1A_D1_PULLTYPESELECT," "VIN1A_D1_PULLTYPESELECT_0,VIN1A_D1_PULLTYPESELECT_1" newline bitfld.long 0x90 16. "VIN1A_D1_PULLUDENABLE," "VIN1A_D1_PULLUDENABLE_0,VIN1A_D1_PULLUDENABLE_1" newline hexmask.long.word 0x90 4.--15. 1. "RESERVED," newline bitfld.long 0x90 0.--3. "VIN1A_D1_MUXMODE," "VIN1A_D1_MUXMODE_0,VIN1A_D1_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_D1_MUXMODE_14,VIN1A_D1_MUXMODE_15" line.long 0x94 "CTRL_CORE_PAD_VIN1A_D2," hexmask.long.word 0x94 20.--31. 1. "RESERVED," newline bitfld.long 0x94 19. "VIN1A_D2_SLEWCONTROL," "VIN1A_D2_SLEWCONTROL_0,VIN1A_D2_SLEWCONTROL_1" newline bitfld.long 0x94 18. "VIN1A_D2_INPUTENABLE," "VIN1A_D2_INPUTENABLE_0,VIN1A_D2_INPUTENABLE_1" newline bitfld.long 0x94 17. "VIN1A_D2_PULLTYPESELECT," "VIN1A_D2_PULLTYPESELECT_0,VIN1A_D2_PULLTYPESELECT_1" newline bitfld.long 0x94 16. "VIN1A_D2_PULLUDENABLE," "VIN1A_D2_PULLUDENABLE_0,VIN1A_D2_PULLUDENABLE_1" newline hexmask.long.word 0x94 4.--15. 1. "RESERVED," newline bitfld.long 0x94 0.--3. "VIN1A_D2_MUXMODE," "VIN1A_D2_MUXMODE_0,VIN1A_D2_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_D2_MUXMODE_14,VIN1A_D2_MUXMODE_15" line.long 0x98 "CTRL_CORE_PAD_VIN1A_D3," hexmask.long.word 0x98 20.--31. 1. "RESERVED," newline bitfld.long 0x98 19. "VIN1A_D3_SLEWCONTROL," "VIN1A_D3_SLEWCONTROL_0,VIN1A_D3_SLEWCONTROL_1" newline bitfld.long 0x98 18. "VIN1A_D3_INPUTENABLE," "VIN1A_D3_INPUTENABLE_0,VIN1A_D3_INPUTENABLE_1" newline bitfld.long 0x98 17. "VIN1A_D3_PULLTYPESELECT," "VIN1A_D3_PULLTYPESELECT_0,VIN1A_D3_PULLTYPESELECT_1" newline bitfld.long 0x98 16. "VIN1A_D3_PULLUDENABLE," "VIN1A_D3_PULLUDENABLE_0,VIN1A_D3_PULLUDENABLE_1" newline hexmask.long.word 0x98 4.--15. 1. "RESERVED," newline bitfld.long 0x98 0.--3. "VIN1A_D3_MUXMODE," "VIN1A_D3_MUXMODE_0,VIN1A_D3_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_D3_MUXMODE_14,VIN1A_D3_MUXMODE_15" line.long 0x9C "CTRL_CORE_PAD_VIN1A_D4," hexmask.long.word 0x9C 20.--31. 1. "RESERVED," newline bitfld.long 0x9C 19. "VIN1A_D4_SLEWCONTROL," "VIN1A_D4_SLEWCONTROL_0,VIN1A_D4_SLEWCONTROL_1" newline bitfld.long 0x9C 18. "VIN1A_D4_INPUTENABLE," "VIN1A_D4_INPUTENABLE_0,VIN1A_D4_INPUTENABLE_1" newline bitfld.long 0x9C 17. "VIN1A_D4_PULLTYPESELECT," "VIN1A_D4_PULLTYPESELECT_0,VIN1A_D4_PULLTYPESELECT_1" newline bitfld.long 0x9C 16. "VIN1A_D4_PULLUDENABLE," "VIN1A_D4_PULLUDENABLE_0,VIN1A_D4_PULLUDENABLE_1" newline hexmask.long.word 0x9C 4.--15. 1. "RESERVED," newline bitfld.long 0x9C 0.--3. "VIN1A_D4_MUXMODE," "VIN1A_D4_MUXMODE_0,VIN1A_D4_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_D4_MUXMODE_14,VIN1A_D4_MUXMODE_15" line.long 0xA0 "CTRL_CORE_PAD_VIN1A_D5," hexmask.long.word 0xA0 20.--31. 1. "RESERVED," newline bitfld.long 0xA0 19. "VIN1A_D5_SLEWCONTROL," "VIN1A_D5_SLEWCONTROL_0,VIN1A_D5_SLEWCONTROL_1" newline bitfld.long 0xA0 18. "VIN1A_D5_INPUTENABLE," "VIN1A_D5_INPUTENABLE_0,VIN1A_D5_INPUTENABLE_1" newline bitfld.long 0xA0 17. "VIN1A_D5_PULLTYPESELECT," "VIN1A_D5_PULLTYPESELECT_0,VIN1A_D5_PULLTYPESELECT_1" newline bitfld.long 0xA0 16. "VIN1A_D5_PULLUDENABLE," "VIN1A_D5_PULLUDENABLE_0,VIN1A_D5_PULLUDENABLE_1" newline hexmask.long.word 0xA0 4.--15. 1. "RESERVED," newline bitfld.long 0xA0 0.--3. "VIN1A_D5_MUXMODE," "VIN1A_D5_MUXMODE_0,VIN1A_D5_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_D5_MUXMODE_14,VIN1A_D5_MUXMODE_15" line.long 0xA4 "CTRL_CORE_PAD_VIN1A_D6," hexmask.long.word 0xA4 20.--31. 1. "RESERVED," newline bitfld.long 0xA4 19. "VIN1A_D6_SLEWCONTROL," "VIN1A_D6_SLEWCONTROL_0,VIN1A_D6_SLEWCONTROL_1" newline bitfld.long 0xA4 18. "VIN1A_D6_INPUTENABLE," "VIN1A_D6_INPUTENABLE_0,VIN1A_D6_INPUTENABLE_1" newline bitfld.long 0xA4 17. "VIN1A_D6_PULLTYPESELECT," "VIN1A_D6_PULLTYPESELECT_0,VIN1A_D6_PULLTYPESELECT_1" newline bitfld.long 0xA4 16. "VIN1A_D6_PULLUDENABLE," "VIN1A_D6_PULLUDENABLE_0,VIN1A_D6_PULLUDENABLE_1" newline hexmask.long.word 0xA4 4.--15. 1. "RESERVED," newline bitfld.long 0xA4 0.--3. "VIN1A_D6_MUXMODE," "VIN1A_D6_MUXMODE_0,VIN1A_D6_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_D6_MUXMODE_14,VIN1A_D6_MUXMODE_15" line.long 0xA8 "CTRL_CORE_PAD_VIN1A_D7," hexmask.long.word 0xA8 20.--31. 1. "RESERVED," newline bitfld.long 0xA8 19. "VIN1A_D7_SLEWCONTROL," "VIN1A_D7_SLEWCONTROL_0,VIN1A_D7_SLEWCONTROL_1" newline bitfld.long 0xA8 18. "VIN1A_D7_INPUTENABLE," "VIN1A_D7_INPUTENABLE_0,VIN1A_D7_INPUTENABLE_1" newline bitfld.long 0xA8 17. "VIN1A_D7_PULLTYPESELECT," "VIN1A_D7_PULLTYPESELECT_0,VIN1A_D7_PULLTYPESELECT_1" newline bitfld.long 0xA8 16. "VIN1A_D7_PULLUDENABLE," "VIN1A_D7_PULLUDENABLE_0,VIN1A_D7_PULLUDENABLE_1" newline hexmask.long.word 0xA8 4.--15. 1. "RESERVED," newline bitfld.long 0xA8 0.--3. "VIN1A_D7_MUXMODE," "VIN1A_D7_MUXMODE_0,VIN1A_D7_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_D7_MUXMODE_14,VIN1A_D7_MUXMODE_15" line.long 0xAC "CTRL_CORE_PAD_VIN1A_D8," hexmask.long.word 0xAC 20.--31. 1. "RESERVED," newline bitfld.long 0xAC 19. "VIN1A_D8_SLEWCONTROL," "VIN1A_D8_SLEWCONTROL_0,VIN1A_D8_SLEWCONTROL_1" newline bitfld.long 0xAC 18. "VIN1A_D8_INPUTENABLE," "VIN1A_D8_INPUTENABLE_0,VIN1A_D8_INPUTENABLE_1" newline bitfld.long 0xAC 17. "VIN1A_D8_PULLTYPESELECT," "VIN1A_D8_PULLTYPESELECT_0,VIN1A_D8_PULLTYPESELECT_1" newline bitfld.long 0xAC 16. "VIN1A_D8_PULLUDENABLE," "VIN1A_D8_PULLUDENABLE_0,VIN1A_D8_PULLUDENABLE_1" newline hexmask.long.word 0xAC 4.--15. 1. "RESERVED," newline bitfld.long 0xAC 0.--3. "VIN1A_D8_MUXMODE," "VIN1A_D8_MUXMODE_0,VIN1A_D8_MUXMODE_1,VIN1A_D8_MUXMODE_2,VIN1A_D8_MUXMODE_3,?,?,?,VIN1A_D8_MUXMODE_7,?,?,?,?,?,?,VIN1A_D8_MUXMODE_14,VIN1A_D8_MUXMODE_15" line.long 0xB0 "CTRL_CORE_PAD_VIN1A_D9," hexmask.long.word 0xB0 20.--31. 1. "RESERVED," newline bitfld.long 0xB0 19. "VIN1A_D9_SLEWCONTROL," "VIN1A_D9_SLEWCONTROL_0,VIN1A_D9_SLEWCONTROL_1" newline bitfld.long 0xB0 18. "VIN1A_D9_INPUTENABLE," "VIN1A_D9_INPUTENABLE_0,VIN1A_D9_INPUTENABLE_1" newline bitfld.long 0xB0 17. "VIN1A_D9_PULLTYPESELECT," "VIN1A_D9_PULLTYPESELECT_0,VIN1A_D9_PULLTYPESELECT_1" newline bitfld.long 0xB0 16. "VIN1A_D9_PULLUDENABLE," "VIN1A_D9_PULLUDENABLE_0,VIN1A_D9_PULLUDENABLE_1" newline hexmask.long.word 0xB0 4.--15. 1. "RESERVED," newline bitfld.long 0xB0 0.--3. "VIN1A_D9_MUXMODE," "VIN1A_D9_MUXMODE_0,VIN1A_D9_MUXMODE_1,VIN1A_D9_MUXMODE_2,VIN1A_D9_MUXMODE_3,?,?,?,VIN1A_D9_MUXMODE_7,?,?,?,?,?,?,VIN1A_D9_MUXMODE_14,VIN1A_D9_MUXMODE_15" line.long 0xB4 "CTRL_CORE_PAD_VIN1A_D10," hexmask.long.word 0xB4 20.--31. 1. "RESERVED," newline bitfld.long 0xB4 19. "VIN1A_D10_SLEWCONTROL," "VIN1A_D10_SLEWCONTROL_0,VIN1A_D10_SLEWCONTROL_1" newline bitfld.long 0xB4 18. "VIN1A_D10_INPUTENABLE," "VIN1A_D10_INPUTENABLE_0,VIN1A_D10_INPUTENABLE_1" newline bitfld.long 0xB4 17. "VIN1A_D10_PULLTYPESELECT," "VIN1A_D10_PULLTYPESELECT_0,VIN1A_D10_PULLTYPESELECT_1" newline bitfld.long 0xB4 16. "VIN1A_D10_PULLUDENABLE," "VIN1A_D10_PULLUDENABLE_0,VIN1A_D10_PULLUDENABLE_1" newline hexmask.long.word 0xB4 4.--15. 1. "RESERVED," newline bitfld.long 0xB4 0.--3. "VIN1A_D10_MUXMODE," "VIN1A_D10_MUXMODE_0,VIN1A_D10_MUXMODE_1,VIN1A_D10_MUXMODE_2,VIN1A_D10_MUXMODE_3,?,?,?,VIN1A_D10_MUXMODE_7,?,?,?,?,?,?,VIN1A_D10_MUXMODE_14,VIN1A_D10_MUXMODE_15" line.long 0xB8 "CTRL_CORE_PAD_VIN1A_D11," hexmask.long.word 0xB8 20.--31. 1. "RESERVED," newline bitfld.long 0xB8 19. "VIN1A_D11_SLEWCONTROL," "VIN1A_D11_SLEWCONTROL_0,VIN1A_D11_SLEWCONTROL_1" newline bitfld.long 0xB8 18. "VIN1A_D11_INPUTENABLE," "VIN1A_D11_INPUTENABLE_0,VIN1A_D11_INPUTENABLE_1" newline bitfld.long 0xB8 17. "VIN1A_D11_PULLTYPESELECT," "VIN1A_D11_PULLTYPESELECT_0,VIN1A_D11_PULLTYPESELECT_1" newline bitfld.long 0xB8 16. "VIN1A_D11_PULLUDENABLE," "VIN1A_D11_PULLUDENABLE_0,VIN1A_D11_PULLUDENABLE_1" newline hexmask.long.word 0xB8 4.--15. 1. "RESERVED," newline bitfld.long 0xB8 0.--3. "VIN1A_D11_MUXMODE," "VIN1A_D11_MUXMODE_0,VIN1A_D11_MUXMODE_1,VIN1A_D11_MUXMODE_2,VIN1A_D11_MUXMODE_3,?,?,?,VIN1A_D11_MUXMODE_7,?,?,?,?,?,?,VIN1A_D11_MUXMODE_14,VIN1A_D11_MUXMODE_15" line.long 0xBC "CTRL_CORE_PAD_VIN1A_D12," hexmask.long.word 0xBC 20.--31. 1. "RESERVED," newline bitfld.long 0xBC 19. "VIN1A_D12_SLEWCONTROL," "VIN1A_D12_SLEWCONTROL_0,VIN1A_D12_SLEWCONTROL_1" newline bitfld.long 0xBC 18. "VIN1A_D12_INPUTENABLE," "VIN1A_D12_INPUTENABLE_0,VIN1A_D12_INPUTENABLE_1" newline bitfld.long 0xBC 17. "VIN1A_D12_PULLTYPESELECT," "VIN1A_D12_PULLTYPESELECT_0,VIN1A_D12_PULLTYPESELECT_1" newline bitfld.long 0xBC 16. "VIN1A_D12_PULLUDENABLE," "VIN1A_D12_PULLUDENABLE_0,VIN1A_D12_PULLUDENABLE_1" newline hexmask.long.word 0xBC 4.--15. 1. "RESERVED," newline bitfld.long 0xBC 0.--3. "VIN1A_D12_MUXMODE," "VIN1A_D12_MUXMODE_0,VIN1A_D12_MUXMODE_1,VIN1A_D12_MUXMODE_2,VIN1A_D12_MUXMODE_3,?,?,VIN1A_D12_MUXMODE_6,?,?,?,?,?,?,?,VIN1A_D12_MUXMODE_14,VIN1A_D12_MUXMODE_15" line.long 0xC0 "CTRL_CORE_PAD_VIN1A_D13," hexmask.long.word 0xC0 20.--31. 1. "RESERVED," newline bitfld.long 0xC0 19. "VIN1A_D13_SLEWCONTROL," "VIN1A_D13_SLEWCONTROL_0,VIN1A_D13_SLEWCONTROL_1" newline bitfld.long 0xC0 18. "VIN1A_D13_INPUTENABLE," "VIN1A_D13_INPUTENABLE_0,VIN1A_D13_INPUTENABLE_1" newline bitfld.long 0xC0 17. "VIN1A_D13_PULLTYPESELECT," "VIN1A_D13_PULLTYPESELECT_0,VIN1A_D13_PULLTYPESELECT_1" newline bitfld.long 0xC0 16. "VIN1A_D13_PULLUDENABLE," "VIN1A_D13_PULLUDENABLE_0,VIN1A_D13_PULLUDENABLE_1" newline hexmask.long.word 0xC0 4.--15. 1. "RESERVED," newline bitfld.long 0xC0 0.--3. "VIN1A_D13_MUXMODE," "VIN1A_D13_MUXMODE_0,VIN1A_D13_MUXMODE_1,VIN1A_D13_MUXMODE_2,VIN1A_D13_MUXMODE_3,?,?,VIN1A_D13_MUXMODE_6,?,?,?,?,?,?,?,VIN1A_D13_MUXMODE_14,VIN1A_D13_MUXMODE_15" line.long 0xC4 "CTRL_CORE_PAD_VIN1A_D14," hexmask.long.word 0xC4 20.--31. 1. "RESERVED," newline bitfld.long 0xC4 19. "VIN1A_D14_SLEWCONTROL," "VIN1A_D14_SLEWCONTROL_0,VIN1A_D14_SLEWCONTROL_1" newline bitfld.long 0xC4 18. "VIN1A_D14_INPUTENABLE," "VIN1A_D14_INPUTENABLE_0,VIN1A_D14_INPUTENABLE_1" newline bitfld.long 0xC4 17. "VIN1A_D14_PULLTYPESELECT," "VIN1A_D14_PULLTYPESELECT_0,VIN1A_D14_PULLTYPESELECT_1" newline bitfld.long 0xC4 16. "VIN1A_D14_PULLUDENABLE," "VIN1A_D14_PULLUDENABLE_0,VIN1A_D14_PULLUDENABLE_1" newline hexmask.long.word 0xC4 4.--15. 1. "RESERVED," newline bitfld.long 0xC4 0.--3. "VIN1A_D14_MUXMODE," "VIN1A_D14_MUXMODE_0,VIN1A_D14_MUXMODE_1,VIN1A_D14_MUXMODE_2,VIN1A_D14_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,VIN1A_D14_MUXMODE_14,VIN1A_D14_MUXMODE_15" line.long 0xC8 "CTRL_CORE_PAD_VIN1A_D15," hexmask.long.word 0xC8 20.--31. 1. "RESERVED," newline bitfld.long 0xC8 19. "VIN1A_D15_SLEWCONTROL," "VIN1A_D15_SLEWCONTROL_0,VIN1A_D15_SLEWCONTROL_1" newline bitfld.long 0xC8 18. "VIN1A_D15_INPUTENABLE," "VIN1A_D15_INPUTENABLE_0,VIN1A_D15_INPUTENABLE_1" newline bitfld.long 0xC8 17. "VIN1A_D15_PULLTYPESELECT," "VIN1A_D15_PULLTYPESELECT_0,VIN1A_D15_PULLTYPESELECT_1" newline bitfld.long 0xC8 16. "VIN1A_D15_PULLUDENABLE," "VIN1A_D15_PULLUDENABLE_0,VIN1A_D15_PULLUDENABLE_1" newline hexmask.long.word 0xC8 4.--15. 1. "RESERVED," newline bitfld.long 0xC8 0.--3. "VIN1A_D15_MUXMODE," "VIN1A_D15_MUXMODE_0,VIN1A_D15_MUXMODE_1,VIN1A_D15_MUXMODE_2,VIN1A_D15_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,VIN1A_D15_MUXMODE_14,VIN1A_D15_MUXMODE_15" line.long 0xCC "CTRL_CORE_PAD_VIN2A_CLK0," hexmask.long.word 0xCC 20.--31. 1. "RESERVED," newline bitfld.long 0xCC 19. "VIN2A_CLK0_SLEWCONTROL," "VIN2A_CLK0_SLEWCONTROL_0,VIN2A_CLK0_SLEWCONTROL_1" newline bitfld.long 0xCC 18. "VIN2A_CLK0_INPUTENABLE," "VIN2A_CLK0_INPUTENABLE_0,VIN2A_CLK0_INPUTENABLE_1" newline bitfld.long 0xCC 17. "VIN2A_CLK0_PULLTYPESELECT," "VIN2A_CLK0_PULLTYPESELECT_0,VIN2A_CLK0_PULLTYPESELECT_1" newline bitfld.long 0xCC 16. "VIN2A_CLK0_PULLUDENABLE," "VIN2A_CLK0_PULLUDENABLE_0,VIN2A_CLK0_PULLUDENABLE_1" newline hexmask.long.word 0xCC 4.--15. 1. "RESERVED," newline bitfld.long 0xCC 0.--3. "VIN2A_CLK0_MUXMODE," "VIN2A_CLK0_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,VIN2A_CLK0_MUXMODE_14,VIN2A_CLK0_MUXMODE_15" line.long 0xD0 "CTRL_CORE_PAD_VIN2A_DE0," hexmask.long.word 0xD0 20.--31. 1. "RESERVED," newline bitfld.long 0xD0 19. "VIN2A_DE0_SLEWCONTROL," "VIN2A_DE0_SLEWCONTROL_0,VIN2A_DE0_SLEWCONTROL_1" newline bitfld.long 0xD0 18. "VIN2A_DE0_INPUTENABLE," "VIN2A_DE0_INPUTENABLE_0,VIN2A_DE0_INPUTENABLE_1" newline bitfld.long 0xD0 17. "VIN2A_DE0_PULLTYPESELECT," "VIN2A_DE0_PULLTYPESELECT_0,VIN2A_DE0_PULLTYPESELECT_1" newline bitfld.long 0xD0 16. "VIN2A_DE0_PULLUDENABLE," "VIN2A_DE0_PULLUDENABLE_0,VIN2A_DE0_PULLUDENABLE_1" newline hexmask.long.word 0xD0 4.--15. 1. "RESERVED," newline bitfld.long 0xD0 0.--3. "VIN2A_DE0_MUXMODE," "VIN2A_DE0_MUXMODE_0,VIN2A_DE0_MUXMODE_1,VIN2A_DE0_MUXMODE_2,?,?,VIN2A_DE0_MUXMODE_5,?,?,?,?,?,?,?,?,VIN2A_DE0_MUXMODE_14,VIN2A_DE0_MUXMODE_15" line.long 0xD4 "CTRL_CORE_PAD_VIN2A_FLD0," hexmask.long.word 0xD4 20.--31. 1. "RESERVED," newline bitfld.long 0xD4 19. "VIN2A_FLD0_SLEWCONTROL," "VIN2A_FLD0_SLEWCONTROL_0,VIN2A_FLD0_SLEWCONTROL_1" newline bitfld.long 0xD4 18. "VIN2A_FLD0_INPUTENABLE," "VIN2A_FLD0_INPUTENABLE_0,VIN2A_FLD0_INPUTENABLE_1" newline bitfld.long 0xD4 17. "VIN2A_FLD0_PULLTYPESELECT," "VIN2A_FLD0_PULLTYPESELECT_0,VIN2A_FLD0_PULLTYPESELECT_1" newline bitfld.long 0xD4 16. "VIN2A_FLD0_PULLUDENABLE," "VIN2A_FLD0_PULLUDENABLE_0,VIN2A_FLD0_PULLUDENABLE_1" newline hexmask.long.word 0xD4 4.--15. 1. "RESERVED," newline bitfld.long 0xD4 0.--3. "VIN2A_FLD0_MUXMODE," "VIN2A_FLD0_MUXMODE_0,VIN2A_FLD0_MUXMODE_1,VIN2A_FLD0_MUXMODE_2,?,?,?,?,?,?,?,?,?,?,?,VIN2A_FLD0_MUXMODE_14,VIN2A_FLD0_MUXMODE_15" line.long 0xD8 "CTRL_CORE_PAD_VOUT1_CLK," hexmask.long.word 0xD8 20.--31. 1. "RESERVED," newline bitfld.long 0xD8 19. "VOUT1_CLK_SLEWCONTROL," "VOUT1_CLK_SLEWCONTROL_0,VOUT1_CLK_SLEWCONTROL_1" newline bitfld.long 0xD8 18. "VOUT1_CLK_INPUTENABLE," "VOUT1_CLK_INPUTENABLE_0,VOUT1_CLK_INPUTENABLE_1" newline bitfld.long 0xD8 17. "VOUT1_CLK_PULLTYPESELECT," "VOUT1_CLK_PULLTYPESELECT_0,VOUT1_CLK_PULLTYPESELECT_1" newline bitfld.long 0xD8 16. "VOUT1_CLK_PULLUDENABLE," "VOUT1_CLK_PULLUDENABLE_0,VOUT1_CLK_PULLUDENABLE_1" newline hexmask.long.word 0xD8 4.--15. 1. "RESERVED," newline bitfld.long 0xD8 0.--3. "VOUT1_CLK_MUXMODE," "VOUT1_CLK_MUXMODE_0,?,VOUT1_CLK_MUXMODE_2,?,VOUT1_CLK_MUXMODE_4,?,?,?,?,VOUT1_CLK_MUXMODE_9,?,?,?,?,VOUT1_CLK_MUXMODE_14,VOUT1_CLK_MUXMODE_15" line.long 0xDC "CTRL_CORE_PAD_VOUT1_DE," hexmask.long.word 0xDC 20.--31. 1. "RESERVED," newline bitfld.long 0xDC 19. "VOUT1_DE_SLEWCONTROL," "VOUT1_DE_SLEWCONTROL_0,VOUT1_DE_SLEWCONTROL_1" newline bitfld.long 0xDC 18. "VOUT1_DE_INPUTENABLE," "VOUT1_DE_INPUTENABLE_0,VOUT1_DE_INPUTENABLE_1" newline bitfld.long 0xDC 17. "VOUT1_DE_PULLTYPESELECT," "VOUT1_DE_PULLTYPESELECT_0,VOUT1_DE_PULLTYPESELECT_1" newline bitfld.long 0xDC 16. "VOUT1_DE_PULLUDENABLE," "VOUT1_DE_PULLUDENABLE_0,VOUT1_DE_PULLUDENABLE_1" newline hexmask.long.word 0xDC 4.--15. 1. "RESERVED," newline bitfld.long 0xDC 0.--3. "VOUT1_DE_MUXMODE," "VOUT1_DE_MUXMODE_0,VOUT1_DE_MUXMODE_1,VOUT1_DE_MUXMODE_2,?,VOUT1_DE_MUXMODE_4,?,?,?,?,?,?,?,?,?,VOUT1_DE_MUXMODE_14,VOUT1_DE_MUXMODE_15" line.long 0xE0 "CTRL_CORE_PAD_VOUT1_FLD," hexmask.long.word 0xE0 20.--31. 1. "RESERVED," newline bitfld.long 0xE0 19. "VOUT1_FLD_SLEWCONTROL," "VOUT1_FLD_SLEWCONTROL_0,VOUT1_FLD_SLEWCONTROL_1" newline bitfld.long 0xE0 18. "VOUT1_FLD_INPUTENABLE," "VOUT1_FLD_INPUTENABLE_0,VOUT1_FLD_INPUTENABLE_1" newline bitfld.long 0xE0 17. "VOUT1_FLD_PULLTYPESELECT," "VOUT1_FLD_PULLTYPESELECT_0,VOUT1_FLD_PULLTYPESELECT_1" newline bitfld.long 0xE0 16. "VOUT1_FLD_PULLUDENABLE," "VOUT1_FLD_PULLUDENABLE_0,VOUT1_FLD_PULLUDENABLE_1" newline hexmask.long.word 0xE0 4.--15. 1. "RESERVED," newline bitfld.long 0xE0 0.--3. "VOUT1_FLD_MUXMODE," "VOUT1_FLD_MUXMODE_0,VOUT1_FLD_MUXMODE_1,VOUT1_FLD_MUXMODE_2,?,VOUT1_FLD_MUXMODE_4,?,?,?,?,?,?,?,?,?,VOUT1_FLD_MUXMODE_14,VOUT1_FLD_MUXMODE_15" line.long 0xE4 "CTRL_CORE_PAD_VOUT1_HSYNC," hexmask.long.word 0xE4 20.--31. 1. "RESERVED," newline bitfld.long 0xE4 19. "VOUT1_HSYNC_SLEWCONTROL," "VOUT1_HSYNC_SLEWCONTROL_0,VOUT1_HSYNC_SLEWCONTROL_1" newline bitfld.long 0xE4 18. "VOUT1_HSYNC_INPUTENABLE," "VOUT1_HSYNC_INPUTENABLE_0,VOUT1_HSYNC_INPUTENABLE_1" newline bitfld.long 0xE4 17. "VOUT1_HSYNC_PULLTYPESELECT," "VOUT1_HSYNC_PULLTYPESELECT_0,VOUT1_HSYNC_PULLTYPESELECT_1" newline bitfld.long 0xE4 16. "VOUT1_HSYNC_PULLUDENABLE," "VOUT1_HSYNC_PULLUDENABLE_0,VOUT1_HSYNC_PULLUDENABLE_1" newline hexmask.long.word 0xE4 4.--15. 1. "RESERVED," newline bitfld.long 0xE4 0.--3. "VOUT1_HSYNC_MUXMODE," "VOUT1_HSYNC_MUXMODE_0,VOUT1_HSYNC_MUXMODE_1,VOUT1_HSYNC_MUXMODE_2,?,?,?,?,?,?,VOUT1_HSYNC_MUXMODE_9,?,?,?,?,VOUT1_HSYNC_MUXMODE_14,VOUT1_HSYNC_MUXMODE_15" line.long 0xE8 "CTRL_CORE_PAD_VOUT1_VSYNC," hexmask.long.word 0xE8 20.--31. 1. "RESERVED," newline bitfld.long 0xE8 19. "VOUT1_VSYNC_SLEWCONTROL," "VOUT1_VSYNC_SLEWCONTROL_0,VOUT1_VSYNC_SLEWCONTROL_1" newline bitfld.long 0xE8 18. "VOUT1_VSYNC_INPUTENABLE," "VOUT1_VSYNC_INPUTENABLE_0,VOUT1_VSYNC_INPUTENABLE_1" newline bitfld.long 0xE8 17. "VOUT1_VSYNC_PULLTYPESELECT," "VOUT1_VSYNC_PULLTYPESELECT_0,VOUT1_VSYNC_PULLTYPESELECT_1" newline bitfld.long 0xE8 16. "VOUT1_VSYNC_PULLUDENABLE," "VOUT1_VSYNC_PULLUDENABLE_0,VOUT1_VSYNC_PULLUDENABLE_1" newline hexmask.long.word 0xE8 4.--15. 1. "RESERVED," newline bitfld.long 0xE8 0.--3. "VOUT1_VSYNC_MUXMODE," "VOUT1_VSYNC_MUXMODE_0,VOUT1_VSYNC_MUXMODE_1,VOUT1_VSYNC_MUXMODE_2,?,?,?,?,?,?,VOUT1_VSYNC_MUXMODE_9,?,?,?,?,VOUT1_VSYNC_MUXMODE_14,VOUT1_VSYNC_MUXMODE_15" line.long 0xEC "CTRL_CORE_PAD_VOUT1_D0," hexmask.long.word 0xEC 20.--31. 1. "RESERVED," newline bitfld.long 0xEC 19. "VOUT1_D0_SLEWCONTROL," "VOUT1_D0_SLEWCONTROL_0,VOUT1_D0_SLEWCONTROL_1" newline bitfld.long 0xEC 18. "VOUT1_D0_INPUTENABLE," "VOUT1_D0_INPUTENABLE_0,VOUT1_D0_INPUTENABLE_1" newline bitfld.long 0xEC 17. "VOUT1_D0_PULLTYPESELECT," "VOUT1_D0_PULLTYPESELECT_0,VOUT1_D0_PULLTYPESELECT_1" newline bitfld.long 0xEC 16. "VOUT1_D0_PULLUDENABLE," "VOUT1_D0_PULLUDENABLE_0,VOUT1_D0_PULLUDENABLE_1" newline hexmask.long.word 0xEC 4.--15. 1. "RESERVED," newline bitfld.long 0xEC 0.--3. "VOUT1_D0_MUXMODE," "VOUT1_D0_MUXMODE_0,VOUT1_D0_MUXMODE_1,?,?,?,VOUT1_D0_MUXMODE_5,?,?,?,?,?,?,?,?,VOUT1_D0_MUXMODE_14,VOUT1_D0_MUXMODE_15" line.long 0xF0 "CTRL_CORE_PAD_VOUT1_D1," hexmask.long.word 0xF0 20.--31. 1. "RESERVED," newline bitfld.long 0xF0 19. "VOUT1_D1_SLEWCONTROL," "VOUT1_D1_SLEWCONTROL_0,VOUT1_D1_SLEWCONTROL_1" newline bitfld.long 0xF0 18. "VOUT1_D1_INPUTENABLE," "VOUT1_D1_INPUTENABLE_0,VOUT1_D1_INPUTENABLE_1" newline bitfld.long 0xF0 17. "VOUT1_D1_PULLTYPESELECT," "VOUT1_D1_PULLTYPESELECT_0,VOUT1_D1_PULLTYPESELECT_1" newline bitfld.long 0xF0 16. "VOUT1_D1_PULLUDENABLE," "VOUT1_D1_PULLUDENABLE_0,VOUT1_D1_PULLUDENABLE_1" newline hexmask.long.word 0xF0 4.--15. 1. "RESERVED," newline bitfld.long 0xF0 0.--3. "VOUT1_D1_MUXMODE," "VOUT1_D1_MUXMODE_0,VOUT1_D1_MUXMODE_1,?,?,?,VOUT1_D1_MUXMODE_5,?,?,?,?,?,?,?,?,VOUT1_D1_MUXMODE_14,VOUT1_D1_MUXMODE_15" line.long 0xF4 "CTRL_CORE_PAD_VOUT1_D2," hexmask.long.word 0xF4 20.--31. 1. "RESERVED," newline bitfld.long 0xF4 19. "VOUT1_D2_SLEWCONTROL," "VOUT1_D2_SLEWCONTROL_0,VOUT1_D2_SLEWCONTROL_1" newline bitfld.long 0xF4 18. "VOUT1_D2_INPUTENABLE," "VOUT1_D2_INPUTENABLE_0,VOUT1_D2_INPUTENABLE_1" newline bitfld.long 0xF4 17. "VOUT1_D2_PULLTYPESELECT," "VOUT1_D2_PULLTYPESELECT_0,VOUT1_D2_PULLTYPESELECT_1" newline bitfld.long 0xF4 16. "VOUT1_D2_PULLUDENABLE," "VOUT1_D2_PULLUDENABLE_0,VOUT1_D2_PULLUDENABLE_1" newline hexmask.long.word 0xF4 4.--15. 1. "RESERVED," newline bitfld.long 0xF4 0.--3. "VOUT1_D2_MUXMODE," "VOUT1_D2_MUXMODE_0,VOUT1_D2_MUXMODE_1,?,?,VOUT1_D2_MUXMODE_4,VOUT1_D2_MUXMODE_5,?,?,?,?,?,?,?,?,VOUT1_D2_MUXMODE_14,VOUT1_D2_MUXMODE_15" line.long 0xF8 "CTRL_CORE_PAD_VOUT1_D3," hexmask.long.word 0xF8 20.--31. 1. "RESERVED," newline bitfld.long 0xF8 19. "VOUT1_D3_SLEWCONTROL," "VOUT1_D3_SLEWCONTROL_0,VOUT1_D3_SLEWCONTROL_1" newline bitfld.long 0xF8 18. "VOUT1_D3_INPUTENABLE," "VOUT1_D3_INPUTENABLE_0,VOUT1_D3_INPUTENABLE_1" newline bitfld.long 0xF8 17. "VOUT1_D3_PULLTYPESELECT," "VOUT1_D3_PULLTYPESELECT_0,VOUT1_D3_PULLTYPESELECT_1" newline bitfld.long 0xF8 16. "VOUT1_D3_PULLUDENABLE," "VOUT1_D3_PULLUDENABLE_0,VOUT1_D3_PULLUDENABLE_1" newline hexmask.long.word 0xF8 4.--15. 1. "RESERVED," newline bitfld.long 0xF8 0.--3. "VOUT1_D3_MUXMODE," "VOUT1_D3_MUXMODE_0,VOUT1_D3_MUXMODE_1,?,?,VOUT1_D3_MUXMODE_4,VOUT1_D3_MUXMODE_5,?,?,?,?,?,?,?,?,VOUT1_D3_MUXMODE_14,VOUT1_D3_MUXMODE_15" line.long 0xFC "CTRL_CORE_PAD_VOUT1_D4," hexmask.long.word 0xFC 20.--31. 1. "RESERVED," newline bitfld.long 0xFC 19. "VOUT1_D4_SLEWCONTROL," "VOUT1_D4_SLEWCONTROL_0,VOUT1_D4_SLEWCONTROL_1" newline bitfld.long 0xFC 18. "VOUT1_D4_INPUTENABLE," "VOUT1_D4_INPUTENABLE_0,VOUT1_D4_INPUTENABLE_1" newline bitfld.long 0xFC 17. "VOUT1_D4_PULLTYPESELECT," "VOUT1_D4_PULLTYPESELECT_0,VOUT1_D4_PULLTYPESELECT_1" newline bitfld.long 0xFC 16. "VOUT1_D4_PULLUDENABLE," "VOUT1_D4_PULLUDENABLE_0,VOUT1_D4_PULLUDENABLE_1" newline hexmask.long.word 0xFC 4.--15. 1. "RESERVED," newline bitfld.long 0xFC 0.--3. "VOUT1_D4_MUXMODE," "VOUT1_D4_MUXMODE_0,VOUT1_D4_MUXMODE_1,?,?,VOUT1_D4_MUXMODE_4,VOUT1_D4_MUXMODE_5,?,?,?,?,?,?,?,?,VOUT1_D4_MUXMODE_14,VOUT1_D4_MUXMODE_15" line.long 0x100 "CTRL_CORE_PAD_VOUT1_D5," hexmask.long.word 0x100 20.--31. 1. "RESERVED," newline bitfld.long 0x100 19. "VOUT1_D5_SLEWCONTROL," "VOUT1_D5_SLEWCONTROL_0,VOUT1_D5_SLEWCONTROL_1" newline bitfld.long 0x100 18. "VOUT1_D5_INPUTENABLE," "VOUT1_D5_INPUTENABLE_0,VOUT1_D5_INPUTENABLE_1" newline bitfld.long 0x100 17. "VOUT1_D5_PULLTYPESELECT," "VOUT1_D5_PULLTYPESELECT_0,VOUT1_D5_PULLTYPESELECT_1" newline bitfld.long 0x100 16. "VOUT1_D5_PULLUDENABLE," "VOUT1_D5_PULLUDENABLE_0,VOUT1_D5_PULLUDENABLE_1" newline hexmask.long.word 0x100 4.--15. 1. "RESERVED," newline bitfld.long 0x100 0.--3. "VOUT1_D5_MUXMODE," "VOUT1_D5_MUXMODE_0,VOUT1_D5_MUXMODE_1,?,?,VOUT1_D5_MUXMODE_4,VOUT1_D5_MUXMODE_5,?,?,?,VOUT1_D5_MUXMODE_9,?,?,?,?,VOUT1_D5_MUXMODE_14,VOUT1_D5_MUXMODE_15" line.long 0x104 "CTRL_CORE_PAD_VOUT1_D6," hexmask.long.word 0x104 20.--31. 1. "RESERVED," newline bitfld.long 0x104 19. "VOUT1_D6_SLEWCONTROL," "VOUT1_D6_SLEWCONTROL_0,VOUT1_D6_SLEWCONTROL_1" newline bitfld.long 0x104 18. "VOUT1_D6_INPUTENABLE," "VOUT1_D6_INPUTENABLE_0,VOUT1_D6_INPUTENABLE_1" newline bitfld.long 0x104 17. "VOUT1_D6_PULLTYPESELECT," "VOUT1_D6_PULLTYPESELECT_0,VOUT1_D6_PULLTYPESELECT_1" newline bitfld.long 0x104 16. "VOUT1_D6_PULLUDENABLE," "VOUT1_D6_PULLUDENABLE_0,VOUT1_D6_PULLUDENABLE_1" newline hexmask.long.word 0x104 4.--15. 1. "RESERVED," newline bitfld.long 0x104 0.--3. "VOUT1_D6_MUXMODE," "VOUT1_D6_MUXMODE_0,VOUT1_D6_MUXMODE_1,?,?,VOUT1_D6_MUXMODE_4,VOUT1_D6_MUXMODE_5,VOUT1_D6_MUXMODE_6,?,?,VOUT1_D6_MUXMODE_9,?,?,?,?,VOUT1_D6_MUXMODE_14,VOUT1_D6_MUXMODE_15" line.long 0x108 "CTRL_CORE_PAD_VOUT1_D7," hexmask.long.word 0x108 20.--31. 1. "RESERVED," newline bitfld.long 0x108 19. "VOUT1_D7_SLEWCONTROL," "VOUT1_D7_SLEWCONTROL_0,VOUT1_D7_SLEWCONTROL_1" newline bitfld.long 0x108 18. "VOUT1_D7_INPUTENABLE," "VOUT1_D7_INPUTENABLE_0,VOUT1_D7_INPUTENABLE_1" newline bitfld.long 0x108 17. "VOUT1_D7_PULLTYPESELECT," "VOUT1_D7_PULLTYPESELECT_0,VOUT1_D7_PULLTYPESELECT_1" newline bitfld.long 0x108 16. "VOUT1_D7_PULLUDENABLE," "VOUT1_D7_PULLUDENABLE_0,VOUT1_D7_PULLUDENABLE_1" newline hexmask.long.word 0x108 4.--15. 1. "RESERVED," newline bitfld.long 0x108 0.--3. "VOUT1_D7_MUXMODE," "VOUT1_D7_MUXMODE_0,VOUT1_D7_MUXMODE_1,?,VOUT1_D7_MUXMODE_3,VOUT1_D7_MUXMODE_4,?,VOUT1_D7_MUXMODE_6,?,?,VOUT1_D7_MUXMODE_9,?,?,?,?,VOUT1_D7_MUXMODE_14,VOUT1_D7_MUXMODE_15" line.long 0x10C "CTRL_CORE_PAD_VOUT1_D8," hexmask.long.word 0x10C 20.--31. 1. "RESERVED," newline bitfld.long 0x10C 19. "VOUT1_D8_SLEWCONTROL," "VOUT1_D8_SLEWCONTROL_0,VOUT1_D8_SLEWCONTROL_1" newline bitfld.long 0x10C 18. "VOUT1_D8_INPUTENABLE," "VOUT1_D8_INPUTENABLE_0,VOUT1_D8_INPUTENABLE_1" newline bitfld.long 0x10C 17. "VOUT1_D8_PULLTYPESELECT," "VOUT1_D8_PULLTYPESELECT_0,VOUT1_D8_PULLTYPESELECT_1" newline bitfld.long 0x10C 16. "VOUT1_D8_PULLUDENABLE," "VOUT1_D8_PULLUDENABLE_0,VOUT1_D8_PULLUDENABLE_1" newline hexmask.long.word 0x10C 4.--15. 1. "RESERVED," newline bitfld.long 0x10C 0.--3. "VOUT1_D8_MUXMODE," "VOUT1_D8_MUXMODE_0,VOUT1_D8_MUXMODE_1,VOUT1_D8_MUXMODE_2,VOUT1_D8_MUXMODE_3,?,?,VOUT1_D8_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D8_MUXMODE_14,VOUT1_D8_MUXMODE_15" line.long 0x110 "CTRL_CORE_PAD_VOUT1_D9," hexmask.long.word 0x110 20.--31. 1. "RESERVED," newline bitfld.long 0x110 19. "VOUT1_D9_SLEWCONTROL," "VOUT1_D9_SLEWCONTROL_0,VOUT1_D9_SLEWCONTROL_1" newline bitfld.long 0x110 18. "VOUT1_D9_INPUTENABLE," "VOUT1_D9_INPUTENABLE_0,VOUT1_D9_INPUTENABLE_1" newline bitfld.long 0x110 17. "VOUT1_D9_PULLTYPESELECT," "VOUT1_D9_PULLTYPESELECT_0,VOUT1_D9_PULLTYPESELECT_1" newline bitfld.long 0x110 16. "VOUT1_D9_PULLUDENABLE," "VOUT1_D9_PULLUDENABLE_0,VOUT1_D9_PULLUDENABLE_1" newline hexmask.long.word 0x110 4.--15. 1. "RESERVED," newline bitfld.long 0x110 0.--3. "VOUT1_D9_MUXMODE," "VOUT1_D9_MUXMODE_0,VOUT1_D9_MUXMODE_1,VOUT1_D9_MUXMODE_2,VOUT1_D9_MUXMODE_3,?,?,VOUT1_D9_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D9_MUXMODE_14,VOUT1_D9_MUXMODE_15" line.long 0x114 "CTRL_CORE_PAD_VOUT1_D10," hexmask.long.word 0x114 20.--31. 1. "RESERVED," newline bitfld.long 0x114 19. "VOUT1_D10_SLEWCONTROL," "VOUT1_D10_SLEWCONTROL_0,VOUT1_D10_SLEWCONTROL_1" newline bitfld.long 0x114 18. "VOUT1_D10_INPUTENABLE," "VOUT1_D10_INPUTENABLE_0,VOUT1_D10_INPUTENABLE_1" newline bitfld.long 0x114 17. "VOUT1_D10_PULLTYPESELECT," "VOUT1_D10_PULLTYPESELECT_0,VOUT1_D10_PULLTYPESELECT_1" newline bitfld.long 0x114 16. "VOUT1_D10_PULLUDENABLE," "VOUT1_D10_PULLUDENABLE_0,VOUT1_D10_PULLUDENABLE_1" newline hexmask.long.word 0x114 4.--15. 1. "RESERVED," newline bitfld.long 0x114 0.--3. "VOUT1_D10_MUXMODE," "VOUT1_D10_MUXMODE_0,VOUT1_D10_MUXMODE_1,VOUT1_D10_MUXMODE_2,VOUT1_D10_MUXMODE_3,?,?,VOUT1_D10_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D10_MUXMODE_14,VOUT1_D10_MUXMODE_15" line.long 0x118 "CTRL_CORE_PAD_VOUT1_D11," hexmask.long.word 0x118 20.--31. 1. "RESERVED," newline bitfld.long 0x118 19. "VOUT1_D11_SLEWCONTROL," "VOUT1_D11_SLEWCONTROL_0,VOUT1_D11_SLEWCONTROL_1" newline bitfld.long 0x118 18. "VOUT1_D11_INPUTENABLE," "VOUT1_D11_INPUTENABLE_0,VOUT1_D11_INPUTENABLE_1" newline bitfld.long 0x118 17. "VOUT1_D11_PULLTYPESELECT," "VOUT1_D11_PULLTYPESELECT_0,VOUT1_D11_PULLTYPESELECT_1" newline bitfld.long 0x118 16. "VOUT1_D11_PULLUDENABLE," "VOUT1_D11_PULLUDENABLE_0,VOUT1_D11_PULLUDENABLE_1" newline hexmask.long.word 0x118 4.--15. 1. "RESERVED," newline bitfld.long 0x118 0.--3. "VOUT1_D11_MUXMODE," "VOUT1_D11_MUXMODE_0,VOUT1_D11_MUXMODE_1,VOUT1_D11_MUXMODE_2,VOUT1_D11_MUXMODE_3,?,?,VOUT1_D11_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D11_MUXMODE_14,VOUT1_D11_MUXMODE_15" line.long 0x11C "CTRL_CORE_PAD_VOUT1_D12," hexmask.long.word 0x11C 20.--31. 1. "RESERVED," newline bitfld.long 0x11C 19. "VOUT1_D12_SLEWCONTROL," "VOUT1_D12_SLEWCONTROL_0,VOUT1_D12_SLEWCONTROL_1" newline bitfld.long 0x11C 18. "VOUT1_D12_INPUTENABLE," "VOUT1_D12_INPUTENABLE_0,VOUT1_D12_INPUTENABLE_1" newline bitfld.long 0x11C 17. "VOUT1_D12_PULLTYPESELECT," "VOUT1_D12_PULLTYPESELECT_0,VOUT1_D12_PULLTYPESELECT_1" newline bitfld.long 0x11C 16. "VOUT1_D12_PULLUDENABLE," "VOUT1_D12_PULLUDENABLE_0,VOUT1_D12_PULLUDENABLE_1" newline hexmask.long.word 0x11C 4.--15. 1. "RESERVED," newline bitfld.long 0x11C 0.--3. "VOUT1_D12_MUXMODE," "VOUT1_D12_MUXMODE_0,VOUT1_D12_MUXMODE_1,VOUT1_D12_MUXMODE_2,VOUT1_D12_MUXMODE_3,?,?,VOUT1_D12_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D12_MUXMODE_14,VOUT1_D12_MUXMODE_15" line.long 0x120 "CTRL_CORE_PAD_VOUT1_D13," hexmask.long.word 0x120 20.--31. 1. "RESERVED," newline bitfld.long 0x120 19. "VOUT1_D13_SLEWCONTROL," "VOUT1_D13_SLEWCONTROL_0,VOUT1_D13_SLEWCONTROL_1" newline bitfld.long 0x120 18. "VOUT1_D13_INPUTENABLE," "VOUT1_D13_INPUTENABLE_0,VOUT1_D13_INPUTENABLE_1" newline bitfld.long 0x120 17. "VOUT1_D13_PULLTYPESELECT," "VOUT1_D13_PULLTYPESELECT_0,VOUT1_D13_PULLTYPESELECT_1" newline bitfld.long 0x120 16. "VOUT1_D13_PULLUDENABLE," "VOUT1_D13_PULLUDENABLE_0,VOUT1_D13_PULLUDENABLE_1" newline hexmask.long.word 0x120 4.--15. 1. "RESERVED," newline bitfld.long 0x120 0.--3. "VOUT1_D13_MUXMODE," "VOUT1_D13_MUXMODE_0,VOUT1_D13_MUXMODE_1,VOUT1_D13_MUXMODE_2,VOUT1_D13_MUXMODE_3,?,?,VOUT1_D13_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D13_MUXMODE_14,VOUT1_D13_MUXMODE_15" line.long 0x124 "CTRL_CORE_PAD_VOUT1_D14," hexmask.long.word 0x124 20.--31. 1. "RESERVED," newline bitfld.long 0x124 19. "VOUT1_D14_SLEWCONTROL," "VOUT1_D14_SLEWCONTROL_0,VOUT1_D14_SLEWCONTROL_1" newline bitfld.long 0x124 18. "VOUT1_D14_INPUTENABLE," "VOUT1_D14_INPUTENABLE_0,VOUT1_D14_INPUTENABLE_1" newline bitfld.long 0x124 17. "VOUT1_D14_PULLTYPESELECT," "VOUT1_D14_PULLTYPESELECT_0,VOUT1_D14_PULLTYPESELECT_1" newline bitfld.long 0x124 16. "VOUT1_D14_PULLUDENABLE," "VOUT1_D14_PULLUDENABLE_0,VOUT1_D14_PULLUDENABLE_1" newline hexmask.long.word 0x124 4.--15. 1. "RESERVED," newline bitfld.long 0x124 0.--3. "VOUT1_D14_MUXMODE," "VOUT1_D14_MUXMODE_0,VOUT1_D14_MUXMODE_1,VOUT1_D14_MUXMODE_2,VOUT1_D14_MUXMODE_3,?,?,VOUT1_D14_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D14_MUXMODE_14,VOUT1_D14_MUXMODE_15" line.long 0x128 "CTRL_CORE_PAD_VOUT1_D15," hexmask.long.word 0x128 20.--31. 1. "RESERVED," newline bitfld.long 0x128 19. "VOUT1_D15_SLEWCONTROL," "VOUT1_D15_SLEWCONTROL_0,VOUT1_D15_SLEWCONTROL_1" newline bitfld.long 0x128 18. "VOUT1_D15_INPUTENABLE," "VOUT1_D15_INPUTENABLE_0,VOUT1_D15_INPUTENABLE_1" newline bitfld.long 0x128 17. "VOUT1_D15_PULLTYPESELECT," "VOUT1_D15_PULLTYPESELECT_0,VOUT1_D15_PULLTYPESELECT_1" newline bitfld.long 0x128 16. "VOUT1_D15_PULLUDENABLE," "VOUT1_D15_PULLUDENABLE_0,VOUT1_D15_PULLUDENABLE_1" newline hexmask.long.word 0x128 4.--15. 1. "RESERVED," newline bitfld.long 0x128 0.--3. "VOUT1_D15_MUXMODE," "VOUT1_D15_MUXMODE_0,VOUT1_D15_MUXMODE_1,VOUT1_D15_MUXMODE_2,VOUT1_D15_MUXMODE_3,?,?,VOUT1_D15_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D15_MUXMODE_14,VOUT1_D15_MUXMODE_15" line.long 0x12C "CTRL_CORE_PAD_VOUT1_D16," hexmask.long.word 0x12C 20.--31. 1. "RESERVED," newline bitfld.long 0x12C 19. "VOUT1_D16_SLEWCONTROL," "VOUT1_D16_SLEWCONTROL_0,VOUT1_D16_SLEWCONTROL_1" newline bitfld.long 0x12C 18. "VOUT1_D16_INPUTENABLE," "VOUT1_D16_INPUTENABLE_0,VOUT1_D16_INPUTENABLE_1" newline bitfld.long 0x12C 17. "VOUT1_D16_PULLTYPESELECT," "VOUT1_D16_PULLTYPESELECT_0,VOUT1_D16_PULLTYPESELECT_1" newline bitfld.long 0x12C 16. "VOUT1_D16_PULLUDENABLE," "VOUT1_D16_PULLUDENABLE_0,VOUT1_D16_PULLUDENABLE_1" newline hexmask.long.word 0x12C 4.--15. 1. "RESERVED," newline bitfld.long 0x12C 0.--3. "VOUT1_D16_MUXMODE," "VOUT1_D16_MUXMODE_0,VOUT1_D16_MUXMODE_1,VOUT1_D16_MUXMODE_2,VOUT1_D16_MUXMODE_3,VOUT1_D16_MUXMODE_4,VOUT1_D16_MUXMODE_5,VOUT1_D16_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D16_MUXMODE_14,VOUT1_D16_MUXMODE_15" line.long 0x130 "CTRL_CORE_PAD_VOUT1_D17," hexmask.long.word 0x130 20.--31. 1. "RESERVED," newline bitfld.long 0x130 19. "VOUT1_D17_SLEWCONTROL," "VOUT1_D17_SLEWCONTROL_0,VOUT1_D17_SLEWCONTROL_1" newline bitfld.long 0x130 18. "VOUT1_D17_INPUTENABLE," "VOUT1_D17_INPUTENABLE_0,VOUT1_D17_INPUTENABLE_1" newline bitfld.long 0x130 17. "VOUT1_D17_PULLTYPESELECT," "VOUT1_D17_PULLTYPESELECT_0,VOUT1_D17_PULLTYPESELECT_1" newline bitfld.long 0x130 16. "VOUT1_D17_PULLUDENABLE," "VOUT1_D17_PULLUDENABLE_0,VOUT1_D17_PULLUDENABLE_1" newline hexmask.long.word 0x130 4.--15. 1. "RESERVED," newline bitfld.long 0x130 0.--3. "VOUT1_D17_MUXMODE," "VOUT1_D17_MUXMODE_0,?,VOUT1_D17_MUXMODE_2,VOUT1_D17_MUXMODE_3,VOUT1_D17_MUXMODE_4,VOUT1_D17_MUXMODE_5,VOUT1_D17_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D17_MUXMODE_14,VOUT1_D17_MUXMODE_15" line.long 0x134 "CTRL_CORE_PAD_VOUT1_D18," hexmask.long.word 0x134 20.--31. 1. "RESERVED," newline bitfld.long 0x134 19. "VOUT1_D18_SLEWCONTROL," "VOUT1_D18_SLEWCONTROL_0,VOUT1_D18_SLEWCONTROL_1" newline bitfld.long 0x134 18. "VOUT1_D18_INPUTENABLE," "VOUT1_D18_INPUTENABLE_0,VOUT1_D18_INPUTENABLE_1" newline bitfld.long 0x134 17. "VOUT1_D18_PULLTYPESELECT," "VOUT1_D18_PULLTYPESELECT_0,VOUT1_D18_PULLTYPESELECT_1" newline bitfld.long 0x134 16. "VOUT1_D18_PULLUDENABLE," "VOUT1_D18_PULLUDENABLE_0,VOUT1_D18_PULLUDENABLE_1" newline hexmask.long.word 0x134 4.--15. 1. "RESERVED," newline bitfld.long 0x134 0.--3. "VOUT1_D18_MUXMODE," "VOUT1_D18_MUXMODE_0,?,VOUT1_D18_MUXMODE_2,VOUT1_D18_MUXMODE_3,VOUT1_D18_MUXMODE_4,VOUT1_D18_MUXMODE_5,VOUT1_D18_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D18_MUXMODE_14,VOUT1_D18_MUXMODE_15" line.long 0x138 "CTRL_CORE_PAD_VOUT1_D19," hexmask.long.word 0x138 20.--31. 1. "RESERVED," newline bitfld.long 0x138 19. "VOUT1_D19_SLEWCONTROL," "VOUT1_D19_SLEWCONTROL_0,VOUT1_D19_SLEWCONTROL_1" newline bitfld.long 0x138 18. "VOUT1_D19_INPUTENABLE," "VOUT1_D19_INPUTENABLE_0,VOUT1_D19_INPUTENABLE_1" newline bitfld.long 0x138 17. "VOUT1_D19_PULLTYPESELECT," "VOUT1_D19_PULLTYPESELECT_0,VOUT1_D19_PULLTYPESELECT_1" newline bitfld.long 0x138 16. "VOUT1_D19_PULLUDENABLE," "VOUT1_D19_PULLUDENABLE_0,VOUT1_D19_PULLUDENABLE_1" newline hexmask.long.word 0x138 4.--15. 1. "RESERVED," newline bitfld.long 0x138 0.--3. "VOUT1_D19_MUXMODE," "VOUT1_D19_MUXMODE_0,?,VOUT1_D19_MUXMODE_2,VOUT1_D19_MUXMODE_3,VOUT1_D19_MUXMODE_4,VOUT1_D19_MUXMODE_5,VOUT1_D19_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D19_MUXMODE_14,VOUT1_D19_MUXMODE_15" line.long 0x13C "CTRL_CORE_PAD_VOUT1_D20," hexmask.long.word 0x13C 20.--31. 1. "RESERVED," newline bitfld.long 0x13C 19. "VOUT1_D20_SLEWCONTROL," "VOUT1_D20_SLEWCONTROL_0,VOUT1_D20_SLEWCONTROL_1" newline bitfld.long 0x13C 18. "VOUT1_D20_INPUTENABLE," "VOUT1_D20_INPUTENABLE_0,VOUT1_D20_INPUTENABLE_1" newline bitfld.long 0x13C 17. "VOUT1_D20_PULLTYPESELECT," "VOUT1_D20_PULLTYPESELECT_0,VOUT1_D20_PULLTYPESELECT_1" newline bitfld.long 0x13C 16. "VOUT1_D20_PULLUDENABLE," "VOUT1_D20_PULLUDENABLE_0,VOUT1_D20_PULLUDENABLE_1" newline hexmask.long.word 0x13C 4.--15. 1. "RESERVED," newline bitfld.long 0x13C 0.--3. "VOUT1_D20_MUXMODE," "VOUT1_D20_MUXMODE_0,?,VOUT1_D20_MUXMODE_2,VOUT1_D20_MUXMODE_3,VOUT1_D20_MUXMODE_4,VOUT1_D20_MUXMODE_5,VOUT1_D20_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D20_MUXMODE_14,VOUT1_D20_MUXMODE_15" line.long 0x140 "CTRL_CORE_PAD_VOUT1_D21," hexmask.long.word 0x140 20.--31. 1. "RESERVED," newline bitfld.long 0x140 19. "VOUT1_D21_SLEWCONTROL," "VOUT1_D21_SLEWCONTROL_0,VOUT1_D21_SLEWCONTROL_1" newline bitfld.long 0x140 18. "VOUT1_D21_INPUTENABLE," "VOUT1_D21_INPUTENABLE_0,VOUT1_D21_INPUTENABLE_1" newline bitfld.long 0x140 17. "VOUT1_D21_PULLTYPESELECT," "VOUT1_D21_PULLTYPESELECT_0,VOUT1_D21_PULLTYPESELECT_1" newline bitfld.long 0x140 16. "VOUT1_D21_PULLUDENABLE," "VOUT1_D21_PULLUDENABLE_0,VOUT1_D21_PULLUDENABLE_1" newline hexmask.long.word 0x140 4.--15. 1. "RESERVED," newline bitfld.long 0x140 0.--3. "VOUT1_D21_MUXMODE," "VOUT1_D21_MUXMODE_0,?,VOUT1_D21_MUXMODE_2,VOUT1_D21_MUXMODE_3,VOUT1_D21_MUXMODE_4,VOUT1_D21_MUXMODE_5,VOUT1_D21_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D21_MUXMODE_14,VOUT1_D21_MUXMODE_15" line.long 0x144 "CTRL_CORE_PAD_VOUT1_D22," hexmask.long.word 0x144 20.--31. 1. "RESERVED," newline bitfld.long 0x144 19. "VOUT1_D22_SLEWCONTROL," "VOUT1_D22_SLEWCONTROL_0,VOUT1_D22_SLEWCONTROL_1" newline bitfld.long 0x144 18. "VOUT1_D22_INPUTENABLE," "VOUT1_D22_INPUTENABLE_0,VOUT1_D22_INPUTENABLE_1" newline bitfld.long 0x144 17. "VOUT1_D22_PULLTYPESELECT," "VOUT1_D22_PULLTYPESELECT_0,VOUT1_D22_PULLTYPESELECT_1" newline bitfld.long 0x144 16. "VOUT1_D22_PULLUDENABLE," "VOUT1_D22_PULLUDENABLE_0,VOUT1_D22_PULLUDENABLE_1" newline hexmask.long.word 0x144 4.--15. 1. "RESERVED," newline bitfld.long 0x144 0.--3. "VOUT1_D22_MUXMODE," "VOUT1_D22_MUXMODE_0,?,VOUT1_D22_MUXMODE_2,VOUT1_D22_MUXMODE_3,VOUT1_D22_MUXMODE_4,VOUT1_D22_MUXMODE_5,VOUT1_D22_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D22_MUXMODE_14,VOUT1_D22_MUXMODE_15" line.long 0x148 "CTRL_CORE_PAD_VOUT1_D23," hexmask.long.word 0x148 20.--31. 1. "RESERVED," newline bitfld.long 0x148 19. "VOUT1_D23_SLEWCONTROL," "VOUT1_D23_SLEWCONTROL_0,VOUT1_D23_SLEWCONTROL_1" newline bitfld.long 0x148 18. "VOUT1_D23_INPUTENABLE," "VOUT1_D23_INPUTENABLE_0,VOUT1_D23_INPUTENABLE_1" newline bitfld.long 0x148 17. "VOUT1_D23_PULLTYPESELECT," "VOUT1_D23_PULLTYPESELECT_0,VOUT1_D23_PULLTYPESELECT_1" newline bitfld.long 0x148 16. "VOUT1_D23_PULLUDENABLE," "VOUT1_D23_PULLUDENABLE_0,VOUT1_D23_PULLUDENABLE_1" newline hexmask.long.word 0x148 4.--15. 1. "RESERVED," newline bitfld.long 0x148 0.--3. "VOUT1_D23_MUXMODE," "VOUT1_D23_MUXMODE_0,?,VOUT1_D23_MUXMODE_2,VOUT1_D23_MUXMODE_3,VOUT1_D23_MUXMODE_4,VOUT1_D23_MUXMODE_5,VOUT1_D23_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D23_MUXMODE_14,VOUT1_D23_MUXMODE_15" line.long 0x14C "CTRL_CORE_PAD_DCAN2_TX,SR1.0 Only" hexmask.long.word 0x14C 20.--31. 1. "RESERVED," newline bitfld.long 0x14C 19. "DCAN2_TX_SLEWCONTROL," "DCAN2_TX_SLEWCONTROL_0,DCAN2_TX_SLEWCONTROL_1" newline bitfld.long 0x14C 18. "DCAN2_TX_INPUTENABLE," "DCAN2_TX_INPUTENABLE_0,DCAN2_TX_INPUTENABLE_1" newline bitfld.long 0x14C 17. "DCAN2_TX_PULLTYPESELECT," "DCAN2_TX_PULLTYPESELECT_0,DCAN2_TX_PULLTYPESELECT_1" newline bitfld.long 0x14C 16. "DCAN2_TX_PULLUDENABLE," "DCAN2_TX_PULLUDENABLE_0,DCAN2_TX_PULLUDENABLE_1" newline hexmask.long.word 0x14C 4.--15. 1. "RESERVED," newline bitfld.long 0x14C 0.--3. "DCAN2_TX_MUXMODE," "DCAN2_TX_MUXMODE_0,DCAN2_TX_MUXMODE_1,DCAN2_TX_MUXMODE_2,DCAN2_TX_MUXMODE_3,DCAN2_TX_MUXMODE_4,DCAN2_TX_MUXMODE_5,DCAN2_TX_MUXMODE_6,DCAN2_TX_MUXMODE_7,DCAN2_TX_MUXMODE_8,?,?,?,?,?,DCAN2_TX_MUXMODE_14,DCAN2_TX_MUXMODE_15" group.long 0x154C++0x07 line.long 0x00 "CTRL_CORE_PAD_MCAN_TX,SR2.0 Only" hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline bitfld.long 0x00 19. "MCAN_TX_SLEWCONTROL," "MCAN_TX_SLEWCONTROL_0,MCAN_TX_SLEWCONTROL_1" newline bitfld.long 0x00 18. "MCAN_TX_INPUTENABLE," "MCAN_TX_INPUTENABLE_0,MCAN_TX_INPUTENABLE_1" newline bitfld.long 0x00 17. "MCAN_TX_PULLTYPESELECT," "MCAN_TX_PULLTYPESELECT_0,MCAN_TX_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "MCAN_TX_PULLUDENABLE," "MCAN_TX_PULLUDENABLE_0,MCAN_TX_PULLUDENABLE_1" newline hexmask.long.word 0x00 4.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "MCAN_TX_MUXMODE," "MCAN_TX_MUXMODE_0,MCAN_TX_MUXMODE_1,MCAN_TX_MUXMODE_2,MCAN_TX_MUXMODE_3,MCAN_TX_MUXMODE_4,MCAN_TX_MUXMODE_5,MCAN_TX_MUXMODE_6,MCAN_TX_MUXMODE_7,MCAN_TX_MUXMODE_8,?,?,?,?,?,MCAN_TX_MUXMODE_14,MCAN_TX_MUXMODE_15" line.long 0x04 "CTRL_CORE_PAD_DCAN2_RX,SR1.0 Only" hexmask.long.word 0x04 20.--31. 1. "RESERVED," newline bitfld.long 0x04 19. "DCAN2_RX_SLEWCONTROL," "DCAN2_RX_SLEWCONTROL_0,DCAN2_RX_SLEWCONTROL_1" newline bitfld.long 0x04 18. "DCAN2_RX_INPUTENABLE," "DCAN2_RX_INPUTENABLE_0,DCAN2_RX_INPUTENABLE_1" newline bitfld.long 0x04 17. "DCAN2_RX_PULLTYPESELECT," "DCAN2_RX_PULLTYPESELECT_0,DCAN2_RX_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "DCAN2_RX_PULLUDENABLE," "DCAN2_RX_PULLUDENABLE_0,DCAN2_RX_PULLUDENABLE_1" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 0.--3. "DCAN2_RX_MUXMODE," "DCAN2_RX_MUXMODE_0,DCAN2_RX_MUXMODE_1,DCAN2_RX_MUXMODE_2,DCAN2_RX_MUXMODE_3,DCAN2_RX_MUXMODE_4,DCAN2_RX_MUXMODE_5,?,DCAN2_RX_MUXMODE_7,?,?,?,?,?,?,DCAN2_RX_MUXMODE_14,DCAN2_RX_MUXMODE_15" group.long 0x1550++0x67 line.long 0x00 "CTRL_CORE_PAD_MCAN_RX,SR2.0 Only" hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline bitfld.long 0x00 19. "MCAN_RX_SLEWCONTROL," "MCAN_RX_SLEWCONTROL_0,MCAN_RX_SLEWCONTROL_1" newline bitfld.long 0x00 18. "MCAN_RX_INPUTENABLE," "MCAN_RX_INPUTENABLE_0,MCAN_RX_INPUTENABLE_1" newline bitfld.long 0x00 17. "MCAN_RX_PULLTYPESELECT," "MCAN_RX_PULLTYPESELECT_0,MCAN_RX_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "MCAN_RX_PULLUDENABLE," "MCAN_RX_PULLUDENABLE_0,MCAN_RX_PULLUDENABLE_1" newline hexmask.long.word 0x00 4.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "MCAN_RX_MUXMODE," "MCAN_RX_MUXMODE_0,MCAN_RX_MUXMODE_1,MCAN_RX_MUXMODE_2,MCAN_RX_MUXMODE_3,MCAN_RX_MUXMODE_4,MCAN_RX_MUXMODE_5,?,MCAN_RX_MUXMODE_7,?,?,?,?,?,?,MCAN_RX_MUXMODE_14,MCAN_RX_MUXMODE_15" line.long 0x04 "CTRL_CORE_PAD_MDIO_MCLK," hexmask.long.word 0x04 20.--31. 1. "RESERVED," newline bitfld.long 0x04 19. "MDIO_MCLK_SLEWCONTROL," "MDIO_MCLK_SLEWCONTROL_0,MDIO_MCLK_SLEWCONTROL_1" newline bitfld.long 0x04 18. "MDIO_MCLK_INPUTENABLE," "MDIO_MCLK_INPUTENABLE_0,MDIO_MCLK_INPUTENABLE_1" newline bitfld.long 0x04 17. "MDIO_MCLK_PULLTYPESELECT," "MDIO_MCLK_PULLTYPESELECT_0,MDIO_MCLK_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "MDIO_MCLK_PULLUDENABLE," "MDIO_MCLK_PULLUDENABLE_0,MDIO_MCLK_PULLUDENABLE_1" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 0.--3. "MDIO_MCLK_MUXMODE," "MDIO_MCLK_MUXMODE_0,?,?,?,MDIO_MCLK_MUXMODE_4,?,?,?,?,?,?,?,?,?,MDIO_MCLK_MUXMODE_14,MDIO_MCLK_MUXMODE_15" line.long 0x08 "CTRL_CORE_PAD_MDIO_D," hexmask.long.word 0x08 20.--31. 1. "RESERVED," newline bitfld.long 0x08 19. "MDIO_D_SLEWCONTROL," "MDIO_D_SLEWCONTROL_0,MDIO_D_SLEWCONTROL_1" newline bitfld.long 0x08 18. "MDIO_D_INPUTENABLE," "MDIO_D_INPUTENABLE_0,MDIO_D_INPUTENABLE_1" newline bitfld.long 0x08 17. "MDIO_D_PULLTYPESELECT," "MDIO_D_PULLTYPESELECT_0,MDIO_D_PULLTYPESELECT_1" newline bitfld.long 0x08 16. "MDIO_D_PULLUDENABLE," "MDIO_D_PULLUDENABLE_0,MDIO_D_PULLUDENABLE_1" newline hexmask.long.word 0x08 4.--15. 1. "RESERVED," newline bitfld.long 0x08 0.--3. "MDIO_D_MUXMODE," "MDIO_D_MUXMODE_0,?,?,?,MDIO_D_MUXMODE_4,MDIO_D_MUXMODE_5,?,?,?,?,?,?,?,?,MDIO_D_MUXMODE_14,MDIO_D_MUXMODE_15" line.long 0x0C "CTRL_CORE_PAD_RGMII0_TXC," hexmask.long.word 0x0C 20.--31. 1. "RESERVED," newline bitfld.long 0x0C 19. "RGMII0_TXC_SLEWCONTROL," "RGMII0_TXC_SLEWCONTROL_0,RGMII0_TXC_SLEWCONTROL_1" newline bitfld.long 0x0C 18. "RGMII0_TXC_INPUTENABLE," "RGMII0_TXC_INPUTENABLE_0,RGMII0_TXC_INPUTENABLE_1" newline bitfld.long 0x0C 17. "RGMII0_TXC_PULLTYPESELECT," "RGMII0_TXC_PULLTYPESELECT_0,RGMII0_TXC_PULLTYPESELECT_1" newline bitfld.long 0x0C 16. "RGMII0_TXC_PULLUDENABLE," "RGMII0_TXC_PULLUDENABLE_0,RGMII0_TXC_PULLUDENABLE_1" newline hexmask.long.word 0x0C 4.--15. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "RGMII0_TXC_MUXMODE," "RGMII0_TXC_MUXMODE_0,?,?,RGMII0_TXC_MUXMODE_3,RGMII0_TXC_MUXMODE_4,RGMII0_TXC_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_TXC_MUXMODE_14,RGMII0_TXC_MUXMODE_15" line.long 0x10 "CTRL_CORE_PAD_RGMII0_TXCTL," hexmask.long.word 0x10 20.--31. 1. "RESERVED," newline bitfld.long 0x10 19. "RGMII0_TXCTL_SLEWCONTROL," "RGMII0_TXCTL_SLEWCONTROL_0,RGMII0_TXCTL_SLEWCONTROL_1" newline bitfld.long 0x10 18. "RGMII0_TXCTL_INPUTENABLE," "RGMII0_TXCTL_INPUTENABLE_0,RGMII0_TXCTL_INPUTENABLE_1" newline bitfld.long 0x10 17. "RGMII0_TXCTL_PULLTYPESELECT," "RGMII0_TXCTL_PULLTYPESELECT_0,RGMII0_TXCTL_PULLTYPESELECT_1" newline bitfld.long 0x10 16. "RGMII0_TXCTL_PULLUDENABLE," "RGMII0_TXCTL_PULLUDENABLE_0,RGMII0_TXCTL_PULLUDENABLE_1" newline hexmask.long.word 0x10 4.--15. 1. "RESERVED," newline bitfld.long 0x10 0.--3. "RGMII0_TXCTL_MUXMODE," "RGMII0_TXCTL_MUXMODE_0,?,?,RGMII0_TXCTL_MUXMODE_3,RGMII0_TXCTL_MUXMODE_4,RGMII0_TXCTL_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_TXCTL_MUXMODE_14,RGMII0_TXCTL_MUXMODE_15" line.long 0x14 "CTRL_CORE_PAD_RGMII0_TXD3," hexmask.long.word 0x14 20.--31. 1. "RESERVED," newline bitfld.long 0x14 19. "RGMII0_TXD3_SLEWCONTROL," "RGMII0_TXD3_SLEWCONTROL_0,RGMII0_TXD3_SLEWCONTROL_1" newline bitfld.long 0x14 18. "RGMII0_TXD3_INPUTENABLE," "RGMII0_TXD3_INPUTENABLE_0,RGMII0_TXD3_INPUTENABLE_1" newline bitfld.long 0x14 17. "RGMII0_TXD3_PULLTYPESELECT," "RGMII0_TXD3_PULLTYPESELECT_0,RGMII0_TXD3_PULLTYPESELECT_1" newline bitfld.long 0x14 16. "RGMII0_TXD3_PULLUDENABLE," "RGMII0_TXD3_PULLUDENABLE_0,RGMII0_TXD3_PULLUDENABLE_1" newline hexmask.long.word 0x14 4.--15. 1. "RESERVED," newline bitfld.long 0x14 0.--3. "RGMII0_TXD3_MUXMODE," "RGMII0_TXD3_MUXMODE_0,?,?,?,?,RGMII0_TXD3_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_TXD3_MUXMODE_14,RGMII0_TXD3_MUXMODE_15" line.long 0x18 "CTRL_CORE_PAD_RGMII0_TXD2," hexmask.long.word 0x18 20.--31. 1. "RESERVED," newline bitfld.long 0x18 19. "RGMII0_TXD2_SLEWCONTROL," "RGMII0_TXD2_SLEWCONTROL_0,RGMII0_TXD2_SLEWCONTROL_1" newline bitfld.long 0x18 18. "RGMII0_TXD2_INPUTENABLE," "RGMII0_TXD2_INPUTENABLE_0,RGMII0_TXD2_INPUTENABLE_1" newline bitfld.long 0x18 17. "RGMII0_TXD2_PULLTYPESELECT," "RGMII0_TXD2_PULLTYPESELECT_0,RGMII0_TXD2_PULLTYPESELECT_1" newline bitfld.long 0x18 16. "RGMII0_TXD2_PULLUDENABLE," "RGMII0_TXD2_PULLUDENABLE_0,RGMII0_TXD2_PULLUDENABLE_1" newline hexmask.long.word 0x18 4.--15. 1. "RESERVED," newline bitfld.long 0x18 0.--3. "RGMII0_TXD2_MUXMODE," "RGMII0_TXD2_MUXMODE_0,?,?,RGMII0_TXD2_MUXMODE_3,?,RGMII0_TXD2_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_TXD2_MUXMODE_14,RGMII0_TXD2_MUXMODE_15" line.long 0x1C "CTRL_CORE_PAD_RGMII0_TXD1," hexmask.long.word 0x1C 20.--31. 1. "RESERVED," newline bitfld.long 0x1C 19. "RGMII0_TXD1_SLEWCONTROL," "RGMII0_TXD1_SLEWCONTROL_0,RGMII0_TXD1_SLEWCONTROL_1" newline bitfld.long 0x1C 18. "RGMII0_TXD1_INPUTENABLE," "RGMII0_TXD1_INPUTENABLE_0,RGMII0_TXD1_INPUTENABLE_1" newline bitfld.long 0x1C 17. "RGMII0_TXD1_PULLTYPESELECT," "RGMII0_TXD1_PULLTYPESELECT_0,RGMII0_TXD1_PULLTYPESELECT_1" newline bitfld.long 0x1C 16. "RGMII0_TXD1_PULLUDENABLE," "RGMII0_TXD1_PULLUDENABLE_0,RGMII0_TXD1_PULLUDENABLE_1" newline hexmask.long.word 0x1C 4.--15. 1. "RESERVED," newline bitfld.long 0x1C 0.--3. "RGMII0_TXD1_MUXMODE," "RGMII0_TXD1_MUXMODE_0,?,?,?,?,RGMII0_TXD1_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_TXD1_MUXMODE_14,RGMII0_TXD1_MUXMODE_15" line.long 0x20 "CTRL_CORE_PAD_RGMII0_TXD0," hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline bitfld.long 0x20 19. "RGMII0_TXD0_SLEWCONTROL," "RGMII0_TXD0_SLEWCONTROL_0,RGMII0_TXD0_SLEWCONTROL_1" newline bitfld.long 0x20 18. "RGMII0_TXD0_INPUTENABLE," "RGMII0_TXD0_INPUTENABLE_0,RGMII0_TXD0_INPUTENABLE_1" newline bitfld.long 0x20 17. "RGMII0_TXD0_PULLTYPESELECT," "RGMII0_TXD0_PULLTYPESELECT_0,RGMII0_TXD0_PULLTYPESELECT_1" newline bitfld.long 0x20 16. "RGMII0_TXD0_PULLUDENABLE," "RGMII0_TXD0_PULLUDENABLE_0,RGMII0_TXD0_PULLUDENABLE_1" newline hexmask.long.word 0x20 4.--15. 1. "RESERVED," newline bitfld.long 0x20 0.--3. "RGMII0_TXD0_MUXMODE," "RGMII0_TXD0_MUXMODE_0,?,?,?,?,RGMII0_TXD0_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_TXD0_MUXMODE_14,RGMII0_TXD0_MUXMODE_15" line.long 0x24 "CTRL_CORE_PAD_RGMII0_RXC," hexmask.long.word 0x24 20.--31. 1. "RESERVED," newline bitfld.long 0x24 19. "RGMII0_RXC_SLEWCONTROL," "RGMII0_RXC_SLEWCONTROL_0,RGMII0_RXC_SLEWCONTROL_1" newline bitfld.long 0x24 18. "RGMII0_RXC_INPUTENABLE," "RGMII0_RXC_INPUTENABLE_0,RGMII0_RXC_INPUTENABLE_1" newline bitfld.long 0x24 17. "RGMII0_RXC_PULLTYPESELECT," "RGMII0_RXC_PULLTYPESELECT_0,RGMII0_RXC_PULLTYPESELECT_1" newline bitfld.long 0x24 16. "RGMII0_RXC_PULLUDENABLE," "RGMII0_RXC_PULLUDENABLE_0,RGMII0_RXC_PULLUDENABLE_1" newline hexmask.long.word 0x24 4.--15. 1. "RESERVED," newline bitfld.long 0x24 0.--3. "RGMII0_RXC_MUXMODE," "RGMII0_RXC_MUXMODE_0,?,?,RGMII0_RXC_MUXMODE_3,?,RGMII0_RXC_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_RXC_MUXMODE_14,RGMII0_RXC_MUXMODE_15" line.long 0x28 "CTRL_CORE_PAD_RGMII0_RXCTL," hexmask.long.word 0x28 20.--31. 1. "RESERVED," newline bitfld.long 0x28 19. "RGMII0_RXCTL_SLEWCONTROL," "RGMII0_RXCTL_SLEWCONTROL_0,RGMII0_RXCTL_SLEWCONTROL_1" newline bitfld.long 0x28 18. "RGMII0_RXCTL_INPUTENABLE," "RGMII0_RXCTL_INPUTENABLE_0,RGMII0_RXCTL_INPUTENABLE_1" newline bitfld.long 0x28 17. "RGMII0_RXCTL_PULLTYPESELECT," "RGMII0_RXCTL_PULLTYPESELECT_0,RGMII0_RXCTL_PULLTYPESELECT_1" newline bitfld.long 0x28 16. "RGMII0_RXCTL_PULLUDENABLE," "RGMII0_RXCTL_PULLUDENABLE_0,RGMII0_RXCTL_PULLUDENABLE_1" newline hexmask.long.word 0x28 4.--15. 1. "RESERVED," newline bitfld.long 0x28 0.--3. "RGMII0_RXCTL_MUXMODE," "RGMII0_RXCTL_MUXMODE_0,?,?,RGMII0_RXCTL_MUXMODE_3,?,RGMII0_RXCTL_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_RXCTL_MUXMODE_14,RGMII0_RXCTL_MUXMODE_15" line.long 0x2C "CTRL_CORE_PAD_RGMII0_RXD3," hexmask.long.word 0x2C 20.--31. 1. "RESERVED," newline bitfld.long 0x2C 19. "RGMII0_RXD3_SLEWCONTROL," "RGMII0_RXD3_SLEWCONTROL_0,RGMII0_RXD3_SLEWCONTROL_1" newline bitfld.long 0x2C 18. "RGMII0_RXD3_INPUTENABLE," "RGMII0_RXD3_INPUTENABLE_0,RGMII0_RXD3_INPUTENABLE_1" newline bitfld.long 0x2C 17. "RGMII0_RXD3_PULLTYPESELECT," "RGMII0_RXD3_PULLTYPESELECT_0,RGMII0_RXD3_PULLTYPESELECT_1" newline bitfld.long 0x2C 16. "RGMII0_RXD3_PULLUDENABLE," "RGMII0_RXD3_PULLUDENABLE_0,RGMII0_RXD3_PULLUDENABLE_1" newline hexmask.long.word 0x2C 4.--15. 1. "RESERVED," newline bitfld.long 0x2C 0.--3. "RGMII0_RXD3_MUXMODE," "RGMII0_RXD3_MUXMODE_0,?,?,?,?,RGMII0_RXD3_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_RXD3_MUXMODE_14,RGMII0_RXD3_MUXMODE_15" line.long 0x30 "CTRL_CORE_PAD_RGMII0_RXD2," hexmask.long.word 0x30 20.--31. 1. "RESERVED," newline bitfld.long 0x30 19. "RGMII0_RXD2_SLEWCONTROL," "RGMII0_RXD2_SLEWCONTROL_0,RGMII0_RXD2_SLEWCONTROL_1" newline bitfld.long 0x30 18. "RGMII0_RXD2_INPUTENABLE," "RGMII0_RXD2_INPUTENABLE_0,RGMII0_RXD2_INPUTENABLE_1" newline bitfld.long 0x30 17. "RGMII0_RXD2_PULLTYPESELECT," "RGMII0_RXD2_PULLTYPESELECT_0,RGMII0_RXD2_PULLTYPESELECT_1" newline bitfld.long 0x30 16. "RGMII0_RXD2_PULLUDENABLE," "RGMII0_RXD2_PULLUDENABLE_0,RGMII0_RXD2_PULLUDENABLE_1" newline hexmask.long.word 0x30 4.--15. 1. "RESERVED," newline bitfld.long 0x30 0.--3. "RGMII0_RXD2_MUXMODE," "RGMII0_RXD2_MUXMODE_0,?,?,?,?,RGMII0_RXD2_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_RXD2_MUXMODE_14,RGMII0_RXD2_MUXMODE_15" line.long 0x34 "CTRL_CORE_PAD_RGMII0_RXD1," hexmask.long.word 0x34 20.--31. 1. "RESERVED," newline bitfld.long 0x34 19. "RGMII0_RXD1_SLEWCONTROL," "RGMII0_RXD1_SLEWCONTROL_0,RGMII0_RXD1_SLEWCONTROL_1" newline bitfld.long 0x34 18. "RGMII0_RXD1_INPUTENABLE," "RGMII0_RXD1_INPUTENABLE_0,RGMII0_RXD1_INPUTENABLE_1" newline bitfld.long 0x34 17. "RGMII0_RXD1_PULLTYPESELECT," "RGMII0_RXD1_PULLTYPESELECT_0,RGMII0_RXD1_PULLTYPESELECT_1" newline bitfld.long 0x34 16. "RGMII0_RXD1_PULLUDENABLE," "RGMII0_RXD1_PULLUDENABLE_0,RGMII0_RXD1_PULLUDENABLE_1" newline hexmask.long.word 0x34 4.--15. 1. "RESERVED," newline bitfld.long 0x34 0.--3. "RGMII0_RXD1_MUXMODE," "RGMII0_RXD1_MUXMODE_0,?,?,?,?,RGMII0_RXD1_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_RXD1_MUXMODE_14,RGMII0_RXD1_MUXMODE_15" line.long 0x38 "CTRL_CORE_PAD_RGMII0_RXD0," hexmask.long.word 0x38 20.--31. 1. "RESERVED," newline bitfld.long 0x38 19. "RGMII0_RXD0_SLEWCONTROL," "RGMII0_RXD0_SLEWCONTROL_0,RGMII0_RXD0_SLEWCONTROL_1" newline bitfld.long 0x38 18. "RGMII0_RXD0_INPUTENABLE," "RGMII0_RXD0_INPUTENABLE_0,RGMII0_RXD0_INPUTENABLE_1" newline bitfld.long 0x38 17. "RGMII0_RXD0_PULLTYPESELECT," "RGMII0_RXD0_PULLTYPESELECT_0,RGMII0_RXD0_PULLTYPESELECT_1" newline bitfld.long 0x38 16. "RGMII0_RXD0_PULLUDENABLE," "RGMII0_RXD0_PULLUDENABLE_0,RGMII0_RXD0_PULLUDENABLE_1" newline hexmask.long.word 0x38 4.--15. 1. "RESERVED," newline bitfld.long 0x38 0.--3. "RGMII0_RXD0_MUXMODE," "RGMII0_RXD0_MUXMODE_0,?,?,?,?,RGMII0_RXD0_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_RXD0_MUXMODE_14,RGMII0_RXD0_MUXMODE_15" line.long 0x3C "CTRL_CORE_PAD_XREF_CLK0," hexmask.long.word 0x3C 20.--31. 1. "RESERVED," newline bitfld.long 0x3C 19. "XREF_CLK0_SLEWCONTROL," "XREF_CLK0_SLEWCONTROL_0,XREF_CLK0_SLEWCONTROL_1" newline bitfld.long 0x3C 18. "XREF_CLK0_INPUTENABLE," "XREF_CLK0_INPUTENABLE_0,XREF_CLK0_INPUTENABLE_1" newline bitfld.long 0x3C 17. "XREF_CLK0_PULLTYPESELECT," "XREF_CLK0_PULLTYPESELECT_0,XREF_CLK0_PULLTYPESELECT_1" newline bitfld.long 0x3C 16. "XREF_CLK0_PULLUDENABLE," "XREF_CLK0_PULLUDENABLE_0,XREF_CLK0_PULLUDENABLE_1" newline hexmask.long.word 0x3C 4.--15. 1. "RESERVED," newline bitfld.long 0x3C 0.--3. "XREF_CLK0_MUXMODE," "XREF_CLK0_MUXMODE_0,XREF_CLK0_MUXMODE_1,?,?,XREF_CLK0_MUXMODE_4,XREF_CLK0_MUXMODE_5,XREF_CLK0_MUXMODE_6,XREF_CLK0_MUXMODE_7,?,?,?,?,?,?,XREF_CLK0_MUXMODE_14,XREF_CLK0_MUXMODE_15" line.long 0x40 "CTRL_CORE_PAD_SPI1_SCLK," hexmask.long.word 0x40 20.--31. 1. "RESERVED," newline bitfld.long 0x40 19. "SPI1_SCLK_SLEWCONTROL," "SPI1_SCLK_SLEWCONTROL_0,SPI1_SCLK_SLEWCONTROL_1" newline bitfld.long 0x40 18. "SPI1_SCLK_INPUTENABLE," "SPI1_SCLK_INPUTENABLE_0,SPI1_SCLK_INPUTENABLE_1" newline bitfld.long 0x40 17. "SPI1_SCLK_PULLTYPESELECT," "SPI1_SCLK_PULLTYPESELECT_0,SPI1_SCLK_PULLTYPESELECT_1" newline bitfld.long 0x40 16. "SPI1_SCLK_PULLUDENABLE," "SPI1_SCLK_PULLUDENABLE_0,SPI1_SCLK_PULLUDENABLE_1" newline hexmask.long.word 0x40 4.--15. 1. "RESERVED," newline bitfld.long 0x40 0.--3. "SPI1_SCLK_MUXMODE," "SPI1_SCLK_MUXMODE_0,SPI1_SCLK_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,SPI1_SCLK_MUXMODE_14,SPI1_SCLK_MUXMODE_15" line.long 0x44 "CTRL_CORE_PAD_SPI1_D1," hexmask.long.word 0x44 20.--31. 1. "RESERVED," newline bitfld.long 0x44 19. "SPI1_D1_SLEWCONTROL," "SPI1_D1_SLEWCONTROL_0,SPI1_D1_SLEWCONTROL_1" newline bitfld.long 0x44 18. "SPI1_D1_INPUTENABLE," "SPI1_D1_INPUTENABLE_0,SPI1_D1_INPUTENABLE_1" newline bitfld.long 0x44 17. "SPI1_D1_PULLTYPESELECT," "SPI1_D1_PULLTYPESELECT_0,SPI1_D1_PULLTYPESELECT_1" newline bitfld.long 0x44 16. "SPI1_D1_PULLUDENABLE," "SPI1_D1_PULLUDENABLE_0,SPI1_D1_PULLUDENABLE_1" newline hexmask.long.word 0x44 4.--15. 1. "RESERVED," newline bitfld.long 0x44 0.--3. "SPI1_D1_MUXMODE," "SPI1_D1_MUXMODE_0,SPI1_D1_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,SPI1_D1_MUXMODE_14,SPI1_D1_MUXMODE_15" line.long 0x48 "CTRL_CORE_PAD_SPI1_D0," hexmask.long.word 0x48 20.--31. 1. "RESERVED," newline bitfld.long 0x48 19. "SPI1_D0_SLEWCONTROL," "SPI1_D0_SLEWCONTROL_0,SPI1_D0_SLEWCONTROL_1" newline bitfld.long 0x48 18. "SPI1_D0_INPUTENABLE," "SPI1_D0_INPUTENABLE_0,SPI1_D0_INPUTENABLE_1" newline bitfld.long 0x48 17. "SPI1_D0_PULLTYPESELECT," "SPI1_D0_PULLTYPESELECT_0,SPI1_D0_PULLTYPESELECT_1" newline bitfld.long 0x48 16. "SPI1_D0_PULLUDENABLE," "SPI1_D0_PULLUDENABLE_0,SPI1_D0_PULLUDENABLE_1" newline hexmask.long.word 0x48 4.--15. 1. "RESERVED," newline bitfld.long 0x48 0.--3. "SPI1_D0_MUXMODE," "SPI1_D0_MUXMODE_0,SPI1_D0_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,SPI1_D0_MUXMODE_14,SPI1_D0_MUXMODE_15" line.long 0x4C "CTRL_CORE_PAD_SPI1_CS0," hexmask.long.word 0x4C 20.--31. 1. "RESERVED," newline bitfld.long 0x4C 19. "SPI1_CS0_SLEWCONTROL," "SPI1_CS0_SLEWCONTROL_0,SPI1_CS0_SLEWCONTROL_1" newline bitfld.long 0x4C 18. "SPI1_CS0_INPUTENABLE," "SPI1_CS0_INPUTENABLE_0,SPI1_CS0_INPUTENABLE_1" newline bitfld.long 0x4C 17. "SPI1_CS0_PULLTYPESELECT," "SPI1_CS0_PULLTYPESELECT_0,SPI1_CS0_PULLTYPESELECT_1" newline bitfld.long 0x4C 16. "SPI1_CS0_PULLUDENABLE," "SPI1_CS0_PULLUDENABLE_0,SPI1_CS0_PULLUDENABLE_1" newline hexmask.long.word 0x4C 4.--15. 1. "RESERVED," newline bitfld.long 0x4C 0.--3. "SPI1_CS0_MUXMODE," "SPI1_CS0_MUXMODE_0,SPI1_CS0_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,SPI1_CS0_MUXMODE_14,SPI1_CS0_MUXMODE_15" line.long 0x50 "CTRL_CORE_PAD_SPI1_CS1," hexmask.long.word 0x50 20.--31. 1. "RESERVED," newline bitfld.long 0x50 19. "SPI1_CS1_SLEWCONTROL," "SPI1_CS1_SLEWCONTROL_0,SPI1_CS1_SLEWCONTROL_1" newline bitfld.long 0x50 18. "SPI1_CS1_INPUTENABLE," "SPI1_CS1_INPUTENABLE_0,SPI1_CS1_INPUTENABLE_1" newline bitfld.long 0x50 17. "SPI1_CS1_PULLTYPESELECT," "SPI1_CS1_PULLTYPESELECT_0,SPI1_CS1_PULLTYPESELECT_1" newline bitfld.long 0x50 16. "SPI1_CS1_PULLUDENABLE," "SPI1_CS1_PULLUDENABLE_0,SPI1_CS1_PULLUDENABLE_1" newline hexmask.long.word 0x50 4.--15. 1. "RESERVED," newline bitfld.long 0x50 0.--3. "SPI1_CS1_MUXMODE," "SPI1_CS1_MUXMODE_0,SPI1_CS1_MUXMODE_1,?,?,SPI1_CS1_MUXMODE_4,?,?,SPI1_CS1_MUXMODE_7,?,?,?,?,?,?,SPI1_CS1_MUXMODE_14,SPI1_CS1_MUXMODE_15" line.long 0x54 "CTRL_CORE_PAD_SPI2_SCLK," hexmask.long.word 0x54 20.--31. 1. "RESERVED," newline bitfld.long 0x54 19. "SPI2_SCLK_SLEWCONTROL," "SPI2_SCLK_SLEWCONTROL_0,SPI2_SCLK_SLEWCONTROL_1" newline bitfld.long 0x54 18. "SPI2_SCLK_INPUTENABLE," "SPI2_SCLK_INPUTENABLE_0,SPI2_SCLK_INPUTENABLE_1" newline bitfld.long 0x54 17. "SPI2_SCLK_PULLTYPESELECT," "SPI2_SCLK_PULLTYPESELECT_0,SPI2_SCLK_PULLTYPESELECT_1" newline bitfld.long 0x54 16. "SPI2_SCLK_PULLUDENABLE," "SPI2_SCLK_PULLUDENABLE_0,SPI2_SCLK_PULLUDENABLE_1" newline hexmask.long.word 0x54 4.--15. 1. "RESERVED," newline bitfld.long 0x54 0.--3. "SPI2_SCLK_MUXMODE," "SPI2_SCLK_MUXMODE_0,SPI2_SCLK_MUXMODE_1,SPI2_SCLK_MUXMODE_2,SPI2_SCLK_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,SPI2_SCLK_MUXMODE_14,SPI2_SCLK_MUXMODE_15" line.long 0x58 "CTRL_CORE_PAD_SPI2_D1," hexmask.long.word 0x58 20.--31. 1. "RESERVED," newline bitfld.long 0x58 19. "SPI2_D1_SLEWCONTROL," "SPI2_D1_SLEWCONTROL_0,SPI2_D1_SLEWCONTROL_1" newline bitfld.long 0x58 18. "SPI2_D1_INPUTENABLE," "SPI2_D1_INPUTENABLE_0,SPI2_D1_INPUTENABLE_1" newline bitfld.long 0x58 17. "SPI2_D1_PULLTYPESELECT," "SPI2_D1_PULLTYPESELECT_0,SPI2_D1_PULLTYPESELECT_1" newline bitfld.long 0x58 16. "SPI2_D1_PULLUDENABLE," "SPI2_D1_PULLUDENABLE_0,SPI2_D1_PULLUDENABLE_1" newline hexmask.long.word 0x58 4.--15. 1. "RESERVED," newline bitfld.long 0x58 0.--3. "SPI2_D1_MUXMODE," "SPI2_D1_MUXMODE_0,SPI2_D1_MUXMODE_1,?,SPI2_D1_MUXMODE_3,?,?,?,SPI2_D1_MUXMODE_7,?,?,?,?,?,?,SPI2_D1_MUXMODE_14,SPI2_D1_MUXMODE_15" line.long 0x5C "CTRL_CORE_PAD_SPI2_D0," hexmask.long.word 0x5C 20.--31. 1. "RESERVED," newline bitfld.long 0x5C 19. "SPI2_D0_SLEWCONTROL," "SPI2_D0_SLEWCONTROL_0,SPI2_D0_SLEWCONTROL_1" newline bitfld.long 0x5C 18. "SPI2_D0_INPUTENABLE," "SPI2_D0_INPUTENABLE_0,SPI2_D0_INPUTENABLE_1" newline bitfld.long 0x5C 17. "SPI2_D0_PULLTYPESELECT," "SPI2_D0_PULLTYPESELECT_0,SPI2_D0_PULLTYPESELECT_1" newline bitfld.long 0x5C 16. "SPI2_D0_PULLUDENABLE," "SPI2_D0_PULLUDENABLE_0,SPI2_D0_PULLUDENABLE_1" newline hexmask.long.word 0x5C 4.--15. 1. "RESERVED," newline bitfld.long 0x5C 0.--3. "SPI2_D0_MUXMODE," "SPI2_D0_MUXMODE_0,SPI2_D0_MUXMODE_1,?,SPI2_D0_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,SPI2_D0_MUXMODE_14,SPI2_D0_MUXMODE_15" line.long 0x60 "CTRL_CORE_PAD_SPI2_CS0," hexmask.long.word 0x60 20.--31. 1. "RESERVED," newline bitfld.long 0x60 19. "SPI2_CS0_SLEWCONTROL," "SPI2_CS0_SLEWCONTROL_0,SPI2_CS0_SLEWCONTROL_1" newline bitfld.long 0x60 18. "SPI2_CS0_INPUTENABLE," "SPI2_CS0_INPUTENABLE_0,SPI2_CS0_INPUTENABLE_1" newline bitfld.long 0x60 17. "SPI2_CS0_PULLTYPESELECT," "SPI2_CS0_PULLTYPESELECT_0,SPI2_CS0_PULLTYPESELECT_1" newline bitfld.long 0x60 16. "SPI2_CS0_PULLUDENABLE," "SPI2_CS0_PULLUDENABLE_0,SPI2_CS0_PULLUDENABLE_1" newline hexmask.long.word 0x60 4.--15. 1. "RESERVED," newline bitfld.long 0x60 0.--3. "SPI2_CS0_MUXMODE," "SPI2_CS0_MUXMODE_0,SPI2_CS0_MUXMODE_1,SPI2_CS0_MUXMODE_2,SPI2_CS0_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,SPI2_CS0_MUXMODE_14,SPI2_CS0_MUXMODE_15" line.long 0x64 "CTRL_CORE_PAD_DCAN1_TX,SR1.0 Only" hexmask.long.word 0x64 20.--31. 1. "RESERVED," newline bitfld.long 0x64 19. "DCAN1_TX_SLEWCONTROL," "DCAN1_TX_SLEWCONTROL_0,DCAN1_TX_SLEWCONTROL_1" newline bitfld.long 0x64 18. "DCAN1_TX_INPUTENABLE," "DCAN1_TX_INPUTENABLE_0,DCAN1_TX_INPUTENABLE_1" newline bitfld.long 0x64 17. "DCAN1_TX_PULLTYPESELECT," "DCAN1_TX_PULLTYPESELECT_0,DCAN1_TX_PULLTYPESELECT_1" newline bitfld.long 0x64 16. "DCAN1_TX_PULLUDENABLE," "DCAN1_TX_PULLUDENABLE_0,DCAN1_TX_PULLUDENABLE_1" newline hexmask.long.word 0x64 4.--15. 1. "RESERVED," newline bitfld.long 0x64 0.--3. "DCAN1_TX_MUXMODE," "DCAN1_TX_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,DCAN1_TX_MUXMODE_14,DCAN1_TX_MUXMODE_15" group.long 0x15B4++0x07 line.long 0x00 "CTRL_CORE_PAD_DCAN_TX,SR2.0 Only" hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline bitfld.long 0x00 19. "DCAN_TX_SLEWCONTROL," "DCAN_TX_SLEWCONTROL_0,DCAN_TX_SLEWCONTROL_1" newline bitfld.long 0x00 18. "DCAN_TX_INPUTENABLE," "DCAN_TX_INPUTENABLE_0,DCAN_TX_INPUTENABLE_1" newline bitfld.long 0x00 17. "DCAN_TX_PULLTYPESELECT," "DCAN_TX_PULLTYPESELECT_0,DCAN_TX_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "DCAN_TX_PULLUDENABLE," "DCAN_TX_PULLUDENABLE_0,DCAN_TX_PULLUDENABLE_1" newline hexmask.long.word 0x00 4.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "DCAN_TX_MUXMODE," "DCAN_TX_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,DCAN_TX_MUXMODE_14,DCAN_TX_MUXMODE_15" line.long 0x04 "CTRL_CORE_PAD_DCAN1_RX,SR1.0 Only" hexmask.long.word 0x04 20.--31. 1. "RESERVED," newline bitfld.long 0x04 19. "DCAN1_RX_SLEWCONTROL," "DCAN1_RX_SLEWCONTROL_0,DCAN1_RX_SLEWCONTROL_1" newline bitfld.long 0x04 18. "DCAN1_RX_INPUTENABLE," "DCAN1_RX_INPUTENABLE_0,DCAN1_RX_INPUTENABLE_1" newline bitfld.long 0x04 17. "DCAN1_RX_PULLTYPESELECT," "DCAN1_RX_PULLTYPESELECT_0,DCAN1_RX_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "DCAN1_RX_PULLUDENABLE," "DCAN1_RX_PULLUDENABLE_0,DCAN1_RX_PULLUDENABLE_1" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 0.--3. "DCAN1_RX_MUXMODE," "DCAN1_RX_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,DCAN1_RX_MUXMODE_14,DCAN1_RX_MUXMODE_15" group.long 0x15B8++0x5F line.long 0x00 "CTRL_CORE_PAD_DCAN_RX,SR2.0 Only" hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline bitfld.long 0x00 19. "DCAN_RX_SLEWCONTROL," "DCAN_RX_SLEWCONTROL_0,DCAN_RX_SLEWCONTROL_1" newline bitfld.long 0x00 18. "DCAN_RX_INPUTENABLE," "DCAN_RX_INPUTENABLE_0,DCAN_RX_INPUTENABLE_1" newline bitfld.long 0x00 17. "DCAN_RX_PULLTYPESELECT," "DCAN_RX_PULLTYPESELECT_0,DCAN_RX_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "DCAN_RX_PULLUDENABLE," "DCAN_RX_PULLUDENABLE_0,DCAN_RX_PULLUDENABLE_1" newline hexmask.long.word 0x00 4.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "DCAN_RX_MUXMODE," "DCAN_RX_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,DCAN_RX_MUXMODE_14,DCAN_RX_MUXMODE_15" line.long 0x04 "CTRL_CORE_PAD_UART1_RXD," hexmask.long.word 0x04 20.--31. 1. "RESERVED," newline bitfld.long 0x04 19. "UART1_RXD_SLEWCONTROL," "UART1_RXD_SLEWCONTROL_0,UART1_RXD_SLEWCONTROL_1" newline bitfld.long 0x04 18. "UART1_RXD_INPUTENABLE," "UART1_RXD_INPUTENABLE_0,UART1_RXD_INPUTENABLE_1" newline bitfld.long 0x04 17. "UART1_RXD_PULLTYPESELECT," "UART1_RXD_PULLTYPESELECT_0,UART1_RXD_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "UART1_RXD_PULLUDENABLE," "UART1_RXD_PULLUDENABLE_0,UART1_RXD_PULLUDENABLE_1" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 0.--3. "UART1_RXD_MUXMODE," "UART1_RXD_MUXMODE_0,?,?,?,UART1_RXD_MUXMODE_4,UART1_RXD_MUXMODE_5,?,?,?,?,UART1_RXD_MUXMODE_10,?,UART1_RXD_MUXMODE_12,?,UART1_RXD_MUXMODE_14,UART1_RXD_MUXMODE_15" line.long 0x08 "CTRL_CORE_PAD_UART1_TXD," hexmask.long.word 0x08 20.--31. 1. "RESERVED," newline bitfld.long 0x08 19. "UART1_TXD_SLEWCONTROL," "UART1_TXD_SLEWCONTROL_0,UART1_TXD_SLEWCONTROL_1" newline bitfld.long 0x08 18. "UART1_TXD_INPUTENABLE," "UART1_TXD_INPUTENABLE_0,UART1_TXD_INPUTENABLE_1" newline bitfld.long 0x08 17. "UART1_TXD_PULLTYPESELECT," "UART1_TXD_PULLTYPESELECT_0,UART1_TXD_PULLTYPESELECT_1" newline bitfld.long 0x08 16. "UART1_TXD_PULLUDENABLE," "UART1_TXD_PULLUDENABLE_0,UART1_TXD_PULLUDENABLE_1" newline hexmask.long.word 0x08 4.--15. 1. "RESERVED," newline bitfld.long 0x08 0.--3. "UART1_TXD_MUXMODE," "UART1_TXD_MUXMODE_0,?,?,?,UART1_TXD_MUXMODE_4,?,?,?,?,?,UART1_TXD_MUXMODE_10,?,UART1_TXD_MUXMODE_12,?,UART1_TXD_MUXMODE_14,UART1_TXD_MUXMODE_15" line.long 0x0C "CTRL_CORE_PAD_UART1_CTSN," hexmask.long.word 0x0C 20.--31. 1. "RESERVED," newline bitfld.long 0x0C 19. "UART1_CTSN_SLEWCONTROL," "UART1_CTSN_SLEWCONTROL_0,UART1_CTSN_SLEWCONTROL_1" newline bitfld.long 0x0C 18. "UART1_CTSN_INPUTENABLE," "UART1_CTSN_INPUTENABLE_0,UART1_CTSN_INPUTENABLE_1" newline bitfld.long 0x0C 17. "UART1_CTSN_PULLTYPESELECT," "UART1_CTSN_PULLTYPESELECT_0,UART1_CTSN_PULLTYPESELECT_1" newline bitfld.long 0x0C 16. "UART1_CTSN_PULLUDENABLE," "UART1_CTSN_PULLUDENABLE_0,UART1_CTSN_PULLUDENABLE_1" newline hexmask.long.word 0x0C 4.--15. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "UART1_CTSN_MUXMODE," "UART1_CTSN_MUXMODE_0,UART1_CTSN_MUXMODE_1,UART1_CTSN_MUXMODE_2,UART1_CTSN_MUXMODE_3,UART1_CTSN_MUXMODE_4,UART1_CTSN_MUXMODE_5,UART1_CTSN_MUXMODE_6,UART1_CTSN_MUXMODE_7,UART1_CTSN_MUXMODE_8,UART1_CTSN_MUXMODE_9,UART1_CTSN_MUXMODE_10,UART1_CTSN_MUXMODE_11,UART1_CTSN_MUXMODE_12,?,UART1_CTSN_MUXMODE_14,UART1_CTSN_MUXMODE_15" line.long 0x10 "CTRL_CORE_PAD_UART1_RTSN," hexmask.long.word 0x10 20.--31. 1. "RESERVED," newline bitfld.long 0x10 19. "UART1_RTSN_SLEWCONTROL," "UART1_RTSN_SLEWCONTROL_0,UART1_RTSN_SLEWCONTROL_1" newline bitfld.long 0x10 18. "UART1_RTSN_INPUTENABLE," "UART1_RTSN_INPUTENABLE_0,UART1_RTSN_INPUTENABLE_1" newline bitfld.long 0x10 17. "UART1_RTSN_PULLTYPESELECT," "UART1_RTSN_PULLTYPESELECT_0,UART1_RTSN_PULLTYPESELECT_1" newline bitfld.long 0x10 16. "UART1_RTSN_PULLUDENABLE," "UART1_RTSN_PULLUDENABLE_0,UART1_RTSN_PULLUDENABLE_1" newline hexmask.long.word 0x10 4.--15. 1. "RESERVED," newline bitfld.long 0x10 0.--3. "UART1_RTSN_MUXMODE," "UART1_RTSN_MUXMODE_0,?,UART1_RTSN_MUXMODE_2,UART1_RTSN_MUXMODE_3,UART1_RTSN_MUXMODE_4,UART1_RTSN_MUXMODE_5,UART1_RTSN_MUXMODE_6,UART1_RTSN_MUXMODE_7,UART1_RTSN_MUXMODE_8,UART1_RTSN_MUXMODE_9,UART1_RTSN_MUXMODE_10,?,UART1_RTSN_MUXMODE_12,?,UART1_RTSN_MUXMODE_14,UART1_RTSN_MUXMODE_15" line.long 0x14 "CTRL_CORE_PAD_UART2_RXD," hexmask.long.word 0x14 20.--31. 1. "RESERVED," newline bitfld.long 0x14 19. "UART2_RXD_SLEWCONTROL," "UART2_RXD_SLEWCONTROL_0,UART2_RXD_SLEWCONTROL_1" newline bitfld.long 0x14 18. "UART2_RXD_INPUTENABLE," "UART2_RXD_INPUTENABLE_0,UART2_RXD_INPUTENABLE_1" newline bitfld.long 0x14 17. "UART2_RXD_PULLTYPESELECT," "UART2_RXD_PULLTYPESELECT_0,UART2_RXD_PULLTYPESELECT_1" newline bitfld.long 0x14 16. "UART2_RXD_PULLUDENABLE," "UART2_RXD_PULLUDENABLE_0,UART2_RXD_PULLUDENABLE_1" newline hexmask.long.word 0x14 4.--15. 1. "RESERVED," newline bitfld.long 0x14 0.--3. "UART2_RXD_MUXMODE," "UART2_RXD_MUXMODE_0,?,?,?,UART2_RXD_MUXMODE_4,?,UART2_RXD_MUXMODE_6,UART2_RXD_MUXMODE_7,?,?,UART2_RXD_MUXMODE_10,UART2_RXD_MUXMODE_11,UART2_RXD_MUXMODE_12,?,UART2_RXD_MUXMODE_14,UART2_RXD_MUXMODE_15" line.long 0x18 "CTRL_CORE_PAD_UART2_TXD," hexmask.long.word 0x18 20.--31. 1. "RESERVED," newline bitfld.long 0x18 19. "UART2_TXD_SLEWCONTROL," "UART2_TXD_SLEWCONTROL_0,UART2_TXD_SLEWCONTROL_1" newline bitfld.long 0x18 18. "UART2_TXD_INPUTENABLE," "UART2_TXD_INPUTENABLE_0,UART2_TXD_INPUTENABLE_1" newline bitfld.long 0x18 17. "UART2_TXD_PULLTYPESELECT," "UART2_TXD_PULLTYPESELECT_0,UART2_TXD_PULLTYPESELECT_1" newline bitfld.long 0x18 16. "UART2_TXD_PULLUDENABLE," "UART2_TXD_PULLUDENABLE_0,UART2_TXD_PULLUDENABLE_1" newline hexmask.long.word 0x18 4.--15. 1. "RESERVED," newline bitfld.long 0x18 0.--3. "UART2_TXD_MUXMODE," "UART2_TXD_MUXMODE_0,?,?,?,UART2_TXD_MUXMODE_4,?,UART2_TXD_MUXMODE_6,UART2_TXD_MUXMODE_7,?,?,?,UART2_TXD_MUXMODE_11,UART2_TXD_MUXMODE_12,?,UART2_TXD_MUXMODE_14,UART2_TXD_MUXMODE_15" line.long 0x1C "CTRL_CORE_PAD_UART2_CTSN," hexmask.long.word 0x1C 20.--31. 1. "RESERVED," newline bitfld.long 0x1C 19. "UART2_CTSN_SLEWCONTROL," "UART2_CTSN_SLEWCONTROL_0,UART2_CTSN_SLEWCONTROL_1" newline bitfld.long 0x1C 18. "UART2_CTSN_INPUTENABLE," "UART2_CTSN_INPUTENABLE_0,UART2_CTSN_INPUTENABLE_1" newline bitfld.long 0x1C 17. "UART2_CTSN_PULLTYPESELECT," "UART2_CTSN_PULLTYPESELECT_0,UART2_CTSN_PULLTYPESELECT_1" newline bitfld.long 0x1C 16. "UART2_CTSN_PULLUDENABLE," "UART2_CTSN_PULLUDENABLE_0,UART2_CTSN_PULLUDENABLE_1" newline hexmask.long.word 0x1C 4.--15. 1. "RESERVED," newline bitfld.long 0x1C 0.--3. "UART2_CTSN_MUXMODE," "UART2_CTSN_MUXMODE_0,?,UART2_CTSN_MUXMODE_2,UART2_CTSN_MUXMODE_3,UART2_CTSN_MUXMODE_4,UART2_CTSN_MUXMODE_5,UART2_CTSN_MUXMODE_6,?,?,UART2_CTSN_MUXMODE_9,UART2_CTSN_MUXMODE_10,?,UART2_CTSN_MUXMODE_12,?,UART2_CTSN_MUXMODE_14,UART2_CTSN_MUXMODE_15" line.long 0x20 "CTRL_CORE_PAD_UART2_RTSN," hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline bitfld.long 0x20 19. "UART2_RTSN_SLEWCONTROL," "UART2_RTSN_SLEWCONTROL_0,UART2_RTSN_SLEWCONTROL_1" newline bitfld.long 0x20 18. "UART2_RTSN_INPUTENABLE," "UART2_RTSN_INPUTENABLE_0,UART2_RTSN_INPUTENABLE_1" newline bitfld.long 0x20 17. "UART2_RTSN_PULLTYPESELECT," "UART2_RTSN_PULLTYPESELECT_0,UART2_RTSN_PULLTYPESELECT_1" newline bitfld.long 0x20 16. "UART2_RTSN_PULLUDENABLE," "UART2_RTSN_PULLUDENABLE_0,UART2_RTSN_PULLUDENABLE_1" newline hexmask.long.word 0x20 4.--15. 1. "RESERVED," newline bitfld.long 0x20 0.--3. "UART2_RTSN_MUXMODE," "UART2_RTSN_MUXMODE_0,UART2_RTSN_MUXMODE_1,?,UART2_RTSN_MUXMODE_3,UART2_RTSN_MUXMODE_4,?,UART2_RTSN_MUXMODE_6,?,?,UART2_RTSN_MUXMODE_9,?,?,UART2_RTSN_MUXMODE_12,?,UART2_RTSN_MUXMODE_14,UART2_RTSN_MUXMODE_15" line.long 0x24 "CTRL_CORE_PAD_I2C1_SDA," hexmask.long.word 0x24 19.--31. 1. "RESERVED," newline bitfld.long 0x24 18. "I2C1_SDA_INPUTENABLE," "I2C1_SDA_INPUTENABLE_0,I2C1_SDA_INPUTENABLE_1" newline hexmask.long.tbyte 0x24 0.--17. 1. "RESERVED," line.long 0x28 "CTRL_CORE_PAD_I2C1_SCL," hexmask.long.word 0x28 19.--31. 1. "RESERVED," newline bitfld.long 0x28 18. "I2C1_SCL_INPUTENABLE," "I2C1_SCL_INPUTENABLE_0,I2C1_SCL_INPUTENABLE_1" newline hexmask.long.tbyte 0x28 0.--17. 1. "RESERVED," line.long 0x2C "CTRL_CORE_PAD_I2C2_SDA," hexmask.long.word 0x2C 19.--31. 1. "RESERVED," newline bitfld.long 0x2C 18. "I2C2_SDA_INPUTENABLE," "I2C2_SDA_INPUTENABLE_0,I2C2_SDA_INPUTENABLE_1" newline hexmask.long.tbyte 0x2C 0.--17. 1. "RESERVED," line.long 0x30 "CTRL_CORE_PAD_I2C2_SCL," hexmask.long.word 0x30 19.--31. 1. "RESERVED," newline bitfld.long 0x30 18. "I2C2_SCL_INPUTENABLE," "I2C2_SCL_INPUTENABLE_0,I2C2_SCL_INPUTENABLE_1" newline hexmask.long.tbyte 0x30 0.--17. 1. "RESERVED," line.long 0x34 "CTRL_CORE_PAD_TMS," hexmask.long.word 0x34 20.--31. 1. "RESERVED," newline bitfld.long 0x34 19. "TMS_SLEWCONTROL," "TMS_SLEWCONTROL_0,TMS_SLEWCONTROL_1" newline bitfld.long 0x34 18. "TMS_INPUTENABLE," "TMS_INPUTENABLE_0,TMS_INPUTENABLE_1" newline hexmask.long.word 0x34 4.--17. 1. "RESERVED," newline bitfld.long 0x34 0.--3. "TMS_MUXMODE," "TMS_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x38 "CTRL_CORE_PAD_TDI," hexmask.long.word 0x38 20.--31. 1. "RESERVED," newline bitfld.long 0x38 19. "TDI_SLEWCONTROL," "TDI_SLEWCONTROL_0,TDI_SLEWCONTROL_1" newline bitfld.long 0x38 18. "TDI_INPUTENABLE," "TDI_INPUTENABLE_0,TDI_INPUTENABLE_1" newline bitfld.long 0x38 17. "TDI_PULLTYPESELECT," "TDI_PULLTYPESELECT_0,TDI_PULLTYPESELECT_1" newline bitfld.long 0x38 16. "TDI_PULLUDENABLE," "TDI_PULLUDENABLE_0,TDI_PULLUDENABLE_1" newline hexmask.long.word 0x38 4.--15. 1. "RESERVED," newline bitfld.long 0x38 0.--3. "TDI_MUXMODE," "TDI_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,TDI_MUXMODE_14,TDI_MUXMODE_15" line.long 0x3C "CTRL_CORE_PAD_TDO," hexmask.long.word 0x3C 20.--31. 1. "RESERVED," newline bitfld.long 0x3C 19. "TDO_SLEWCONTROL," "TDO_SLEWCONTROL_0,TDO_SLEWCONTROL_1" newline bitfld.long 0x3C 18. "TDO_INPUTENABLE," "TDO_INPUTENABLE_0,TDO_INPUTENABLE_1" newline bitfld.long 0x3C 17. "TDO_PULLTYPESELECT," "TDO_PULLTYPESELECT_0,TDO_PULLTYPESELECT_1" newline bitfld.long 0x3C 16. "TDO_PULLUDENABLE," "TDO_PULLUDENABLE_0,TDO_PULLUDENABLE_1" newline hexmask.long.word 0x3C 4.--15. 1. "RESERVED," newline bitfld.long 0x3C 0.--3. "TDO_MUXMODE," "TDO_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,TDO_MUXMODE_14,TDO_MUXMODE_15" line.long 0x40 "CTRL_CORE_PAD_TCLK," hexmask.long.word 0x40 19.--31. 1. "RESERVED," newline bitfld.long 0x40 18. "TCLK_INPUTENABLE," "TCLK_INPUTENABLE_0,TCLK_INPUTENABLE_1" newline bitfld.long 0x40 17. "TCLK_PULLTYPESELECT," "TCLK_PULLTYPESELECT_0,TCLK_PULLTYPESELECT_1" newline bitfld.long 0x40 16. "TCLK_PULLUDENABLE," "TCLK_PULLUDENABLE_0,TCLK_PULLUDENABLE_1" newline hexmask.long.word 0x40 4.--15. 1. "RESERVED," newline bitfld.long 0x40 0.--3. "TCLK_MUXMODE," "TCLK_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x44 "CTRL_CORE_PAD_TRSTN," hexmask.long.word 0x44 20.--31. 1. "RESERVED," newline bitfld.long 0x44 19. "TRSTN_SLEWCONTROL," "TRSTN_SLEWCONTROL_0,TRSTN_SLEWCONTROL_1" newline bitfld.long 0x44 18. "TRSTN_INPUTENABLE," "TRSTN_INPUTENABLE_0,TRSTN_INPUTENABLE_1" newline bitfld.long 0x44 17. "TRSTN_PULLTYPESELECT," "TRSTN_PULLTYPESELECT_0,TRSTN_PULLTYPESELECT_1" newline bitfld.long 0x44 16. "TRSTN_PULLUDENABLE," "TRSTN_PULLUDENABLE_0,TRSTN_PULLUDENABLE_1" newline hexmask.long.word 0x44 0.--15. 1. "RESERVED," line.long 0x48 "CTRL_CORE_PAD_RTCK," hexmask.long.word 0x48 20.--31. 1. "RESERVED," newline bitfld.long 0x48 19. "RTCK_SLEWCONTROL," "RTCK_SLEWCONTROL_0,RTCK_SLEWCONTROL_1" newline bitfld.long 0x48 18. "RTCK_INPUTENABLE," "RTCK_INPUTENABLE_0,RTCK_INPUTENABLE_1" newline bitfld.long 0x48 17. "RTCK_PULLTYPESELECT," "RTCK_PULLTYPESELECT_0,RTCK_PULLTYPESELECT_1" newline bitfld.long 0x48 16. "RTCK_PULLUDENABLE," "RTCK_PULLUDENABLE_0,RTCK_PULLUDENABLE_1" newline hexmask.long.word 0x48 4.--15. 1. "RESERVED," newline bitfld.long 0x48 0.--3. "RTCK_MUXMODE," "RTCK_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,RTCK_MUXMODE_14,RTCK_MUXMODE_15" line.long 0x4C "CTRL_CORE_PAD_EMU0," hexmask.long.word 0x4C 20.--31. 1. "RESERVED," newline bitfld.long 0x4C 19. "EMU0_SLEWCONTROL," "EMU0_SLEWCONTROL_0,EMU0_SLEWCONTROL_1" newline bitfld.long 0x4C 18. "EMU0_INPUTENABLE," "EMU0_INPUTENABLE_0,EMU0_INPUTENABLE_1" newline bitfld.long 0x4C 17. "EMU0_PULLTYPESELECT," "EMU0_PULLTYPESELECT_0,EMU0_PULLTYPESELECT_1" newline bitfld.long 0x4C 16. "EMU0_PULLUDENABLE," "EMU0_PULLUDENABLE_0,EMU0_PULLUDENABLE_1" newline hexmask.long.word 0x4C 4.--15. 1. "RESERVED," newline bitfld.long 0x4C 0.--3. "EMU0_MUXMODE," "EMU0_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,EMU0_MUXMODE_14,EMU0_MUXMODE_15" line.long 0x50 "CTRL_CORE_PAD_EMU1," hexmask.long.word 0x50 20.--31. 1. "RESERVED," newline bitfld.long 0x50 19. "EMU1_SLEWCONTROL," "EMU1_SLEWCONTROL_0,EMU1_SLEWCONTROL_1" newline bitfld.long 0x50 18. "EMU1_INPUTENABLE," "EMU1_INPUTENABLE_0,EMU1_INPUTENABLE_1" newline bitfld.long 0x50 17. "EMU1_PULLTYPESELECT," "EMU1_PULLTYPESELECT_0,EMU1_PULLTYPESELECT_1" newline bitfld.long 0x50 16. "EMU1_PULLUDENABLE," "EMU1_PULLUDENABLE_0,EMU1_PULLUDENABLE_1" newline hexmask.long.word 0x50 4.--15. 1. "RESERVED," newline bitfld.long 0x50 0.--3. "EMU1_MUXMODE," "EMU1_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,EMU1_MUXMODE_14,EMU1_MUXMODE_15" line.long 0x54 "CTRL_CORE_PAD_RESETN," hexmask.long.word 0x54 18.--31. 1. "RESERVED," newline bitfld.long 0x54 17. "RESETN_PULLTYPESELECT," "RESETN_PULLTYPESELECT_0,RESETN_PULLTYPESELECT_1" newline bitfld.long 0x54 16. "RESETN_PULLUDENABLE," "RESETN_PULLUDENABLE_0,RESETN_PULLUDENABLE_1" newline hexmask.long.word 0x54 0.--15. 1. "RESERVED," line.long 0x58 "CTRL_CORE_PAD_NMIN," hexmask.long.word 0x58 18.--31. 1. "RESERVED," newline bitfld.long 0x58 17. "NMIN_PULLTYPESELECT," "NMIN_PULLTYPESELECT_0,NMIN_PULLTYPESELECT_1" newline bitfld.long 0x58 16. "NMIN_PULLUDENABLE," "NMIN_PULLUDENABLE_0,NMIN_PULLUDENABLE_1" newline hexmask.long.word 0x58 0.--15. 1. "RESERVED," line.long 0x5C "CTRL_CORE_PAD_RSTOUTN," hexmask.long.word 0x5C 18.--31. 1. "RESERVED," newline bitfld.long 0x5C 17. "RSTOUTN_PULLTYPESELECT," "RSTOUTN_PULLTYPESELECT_0,RSTOUTN_PULLTYPESELECT_1" newline bitfld.long 0x5C 16. "RSTOUTN_PULLUDENABLE," "RSTOUTN_PULLUDENABLE_0,RSTOUTN_PULLUDENABLE_1" newline hexmask.long.word 0x5C 0.--15. 1. "RESERVED," group.long 0x1A10++0x0B line.long 0x00 "CTRL_CORE_L4_CFG_ROLES_0_LOWER,L4 Config Protection Group 0 Roles [31:0]" line.long 0x04 "CTRL_CORE_L4_CFG_ROLES_0_UPPER,L4 Config Protection Group 0 Roles [63:32]" line.long 0x08 "CTRL_CORE_L4_CFG_MEMBERS_0,L4 Config Protection Group 0 Members and lock" bitfld.long 0x08 31. "L4_CFG_DISABLE_0,L4 Config Protection Group 0 Lock" "0,1" newline hexmask.long.word 0x08 16.--30. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "L4_CFG_MEMBERS_0,L4 Config Protection Group 0 Members [15:0]" group.long 0x1A20++0x0B line.long 0x00 "CTRL_CORE_L4_CFG_ROLES_1_LOWER,L4 Config Protection Group 1 Roles [31:0]" line.long 0x04 "CTRL_CORE_L4_CFG_ROLES_1_UPPER,L4 Config Protection Group 1 Roles [63:32]" line.long 0x08 "CTRL_CORE_L4_CFG_MEMBERS_1,L4 Config Protection Group 1 Members and lock" bitfld.long 0x08 31. "L4_CFG_DISABLE_1,L4 Config Protection Group 1 Lock" "0,1" newline hexmask.long.word 0x08 16.--30. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "L4_CFG_MEMBERS_1,L4 Config Protection Group 1 Members [15:0]" group.long 0x1A40++0x0B line.long 0x00 "CTRL_CORE_L4_PER_1_ROLES_0_LOWER,L4 Per 1 Protection Group 0 Roles [31:0]" line.long 0x04 "CTRL_CORE_L4_PER_1_ROLES_0_UPPER,L4 Per 1 Protection Group 0 Roles [63:32]" line.long 0x08 "CTRL_CORE_L4_PER_1_MEMBERS_0,L4 Per 1 Protection Group 0 Members and lock" bitfld.long 0x08 31. "L4_PER_1_DISABLE_0,L4 Per 1 Protection Group 0 Lock" "0,1" newline hexmask.long.word 0x08 16.--30. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "L4_PER_1_MEMBERS_0,L4 Per 1 Protection Group 0 Members [15:0]" group.long 0x1A60++0x0B line.long 0x00 "CTRL_CORE_L4_PER_2_ROLES_0_LOWER,L4 Per 2 Protection Group 0 Roles [31:0]" line.long 0x04 "CTRL_CORE_L4_PER_2_ROLES_0_UPPER,L4 Per 2 Protection Group 0 Roles [63:32]" line.long 0x08 "CTRL_CORE_L4_PER_2_MEMBERS_0,L4 Per 2 Protection Group 0 Members and lock" bitfld.long 0x08 31. "L4_PER_2_DISABLE_0,L4 Per 2 Protection Group 0 Lock" "0,1" newline hexmask.long.word 0x08 16.--30. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "L4_PER_2_MEMBERS_0,L4 Per 2 Protection Group 0 Members [15:0]" group.long 0x1A70++0x0B line.long 0x00 "CTRL_CORE_L4_PER_3_ROLES_0_LOWER,L4 Per 3 Protection Group 0 Roles [31:0]" line.long 0x04 "CTRL_CORE_L4_PER_3_ROLES_0_UPPER,L4 Per 3 Protection Group 0 Roles [63:32]" line.long 0x08 "CTRL_CORE_L4_PER_3_MEMBERS_0,L4 Per 3 Protection Group 0 Members and lock" bitfld.long 0x08 31. "L4_PER_3_DISABLE_0,L4 Per 3 Protection Group 0 Lock" "0,1" newline hexmask.long.word 0x08 16.--30. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "L4_PER_3_MEMBERS_0,L4 Per 3 Protection Group 0 Members [15:0]" group.long 0x1A80++0x0B line.long 0x00 "CTRL_CORE_L4_WKUP_ROLES_0_LOWER,L4 Wakeup Protection Group 0 Roles [31:0]" line.long 0x04 "CTRL_CORE_L4_WKUP_ROLES_0_UPPER,L4 Wakeup Protection Group 0 Roles [63:32]" line.long 0x08 "CTRL_CORE_L4_WKUP_MEMBERS_0,L4 Wakeup Protection Group 0 Members and lock" bitfld.long 0x08 31. "L4_WKUP_DISABLE_0,L4 Wakeup Protection Group 0 Lock" "0,1" newline hexmask.long.word 0x08 16.--30. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "L4_WKUP_MEMBERS_0,L4 Wakeup Protection Group 0 Members [15:0]" group.long 0x1AA0++0x0B line.long 0x00 "CTRL_CORE_L4_WKUP_ROLES_3_LOWER,L4 Wakeup Protection Group 3 Roles [31:0]" line.long 0x04 "CTRL_CORE_L4_WKUP_ROLES_3_UPPER,L4 Wakeup Protection Group 3 Roles [63:32]" line.long 0x08 "CTRL_CORE_L4_WKUP_MEMBERS_3,L4 Wakeup Protection Group 3 Members and lock" bitfld.long 0x08 31. "L4_WKUP_DISABLE_3,L4 Wakeup Protection Group 3 Lock" "0,1" newline hexmask.long.word 0x08 16.--30. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "L4_WKUP_MEMBERS_3,L4 Wakeup Protection Group 3 Members [15:0]" group.long 0x1AB0++0x0B line.long 0x00 "CTRL_CORE_L4_WKUP_ROLES_4_LOWER,L4 Wakeup Protection Group 4 Roles [31:0]" line.long 0x04 "CTRL_CORE_L4_WKUP_ROLES_4_UPPER,L4 Wakeup Protection Group 4 Roles [63:32]" line.long 0x08 "CTRL_CORE_L4_WKUP_MEMBERS_4,L4 Wakeup Protection Group 4 Members and lock" bitfld.long 0x08 31. "L4_WKUP_DISABLE_4,L4 Wakeup Protection Group 4 Lock" "0,1" newline hexmask.long.word 0x08 16.--30. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "L4_WKUP_MEMBERS_4,L4 Wakeup Protection Group 4 Members [15:0]" rgroup.long 0x1B38++0x13 line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_0,Standard Fuse OPP VDD_GPU [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_1,Standard Fuse OPP VDD_GPU [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_2,Standard Fuse OPP VDD_GPU [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_3,Standard Fuse OPP VDD_GPU [127:96]" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_4,Standard Fuse OPP VDD_GPU [159:128]" rgroup.long 0x1B60++0x1F line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_0,Standard Fuse OPP VDD_CORE [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_1,Standard Fuse OPP VDD_CORE [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_2,Standard Fuse OPP VDD_CORE [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_3,Standard Fuse OPP VDD_CORE [127:96]" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_4,Standard Fuse OPP VDD_CORE [159:128]" line.long 0x14 "CTRL_CORE_LDOSRAM_CORE_4_VOLTAGE_CTRL,CORE 4th SRAM LDO Control register" rbitfld.long 0x14 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 26. "LDOSRAMCORE_4_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value" "LDOSRAMCORE_4_RETMODE_MUX_CTRL_0,LDOSRAMCORE_4_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x14 21.--25. "LDOSRAMCORE_4_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 16.--20. "LDOSRAMCORE_4_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x14 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 10. "LDOSRAMCORE_4_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value" "LDOSRAMCORE_4_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_4_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x14 5.--9. "LDOSRAMCORE_4_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 0.--4. "LDOSRAMCORE_4_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "CTRL_CORE_LDOSRAM_CORE_5_VOLTAGE_CTRL,CORE 5th SRAM LDO Control register" rbitfld.long 0x18 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 26. "LDOSRAMCORE_5_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value" "LDOSRAMCORE_5_RETMODE_MUX_CTRL_0,LDOSRAMCORE_5_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x18 21.--25. "LDOSRAMCORE_5_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 16.--20. "LDOSRAMCORE_5_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x18 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 10. "LDOSRAMCORE_5_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value" "LDOSRAMCORE_5_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_5_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x18 5.--9. "LDOSRAMCORE_5_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 0.--4. "LDOSRAMCORE_5_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "CTRL_CORE_LDOSRAM_DSPEVE_2_VOLTAGE_CTRL,DSPEVE 2nd SRAM LDO Control register" rbitfld.long 0x1C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 26. "LDOSRAMDSPEVE_2_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value" "LDOSRAMDSPEVE_2_RETMODE_MUX_CTRL_0,LDOSRAMDSPEVE_2_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x1C 21.--25. "LDOSRAMDSPEVE_2_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 16.--20. "LDOSRAMDSPEVE_2_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x1C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 10. "LDOSRAMDSPEVE_2_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value" "LDOSRAMDSPEVE_2_ACTMODE_MUX_CTRL_0,LDOSRAMDSPEVE_2_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x1C 5.--9. "LDOSRAMDSPEVE_2_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 0.--4. "LDOSRAMDSPEVE_2_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1C04++0x07 line.long 0x00 "CTRL_CORE_SMA_SW_2,OCP Spare Register" line.long 0x04 "CTRL_CORE_SMA_SW_3,OCP Spare Register" group.long 0x1C14++0x07 line.long 0x00 "CTRL_CORE_SMA_SW_6,OCP Spare Register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "RMII_CLK_SETTING,RMII CLK setting" "Internal clock from..,Reserved" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," newline bitfld.long 0x00 0. "MUXSEL_32K_CLKIN,Setting for mux to select 32KHz clock input to PRCM" "0,1" line.long 0x04 "CTRL_CORE_SMA_SW_7,OCP Spare Register" hexmask.long.word 0x04 17.--31. 1. "RESERVED," newline bitfld.long 0x04 16. "MMU1_ABORT_ENABLE,MMU1 abort enable" "0,1" newline rbitfld.long 0x04 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 11. "EDMA_TC0_RD_MMU_ROUTE_ENABLE,EDMA TC0 RD traffic MMU route enable" "0,1" newline bitfld.long 0x04 10. "EDMA_TC1_RD_MMU_ROUTE_ENABLE,EDMA TC1 RD traffic MMU route enable" "0,1" newline bitfld.long 0x04 9. "EDMA_TC0_WR_MMU_ROUTE_ENABLE,EDMA TC0 WR traffic MMU route enable" "0,1" newline bitfld.long 0x04 8. "EDMA_TC1_WR_MMU_ROUTE_ENABLE,EDMA TC1 WR traffic MMU route enable" "0,1" newline hexmask.long.byte 0x04 0.--7. 1. "RESERVED," group.long 0x1C48++0x5F line.long 0x00 "CTRL_CORE_FIREWALL_CONNID_CONTROL_0,Firewall ConnID control register" bitfld.long 0x00 28.--31. "MMU1_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "EDMA_TC0_RD_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "EDMA_TC0_WR_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "EDMA_TC1_RD_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "EDMA_TC1_WR_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "VIP1_P0_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "VIP1_P1_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "EVE1_TC0_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "CTRL_CORE_FIREWALL_CONNID_CONTROL_1,Firewall ConnID control register" bitfld.long 0x04 28.--31. "EVE1_TC1_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 24.--27. "DSP1_EDMA_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 20.--23. "DSP1_MDMA_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 16.--19. "DSP2_EDMA_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12.--15. "DSP2_MDMA_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. "DSS_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x04 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. "IPU1_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "CTRL_CORE_FIREWALL_CONNID_CONTROL_2,Firewall ConnID control register" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "DSP1_CFG_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 20.--23. "DSP2_CFG_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 16.--19. "GMAC_SW_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 0.--15. 1. "RESERVED," line.long 0x0C "CTRL_CORE_FIREWALL_CONNID_CONTROL_3,Firewall ConnID control register" rbitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 24.--27. "ISS_RT_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x0C 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 16.--19. "ISS_NRT1_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 12.--15. "ISS_NRT2_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 0.--11. 1. "RESERVED," line.long 0x10 "CTRL_CORE_EMIF_MPU_ROUTING,EMIF MPU traffic control register" hexmask.long 0x10 4.--31. 1. "RESERVED," newline bitfld.long 0x10 3. "EVE1_ROUTING_ENABLE," "0,1" newline bitfld.long 0x10 2. "DSP2_ROUTING_ENABLE," "0,1" newline bitfld.long 0x10 1. "DSP1_ROUTING_ENABLE," "0,1" newline bitfld.long 0x10 0. "IPU1_ROUTING_ENABLE," "0,1" line.long 0x14 "CTRL_CORE_PRCM_CLKSEL_CONTROL,PRCM Clock selection control register" rbitfld.long 0x14 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 28. "EVE_CLKSEL,EVE Clock selection control" "EVE_CLKSEL_0,EVE_CLKSEL_1" newline rbitfld.long 0x14 26.--27. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 24.--25. "DSP_CLKSEL,DSP Clock selection control" "DSP_CLKSEL_0,DSP_CLKSEL_1,DSP_CLKSEL_2,DSP_CLKSEL_3" newline rbitfld.long 0x14 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 20.--21. "ADC_CLKSEL,ADC Clock selection control" "ADC_CLKSEL_0,ADC_CLKSEL_1,ADC_CLKSEL_2,ADC_CLKSEL_3" newline rbitfld.long 0x14 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 16.--17. "RTI1_CLKSEL,RTI1 Clock selection control" "RTI1_CLKSEL_0,RTI1_CLKSEL_1,RTI1_CLKSEL_2,RTI1_CLKSEL_3" newline rbitfld.long 0x14 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 12.--13. "RTI2_CLKSEL,RTI2 Clock selection control" "RTI2_CLKSEL_0,RTI2_CLKSEL_1,RTI2_CLKSEL_2,RTI2_CLKSEL_3" newline rbitfld.long 0x14 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 8.--9. "RTI3_CLKSEL,RTI3 Clock selection control" "RTI3_CLKSEL_0,RTI3_CLKSEL_1,RTI3_CLKSEL_2,RTI3_CLKSEL_3" newline rbitfld.long 0x14 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 4.--5. "RTI4_CLKSEL,RTI4 Clock selection control" "RTI4_CLKSEL_0,RTI4_CLKSEL_1,RTI4_CLKSEL_2,RTI4_CLKSEL_3" newline rbitfld.long 0x14 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 0.--1. "RTI5_CLKSEL,RTI5 Clock selection control" "RTI5_CLKSEL_0,RTI5_CLKSEL_1,RTI5_CLKSEL_2,RTI5_CLKSEL_3" line.long 0x18 "CTRL_CORE_PRCM_CLKDIV_CONTROL1,PRCM Clock divider control1 register" rbitfld.long 0x18 30.--31. "RESERVED,Read returns 0" "0,1,2,3" newline rbitfld.long 0x18 29. "DBG_STM_EXPT_CLK_HSDIV_CHANGE_ACK,HSDIVIDER change ack" "0,1" newline rbitfld.long 0x18 28. "DBG_STM_EXPT_CLK_HSDIV_EN_ACK,EN_ACK from HSDIVIDER" "0,1" newline rbitfld.long 0x18 27. "DBG_TRC_EXPT_CLK_HSDIV_CHANGE_ACK,HSDIVIDER change ack" "0,1" newline rbitfld.long 0x18 26. "DBG_TRC_EXPT_CLK_HSDIV_EN_ACK,EN_ACK from HSDIVIDER" "0,1" newline rbitfld.long 0x18 25. "DBG_ATB_CLK_HSDIV_CHANGE_ACK,HSDIVIDER change ack" "0,1" newline rbitfld.long 0x18 24. "DBG_ATB_CLK_HSDIV_EN_ACK,EN_ACK from HSDIVIDER" "0,1" newline bitfld.long 0x18 23. "DBG_STM_EXPT_CLK_TENABLEDIV_SEL," "0,1" newline bitfld.long 0x18 22. "DBG_STM_EXPT_CLK_TENABLEDIV,Needs to be pulsed (LO->HI->LO) for latching the divider value in to the DPLL" "0,1" newline bitfld.long 0x18 16.--21. "DBG_STM_EXPT_CLK_DIV,DebugSS STM Clock divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x18 15. "DBG_TRC_EXPT_CLK_TENABLEDIV_SEL," "0,1" newline bitfld.long 0x18 14. "DBG_TRC_EXPT_CLK_TENABLEDIV,Needs to be pulsed (LO->HI->LO) for latching the divider value in to the DPLL" "0,1" newline bitfld.long 0x18 8.--13. "DBG_TRC_EXPT_CLK_DIV,DebugSS TRC Clock divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x18 7. "RESERVED," "0,1" newline bitfld.long 0x18 6. "DBG_ATB_CLK_TENABLEDIV,Needs to be pulsed (LO->HI->LO) for latching the divider value in to the DPLL" "0,1" newline bitfld.long 0x18 0.--5. "DBG_ATB_CLK_DIV,DebugSS ATB Clock divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "CTRL_CORE_PRCM_CLKDIV_CONTROL2,PRCM Clock divider control2 register" rbitfld.long 0x1C 29.--31. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 28. "VID_PIX_CLK_TENABLEDIV_SEL,VID_PIX_CLK_TENABLEDIV control select" "Control from PRCM,Control from Control Module -.." newline rbitfld.long 0x1C 27. "VID_PIX_CLK_HSDIV_CHANGE_ACK,HSDIVIDER change ack" "0,1" newline bitfld.long 0x1C 25.--26. "VID_PIX_CLK_EXT_CLK_DIV,Video Clock divider value" "VID_PIX_CLK_EXT_CLK_DIV_0,VID_PIX_CLK_EXT_CLK_DIV_1,VID_PIX_CLK_EXT_CLK_DIV_2,VID_PIX_CLK_EXT_CLK_DIV_3" newline rbitfld.long 0x1C 24. "VID_PIX_CLK_HSDIV_EN_ACK,EN_ACK from HSDIVIDER" "0,1" newline bitfld.long 0x1C 23. "VID_PIX_CLK_HSDIV_EN,Clock enable to the Video Clock HS divider" "0,1" newline bitfld.long 0x1C 22. "VID_PIX_CLK_HSDIV_LATCH_EN,Video Clock HS divider latch enable: To be toggled to latch DIV value in HSDIVIDER" "0,1" newline bitfld.long 0x1C 16.--21. "VID_PIX_CLK_HSDIV,Video Clock HS divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x1C 14.--15. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "TESOC_DBG_ATB_CLK_TENABLEDIV_SEL,Mux select for the TENABLE of Core DPLL HS divider" "PRCM,DBG_ATB_CLK,TESOC_EXT_CLK_HSDIV,Reserved" newline rbitfld.long 0x1C 11. "TESOC_HSDIV_CHANGE_ACK,HSDIVIDER change ack" "0,1" newline bitfld.long 0x1C 9.--10. "TESOC_EXT_CLK_DIV,TesOC clock divider value" "TESOC_EXT_CLK_DIV_0,TESOC_EXT_CLK_DIV_1,TESOC_EXT_CLK_DIV_2,TESOC_EXT_CLK_DIV_3" newline rbitfld.long 0x1C 8. "TESOC_HSDIV_EN_ACK,EN_ACK from HSDIVIDER" "0,1" newline bitfld.long 0x1C 7. "TESOC_HSDIV_EN,Clock enable to TesOC clock HS divider" "0,1" newline bitfld.long 0x1C 6. "TESOC_HSDIV_LATCH_EN,TesOC clock HS divider latch enable: To be toggled to latch DIV value in DPLL" "0,1" newline bitfld.long 0x1C 0.--5. "TESOC_HSDIV,TesOC clock HS divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "CTRL_CORE_SMA_SW_10,OCP Spare Register" rbitfld.long 0x20 30.--31. "SMA_SW_10,spare bits" "0,1,2,3" newline bitfld.long 0x20 29. "IE_CSI2_0_Y4," "0,1" newline bitfld.long 0x20 28. "IE_CSI2_0_X4," "0,1" newline bitfld.long 0x20 27. "IE_CSI2_0_Y3," "0,1" newline bitfld.long 0x20 25.--26. "IE_CSI2_0_X3," "0,1,2,3" newline bitfld.long 0x20 24. "IE_CSI2_0_Y2," "0,1" newline bitfld.long 0x20 23. "IE_CSI2_0_X2," "0,1" newline bitfld.long 0x20 22. "IE_CSI2_0_Y1," "0,1" newline bitfld.long 0x20 21. "IE_CSI2_0_X1," "0,1" newline bitfld.long 0x20 20. "IE_CSI2_0_Y0," "0,1" newline bitfld.long 0x20 19. "IE_CSI2_0_X0," "0,1" newline bitfld.long 0x20 18. "PIPD_CSI2_0_X4," "0,1" newline bitfld.long 0x20 17. "PIPD_CSI2_0_Y3," "0,1" newline bitfld.long 0x20 16. "PIPD_CSI2_0_X3," "0,1" newline bitfld.long 0x20 15. "PIPD_CSI2_0_Y2," "0,1" newline bitfld.long 0x20 14. "PIPD_CSI2_0_X2," "0,1" newline bitfld.long 0x20 13. "PIPD_CSI2_0_Y1," "0,1" newline bitfld.long 0x20 12. "PIPD_CSI2_0_X1," "0,1" newline bitfld.long 0x20 11. "PIPD_CSI2_0_Y0," "0,1" newline bitfld.long 0x20 10. "PIPD_CSI2_0_X0," "0,1" newline bitfld.long 0x20 9. "PIPU_CSI2_0_Y4," "0,1" newline bitfld.long 0x20 8. "PIPU_CSI2_0_X4," "0,1" newline bitfld.long 0x20 7. "PIPU_CSI2_0_Y3," "0,1" newline bitfld.long 0x20 6. "PIPU_CSI2_0_X3," "0,1" newline bitfld.long 0x20 5. "PIPU_CSI2_0_Y2," "0,1" newline bitfld.long 0x20 4. "PIPU_CSI2_0_X2," "0,1" newline bitfld.long 0x20 3. "PIPU_CSI2_0_Y1," "0,1" newline bitfld.long 0x20 2. "PIPU_CSI2_0_X1," "0,1" newline bitfld.long 0x20 1. "PIPU_CSI2_0_Y0," "0,1" newline bitfld.long 0x20 0. "PIPU_CSI2_0_X0," "0,1" line.long 0x24 "CTRL_CORE_SMA_SW_11,OCP Spare Register" line.long 0x28 "CTRL_CORE_SMA_SW_12,OCP Spare Register" line.long 0x2C "CTRL_CORE_SMA_SW_13,OCP Spare Register" line.long 0x30 "CTRL_CORE_TESOC_LAST_RESET_INDICATOR,TESOC last reset indicator register" rbitfld.long 0x30 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x30 24.--27. "IPU_LAST_RESET_INDICATOR,IPU resert indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x30 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x30 16.--19. "DSP1_LAST_RESET_INDICATOR,DSP1 resert indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x30 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x30 8.--11. "DSP2_LAST_RESET_INDICATOR,DSP2 resert indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x30 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x30 0.--3. "EVE_LAST_RESET_INDICATOR,EVE resert indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x34 "CTRL_CORE_SD_DAC_CONTROL,SD DAC control register" bitfld.long 0x34 31. "SD_DAC_CALSET," "0,1" newline hexmask.long.word 0x34 21.--30. 1. "SD_DAC_CAL,10-bit data for SD_DAC test or debug purposes" newline hexmask.long.word 0x34 6.--20. 1. "CTL,SD_DAC Control interface for reconfiguration of the module in functional mode through internal configuration registers" newline bitfld.long 0x34 5. "CTL_WR_ACK,Used only for synchronous mode of the CTL interface" "0,1" newline bitfld.long 0x34 4. "CTL_ASYNC_EN,Asynchronous mode enable for CTL interface" "Synchronous mode,Asynchronous mode" newline bitfld.long 0x34 3. "TVOUTBYPASS,TVOUT Bypass enable" "Normal mode,Bypass mode" newline bitfld.long 0x34 2. "ACEN,AC coupling enable" "DC coupling selected,AC coupling selected" newline rbitfld.long 0x34 0.--1. "RESERVED," "0,1,2,3" line.long 0x38 "CTRL_CORE_SD_DAC_TRIM_VALUE,SD DAC trim value" bitfld.long 0x38 31. "COMP_EN,Optional control for lower output swing" "High full-scale output swing,Low full-scale output swing" newline hexmask.long.byte 0x38 23.--30. 1. "RESERVED," newline hexmask.long.tbyte 0x38 0.--22. 1. "SD_DAC_TRIM,SD DAC trim value" line.long 0x3C "CTRL_CORE_ADC_ERROR_OFFSET,ADC Error offset register" hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x3C 0.--7. 1. "ERROR_OFFSET,Error offset value driven from efuse with optional override" line.long 0x40 "CTRL_CORE_IPU_WAKEUP,IPU wakeup enable" hexmask.long 0x40 1.--31. 1. "RESERVED," newline bitfld.long 0x40 0. "IPU_WKUP_EN,IPU wakeup enable" "0,1" line.long 0x44 "CTRL_CORE_ISS_EFUSE,ADC Error offset register" hexmask.long 0x44 7.--31. 1. "RESERVED," newline bitfld.long 0x44 6. "STD_FUSE_ISS_EFUSE1_EN,Error offset value driven from efuse with optional override" "0,1" newline bitfld.long 0x44 5. "STD_FUSE_ISS_EFUSE2_EN,Error offset value driven from efuse with optional override" "0,1" newline bitfld.long 0x44 4. "STD_FUSE_ISS_EFUSE3_EN,Error offset value driven from efuse with optional override" "0,1" newline bitfld.long 0x44 3. "STD_FUSE_ISS_EFUSE4_EN,Error offset value driven from efuse with optional override" "0,1" newline bitfld.long 0x44 2. "STD_FUSE_ISS_EFUSE5_EN,Error offset value driven from efuse with optional override" "0,1" newline bitfld.long 0x44 1. "STD_FUSE_ISS_EFUSE6_EN,Error offset value driven from efuse with optional override" "0,1" newline bitfld.long 0x44 0. "STD_FUSE_ISS_EFUSE7_EN,Error offset value driven from efuse with optional override" "0,1" line.long 0x48 "CTRL_CORE_SMA_SW_14,OCP Spare Register (SR1.0 Only)" bitfld.long 0x48 31. "MCASP_MODE_17_VOUT1_D22_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d22 not selected0x1: mcasp2_axr4 selected on pad vout1_d22 as function 17" "0,1" newline bitfld.long 0x48 30. "MCASP_MODE_17_VOUT1_D21_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d21 not selected0x1: mcasp2_axr3 selected on pad vout1_d21 as function 17" "0,1" newline bitfld.long 0x48 29. "MCASP_MODE_17_VOUT1_D20_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d20 not selected0x1: mcasp2_axr2 selected on pad vout1_d20 as function 17" "0,1" newline bitfld.long 0x48 28. "MCASP_MODE_17_VOUT1_D19_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d19 not selected0x1: mcasp2_axr1 selected on pad vout1_d19 as function 17" "0,1" newline bitfld.long 0x48 27. "MCASP_MODE_17_VOUT1_D18_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d18 not selected0x1: mcasp2_axr0 selected on pad vout1_d18 as function 17" "0,1" newline bitfld.long 0x48 26. "MCASP_MODE_17_VOUT1_D17_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d17 not selected0x1: mcasp2_fsr selected on pad vout1_d17 as function 17" "0,1" newline bitfld.long 0x48 25. "MCASP_MODE_17_VOUT1_D16_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d16 not selected0x1: This option is not supported and must not be used" "0,1" newline bitfld.long 0x48 24. "MCASP_MODE_17_VOUT1_D15_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d15 not selected0x1: mcasp2_fsx selected on pad vout1_d15 as function 17" "0,1" newline bitfld.long 0x48 23. "MCASP_MODE_17_VOUT1_D14_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d14 not selected0x1: mcasp2_aclkx selected on pad vout1_d14 as function 17" "0,1" newline bitfld.long 0x48 22. "MCASP_MODE_17_VOUT1_D13_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d13 not selected0x1: mcasp2_aclkr selected on pad vout1_d13 as function 17" "0,1" newline bitfld.long 0x48 21. "MCASP_MODE_17_GPMC_AD7_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad7 not selected0x1: mcasp2_ahclkx selected on pad gpmc_ad7 as function 17" "0,1" newline bitfld.long 0x48 20. "MCASP_MODE_17_VIN1A_D5_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_d5 not selected0x1: mcasp3_ahclkx selected on pad vin1a_d5 as function 17" "0,1" newline bitfld.long 0x48 19. "MCASP_MODE_17_VIN1A_D4_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_d4 not selected0x1: mcasp3_axr5 selected on pad vin1a_d4 as function 17" "0,1" newline bitfld.long 0x48 18. "MCASP_MODE_17_VIN1A_D3_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_d3 not selected0x1: mcasp3_axr4 selected on pad vin1a_d3 as function 17" "0,1" newline bitfld.long 0x48 17. "MCASP_MODE_17_VIN1A_D2_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_d2 not selected0x1: mcasp3_axr3 selected on pad vin1a_d2 as function 17" "0,1" newline bitfld.long 0x48 16. "MCASP_MODE_17_VIN1A_D1_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_d1 not selected0x1: mcasp3_axr2 selected on pad vin1a_d1 as function 17" "0,1" newline bitfld.long 0x48 15. "MCASP_MODE_17_VIN1A_D0_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_d0 not selected0x1: mcasp3_axr1 selected on pad vin1a_d0 as function 17" "0,1" newline bitfld.long 0x48 14. "MCASP_MODE_17_VIN1A_VSYNC0_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_vsync0 not selected0x1: mcasp3_axr0 selected on pad vin1a_vsync0 as function 17" "0,1" newline bitfld.long 0x48 13. "MCASP_MODE_17_VIN1A_HSYNC0_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_hsync0 not selected0x1: mcasp3_fsr selected on pad vin1a_hsync0 as function 17" "0,1" newline bitfld.long 0x48 12. "MCASP_MODE_17_VIN1A_FLD0_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_fld0 not selected0x1: mcasp3_aclkr selected on pad vin1a_fld0 as function 17" "0,1" newline bitfld.long 0x48 11. "MCASP_MODE_17_VIN1A_DE0_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_de0 not selected0x1: This option is not supported and must not be used" "0,1" newline bitfld.long 0x48 10. "MCASP_MODE_17_VIN1A_CLK0_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_clk0 not selected0x1: mcasp3_aclkx selected on pad vin1a_clk0 as function 17" "0,1" newline bitfld.long 0x48 9. "MCASP_MODE_17_GPMC_AD15_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad15 not selected0x1: mcasp2_axr5 selected on pad gpmc_ad15 as function 17" "0,1" newline bitfld.long 0x48 8. "MCASP_MODE_17_GPMC_AD14_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad14 not selected0x1: mcasp2_axr4 selected on pad gpmc_ad14 as function 17" "0,1" newline bitfld.long 0x48 7. "MCASP_MODE_17_GPMC_AD13_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad13 not selected0x1: mcasp2_axr3 selected on pad gpmc_ad13 as function 17" "0,1" newline bitfld.long 0x48 6. "MCASP_MODE_17_GPMC_AD12_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad12 not selected0x1: mcasp2_axr2 selected on pad gpmc_ad12 as function 17" "0,1" newline bitfld.long 0x48 5. "MCASP_MODE_17_GPMC_AD11_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad11 not selected0x1: mcasp2_axr1 selected on pad gpmc_ad11 as function 17" "0,1" newline bitfld.long 0x48 4. "MCASP_MODE_17_GPMC_AD10_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad10 not selected0x1: mcasp2_axr0 selected on pad gpmc_ad10 as function 17" "0,1" newline bitfld.long 0x48 3. "MCASP_MODE_17_GPMC_AD9_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad9 not selected0x1: mcasp2_fsr selected on pad gpmc_ad9 as function 17" "0,1" newline bitfld.long 0x48 2. "MCASP_MODE_17_GPMC_AD8_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad8 not selected0x1: mcasp2_aclkr selected on pad gpmc_ad8 as function 17" "0,1" newline bitfld.long 0x48 1. "MCASP_MODE_17_GPMC_AD6_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad6 not selected0x1: mcasp2_fsx selected on pad gpmc_ad6 as function 17" "0,1" newline bitfld.long 0x48 0. "MCASP_MODE_17_GPMC_AD5_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad5 not selected0x1: mcasp2_aclkx selected on pad gpmc_ad5 as function 17" "0,1" line.long 0x4C "CTRL_CORE_SMA_SW_15,OCP Spare Register (SR1.0 Only)" hexmask.long 0x4C 3.--31. 1. "SMA_SW_15,OCP Spare Bits" newline bitfld.long 0x4C 2. "MCASP_MODE_17_VOUT1_D12_MUX_CONTROL_1,SR2.0 Only:0x0: Function 17 for pad vout1_d12 not selected0x1: mcasp2_ahclkx selected on pad vout1_d12 as function 17" "0,1" newline bitfld.long 0x4C 1. "MCASP_MODE_17_VIN1A_D6_MUX_CONTROL_1,SR2.0 Only:0x0: Function 17 for pad vin1a_d6 not selected0x1: mcasp3_fsx selected on pad vin1a_d6 as function 17" "0,1" newline bitfld.long 0x4C 0. "MCASP_MODE_17_VOUT1_D23_MUX_CONTROL_1,SR2.0 Only:0x0: Function 17 for pad vout1_d23 not selected0x1: mcasp2_axr5 selected on pad vout1_d23 as function 17" "0,1" line.long 0x50 "CTRL_CORE_SMA_SW_16,OCP Spare Register (SR1.0 Only)" hexmask.long 0x50 1.--31. 1. "SMA_SW_16,OCP Spare Register" newline bitfld.long 0x50 0. "CORE_DPLL_INPUT_CLK_SELECTION,SR2.0 Only:DPLL_CORE input clock selection.0x0: SYS_CLK1 selected as input clock (REF_CLK) for" "0,1" line.long 0x54 "CTRL_CORE_SMA_SW_17,OCP Spare Register (SR1.0 Only)" hexmask.long.tbyte 0x54 12.--31. 1. "SMA_SW_17,OCP Spare Bits" newline rbitfld.long 0x54 11. "MCAN_CLK_HSDIV_CHANGE_ACK,SR2.0 Only:Acknowledge flag which indicates that the on-the-fly change of H14 divider of DPLL_GMAC_DSP is done" "0,1" newline rbitfld.long 0x54 10. "MCAN_CLK_HSDIV_EN_ACK,SR2.0 Only:Indicates whether CLKOUTX2_H14 of DPLL_GMAC_DSP is enabled or not.0x0: CLKOUTX2_H14 is" "0,1" newline bitfld.long 0x54 9. "MCAN_CLK_TENABLEDIV_SEL,SR2.0 Only:TENABLEDIV control select for H14 of" "0,1" newline bitfld.long 0x54 8. "RESERVED,Reserved" "0,1" newline bitfld.long 0x54 7. "MCAN_CLK_HSDIV_EN,SR2.0 Only:Output clock (CLKOUTX2_H14) enable for H14 of" "0,1" newline bitfld.long 0x54 6. "MCAN_CLK_HSDIV_LATCH_EN,SR2.0 Only:To be toggled (LO->HI->LO) to latch MCAN_CLK_HSDIV value in H14 of DPLL_GMAC_DSP" "0,1" newline bitfld.long 0x54 0.--5. "MCAN_CLK_HSDIV,SR2.0 Only:Divider value for H14 of DPLL_GMAC_DSP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x58 "CTRL_CORE_ROM_CPU0_BRANCH," line.long 0x5C "CTRL_CORE_ROM_CPU1_BRANCH," rgroup.long 0x1CB0++0x27 line.long 0x00 "CTRL_CORE_SMA_SW_18,OCP Spare Register" line.long 0x04 "CTRL_CORE_SMA_SW_19,OCP Spare Register" line.long 0x08 "CTRL_CORE_SMA_SW_20,OCP Spare Register" line.long 0x0C "CTRL_CORE_SMA_SW_21,OCP Spare Register" line.long 0x10 "CTRL_CORE_SMA_SW_22,OCP Spare Register (SR1.0 Only)" hexmask.long.word 0x10 18.--31. 1. "SMA_SW_22,OCP Spare Register" newline hexmask.long.tbyte 0x10 0.--17. 1. "CORE_DPLL_REGMF_CONTROL,SR2.0 Only:Fractional part of the software-configured multiplication ratio M of DPLL_CORE" line.long 0x14 "CTRL_CORE_SMA_SW_23,OCP Spare Register" line.long 0x18 "CTRL_CORE_SMA_SW_24,OCP Spare Register" line.long 0x1C "CTRL_CORE_SMA_SW_25,OCP Spare Register" line.long 0x20 "CTRL_CORE_SMA_SW_26,OCP Spare Register" line.long 0x24 "CTRL_CORE_SMA_SW_27,OCP Spare Register" repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x1CA8)++0x03 line.long 0x00 "CTRL_CORE_ROM_AUXBOOT$1," repeat.end width 0x0B tree.end tree "CTRL_MODULE_CORE_TARG" base ad:0x4A004000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CTRL_MODULE_WKUP" base ad:0x4AE0C000 group.long 0x100++0x03 line.long 0x00 "CTRL_WKUP_SEC_CTRL,Control Register" bitfld.long 0x00 31. "SECCTRLWRDISABLE,Control Register write disable control" "Write in this register is allowed,Write in this register is forbidden" newline hexmask.long 0x00 5.--30. 1. "RESERVED," newline bitfld.long 0x00 4. "SECURE_EMIF_CONFIG_RO_EN,Access mode for registers: CTRL_WKUP_EMIF1_SDRAM_CONFIG CTRL_WKUP_EMIF2_SDRAM_CONFIG" "These registers are RW,These registers are RO" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x108++0x0B line.long 0x00 "CTRL_WKUP_SEC_TAP,TAP controllers register" bitfld.long 0x00 31. "SECTAPWR_DISABLE,TAP controllers register write disable control" "0,1" newline rbitfld.long 0x00 27.--30. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 26. "RESERVED,Reserved" "0,1" newline hexmask.long.word 0x00 13.--25. 1. "RESERVED," newline bitfld.long 0x00 12. "DSP2_TAPENABLE,DSP2 TAP control" "DSP2_TAPENABLE_0,DSP2_TAPENABLE_1" newline bitfld.long 0x00 11. "JTAGEXT_TAPENABLE,External JTAG expansion TAP control" "JTAGEXT_TAPENABLE_0,JTAGEXT_TAPENABLE_1" newline rbitfld.long 0x00 5.--10. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 4. "IEEE1500_ENABLE,IEEE1500 and P1500 access enable" "0,1" newline bitfld.long 0x00 3. "P1500_ENABLE,P1500 access enable" "P1500_ENABLE_0,P1500_ENABLE_1" newline bitfld.long 0x00 2. "IPU1_TAPENABLE,IPU1 TAP control" "IPU1_TAPENABLE_0,IPU1_TAPENABLE_1" newline bitfld.long 0x00 1. "DSP1_TAPENABLE,DSP1 TAP control" "DSP1_TAPENABLE_0,DSP1_TAPENABLE_1" newline bitfld.long 0x00 0. "DAP_TAPENABLE,DAP TAP control" "DAP_TAPENABLE_0,DAP_TAPENABLE_1" line.long 0x04 "CTRL_WKUP_OCPREG_SPARE,OCP Spare Register" bitfld.long 0x04 31. "OCPREG_SPARE31,OCP spare register 31" "0,1" newline bitfld.long 0x04 30. "OCPREG_SPARE30,OCP spare register 30" "0,1" newline bitfld.long 0x04 29. "OCPREG_SPARE29,OCP spare register 29" "0,1" newline bitfld.long 0x04 28. "OCPREG_SPARE28,OCP spare register 28" "0,1" newline bitfld.long 0x04 27. "OCPREG_SPARE27,OCP spare register 27" "0,1" newline bitfld.long 0x04 26. "OCPREG_SPARE26,OCP spare register 26" "0,1" newline bitfld.long 0x04 25. "OCPREG_SPARE25,OCP spare register 25" "0,1" newline bitfld.long 0x04 24. "OCPREG_SPARE24,OCP spare register 24" "0,1" newline bitfld.long 0x04 23. "OCPREG_SPARE23,OCP spare register 23" "0,1" newline bitfld.long 0x04 22. "OCPREG_SPARE22,OCP spare register 22" "0,1" newline bitfld.long 0x04 21. "OCPREG_SPARE21,OCP spare register 21" "0,1" newline bitfld.long 0x04 20. "OCPREG_SPARE20,OCP spare register 20" "0,1" newline bitfld.long 0x04 19. "OCPREG_SPARE19,OCP spare register 19" "0,1" newline bitfld.long 0x04 18. "OCPREG_SPARE18,OCP spare register 18" "0,1" newline bitfld.long 0x04 17. "OCPREG_SPARE17,OCP spare register 17" "0,1" newline bitfld.long 0x04 16. "OCPREG_SPARE16,OCP spare register 16" "0,1" newline bitfld.long 0x04 15. "OCPREG_SPARE15,OCP spare register 15" "0,1" newline bitfld.long 0x04 14. "OCPREG_SPARE14,OCP spare register 14" "0,1" newline bitfld.long 0x04 13. "OCPREG_SPARE13,OCP spare register 13" "0,1" newline bitfld.long 0x04 12. "OCPREG_SPARE12,OCP spare register 12" "0,1" newline bitfld.long 0x04 11. "OCPREG_SPARE11,OCP spare register 11" "0,1" newline bitfld.long 0x04 10. "OCPREG_SPARE10,OCP spare register 10" "0,1" newline bitfld.long 0x04 9. "OCPREG_SPARE9,OCP spare register 9" "0,1" newline bitfld.long 0x04 8. "OCPREG_SPARE8,OCP spare register 8" "0,1" newline bitfld.long 0x04 7. "OCPREG_SPARE7,OCP spare register 7" "0,1" newline bitfld.long 0x04 6. "OCPREG_SPARE6,OCP spare register 6" "0,1" newline bitfld.long 0x04 5. "OCPREG_SPARE5,OCP spare register 5" "0,1" newline bitfld.long 0x04 4. "OCPREG_SPARE4,OCP spare register 4" "0,1" newline bitfld.long 0x04 3. "OCPREG_SPARE3,OCP spare register 3" "0,1" newline bitfld.long 0x04 2. "OCPREG_SPARE2,OCP spare register 2" "0,1" newline bitfld.long 0x04 1. "OCPREG_SPARE1,OCP spare register 1" "0,1" newline rbitfld.long 0x04 0. "RESERVED," "0,1" line.long 0x08 "CTRL_WKUP_SECURE_EMIF1_SDRAM_CONFIG,EMIF1 SDRAM configuration register" rbitfld.long 0x08 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 27.--28. "EMIF1_SDRAM_IBANK_POS,Internal bank position" "0,1,2,3" newline bitfld.long 0x08 24.--26. "EMIF1_SDRAM_DDR_TERM,DDR2 and DDR3 termination resistor value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 23. "EMIF1_SDRAM_DDR2_DDQS,DDR2 differential DQS enable" "0,1" newline bitfld.long 0x08 21.--22. "EMIF1_SDRAM_DYN_ODT,DDR3 Dynamic ODT" "0,1,2,3" newline bitfld.long 0x08 20. "EMIF1_SDRAM_DDR_DISABLE_DLL,Disable DLL select" "0,1" newline bitfld.long 0x08 18.--19. "EMIF1_SDRAM_DRIVE,SDRAM drive strength" "0,1,2,3" newline bitfld.long 0x08 16.--17. "EMIF1_SDRAM_CWL,DDR3 CAS Write latency" "0,1,2,3" newline rbitfld.long 0x08 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 10.--13. "EMIF1_SDRAM_CL,CAS Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 7.--9. "EMIF1_SDRAM_ROWSIZE,Row Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 4.--6. "EMIF1_SDRAM_IBANK,Internal Bank setup" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 0.--2. "EMIF1_SDRAM_PAGESIZE,Page Size" "0,1,2,3,4,5,6,7" rgroup.long 0x13C++0x03 line.long 0x00 "CTRL_WKUP_STD_FUSE_CONF,Standard Fuse conf [63:32]" hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline bitfld.long 0x00 19. "STD_FUSE_EMIF1_INITREF_DEF_DIS,Disable EMIF1 DDR refresh and initialization sequence" "refresh and initialization sequence is enabled,refresh and initialization sequence is disabled" newline bitfld.long 0x00 18. "STD_FUSE_EMIF1_DDR3_LPDDR2N,EMIF1 DDR3" "LPDDR2 configured,DDR3 configured" newline bitfld.long 0x00 13.--17. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. "STD_FUSE_CH_SPEEDUP_DISABLE,ROM code settings for configuration header block and speedup block" "enables CH and speedup,disables CH and speedup" newline hexmask.long.word 0x00 0.--11. 1. "RESERVED," group.long 0x144++0x03 line.long 0x00 "CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT,SLICE register for emif1 and emif2" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 17. "EMIF1_NARROW_ONLY,EMIF1 operates in narrow mode to allow for data macros to be powered down to save power" "narrow mode disabled,narrow mode enabled" newline bitfld.long 0x00 16. "EMIF1_EN_ECC,EMIF1 ECC enable" "ECC is disabled,ECC is enabled" newline bitfld.long 0x00 14.--15. "EMIF1_REG_PHY_NUM_OF_SAMPLES,Controls the number of DQ samples required for read leveling" "4 samples,8 samples,16 samples,128 samples" newline bitfld.long 0x00 13. "EMIF1_REG_PHY_SEL_LOGIC,Selects an algorithm for read leveling" "Algorithm 1 is used,Algorithm 2 is used" newline bitfld.long 0x00 12. "EMIF1_REG_PHY_ALL_DQ_MPR_RD_RESP,Analysis method of DQ bits during read leveling" "if the DRAM provides a read response on only one..,if the DRAM provides a read response on all DQ.." newline bitfld.long 0x00 9.--11. "EMIF1_REG_PHY_OUTPUT_STATUS_SELECT,Selects the status to be observed on the outputs of the DDR PHYs through" "selects phy_reg_rdlvl_start_ratio[7:0],selects phy_reg_rdlvl_start_ratio[15:8],selects phy_reg_rdlvl_end_ratio[7:0],selects phy_reg_rdlvl_end_ratio[15:8],?..." newline rbitfld.long 0x00 8. "RESERVED," "0,1" newline bitfld.long 0x00 7. "EMIF1_SDRAM_DISABLE_RESET,DDR3 SDRAM reset disable" "DDR3 SDRAM reset signal is enabled,DDR3 SDRAM reset signal is disabled" newline bitfld.long 0x00 5.--6. "EMIF1_PHY_RD_LOCAL_ODT,Control of ODT (on - die termination) settings for the device DDR I/Os" "ODT disabled,60 Ohms,80 Ohms 0x3 =120 Ohms,?..." newline bitfld.long 0x00 4. "RESERVED," "0,1" newline bitfld.long 0x00 3. "EMIF1_DFI_CLOCK_PHASE_CTRL,EMIF_FICLK clock phase control (shifting by 180)" "0,1" newline bitfld.long 0x00 2. "EMIF1_EN_SLICE_2,Enable command PHY 2" "0,1" newline bitfld.long 0x00 1. "EMIF1_EN_SLICE_1,Enable command PHY 1" "0,1" newline bitfld.long 0x00 0. "EMIF1_EN_SLICE_0,Enable command PHY 0" "0,1" rgroup.long 0x14C++0x03 line.long 0x00 "CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT_1," group.long 0x164++0x03 line.long 0x00 "CTRL_WKUP_LDOSRAM_CORE_VOLTAGE_CTRL,Core SRAM LDO Control register" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 26. "LDOSRAMCORE_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value" "LDOSRAMCORE_RETMODE_MUX_CTRL_0,LDOSRAMCORE_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x00 21.--25. "LDOSRAMCORE_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "LDOSRAMCORE_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10. "LDOSRAMCORE_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value" "LDOSRAMCORE_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x00 5.--9. "LDOSRAMCORE_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "LDOSRAMCORE_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x200++0x17 line.long 0x00 "CTRL_WKUP_STD_FUSE_DIE_ID_0,Die ID Register : Part 0" line.long 0x04 "CTRL_WKUP_ID_CODE,ID_CODE Key Register" line.long 0x08 "CTRL_WKUP_STD_FUSE_DIE_ID_1,Die ID Register : Part 1" line.long 0x0C "CTRL_WKUP_STD_FUSE_DIE_ID_2,Die ID Register : Part 2" line.long 0x10 "CTRL_WKUP_STD_FUSE_DIE_ID_3,Die ID Register : Part 3" line.long 0x14 "CTRL_WKUP_STD_FUSE_PROD_ID_0,Prod ID Register : Part 0" group.long 0x5AC++0x03 line.long 0x00 "CTRL_WKUP_CONTROL_XTAL_OSCILLATOR,XTAL OSCILLATOR control" bitfld.long 0x00 31. "OSCILLATOR0_BOOST,Fast startup control of OSC0" "Fast startup is disabled,Fast startup is enabled" newline bitfld.long 0x00 30. "OSCILLATOR0_OS_OUT,Oscillator output of OSC0" "low to high transition in BOOST mode,BOOST is disabled" newline bitfld.long 0x00 29. "OSCILLATOR1_BOOST,Fast startup control of OSC1" "Fast startup is disabled,Fast startup is enabled" newline bitfld.long 0x00 28. "OSCILLATOR1_OS_OUT,Oscillator output of OSC1" "low to high transition in BOOST mode,BOOST is disabled" newline hexmask.long 0x00 0.--27. 1. "RESERVED," group.long 0x5C8++0x0F line.long 0x00 "CTRL_WKUP_EFUSE_1,EFUSE compensation 1" bitfld.long 0x00 31. "DDRDIFF_PTV_NORTH_SIDE_N5," "0,1" newline bitfld.long 0x00 30. "DDRDIFF_PTV_NORTH_SIDE_N4," "0,1" newline bitfld.long 0x00 29. "DDRDIFF_PTV_NORTH_SIDE_N3," "0,1" newline bitfld.long 0x00 28. "DDRDIFF_PTV_NORTH_SIDE_N2," "0,1" newline bitfld.long 0x00 27. "DDRDIFF_PTV_NORTH_SIDE_N1," "0,1" newline bitfld.long 0x00 26. "DDRDIFF_PTV_NORTH_SIDE_N0," "0,1" newline bitfld.long 0x00 25. "DDRDIFF_PTV_NORTH_SIDE_P5," "0,1" newline bitfld.long 0x00 24. "DDRDIFF_PTV_NORTH_SIDE_P4," "0,1" newline bitfld.long 0x00 23. "DDRDIFF_PTV_NORTH_SIDE_P3," "0,1" newline bitfld.long 0x00 22. "DDRDIFF_PTV_NORTH_SIDE_P2," "0,1" newline bitfld.long 0x00 21. "DDRDIFF_PTV_NORTH_SIDE_P1," "0,1" newline bitfld.long 0x00 20. "DDRDIFF_PTV_NORTH_SIDE_P0," "0,1" newline bitfld.long 0x00 19. "DDRDIFF_PTV_EAST_SIDE_N5," "0,1" newline bitfld.long 0x00 18. "DDRDIFF_PTV_EAST_SIDE_N4," "0,1" newline bitfld.long 0x00 17. "DDRDIFF_PTV_EAST_SIDE_N3," "0,1" newline bitfld.long 0x00 16. "DDRDIFF_PTV_EAST_SIDE_N2," "0,1" newline bitfld.long 0x00 15. "DDRDIFF_PTV_EAST_SIDE_N1," "0,1" newline bitfld.long 0x00 14. "DDRDIFF_PTV_EAST_SIDE_N0," "0,1" newline bitfld.long 0x00 13. "DDRDIFF_PTV_EAST_SIDE_P5," "0,1" newline bitfld.long 0x00 12. "DDRDIFF_PTV_EAST_SIDE_P4," "0,1" newline bitfld.long 0x00 11. "DDRDIFF_PTV_EAST_SIDE_P3," "0,1" newline bitfld.long 0x00 10. "DDRDIFF_PTV_EAST_SIDE_P2," "0,1" newline bitfld.long 0x00 9. "DDRDIFF_PTV_EAST_SIDE_P1," "0,1" newline bitfld.long 0x00 8. "DDRDIFF_PTV_EAST_SIDE_P0," "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," line.long 0x04 "CTRL_WKUP_EFUSE_2,EFUSE compensation 2" bitfld.long 0x04 31. "DDRDIFF_PTV_SOUTH_SIDE_N5," "0,1" newline bitfld.long 0x04 30. "DDRDIFF_PTV_SOUTH_SIDE_N4," "0,1" newline bitfld.long 0x04 29. "DDRDIFF_PTV_SOUTH_SIDE_N3," "0,1" newline bitfld.long 0x04 28. "DDRDIFF_PTV_SOUTH_SIDE_N2," "0,1" newline bitfld.long 0x04 27. "DDRDIFF_PTV_SOUTH_SIDE_N1," "0,1" newline bitfld.long 0x04 26. "DDRDIFF_PTV_SOUTH_SIDE_N0," "0,1" newline bitfld.long 0x04 25. "DDRDIFF_PTV_SOUTH_SIDE_P5," "0,1" newline bitfld.long 0x04 24. "DDRDIFF_PTV_SOUTH_SIDE_P4," "0,1" newline bitfld.long 0x04 23. "DDRDIFF_PTV_SOUTH_SIDE_P3," "0,1" newline bitfld.long 0x04 22. "DDRDIFF_PTV_SOUTH_SIDE_P2," "0,1" newline bitfld.long 0x04 21. "DDRDIFF_PTV_SOUTH_SIDE_P1," "0,1" newline bitfld.long 0x04 20. "DDRDIFF_PTV_SOUTH_SIDE_P0," "0,1" newline bitfld.long 0x04 19. "DDRDIFF_PTV_WEST_SIDE_N5," "0,1" newline bitfld.long 0x04 18. "DDRDIFF_PTV_WEST_SIDE_N4," "0,1" newline bitfld.long 0x04 17. "DDRDIFF_PTV_WEST_SIDE_N3," "0,1" newline bitfld.long 0x04 16. "DDRDIFF_PTV_WEST_SIDE_N2," "0,1" newline bitfld.long 0x04 15. "DDRDIFF_PTV_WEST_SIDE_N1," "0,1" newline bitfld.long 0x04 14. "DDRDIFF_PTV_WEST_SIDE_N0," "0,1" newline bitfld.long 0x04 13. "DDRDIFF_PTV_WEST_SIDE_P5," "0,1" newline bitfld.long 0x04 12. "DDRDIFF_PTV_WEST_SIDE_P4," "0,1" newline bitfld.long 0x04 11. "DDRDIFF_PTV_WEST_SIDE_P3," "0,1" newline bitfld.long 0x04 10. "DDRDIFF_PTV_WEST_SIDE_P2," "0,1" newline bitfld.long 0x04 9. "DDRDIFF_PTV_WEST_SIDE_P1," "0,1" newline bitfld.long 0x04 8. "DDRDIFF_PTV_WEST_SIDE_P0," "0,1" newline hexmask.long.byte 0x04 0.--7. 1. "RESERVED," line.long 0x08 "CTRL_WKUP_EFUSE_3,EFUSE compensation 3" bitfld.long 0x08 31. "DDRSE_PTV_NORTH_SIDE_N5," "0,1" newline bitfld.long 0x08 30. "DDRSE_PTV_NORTH_SIDE_N4," "0,1" newline bitfld.long 0x08 29. "DDRSE_PTV_NORTH_SIDE_N3," "0,1" newline bitfld.long 0x08 28. "DDRSE_PTV_NORTH_SIDE_N2," "0,1" newline bitfld.long 0x08 27. "DDRSE_PTV_NORTH_SIDE_N1," "0,1" newline bitfld.long 0x08 26. "DDRSE_PTV_NORTH_SIDE_N0," "0,1" newline bitfld.long 0x08 25. "DDRSE_PTV_NORTH_SIDE_P5," "0,1" newline bitfld.long 0x08 24. "DDRSE_PTV_NORTH_SIDE_P4," "0,1" newline bitfld.long 0x08 23. "DDRSE_PTV_NORTH_SIDE_P3," "0,1" newline bitfld.long 0x08 22. "DDRSE_PTV_NORTH_SIDE_P2," "0,1" newline bitfld.long 0x08 21. "DDRSE_PTV_NORTH_SIDE_P1," "0,1" newline bitfld.long 0x08 20. "DDRSE_PTV_NORTH_SIDE_P0," "0,1" newline bitfld.long 0x08 19. "DDRSE_PTV_EAST_SIDE_N5," "0,1" newline bitfld.long 0x08 18. "DDRSE_PTV_EAST_SIDE_N4," "0,1" newline bitfld.long 0x08 17. "DDRSE_PTV_EAST_SIDE_N3," "0,1" newline bitfld.long 0x08 16. "DDRSE_PTV_EAST_SIDE_N2," "0,1" newline bitfld.long 0x08 15. "DDRSE_PTV_EAST_SIDE_N1," "0,1" newline bitfld.long 0x08 14. "DDRSE_PTV_EAST_SIDE_N0," "0,1" newline bitfld.long 0x08 13. "DDRSE_PTV_EAST_SIDE_P5," "0,1" newline bitfld.long 0x08 12. "DDRSE_PTV_EAST_SIDE_P4," "0,1" newline bitfld.long 0x08 11. "DDRSE_PTV_EAST_SIDE_P3," "0,1" newline bitfld.long 0x08 10. "DDRSE_PTV_EAST_SIDE_P2," "0,1" newline bitfld.long 0x08 9. "DDRSE_PTV_EAST_SIDE_P1," "0,1" newline bitfld.long 0x08 8. "DDRSE_PTV_EAST_SIDE_P0," "0,1" newline hexmask.long.byte 0x08 0.--7. 1. "RESERVED," line.long 0x0C "CTRL_WKUP_EFUSE_4,EFUSE compensation 4" bitfld.long 0x0C 31. "DDRSE_PTV_SOUTH_SIDE_N5," "0,1" newline bitfld.long 0x0C 30. "DDRSE_PTV_SOUTH_SIDE_N4," "0,1" newline bitfld.long 0x0C 29. "DDRSE_PTV_SOUTH_SIDE_N3," "0,1" newline bitfld.long 0x0C 28. "DDRSE_PTV_SOUTH_SIDE_N2," "0,1" newline bitfld.long 0x0C 27. "DDRSE_PTV_SOUTH_SIDE_N1," "0,1" newline bitfld.long 0x0C 26. "DDRSE_PTV_SOUTH_SIDE_N0," "0,1" newline bitfld.long 0x0C 25. "DDRSE_PTV_SOUTH_SIDE_P5," "0,1" newline bitfld.long 0x0C 24. "DDRSE_PTV_SOUTH_SIDE_P4," "0,1" newline bitfld.long 0x0C 23. "DDRSE_PTV_SOUTH_SIDE_P3," "0,1" newline bitfld.long 0x0C 22. "DDRSE_PTV_SOUTH_SIDE_P2," "0,1" newline bitfld.long 0x0C 21. "DDRSE_PTV_SOUTH_SIDE_P1," "0,1" newline bitfld.long 0x0C 20. "DDRSE_PTV_SOUTH_SIDE_P0," "0,1" newline bitfld.long 0x0C 19. "DDRSE_PTV_WEST_SIDE_N5," "0,1" newline bitfld.long 0x0C 18. "DDRSE_PTV_WEST_SIDE_N4," "0,1" newline bitfld.long 0x0C 17. "DDRSE_PTV_WEST_SIDE_N3," "0,1" newline bitfld.long 0x0C 16. "DDRSE_PTV_WEST_SIDE_N2," "0,1" newline bitfld.long 0x0C 15. "DDRSE_PTV_WEST_SIDE_N1," "0,1" newline bitfld.long 0x0C 14. "DDRSE_PTV_WEST_SIDE_N0," "0,1" newline bitfld.long 0x0C 13. "DDRSE_PTV_WEST_SIDE_P5," "0,1" newline bitfld.long 0x0C 12. "DDRSE_PTV_WEST_SIDE_P4," "0,1" newline bitfld.long 0x0C 11. "DDRSE_PTV_WEST_SIDE_P3," "0,1" newline bitfld.long 0x0C 10. "DDRSE_PTV_WEST_SIDE_P2," "0,1" newline bitfld.long 0x0C 9. "DDRSE_PTV_WEST_SIDE_P1," "0,1" newline bitfld.long 0x0C 8. "DDRSE_PTV_WEST_SIDE_P0," "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED," group.long 0x5F8++0x03 line.long 0x00 "CTRL_WKUP_EFUSE_13," bitfld.long 0x00 31. "SDIO1833_PTV_N5," "0,1" newline bitfld.long 0x00 30. "SDIO1833_PTV_N4," "0,1" newline bitfld.long 0x00 29. "SDIO1833_PTV_N3," "0,1" newline bitfld.long 0x00 28. "SDIO1833_PTV_N2," "0,1" newline bitfld.long 0x00 27. "SDIO1833_PTV_N1," "0,1" newline bitfld.long 0x00 26. "SDIO1833_PTV_N0," "0,1" newline bitfld.long 0x00 25. "SDIO1833_PTV_P5," "0,1" newline bitfld.long 0x00 24. "SDIO1833_PTV_P4," "0,1" newline bitfld.long 0x00 23. "SDIO1833_PTV_P3," "0,1" newline bitfld.long 0x00 22. "SDIO1833_PTV_P2," "0,1" newline bitfld.long 0x00 21. "SDIO1833_PTV_P1," "0,1" newline bitfld.long 0x00 20. "SDIO1833_PTV_P0," "0,1" newline hexmask.long.tbyte 0x00 0.--19. 1. "RESERVED," group.long 0x700++0x7F line.long 0x00 "CTRL_WKUP_CONF_DEBUG_SEL_TST_0,This register is used to select an observable signal for WKUP observability line 0" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "MODE,Selects one of the following signals to be available on WKUP observability line 0" "MODE_0,MODE_1" line.long 0x04 "CTRL_WKUP_CONF_DEBUG_SEL_TST_1,This register is used to select an observable signal for WKUP observability line 1" hexmask.long 0x04 1.--31. 1. "RESERVED," newline bitfld.long 0x04 0. "MODE,Selects one of the following signals to be available on WKUP observability line 1" "MODE_0,MODE_1" line.long 0x08 "CTRL_WKUP_CONF_DEBUG_SEL_TST_2,This register is used to select an observable signal for WKUP observability line 2" hexmask.long 0x08 1.--31. 1. "RESERVED," newline bitfld.long 0x08 0. "MODE,Selects one of the following signals to be available on WKUP observability line 2" "MODE_0,MODE_1" line.long 0x0C "CTRL_WKUP_CONF_DEBUG_SEL_TST_3,This register is used to select an observable signal for WKUP observability line 3" hexmask.long 0x0C 1.--31. 1. "RESERVED," newline bitfld.long 0x0C 0. "MODE,Selects one of the following signals to be available on WKUP observability line 3" "MODE_0,MODE_1" line.long 0x10 "CTRL_WKUP_CONF_DEBUG_SEL_TST_4,This register is used to select an observable signal for WKUP observability line 4" hexmask.long 0x10 1.--31. 1. "RESERVED," newline bitfld.long 0x10 0. "MODE,Selects one of the following signals to be available on WKUP observability line 4" "MODE_0,MODE_1" line.long 0x14 "CTRL_WKUP_CONF_DEBUG_SEL_TST_5,This register is used to select an observable signal for WKUP observability line 5" hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "MODE,Selects one of the following signals to be available on WKUP observability line 5" "MODE_0,MODE_1" line.long 0x18 "CTRL_WKUP_CONF_DEBUG_SEL_TST_6,This register is used to select an observable signal for WKUP observability line 6" hexmask.long 0x18 1.--31. 1. "RESERVED," newline bitfld.long 0x18 0. "MODE,Selects one of the following signals to be available on WKUP observability line 6" "MODE_0,MODE_1" line.long 0x1C "CTRL_WKUP_CONF_DEBUG_SEL_TST_7,This register is used to select an observable signal for WKUP observability line 7" hexmask.long 0x1C 1.--31. 1. "RESERVED," newline bitfld.long 0x1C 0. "MODE,Selects one of the following signals to be available on WKUP observability line 7" "MODE_0,MODE_1" line.long 0x20 "CTRL_WKUP_CONF_DEBUG_SEL_TST_8,This register is used to select an observable signal for WKUP observability line 8" hexmask.long 0x20 1.--31. 1. "RESERVED," newline bitfld.long 0x20 0. "MODE,Selects one of the following signals to be available on WKUP observability line 8" "MODE_0,MODE_1" line.long 0x24 "CTRL_WKUP_CONF_DEBUG_SEL_TST_9,This register is used to select an observable signal for WKUP observability line 9" hexmask.long 0x24 1.--31. 1. "RESERVED," newline bitfld.long 0x24 0. "MODE,Selects one of the following signals to be available on WKUP observability line 9" "MODE_0,MODE_1" line.long 0x28 "CTRL_WKUP_CONF_DEBUG_SEL_TST_10,This register is used to select an observable signal for WKUP observability line 10" hexmask.long 0x28 1.--31. 1. "RESERVED," newline bitfld.long 0x28 0. "MODE,Selects one of the following signals to be available on WKUP observability line 10" "MODE_0,MODE_1" line.long 0x2C "CTRL_WKUP_CONF_DEBUG_SEL_TST_11,This register is used to select an observable signal for WKUP observability line 11" hexmask.long 0x2C 1.--31. 1. "RESERVED," newline bitfld.long 0x2C 0. "MODE,Selects one of the following signals to be available on WKUP observability line 11" "MODE_0,MODE_1" line.long 0x30 "CTRL_WKUP_CONF_DEBUG_SEL_TST_12,This register is used to select an observable signal for WKUP observability line 12" hexmask.long 0x30 1.--31. 1. "RESERVED," newline bitfld.long 0x30 0. "MODE,Selects one of the following signals to be available on WKUP observability line 12" "MODE_0,MODE_1" line.long 0x34 "CTRL_WKUP_CONF_DEBUG_SEL_TST_13,This register is used to select an observable signal for WKUP observability line 13" hexmask.long 0x34 1.--31. 1. "RESERVED," newline bitfld.long 0x34 0. "MODE,Selects one of the following signals to be available on WKUP observability line 13" "MODE_0,MODE_1" line.long 0x38 "CTRL_WKUP_CONF_DEBUG_SEL_TST_14,This register is used to select an observable signal for WKUP observability line 14" hexmask.long 0x38 1.--31. 1. "RESERVED," newline bitfld.long 0x38 0. "MODE,Selects one of the following signals to be available on WKUP observability line 14" "MODE_0,MODE_1" line.long 0x3C "CTRL_WKUP_CONF_DEBUG_SEL_TST_15,This register is used to select an observable signal for WKUP observability line 15" hexmask.long 0x3C 1.--31. 1. "RESERVED," newline bitfld.long 0x3C 0. "MODE,Selects one of the following signals to be available on WKUP observability line 15" "MODE_0,MODE_1" line.long 0x40 "CTRL_WKUP_CONF_DEBUG_SEL_TST_16,This register is used to select an observable signal for WKUP observability line 16" hexmask.long 0x40 1.--31. 1. "RESERVED," newline bitfld.long 0x40 0. "MODE,Selects one of the following signals to be available on WKUP observability line 16" "MODE_0,MODE_1" line.long 0x44 "CTRL_WKUP_CONF_DEBUG_SEL_TST_17,This register is used to select an observable signal for WKUP observability line 17" hexmask.long 0x44 1.--31. 1. "RESERVED," newline bitfld.long 0x44 0. "MODE,Selects one of the following signals to be available on WKUP observability line 17" "MODE_0,MODE_1" line.long 0x48 "CTRL_WKUP_CONF_DEBUG_SEL_TST_18,This register is used to select an observable signal for WKUP observability line 18" hexmask.long 0x48 1.--31. 1. "RESERVED," newline bitfld.long 0x48 0. "MODE,Selects one of the following signals to be available on WKUP observability line 18" "MODE_0,MODE_1" line.long 0x4C "CTRL_WKUP_CONF_DEBUG_SEL_TST_19,This register is used to select an observable signal for WKUP observability line 19" hexmask.long 0x4C 1.--31. 1. "RESERVED," newline bitfld.long 0x4C 0. "MODE,Selects one of the following signals to be available on WKUP observability line 19" "MODE_0,MODE_1" line.long 0x50 "CTRL_WKUP_CONF_DEBUG_SEL_TST_20,This register is used to select an observable signal for WKUP observability line 20" hexmask.long 0x50 1.--31. 1. "RESERVED," newline bitfld.long 0x50 0. "MODE,Selects one of the following signals to be available on WKUP observability line 20" "MODE_0,MODE_1" line.long 0x54 "CTRL_WKUP_CONF_DEBUG_SEL_TST_21,This register is used to select an observable signal for WKUP observability line 21" hexmask.long 0x54 1.--31. 1. "RESERVED," newline bitfld.long 0x54 0. "MODE,Selects one of the following signals to be available on WKUP observability line 21" "MODE_0,MODE_1" line.long 0x58 "CTRL_WKUP_CONF_DEBUG_SEL_TST_22,This register is used to select an observable signal for WKUP observability line 22" hexmask.long 0x58 1.--31. 1. "RESERVED," newline bitfld.long 0x58 0. "MODE,Selects one of the following signals to be available on WKUP observability line 22" "MODE_0,MODE_1" line.long 0x5C "CTRL_WKUP_CONF_DEBUG_SEL_TST_23,This register is used to select an observable signal for WKUP observability line 23" hexmask.long 0x5C 1.--31. 1. "RESERVED," newline bitfld.long 0x5C 0. "MODE,Selects one of the following signals to be available on WKUP observability line 23" "MODE_0,MODE_1" line.long 0x60 "CTRL_WKUP_CONF_DEBUG_SEL_TST_24,This register is used to select an observable signal for WKUP observability line 24" hexmask.long 0x60 1.--31. 1. "RESERVED," newline bitfld.long 0x60 0. "MODE,Selects one of the following signals to be available on WKUP observability line 24" "MODE_0,MODE_1" line.long 0x64 "CTRL_WKUP_CONF_DEBUG_SEL_TST_25,This register is used to select an observable signal for WKUP observability line 25" hexmask.long 0x64 1.--31. 1. "RESERVED," newline bitfld.long 0x64 0. "MODE,Selects one of the following signals to be available on WKUP observability line 25" "MODE_0,MODE_1" line.long 0x68 "CTRL_WKUP_CONF_DEBUG_SEL_TST_26,This register is used to select an observable signal for WKUP observability line 26" hexmask.long 0x68 1.--31. 1. "RESERVED," newline bitfld.long 0x68 0. "MODE,Selects one of the following signals to be available on WKUP observability line 26" "MODE_0,MODE_1" line.long 0x6C "CTRL_WKUP_CONF_DEBUG_SEL_TST_27,This register is used to select an observable signal for WKUP observability line 27" hexmask.long 0x6C 1.--31. 1. "RESERVED," newline bitfld.long 0x6C 0. "MODE,Selects one of the following signals to be available on WKUP observability line 27" "MODE_0,MODE_1" line.long 0x70 "CTRL_WKUP_CONF_DEBUG_SEL_TST_28,This register is used to select an observable signal for WKUP observability line 28" hexmask.long 0x70 1.--31. 1. "RESERVED," newline bitfld.long 0x70 0. "MODE,Selects one of the following signals to be available on WKUP observability line 28" "MODE_0,MODE_1" line.long 0x74 "CTRL_WKUP_CONF_DEBUG_SEL_TST_29,This register is used to select an observable signal for WKUP observability line 29" hexmask.long 0x74 1.--31. 1. "RESERVED," newline bitfld.long 0x74 0. "MODE,Selects one of the following signals to be available on WKUP observability line 29" "MODE_0,MODE_1" line.long 0x78 "CTRL_WKUP_CONF_DEBUG_SEL_TST_30,This register is used to select an observable signal for WKUP observability line 30" hexmask.long 0x78 1.--31. 1. "RESERVED," newline bitfld.long 0x78 0. "MODE,Selects one of the following signals to be available on WKUP observability line 30" "MODE_0,MODE_1" line.long 0x7C "CTRL_WKUP_CONF_DEBUG_SEL_TST_31,This register is used to select an observable signal for WKUP observability line 31" hexmask.long 0x7C 1.--31. 1. "RESERVED," newline bitfld.long 0x7C 0. "MODE,Selects one of the following signals to be available on WKUP observability line 31" "MODE_0,MODE_1" width 0x0B tree.end tree "CTRL_MODULE_WKUP_TARG" base ad:0x4AE0D000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CUSTEFUSE_CM_CORE" base ad:0x4A009600 group.long 0x00++0x03 line.long 0x00 "CM_CUSTEFUSE_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline rbitfld.long 0x00 9. "CLKACTIVITY_CUSTEFUSE_SYS_GFCLK,This field indicates the state of the Cust_Efuse_SYS_CLK clock input of the domain" "CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_0,CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_CUSTEFUSE_L4_GICLK,This field indicates the state of the L4_CUSTEFUSE_GICLK clock input of the domain" "CLKACTIVITY_CUSTEFUSE_L4_GICLK_0,CLKACTIVITY_CUSTEFUSE_L4_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the CUSTEFUSE clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x20++0x03 line.long 0x00 "CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL,This register manages the CUSTEFUSE clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "CUSTEFUSE_PRM" base ad:0x4AE07600 group.long 0x00++0x07 line.long 0x00 "PM_CUSTEFUSE_PWRSTCTRL,This register controls the CUSTEFUSE power state to reach upon a domain sleep transition" hexmask.long 0x00 5.--31. 1. "RESERVED," bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_CUSTEFUSE_PWRSTST,This register provides a status on the current CUSTEFUSE power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.tbyte 0x04 3.--19. 1. "RESERVED," rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT,This register contains dedicated CUSTEFUSE module context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end repeat 2. (list 2. 1. )(list ad:0x48480000 ad:0x4AE3C000 ) tree "DCAN$1" base $2 group.long 0x00++0x17 line.long 0x00 "DCAN_CTL,DCAN control register NOTE: The Bus-Off recovery sequence (refer to CAN specification) cannot be shortened by setting or resetting INIT bit" rbitfld.long 0x00 26.--31. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 25. "WUBA,Automatic wake up on bus activity when in local power-down mode" "WUBA_0,WUBA_1" newline bitfld.long 0x00 24. "PDR,Request for local low power-down mode" "PDR_0,PDR_1" rbitfld.long 0x00 21.--23. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. "DE3,Enable DMA request line for IF3" "DE3_0,DE3_1" bitfld.long 0x00 19. "DE2,Enable DMA request line for IF2" "DE2_0,DE2_1" newline bitfld.long 0x00 18. "DE1,Enable DMA request line for IF1" "DE1_0,DE1_1" bitfld.long 0x00 17. "IE1,Interrupt line 1 enable" "IE1_0,IE1_1" newline bitfld.long 0x00 16. "INITDBG,Internal init state while debug access" "INITDBG_0,INITDBG_1" bitfld.long 0x00 15. "SWR,Software reset enable" "SWR_0,SWR_1" newline rbitfld.long 0x00 14. "RESERVED,This bit is always read as 0" "0,1" bitfld.long 0x00 10.--13. "PMD," "?,?,?,?,?,PMD_5,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 9. "ABO,Auto-Bus-On enable" "ABO_0,ABO_1" bitfld.long 0x00 8. "IDS,Interruption debug support enable" "IDS_0,IDS_1" newline bitfld.long 0x00 7. "TEST,Test mode enable" "TEST_0,TEST_1" bitfld.long 0x00 6. "CCE,Configuration change enable" "CCE_0,CCE_1" newline bitfld.long 0x00 5. "DAR,Disable automatic retransmission" "DAR_0,DAR_1" rbitfld.long 0x00 4. "RESERVED,This bit is always read as 0" "0,1" newline bitfld.long 0x00 3. "EIE,Error interrupt enable" "EIE_0,EIE_1" bitfld.long 0x00 2. "SIE,Status change interrupt enable" "SIE_0,SIE_1" newline bitfld.long 0x00 1. "IE0,Interrupt line 0 enable" "IE0_0,IE0_1" bitfld.long 0x00 0. "INIT,Initialization" "INIT_0,INIT_1" line.long 0x04 "DCAN_ES,Error and Status Register Interrupts are generated by bits PER. BOFF and EWARN (if EIE bit in is 1) and by bits WAKEUPPND. RXOK. TXOK. and LEC (if SIE bit in is 1)" hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED,These bits are always read as 0" rbitfld.long 0x04 10. "PDA,Local power-down mode acknowledge" "PDA_0,PDA_1" newline rbitfld.long 0x04 9. "WAKEUPPND,Wake up pending" "WAKEUPPND_0,WAKEUPPND_1" bitfld.long 0x04 8. "PER,Parity error detected" "PER_0_w,PER_1_w" newline rbitfld.long 0x04 7. "BOFF,Bus-Off state" "BOFF_0,BOFF_1" rbitfld.long 0x04 6. "EWARN,Warning state" "EWARN_0,EWARN_1" newline rbitfld.long 0x04 5. "EPASS,Error passive state" "EPASS_0,EPASS_1" rbitfld.long 0x04 4. "RXOK,Received a message successfully" "RXOK_0,RXOK_1" newline rbitfld.long 0x04 3. "TXOK,Transmitted a message successfully" "TXOK_0,TXOK_1" rbitfld.long 0x04 0.--2. "LEC,Last error code" "LEC_0,LEC_1,LEC_2,LEC_3,LEC_4,LEC_5,LEC_6,LEC_7" line.long 0x08 "DCAN_ERRC,Error Counter Register" hexmask.long.word 0x08 16.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x08 15. "RP,Receive error passive" "RP_0,RP_1" newline hexmask.long.byte 0x08 8.--14. 1. "REC,Receive error counter" hexmask.long.byte 0x08 0.--7. 1. "TEC,Transmit error counter" line.long 0x0C "DCAN_BTR,Bit timing register This register is only writable if CCE and INIT bits in the are set" hexmask.long.word 0x0C 20.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x0C 16.--19. "BRPE,Baud rate prescaler extension.Valid programmed values are 0 to 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x0C 15. "RESERVED,These bits are always read as 0" "0,1" bitfld.long 0x0C 12.--14. "TSEG2,Time segment after the sample pointValid programmed values are 0 to 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 8.--11. "TSEG1,Time segment before the sample pointValid programmed values are 1 to15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 6.--7. "SJW,Synchronization Jump WidthValid programmed values are 0 to 3" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "BRP,Baud rate prescalerValue by which the CAN_CLK frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "DCAN_INT,Interrupt register" hexmask.long.byte 0x10 24.--31. 1. "RESERVED,These bits are always read as 0" hexmask.long.byte 0x10 16.--23. 1. "INT1ID,Interrupt 1 Identifier (indicates the message object with the highest pending interrupt)0x01-0x80: Number of message object which caused the interrupt" newline hexmask.long.word 0x10 0.--15. 1. "INT0ID,Interrupt Identifier (the number here indicates the source of the interrupt)0x0001-0x0080: Number of message object which caused the interrupt" line.long 0x14 "DCAN_TEST,Test Register For all test modes. the TEST bit in control register needs to be set to 1" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x14 9. "RDA,RAM direct access enable" "RDA_0,RDA_1" newline bitfld.long 0x14 8. "EXL,External loopback mode" "EXL_0,EXL_1" rbitfld.long 0x14 7. "RX,Receive pin" "RX_0,RX_1" newline bitfld.long 0x14 5.--6. "TX,Control of CAN_TX pin" "TX_0,TX_1,TX_2,TX_3" bitfld.long 0x14 4. "LBACK,Loopback mode" "LBACK_0,LBACK_1" newline bitfld.long 0x14 3. "SILENT,Silent mode" "SILENT_0,SILENT_1" rbitfld.long 0x14 0.--2. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7" rgroup.long 0x1C++0x17 line.long 0x00 "DCAN_PERR,Parity Error Code Register If a parity error is detected. the PER flag will be set in" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x00 8.--10. "WORD_NUMBER,Word number where parity error has been detectedRDA word number (1 to 5) of the message object (according to the message RAM representation in RDA mode)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Message object number where parity error has been detected (0x01-0x80)" line.long 0x04 "DCAN_REL,Core revision register" line.long 0x08 "DCAN_ECCDIAG,ECC Diagnostic Register" hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0.--3. "ECCDIAG,SECDED diagnostic mode enable/disable" "?,?,?,?,?,Diagnostic mode is enabled,?,?,?,?,Diagnostic mode is disabled single and double..,?..." line.long 0x0C "DCAN_ECCDIAG_STAT,ECC Diagnostic Status Register" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 8. "DEFLG_DIAG,Double bit error flag diagnostic" "The bit is unchanged,The bit is cleared to 0" newline hexmask.long.byte 0x0C 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x0C 0. "SEFLG_DIAG,Single bit error flag diagnostic" "The bit is unchanged,The bit is cleared to 0" line.long 0x10 "DCAN_ECC_CS,ECC Control and Status Register" rbitfld.long 0x10 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. "SBE_EVT_EN,Enable/disable SECDED single bit error event (CAN_SERR signal)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x10 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 16.--19. "ECCMODE,Enable/disable SECDED single bit error correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED,Reserved" bitfld.long 0x10 8. "DEFLG,Double bit error flag" "The bit is unchanged,The bit is cleared to 0" newline hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x10 0. "SEFLG,Single bit error flag" "The bit is unchanged,The bit is cleared to 0" line.long 0x14 "DCAN_ECC_SERR,ECC Single Bit Error Code Register" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 0.--7. 1. "MESSAGE_NUMBER,Message object number where ECC single bit error has been detected" group.long 0x80++0x53 line.long 0x00 "DCAN_ABOTR,Auto-Bus-On Time Register On write access to the while Auto-Bus-On timer is running. the Auto-Bus-On procedure will be aborted" line.long 0x04 "DCAN_TXRQ_X,Transmission Request X Register The software can detect if one or more bits in the different transmission request registers are set" hexmask.long.word 0x04 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x04 14.--15. "TXRQSTREG8,Transmission request bits (aggregate for 113-128 message objects)" "0,1,2,3" newline bitfld.long 0x04 12.--13. "TXRQSTREG7,Transmission request bits (aggregate for 97-112 message objects)" "0,1,2,3" bitfld.long 0x04 10.--11. "TXRQSTREG6,Transmission request bits (aggregate for 81-96 message objects)" "0,1,2,3" newline bitfld.long 0x04 8.--9. "TXRQSTREG5,Transmission request bits (aggregate for 65-80 message objects)" "0,1,2,3" bitfld.long 0x04 6.--7. "TXRQSTREG4,Transmission request bits (aggregate for 49-64 message objects)" "0,1,2,3" newline bitfld.long 0x04 4.--5. "TXRQSTREG3,Transmission request bits (aggregate for 33-48 message objects)" "0,1,2,3" bitfld.long 0x04 2.--3. "TXRQSTREG2,Transmission request bits (aggregate for 17-32 message objects)" "0,1,2,3" newline bitfld.long 0x04 0.--1. "TXRQSTREG1,Transmission request bits (aggregate for 1-16 message objects)" "0,1,2,3" line.long 0x08 "DCAN_TXRQ12,Transmission Request Register This register holds the TxRqst bits of the implemented message objects" line.long 0x0C "DCAN_TXRQ34,Transmission Request Register This register holds the TxRqst bits of the implemented message objects" line.long 0x10 "DCAN_TXRQ56,Transmission Request Register This register holds the TxRqst bits of the implemented message objects" line.long 0x14 "DCAN_TXRQ78,Transmission Request Register This register holds the TxRqst bits of the implemented message objects" line.long 0x18 "DCAN_NWDAT_X,New Data X Register With the new data X register. the software can detect if one or more bits in the different new data registers are set" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14.--15. "NEWDATREG8,New data bits (aggregate for 113-128 message objects)" "0,1,2,3" newline bitfld.long 0x18 12.--13. "NEWDATREG7,New data bits (aggregate for 97-112 message objects)" "0,1,2,3" bitfld.long 0x18 10.--11. "NEWDATREG6,New data bits (aggregate for 81-96 message objects)" "0,1,2,3" newline bitfld.long 0x18 8.--9. "NEWDATREG5,New data bits (aggregate for 65-80 message objects)" "0,1,2,3" bitfld.long 0x18 6.--7. "NEWDATREG4,New data bits (aggregate for 49-64 message objects)" "0,1,2,3" newline bitfld.long 0x18 4.--5. "NEWDATREG3,New data bits (aggregate for 33-48 message objects)" "0,1,2,3" bitfld.long 0x18 2.--3. "NEWDATREG2,New data bits (aggregate for 17-32 message objects)" "0,1,2,3" newline bitfld.long 0x18 0.--1. "NEWDATREG1,New data bits (aggregate for 1-16 message objects)" "0,1,2,3" line.long 0x1C "DCAN_NWDAT12,New Data Register This register hold the NewDat bits of the implemented message objects" line.long 0x20 "DCAN_NWDAT34,New Data Register This register hold the NewDat bits of the implemented message objects" line.long 0x24 "DCAN_NWDAT56,New Data Register This register hold the NewDat bits of the implemented message objects" line.long 0x28 "DCAN_NWDAT78,New Data Register This register hold the NewDat bits of the implemented message objects" line.long 0x2C "DCAN_INTPND_X,Interrupt Pending X Register With the interrupt pending X register. the software can detect if one or more bits in the different interrupt pending registers are set" hexmask.long.word 0x2C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 14.--15. "INTPNDREG8,Interrupt Pending bits (aggregate for 113-128 message objects)" "0,1,2,3" newline bitfld.long 0x2C 12.--13. "INTPNDREG7,Interrupt Pending bits (aggregate for 97-112 message objects)" "0,1,2,3" bitfld.long 0x2C 10.--11. "INTPNDREG6,Interrupt Pendingbits (aggregate for 81-96 message objects)" "0,1,2,3" newline bitfld.long 0x2C 8.--9. "INTPNDREG5,Interrupt Pending bits (aggregate for 65-80 message objects)" "0,1,2,3" bitfld.long 0x2C 6.--7. "INTPNDREG4,Interrupt Pending bits (aggregate for 49-64 message objects)" "0,1,2,3" newline bitfld.long 0x2C 4.--5. "INTPNDREG3,Interrupt Pending bits (aggregate for 33-48 message objects)" "0,1,2,3" bitfld.long 0x2C 2.--3. "INTPNDREG2,Interrupt Pending bits (aggregate for 17-32 message objects)" "0,1,2,3" newline bitfld.long 0x2C 0.--1. "INTPNDREG1,Interrupt Pending bits (aggregate for 1-16 message objects)" "0,1,2,3" line.long 0x30 "DCAN_INTPND12,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects" line.long 0x34 "DCAN_INTPND34,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects" line.long 0x38 "DCAN_INTPND56,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects" line.long 0x3C "DCAN_INTPND78,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects" line.long 0x40 "DCAN_MSGVAL_X,Message Valid X Register With the message valid X register. the software can detect if one or more bits in the different message valid registers are set" hexmask.long.word 0x40 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x40 14.--15. "MSGVALREG8,Message valid bits (aggregate for 113-128 message objects)" "0,1,2,3" newline bitfld.long 0x40 12.--13. "MSGVALREG7,Message valid bits (aggregate for 97-112 message objects)" "0,1,2,3" bitfld.long 0x40 10.--11. "MSGVALREG6,Message valid bits (aggregate for 81-96 message objects)" "0,1,2,3" newline bitfld.long 0x40 8.--9. "MSGVALREG5,Message valid bits (aggregate for 65-80 message objects)" "0,1,2,3" bitfld.long 0x40 6.--7. "MSGVALREG4,Message valid bits (aggregate for 49-64 message objects)" "0,1,2,3" newline bitfld.long 0x40 4.--5. "MSGVALREG3,Message valid bits (aggregate for 33-48 message objects)" "0,1,2,3" bitfld.long 0x40 2.--3. "MSGVALREG2,Message valid bits (aggregate for 17-32 message objects)" "0,1,2,3" newline bitfld.long 0x40 0.--1. "MSGVALREG1,Message valid bits (aggregate for 1-16 message objects)" "0,1,2,3" line.long 0x44 "DCAN_MSGVAL12,Message Valid Register These registers hold the MsgVal bits of the implemented message objects" line.long 0x48 "DCAN_MSGVAL34,Message Valid Register These registers hold the MsgVal bits of the implemented message objects" line.long 0x4C "DCAN_MSGVAL56,Message Valid Register These registers hold the MsgVal bits of the implemented message objects" line.long 0x50 "DCAN_MSGVAL78,Message Valid Register These registers hold the MsgVal bits of the implemented message objects" group.long 0xD8++0x0F line.long 0x00 "DCAN_INTMUX12,Interrupt Multiplexer Register The IntMux flag determine for each message object. which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set" line.long 0x04 "DCAN_INTMUX34,Interrupt Multiplexer Register The IntMux flag determine for each message object. which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set" line.long 0x08 "DCAN_INTMUX56,Interrupt Multiplexer Register The IntMux flag determine for each message object. which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set" line.long 0x0C "DCAN_INTMUX78,Interrupt Multiplexer Register The IntMux flag determine for each message object. which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set" group.long 0x100++0x17 line.long 0x00 "DCAN_IF1CMD,IF1 Command Register The IF1 Command Register () configure and initiate the transfer between the IF1 register set and the message RAM" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x00 23. "WR_RD,Write/Read" "WR_RD_0,WR_RD_1" newline bitfld.long 0x00 22. "MASK,Access mask bits" "MASK_0,MASK_1" bitfld.long 0x00 21. "ARB,Access arbitration bits" "ARB_0,ARB_1" newline bitfld.long 0x00 20. "CONTROL,Access control bitsIf the TXRQST_NEWDAT bit in this register(Bit [18]) is set the TXRQST/ NEWDAT bits in the will be ignored" "CONTROL_0,CONTROL_1" bitfld.long 0x00 19. "CLRINTPND,Clear interrupt pending bit" "CLRINTPND_0,CLRINTPND_1" newline bitfld.long 0x00 18. "TXRQST_NEWDAT,Access transmission request bitNote: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register the TxRqst/NewDat bits in the message object will be set to one independent of the values in" "TXRQST_NEWDAT_0,TXRQST_NEWDAT_1" bitfld.long 0x00 17. "DATA_A,Access Data Bytes" "DATA_A_0,DATA_A_1" newline bitfld.long 0x00 16. "DATA_B,Access Data Bytes" "DATA_B_0,DATA_B_1" bitfld.long 0x00 15. "BUSY,Busy flagThis bit is set to one after the message number has been written to bits [7:0] MESSAGE_NUMBER" "BUSY_0,BUSY_1" newline bitfld.long 0x00 14. "DMAACTIVE,Activation of DMA feature for subsequent internal IF1 updateThe DMA request remains active until the first read or write to one of the IF1 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one" "DMAACTIVE_0,DMAACTIVE_1" rbitfld.long 0x00 8.--13. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Number of message object in message RAM which is used for data transfer0x01-0x80: Valid message numbers" line.long 0x04 "DCAN_IF1MSK,IF1 Mask Register The bits of the IF1/IF2 mask registers mirror the mask bits of a message object" bitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit ('standard') identifiers are used for a message object the identifiers of received data frames are written into bits ID[28:18]" "MXTD_0,MXTD_1" bitfld.long 0x04 30. "MDIR,Mask Message Direction" "MDIR_0,MDIR_1" newline rbitfld.long 0x04 29. "RESERVED,This bit is always read as 1" "0,1" hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask" line.long 0x08 "DCAN_IF1ARB,IF1 arbitration register The Arbitration bits ID[28:0]. XTD. and DIR are used to define the identifier and type of outgoing messages and (together with the mask bits MSK[28:0]. MXTD. and MDIR) for acceptance filtering of incoming messages" bitfld.long 0x08 31. "MSGVAL,Message validThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in" "MSGVAL_0,MSGVAL_1" bitfld.long 0x08 30. "XTD,Extended identifier" "XTD_0,XTD_1" newline bitfld.long 0x08 29. "DIR,Message direction" "DIR_0,DIR_1" hexmask.long 0x08 0.--28. 1. "ID,Message identifierID[28:0]: 29-bit identifier (extended frame)" line.long 0x0C "DCAN_IF1MCTL,IF1 Message Control Register The bits of the IF1/IF2 message control registers mirror the message control bits of a message object" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x0C 15. "NEWDAT,New data" "NEWDAT_0,NEWDAT_1" newline bitfld.long 0x0C 14. "MSGLST,Message lost (only valid for message objects with direction = receive)" "MSGLST_0,MSGLST_1" bitfld.long 0x0C 13. "INTPND,Interrupt pending" "INTPND_0,INTPND_1" newline bitfld.long 0x0C 12. "UMASK,Use acceptance maskIf the UMASK bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "UMASK_0,UMASK_1" bitfld.long 0x0C 11. "TXIE,Transmit interrupt enable" "TXIE_0,TXIE_1" newline bitfld.long 0x0C 10. "RXIE,Receive interrupt enable" "RXIE_0,RXIE_1" bitfld.long 0x0C 9. "RMTEN,Remote enable" "RMTEN_0,RMTEN_1" newline bitfld.long 0x0C 8. "TXRQST,Transmit request" "TXRQST_0,TXRQST_1" bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "EOB_0,EOB_1" newline rbitfld.long 0x0C 4.--6. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--3. "DLC,Data length code0-8: Data frame has 0-8 data bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DCAN_IF1DATA,IF1 Data A Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3" hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2" newline hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1" hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0" line.long 0x14 "DCAN_IF1DATB,IF1 Data B Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7" hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6" newline hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5" hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4" group.long 0x120++0x17 line.long 0x00 "DCAN_IF2CMD,IF2 Command Register The IF2 Command Register () configure and initiate the transfer between the IF2 register set and the message RAM" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x00 23. "WR_RD,Write/Read" "WR_RD_0,WR_RD_1" newline bitfld.long 0x00 22. "MASK,Access mask bits" "MASK_0,MASK_1" bitfld.long 0x00 21. "ARB,Access arbitration bits" "ARB_0,ARB_1" newline bitfld.long 0x00 20. "CONTROL,Access control bitsIf the TXRQST_NEWDAT bit in this register(Bit [18]) is set the TXRQST/ NEWDAT bits in the/ will be ignored" "CONTROL_0,CONTROL_1" bitfld.long 0x00 19. "CLRINTPND,Clear interrupt pending bit" "CLRINTPND_0,CLRINTPND_1" newline bitfld.long 0x00 18. "TXRQST_NEWDAT,Access transmission request bitNote: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register the TxRqst/NewDat bits in the message object will be set to one independent of the values in/" "TXRQST_NEWDAT_0,TXRQST_NEWDAT_1" bitfld.long 0x00 17. "DATA_A,Access Data Bytes" "DATA_A_0,DATA_A_1" newline bitfld.long 0x00 16. "DATA_B,Access Data Bytes" "DATA_B_0,DATA_B_1" bitfld.long 0x00 15. "BUSY,Busy flagThis bit is set to one after the message number has been written to bits [7:0] MESSAGE_NUMBER" "BUSY_0,BUSY_1" newline bitfld.long 0x00 14. "DMAACTIVE,Activation of DMA feature for subsequent internal IF2 updateThe DMA request remains active until the first read or write to one of the IF2 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one" "DMAACTIVE_0,DMAACTIVE_1" rbitfld.long 0x00 8.--13. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Number of message object in message RAM which is used for data transfer0x01-0x80: Valid message numbers" line.long 0x04 "DCAN_IF2MSK,IF2 Mask Register The bits of the IF1/IF2 mask registers mirror the mask bits of a message object" bitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit ('standard') identifiers are used for a message object the identifiers of received data frames are written into bits ID[28:18]" "MXTD_0,MXTD_1" bitfld.long 0x04 30. "MDIR,Mask Message Direction" "MDIR_0,MDIR_1" newline rbitfld.long 0x04 29. "RESERVED,This bit is always read as 1" "0,1" hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask" line.long 0x08 "DCAN_IF2ARB,IF2 arbitration register The Arbitration bits ID[28:0]. XTD. and DIR are used to define the identifier and type of outgoing messages and (together with the mask bits MSK[28:0]. MXTD. and MDIR) for acceptance filtering of incoming messages" bitfld.long 0x08 31. "MSGVAL,Message validThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in" "MSGVAL_0,MSGVAL_1" bitfld.long 0x08 30. "XTD,Extended identifier" "XTD_0,XTD_1" newline bitfld.long 0x08 29. "DIR,Message direction" "DIR_0,DIR_1" hexmask.long 0x08 0.--28. 1. "ID,Message identifierID[28:0]: 29-bit identifier (extended frame)" line.long 0x0C "DCAN_IF2MCTL,IF2 Message Control Register The bits of the IF1/IF2 message control registers mirror the message control bits of a message object" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x0C 15. "NEWDAT,New data" "NEWDAT_0,NEWDAT_1" newline bitfld.long 0x0C 14. "MSGLST,Message lost (only valid for message objects with direction = receive)" "MSGLST_0,MSGLST_1" bitfld.long 0x0C 13. "INTPND,Interrupt pending" "INTPND_0,INTPND_1" newline bitfld.long 0x0C 12. "UMASK,Use acceptance maskIf the UMask bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "UMASK_0,UMASK_1" bitfld.long 0x0C 11. "TXIE,Transmit interrupt enable" "TXIE_0,TXIE_1" newline bitfld.long 0x0C 10. "RXIE,Receive interrupt enable" "RXIE_0,RXIE_1" bitfld.long 0x0C 9. "RMTEN,Remote enable" "RMTEN_0,RMTEN_1" newline bitfld.long 0x0C 8. "TXRQST,Transmit request" "TXRQST_0,TXRQST_1" bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "EOB_0,EOB_1" newline rbitfld.long 0x0C 4.--6. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--3. "DLC,Data length code0-8: Data frame has 0-8 data bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DCAN_IF2DATA,IF2 Data A Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3" hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2" newline hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1" hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0" line.long 0x14 "DCAN_IF2DATB,IF2 Data B Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7" hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6" newline hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5" hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4" group.long 0x140++0x17 line.long 0x00 "DCAN_IF3OBS,IF3 Observation Register The IF3 register set can automatically be updated with received message objects without the need to initiate the transfer from message RAM by software (Additional information can be found in NOTE: If IF3 Update.." hexmask.long.word 0x00 16.--31. 1. "RESERVED,These bits are always read as 0" rbitfld.long 0x00 15. "IF3_UPD,IF3 Update Data" "IF3_UPD_0,IF3_UPD_1" newline rbitfld.long 0x00 13.--14. "RESERVED,These bits are always read as 0" "0,1,2,3" rbitfld.long 0x00 12. "IF3_SDB,IF3 Status of Data B read access" "IF3_SDB_0,IF3_SDB_1" newline rbitfld.long 0x00 11. "IF3_SDA,IF3 Status of Data A read access" "IF3_SDA_0,IF3_SDA_1" rbitfld.long 0x00 10. "IF3_SC,IF3 Status of control bits read access" "IF3_SC_0,IF3_SC_1" newline rbitfld.long 0x00 9. "IF3_SA,IF3 Status of Arbitration data read access" "IF3_SA_0,IF3_SA_1" rbitfld.long 0x00 8. "IF3_SM,IF3 Status of Mask data read access" "IF3_SM_0,IF3_SM_1" newline rbitfld.long 0x00 5.--7. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "DATAB,Data B read observation" "DATAB_0,DATAB_1" newline bitfld.long 0x00 3. "DATAA,Data A read observation" "DATAA_0,DATAA_1" bitfld.long 0x00 2. "CTRL,Ctrl read observation" "CTRL_0,CTRL_1" newline bitfld.long 0x00 1. "ARB,Arbitration data read observation" "ARB_0,ARB_1" bitfld.long 0x00 0. "MASK,Mask data read observation" "MASK_0,MASK_1" line.long 0x04 "DCAN_IF3MSK,IF3 Mask Register" rbitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit ('standard') identifiers are used for a message object the identifiers of received data frames are written into bits ID[28:18]" "MXTD_0,MXTD_1" rbitfld.long 0x04 30. "MDIR,Mask Message Direction" "MDIR_0,MDIR_1" newline rbitfld.long 0x04 29. "RESERVED,These bits are always read as 1" "0,1" hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask" line.long 0x08 "DCAN_IF3ARB,IF3 Arbitration Register" bitfld.long 0x08 31. "MSGVAL,Message ValidThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in" "MSGVAL_0,MSGVAL_1" bitfld.long 0x08 30. "XTD,Extended Identifier" "XTD_0,XTD_1" newline bitfld.long 0x08 29. "DIR,Message Direction" "DIR_0,DIR_1" hexmask.long 0x08 0.--28. 1. "ID,Message IdentifierID[28:0]: 29-bit Identifier ('extended frame')" line.long 0x0C "DCAN_IF3MCTL,IF3 Message Control Register" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x0C 15. "NEWDAT,New Data" "NEWDAT_0,NEWDAT_1" newline bitfld.long 0x0C 14. "MSGLST,Message Lost (only valid for message objects with direction = receive)" "MSGLST_0,MSGLST_1" bitfld.long 0x0C 13. "INTPND,Interrupt Pending" "INTPND_0,INTPND_1" newline bitfld.long 0x0C 12. "UMASK,Use Acceptance MaskIf the UMASK bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "UMASK_0,UMASK_1" bitfld.long 0x0C 11. "TXIE,Transmit Interrupt enable" "TXIE_0,TXIE_1" newline bitfld.long 0x0C 10. "RXIE,Receive Interrupt enable" "RXIE_0,RXIE_1" bitfld.long 0x0C 9. "RMTEN,Remote enable" "RMTEN_0,RMTEN_1" newline bitfld.long 0x0C 8. "TXRQST,Transmit Request" "TXRQST_0,TXRQST_1" bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "EOB_0,EOB_1" newline bitfld.long 0x0C 4.--6. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--3. "DLC,Data Length Code0-8: Data frame has 0-8 data bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DCAN_IF3DATA,IF3 Data A The data bytes of CAN messages are stored in the IF3 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3" hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2" newline hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1" hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0" line.long 0x14 "DCAN_IF3DATB,IF3 Data B The data bytes of CAN messages are stored in the IF3 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7" hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6" newline hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5" hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4" group.long 0x160++0x0F line.long 0x00 "DCAN_IF3UPD12,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object" line.long 0x04 "DCAN_IF3UPD34,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object" line.long 0x08 "DCAN_IF3UPD56,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object" line.long 0x0C "DCAN_IF3UPD78,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object" group.long 0x1E0++0x07 line.long 0x00 "DCAN_TIOC,TX I/O Control Register The CAN_TX pin of the DCAN module can be used as general purpose IO pin if CAN function is not needed" hexmask.long.word 0x00 19.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x00 18. "PU,CAN_TX pull up/pull down select" "PU_0,PU_1" newline bitfld.long 0x00 17. "PD,CAN_TX pull disable" "PD_0,PD_1" bitfld.long 0x00 16. "OD,CAN_TX open drain enable" "OD_0,OD_1" newline hexmask.long.word 0x00 4.--15. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x00 3. "FUNC,CAN_TX function" "FUNC_0,FUNC_1" newline bitfld.long 0x00 2. "DIR,CAN_TX data direction" "DIR_0,DIR_1" bitfld.long 0x00 1. "OUT,CAN_TX data out" "OUT_0,OUT_1" newline bitfld.long 0x00 0. "IN,CAN_TX data inNote: When CAN_TX pin is connected to a CAN transceiver an external pullup resistor has to be used to ensure that the CAN bus will not be disturbed (e.g. while reset of the DCAN module)" "IN_0,IN_1" line.long 0x04 "DCAN_RIOC,RX I/O Control Register The CAN_RX pin of the DCAN_module can be used as general purpose IO pin if CAN function is not needed" hexmask.long.word 0x04 19.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x04 18. "PU,CAN_RX pull up/pull down select" "PU_0,PU_1" newline bitfld.long 0x04 17. "PD,CAN_RX pull disable" "PD_0,PD_1" bitfld.long 0x04 16. "OD,CAN_RX open drain enable" "OD_0,OD_1" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x04 3. "FUNC,CAN_RX function" "FUNC_0,FUNC_1" newline bitfld.long 0x04 2. "DIR,CAN_RX data direction" "DIR_0,DIR_1" bitfld.long 0x04 1. "OUT,CAN_RX data out" "OUT_0,OUT_1" newline bitfld.long 0x04 0. "IN,CAN_RX data in" "IN_0,IN_1" width 0x0B tree.end repeat.end tree "DCAN1_TARG" base ad:0x4AE3E000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCAN2_TARG" base ad:0x48482000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end repeat 7. (list 6. 7. 5. 1. 2. 3. 4. )(list ad:0x48848000 ad:0x4884A000 ad:0x4884C000 ad:0x48856000 ad:0x48858000 ad:0x4885A000 ad:0x4885C000 ) tree "DCC$1" base $2 group.long 0x00++0x2B line.long 0x00 "DCCGCTRL,DCC Global Control RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x00 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag inDCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..." bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DCCREV,DCC Revision IDNOTE: For SR1.0 physical addresses. see" line.long 0x08 "DCCCNTSEED0,Count0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x08 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)" line.long 0x0C "DCCVALIDSEED0,Valid0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x0C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x10 "DCCCNTSEED1,Count1 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x10 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)" line.long 0x14 "DCCSTAT,DCC Status RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long 0x14 2.--31. 1. "RES," bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag" newline bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occurred" "no effect,clear the error flag" line.long 0x18 "DCCCNT0,Count0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x18 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0" line.long 0x1C "DCCVALID0,Valid0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x1C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0" line.long 0x20 "DCCCNT1,Count1 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x20 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1" line.long 0x24 "DCCCLKSRC1,Clock Source Selection Register" hexmask.long.word 0x24 16.--31. 1. "RES0,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 4.--11. 1. "RES1,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 0.--3. "CLKSRC,This field specifies the clock source for COUNT1 when the KEY field enables this feature" "Clock source 0 is selected for COUNT1,Clock source 1 is selected for COUNT1,Clock source 2 is selected for COUNT1,Clock source 3 is selected for COUNT1,Clock source 4 is selected for COUNT1,Clock source 5 is selected for COUNT1,Clock source 6 is selected for COUNT1,Clock source 7 is selected for COUNT1,?..." line.long 0x28 "DCCCLKSRC0,Clock Source Selection Register" hexmask.long 0x28 4.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for COUNT0" "?,?,?,?,?,Clock0[2] is selected as source for COUNT0,?,?,?,?,Clock0[1] is selected as source for COUNT0,?..." width 0x0B tree.end repeat.end tree "DCC1_SR2" base ad:0x48828000 group.long 0x00++0x2B line.long 0x00 "DCCGCTRL,DCC Global Control RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x00 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag inDCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..." bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DCCREV,DCC Revision IDNOTE: For SR1.0 physical addresses. see" line.long 0x08 "DCCCNTSEED0,Count0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x08 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)" line.long 0x0C "DCCVALIDSEED0,Valid0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x0C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x10 "DCCCNTSEED1,Count1 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x10 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)" line.long 0x14 "DCCSTAT,DCC Status RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long 0x14 2.--31. 1. "RES," bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag" newline bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occurred" "no effect,clear the error flag" line.long 0x18 "DCCCNT0,Count0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x18 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0" line.long 0x1C "DCCVALID0,Valid0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x1C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0" line.long 0x20 "DCCCNT1,Count1 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x20 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1" line.long 0x24 "DCCCLKSRC1,Clock Source Selection Register" hexmask.long.word 0x24 16.--31. 1. "RES0,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 4.--11. 1. "RES1,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 0.--3. "CLKSRC,This field specifies the clock source for COUNT1 when the KEY field enables this feature" "Clock source 0 is selected for COUNT1,Clock source 1 is selected for COUNT1,Clock source 2 is selected for COUNT1,Clock source 3 is selected for COUNT1,Clock source 4 is selected for COUNT1,Clock source 5 is selected for COUNT1,Clock source 6 is selected for COUNT1,Clock source 7 is selected for COUNT1,?..." line.long 0x28 "DCCCLKSRC0,Clock Source Selection Register" hexmask.long 0x28 4.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for COUNT0" "?,?,?,?,?,Clock0[2] is selected as source for COUNT0,?,?,?,?,Clock0[1] is selected as source for COUNT0,?..." width 0x0B tree.end tree "DCC1_TARG" base ad:0x48856000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC1_TARG_SR2" base ad:0x48829000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC2_SR2" base ad:0x4882A000 group.long 0x00++0x2B line.long 0x00 "DCCGCTRL,DCC Global Control RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x00 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag inDCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..." bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DCCREV,DCC Revision IDNOTE: For SR1.0 physical addresses. see" line.long 0x08 "DCCCNTSEED0,Count0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x08 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)" line.long 0x0C "DCCVALIDSEED0,Valid0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x0C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x10 "DCCCNTSEED1,Count1 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x10 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)" line.long 0x14 "DCCSTAT,DCC Status RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long 0x14 2.--31. 1. "RES," bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag" newline bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occurred" "no effect,clear the error flag" line.long 0x18 "DCCCNT0,Count0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x18 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0" line.long 0x1C "DCCVALID0,Valid0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x1C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0" line.long 0x20 "DCCCNT1,Count1 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x20 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1" line.long 0x24 "DCCCLKSRC1,Clock Source Selection Register" hexmask.long.word 0x24 16.--31. 1. "RES0,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 4.--11. 1. "RES1,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 0.--3. "CLKSRC,This field specifies the clock source for COUNT1 when the KEY field enables this feature" "Clock source 0 is selected for COUNT1,Clock source 1 is selected for COUNT1,Clock source 2 is selected for COUNT1,Clock source 3 is selected for COUNT1,Clock source 4 is selected for COUNT1,Clock source 5 is selected for COUNT1,Clock source 6 is selected for COUNT1,Clock source 7 is selected for COUNT1,?..." line.long 0x28 "DCCCLKSRC0,Clock Source Selection Register" hexmask.long 0x28 4.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for COUNT0" "?,?,?,?,?,Clock0[2] is selected as source for COUNT0,?,?,?,?,Clock0[1] is selected as source for COUNT0,?..." width 0x0B tree.end tree "DCC2_TARG" base ad:0x48858000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC2_TARG_SR2" base ad:0x4882B000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC3_SR2" base ad:0x4882C000 group.long 0x00++0x2B line.long 0x00 "DCCGCTRL,DCC Global Control RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x00 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag inDCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..." bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DCCREV,DCC Revision IDNOTE: For SR1.0 physical addresses. see" line.long 0x08 "DCCCNTSEED0,Count0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x08 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)" line.long 0x0C "DCCVALIDSEED0,Valid0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x0C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x10 "DCCCNTSEED1,Count1 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x10 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)" line.long 0x14 "DCCSTAT,DCC Status RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long 0x14 2.--31. 1. "RES," bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag" newline bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occurred" "no effect,clear the error flag" line.long 0x18 "DCCCNT0,Count0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x18 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0" line.long 0x1C "DCCVALID0,Valid0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x1C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0" line.long 0x20 "DCCCNT1,Count1 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x20 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1" line.long 0x24 "DCCCLKSRC1,Clock Source Selection Register" hexmask.long.word 0x24 16.--31. 1. "RES0,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 4.--11. 1. "RES1,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 0.--3. "CLKSRC,This field specifies the clock source for COUNT1 when the KEY field enables this feature" "Clock source 0 is selected for COUNT1,Clock source 1 is selected for COUNT1,Clock source 2 is selected for COUNT1,Clock source 3 is selected for COUNT1,Clock source 4 is selected for COUNT1,Clock source 5 is selected for COUNT1,Clock source 6 is selected for COUNT1,Clock source 7 is selected for COUNT1,?..." line.long 0x28 "DCCCLKSRC0,Clock Source Selection Register" hexmask.long 0x28 4.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for COUNT0" "?,?,?,?,?,Clock0[2] is selected as source for COUNT0,?,?,?,?,Clock0[1] is selected as source for COUNT0,?..." width 0x0B tree.end tree "DCC3_TARG" base ad:0x4885A000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC3_TARG_SR2" base ad:0x4882D000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC4_SR2" base ad:0x4882E000 group.long 0x00++0x2B line.long 0x00 "DCCGCTRL,DCC Global Control RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x00 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag inDCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..." bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DCCREV,DCC Revision IDNOTE: For SR1.0 physical addresses. see" line.long 0x08 "DCCCNTSEED0,Count0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x08 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)" line.long 0x0C "DCCVALIDSEED0,Valid0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x0C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x10 "DCCCNTSEED1,Count1 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x10 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)" line.long 0x14 "DCCSTAT,DCC Status RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long 0x14 2.--31. 1. "RES," bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag" newline bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occurred" "no effect,clear the error flag" line.long 0x18 "DCCCNT0,Count0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x18 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0" line.long 0x1C "DCCVALID0,Valid0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x1C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0" line.long 0x20 "DCCCNT1,Count1 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x20 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1" line.long 0x24 "DCCCLKSRC1,Clock Source Selection Register" hexmask.long.word 0x24 16.--31. 1. "RES0,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 4.--11. 1. "RES1,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 0.--3. "CLKSRC,This field specifies the clock source for COUNT1 when the KEY field enables this feature" "Clock source 0 is selected for COUNT1,Clock source 1 is selected for COUNT1,Clock source 2 is selected for COUNT1,Clock source 3 is selected for COUNT1,Clock source 4 is selected for COUNT1,Clock source 5 is selected for COUNT1,Clock source 6 is selected for COUNT1,Clock source 7 is selected for COUNT1,?..." line.long 0x28 "DCCCLKSRC0,Clock Source Selection Register" hexmask.long 0x28 4.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for COUNT0" "?,?,?,?,?,Clock0[2] is selected as source for COUNT0,?,?,?,?,Clock0[1] is selected as source for COUNT0,?..." width 0x0B tree.end tree "DCC4_TARG" base ad:0x4885C000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC4_TARG_SR2" base ad:0x4882F000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC5_SR2" base ad:0x4884E000 group.long 0x00++0x2B line.long 0x00 "DCCGCTRL,DCC Global Control RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x00 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag inDCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..." bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DCCREV,DCC Revision IDNOTE: For SR1.0 physical addresses. see" line.long 0x08 "DCCCNTSEED0,Count0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x08 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)" line.long 0x0C "DCCVALIDSEED0,Valid0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x0C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x10 "DCCCNTSEED1,Count1 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x10 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)" line.long 0x14 "DCCSTAT,DCC Status RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long 0x14 2.--31. 1. "RES," bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag" newline bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occurred" "no effect,clear the error flag" line.long 0x18 "DCCCNT0,Count0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x18 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0" line.long 0x1C "DCCVALID0,Valid0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x1C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0" line.long 0x20 "DCCCNT1,Count1 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x20 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1" line.long 0x24 "DCCCLKSRC1,Clock Source Selection Register" hexmask.long.word 0x24 16.--31. 1. "RES0,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 4.--11. 1. "RES1,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 0.--3. "CLKSRC,This field specifies the clock source for COUNT1 when the KEY field enables this feature" "Clock source 0 is selected for COUNT1,Clock source 1 is selected for COUNT1,Clock source 2 is selected for COUNT1,Clock source 3 is selected for COUNT1,Clock source 4 is selected for COUNT1,Clock source 5 is selected for COUNT1,Clock source 6 is selected for COUNT1,Clock source 7 is selected for COUNT1,?..." line.long 0x28 "DCCCLKSRC0,Clock Source Selection Register" hexmask.long 0x28 4.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for COUNT0" "?,?,?,?,?,Clock0[2] is selected as source for COUNT0,?,?,?,?,Clock0[1] is selected as source for COUNT0,?..." width 0x0B tree.end tree "DCC5_TARG" base ad:0x4884C000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC5_TARG_SR2" base ad:0x4884F000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC6_SR2" base ad:0x48852000 group.long 0x00++0x2B line.long 0x00 "DCCGCTRL,DCC Global Control RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x00 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag inDCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..." bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DCCREV,DCC Revision IDNOTE: For SR1.0 physical addresses. see" line.long 0x08 "DCCCNTSEED0,Count0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x08 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)" line.long 0x0C "DCCVALIDSEED0,Valid0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x0C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x10 "DCCCNTSEED1,Count1 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x10 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)" line.long 0x14 "DCCSTAT,DCC Status RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long 0x14 2.--31. 1. "RES," bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag" newline bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occurred" "no effect,clear the error flag" line.long 0x18 "DCCCNT0,Count0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x18 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0" line.long 0x1C "DCCVALID0,Valid0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x1C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0" line.long 0x20 "DCCCNT1,Count1 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x20 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1" line.long 0x24 "DCCCLKSRC1,Clock Source Selection Register" hexmask.long.word 0x24 16.--31. 1. "RES0,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 4.--11. 1. "RES1,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 0.--3. "CLKSRC,This field specifies the clock source for COUNT1 when the KEY field enables this feature" "Clock source 0 is selected for COUNT1,Clock source 1 is selected for COUNT1,Clock source 2 is selected for COUNT1,Clock source 3 is selected for COUNT1,Clock source 4 is selected for COUNT1,Clock source 5 is selected for COUNT1,Clock source 6 is selected for COUNT1,Clock source 7 is selected for COUNT1,?..." line.long 0x28 "DCCCLKSRC0,Clock Source Selection Register" hexmask.long 0x28 4.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for COUNT0" "?,?,?,?,?,Clock0[2] is selected as source for COUNT0,?,?,?,?,Clock0[1] is selected as source for COUNT0,?..." width 0x0B tree.end tree "DCC6_TARG" base ad:0x48848000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC6_TARG_SR2" base ad:0x48853000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC7_SR2" base ad:0x48854000 group.long 0x00++0x2B line.long 0x00 "DCCGCTRL,DCC Global Control RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x00 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag inDCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..." bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DCCREV,DCC Revision IDNOTE: For SR1.0 physical addresses. see" line.long 0x08 "DCCCNTSEED0,Count0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x08 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)" line.long 0x0C "DCCVALIDSEED0,Valid0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x0C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x10 "DCCCNTSEED1,Count1 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x10 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)" line.long 0x14 "DCCSTAT,DCC Status RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long 0x14 2.--31. 1. "RES," bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag" newline bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occurred" "no effect,clear the error flag" line.long 0x18 "DCCCNT0,Count0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x18 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0" line.long 0x1C "DCCVALID0,Valid0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x1C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0" line.long 0x20 "DCCCNT1,Count1 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x20 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1" line.long 0x24 "DCCCLKSRC1,Clock Source Selection Register" hexmask.long.word 0x24 16.--31. 1. "RES0,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 4.--11. 1. "RES1,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 0.--3. "CLKSRC,This field specifies the clock source for COUNT1 when the KEY field enables this feature" "Clock source 0 is selected for COUNT1,Clock source 1 is selected for COUNT1,Clock source 2 is selected for COUNT1,Clock source 3 is selected for COUNT1,Clock source 4 is selected for COUNT1,Clock source 5 is selected for COUNT1,Clock source 6 is selected for COUNT1,Clock source 7 is selected for COUNT1,?..." line.long 0x28 "DCCCLKSRC0,Clock Source Selection Register" hexmask.long 0x28 4.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for COUNT0" "?,?,?,?,?,Clock0[2] is selected as source for COUNT0,?,?,?,?,Clock0[1] is selected as source for COUNT0,?..." width 0x0B tree.end tree "DCC7_TARG" base ad:0x4884A000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC7_TARG_SR2" base ad:0x48855000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DEBUGSS_CT_TBR_FW" base ad:0x4A224000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x07 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" line.long 0x04 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x04 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x04 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x04 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "DEBUGSS_CT_TBR_FW_CFG_TARG" base ad:0x4A225000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DEBUGSS_CT_TBR_TARG" base ad:0x45000300 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "DEVICE_PRM" base ad:0x4AE07D00 group.long 0x00++0x103 line.long 0x00 "PRM_RSTCTRL,Global software cold and warm reset control" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "RST_GLOBAL_COLD_SW,Global COLD software reset control" "RST_GLOBAL_COLD_SW_0,RST_GLOBAL_COLD_SW_1" newline bitfld.long 0x00 0. "RST_GLOBAL_WARM_SW,Global WARM software reset control" "RST_GLOBAL_WARM_SW_0,RST_GLOBAL_WARM_SW_1" line.long 0x04 "PRM_RSTST,This register logs the global reset sources" hexmask.long.word 0x04 17.--31. 1. "RESERVED," bitfld.long 0x04 16. "TSHUT_IVA_RST,TSHUT_IVA warm reset event" "TSHUT_IVA_RST_0,TSHUT_IVA_RST_1" newline bitfld.long 0x04 15. "TSHUT_DSPEVE_RST,TSHUT_DSPEVE warm reset event" "TSHUT_DSPEVE_RST_0,TSHUT_DSPEVE_RST_1" bitfld.long 0x04 14. "LLI_RST,LLI warm reset event" "LLI_RST_0,LLI_RST_1" newline bitfld.long 0x04 13. "TSHUT_CORE_RST,TSHUT_CORE warm reset event" "TSHUT_CORE_RST_0,TSHUT_CORE_RST_1" bitfld.long 0x04 12. "TSHUT_MM_RST,TSHUT_GPU warm reset event" "TSHUT_MM_RST_0,TSHUT_MM_RST_1" newline bitfld.long 0x04 11. "TSHUT_MPU_RST,TSHUT_MPU warm reset event" "TSHUT_MPU_RST_0,TSHUT_MPU_RST_1" bitfld.long 0x04 10. "C2C_RST,C2C warm reset event" "C2C_RST_0,C2C_RST_1" newline bitfld.long 0x04 9. "ICEPICK_RST,IcePick reset event" "ICEPICK_RST_0,ICEPICK_RST_1" bitfld.long 0x04 8. "VDD_CORE_VOLT_MGR_RST,VDD_CORE voltage manager reset event This is a source of global WARM reset" "VDD_CORE_VOLT_MGR_RST_0,VDD_CORE_VOLT_MGR_RST_1" newline bitfld.long 0x04 7. "VDD_MM_VOLT_MGR_RST,VDD_MM voltage manager reset event This is a source of global WARM reset" "VDD_MM_VOLT_MGR_RST_0,VDD_MM_VOLT_MGR_RST_1" bitfld.long 0x04 6. "VDD_MPU_VOLT_MGR_RST,VDD_MPU voltage manager reset event This is a source of global WARM reset" "VDD_MPU_VOLT_MGR_RST_0,VDD_MPU_VOLT_MGR_RST_1" newline bitfld.long 0x04 5. "EXTERNAL_WARM_RST,External warm reset event" "EXTERNAL_WARM_RST_0,EXTERNAL_WARM_RST_1" bitfld.long 0x04 4. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 3. "MPU_WDT_RST,MPU Watchdog timer reset event" "MPU_WDT_RST_0,MPU_WDT_RST_1" bitfld.long 0x04 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 1. "GLOBAL_WARM_SW_RST,Global warm software reset event" "GLOBAL_WARM_SW_RST_0,GLOBAL_WARM_SW_RST_1" bitfld.long 0x04 0. "GLOBAL_COLD_RST,Power-on (cold) reset event" "GLOBAL_COLD_RST_0,GLOBAL_COLD_RST_1" line.long 0x08 "PRM_RSTTIME,Reset duration control" hexmask.long.tbyte 0x08 15.--31. 1. "RESERVED," bitfld.long 0x08 10.--14. "RSTTIME2,Power domain reset duration 2 in number of RM.SYSCLK clock cycles" "RSTTIME2_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline hexmask.long.word 0x08 0.--9. 1. "RSTTIME1,Global reset duration 1 in number of Func_32k_clk clock cycles" line.long 0x0C "PRM_CLKREQCTRL,This register allows controlling the CLKREQ signal towards SCRM" hexmask.long 0x0C 3.--31. 1. "RESERVED," bitfld.long 0x0C 0.--2. "CLKREQ_COND,Control upon which condition CLKREQ signal is de-asserted" "CLKREQ_COND_0,CLKREQ_COND_1,CLKREQ_COND_2,CLKREQ_COND_3,CLKREQ_COND_4,CLKREQ_COND_5,CLKREQ_COND_6,CLKREQ_COND_7" line.long 0x10 "PRM_VOLTCTRL,This register provides voltage domain management controls" hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED," bitfld.long 0x10 14. "VDD_MM_I2C_DISABLE,This bit allows disabling I2C interface with powerIC for MM voltage (for debug purpose only)" "VDD_MM_I2C_DISABLE_0,VDD_MM_I2C_DISABLE_1" newline bitfld.long 0x10 13. "VDD_MPU_I2C_DISABLE,This bit allows disabling I2C interface with powerIC for MPU voltage (for debug purpose only)" "VDD_MPU_I2C_DISABLE_0,VDD_MPU_I2C_DISABLE_1" bitfld.long 0x10 12. "VDD_CORE_I2C_DISABLE,This bit allows disabling I2C interface with powerIC for CORE voltage (for debug purpose only)" "VDD_CORE_I2C_DISABLE_0,VDD_CORE_I2C_DISABLE_1" newline rbitfld.long 0x10 10.--11. "RESERVED," "0,1,2,3" bitfld.long 0x10 9. "VDD_MM_PRESENCE,This bit control the presence of MM voltage in device" "VDD_MM_PRESENCE_0,VDD_MM_PRESENCE_1" newline bitfld.long 0x10 8. "VDD_MPU_PRESENCE,This bit control the presence of MPU voltage in device" "VDD_MPU_PRESENCE_0,VDD_MPU_PRESENCE_1" rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 4.--5. "AUTO_CTRL_VDD_MM_L,This bit field specifies the state to which the hardware can automatically transition the VDD_MM_L voltage domain" "AUTO_CTRL_VDD_MM_L_0,AUTO_CTRL_VDD_MM_L_1,AUTO_CTRL_VDD_MM_L_2,AUTO_CTRL_VDD_MM_L_3" bitfld.long 0x10 2.--3. "AUTO_CTRL_VDD_MPU_L,This bit field specifies the state to which the hardware can automatically transition the VDD_MPU_L voltage domain" "AUTO_CTRL_VDD_MPU_L_0,AUTO_CTRL_VDD_MPU_L_1,AUTO_CTRL_VDD_MPU_L_2,AUTO_CTRL_VDD_MPU_L_3" newline bitfld.long 0x10 0.--1. "AUTO_CTRL_VDD_CORE_L,This bit field specifies the state to which the hardware can automatically transition the VDD_CORE_L voltage domain" "AUTO_CTRL_VDD_CORE_L_0,AUTO_CTRL_VDD_CORE_L_1,AUTO_CTRL_VDD_CORE_L_2,AUTO_CTRL_VDD_CORE_L_3" line.long 0x14 "PRM_PWRREQCTRL,This register allows controlling the PWRREQ signal towards power IC" hexmask.long 0x14 2.--31. 1. "RESERVED," bitfld.long 0x14 0.--1. "PWRREQ_COND,Control upon which condition from MPU MM and CORE voltage domains PWRREQ is de-asserted" "PWRREQ_COND_0,PWRREQ_COND_1,PWRREQ_COND_2,PWRREQ_COND_3" line.long 0x18 "PRM_PSCON_COUNT,This register allows controlling 2 parameters for power state controller" hexmask.long.byte 0x18 24.--31. 1. "RESERVED," hexmask.long.byte 0x18 16.--23. 1. "HG_PONOUT_2_PGOODIN_TIME,The value 'NbCycles' set in this field determines the duration of the PONOUT to PGOODIN transition for power domain without DPS" newline hexmask.long.byte 0x18 8.--15. 1. "PONOUT_2_PGOODIN_TIME,The value 'NbCycles' set in this field determines the duration of the PONOUT to PGOODIN transition for power domain without DPS" hexmask.long.byte 0x18 0.--7. 1. "PCHARGE_TIME,Number of system clock cycles for the SRAM pre-charge duration" line.long 0x1C "PRM_IO_COUNT,This register allows controlling DDR IO isolation removal setup" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," hexmask.long.byte 0x1C 0.--7. 1. "ISO_2_ON_TIME,Determines the setup time of the DDR IOs going out of isolation" line.long 0x20 "PRM_IO_PMCTRL,This register allows controlling power management features of the IOs" hexmask.long.word 0x20 17.--31. 1. "RESERVED," bitfld.long 0x20 16. "GLOBAL_WUEN,Global IO wakeup enable" "GLOBAL_WUEN_0,GLOBAL_WUEN_1" newline rbitfld.long 0x20 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x20 9. "WUCLK_STATUS,Gives value of WUCLKOUT signal coming back from IO pad ring" "0,1" newline bitfld.long 0x20 8. "WUCLK_CTRL,Direct control on WUCLKIN signal to IO pad ring" "WUCLK_CTRL_0,WUCLK_CTRL_1" rbitfld.long 0x20 6.--7. "RESERVED," "0,1,2,3" newline rbitfld.long 0x20 5. "IO_ON_STATUS,Gives the functional status of the IO ring" "IO_ON_STATUS_0,IO_ON_STATUS_1" bitfld.long 0x20 4. "ISOOVR_EXTEND,Control non-EMIF IO isolation extension upon a device wakeup from OFF mode" "ISOOVR_EXTEND_0,ISOOVR_EXTEND_1" newline rbitfld.long 0x20 2.--3. "RESERVED," "0,1,2,3" rbitfld.long 0x20 1. "ISOCLK_STATUS,Gives value of ISOCLKOUT signal coming back from IO pad ring" "0,1" newline bitfld.long 0x20 0. "ISOCLK_OVERRIDE,Override control on ISOCLKIN signal to IO pad ring" "ISOCLK_OVERRIDE_0,ISOCLK_OVERRIDE_1" line.long 0x24 "PRM_VOLTSETUP_WARMRESET,This register provides bit-fields for specifying voltage stabilization duration upon a global warm reset" hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED," bitfld.long 0x24 8.--9. "STABLE_PRESCAL,Determines prescaler for stabilization duration counting" "STABLE_PRESCAL_0,STABLE_PRESCAL_1,STABLE_PRESCAL_2,STABLE_PRESCAL_3" newline rbitfld.long 0x24 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x24 0.--5. "STABLE_COUNT,Determines the stabilization duration of all VDD_xxx_L regulators upon a global warm reset assertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "PRM_VOLTSETUP_CORE_OFF,This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators" rbitfld.long 0x28 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 24.--25. "RAMP_DOWN_PRESCAL,Determines prescaler for ramp-down duration counting" "RAMP_DOWN_PRESCAL_0,RAMP_DOWN_PRESCAL_1,RAMP_DOWN_PRESCAL_2,RAMP_DOWN_PRESCAL_3" newline rbitfld.long 0x28 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x28 16.--21. "RAMP_DOWN_COUNT,Determines the ramp-down duration of VDD_CORE_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x28 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 8.--9. "RAMP_UP_PRESCAL,Determines prescaler for ramp-up duration counting" "RAMP_UP_PRESCAL_0,RAMP_UP_PRESCAL_1,RAMP_UP_PRESCAL_2,RAMP_UP_PRESCAL_3" newline rbitfld.long 0x28 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x28 0.--5. "RAMP_UP_COUNT,Determines the ramp-up duration of VDD_CORE_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "PRM_VOLTSETUP_MPU_OFF,This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators" rbitfld.long 0x2C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 24.--25. "RAMP_DOWN_PRESCAL,Determines prescaler for ramp-down duration counting" "RAMP_DOWN_PRESCAL_0,RAMP_DOWN_PRESCAL_1,RAMP_DOWN_PRESCAL_2,RAMP_DOWN_PRESCAL_3" newline rbitfld.long 0x2C 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x2C 16.--21. "RAMP_DOWN_COUNT,Determines the ramp-down duration of VDD_MPU_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x2C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 8.--9. "RAMP_UP_PRESCAL,Determines prescaler for ramp-up duration counting" "RAMP_UP_PRESCAL_0,RAMP_UP_PRESCAL_1,RAMP_UP_PRESCAL_2,RAMP_UP_PRESCAL_3" newline rbitfld.long 0x2C 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x2C 0.--5. "RAMP_UP_COUNT,Determines the ramp-up duration of VDD_MPU_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x30 "PRM_VOLTSETUP_MM_OFF,This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators" rbitfld.long 0x30 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 24.--25. "RAMP_DOWN_PRESCAL,Determines prescaler for ramp-down duration counting" "RAMP_DOWN_PRESCAL_0,RAMP_DOWN_PRESCAL_1,RAMP_DOWN_PRESCAL_2,RAMP_DOWN_PRESCAL_3" newline rbitfld.long 0x30 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x30 16.--21. "RAMP_DOWN_COUNT,Determines the ramp-down duration of VDD_MM_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x30 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 8.--9. "RAMP_UP_PRESCAL,Determines prescaler for ramp-up duration counting" "RAMP_UP_PRESCAL_0,RAMP_UP_PRESCAL_1,RAMP_UP_PRESCAL_2,RAMP_UP_PRESCAL_3" newline rbitfld.long 0x30 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x30 0.--5. "RAMP_UP_COUNT,Determines the ramp-up duration of VDD_MM_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x34 "PRM_VOLTSETUP_CORE_RET_SLEEP,This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators" rbitfld.long 0x34 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 24.--25. "RAMP_DOWN_PRESCAL,Determines prescaler for ramp-down duration counting" "RAMP_DOWN_PRESCAL_0,RAMP_DOWN_PRESCAL_1,RAMP_DOWN_PRESCAL_2,RAMP_DOWN_PRESCAL_3" newline rbitfld.long 0x34 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x34 16.--21. "RAMP_DOWN_COUNT,Determines the ramp-down duration of VDD_CORE_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x34 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 8.--9. "RAMP_UP_PRESCAL,Determines prescaler for ramp-up duration counting" "RAMP_UP_PRESCAL_0,RAMP_UP_PRESCAL_1,RAMP_UP_PRESCAL_2,RAMP_UP_PRESCAL_3" newline rbitfld.long 0x34 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x34 0.--5. "RAMP_UP_COUNT,Determines the ramp-up duration of VDD_CORE_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "PRM_VOLTSETUP_MPU_RET_SLEEP,This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators" rbitfld.long 0x38 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 24.--25. "RAMP_DOWN_PRESCAL,Determines prescaler for ramp-down duration counting" "RAMP_DOWN_PRESCAL_0,RAMP_DOWN_PRESCAL_1,RAMP_DOWN_PRESCAL_2,RAMP_DOWN_PRESCAL_3" newline rbitfld.long 0x38 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x38 16.--21. "RAMP_DOWN_COUNT,Determines the ramp-down duration of VDD_MPU_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x38 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 8.--9. "RAMP_UP_PRESCAL,Determines prescaler for ramp-up duration counting" "RAMP_UP_PRESCAL_0,RAMP_UP_PRESCAL_1,RAMP_UP_PRESCAL_2,RAMP_UP_PRESCAL_3" newline rbitfld.long 0x38 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x38 0.--5. "RAMP_UP_COUNT,Determines the ramp-up duration of VDD_MPU_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x3C "PRM_VOLTSETUP_MM_RET_SLEEP,This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators" rbitfld.long 0x3C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 24.--25. "RAMP_DOWN_PRESCAL,Determines prescaler for ramp-down duration counting" "RAMP_DOWN_PRESCAL_0,RAMP_DOWN_PRESCAL_1,RAMP_DOWN_PRESCAL_2,RAMP_DOWN_PRESCAL_3" newline rbitfld.long 0x3C 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x3C 16.--21. "RAMP_DOWN_COUNT,Determines the ramp-down duration of VDD_MM_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x3C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 8.--9. "RAMP_UP_PRESCAL,Determines prescaler for ramp-up duration counting" "RAMP_UP_PRESCAL_0,RAMP_UP_PRESCAL_1,RAMP_UP_PRESCAL_2,RAMP_UP_PRESCAL_3" newline rbitfld.long 0x3C 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x3C 0.--5. "RAMP_UP_COUNT,Determines the ramp-up duration of VDD_MM_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "PRM_VP_CORE_CONFIG,This register allows the configuration of the Voltage Processor dedicated to CORE Voltage Domain (VDD_CORE_L)" hexmask.long.byte 0x40 24.--31. 1. "ERROROFFSET,Offset value in the Error to Voltage converter (two's complement number)" hexmask.long.byte 0x40 16.--23. 1. "ERRORGAIN,Gain value in the Error to Voltage converter (two's complement number)" newline hexmask.long.byte 0x40 8.--15. 1. "INITVOLTAGE,Set the initial voltage level of the SMPS" rbitfld.long 0x40 4.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x40 3. "TIMEOUTEN,Enable or disable the timeout capability of the Voltage Controller State Machine" "TIMEOUTEN_0,TIMEOUTEN_1" bitfld.long 0x40 2. "INITVDD,Initializes the voltage in the Voltage Processor" "INITVDD_0,INITVDD_1" newline bitfld.long 0x40 1. "FORCEUPDATE,Forces an update of the SMPS" "FORCEUPDATE_0,FORCEUPDATE_1" bitfld.long 0x40 0. "ISSNABLE,Enables or disables the Voltage Processor updates on SR_SInterruptz" "ISSNABLE_0,ISSNABLE_1" line.long 0x44 "PRM_VP_CORE_STATUS,This register reflects the idle state of the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L. This register is read only and automatically updated" hexmask.long 0x44 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x44 0. "VPINIDLE,CORE Voltage Processor idle status" "VPINIDLE_0,VPINIDLE_1" line.long 0x48 "PRM_VP_CORE_VLIMITTO,This register allows the configuration of the voltage limits and timeout values of the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L)" hexmask.long.byte 0x48 24.--31. 1. "VDDMAX,Defines the maximum voltage supply level" hexmask.long.byte 0x48 16.--23. 1. "VDDMIN,Defines the minimum voltage supply level" newline hexmask.long.word 0x48 0.--15. 1. "TIMEOUT,Defines Voltage Controller maximum wait time for responses" line.long 0x4C "PRM_VP_CORE_VOLTAGE,This register indicates the current value of the SMPS voltage for the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L)" hexmask.long.tbyte 0x4C 8.--31. 1. "FORCEUPDATEWAIT,The time voltage processor needs to wait for SMPS to be settled after receiving SMPS acknowledge" hexmask.long.byte 0x4C 0.--7. 1. "VPVOLTAGE,Indicates the current SMPS programmed voltage" line.long 0x50 "PRM_VP_CORE_VSTEPMAX,This register allows the programming of the maximum voltage step and waiting time of the Voltage Processor dedicated to CORE Voltage Domain (VDD_CORE_L)" hexmask.long.byte 0x50 24.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x50 8.--23. 1. "SMPSWAITTIMEMAX,Slew rate for positive voltage step (in number of cycles per step)" newline hexmask.long.byte 0x50 0.--7. 1. "VSTEPMAX,Maximum voltage step" line.long 0x54 "PRM_VP_CORE_VSTEPMIN,This register allows the programming of the minimum voltage step and waiting time of the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L)" hexmask.long.byte 0x54 24.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x54 8.--23. 1. "SMPSWAITTIMEMIN,Slew rate for negative voltage step (in number of cycles per step)" newline hexmask.long.byte 0x54 0.--7. 1. "VSTEPMIN,Minimum voltage step" line.long 0x58 "PRM_VP_MPU_CONFIG,This register allows the configuration of the Voltage Processor dedicated to MPU Voltage Domain (VDD_MPU_L)" hexmask.long.byte 0x58 24.--31. 1. "ERROROFFSET,Offset value in the Error to Voltage converter (two's complement number)" hexmask.long.byte 0x58 16.--23. 1. "ERRORGAIN,Gain value in the Error to Voltage converter (two's complement number)" newline hexmask.long.byte 0x58 8.--15. 1. "INITVOLTAGE,Set the initial voltage level of the SMPS" rbitfld.long 0x58 4.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x58 3. "TIMEOUTEN,Enable or disable the timeout capability of the Voltage Controller State Machine" "TIMEOUTEN_0,TIMEOUTEN_1" bitfld.long 0x58 2. "INITVDD,Initializes the voltage in the Voltage Processor" "INITVDD_0,INITVDD_1" newline bitfld.long 0x58 1. "FORCEUPDATE,Forces an update of the SMPS" "FORCEUPDATE_0,FORCEUPDATE_1" bitfld.long 0x58 0. "ISSNABLE,Enables or disables the Voltage Processor updates on SR_SInterruptz" "ISSNABLE_0,ISSNABLE_1" line.long 0x5C "PRM_VP_MPU_STATUS,This register reflects the idle state of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L. This register is read only and automatically updated" hexmask.long 0x5C 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x5C 0. "VPINIDLE,Voltage Processor 1 idle status" "VPINIDLE_0,VPINIDLE_1" line.long 0x60 "PRM_VP_MPU_VLIMITTO,This register allows the configuration of the voltage limits and timeout values of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L)" hexmask.long.byte 0x60 24.--31. 1. "VDDMAX,Defines the maximum voltage supply level" hexmask.long.byte 0x60 16.--23. 1. "VDDMIN,Defines the minimum voltage supply level" newline hexmask.long.word 0x60 0.--15. 1. "TIMEOUT,Defines Voltage Controller maximum wait time for responses" line.long 0x64 "PRM_VP_MPU_VOLTAGE,This register indicates the current value of the SMPS voltage for the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L)" hexmask.long.tbyte 0x64 8.--31. 1. "FORCEUPDATEWAIT,The time voltage processor needs to wait for SMPS to be settled after receiving SMPS acknowledge" hexmask.long.byte 0x64 0.--7. 1. "VPVOLTAGE,Indicates the current SMPS programmed voltage" line.long 0x68 "PRM_VP_MPU_VSTEPMAX,This register allows the programming of the maximum voltage step and waiting time of the Voltage Processor dedicated to MPU Voltage Domain (VDD_MPU_L)" hexmask.long.byte 0x68 24.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x68 8.--23. 1. "SMPSWAITTIMEMAX,Slew rate for positive voltage step (in number of cycles per step)" newline hexmask.long.byte 0x68 0.--7. 1. "VSTEPMAX,Maximum voltage step" line.long 0x6C "PRM_VP_MPU_VSTEPMIN,This register allows the programming of the minimum voltage step and waiting time of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L)" hexmask.long.byte 0x6C 24.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x6C 8.--23. 1. "SMPSWAITTIMEMIN,Slew rate for negative voltage step (in number of cycles per step)" newline hexmask.long.byte 0x6C 0.--7. 1. "VSTEPMIN,Minimum voltage step" line.long 0x70 "PRM_VP_MM_CONFIG,This register allows the configuration of the Voltage Processor dedicated to MM Voltage Domain (VDD_MM_L)" hexmask.long.byte 0x70 24.--31. 1. "ERROROFFSET,Offset value in the Error to Voltage converter (two's complement number)" hexmask.long.byte 0x70 16.--23. 1. "ERRORGAIN,Gain value in the Error to Voltage converter (two's complement number)" newline hexmask.long.byte 0x70 8.--15. 1. "INITVOLTAGE,Set the initial voltage level of the SMPS" rbitfld.long 0x70 4.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x70 3. "TIMEOUTEN,Enable or disable the timeout capability of the Voltage Controller State Machine" "TIMEOUTEN_0,TIMEOUTEN_1" bitfld.long 0x70 2. "INITVDD,Initializes the voltage in the Voltage Processor" "INITVDD_0,INITVDD_1" newline bitfld.long 0x70 1. "FORCEUPDATE,Forces an update of the SMPS" "FORCEUPDATE_0,FORCEUPDATE_1" bitfld.long 0x70 0. "ISSNABLE,Enables or disables the Voltage Processor updates on SR_SInterruptz" "ISSNABLE_0,ISSNABLE_1" line.long 0x74 "PRM_VP_MM_STATUS,This register reflects the idle state of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MM_L. This register is read only and automatically updated" hexmask.long 0x74 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x74 0. "VPINIDLE,Voltage Processor 1 idle status" "VPINIDLE_0,VPINIDLE_1" line.long 0x78 "PRM_VP_MM_VLIMITTO,This register allows the configuration of the voltage limits and timeout values of the Voltage Processor dedicated to the MM voltage Domain (VDD_MM_L)" hexmask.long.byte 0x78 24.--31. 1. "VDDMAX,Defines the maximum voltage supply level" hexmask.long.byte 0x78 16.--23. 1. "VDDMIN,Defines the minimum voltage supply level" newline hexmask.long.word 0x78 0.--15. 1. "TIMEOUT,Defines Voltage Controller maximum wait time for responses" line.long 0x7C "PRM_VP_MM_VOLTAGE,This register indicates the current value of the SMPS voltage for the Voltage Processor dedicated to the MM voltage Domain (VDD_MM_L)" hexmask.long.tbyte 0x7C 8.--31. 1. "FORCEUPDATEWAIT,The time voltage processor needs to wait for SMPS to be settled after receiving SMPS acknowledge" hexmask.long.byte 0x7C 0.--7. 1. "VPVOLTAGE,Indicates the current SMPS programmed voltage" line.long 0x80 "PRM_VP_MM_VSTEPMAX,This register allows the programming of the maximum voltage step and waiting time of the Voltage Processor dedicated to MM voltage Domain (VDD_MM_L)" hexmask.long.byte 0x80 24.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x80 8.--23. 1. "SMPSWAITTIMEMAX,Slew rate for positive voltage step (in number of cycles per step)" newline hexmask.long.byte 0x80 0.--7. 1. "VSTEPMAX,Maximum voltage step" line.long 0x84 "PRM_VP_MM_VSTEPMIN,This register allows the programming of the minimum voltage step and waiting time of the Voltage Processor dedicated to the MM voltage Domain (VDD_MM_L)" hexmask.long.byte 0x84 24.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x84 8.--23. 1. "SMPSWAITTIMEMIN,Slew rate for negative voltage step (in number of cycles per step)" newline hexmask.long.byte 0x84 0.--7. 1. "VSTEPMIN,Minimum voltage step" line.long 0x88 "PRM_VC_SMPS_CORE_CONFIG,This register allows the setting of the I2C slave address of the Power IC device. the setting of the voltage configuration register address for the CORE VDD and the Command (ON/ON-Low-Power/Retention/OFF) configuration register.." rbitfld.long 0x88 29.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x88 28. "CMD_VDD_CORE_L,Command values (ON/ON-Low-Power/Retention/OFF voltage values) set selection for VDD_CORE_L channel" "CMD_VDD_CORE_L_0,CMD_VDD_CORE_L_1" newline bitfld.long 0x88 27. "RACEN_VDD_CORE_L,Enable bit for usage of RAC_VDD_CORE_L" "RACEN_VDD_CORE_L_0,RACEN_VDD_CORE_L_1" bitfld.long 0x88 26. "RAC_VDD_CORE_L,Command (ON/ON-Low-Power/Retention/OFF) configuration register address pointer for VDD_CORE_L channel" "RAC_VDD_CORE_L_0,RAC_VDD_CORE_L_1" newline bitfld.long 0x88 25. "RAV_VDD_CORE_L,Voltage configuration register address pointer for VDD_CORE_L channel" "RAV_VDD_CORE_L_0,RAV_VDD_CORE_L_1" bitfld.long 0x88 24. "SEL_SA_VDD_CORE_L,Slave address pointer for VDD_CORE_L channel" "SEL_SA_VDD_CORE_L_0,SEL_SA_VDD_CORE_L_1" newline hexmask.long.byte 0x88 16.--23. 1. "CMDRA_VDD_CORE_L,Command (ON/ON-Low-Power /Retention/OFF) configuration register address value for VDD_CORE_L channel.(if VDD_CORE_L source has different command configuration register than voltage VDD_MPU_L)" hexmask.long.byte 0x88 8.--15. 1. "VOLRA_VDD_CORE_L,Set the voltage configuration register address value for the VDD_CORE_L channel (if VDD_CORE_L source is placed in same chip as VDD_MPU_L source and have different voltage configuration register)" newline rbitfld.long 0x88 7. "RESERVED,Write 0's for future compatibility" "0,1" hexmask.long.byte 0x88 0.--6. 1. "SA_VDD_CORE_L,Set the I2C slave address value for the first Power IC device" line.long 0x8C "PRM_VC_SMPS_MM_CONFIG,This register allows the setting of the I2C slave address of the Power IC device. the setting of the voltage configuration register address for the MM VDD and the Command (ON/ON-Low-Power/Retention/OFF) configuration register.." rbitfld.long 0x8C 29.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x8C 28. "CMD_VDD_MM_L,Command values (ON/ON-Low-Power/Retention/OFF voltage values) set selection for VDD_MM_L channel" "CMD_VDD_MM_L_0,CMD_VDD_MM_L_1" newline bitfld.long 0x8C 27. "RACEN_VDD_MM_L,Enable bit for usage of RAC_VDD_MM_L" "RACEN_VDD_MM_L_0,RACEN_VDD_MM_L_1" bitfld.long 0x8C 26. "RAC_VDD_MM_L,Command (ON/ON-Low-Power/Retention/OFF) configuration register address pointer for VDD_MM_L channel" "RAC_VDD_MM_L_0,RAC_VDD_MM_L_1" newline bitfld.long 0x8C 25. "RAV_VDD_MM_L,Voltage configuration register address pointer for VDD_MM_L channel" "RAV_VDD_MM_L_0,RAV_VDD_MM_L_1" bitfld.long 0x8C 24. "SEL_SA_VDD_MM_L,Slave address pointer for VDD_MM_L channel" "SEL_SA_VDD_MM_L_0,SEL_SA_VDD_MM_L_1" newline hexmask.long.byte 0x8C 16.--23. 1. "CMDRA_VDD_MM_L,Command (ON/ON-Low-Power /Retention/OFF) configuration register address value for VDD_MM_L channel (if VDD_MM_L source has different command configuration register than voltage VDD_MPU_L)" hexmask.long.byte 0x8C 8.--15. 1. "VOLRA_VDD_MM_L,Voltage configuration register address value for VDD_MM_L channel (if VDD_MM_L source is placed in same chip as VDD_MPU_L source and have different voltage configuration register)" newline rbitfld.long 0x8C 7. "RESERVED,Write 0's for future compatibility" "0,1" hexmask.long.byte 0x8C 0.--6. 1. "SA_VDD_MM_L,Set the I2C slave address value for the second (if any) Power IC device" line.long 0x90 "PRM_VC_SMPS_MPU_CONFIG,This register allows the setting of the I2C slave address of the Power IC device. the setting of the voltage configuration register address for the MPU VDD and the Command (ON/ON-Low-Power/Retention/OFF) configuration register.." rbitfld.long 0x90 29.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x90 28. "CMD_VDD_MPU_L,Command values (ON/ON-Low-Power/Retention/OFF voltage values) set selection for VDD_MPU_L channel (This bit has no influence on VDD_MPU_L channel)" "0,1" newline bitfld.long 0x90 27. "RACEN_VDD_MPU_L,Enable bit for usage of RAC_VDD_MPU_L" "RACEN_VDD_MPU_L_0,RACEN_VDD_MPU_L_1" bitfld.long 0x90 26. "RAC_VDD_MPU_L,Command (ON/ON-Low-Power/Retention/OFF) configuration register address pointer for VDD_MPU_L channel" "0,1" newline bitfld.long 0x90 25. "RAV_VDD_MPU_L,Voltage configuration register address pointer for VDD_MPU_L channel" "0,1" bitfld.long 0x90 24. "SEL_SA_VDD_MPU_L,Slave address pointer for VDD_MPU_L channel" "0,1" newline hexmask.long.byte 0x90 16.--23. 1. "CMDRA_VDD_MPU_L,Command (ON/ON-Low-Power /Retention/OFF) configuration register address value for VDD_MPU_L channel" hexmask.long.byte 0x90 8.--15. 1. "VOLRA_VDD_MPU_L,Voltage configuration register address value for VDD_MPU_L channel" newline rbitfld.long 0x90 7. "RESERVED,Write 0's for future compatibility" "0,1" hexmask.long.byte 0x90 0.--6. 1. "SA_VDD_MPU_L,Set the I2C slave address value for the third (if any) Power IC device" line.long 0x94 "PRM_VC_VAL_CMD_VDD_CORE_L,This register allows the setting of the ON/ON-Low-Power/Retention/OFF command values for VDD_CORE_L channel" hexmask.long.byte 0x94 24.--31. 1. "ON,Set the ON command value" hexmask.long.byte 0x94 16.--23. 1. "ONLP,Set the ON-Low-Power command value" newline hexmask.long.byte 0x94 8.--15. 1. "RET,Set the RET command value" hexmask.long.byte 0x94 0.--7. 1. "OFF,Set the OFF command value" line.long 0x98 "PRM_VC_VAL_CMD_VDD_MM_L,This register allows the setting of the ON/ON-Low-Power/Retention/OFF command values for VDD_MM_L channel" hexmask.long.byte 0x98 24.--31. 1. "ON,Set the ON command value" hexmask.long.byte 0x98 16.--23. 1. "ONLP,Set the ON-Low-Power command value" newline hexmask.long.byte 0x98 8.--15. 1. "RET,Set the RET command value" hexmask.long.byte 0x98 0.--7. 1. "OFF,Set the OFF command value" line.long 0x9C "PRM_VC_VAL_CMD_VDD_MPU_L,This register allows the setting of the ON/ON-Low-Power/Retention/OFF command values for VDD_MPU_L channel" hexmask.long.byte 0x9C 24.--31. 1. "ON,Set the ON command value" hexmask.long.byte 0x9C 16.--23. 1. "ONLP,Set the ON-Low-Power command value" newline hexmask.long.byte 0x9C 8.--15. 1. "RET,Set the RET command value" hexmask.long.byte 0x9C 0.--7. 1. "OFF,Set the OFF command value" line.long 0xA0 "PRM_VC_VAL_BYPASS,Bypass data values register used for bypass command channel to send other configuration information (other then voltage configuration parameters) for SMPS chips which have no other configuration interface then this I2C interface and.." rbitfld.long 0xA0 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA0 25. "OPP_CHANGE_EMIF_LVL,This bit controls read-write leveling of EMIF memories (DDR3)" "OPP_CHANGE_EMIF_LVL_0,OPP_CHANGE_EMIF_LVL_1" newline bitfld.long 0xA0 24. "VALID,This bit validates the bypass command" "VALID_0,VALID_1" hexmask.long.byte 0xA0 16.--23. 1. "DATA,Data to send to the Power IC device" newline hexmask.long.byte 0xA0 8.--15. 1. "REGADDR,Set the address of Power IC device register to configure" rbitfld.long 0xA0 7. "RESERVED," "0,1" newline hexmask.long.byte 0xA0 0.--6. 1. "SLAVEADDR,Set the I2C slave address value" line.long 0xA4 "PRM_VC_CORE_ERRST,This debug register logs CORE related error status coming from Voltage Controller" hexmask.long 0xA4 6.--31. 1. "RESERVED," bitfld.long 0xA4 5. "VFSM_TIMEOUT_ERR_CORE,CORE voltage FSM command frame is finished but is not acknowledged by the slave or (I2C multimaster) arbitration lost" "VFSM_TIMEOUT_ERR_CORE_0,VFSM_TIMEOUT_ERR_CORE_1" newline bitfld.long 0xA4 4. "VFSM_RA_ERR_CORE,Wrong register address error for CORE voltage FSM" "VFSM_RA_ERR_CORE_0,VFSM_RA_ERR_CORE_1" bitfld.long 0xA4 3. "VFSM_SA_ERR_CORE,Wrong slave address error for CORE voltage FSM" "VFSM_SA_ERR_CORE_0,VFSM_SA_ERR_CORE_1" newline bitfld.long 0xA4 2. "SMPS_TIMEOUT_ERR_CORE,CORE voltage processor command frame is finished but is not acknowledged by the slave or (I2C multimaster) arbitration lost" "SMPS_TIMEOUT_ERR_CORE_0,SMPS_TIMEOUT_ERR_CORE_1" bitfld.long 0xA4 1. "SMPS_RA_ERR_CORE,Wrong register address error for CORE voltage processor" "SMPS_RA_ERR_CORE_0,SMPS_RA_ERR_CORE_1" newline bitfld.long 0xA4 0. "SMPS_SA_ERR_CORE,Wrong slave address error for CORE voltage processor" "SMPS_SA_ERR_CORE_0,SMPS_SA_ERR_CORE_1" line.long 0xA8 "PRM_VC_MM_ERRST,This debug register logs MM related error status coming from Voltage Controller" hexmask.long 0xA8 6.--31. 1. "RESERVED," bitfld.long 0xA8 5. "VFSM_TIMEOUT_ERR_MM,MM voltage FSM command frame is finished but is not acknowledged by the slave or (I2C multimaster) arbitration lost" "VFSM_TIMEOUT_ERR_MM_0,VFSM_TIMEOUT_ERR_MM_1" newline bitfld.long 0xA8 4. "VFSM_RA_ERR_MM,Wrong register address error for MM voltage FSM" "VFSM_RA_ERR_MM_0,VFSM_RA_ERR_MM_1" bitfld.long 0xA8 3. "VFSM_SA_ERR_MM,Wrong slave address error for MM voltage FSM" "VFSM_SA_ERR_MM_0,VFSM_SA_ERR_MM_1" newline bitfld.long 0xA8 2. "SMPS_TIMEOUT_ERR_MM,MM voltage processor command frame is finished but is not acknowledged by the slave or (I2C multimaster) arbitration lost" "SMPS_TIMEOUT_ERR_MM_0,SMPS_TIMEOUT_ERR_MM_1" bitfld.long 0xA8 1. "SMPS_RA_ERR_MM,Wrong register address error for MM voltage processor" "SMPS_RA_ERR_MM_0,SMPS_RA_ERR_MM_1" newline bitfld.long 0xA8 0. "SMPS_SA_ERR_MM,Wrong slave address error for MM voltage processor" "SMPS_SA_ERR_MM_0,SMPS_SA_ERR_MM_1" line.long 0xAC "PRM_VC_MPU_ERRST,This debug register logs MPU related error status coming from Voltage Controller" hexmask.long 0xAC 6.--31. 1. "RESERVED," bitfld.long 0xAC 5. "VFSM_TIMEOUT_ERR_MPU,MPU voltage FSM command frame is finished but is not acknowledged by the slave or (I2C multimaster) arbitration lost" "VFSM_TIMEOUT_ERR_MPU_0,VFSM_TIMEOUT_ERR_MPU_1" newline bitfld.long 0xAC 4. "VFSM_RA_ERR_MPU,Wrong register address error for MPU voltage FSM" "VFSM_RA_ERR_MPU_0,VFSM_RA_ERR_MPU_1" bitfld.long 0xAC 3. "VFSM_SA_ERR_MPU,Wrong slave address error for MPU voltage FSM" "VFSM_SA_ERR_MPU_0,VFSM_SA_ERR_MPU_1" newline bitfld.long 0xAC 2. "SMPS_TIMEOUT_ERR_MPU,MPU voltage processor command frame is finished but is not acknowledged by the slave or (I2C multimaster) arbitration lost" "SMPS_TIMEOUT_ERR_MPU_0,SMPS_TIMEOUT_ERR_MPU_1" bitfld.long 0xAC 1. "SMPS_RA_ERR_MPU,Wrong register address error for MPU voltage processor" "SMPS_RA_ERR_MPU_0,SMPS_RA_ERR_MPU_1" newline bitfld.long 0xAC 0. "SMPS_SA_ERR_MPU,Wrong slave address error for MPU voltage processor" "SMPS_SA_ERR_MPU_0,SMPS_SA_ERR_MPU_1" line.long 0xB0 "PRM_VC_BYPASS_ERRST,This debug register logs BYPASS related error status coming from Voltage Controller" hexmask.long 0xB0 3.--31. 1. "RESERVED," bitfld.long 0xB0 2. "BYPS_TIMEOUT_ERR,BYPASS command frame is finished but is not acknowledged by the slave or (I2C multimaster) arbitration lost" "BYPS_TIMEOUT_ERR_0,BYPS_TIMEOUT_ERR_1" newline bitfld.long 0xB0 1. "BYPS_RA_ERR,Wrong register address error for BYPASS command" "BYPS_RA_ERR_0,BYPS_RA_ERR_1" bitfld.long 0xB0 0. "BYPS_SA_ERR,Wrong slave address error for BYPASS command" "BYPS_SA_ERR_0,BYPS_SA_ERR_1" line.long 0xB4 "PRM_VC_CFG_I2C_MODE,I2C configuration register" hexmask.long 0xB4 7.--31. 1. "RESERVED," bitfld.long 0xB4 6. "DFILTEREN,This field enables double filter procedure for I2C input lines" "DFILTEREN_0,DFILTEREN_1" newline rbitfld.long 0xB4 5. "RESERVED," "0,1" bitfld.long 0xB4 4. "SRMODEEN,Enables the I2C repeated start operation mode (effect of holding the SCL and SDA lines low in effect blocking the I2C bus from losing arbitration between repeated start points)" "SRMODEEN_0,SRMODEEN_1" newline bitfld.long 0xB4 3. "HSMODEEN,Enables I2C bus High Speed mode" "HSMODEEN_0,HSMODEEN_1" bitfld.long 0xB4 0.--2. "HSMCODE,Master code value for I2C High Speed preamble transmission" "0,1,2,3,4,5,6,7" line.long 0xB8 "PRM_VC_CFG_I2C_CLK,I2C Interface clock configuration parameters" hexmask.long.byte 0xB8 24.--31. 1. "HSSCLL,Number of the system clock cycles necessary to count the low period of the I2C clock signal when the I2C interface runs in High-Speed mode of operation" hexmask.long.byte 0xB8 16.--23. 1. "HSSCLH,Number of the system clock cycles necessary to count the high period of the I2C clock signal when the I2C interface runs in High-Speed mode of operation" newline hexmask.long.byte 0xB8 8.--15. 1. "SCLL,Number of the system clock cycles necessary to count the low period of the I2C clock signal when the I2C interface runs in Fast mode of operation" hexmask.long.byte 0xB8 0.--7. 1. "SCLH,Number of the system clock cycles necessary to count the high period of the I2C clock signal when the I2C interface runs in Fast mode of operation" line.long 0xBC "PRM_SRAM_COUNT,Common setup for SRAM LDO transition counters" hexmask.long.byte 0xBC 24.--31. 1. "STARTUP_COUNT,Determines the start-up duration of SRAM and ABB LDO" hexmask.long.byte 0xBC 16.--23. 1. "SLPCNT_VALUE,Delay between retention/off assertion of last SRAM bank and SRAMALLRET signal to LDO is driven high" newline hexmask.long.byte 0xBC 8.--15. 1. "VSETUPCNT_VALUE,SRAM LDO rampup time from retention to active mode" rbitfld.long 0xBC 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0xBC 0.--5. "PCHARGECNT_VALUE,Delay between de-assertion of standby_rta_ret_on and standby_rta_ret_good" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0xC0 "PRM_SRAM_WKUP_SETUP,Setup of memory in WKUP voltage domain" hexmask.long 0xC0 1.--31. 1. "RESERVED," bitfld.long 0xC0 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0xC4 "PRM_SLDO_CORE_SETUP,Setup of the SRAM LDO for CORE voltage domain" hexmask.long.tbyte 0xC4 9.--31. 1. "RESERVED," bitfld.long 0xC4 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" newline bitfld.long 0xC4 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" bitfld.long 0xC4 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" newline bitfld.long 0xC4 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" bitfld.long 0xC4 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" newline bitfld.long 0xC4 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" bitfld.long 0xC4 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" newline bitfld.long 0xC4 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" bitfld.long 0xC4 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0xC8 "PRM_SLDO_CORE_CTRL,Control and status of the SRAM LDO for CORE voltage domain" hexmask.long.tbyte 0xC8 10.--31. 1. "RESERVED," bitfld.long 0xC8 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" newline bitfld.long 0xC8 8. "SRAMLDO_STATUS,SRAMLDO status" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" hexmask.long.byte 0xC8 1.--7. 1. "RESERVED," newline bitfld.long 0xC8 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,?" line.long 0xCC "PRM_SLDO_MPU_SETUP,Setup of the SRAM LDO for MPU voltage domain" hexmask.long.tbyte 0xCC 9.--31. 1. "RESERVED," bitfld.long 0xCC 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" newline bitfld.long 0xCC 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" bitfld.long 0xCC 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" newline bitfld.long 0xCC 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" bitfld.long 0xCC 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" newline bitfld.long 0xCC 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" bitfld.long 0xCC 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" newline bitfld.long 0xCC 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" bitfld.long 0xCC 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0xD0 "PRM_SLDO_MPU_CTRL,Control and status of the SRAM LDO for MPU voltage domain" hexmask.long.tbyte 0xD0 10.--31. 1. "RESERVED," rbitfld.long 0xD0 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" newline rbitfld.long 0xD0 8. "SRAMLDO_STATUS,SRAMLDO status" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" hexmask.long.byte 0xD0 1.--7. 1. "RESERVED," newline bitfld.long 0xD0 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,RETMODE_ENABLE_1" line.long 0xD4 "PRM_SLDO_GPU_SETUP,Setup of the SRAM LDO for GPU voltage domain" hexmask.long.tbyte 0xD4 9.--31. 1. "RESERVED," bitfld.long 0xD4 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" newline bitfld.long 0xD4 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" bitfld.long 0xD4 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" newline bitfld.long 0xD4 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" bitfld.long 0xD4 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" newline bitfld.long 0xD4 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" bitfld.long 0xD4 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" newline bitfld.long 0xD4 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" bitfld.long 0xD4 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0xD8 "PRM_SLDO_GPU_CTRL,Control and status of the SRAM LDO for GPU voltage domain" hexmask.long.tbyte 0xD8 10.--31. 1. "RESERVED," rbitfld.long 0xD8 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" newline rbitfld.long 0xD8 8. "SRAMLDO_STATUS,SRAMLDO status" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" hexmask.long.byte 0xD8 1.--7. 1. "RESERVED," newline bitfld.long 0xD8 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,RETMODE_ENABLE_1" line.long 0xDC "PRM_ABBLDO_MPU_SETUP,Selects the MPU_ABB LDO mode" hexmask.long.word 0xDC 16.--31. 1. "RESERVED," hexmask.long.byte 0xDC 8.--15. 1. "SR2_WTCNT_VALUE,LDO settling time for active-mode OPP change" newline rbitfld.long 0xDC 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0xDC 4. "NOCAP,Defines whether ABB LDO is cap-less or not" "NOCAP_0,NOCAP_1" newline rbitfld.long 0xDC 3. "RESERVED," "0,1" bitfld.long 0xDC 2. "ACTIVE_FBB_SEL,Defines ABB LDO mode when voltage is in slow fast OPP" "ACTIVE_FBB_SEL_0,ACTIVE_FBB_SEL_1" newline rbitfld.long 0xDC 1. "RESERVED," "0,1" bitfld.long 0xDC 0. "SR2EN,Enable ABB power management" "SR2EN_0,SR2EN_1" line.long 0xE0 "PRM_ABBLDO_MPU_CTRL,Control and Status of ABB on MPU voltage domain" hexmask.long 0xE0 7.--31. 1. "RESERVED," rbitfld.long 0xE0 6. "SR2_IN_TRANSITION,Indicates VBBLDO_CON is or is not in transition state" "SR2_IN_TRANSITION_0,SR2_IN_TRANSITION_1" newline rbitfld.long 0xE0 5. "RESERVED," "0,1" rbitfld.long 0xE0 3.--4. "SR2_STATUS,Indicate ABB LDO current operation status" "SR2_STATUS_0,SR2_STATUS_1,SR2_STATUS_2,SR2_STATUS_3" newline bitfld.long 0xE0 2. "OPP_CHANGE,When OPP_CHANGE is set to 1 VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge" "0,1" bitfld.long 0xE0 0.--1. "OPP_SEL,Selects the OPP at which the MPU voltage domain is operating" "OPP_SEL_0,OPP_SEL_1,OPP_SEL_2,OPP_SEL_3" line.long 0xE4 "PRM_ABBLDO_GPU_SETUP,Selects the GPU_ABB LDO mode" hexmask.long.word 0xE4 16.--31. 1. "RESERVED," hexmask.long.byte 0xE4 8.--15. 1. "SR2_WTCNT_VALUE,LDO settling time for active-mode OPP change" newline rbitfld.long 0xE4 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0xE4 4. "NOCAP,Defines whether ABB LDO is cap-less or not" "NOCAP_0,NOCAP_1" newline rbitfld.long 0xE4 3. "RESERVED," "0,1" bitfld.long 0xE4 2. "ACTIVE_FBB_SEL,Defines ABB LDO mode when voltage is in slow fast OPP" "ACTIVE_FBB_SEL_0,ACTIVE_FBB_SEL_1" newline rbitfld.long 0xE4 1. "RESERVED," "0,1" bitfld.long 0xE4 0. "SR2EN,Enable ABB power management" "SR2EN_0,SR2EN_1" line.long 0xE8 "PRM_ABBLDO_GPU_CTRL,Control and Status of ABB on GPU voltage domain" hexmask.long 0xE8 7.--31. 1. "RESERVED," rbitfld.long 0xE8 6. "SR2_IN_TRANSITION,Indicates VBBLDO_CON is or is not in transition state" "SR2_IN_TRANSITION_0,SR2_IN_TRANSITION_1" newline rbitfld.long 0xE8 5. "RESERVED," "0,1" rbitfld.long 0xE8 3.--4. "SR2_STATUS,Indicate ABB LDO current operation status" "SR2_STATUS_0,SR2_STATUS_1,SR2_STATUS_2,SR2_STATUS_3" newline bitfld.long 0xE8 2. "OPP_CHANGE,When OPP_CHANGE is set to 1 VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge" "0,1" bitfld.long 0xE8 0.--1. "OPP_SEL,Selects the OPP at which the MM voltage domain is operating (Fast OPP Nominal OPP or Slow OPP)" "OPP_SEL_0,OPP_SEL_1,OPP_SEL_2,OPP_SEL_3" line.long 0xEC "PRM_BANDGAP_SETUP,Setup of the bandgap" hexmask.long.tbyte 0xEC 8.--31. 1. "RESERVED," hexmask.long.byte 0xEC 0.--7. 1. "STARTUP_COUNT,Determines the start-up duration of BANDGAP" line.long 0xF0 "PRM_DEVICE_OFF_CTRL,This register is used to control device OFF transition" hexmask.long.tbyte 0xF0 10.--31. 1. "RESERVED," bitfld.long 0xF0 9. "EMIF2_OFFWKUP_DISABLE,Controls the EMIF2_DEVICE_OFFWKUP_CORESRTACTST notifier sent to EMIF1 upon a device wakeup from OFF mode" "EMIF2_OFFWKUP_DISABLE_0,EMIF2_OFFWKUP_DISABLE_1" newline bitfld.long 0xF0 8. "EMIF1_OFFWKUP_DISABLE,Controls the EMIF1_DEVICE_OFFWKUP_CORESRTACTST notifier sent to EMIF2 upon a device wakeup from OFF mode" "EMIF1_OFFWKUP_DISABLE_0,EMIF1_OFFWKUP_DISABLE_1" hexmask.long.byte 0xF0 1.--7. 1. "RESERVED," newline bitfld.long 0xF0 0. "DEVICE_OFF_ENABLE,Controls transition to device OFF mode" "DEVICE_OFF_ENABLE_0,DEVICE_OFF_ENABLE_1" line.long 0xF4 "PRM_PHASE1_CNDP,This register stores the start descriptor address of automatic restore phase1" line.long 0xF8 "PRM_PHASE2A_CNDP,This register stores the start descriptor address of automatic restore phase2A" line.long 0xFC "PRM_PHASE2B_CNDP,This register stores the start descriptor address of automatic restore phase2B" line.long 0x100 "PRM_MODEM_IF_CTRL,This register is used to control dedicated interfaces between on-chip modem and APE" hexmask.long.tbyte 0x100 10.--31. 1. "RESERVED," bitfld.long 0x100 9. "MODEM_SHUTDOWN_IRQ,Controls an interrupt signal to shutdown modem" "MODEM_SHUTDOWN_IRQ_0,MODEM_SHUTDOWN_IRQ_1" newline bitfld.long 0x100 8. "MODEM_WAKE_IRQ,Controls an interrupt signal to wakeup modem" "MODEM_WAKE_IRQ_0,MODEM_WAKE_IRQ_1" hexmask.long.byte 0x100 0.--7. 1. "RESERVED," rgroup.long 0x110++0x27 line.long 0x00 "PRM_VOLTST_MPU,This register provides a status on the current MPU voltage domain state" hexmask.long.word 0x00 21.--31. 1. "RESERVED," bitfld.long 0x00 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.tbyte 0x00 2.--19. 1. "RESERVED," bitfld.long 0x00 0.--1. "VOLTSTATEST,Current voltage state status" "VOLTSTATEST_0,VOLTSTATEST_1,VOLTSTATEST_2,VOLTSTATEST_3" line.long 0x04 "PRM_VOLTST_MM,This register provides a status on the current MM voltage domain state" hexmask.long.word 0x04 21.--31. 1. "RESERVED," bitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.tbyte 0x04 2.--19. 1. "RESERVED," bitfld.long 0x04 0.--1. "VOLTSTATEST,Current voltage state status" "VOLTSTATEST_0,VOLTSTATEST_1,VOLTSTATEST_2,VOLTSTATEST_3" line.long 0x08 "PRM_SLDO_DSPEVE_SETUP,Setup of the SRAM LDO for DSPEVE voltage domain" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," bitfld.long 0x08 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" newline bitfld.long 0x08 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" bitfld.long 0x08 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" newline bitfld.long 0x08 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" bitfld.long 0x08 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" newline bitfld.long 0x08 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" bitfld.long 0x08 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" newline bitfld.long 0x08 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" bitfld.long 0x08 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0x0C "PRM_SLDO_IVA_SETUP,Setup of the SRAM LDO for IVA voltage domain" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED," bitfld.long 0x0C 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" newline bitfld.long 0x0C 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" bitfld.long 0x0C 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" newline bitfld.long 0x0C 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" bitfld.long 0x0C 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" newline bitfld.long 0x0C 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" bitfld.long 0x0C 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" newline bitfld.long 0x0C 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" bitfld.long 0x0C 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0x10 "PRM_ABBLDO_DSPEVE_CTRL,Control and Status of ABB on DSPEVE voltage domain" hexmask.long 0x10 7.--31. 1. "RESERVED," rbitfld.long 0x10 6. "SR2_IN_TRANSITION,Indicates VBBLDO_CON is or is not in transition state" "SR2_IN_TRANSITION_0,SR2_IN_TRANSITION_1" newline rbitfld.long 0x10 5. "RESERVED," "0,1" rbitfld.long 0x10 3.--4. "SR2_STATUS,Indicate ABB LDO current operation status" "SR2_STATUS_0,SR2_STATUS_1,SR2_STATUS_2,SR2_STATUS_3" newline bitfld.long 0x10 2. "OPP_CHANGE,When OPP_CHANGE is set to 1 VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge" "0,1" bitfld.long 0x10 0.--1. "OPP_SEL,Selects the OPP at which the MM voltage domain is operating (Fast OPP Nominal OPP or Slow OPP)" "OPP_SEL_0,OPP_SEL_1,OPP_SEL_2,OPP_SEL_3" line.long 0x14 "PRM_ABBLDO_IVA_CTRL,Control and Status of ABB on IVA voltage domain" hexmask.long 0x14 7.--31. 1. "RESERVED," rbitfld.long 0x14 6. "SR2_IN_TRANSITION,Indicates VBBLDO_CON is or is not in transition state" "SR2_IN_TRANSITION_0,SR2_IN_TRANSITION_1" newline rbitfld.long 0x14 5. "RESERVED," "0,1" rbitfld.long 0x14 3.--4. "SR2_STATUS,Indicate ABB LDO current operation status" "SR2_STATUS_0,SR2_STATUS_1,SR2_STATUS_2,SR2_STATUS_3" newline bitfld.long 0x14 2. "OPP_CHANGE,When OPP_CHANGE is set to 1 VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge" "0,1" bitfld.long 0x14 0.--1. "OPP_SEL,Selects the OPP at which the MM voltage domain is operating (Fast OPP Nominal OPP or Slow OPP)" "OPP_SEL_0,OPP_SEL_1,OPP_SEL_2,OPP_SEL_3" line.long 0x18 "PRM_SLDO_DSPEVE_CTRL,Control and status of the SRAM LDO for CORE voltage domain" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," rbitfld.long 0x18 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" newline rbitfld.long 0x18 8. "SRAMLDO_STATUS,SRAMLDO status" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" hexmask.long.byte 0x18 1.--7. 1. "RESERVED," newline bitfld.long 0x18 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,RETMODE_ENABLE_1" line.long 0x1C "PRM_SLDO_IVA_CTRL,Control and status of the SRAM LDO for CORE voltage domain" hexmask.long.tbyte 0x1C 10.--31. 1. "RESERVED," rbitfld.long 0x1C 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" newline rbitfld.long 0x1C 8. "SRAMLDO_STATUS,SRAMLDO status" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" hexmask.long.byte 0x1C 1.--7. 1. "RESERVED," newline bitfld.long 0x1C 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,RETMODE_ENABLE_1" line.long 0x20 "PRM_ABBLDO_DSPEVE_SETUP,Selects the GPU_ABB LDO mode" hexmask.long.word 0x20 16.--31. 1. "RESERVED," hexmask.long.byte 0x20 8.--15. 1. "SR2_WTCNT_VALUE,LDO settling time for active-mode OPP change" newline rbitfld.long 0x20 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x20 4. "NOCAP,Defines whether ABB LDO is cap-less or not" "NOCAP_0,NOCAP_1" newline rbitfld.long 0x20 3. "RESERVED," "0,1" bitfld.long 0x20 2. "ACTIVE_FBB_SEL,Defines ABB LDO mode when voltage is in slow fast OPP" "ACTIVE_FBB_SEL_0,ACTIVE_FBB_SEL_1" newline rbitfld.long 0x20 1. "RESERVED," "0,1" bitfld.long 0x20 0. "SR2EN,Enable ABB power management" "SR2EN_0,SR2EN_1" line.long 0x24 "PRM_ABBLDO_IVA_SETUP,Selects the GPU_ABB LDO mode" hexmask.long.word 0x24 16.--31. 1. "RESERVED," hexmask.long.byte 0x24 8.--15. 1. "SR2_WTCNT_VALUE,LDO settling time for active-mode OPP change" newline rbitfld.long 0x24 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x24 4. "NOCAP,Defines whether ABB LDO is cap-less or not" "NOCAP_0,NOCAP_1" newline rbitfld.long 0x24 3. "RESERVED," "0,1" bitfld.long 0x24 2. "ACTIVE_FBB_SEL,Defines ABB LDO mode when voltage is in slow fast OPP" "ACTIVE_FBB_SEL_0,ACTIVE_FBB_SEL_1" newline rbitfld.long 0x24 1. "RESERVED," "0,1" bitfld.long 0x24 0. "SR2EN,Enable ABB power management" "SR2EN_0,SR2EN_1" width 0x0B tree.end tree "DISPC_COMMON" base ad:0x58010000 rgroup.long 0x00++0x0B line.long 0x00 "DISPC_REVISION,This register contains the IP revision code" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision" line.long 0x04 "DISPC_SYSCONFIG,This register allows to control various parameters of the OCP interface" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x04 12.--13. "MIDLEMODE,Master interface power management standby/wait control" "MIDLEMODE_0,MIDLEMODE_1,MIDLEMODE_2,MIDLEMODE_3" newline rbitfld.long 0x04 10.--11. "RESERVED,Write 0's for future compatibility" "0,1,2,3" bitfld.long 0x04 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" newline rbitfld.long 0x04 6.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3" bitfld.long 0x04 5. "WARMRESET,Warm reset" "WARMRESET_0,WARMRESET_1" newline bitfld.long 0x04 3.--4. "SIDLEMODE,Slave interface power management Idle req/ack control" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x04 2. "ENWAKEUP,WakeUp feature control" "ENWAKEUP_0,ENWAKEUP_1" newline bitfld.long 0x04 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" bitfld.long 0x04 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x08 "DISPC_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" hexmask.long 0x08 5.--31. 1. "RESERVED," bitfld.long 0x08 4. "RESERVED," "0,1" newline bitfld.long 0x08 3. "RESERVED," "0,1" bitfld.long 0x08 2. "RESERVED," "0,1" newline bitfld.long 0x08 1. "DISPC_VP1_RESETDONE,Reset status of DISPC VP1 pixel clock domain" "DISPC_VP1_RESETDONE_0,DISPC_VP1_RESETDONE_1" bitfld.long 0x08 0. "DISPC_FUNC_RESETDONE,Reset status of DISPC Functional clock domain" "DISPC_FUNC_RESETDONE_0,DISPC_FUNC_RESETDONE_1" group.long 0x20++0x17 line.long 0x00 "DISPC_IRQ_EOI,End Of Interrupt number (for H08 interrupt)" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,?" line.long 0x04 "DISPC_IRQSTATUS_RAW,Per-end of group (31 down to 0) internal signaling raw interrupt status vector. line #0" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED," bitfld.long 0x04 13. "WAKEUP_IRQ,Wake-up" "WAKEUP_IRQ_0,WAKEUP_IRQ_1" newline rbitfld.long 0x04 12. "RESERVED," "0,1" bitfld.long 0x04 11. "WB_IRQ,WB IRQ STATUS register indicates the write-back pipeline interrupt events" "WB_IRQ_0,WB_IRQ_1" newline rbitfld.long 0x04 10. "RESERVED," "0,1" rbitfld.long 0x04 9. "RESERVED," "0,1" newline bitfld.long 0x04 8. "VID2_IRQ,VID2 IRQ STATUS register indicates the video pipeline 2 interrupt events" "VID2_IRQ_0,VID2_IRQ_1" bitfld.long 0x04 7. "VID1_IRQ,VID1 IRQ STATUS register indicates the video pipeline 1 interrupt events" "VID1_IRQ_0,VID1_IRQ_1" newline rbitfld.long 0x04 6. "RESERVED," "0,1" rbitfld.long 0x04 5. "RESERVED," "0,1" newline bitfld.long 0x04 4. "GFX1_IRQ,GFX1 IRQ STATUS register indicates the graphics pipeline 1 interrupt events" "GFX1_IRQ_0,GFX1_IRQ_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline rbitfld.long 0x04 2. "RESERVED," "0,1" rbitfld.long 0x04 1. "RESERVED," "0,1" newline bitfld.long 0x04 0. "VP1_IRQ,VP1 IRQ STATUS register indicates the Video Port 1 interrupt events" "VP1_IRQ_0,VP1_IRQ_1" line.long 0x08 "DISPC_IRQSTATUS,Per-end of group (31 down to 0) internal signaling 'enabled' interrupt status vector. line #0" hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED," bitfld.long 0x08 13. "WAKEUP_IRQ,Wake-up" "WAKEUP_IRQ_0,WAKEUP_IRQ_1" newline rbitfld.long 0x08 12. "RESERVED," "0,1" bitfld.long 0x08 11. "WB_IRQ,WB IRQ STATUS register indicates the write-back pipeline interrupt events" "WB_IRQ_0,WB_IRQ_1" newline rbitfld.long 0x08 10. "RESERVED," "0,1" rbitfld.long 0x08 9. "RESERVED," "0,1" newline bitfld.long 0x08 8. "VID2_IRQ,VID2 IRQ STATUS register indicates the video pipeline 2 interrupt events" "VID2_IRQ_0,VID2_IRQ_1" bitfld.long 0x08 7. "VID1_IRQ,VID1 IRQ STATUS register indicates the video pipeline 1 interrupt events" "VID1_IRQ_0,VID1_IRQ_1" newline rbitfld.long 0x08 6. "RESERVED," "0,1" rbitfld.long 0x08 5. "RESERVED," "0,1" newline bitfld.long 0x08 4. "GFX1_IRQ,GFX1 IRQ STATUS register indicates the graphics pipeline 1 interrupt events" "GFX1_IRQ_0,GFX1_IRQ_1" rbitfld.long 0x08 3. "RESERVED," "0,1" newline rbitfld.long 0x08 2. "RESERVED," "0,1" rbitfld.long 0x08 1. "RESERVED," "0,1" newline bitfld.long 0x08 0. "VP1_IRQ,VP1 IRQ STATUS register indicates the Video Port 1 interrupt events" "VP1_IRQ_0,VP1_IRQ_1" line.long 0x0C "DISPC_IRQENABLE_SET,Per-end of group (31 down to 0) internal event interrupt enable bit vector. line #0" hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED," bitfld.long 0x0C 13. "SET_WAKEUP_IRQ,Wake Up Mask" "SET_WAKEUP_IRQ_0,SET_WAKEUP_IRQ_1" newline rbitfld.long 0x0C 12. "RESERVED," "0,1" bitfld.long 0x0C 11. "SET_WB_IRQ,WB IRQ" "SET_WB_IRQ_0,SET_WB_IRQ_1" newline rbitfld.long 0x0C 10. "RESERVED," "0,1" rbitfld.long 0x0C 9. "RESERVED," "0,1" newline bitfld.long 0x0C 8. "SET_VID2_IRQ,VID2 IRQ" "SET_VID2_IRQ_0,SET_VID2_IRQ_1" bitfld.long 0x0C 7. "SET_VID1_IRQ,VID1 IRQ" "SET_VID1_IRQ_0,SET_VID1_IRQ_1" newline rbitfld.long 0x0C 6. "RESERVED," "0,1" rbitfld.long 0x0C 5. "RESERVED," "0,1" newline bitfld.long 0x0C 4. "SET_GFX1_IRQ,GFX1 IRQ" "SET_GFX1_IRQ_0,SET_GFX1_IRQ_1" rbitfld.long 0x0C 3. "RESERVED," "0,1" newline rbitfld.long 0x0C 2. "RESERVED," "0,1" rbitfld.long 0x0C 1. "RESERVED," "0,1" newline bitfld.long 0x0C 0. "SET_VP1_IRQ,VP1 IRQ" "SET_VP1_IRQ_0,SET_VP1_IRQ_1" line.long 0x10 "DISPC_IRQENABLE_CLR," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," bitfld.long 0x10 13. "CLR_WAKEUP_IRQ,Wake Up Mask" "CLR_WAKEUP_IRQ_0,CLR_WAKEUP_IRQ_1" newline rbitfld.long 0x10 12. "RESERVED," "0,1" bitfld.long 0x10 11. "CLR_WB_IRQ,WB IRQ" "CLR_WB_IRQ_0,CLR_WB_IRQ_1" newline rbitfld.long 0x10 10. "RESERVED," "0,1" rbitfld.long 0x10 9. "RESERVED," "0,1" newline bitfld.long 0x10 8. "CLR_VID2_IRQ,VID2 IRQ" "CLR_VID2_IRQ_0,CLR_VID2_IRQ_1" bitfld.long 0x10 7. "CLR_VID1_IRQ,VID1 IRQ" "CLR_VID1_IRQ_0,CLR_VID1_IRQ_1" newline rbitfld.long 0x10 6. "RESERVED," "0,1" rbitfld.long 0x10 5. "RESERVED," "0,1" newline bitfld.long 0x10 4. "CLR_GFX1_IRQ,GFX1 IRQ" "CLR_GFX1_IRQ_0,CLR_GFX1_IRQ_1" rbitfld.long 0x10 3. "RESERVED," "0,1" newline rbitfld.long 0x10 2. "RESERVED," "0,1" rbitfld.long 0x10 1. "RESERVED," "0,1" newline bitfld.long 0x10 0. "CLR_VP1_IRQ,VP1 IRQ" "CLR_VP1_IRQ_0,CLR_VP1_IRQ_1" line.long 0x14 "DISPC_IRQWAKEEN,IRQ wake up register" hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED," bitfld.long 0x14 11. "WB_IRQWAKEEN,wakeupen for WB first level interrupt" "WB_IRQWAKEEN_0,WB_IRQWAKEEN_1" newline rbitfld.long 0x14 10. "RESERVED," "0,1" rbitfld.long 0x14 9. "RESERVED," "0,1" newline bitfld.long 0x14 8. "VID2_IRQWAKEEN,wakeupen for VID2 first level interrupt" "VID2_IRQWAKEEN_0,VID2_IRQWAKEEN_1" bitfld.long 0x14 7. "VID1_IRQWAKEEN,wakeupen for VID1 first level interrupt" "VID1_IRQWAKEEN_0,VID1_IRQWAKEEN_1" newline rbitfld.long 0x14 6. "RESERVED," "0,1" rbitfld.long 0x14 5. "RESERVED," "0,1" newline bitfld.long 0x14 4. "GFX1_IRQWAKEEN,wakeupen for GFX1 first level interrupt" "GFX1_IRQWAKEEN_0,GFX1_IRQWAKEEN_1" rbitfld.long 0x14 3. "RESERVED," "0,1" newline rbitfld.long 0x14 2. "RESERVED," "0,1" rbitfld.long 0x14 1. "RESERVED," "0,1" newline bitfld.long 0x14 0. "VP1_IRQWAKEEN,wakeupen for VP1 first level interrupt" "VP1_IRQWAKEEN_0,VP1_IRQWAKEEN_1" group.long 0x40++0x17 line.long 0x00 "DISPC_GLOBAL_MFLAG_ATTRIBUTE,MFLAG control register" hexmask.long 0x00 3.--31. 1. "RESERVED," bitfld.long 0x00 2. "MFLAG_START," "MFLAG_START_0,MFLAG_START_1" newline bitfld.long 0x00 0.--1. "MFLAG_CTRL," "MFLAG_CTRL_0,MFLAG_CTRL_1,MFLAG_CTRL_2,?" line.long 0x04 "DISPC_GLOBAL_BUFFER,The register configures the DMA buffers allocations to the pipeline" bitfld.long 0x04 31. "BUFFERFILLING,Controls if the DMA buffers are re-filled only when the LOW threshold is reached or if all DMA buffers are re-filled when at least one of them reaches the LOW threshold" "BUFFERFILLING_0,BUFFERFILLING_1" hexmask.long.word 0x04 21.--30. 1. "RESERVED," newline bitfld.long 0x04 18.--20. "WB_BUFFER,WB DMA buffer allocation to one of the pipelines" "WB_BUFFER_0,WB_BUFFER_1,WB_BUFFER_2,WB_BUFFER_3,WB_BUFFER_4,WB_BUFFER_5,WB_BUFFER_6,WB_BUFFER_7" rbitfld.long 0x04 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 12.--14. "VID2_BUFFER,Video2 DMA buffer allocation to one of the pipelines" "VID2_BUFFER_0,VID2_BUFFER_1,VID2_BUFFER_2,VID2_BUFFER_3,VID2_BUFFER_4,VID2_BUFFER_5,VID2_BUFFER_6,VID2_BUFFER_7" bitfld.long 0x04 9.--11. "VID1_BUFFER,Video1 DMA buffer allocation to one of the pipelines" "VID1_BUFFER_0,VID1_BUFFER_1,VID1_BUFFER_2,VID1_BUFFER_3,VID1_BUFFER_4,VID1_BUFFER_5,VID1_BUFFER_6,VID1_BUFFER_7" newline rbitfld.long 0x04 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 3.--5. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0.--2. "GFX1_BUFFER,Gfx1 DMA buffer allocation to one of the pipelines" "GFX1_BUFFER_0,GFX1_BUFFER_1,GFX1_BUFFER_2,GFX1_BUFFER_3,GFX1_BUFFER_4,GFX1_BUFFER_5,GFX1_BUFFER_6,GFX1_BUFFER_7" line.long 0x08 "DISPC_BA0_FLIPIMMEDIATE_EN,Note: Register is not supported in this family of devices" hexmask.long 0x08 6.--31. 1. "RESERVED," bitfld.long 0x08 5. "RESERVED," "0,1" newline bitfld.long 0x08 4. "RESERVED," "0,1" bitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 2. "RESERVED," "0,1" bitfld.long 0x08 1. "RESERVED," "0,1" newline bitfld.long 0x08 0. "RESERVED," "0,1" line.long 0x0C "DISPC_DBG_CONTROL,DISPC debug bus control register Note: GFX2. GFX3. VID-3. OVR3. OVR4. VP2. VP3. VP4. GLBCE1 and GLBCE2 are not supported in this family of devices" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED," hexmask.long.byte 0x0C 1.--8. 1. "DBGMUXSEL," newline bitfld.long 0x0C 0. "DBGEN,Enable debug ports" "DBGEN_0,DBGEN_1" line.long 0x10 "DISPC_DBG_STATUS,DISPC debug status register" line.long 0x14 "DISPC_CLKGATING_DISABLE,Register to control clock gating at DISPC sub-module level Note: CUR. GFX2. GFX3. VID3. OVR3. OVR4. VP2. VP3. VP4. GLBCE1 and GLBCE2 are not supported in this family of devices" rbitfld.long 0x14 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 26. "VP4,Clock gating control for VP4" "VP4_0,VP4_1" newline bitfld.long 0x14 25. "VP3,Clock gating control for VP3" "VP3_0,VP3_1" bitfld.long 0x14 24. "VP2,Clock gating control for VP2" "VP2_0,VP2_1" newline bitfld.long 0x14 23. "VP1,Clock gating control for VP1" "VP1_0,VP1_1" bitfld.long 0x14 22. "OVR4,Clock gating control for OVR4" "OVR4_0,OVR4_1" newline bitfld.long 0x14 21. "OVR3,Clock gating control for OVR3" "OVR3_0,OVR3_1" bitfld.long 0x14 20. "OVR2,Clock gating control for OVR2" "OVR2_0,OVR2_1" newline bitfld.long 0x14 19. "OVR1,Clock gating control for OVR1" "OVR1_0,OVR1_1" bitfld.long 0x14 18. "CUR,Clock gating control for CUR" "CUR_0,CUR_1" newline bitfld.long 0x14 17. "WB,Clock gating control for WB" "WB_0,WB_1" bitfld.long 0x14 16. "GLBCE2,Clock gating control for GLBCE2" "GLBCE2_0,GLBCE2_1" newline bitfld.long 0x14 15. "GLBCE1,Clock gating control for GLBCE1" "GLBCE1_0,GLBCE1_1" bitfld.long 0x14 14. "GFX3,Clock gating control for GFX3" "GFX3_0,GFX3_1" newline bitfld.long 0x14 13. "GFX2,Clock gating control for GFX2" "GFX2_0,GFX2_1" bitfld.long 0x14 12. "GFX1,Clock gating control for GFX1" "GFX1_0,GFX1_1" newline bitfld.long 0x14 11. "VID3,Clock gating control for VID3" "VID3_0,VID3_1" bitfld.long 0x14 10. "VID2,Clock gating control for VID2" "VID2_0,VID2_1" newline bitfld.long 0x14 9. "VID1,Clock gating control for VID1" "VID1_0,VID1_1" bitfld.long 0x14 8. "DMA_CH8,Clock gating control for DMA Channel-8" "DMA_CH8_0,DMA_CH8_1" newline bitfld.long 0x14 7. "DMA_CH7,Clock gating control for DMA Channel-7" "DMA_CH7_0,DMA_CH7_1" bitfld.long 0x14 6. "DMA_CH6,Clock gating control for DMA Channel-6" "DMA_CH6_0,DMA_CH6_1" newline bitfld.long 0x14 5. "DMA_CH5,Clock gating control for DMA Channel-5" "DMA_CH5_0,DMA_CH5_1" bitfld.long 0x14 4. "DMA_CH4,Clock gating control for DMA Channel-4" "DMA_CH4_0,DMA_CH4_1" newline bitfld.long 0x14 3. "DMA_CH3,Clock gating control for DMA Channel-3" "DMA_CH3_0,DMA_CH3_1" bitfld.long 0x14 2. "DMA_CH2,Clock gating control for DMA Channel-2" "DMA_CH2_0,DMA_CH2_1" newline bitfld.long 0x14 1. "DMA_CH1,Clock gating control for DMA Channel-1" "DMA_CH1_0,DMA_CH1_1" bitfld.long 0x14 0. "DMA_COMMON,Clock gating control for DMA_COMMON module" "DMA_COMMON_0,DMA_COMMON_1" width 0x0B tree.end tree "DISPC_GFX1" base ad:0x58011000 group.long 0x00++0x3F line.long 0x00 "DISPC_GFX1_ATTRIBUTES,The register configures the graphics attributes" rbitfld.long 0x00 31. "RESERVED," "0,1" rbitfld.long 0x00 30. "RESERVED," "0,1" newline rbitfld.long 0x00 29. "RESERVED," "0,1" bitfld.long 0x00 28. "PREMULTIPLYALPHA,The field configures the DISPC GFX to process incoming data as premultiplied alpha data or non premultiplied alpha data" "PREMULTIPLYALPHA_0,PREMULTIPLYALPHA_1" newline bitfld.long 0x00 25.--27. "ZORDER,Z-Order defining the priority of the layer compared to others when overlaying" "ZORDER_0,ZORDER_1,ZORDER_2,ZORDER_3,ZORDER_4,ZORDER_5,?,?" bitfld.long 0x00 24. "ANTIFLICKER,Anti-aliasing filtering using a 3-tap filter with hardcoded coefficients (1/4 1/2 1/4)" "ANTIFLICKER_0,ANTIFLICKER_1" newline rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 18. "RESERVED," "0,1" newline bitfld.long 0x00 17. "SELFREFRESHAUTO,Automatic self refresh mode" "SELFREFRESHAUTO_0,SELFREFRESHAUTO_1" rbitfld.long 0x00 16. "RESERVED," "0,1" newline bitfld.long 0x00 15. "SELFREFRESH,Enables the self refresh of the graphics window from its own DMA buffer" "SELFREFRESH_0,SELFREFRESH_1" bitfld.long 0x00 14. "ARBITRATION,Determines the priority of the graphics pipeline" "ARBITRATION_0,ARBITRATION_1" newline rbitfld.long 0x00 12.--13. "RESERVED," "0,1,2,3" bitfld.long 0x00 11. "BUFPRELOAD,Graphics Preload Value" "BUFPRELOAD_0,BUFPRELOAD_1" newline bitfld.long 0x00 8.--10. "CHANNELOUT,Graphics Channel Out configuration wr: immediate" "CHANNELOUT_0,CHANNELOUT_1,?,?,CHANNELOUT_4,?,?,?" bitfld.long 0x00 7. "NIBBLEMODE,Graphics Nibble mode (only for 1- 2- and 4-bpp)" "NIBBLEMODE_0,NIBBLEMODE_1" newline bitfld.long 0x00 1.--6. "FORMAT,Graphics format" "FORMAT_0,FORMAT_1,FORMAT_2,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,?,FORMAT_14,FORMAT_15,FORMAT_16,FORMAT_17,FORMAT_18,FORMAT_19,FORMAT_20,FORMAT_21,FORMAT_22,?,?,?,?,?,?,?,?,?,FORMAT_32,FORMAT_33,FORMAT_34,FORMAT_35,?,FORMAT_37,FORMAT_38,FORMAT_39,FORMAT_40,FORMAT_41,FORMAT_42,FORMAT_43,?,?,FORMAT_46,FORMAT_47,FORMAT_48,FORMAT_49,FORMAT_50,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0. "ENABLE,Graphics Enable" "ENABLE_0,ENABLE_1" line.long 0x04 "DISPC_GFX1_ATTRIBUTES2,The register configures the graphics attributes" rbitfld.long 0x04 31. "RESERVED," "0,1" bitfld.long 0x04 26.--30. "TAGS,Number of OCP TAGS to be used for the pipeline (from 1 to 32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 25. "RESERVED," "0,1" bitfld.long 0x04 24. "REGION_BASED,Enable region-based mechanism" "REGION_BASED_0,REGION_BASED_1" newline hexmask.long.byte 0x04 17.--23. 1. "RESERVED," bitfld.long 0x04 16. "SECURE,OCP requests corresponds to pipeline data are secure/unsecure" "0,1" newline hexmask.long.word 0x04 0.--15. 1. "RESERVED," line.long 0x08 "DISPC_GFX1_BA_j_0,The register configures the base address of the graphics buffer displayed in the graphics window (0 & 1 :for ping-pong mechanism with external trigger. based on the field polarity)" line.long 0x0C "DISPC_GFX1_BA_j_1,The register configures the base address of the graphics buffer displayed in the graphics window (0 & 1 :for ping-pong mechanism with external trigger. based on the field polarity)" line.long 0x10 "DISPC_GFX1_BUF_SIZE_STATUS,The register defines the Graphics buffer size" hexmask.long.word 0x10 16.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x10 0.--15. 1. "BUFSIZE,DMA buffer Size in number of 128-bits" line.long 0x14 "DISPC_GFX1_BUF_THRESHOLD,The register configures the graphics buffer" hexmask.long.word 0x14 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer High Threshold Number of 128-bits defining the threshold value" hexmask.long.word 0x14 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer Low Threshold Number of 128-bits defining the threshold value" line.long 0x18 "DISPC_GFX1_GLOBAL_ALPHA,The register defines the global alpha value for the graphics pipeline" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," hexmask.long.byte 0x18 0.--7. 1. "GLOBALALPHA,Global alpha value from 0 to 255" line.long 0x1C "DISPC_GFX1_IRQENABLE,This register allows to mask/unmask the module internal sources of interrupt. on an event-by-event basis" hexmask.long 0x1C 4.--31. 1. "RESERVED," bitfld.long 0x1C 3. "GFXREGIONBASEDPIPEEND_EN,PIPE end window IRQ for region-based feature" "GFXREGIONBASEDPIPEEND_EN_0,GFXREGIONBASEDPIPEEND_EN_1" newline bitfld.long 0x1C 2. "GFXREGIONBASEDPIPESTART_EN,PIPE start window IRQ for region-based feature" "GFXREGIONBASEDPIPESTART_EN_0,GFXREGIONBASEDPIPESTART_EN_1" bitfld.long 0x1C 1. "GFXENDWINDOW_EN,The end of Gfx Window has been reached" "GFXENDWINDOW_EN_0,GFXENDWINDOW_EN_1" newline bitfld.long 0x1C 0. "GFXBUFFERUNDERFLOW_EN,Gfx DMA Buffer Underflow" "GFXBUFFERUNDERFLOW_EN_0,GFXBUFFERUNDERFLOW_EN_1" line.long 0x20 "DISPC_GFX1_IRQSTATUS,This register regroups all the status of the module internal events that generate an interrupt" hexmask.long 0x20 4.--31. 1. "RESERVED," bitfld.long 0x20 3. "GFXREGIONBASEDPIPEEND_IRQ,PIPE end window IRQ for region-based feature" "GFXREGIONBASEDPIPEEND_IRQ_0,GFXREGIONBASEDPIPEEND_IRQ_1" newline bitfld.long 0x20 2. "GFXREGIONBASEDPIPESTART_IRQ,PIPE start window IRQ for region-based feature" "GFXREGIONBASEDPIPESTART_IRQ_0,GFXREGIONBASEDPIPESTART_IRQ_1" bitfld.long 0x20 1. "GFXENDWINDOW_IRQ,The end of Gfx Window has been reached" "GFXENDWINDOW_IRQ_0,GFXENDWINDOW_IRQ_1" newline bitfld.long 0x20 0. "GFXBUFFERUNDERFLOW_IRQ,Gfx DMA Buffer Underflow" "GFXBUFFERUNDERFLOW_IRQ_0,GFXBUFFERUNDERFLOW_IRQ_1" line.long 0x24 "DISPC_GFX1_MFLAG_THRESHOLD," hexmask.long.word 0x24 16.--31. 1. "HT_MFLAG," hexmask.long.word 0x24 0.--15. 1. "LT_MFLAG," line.long 0x28 "DISPC_GFX1_PIXEL_INC,The register configures the number of bytes to increment between two pixels" hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.byte 0x28 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels" line.long 0x2C "DISPC_GFX1_POSITION,The register configures the position of the graphics window" rbitfld.long 0x2C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x2C 16.--27. 1. "POSY,Y position of the graphics window" newline rbitfld.long 0x2C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x2C 0.--11. 1. "POSX,X position of the graphics window" line.long 0x30 "DISPC_GFX1_PRELOAD,The register configures the graphics DMA buffer Shadow register" hexmask.long.tbyte 0x30 12.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x30 0.--11. 1. "PRELOAD,DMA buffer preload value Number of 128-bit words defining the preload value" line.long 0x34 "DISPC_GFX1_ROW_INC,The register configures the number of bytes to increment at the end of the row" line.long 0x38 "DISPC_GFX1_SIZE,The register configures the size of the graphics window" rbitfld.long 0x38 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x38 16.--27. 1. "SIZEY,Number of lines of the graphics window" newline rbitfld.long 0x38 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x38 0.--11. 1. "SIZEX,Number of pixels of the graphics window" line.long 0x3C "DISPC_GFX1_CLUT,The register configures the Color Look Up Table (CLUT) for GFX pipeline" hexmask.long.byte 0x3C 24.--31. 1. "INDEX,Defines the location in the table where the bit-field VALUE is stored" hexmask.long.byte 0x3C 16.--23. 1. "VALUE_R,8-bit value used to defined the value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x3C 8.--15. 1. "VALUE_G,8-bit value used to defined the value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x3C 0.--7. 1. "VALUE_B,8-bit value used to defined the value to store at the location in the table defined by the bit-field INDEX" width 0x0B tree.end repeat 2. (list 1. 2. )(list ad:0x5801A800 ad:0x5801A900 ) tree "DISPC_OVR$1" base $2 group.long 0x00++0x03 line.long 0x00 "DISPC_OVR_CONFIG,The control register configures the Display Controller module for the VP output" hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED," bitfld.long 0x00 13. "GLBCESEL,Selection between GLBCE-0 and GLBCE-1" "GLBCESEL_0,GLBCESEL_1" bitfld.long 0x00 12. "GLBCEEN,Enable the GLBCE processing" "GLBCEEN_0,GLBCEEN_1" newline bitfld.long 0x00 11. "TCKLCDSELECTION,Transparency Color Key Selection Shadow bit-field" "TCKLCDSELECTION_0,TCKLCDSELECTION_1" bitfld.long 0x00 10. "TCKLCDENABLE,Transparency Color Key Enabled Shadow bit-field" "TCKLCDENABLE_0,TCKLCDENABLE_1" bitfld.long 0x00 8.--9. "INTERLEAVED3DMODE,Define which layer contributes to odd/even lines of the line interleaving 3D format" "INTERLEAVED3DMODE_0,INTERLEAVED3DMODE_1,INTERLEAVED3DMODE_2,INTERLEAVED3DMODE_3" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0x08++0x17 line.long 0x00 "DISPC_OVR_DEFAULT_COLOR,The control register configures the default solid background color bits [31:0]" line.long 0x04 "DISPC_OVR_DEFAULT_COLOR2,The control register configures the default solid background color bits [47:32]" hexmask.long.word 0x04 16.--31. 1. "RESERVED," hexmask.long.word 0x04 0.--15. 1. "DEFAULTCOLOR,48-bit ARGB color value to specify the default solid color to display when there is no data from the overlays" line.long 0x08 "DISPC_OVR_TRANS_COLOR_MAX,The register sets the max transparency color value for the overlays" line.long 0x0C "DISPC_OVR_TRANS_COLOR_MAX2,The register sets the max transparency color value for the overlays" hexmask.long 0x0C 4.--31. 1. "RESERVED," bitfld.long 0x0C 0.--3. "TRANSCOLORKEY,[35:32] Transparency Color Key Value in 36-bit RGB format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DISPC_OVR_TRANS_COLOR_MIN,The register sets the min transparency color value for the overlays" line.long 0x14 "DISPC_OVR_TRANS_COLOR_MIN2,The register sets the min transparency color value for the overlays" hexmask.long 0x14 4.--31. 1. "RESERVED," bitfld.long 0x14 0.--3. "TRANSCOLORKEY,[35:32] Transparency Color Key Value in 36-bit RGB format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end repeat.end repeat 2. (list 1. 2. )(list ad:0x58017000 ad:0x58018000 ) tree "DISPC_VID$1" base $2 group.long 0x00++0x227 line.long 0x00 "DISPC_VID_ACCUH_j_0,The register configures the resize accumulator init values for horizontal up/down-sampling of the video window (DISPC_VIDx_ACCU__0 DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field polarity) It is.." hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x04 "DISPC_VID_ACCUH_j_1,The register configures the resize accumulator init values for horizontal up/down-sampling of the video window (DISPC_VIDx_ACCU__0 DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field polarity) It is.." hexmask.long.byte 0x04 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x04 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x08 "DISPC_VID_ACCUH2_j_0,The register configures the resize accumulator init value for horizontal up/down-sampling of the video window (DISPC_VID#n_ACCU2__0 DISPC_VID#n_ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity) It.." hexmask.long.byte 0x08 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x08 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x0C "DISPC_VID_ACCUH2_j_1,The register configures the resize accumulator init value for horizontal up/down-sampling of the video window (DISPC_VID#n_ACCU2__0 DISPC_VID#n_ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity) It.." hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x0C 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x10 "DISPC_VID_ACCUV_j_0,The register configures the resize accumulator init values for horizontal and vertical up/down-sampling of the video window (DISPC_VIDx_ACCU__0 DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.byte 0x10 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x10 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x14 "DISPC_VID_ACCUV_j_1,The register configures the resize accumulator init values for horizontal and vertical up/down-sampling of the video window (DISPC_VIDx_ACCU__0 DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.byte 0x14 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x14 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x18 "DISPC_VID_ACCUV2_j_0,The register configures the resize accumulator init value for vertical up/down-sampling of the video window (DISPC_VID1_ACCU2__0 DISPC_VID1_ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity) It is.." hexmask.long.byte 0x18 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x18 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x1C "DISPC_VID_ACCUV2_j_1,The register configures the resize accumulator init value for vertical up/down-sampling of the video window (DISPC_VID1_ACCU2__0 DISPC_VID1_ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity) It is.." hexmask.long.byte 0x1C 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x1C 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x20 "DISPC_VID_ATTRIBUTES,The register configures the attributes of the video window" rbitfld.long 0x20 31. "RESERVED," "0,1" rbitfld.long 0x20 30. "RESERVED," "0,1" newline rbitfld.long 0x20 29. "RESERVED," "0,1" bitfld.long 0x20 28. "PREMULTIPLYALPHA,The field configures the DISPC VID1 to process incoming data as premultiplied alpha data or non premultiplied alpha data" "PREMULTIPLYALPHA_0,PREMULTIPLYALPHA_1" newline bitfld.long 0x20 25.--27. "ZORDER,Z-Order defining the priority of the layer compared to others when overlaying" "ZORDER_0,ZORDER_1,ZORDER_2,ZORDER_3,ZORDER_4,ZORDER_5,?,?" bitfld.long 0x20 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "SELFREFRESH_0,SELFREFRESH_1" newline bitfld.long 0x20 23. "ARBITRATION,Determines the priority of the video pipeline" "ARBITRATION_0,ARBITRATION_1" bitfld.long 0x20 22. "DOUBLESTRIDE,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride" "DOUBLESTRIDE_0,DOUBLESTRIDE_1" newline bitfld.long 0x20 21. "VERTICALTAPS,Video Vertical Resize Tap Number" "VERTICALTAPS_0,VERTICALTAPS_1" rbitfld.long 0x20 20. "RESERVED," "0,1" newline bitfld.long 0x20 19. "BUFPRELOAD,Video Preload Value" "BUFPRELOAD_0,BUFPRELOAD_1" rbitfld.long 0x20 18. "RESERVED,Write 0's for future compatibility" "0,1" newline bitfld.long 0x20 17. "SELFREFRESHAUTO,Automatic self refresh mode" "SELFREFRESHAUTO_0,SELFREFRESHAUTO_1" bitfld.long 0x20 14.--16. "CHANNELOUT,Video Channel Out configuration wr: immediate" "CHANNELOUT_0,CHANNELOUT_1,?,?,CHANNELOUT_4,?,?,?" newline rbitfld.long 0x20 12.--13. "RESERVED," "0,1,2,3" bitfld.long 0x20 11. "FULLRANGE,Color Space Conversion full range setting" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x20 10. "NIBBLEMODE,Video Nibble mode (only for 1- 2- and 4-bpp)" "NIBBLEMODE_0,NIBBLEMODE_1" bitfld.long 0x20 9. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1" newline bitfld.long 0x20 7.--8. "RESIZEENABLE,Video Resize Enable" "RESIZEENABLE_0,RESIZEENABLE_1,RESIZEENABLE_2,RESIZEENABLE_3" bitfld.long 0x20 1.--6. "FORMAT,Video Format" "FORMAT_0,FORMAT_1,FORMAT_2,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,?,FORMAT_14,FORMAT_15,FORMAT_16,FORMAT_17,FORMAT_18,FORMAT_19,FORMAT_20,FORMAT_21,FORMAT_22,FORMAT_23,FORMAT_24,?,?,?,?,?,?,?,FORMAT_32,FORMAT_33,FORMAT_34,FORMAT_35,?,FORMAT_37,FORMAT_38,FORMAT_39,FORMAT_40,FORMAT_41,FORMAT_42,FORMAT_43,?,?,FORMAT_46,FORMAT_47,FORMAT_48,FORMAT_49,FORMAT_50,?,?,?,?,?,?,?,?,?,?,FORMAT_61,FORMAT_62,FORMAT_63" newline bitfld.long 0x20 0. "ENABLE,Video pipeline Enable" "ENABLE_0,ENABLE_1" line.long 0x24 "DISPC_VID_ATTRIBUTES2,The register configures the attributes of the video window" rbitfld.long 0x24 31. "RESERVED," "0,1" bitfld.long 0x24 26.--30. "TAGS,Number of OCP TAGS to be used for the pipeline (from 1 to 32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x24 25. "RESERVED," "0,1" bitfld.long 0x24 24. "REGION_BASED,Enable region-based mechanism" "REGION_BASED_0,REGION_BASED_1" newline hexmask.long.byte 0x24 17.--23. 1. "RESERVED," bitfld.long 0x24 16. "SECURE,OCP requests corresponds to pipeline data are secure/unsecure" "0,1" newline hexmask.long.word 0x24 7.--15. 1. "RESERVED," bitfld.long 0x24 4.--6. "VC1_RANGE_CBCR,Defines the VC1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 1.--3. "VC1_RANGE_Y,Defines the VC1 range value for the Y component from 0 to 7" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "VC1ENABLE,Enable/disable the VC1 range mapping processing" "VC1ENABLE_0,VC1ENABLE_1" line.long 0x28 "DISPC_VID_BA_j_0,The register configures the base address of the video buffer for the video window (DISPC_VID1_BA__0 DISPC_VID1_BA__1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_VID1_BA__0 is used)" line.long 0x2C "DISPC_VID_BA_j_1,The register configures the base address of the video buffer for the video window (DISPC_VID1_BA__0 DISPC_VID1_BA__1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_VID1_BA__0 is used)" line.long 0x30 "DISPC_VID_BA_UV_j_0,The register configures the base address of the UV buffer for the video window" line.long 0x34 "DISPC_VID_BA_UV_j_1,The register configures the base address of the UV buffer for the video window" line.long 0x38 "DISPC_VID_BUF_SIZE_STATUS,The register defines the Video buffer size for the video pipeline" hexmask.long.word 0x38 16.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x38 0.--15. 1. "BUFSIZE,Video DMA buffer Size in number of 128-bits" line.long 0x3C "DISPC_VID_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline" hexmask.long.word 0x3C 16.--31. 1. "BUFHIGHTHRESHOLD,Video DMA buffer High Threshold Number of 128-bits defining the threshold value" hexmask.long.word 0x3C 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer High Threshold Number of 128-bits defining the threshold value" line.long 0x40 "DISPC_VID_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline" rbitfld.long 0x40 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x40 16.--26. 1. "RCR,RCr Coefficient Encoded signed value (from -1024 to 1023)" newline rbitfld.long 0x40 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x40 0.--10. 1. "RY,RY Coefficient Encoded signed value (from -1024 to 1023)" line.long 0x44 "DISPC_VID_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline" rbitfld.long 0x44 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x44 16.--26. 1. "GY,GY Coefficient Encoded signed value (from -1024 to 1023)" newline rbitfld.long 0x44 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x44 0.--10. 1. "RCB,RCb Coefficient Encoded signed value (from -1024 to 1023)" line.long 0x48 "DISPC_VID_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline" rbitfld.long 0x48 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x48 16.--26. 1. "GCB,GCb Coefficient Encoded signed value (from -1024 to 1023)" newline rbitfld.long 0x48 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x48 0.--10. 1. "GCR,GCr Coefficient Encoded signed value (from -1024 to 1023)" line.long 0x4C "DISPC_VID_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline" rbitfld.long 0x4C 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x4C 16.--26. 1. "BCR,BCr coefficient Encoded signed value (from -1024 to 1023)" newline rbitfld.long 0x4C 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x4C 0.--10. 1. "BY,BY coefficient Encoded signed value (from -1024 to 1023)" line.long 0x50 "DISPC_VID_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline" hexmask.long.tbyte 0x50 11.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x50 0.--10. 1. "BCB,BCb Coefficient Encoded signed value (from -1024 to 1023)" line.long 0x54 "DISPC_VID_CONV_COEF5,The register configures the color space conversion matrix coefficients for the video pipeline" hexmask.long.word 0x54 19.--31. 1. "GOFFSET,G offset Encoded signed value (from -4096 to 4095)" rbitfld.long 0x54 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x54 3.--15. 1. "ROFFSET,R offset Encoded signed value (from -4096 to 4095)" rbitfld.long 0x54 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x58 "DISPC_VID_CONV_COEF6,The register configures the color space conversion matrix coefficients for the video pipeline" hexmask.long.word 0x58 16.--31. 1. "RESERVED," hexmask.long.word 0x58 3.--15. 1. "BOFFSET,B offset Encoded signed value (from -4096 to 4095)" newline rbitfld.long 0x58 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x5C "DISPC_VID_FIRH,The register configures the resize factor for horizontal up/down-sampling of the video window" hexmask.long.byte 0x5C 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x5C 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter" line.long 0x60 "DISPC_VID_FIRH2,The register configures the resize factor for horizontal up/down-sampling of the video window" hexmask.long.byte 0x60 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x60 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter for Cb and Cr" line.long 0x64 "DISPC_VID_FIRV,The register configures the resize factor for vertical up/down-sampling of the video window" hexmask.long.byte 0x64 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x64 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter" line.long 0x68 "DISPC_VID_FIRV2,The register configures the resize factor for vertical up/down-sampling of the video window" hexmask.long.byte 0x68 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x68 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter for Cb and Cr" line.long 0x6C "DISPC_VID_FIR_COEF_H0_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x6C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x6C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x6C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x70 "DISPC_VID_FIR_COEF_H0_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x70 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x70 10.--29. 1. "RESERVED," newline hexmask.long.word 0x70 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x74 "DISPC_VID_FIR_COEF_H0_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x74 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x74 10.--29. 1. "RESERVED," newline hexmask.long.word 0x74 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x78 "DISPC_VID_FIR_COEF_H0_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x78 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x78 10.--29. 1. "RESERVED," newline hexmask.long.word 0x78 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x7C "DISPC_VID_FIR_COEF_H0_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x7C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x7C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x7C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x80 "DISPC_VID_FIR_COEF_H0_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x80 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x80 10.--29. 1. "RESERVED," newline hexmask.long.word 0x80 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x84 "DISPC_VID_FIR_COEF_H0_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x84 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x84 10.--29. 1. "RESERVED," newline hexmask.long.word 0x84 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x88 "DISPC_VID_FIR_COEF_H0_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x88 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x88 10.--29. 1. "RESERVED," newline hexmask.long.word 0x88 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x8C "DISPC_VID_FIR_COEF_H0_i_8,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x8C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x8C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x8C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x90 "DISPC_VID_FIR_COEF_H0_C_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x90 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x90 10.--29. 1. "RESERVED," newline hexmask.long.word 0x90 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x94 "DISPC_VID_FIR_COEF_H0_C_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x94 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x94 10.--29. 1. "RESERVED," newline hexmask.long.word 0x94 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x98 "DISPC_VID_FIR_COEF_H0_C_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x98 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x98 10.--29. 1. "RESERVED," newline hexmask.long.word 0x98 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x9C "DISPC_VID_FIR_COEF_H0_C_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x9C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x9C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x9C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xA0 "DISPC_VID_FIR_COEF_H0_C_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0xA0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xA0 10.--29. 1. "RESERVED," newline hexmask.long.word 0xA0 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xA4 "DISPC_VID_FIR_COEF_H0_C_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0xA4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xA4 10.--29. 1. "RESERVED," newline hexmask.long.word 0xA4 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xA8 "DISPC_VID_FIR_COEF_H0_C_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0xA8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xA8 10.--29. 1. "RESERVED," newline hexmask.long.word 0xA8 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xAC "DISPC_VID_FIR_COEF_H0_C_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0xAC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xAC 10.--29. 1. "RESERVED," newline hexmask.long.word 0xAC 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xB0 "DISPC_VID_FIR_COEF_H0_C_i_8,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0xB0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xB0 10.--29. 1. "RESERVED," newline hexmask.long.word 0xB0 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xB4 "DISPC_VID_FIR_COEF_H12_k_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xB4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xB4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xB4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xB4 0.--9. 1. "RESERVED," line.long 0xB8 "DISPC_VID_FIR_COEF_H12_k_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xB8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xB8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xB8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xB8 0.--9. 1. "RESERVED," line.long 0xBC "DISPC_VID_FIR_COEF_H12_k_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xBC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xBC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xBC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xBC 0.--9. 1. "RESERVED," line.long 0xC0 "DISPC_VID_FIR_COEF_H12_k_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xC0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xC0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xC0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xC0 0.--9. 1. "RESERVED," line.long 0xC4 "DISPC_VID_FIR_COEF_H12_k_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xC4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xC4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xC4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xC4 0.--9. 1. "RESERVED," line.long 0xC8 "DISPC_VID_FIR_COEF_H12_k_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xC8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xC8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xC8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xC8 0.--9. 1. "RESERVED," line.long 0xCC "DISPC_VID_FIR_COEF_H12_k_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xCC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xCC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xCC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xCC 0.--9. 1. "RESERVED," line.long 0xD0 "DISPC_VID_FIR_COEF_H12_k_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xD0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xD0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xD0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xD0 0.--9. 1. "RESERVED," line.long 0xD4 "DISPC_VID_FIR_COEF_H12_k_8,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xD4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xD4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xD4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xD4 0.--9. 1. "RESERVED," line.long 0xD8 "DISPC_VID_FIR_COEF_H12_k_9,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xD8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xD8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xD8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xD8 0.--9. 1. "RESERVED," line.long 0xDC "DISPC_VID_FIR_COEF_H12_k_10,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xDC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xDC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xDC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xDC 0.--9. 1. "RESERVED," line.long 0xE0 "DISPC_VID_FIR_COEF_H12_k_11,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xE0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xE0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xE0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xE0 0.--9. 1. "RESERVED," line.long 0xE4 "DISPC_VID_FIR_COEF_H12_k_12,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xE4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xE4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xE4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xE4 0.--9. 1. "RESERVED," line.long 0xE8 "DISPC_VID_FIR_COEF_H12_k_13,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xE8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xE8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xE8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xE8 0.--9. 1. "RESERVED," line.long 0xEC "DISPC_VID_FIR_COEF_H12_k_14,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xEC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xEC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xEC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xEC 0.--9. 1. "RESERVED," line.long 0xF0 "DISPC_VID_FIR_COEF_H12_k_15,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xF0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xF0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xF0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xF0 0.--9. 1. "RESERVED," line.long 0xF4 "DISPC_VID_FIR_COEF_H12_C_k_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0xF4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xF4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xF4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xF4 0.--9. 1. "RESERVED," line.long 0xF8 "DISPC_VID_FIR_COEF_H12_C_k_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0xF8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xF8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xF8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xF8 0.--9. 1. "RESERVED," line.long 0xFC "DISPC_VID_FIR_COEF_H12_C_k_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0xFC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xFC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xFC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xFC 0.--9. 1. "RESERVED," line.long 0x100 "DISPC_VID_FIR_COEF_H12_C_k_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x100 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x100 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x100 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x100 0.--9. 1. "RESERVED," line.long 0x104 "DISPC_VID_FIR_COEF_H12_C_k_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x104 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x104 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x104 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x104 0.--9. 1. "RESERVED," line.long 0x108 "DISPC_VID_FIR_COEF_H12_C_k_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x108 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x108 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x108 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x108 0.--9. 1. "RESERVED," line.long 0x10C "DISPC_VID_FIR_COEF_H12_C_k_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x10C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x10C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x10C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x10C 0.--9. 1. "RESERVED," line.long 0x110 "DISPC_VID_FIR_COEF_H12_C_k_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x110 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x110 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x110 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x110 0.--9. 1. "RESERVED," line.long 0x114 "DISPC_VID_FIR_COEF_H12_C_k_8,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x114 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x114 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x114 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x114 0.--9. 1. "RESERVED," line.long 0x118 "DISPC_VID_FIR_COEF_H12_C_k_9,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x118 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x118 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x118 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x118 0.--9. 1. "RESERVED," line.long 0x11C "DISPC_VID_FIR_COEF_H12_C_k_10,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x11C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x11C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x11C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x11C 0.--9. 1. "RESERVED," line.long 0x120 "DISPC_VID_FIR_COEF_H12_C_k_11,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x120 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x120 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x120 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x120 0.--9. 1. "RESERVED," line.long 0x124 "DISPC_VID_FIR_COEF_H12_C_k_12,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x124 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x124 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x124 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x124 0.--9. 1. "RESERVED," line.long 0x128 "DISPC_VID_FIR_COEF_H12_C_k_13,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x128 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x128 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x128 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x128 0.--9. 1. "RESERVED," line.long 0x12C "DISPC_VID_FIR_COEF_H12_C_k_14,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x12C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x12C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x12C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x12C 0.--9. 1. "RESERVED," line.long 0x130 "DISPC_VID_FIR_COEF_H12_C_k_15,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x130 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x130 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x130 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x130 0.--9. 1. "RESERVED," line.long 0x134 "DISPC_VID_FIR_COEF_V0_i_0,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x134 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x134 10.--29. 1. "RESERVED," newline hexmask.long.word 0x134 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x138 "DISPC_VID_FIR_COEF_V0_i_1,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x138 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x138 10.--29. 1. "RESERVED," newline hexmask.long.word 0x138 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x13C "DISPC_VID_FIR_COEF_V0_i_2,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x13C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x13C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x13C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x140 "DISPC_VID_FIR_COEF_V0_i_3,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x140 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x140 10.--29. 1. "RESERVED," newline hexmask.long.word 0x140 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x144 "DISPC_VID_FIR_COEF_V0_i_4,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x144 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x144 10.--29. 1. "RESERVED," newline hexmask.long.word 0x144 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x148 "DISPC_VID_FIR_COEF_V0_i_5,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x148 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x148 10.--29. 1. "RESERVED," newline hexmask.long.word 0x148 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x14C "DISPC_VID_FIR_COEF_V0_i_6,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x14C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x14C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x14C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x150 "DISPC_VID_FIR_COEF_V0_i_7,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x150 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x150 10.--29. 1. "RESERVED," newline hexmask.long.word 0x150 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x154 "DISPC_VID_FIR_COEF_V0_i_8,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x154 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x154 10.--29. 1. "RESERVED," newline hexmask.long.word 0x154 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x158 "DISPC_VID_FIR_COEF_V0_C_i_0,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x158 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x158 10.--29. 1. "RESERVED," newline hexmask.long.word 0x158 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x15C "DISPC_VID_FIR_COEF_V0_C_i_1,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x15C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x15C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x15C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x160 "DISPC_VID_FIR_COEF_V0_C_i_2,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x160 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x160 10.--29. 1. "RESERVED," newline hexmask.long.word 0x160 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x164 "DISPC_VID_FIR_COEF_V0_C_i_3,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x164 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x164 10.--29. 1. "RESERVED," newline hexmask.long.word 0x164 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x168 "DISPC_VID_FIR_COEF_V0_C_i_4,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x168 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x168 10.--29. 1. "RESERVED," newline hexmask.long.word 0x168 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x16C "DISPC_VID_FIR_COEF_V0_C_i_5,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x16C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x16C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x16C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x170 "DISPC_VID_FIR_COEF_V0_C_i_6,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x170 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x170 10.--29. 1. "RESERVED," newline hexmask.long.word 0x170 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x174 "DISPC_VID_FIR_COEF_V0_C_i_7,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x174 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x174 10.--29. 1. "RESERVED," newline hexmask.long.word 0x174 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x178 "DISPC_VID_FIR_COEF_V0_C_i_8,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x178 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x178 10.--29. 1. "RESERVED," newline hexmask.long.word 0x178 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x17C "DISPC_VID_FIR_COEF_V12_k_0,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x17C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x17C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x17C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x17C 0.--9. 1. "RESERVED," line.long 0x180 "DISPC_VID_FIR_COEF_V12_k_1,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x180 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x180 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x180 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x180 0.--9. 1. "RESERVED," line.long 0x184 "DISPC_VID_FIR_COEF_V12_k_2,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x184 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x184 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x184 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x184 0.--9. 1. "RESERVED," line.long 0x188 "DISPC_VID_FIR_COEF_V12_k_3,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x188 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x188 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x188 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x188 0.--9. 1. "RESERVED," line.long 0x18C "DISPC_VID_FIR_COEF_V12_k_4,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x18C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x18C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x18C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x18C 0.--9. 1. "RESERVED," line.long 0x190 "DISPC_VID_FIR_COEF_V12_k_5,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x190 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x190 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x190 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x190 0.--9. 1. "RESERVED," line.long 0x194 "DISPC_VID_FIR_COEF_V12_k_6,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x194 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x194 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x194 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x194 0.--9. 1. "RESERVED," line.long 0x198 "DISPC_VID_FIR_COEF_V12_k_7,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x198 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x198 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x198 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x198 0.--9. 1. "RESERVED," line.long 0x19C "DISPC_VID_FIR_COEF_V12_k_8,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x19C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x19C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x19C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x19C 0.--9. 1. "RESERVED," line.long 0x1A0 "DISPC_VID_FIR_COEF_V12_k_9,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x1A0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1A0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1A0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1A0 0.--9. 1. "RESERVED," line.long 0x1A4 "DISPC_VID_FIR_COEF_V12_k_10,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x1A4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1A4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1A4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1A4 0.--9. 1. "RESERVED," line.long 0x1A8 "DISPC_VID_FIR_COEF_V12_k_11,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x1A8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1A8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1A8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1A8 0.--9. 1. "RESERVED," line.long 0x1AC "DISPC_VID_FIR_COEF_V12_k_12,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x1AC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1AC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1AC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1AC 0.--9. 1. "RESERVED," line.long 0x1B0 "DISPC_VID_FIR_COEF_V12_k_13,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x1B0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1B0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1B0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1B0 0.--9. 1. "RESERVED," line.long 0x1B4 "DISPC_VID_FIR_COEF_V12_k_14,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x1B4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1B4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1B4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1B4 0.--9. 1. "RESERVED," line.long 0x1B8 "DISPC_VID_FIR_COEF_V12_k_15,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x1B8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1B8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1B8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1B8 0.--9. 1. "RESERVED," line.long 0x1BC "DISPC_VID_FIR_COEF_V12_C_k_0,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1BC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1BC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1BC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1BC 0.--9. 1. "RESERVED," line.long 0x1C0 "DISPC_VID_FIR_COEF_V12_C_k_1,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1C0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1C0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1C0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1C0 0.--9. 1. "RESERVED," line.long 0x1C4 "DISPC_VID_FIR_COEF_V12_C_k_2,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1C4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1C4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1C4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1C4 0.--9. 1. "RESERVED," line.long 0x1C8 "DISPC_VID_FIR_COEF_V12_C_k_3,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1C8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1C8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1C8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1C8 0.--9. 1. "RESERVED," line.long 0x1CC "DISPC_VID_FIR_COEF_V12_C_k_4,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1CC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1CC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1CC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1CC 0.--9. 1. "RESERVED," line.long 0x1D0 "DISPC_VID_FIR_COEF_V12_C_k_5,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1D0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1D0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1D0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1D0 0.--9. 1. "RESERVED," line.long 0x1D4 "DISPC_VID_FIR_COEF_V12_C_k_6,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1D4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1D4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1D4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1D4 0.--9. 1. "RESERVED," line.long 0x1D8 "DISPC_VID_FIR_COEF_V12_C_k_7,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1D8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1D8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1D8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1D8 0.--9. 1. "RESERVED," line.long 0x1DC "DISPC_VID_FIR_COEF_V12_C_k_8,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1DC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1DC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1DC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1DC 0.--9. 1. "RESERVED," line.long 0x1E0 "DISPC_VID_FIR_COEF_V12_C_k_9,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1E0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1E0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1E0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1E0 0.--9. 1. "RESERVED," line.long 0x1E4 "DISPC_VID_FIR_COEF_V12_C_k_10,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1E4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1E4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1E4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1E4 0.--9. 1. "RESERVED," line.long 0x1E8 "DISPC_VID_FIR_COEF_V12_C_k_11,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1E8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1E8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1E8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1E8 0.--9. 1. "RESERVED," line.long 0x1EC "DISPC_VID_FIR_COEF_V12_C_k_12,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1EC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1EC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1EC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1EC 0.--9. 1. "RESERVED," line.long 0x1F0 "DISPC_VID_FIR_COEF_V12_C_k_13,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1F0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1F0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1F0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1F0 0.--9. 1. "RESERVED," line.long 0x1F4 "DISPC_VID_FIR_COEF_V12_C_k_14,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1F4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1F4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1F4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1F4 0.--9. 1. "RESERVED," line.long 0x1F8 "DISPC_VID_FIR_COEF_V12_C_k_15,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1F8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1F8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1F8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1F8 0.--9. 1. "RESERVED," line.long 0x1FC "DISPC_VID_GLOBAL_ALPHA,The register defines the global alpha value for the video pipeline" hexmask.long.tbyte 0x1FC 8.--31. 1. "RESERVED," hexmask.long.byte 0x1FC 0.--7. 1. "GLOBALALPHA,Global alpha value from 0 to 255" line.long 0x200 "DISPC_VID_IRQENABLE,This register allows to mask/unmask the module internal sources of interrupt. on an event-by-event basis" hexmask.long 0x200 4.--31. 1. "RESERVED," bitfld.long 0x200 3. "VIDREGIONBASEDPIPEEND_EN,PIPE end window IRQ for region-based feature" "VIDREGIONBASEDPIPEEND_EN_0,VIDREGIONBASEDPIPEEND_EN_1" newline bitfld.long 0x200 2. "VIDREGIONBASEDPIPESTART_EN,PIPE start window IRQ for region-based feature" "VIDREGIONBASEDPIPESTART_EN_0,VIDREGIONBASEDPIPESTART_EN_1" bitfld.long 0x200 1. "VIDENDWINDOW_EN,The end of the video Window has been reached" "VIDENDWINDOW_EN_0,VIDENDWINDOW_EN_1" newline bitfld.long 0x200 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow" "VIDBUFFERUNDERFLOW_EN_0,VIDBUFFERUNDERFLOW_EN_1" line.long 0x204 "DISPC_VID_IRQSTATUS,This register regroups all the status of the module internal events that generate an interrupt" hexmask.long 0x204 4.--31. 1. "RESERVED," bitfld.long 0x204 3. "VIDREGIONBASEDPIPEEND_IRQ,PIPE end window IRQ for region-based feature" "VIDREGIONBASEDPIPEEND_IRQ_0,VIDREGIONBASEDPIPEEND_IRQ_1" newline bitfld.long 0x204 2. "VIDREGIONBASEDPIPESTART_IRQ,PIPE start window IRQ for region-based feature" "VIDREGIONBASEDPIPESTART_IRQ_0,VIDREGIONBASEDPIPESTART_IRQ_1" bitfld.long 0x204 1. "VIDENDWINDOW_IRQ,The end of the video Window has been reached" "VIDENDWINDOW_IRQ_0,VIDENDWINDOW_IRQ_1" newline bitfld.long 0x204 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow" "VIDBUFFERUNDERFLOW_IRQ_0,VIDBUFFERUNDERFLOW_IRQ_1" line.long 0x208 "DISPC_VID_MFLAG_THRESHOLD,MFLAG thresholds for video pipelines" hexmask.long.word 0x208 16.--31. 1. "HT_MFLAG,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level MFLAG is reset to 0" hexmask.long.word 0x208 0.--15. 1. "LT_MFLAG,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level MFLAG is set to 1" line.long 0x20C "DISPC_VID_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer before up/down-scaling" rbitfld.long 0x20C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x20C 16.--27. 1. "MEMSIZEY,Number of lines of the video picture Encoded value (from 1 to 4096) to specify the number of lines of the video picture in memory (program to value minus one)" newline rbitfld.long 0x20C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x20C 0.--11. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value (from 1 to 4096) to specify the number of pixels of the video picture in memory (program to value minus one)" line.long 0x210 "DISPC_VID_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window" hexmask.long.tbyte 0x210 8.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.byte 0x210 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels" line.long 0x214 "DISPC_VID_POSITION,The register configures the position of the video window" rbitfld.long 0x214 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x214 16.--27. 1. "POSY,Y position of the video window Encoded value (from 0 to 4095) to specify the Y position of the video window #1 .The line at the top has the Y-position 0" newline rbitfld.long 0x214 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x214 0.--11. 1. "POSX,X position of the video window Encoded value (from 0 to 4095) to specify the X position of the video window #1" line.long 0x218 "DISPC_VID_PRELOAD,The register configures the DMA buffer of the video pipeline" hexmask.long.tbyte 0x218 12.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x218 0.--11. 1. "PRELOAD,DMA buffer preload value Number of 128-bit words defining the preload value" line.long 0x21C "DISPC_VID_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window" line.long 0x220 "DISPC_VID_SIZE,The register configures the size of the video window" rbitfld.long 0x220 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x220 16.--27. 1. "SIZEY,Number of lines of the video window" newline rbitfld.long 0x220 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x220 0.--11. 1. "SIZEX,Number of pixels of the video window" line.long 0x224 "DISPC_VID_CLUT,The register configures the Color Look Up Table (CLUT) for VID pipeline" hexmask.long.byte 0x224 24.--31. 1. "INDEX,Defines the location in the table where the bit-field VALUE is stored" hexmask.long.byte 0x224 16.--23. 1. "VALUE_R,8-bit value used to defined the value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x224 8.--15. 1. "VALUE_G,8-bit value used to defined the value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x224 0.--7. 1. "VALUE_B,8-bit value used to defined the value to store at the location in the table defined by the bit-field INDEX" width 0x0B tree.end repeat.end tree "DISPC_VP1" base ad:0x5801AC00 group.long 0x00++0x23 line.long 0x00 "DISPC_VP1_CONFIG,The control register configures the Display Controller module for the VP output" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 25. "FULLRANGE,Color Space Conversion full range setting" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x00 24. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1" bitfld.long 0x00 23. "FIDFIRST,Selects the first field to output in case of interlace mode" "FIDFIRST_0,FIDFIRST_1" newline bitfld.long 0x00 22. "OUTPUTMODEENABLE,Selects between progressive and interlace mode for the VP output" "OUTPUTMODEENABLE_0,OUTPUTMODEENABLE_1" bitfld.long 0x00 21. "BT1120ENABLE,Selects BT-1120 format on the VP output" "BT1120ENABLE_0,BT1120ENABLE_1" newline bitfld.long 0x00 20. "BT656ENABLE,Selects BT-656 format on the VP output" "BT656ENABLE_0,BT656ENABLE_1" rbitfld.long 0x00 17.--19. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. "BUFFERHANDSHAKE,Controls the handsSHAKE between DMA buffer and STALL signal in order to prevent from underflow" "BUFFERHANDSHAKE_0,BUFFERHANDSHAKE_1" bitfld.long 0x00 15. "CPR,Color Phase Rotation Control VP output). It shall be reset when ColorConvEnable bit-field is set to 1. Shadow bit-field" "CPR_0,CPR_1" newline rbitfld.long 0x00 9.--14. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8. "EXTERNALSYNCEN,Selects between external sync and internal sync mode for the VP output" "EXTERNALSYNCEN_0,EXTERNALSYNCEN_1" newline bitfld.long 0x00 7. "VSYNCGATED,VSYNC Gated Enabled (VP output) Shadow bit-field" "VSYNCGATED_0,VSYNCGATED_1" bitfld.long 0x00 6. "HSYNCGATED,HSYNC Gated Enabled (VP output) Shadow bit-field" "HSYNCGATED_0,HSYNCGATED_1" newline bitfld.long 0x00 5. "PIXELCLOCKGATED,Pixel Clock Gated Enabled (VP output) Shadow bit-field" "PIXELCLOCKGATED_0,PIXELCLOCKGATED_1" bitfld.long 0x00 4. "PIXELDATAGATED,Pixel Data Gated Enabled (VP output) Shadow bit-field" "PIXELDATAGATED_0,PIXELDATAGATED_1" newline bitfld.long 0x00 3. "HDMIMODE,Configures the timing generator in HDMI compatible mode to generate same timings as HDMI wrapper timings" "HDMIMODE_0,HDMIMODE_1" bitfld.long 0x00 2. "GAMMAENABLE,Enable the gamma Shadow bit-field" "GAMMAENABLE_0,GAMMAENABLE_1" newline bitfld.long 0x00 1. "DATAENABLEGATED,DE Gated Enable Shadow bit-field" "DATAENABLEGATED_0,DATAENABLEGATED_1" bitfld.long 0x00 0. "PIXELGATED,Pixel Gated Enable Shadow bit-field" "PIXELGATED_0,PIXELGATED_1" line.long 0x04 "DISPC_VP1_CONTROL,The control register configures the Display Controller module for the VP output" bitfld.long 0x04 30.--31. "SPATIALTEMPORALDITHERINGFRAMES,Spatial/Temporal dithering number of frames for the VP output" "SPATIALTEMPORALDITHERINGFRAMES_0,SPATIALTEMPORALDITHERINGFRAMES_1,SPATIALTEMPORALDITHERINGFRAMES_2,SPATIALTEMPORALDITHERINGFRAMES_3" rbitfld.long 0x04 27.--29. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 25.--26. "TDMUNUSEDBITS,State of unused bits (TDM mode only) for the VP output" "TDMUNUSEDBITS_0,TDMUNUSEDBITS_1,TDMUNUSEDBITS_2,TDMUNUSEDBITS_3" bitfld.long 0x04 23.--24. "TDMCYCLEFORMAT,Cycle format (TDM mode only) for the VP output" "TDMCYCLEFORMAT_0,TDMCYCLEFORMAT_1,TDMCYCLEFORMAT_2,TDMCYCLEFORMAT_3" newline bitfld.long 0x04 21.--22. "TDMPARALLELMODE,Output Interface width (TDM mode only) for the VP output" "TDMPARALLELMODE_0,TDMPARALLELMODE_1,TDMPARALLELMODE_2,TDMPARALLELMODE_3" bitfld.long 0x04 20. "TDMENABLE,Enable the multiple cycle format for the VP output" "TDMENABLE_0,TDMENABLE_1" newline rbitfld.long 0x04 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 14.--16. "HT,Hold Time for VP output" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 13. "RESERVED," "0,1" rbitfld.long 0x04 12. "RESERVED," "0,1" newline bitfld.long 0x04 11. "STALLMODE,STALL Mode for the VP output" "STALLMODE_0,STALLMODE_1" bitfld.long 0x04 8.--10. "DATALINES,Width of the data bus on VP output" "DATALINES_0,DATALINES_1,DATALINES_2,DATALINES_3,DATALINES_4,DATALINES_5,?,?" newline bitfld.long 0x04 7. "STDITHERENABLE,Spatial Temporal dithering enable for the VP output Shadow bit-field" "STDITHERENABLE_0,STDITHERENABLE_1" rbitfld.long 0x04 6. "RESERVED," "0,1" newline bitfld.long 0x04 5. "GOBIT,GO Command for the VP output" "GOBIT_0,GOBIT_1" rbitfld.long 0x04 2.--4. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 1. "VPPROGLINENUMBERMODULO,Enable the modulo of the line number interrupt generation" "VPPROGLINENUMBERMODULO_0,VPPROGLINENUMBERMODULO_1" bitfld.long 0x04 0. "VPENABLE,Enable the video port output wr:immediate" "VPENABLE_0,VPENABLE_1" line.long 0x08 "DISPC_VP1_CPR_COEF_B,The register configures the color phase rotation matrix coefficients for the Blue component" hexmask.long.word 0x08 22.--31. 1. "BR,BR Coefficient Encoded signed value (from -512 to 511)" rbitfld.long 0x08 21. "RESERVED,Write 0's for future compatibility" "0,1" newline hexmask.long.word 0x08 11.--20. 1. "BG,BG Coefficient Encoded signed value (from -512 to 511)" rbitfld.long 0x08 10. "RESERVED,Write 0's for future compatibility" "0,1" newline hexmask.long.word 0x08 0.--9. 1. "BB,BB Coefficient Encoded signed value (from -512 to 511)" line.long 0x0C "DISPC_VP1_CPR_COEF_G,The register configures the color phase rotation matrix coefficients for the Green component" hexmask.long.word 0x0C 22.--31. 1. "GR,GR Coefficient Encoded signed value (from -512 to 511)" rbitfld.long 0x0C 21. "RESERVED,Write 0's for future compatibility" "0,1" newline hexmask.long.word 0x0C 11.--20. 1. "GG,GG Coefficient Encoded signed value (from -512 to 511)" rbitfld.long 0x0C 10. "RESERVED,Write 0's for future compatibility" "0,1" newline hexmask.long.word 0x0C 0.--9. 1. "GB,GB Coefficient Encoded signed value (from -512 to 511)" line.long 0x10 "DISPC_VP1_CPR_COEF_R,The register configures the color phase rotation matrix coefficients for the Red component" hexmask.long.word 0x10 22.--31. 1. "RR,RR Coefficient Encoded signed value (from -512 to 511)" rbitfld.long 0x10 21. "RESERVED,Write 0's for future compatibility" "0,1" newline hexmask.long.word 0x10 11.--20. 1. "RG,RG Coefficient Encoded signed value (from -512 to 511)" rbitfld.long 0x10 10. "RESERVED,Write 0's for future compatibility" "0,1" newline hexmask.long.word 0x10 0.--9. 1. "RB,RB Coefficient Encoded signed value (from -512 to 511)" line.long 0x14 "DISPC_VP1_DATA_CYCLE_l_0,The control register configures the output data format over up to 3 cycles" rbitfld.long 0x14 28.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel#2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x14 21.--23. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel #2 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x14 12.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel#1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x14 5.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel #1 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "DISPC_VP1_DATA_CYCLE_l_1,The control register configures the output data format over up to 3 cycles" rbitfld.long 0x18 28.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel#2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x18 21.--23. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel #2 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x18 12.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel#1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x18 5.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel #1 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "DISPC_VP1_DATA_CYCLE_l_2,The control register configures the output data format over up to 3 cycles" rbitfld.long 0x1C 28.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel#2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 21.--23. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel #2 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x1C 12.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel#1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 5.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel #1 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "DISPC_VP1_GAMMA_TABLE,The register configures the gamma table on VP output" hexmask.long.byte 0x20 24.--31. 1. "INDEX,Defines the location in the table where the bit-field VALUE is stored" hexmask.long.byte 0x20 16.--23. 1. "VALUE_R,8-bit value used to defined the value to be stored in the gamma table" newline hexmask.long.byte 0x20 8.--15. 1. "VALUE_G,8-bit value used to defined the value to be stored in the gamma table" hexmask.long.byte 0x20 0.--7. 1. "VALUE_B,8-bit value used to defined the value to be stored in the gamma table" group.long 0x3C++0x1F line.long 0x00 "DISPC_VP1_IRQENABLE,This register allows to mask/unmask the module internal sources of interrupt. on an event-by-event basis" hexmask.long 0x00 5.--31. 1. "RESERVED," bitfld.long 0x00 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "VPSYNCLOST_EN_0,VPSYNCLOST_EN_1" newline bitfld.long 0x00 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number" "VPPROGRAMMEDLINENUMBER_EN_0,VPPROGRAMMEDLINENUMBER_EN_1" bitfld.long 0x00 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "VPVSYNC_ODD_EN_0,VPVSYNC_ODD_EN_1" newline bitfld.long 0x00 1. "VPVSYNC_EN,Vertical Synchronization for VP" "VPVSYNC_EN_0,VPVSYNC_EN_1" bitfld.long 0x00 0. "VPFRAMEDONE_EN,Frame Done for Video Port" "VPFRAMEDONE_EN_0,VPFRAMEDONE_EN_1" line.long 0x04 "DISPC_VP1_IRQSTATUS,This register regroups all the status of the module internal events that generate an interrupt" hexmask.long 0x04 5.--31. 1. "RESERVED," bitfld.long 0x04 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output" "VPSYNCLOST_IRQ_0,VPSYNCLOST_IRQ_1" newline bitfld.long 0x04 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number" "VPPROGRAMMEDLINENUMBER_IRQ_0,VPPROGRAMMEDLINENUMBER_IRQ_1" bitfld.long 0x04 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field from interlace mode only" "VPVSYNC_ODD_IRQ_0,VPVSYNC_ODD_IRQ_1" newline bitfld.long 0x04 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output" "VPVSYNC_IRQ_0,VPVSYNC_IRQ_1" bitfld.long 0x04 0. "VPFRAMEDONE_IRQ,Frame Done for VP" "VPFRAMEDONE_IRQ_0,VPFRAMEDONE_IRQ_1" line.long 0x08 "DISPC_VP1_LINE_NUMBER,The control register indicates the panel display line number for the interrupt and the DMA request" hexmask.long.tbyte 0x08 12.--31. 1. "RESERVED," hexmask.long.word 0x08 0.--11. 1. "LINENUMBER,Display panel line number programming" line.long 0x0C "DISPC_VP1_LINE_STATUS,The control register indicates the panel display line number" hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED," hexmask.long.word 0x0C 0.--11. 1. "LINENUMBER,Current display panel line number" line.long 0x10 "DISPC_VP1_POL_FREQ,The register configures the signal configuration" hexmask.long.word 0x10 19.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x10 18. "ALIGN,Defines the alignment betwwen HSYNC and VSYNC assertion" "ALIGN_0,ALIGN_1" newline bitfld.long 0x10 17. "ONOFF,HSYNC/VSYNC Pixel clock Control On/Off" "ONOFF_0,ONOFF_1" bitfld.long 0x10 16. "RF,Program HSYNC/VSYNC Rise or Fall" "RF_0,RF_1" newline bitfld.long 0x10 15. "IEO,Invert output enable" "IEO_0,IEO_1" bitfld.long 0x10 14. "IPC,Invert pixel clock" "IPC_0,IPC_1" newline bitfld.long 0x10 13. "IHS,Invert HSYNC" "IHS_0,IHS_1" bitfld.long 0x10 12. "IVS,Invert VSYNC" "IVS_0,IVS_1" newline hexmask.long.word 0x10 0.--11. 1. "RESERVED," line.long 0x14 "DISPC_VP1_SIZE_SCREEN,The register configures the panel size (horizontal and vertical)" rbitfld.long 0x14 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x14 16.--27. 1. "LPP,Lines per panel Encoded value (from 1 to 4096) to specify the number of lines per panel (program to value minus one)" newline bitfld.long 0x14 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field" "DELTA_LPP_0,DELTA_LPP_1,DELTA_LPP_2,?" rbitfld.long 0x14 12.--13. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "PPL,Pixels per line Encoded value (from 1 to 4096) to specify the number of pixels contains within each line on the display (program to value minus one)" line.long 0x18 "DISPC_VP1_TIMING_H,The register configures the timing logic for the HSYNC signal" hexmask.long.word 0x18 20.--31. 1. "HBP,Horizontal Back Porch" hexmask.long.word 0x18 8.--19. 1. "HFP,Horizontal front porch" newline hexmask.long.byte 0x18 0.--7. 1. "HSW,Horizontal synchronization pulse width Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line display (program to value minus one)" line.long 0x1C "DISPC_VP1_TIMING_V,The register configures the timing logic for the VSYNC signal" hexmask.long.word 0x1C 20.--31. 1. "VBP,Vertical back porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame" hexmask.long.word 0x1C 8.--19. 1. "VFP,Vertical front porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame" newline hexmask.long.byte 0x1C 0.--7. 1. "VSW,Vertical synchronization pulse width Encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus one) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses" width 0x0B tree.end tree "DISPC_WB" base ad:0x58015000 group.long 0x00++0x20B line.long 0x00 "DISPC_WB_ACCUH_j_0,The register configures the resize accumulator init values for horizontal up/down-sampling of the wirte-back window It is used for ARGB and Y setting" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x04 "DISPC_WB_ACCUH_j_1,The register configures the resize accumulator init values for horizontal up/down-sampling of the wirte-back window It is used for ARGB and Y setting" hexmask.long.byte 0x04 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x04 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x08 "DISPC_WB_ACCUH2_j_0,The register configures the resize accumulator init value for horizontal up/down-sampling of the write-back window It is used for Cb and Cr setting" hexmask.long.byte 0x08 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x08 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x0C "DISPC_WB_ACCUH2_j_1,The register configures the resize accumulator init value for horizontal up/down-sampling of the write-back window It is used for Cb and Cr setting" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x0C 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x10 "DISPC_WB_ACCUV_j_0,The register configures the resize accumulator init value for vertical up/down-sampling of the wirte-back window It is used for ARGB and Y setting" hexmask.long.byte 0x10 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x10 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x14 "DISPC_WB_ACCUV_j_1,The register configures the resize accumulator init value for vertical up/down-sampling of the wirte-back window It is used for ARGB and Y setting" hexmask.long.byte 0x14 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x14 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x18 "DISPC_WB_ACCUV2_j_0,The register configures the resize accumulator init value for vertical up/down-sampling of the write-back window It is used for Cb and Cr setting" hexmask.long.byte 0x18 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x18 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x1C "DISPC_WB_ACCUV2_j_1,The register configures the resize accumulator init value for vertical up/down-sampling of the write-back window It is used for Cb and Cr setting" hexmask.long.byte 0x1C 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x1C 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x20 "DISPC_WB_ATTRIBUTES,The register configures the attributes of the viwrite back pipeline" bitfld.long 0x20 28.--31. "IDLENUMBER,Determines the number of idles between requests on the L3 interconnect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x20 27. "IDLESIZE,Determines if the IDLENUMBER corresponds to a number of bursts or singles" "IDLESIZE_0,IDLESIZE_1" newline bitfld.long 0x20 24.--26. "CAPTUREMODE,Defines the frame rate capture" "CAPTUREMODE_0,CAPTUREMODE_1,CAPTUREMODE_2,CAPTUREMODE_3,CAPTUREMODE_4,CAPTUREMODE_5,CAPTUREMODE_6,CAPTUREMODE_7" bitfld.long 0x20 23. "ARBITRATION,Determines the priority of the write-back pipeline" "ARBITRATION_0,ARBITRATION_1" newline bitfld.long 0x20 22. "DOUBLESTRIDE,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride" "DOUBLESTRIDE_0,DOUBLESTRIDE_1" bitfld.long 0x20 21. "VERTICALTAPS,Video Vertical Resize Tap Number" "VERTICALTAPS_0,VERTICALTAPS_1" newline rbitfld.long 0x20 20. "RESERVED," "0,1" bitfld.long 0x20 19. "WRITEBACKMODE,When connected to the overlay output of a channel the write back can operate as a simple transfer from memory to memory (composition engine) or as a capture channel" "WRITEBACKMODE_0,WRITEBACKMODE_1" newline bitfld.long 0x20 15.--18. "CHANNELIN,WB Channel In configuration wr: immediate" "CHANNELIN_0,CHANNELIN_1,?,?,CHANNELIN_4,?,?,CHANNELIN_7,CHANNELIN_8,?,?,?,?,?,?,?" rbitfld.long 0x20 13.--14. "RESERVED," "0,1,2,3" newline bitfld.long 0x20 12. "FULLRANGE,Color Space Conversion full range setting" "FULLRANGE_0,FULLRANGE_1" bitfld.long 0x20 11. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1" newline rbitfld.long 0x20 10. "RESERVED," "0,1" bitfld.long 0x20 9. "ALPHAENABLE,Premultiplied alpha enable" "ALPHAENABLE_0,ALPHAENABLE_1" newline bitfld.long 0x20 7.--8. "RESIZEENABLE,Resize Enable" "RESIZEENABLE_0,RESIZEENABLE_1,RESIZEENABLE_2,RESIZEENABLE_3" bitfld.long 0x20 1.--6. "FORMAT,Write-back Format" "FORMAT_0,FORMAT_1,FORMAT_2,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,?,?,?,FORMAT_16,FORMAT_17,FORMAT_18,?,?,?,FORMAT_22,FORMAT_23,FORMAT_24,?,?,?,?,?,?,?,FORMAT_32,FORMAT_33,FORMAT_34,FORMAT_35,?,FORMAT_37,FORMAT_38,FORMAT_39,FORMAT_40,FORMAT_41,FORMAT_42,FORMAT_43,?,?,?,?,FORMAT_48,FORMAT_49,FORMAT_50,?,?,?,?,?,?,?,?,?,?,FORMAT_61,FORMAT_62,FORMAT_63" newline bitfld.long 0x20 0. "ENABLE,Write-back Enable" "ENABLE_0,ENABLE_1" line.long 0x24 "DISPC_WB_ATTRIBUTES2,The register set the WB pipe" rbitfld.long 0x24 31. "RESERVED," "0,1" bitfld.long 0x24 26.--30. "TAGS,Number of OCP TAGS to be used for the pipeline (from 1 to 32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x24 25. "RESERVED," "0,1" bitfld.long 0x24 24. "REGION_BASED,Enable region-based mechanism for WBPipe" "REGION_BASED_0,REGION_BASED_1" newline rbitfld.long 0x24 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x24 17. "RESERVED," "0,1" newline bitfld.long 0x24 16. "SECURE,OCP requests corresponds to pipeline data are secure/unsecure" "0,1" hexmask.long.word 0x24 1.--15. 1. "RESERVED," newline bitfld.long 0x24 0. "FSC,Field Sequential Color generation : R G and B buffers are generated from RGB buffer" "FSC_0,FSC_1" line.long 0x28 "DISPC_WB_BA_j_0,The register configures the base address of the WB buffer (DISPC_WB_BA__0 DISPC_WB_BA__1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_WB_BA__0 is used)" line.long 0x2C "DISPC_WB_BA_j_1,The register configures the base address of the WB buffer (DISPC_WB_BA__0 DISPC_WB_BA__1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_WB_BA__0 is used)" line.long 0x30 "DISPC_WB_BA_UV_j_0,The register configures the base address of the UV buffer for the write-back pipeline" line.long 0x34 "DISPC_WB_BA_UV_j_1,The register configures the base address of the UV buffer for the write-back pipeline" line.long 0x38 "DISPC_WB_BUF_SIZE_STATUS,The register defines the DMA buufer size for the write back pipeline" hexmask.long.word 0x38 16.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x38 0.--15. 1. "BUFSIZE,DMA buffer Size in number of 128-bits" line.long 0x3C "DISPC_WB_BUF_THRESHOLD,The register configures the DMA buffer associated with the write-back pipeline" hexmask.long.word 0x3C 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer High Threshold Number of 128-bits defining the threshold value" hexmask.long.word 0x3C 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer High Threshold Number of 128-bits defining the threshold value" line.long 0x40 "DISPC_WB_CONV_COEF0,The register configures the color space conversion matrix coefficients for the write back pipeline (YUV444 to RGB24) Shadow register" rbitfld.long 0x40 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x40 16.--26. 1. "YG,YG Coefficient Encoded signed value (from -1024 to 1023)" newline rbitfld.long 0x40 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x40 0.--10. 1. "YR,YR Coefficient Encoded signed value (from -1024 to 1023)" line.long 0x44 "DISPC_WB_CONV_COEF1,The register configures the color space conversion matrix coefficients for the write back pipeline" rbitfld.long 0x44 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x44 16.--26. 1. "CRR,CrR Coefficient Encoded signed value (from -1024 to 1023)" newline rbitfld.long 0x44 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x44 0.--10. 1. "YB,YB Coefficient Encoded signed value (from -1024 to 1023)" line.long 0x48 "DISPC_WB_CONV_COEF2,The register configures the color space conversion matrix coefficients for the write back pipeline" rbitfld.long 0x48 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x48 16.--26. 1. "CRB,CrB Coefficient Encoded signed value (from -1024 to 1023)" newline rbitfld.long 0x48 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x48 0.--10. 1. "CRG,CrG Coefficient Encoded signed value (from -1024 to 1023)" line.long 0x4C "DISPC_WB_CONV_COEF3,The register configures the color space conversion matrix coefficients for the write back pipeline" rbitfld.long 0x4C 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x4C 16.--26. 1. "CBG,CbG coefficient Encoded signed value (from -1024 to 1023)" newline rbitfld.long 0x4C 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x4C 0.--10. 1. "CBR,CbR coefficient Encoded signed value (from -1024 to 1023)" line.long 0x50 "DISPC_WB_CONV_COEF4,The register configures the color space conversion matrix coefficients for the write back pipeline" hexmask.long.tbyte 0x50 11.--31. 1. "RESERVED," hexmask.long.word 0x50 0.--10. 1. "CBB,CbB Coefficient Encoded signed value (from -1024 to 1023)" line.long 0x54 "DISPC_WB_CONV_COEF5,The register configures the color space conversion matrix coefficients for the write-back pipeline" hexmask.long.word 0x54 19.--31. 1. "GOFFSET,G offset Encoded signed value (from -4096 to 4095)" rbitfld.long 0x54 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x54 3.--15. 1. "ROFFSET,R offset Encoded signed value (from -4096 to 4095)" rbitfld.long 0x54 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x58 "DISPC_WB_CONV_COEF6,The register configures the color space conversion matrix coefficients for the write-back pipeline" hexmask.long.word 0x58 16.--31. 1. "RESERVED," hexmask.long.word 0x58 3.--15. 1. "BOFFSET,B offset Encoded signed value (from -4096 to 4095)" newline rbitfld.long 0x58 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x5C "DISPC_WB_FIRH,The register configures the resize factor for horizontal up/down-sampling of the write-back window" hexmask.long.byte 0x5C 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x5C 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter" line.long 0x60 "DISPC_WB_FIRH2,The register configures the resize factor for horizontal up/down-sampling of the wirte-back window" hexmask.long.byte 0x60 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x60 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter for Cb and Cr" line.long 0x64 "DISPC_WB_FIRV,The register configures the resize factor for vertical up/down-sampling of the write-back window It is used for ARGB and Y setting" hexmask.long.byte 0x64 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x64 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter" line.long 0x68 "DISPC_WB_FIRV2,The register configures the resize factor for vertical up/down-sampling of the wirte-back window" hexmask.long.byte 0x68 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x68 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter for Cb and Cr" line.long 0x6C "DISPC_WB_FIR_COEF_H0_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x6C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x6C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x6C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x70 "DISPC_WB_FIR_COEF_H0_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x70 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x70 10.--29. 1. "RESERVED," newline hexmask.long.word 0x70 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x74 "DISPC_WB_FIR_COEF_H0_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x74 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x74 10.--29. 1. "RESERVED," newline hexmask.long.word 0x74 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x78 "DISPC_WB_FIR_COEF_H0_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x78 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x78 10.--29. 1. "RESERVED," newline hexmask.long.word 0x78 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x7C "DISPC_WB_FIR_COEF_H0_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x7C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x7C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x7C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x80 "DISPC_WB_FIR_COEF_H0_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x80 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x80 10.--29. 1. "RESERVED," newline hexmask.long.word 0x80 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x84 "DISPC_WB_FIR_COEF_H0_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x84 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x84 10.--29. 1. "RESERVED," newline hexmask.long.word 0x84 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x88 "DISPC_WB_FIR_COEF_H0_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x88 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x88 10.--29. 1. "RESERVED," newline hexmask.long.word 0x88 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x8C "DISPC_WB_FIR_COEF_H0_i_8,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x8C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x8C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x8C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x90 "DISPC_WB_FIR_COEF_H0_C_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x90 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x90 10.--29. 1. "RESERVED," newline hexmask.long.word 0x90 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x94 "DISPC_WB_FIR_COEF_H0_C_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x94 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x94 10.--29. 1. "RESERVED," newline hexmask.long.word 0x94 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x98 "DISPC_WB_FIR_COEF_H0_C_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x98 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x98 10.--29. 1. "RESERVED," newline hexmask.long.word 0x98 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x9C "DISPC_WB_FIR_COEF_H0_C_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x9C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x9C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x9C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xA0 "DISPC_WB_FIR_COEF_H0_C_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xA0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xA0 10.--29. 1. "RESERVED," newline hexmask.long.word 0xA0 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xA4 "DISPC_WB_FIR_COEF_H0_C_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xA4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xA4 10.--29. 1. "RESERVED," newline hexmask.long.word 0xA4 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xA8 "DISPC_WB_FIR_COEF_H0_C_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xA8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xA8 10.--29. 1. "RESERVED," newline hexmask.long.word 0xA8 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xAC "DISPC_WB_FIR_COEF_H0_C_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xAC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xAC 10.--29. 1. "RESERVED," newline hexmask.long.word 0xAC 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xB0 "DISPC_WB_FIR_COEF_H0_C_i_8,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xB0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xB0 10.--29. 1. "RESERVED," newline hexmask.long.word 0xB0 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xB4 "DISPC_WB_FIR_COEF_H12_k_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xB4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xB4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xB4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xB4 0.--9. 1. "RESERVED," line.long 0xB8 "DISPC_WB_FIR_COEF_H12_k_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xB8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xB8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xB8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xB8 0.--9. 1. "RESERVED," line.long 0xBC "DISPC_WB_FIR_COEF_H12_k_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xBC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xBC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xBC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xBC 0.--9. 1. "RESERVED," line.long 0xC0 "DISPC_WB_FIR_COEF_H12_k_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xC0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xC0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xC0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xC0 0.--9. 1. "RESERVED," line.long 0xC4 "DISPC_WB_FIR_COEF_H12_k_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xC4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xC4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xC4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xC4 0.--9. 1. "RESERVED," line.long 0xC8 "DISPC_WB_FIR_COEF_H12_k_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xC8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xC8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xC8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xC8 0.--9. 1. "RESERVED," line.long 0xCC "DISPC_WB_FIR_COEF_H12_k_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xCC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xCC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xCC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xCC 0.--9. 1. "RESERVED," line.long 0xD0 "DISPC_WB_FIR_COEF_H12_k_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xD0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xD0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xD0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xD0 0.--9. 1. "RESERVED," line.long 0xD4 "DISPC_WB_FIR_COEF_H12_k_8,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xD4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xD4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xD4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xD4 0.--9. 1. "RESERVED," line.long 0xD8 "DISPC_WB_FIR_COEF_H12_k_9,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xD8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xD8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xD8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xD8 0.--9. 1. "RESERVED," line.long 0xDC "DISPC_WB_FIR_COEF_H12_k_10,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xDC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xDC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xDC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xDC 0.--9. 1. "RESERVED," line.long 0xE0 "DISPC_WB_FIR_COEF_H12_k_11,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xE0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xE0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xE0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xE0 0.--9. 1. "RESERVED," line.long 0xE4 "DISPC_WB_FIR_COEF_H12_k_12,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xE4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xE4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xE4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xE4 0.--9. 1. "RESERVED," line.long 0xE8 "DISPC_WB_FIR_COEF_H12_k_13,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xE8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xE8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xE8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xE8 0.--9. 1. "RESERVED," line.long 0xEC "DISPC_WB_FIR_COEF_H12_k_14,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xEC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xEC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xEC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xEC 0.--9. 1. "RESERVED," line.long 0xF0 "DISPC_WB_FIR_COEF_H12_k_15,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xF0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xF0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xF0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xF0 0.--9. 1. "RESERVED," line.long 0xF4 "DISPC_WB_FIR_COEF_H12_C_k_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xF4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xF4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xF4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xF4 0.--9. 1. "RESERVED," line.long 0xF8 "DISPC_WB_FIR_COEF_H12_C_k_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xF8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xF8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xF8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xF8 0.--9. 1. "RESERVED," line.long 0xFC "DISPC_WB_FIR_COEF_H12_C_k_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xFC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xFC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xFC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xFC 0.--9. 1. "RESERVED," line.long 0x100 "DISPC_WB_FIR_COEF_H12_C_k_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x100 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x100 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x100 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x100 0.--9. 1. "RESERVED," line.long 0x104 "DISPC_WB_FIR_COEF_H12_C_k_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x104 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x104 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x104 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x104 0.--9. 1. "RESERVED," line.long 0x108 "DISPC_WB_FIR_COEF_H12_C_k_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x108 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x108 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x108 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x108 0.--9. 1. "RESERVED," line.long 0x10C "DISPC_WB_FIR_COEF_H12_C_k_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x10C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x10C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x10C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x10C 0.--9. 1. "RESERVED," line.long 0x110 "DISPC_WB_FIR_COEF_H12_C_k_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x110 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x110 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x110 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x110 0.--9. 1. "RESERVED," line.long 0x114 "DISPC_WB_FIR_COEF_H12_C_k_8,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x114 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x114 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x114 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x114 0.--9. 1. "RESERVED," line.long 0x118 "DISPC_WB_FIR_COEF_H12_C_k_9,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x118 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x118 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x118 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x118 0.--9. 1. "RESERVED," line.long 0x11C "DISPC_WB_FIR_COEF_H12_C_k_10,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x11C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x11C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x11C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x11C 0.--9. 1. "RESERVED," line.long 0x120 "DISPC_WB_FIR_COEF_H12_C_k_11,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x120 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x120 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x120 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x120 0.--9. 1. "RESERVED," line.long 0x124 "DISPC_WB_FIR_COEF_H12_C_k_12,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x124 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x124 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x124 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x124 0.--9. 1. "RESERVED," line.long 0x128 "DISPC_WB_FIR_COEF_H12_C_k_13,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x128 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x128 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x128 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x128 0.--9. 1. "RESERVED," line.long 0x12C "DISPC_WB_FIR_COEF_H12_C_k_14,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x12C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x12C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x12C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x12C 0.--9. 1. "RESERVED," line.long 0x130 "DISPC_WB_FIR_COEF_H12_C_k_15,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x130 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x130 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x130 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x130 0.--9. 1. "RESERVED," line.long 0x134 "DISPC_WB_FIR_COEF_V0_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x134 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x134 10.--29. 1. "RESERVED," newline hexmask.long.word 0x134 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x138 "DISPC_WB_FIR_COEF_V0_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x138 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x138 10.--29. 1. "RESERVED," newline hexmask.long.word 0x138 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x13C "DISPC_WB_FIR_COEF_V0_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x13C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x13C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x13C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x140 "DISPC_WB_FIR_COEF_V0_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x140 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x140 10.--29. 1. "RESERVED," newline hexmask.long.word 0x140 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x144 "DISPC_WB_FIR_COEF_V0_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x144 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x144 10.--29. 1. "RESERVED," newline hexmask.long.word 0x144 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x148 "DISPC_WB_FIR_COEF_V0_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x148 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x148 10.--29. 1. "RESERVED," newline hexmask.long.word 0x148 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x14C "DISPC_WB_FIR_COEF_V0_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x14C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x14C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x14C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x150 "DISPC_WB_FIR_COEF_V0_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x150 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x150 10.--29. 1. "RESERVED," newline hexmask.long.word 0x150 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x154 "DISPC_WB_FIR_COEF_V0_i_8,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x154 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x154 10.--29. 1. "RESERVED," newline hexmask.long.word 0x154 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x158 "DISPC_WB_FIR_COEF_V0_C_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x158 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x158 10.--29. 1. "RESERVED," newline hexmask.long.word 0x158 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x15C "DISPC_WB_FIR_COEF_V0_C_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x15C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x15C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x15C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x160 "DISPC_WB_FIR_COEF_V0_C_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x160 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x160 10.--29. 1. "RESERVED," newline hexmask.long.word 0x160 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x164 "DISPC_WB_FIR_COEF_V0_C_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x164 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x164 10.--29. 1. "RESERVED," newline hexmask.long.word 0x164 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x168 "DISPC_WB_FIR_COEF_V0_C_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x168 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x168 10.--29. 1. "RESERVED," newline hexmask.long.word 0x168 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x16C "DISPC_WB_FIR_COEF_V0_C_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x16C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x16C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x16C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x170 "DISPC_WB_FIR_COEF_V0_C_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x170 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x170 10.--29. 1. "RESERVED," newline hexmask.long.word 0x170 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x174 "DISPC_WB_FIR_COEF_V0_C_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x174 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x174 10.--29. 1. "RESERVED," newline hexmask.long.word 0x174 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x178 "DISPC_WB_FIR_COEF_V0_C_i_8,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x178 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x178 10.--29. 1. "RESERVED," newline hexmask.long.word 0x178 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x17C "DISPC_WB_FIR_COEF_V12_k_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x17C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x17C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x17C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x17C 0.--9. 1. "RESERVED," line.long 0x180 "DISPC_WB_FIR_COEF_V12_k_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x180 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x180 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x180 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x180 0.--9. 1. "RESERVED," line.long 0x184 "DISPC_WB_FIR_COEF_V12_k_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x184 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x184 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x184 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x184 0.--9. 1. "RESERVED," line.long 0x188 "DISPC_WB_FIR_COEF_V12_k_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x188 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x188 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x188 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x188 0.--9. 1. "RESERVED," line.long 0x18C "DISPC_WB_FIR_COEF_V12_k_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x18C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x18C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x18C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x18C 0.--9. 1. "RESERVED," line.long 0x190 "DISPC_WB_FIR_COEF_V12_k_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x190 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x190 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x190 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x190 0.--9. 1. "RESERVED," line.long 0x194 "DISPC_WB_FIR_COEF_V12_k_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x194 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x194 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x194 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x194 0.--9. 1. "RESERVED," line.long 0x198 "DISPC_WB_FIR_COEF_V12_k_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x198 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x198 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x198 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x198 0.--9. 1. "RESERVED," line.long 0x19C "DISPC_WB_FIR_COEF_V12_k_8,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x19C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x19C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x19C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x19C 0.--9. 1. "RESERVED," line.long 0x1A0 "DISPC_WB_FIR_COEF_V12_k_9,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1A0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1A0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1A0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1A0 0.--9. 1. "RESERVED," line.long 0x1A4 "DISPC_WB_FIR_COEF_V12_k_10,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1A4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1A4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1A4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1A4 0.--9. 1. "RESERVED," line.long 0x1A8 "DISPC_WB_FIR_COEF_V12_k_11,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1A8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1A8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1A8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1A8 0.--9. 1. "RESERVED," line.long 0x1AC "DISPC_WB_FIR_COEF_V12_k_12,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1AC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1AC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1AC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1AC 0.--9. 1. "RESERVED," line.long 0x1B0 "DISPC_WB_FIR_COEF_V12_k_13,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1B0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1B0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1B0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1B0 0.--9. 1. "RESERVED," line.long 0x1B4 "DISPC_WB_FIR_COEF_V12_k_14,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1B4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1B4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1B4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1B4 0.--9. 1. "RESERVED," line.long 0x1B8 "DISPC_WB_FIR_COEF_V12_k_15,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1B8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1B8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1B8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1B8 0.--9. 1. "RESERVED," line.long 0x1BC "DISPC_WB_FIR_COEF_V12_C_k_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1BC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1BC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1BC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1BC 0.--9. 1. "RESERVED," line.long 0x1C0 "DISPC_WB_FIR_COEF_V12_C_k_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1C0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1C0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1C0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1C0 0.--9. 1. "RESERVED," line.long 0x1C4 "DISPC_WB_FIR_COEF_V12_C_k_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1C4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1C4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1C4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1C4 0.--9. 1. "RESERVED," line.long 0x1C8 "DISPC_WB_FIR_COEF_V12_C_k_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1C8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1C8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1C8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1C8 0.--9. 1. "RESERVED," line.long 0x1CC "DISPC_WB_FIR_COEF_V12_C_k_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1CC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1CC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1CC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1CC 0.--9. 1. "RESERVED," line.long 0x1D0 "DISPC_WB_FIR_COEF_V12_C_k_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1D0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1D0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1D0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1D0 0.--9. 1. "RESERVED," line.long 0x1D4 "DISPC_WB_FIR_COEF_V12_C_k_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1D4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1D4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1D4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1D4 0.--9. 1. "RESERVED," line.long 0x1D8 "DISPC_WB_FIR_COEF_V12_C_k_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1D8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1D8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1D8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1D8 0.--9. 1. "RESERVED," line.long 0x1DC "DISPC_WB_FIR_COEF_V12_C_k_8,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1DC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1DC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1DC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1DC 0.--9. 1. "RESERVED," line.long 0x1E0 "DISPC_WB_FIR_COEF_V12_C_k_9,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1E0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1E0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1E0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1E0 0.--9. 1. "RESERVED," line.long 0x1E4 "DISPC_WB_FIR_COEF_V12_C_k_10,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1E4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1E4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1E4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1E4 0.--9. 1. "RESERVED," line.long 0x1E8 "DISPC_WB_FIR_COEF_V12_C_k_11,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1E8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1E8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1E8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1E8 0.--9. 1. "RESERVED," line.long 0x1EC "DISPC_WB_FIR_COEF_V12_C_k_12,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1EC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1EC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1EC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1EC 0.--9. 1. "RESERVED," line.long 0x1F0 "DISPC_WB_FIR_COEF_V12_C_k_13,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1F0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1F0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1F0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1F0 0.--9. 1. "RESERVED," line.long 0x1F4 "DISPC_WB_FIR_COEF_V12_C_k_14,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1F4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1F4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1F4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1F4 0.--9. 1. "RESERVED," line.long 0x1F8 "DISPC_WB_FIR_COEF_V12_C_k_15,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1F8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1F8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1F8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1F8 0.--9. 1. "RESERVED," line.long 0x1FC "DISPC_WB_IRQENABLE,This register allows to mask/unmask the module internal sources of interrupt. on an event-by-event basis" hexmask.long 0x1FC 5.--31. 1. "RESERVED," bitfld.long 0x1FC 4. "WBSYNC_EN,Write-back synced (configuration copied from shadow to work)" "WBSYNC_EN_0,WBSYNC_EN_1" newline bitfld.long 0x1FC 3. "WBREGIONBASEDEVENT_EN,For Write-back region-based event indicating end of current window" "WBREGIONBASEDEVENT_EN_0,WBREGIONBASEDEVENT_EN_1" bitfld.long 0x1FC 2. "WBFRAMEDONE_EN,Write-back Frame Done" "WBFRAMEDONE_EN_0,WBFRAMEDONE_EN_1" newline bitfld.long 0x1FC 1. "WBUNCOMPLETEERROR_EN,The write back buffer has been flushed before been fully drained" "WBUNCOMPLETEERROR_EN_0,WBUNCOMPLETEERROR_EN_1" bitfld.long 0x1FC 0. "WBBUFFEROVERFLOW_EN,Write-back DMA Buffer Overflow" "WBBUFFEROVERFLOW_EN_0,WBBUFFEROVERFLOW_EN_1" line.long 0x200 "DISPC_WB_IRQSTATUS,This register regroups all the status of the module internal events that generate an interrupt" hexmask.long 0x200 5.--31. 1. "RESERVED," bitfld.long 0x200 4. "WBSYNC_IRQ,Write-back synced (configuration copied from shadow to work)" "WBSYNC_IRQ_0,WBSYNC_IRQ_1" newline bitfld.long 0x200 3. "WBREGIONBASEDEVENT_IRQ,Write-back Frame Done" "WBREGIONBASEDEVENT_IRQ_0,WBREGIONBASEDEVENT_IRQ_1" bitfld.long 0x200 2. "WBFRAMEDONE_IRQ,Write-back Frame Done" "WBFRAMEDONE_IRQ_0,WBFRAMEDONE_IRQ_1" newline bitfld.long 0x200 1. "WBUNCOMPLETEERROR_IRQ,Write back DMA buffer is flushed before been completely drained" "WBUNCOMPLETEERROR_IRQ_0,WBUNCOMPLETEERROR_IRQ_1" bitfld.long 0x200 0. "WBBUFFEROVERFLOW_IRQ,Write-back DMA Buffer Overrflow" "WBBUFFEROVERFLOW_IRQ_0,WBBUFFEROVERFLOW_IRQ_1" line.long 0x204 "DISPC_WB_MFLAG_THRESHOLD," hexmask.long.word 0x204 16.--31. 1. "HT_MFLAG," hexmask.long.word 0x204 0.--15. 1. "LT_MFLAG," line.long 0x208 "DISPC_WB_PICTURE_SIZE,The register configures the size of the write-back picture associated with the write back pipeline after up/down-scaling (size of the image stored in DDR memory. generated by WB pipe)" rbitfld.long 0x208 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x208 16.--27. 1. "MEMSIZEY,Number of lines of the wb picture in memory Encoded value (from 1 to 4096) to specify the number of lines of the picture store in memory (program to value minus one)" newline rbitfld.long 0x208 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x208 0.--11. 1. "MEMSIZEX,Number of pixels of the wb picture in memory" group.long 0x210++0x0B line.long 0x00 "DISPC_WB_SIZE,The register configures the size of the output of overlay connected to the write-back pipeline when the overlay output is only used by the write-back pipeline" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 16.--27. 1. "SIZEY,Number of lines of the Write-back picture Encoded value (from 1 to 4096) to specify the number of lines of the write-back picture from overlay or pipeline" newline rbitfld.long 0x00 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. "SIZEX,Number of pixels of the Write-back picture Encoded value (from 1 to 4096) to specify the number of pixels of the write-back picture from overlay or pipeline" line.long 0x04 "DISPC_WB_POSITION,The register configures the start position of the window on overlay which wb will capture Shadow register" rbitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 16.--27. 1. "POSY,Y position of the video window Encoded value (from 0 to 4095) to specify the Y position of the video window #1 .The line at the top has the Y-position 0" newline rbitfld.long 0x04 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. "POSX,X position of the video window Encoded value (from 0 to 4095) to specify the X position of the video window #1" line.long 0x08 "DISPC_WB_REGION_BASED_TOTAL_PICTURE_SIZEY,The register configures the total sizey (total number of lines) of all the windows written back to the memory in Write-Back Region-based mode" hexmask.long.tbyte 0x08 12.--31. 1. "RESERVED," hexmask.long.word 0x08 0.--11. 1. "SIZEY,Total number of lines of the Write-back picture in Region-based mode Encoded value (from 1 to 4096) to specify the number of lines of the write-back picture from overlay or pipeline" width 0x0B tree.end tree "DMA" base ad:0x52020200 rgroup.long 0x00++0x07 line.long 0x00 "SIMCOP_DMA_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "SIMCOP_DMA_HWINFO,Information about the IP module's hardware configuration. i.e" hexmask.long 0x04 3.--31. 1. "RESERVED," bitfld.long 0x04 2. "CHAN,Logical channels" "CHAN_0_r,CHAN_1_r" newline bitfld.long 0x04 0.--1. "CONTEXT,Maximum outstanding OCP transactions" "CONTEXT_0_r,CONTEXT_1_r,CONTEXT_2_r,?" group.long 0x10++0x03 line.long 0x00 "SIMCOP_DMA_SYSCONFIG,Clock management configuration" hexmask.long 0x00 6.--31. 1. "RESERVED," bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x0B line.long 0x00 "SIMCOP_DMA_IRQ_EOI,End Of Interrupt number specification" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 0.--1. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1,?,?" line.long 0x04 "SIMCOP_DMA_CTRL," hexmask.long.word 0x04 16.--31. 1. "BW_LIMITER,SIMCOP DMA guarantees that there are at least BW_LIMITER functional clock cycles between two OCP requests" hexmask.long.byte 0x04 8.--15. 1. "RESERVED," newline bitfld.long 0x04 4.--7. "TAG_CNT,Limits the outstanding transactions count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 3. "POSTED_WRITES,Select write type" "POSTED_WRITES_0,POSTED_WRITES_1" newline rbitfld.long 0x04 2. "RESERVED," "0,1" bitfld.long 0x04 0.--1. "MAX_BURST_SIZE,Defines the maximum burst length for INCR bursts" "MAX_BURST_SIZE_0,MAX_BURST_SIZE_1,MAX_BURST_SIZE_2,MAX_BURST_SIZE_3" line.long 0x08 "SIMCOP_DMA_IRQSTATUS_RAW_j_0,Per-event raw interrupt status vector Raw status is set even if event is not enabled" bitfld.long 0x08 31. "CHAN7_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN7_FRAME_DONE_IRQ_0_r,CHAN7_FRAME_DONE_IRQ_1_w" bitfld.long 0x08 30. "CHAN6_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN6_FRAME_DONE_IRQ_0_r,CHAN6_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x08 29. "CHAN5_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN5_FRAME_DONE_IRQ_0_r,CHAN5_FRAME_DONE_IRQ_1_w" bitfld.long 0x08 28. "CHAN4_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN4_FRAME_DONE_IRQ_0_r,CHAN4_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x08 27. "CHAN3_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN3_FRAME_DONE_IRQ_0_r,CHAN3_FRAME_DONE_IRQ_1_w" bitfld.long 0x08 26. "CHAN2_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN2_FRAME_DONE_IRQ_0_r,CHAN2_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x08 25. "CHAN1_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN1_FRAME_DONE_IRQ_0_r,CHAN1_FRAME_DONE_IRQ_1_w" bitfld.long 0x08 24. "CHAN0_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN0_FRAME_DONE_IRQ_0_r,CHAN0_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x08 23. "CHAN7_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN7_BLOCK_DONE_IRQ_0_r,CHAN7_BLOCK_DONE_IRQ_1_w" bitfld.long 0x08 22. "CHAN6_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN6_BLOCK_DONE_IRQ_0_r,CHAN6_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x08 21. "CHAN5_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN5_BLOCK_DONE_IRQ_0_r,CHAN5_BLOCK_DONE_IRQ_1_w" bitfld.long 0x08 20. "CHAN4_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN4_BLOCK_DONE_IRQ_0_r,CHAN4_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x08 19. "CHAN3_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN3_BLOCK_DONE_IRQ_0_r,CHAN3_BLOCK_DONE_IRQ_1_w" bitfld.long 0x08 18. "CHAN2_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN2_BLOCK_DONE_IRQ_0_r,CHAN2_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x08 17. "CHAN1_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN1_BLOCK_DONE_IRQ_0_r,CHAN1_BLOCK_DONE_IRQ_1_w" bitfld.long 0x08 16. "CHAN0_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN0_BLOCK_DONE_IRQ_0_r,CHAN0_BLOCK_DONE_IRQ_1_w" newline hexmask.long.word 0x08 1.--15. 1. "RESERVED," bitfld.long 0x08 0. "OCP_ERR,OCP error" "OCP_ERR_0_r,OCP_ERR_1_w" group.long 0x30++0x03 line.long 0x00 "SIMCOP_DMA_IRQSTATUS_RAW_j_1,Per-event raw interrupt status vector Raw status is set even if event is not enabled" bitfld.long 0x00 31. "CHAN7_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN7_FRAME_DONE_IRQ_0_r,CHAN7_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 30. "CHAN6_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN6_FRAME_DONE_IRQ_0_r,CHAN6_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 29. "CHAN5_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN5_FRAME_DONE_IRQ_0_r,CHAN5_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 28. "CHAN4_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN4_FRAME_DONE_IRQ_0_r,CHAN4_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 27. "CHAN3_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN3_FRAME_DONE_IRQ_0_r,CHAN3_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 26. "CHAN2_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN2_FRAME_DONE_IRQ_0_r,CHAN2_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 25. "CHAN1_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN1_FRAME_DONE_IRQ_0_r,CHAN1_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 24. "CHAN0_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN0_FRAME_DONE_IRQ_0_r,CHAN0_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 23. "CHAN7_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN7_BLOCK_DONE_IRQ_0_r,CHAN7_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 22. "CHAN6_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN6_BLOCK_DONE_IRQ_0_r,CHAN6_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 21. "CHAN5_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN5_BLOCK_DONE_IRQ_0_r,CHAN5_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 20. "CHAN4_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN4_BLOCK_DONE_IRQ_0_r,CHAN4_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 19. "CHAN3_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN3_BLOCK_DONE_IRQ_0_r,CHAN3_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 18. "CHAN2_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN2_BLOCK_DONE_IRQ_0_r,CHAN2_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 17. "CHAN1_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN1_BLOCK_DONE_IRQ_0_r,CHAN1_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 16. "CHAN0_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN0_BLOCK_DONE_IRQ_0_r,CHAN0_BLOCK_DONE_IRQ_1_w" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," bitfld.long 0x00 0. "OCP_ERR,OCP error" "OCP_ERR_0_r,OCP_ERR_1_w" group.long 0x24++0x03 line.long 0x00 "SIMCOP_DMA_IRQSTATUS_j_0,Per-event 'enabled' interrupt status vector Enabled status isn't set unless event is enabled" bitfld.long 0x00 31. "CHAN7_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN7_FRAME_DONE_IRQ_0_r,CHAN7_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 30. "CHAN6_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN6_FRAME_DONE_IRQ_0_r,CHAN6_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 29. "CHAN5_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN5_FRAME_DONE_IRQ_0_r,CHAN5_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 28. "CHAN4_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN4_FRAME_DONE_IRQ_0_r,CHAN4_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 27. "CHAN3_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN3_FRAME_DONE_IRQ_0_r,CHAN3_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 26. "CHAN2_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN2_FRAME_DONE_IRQ_0_r,CHAN2_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 25. "CHAN1_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN1_FRAME_DONE_IRQ_0_r,CHAN1_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 24. "CHAN0_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN0_FRAME_DONE_IRQ_0_r,CHAN0_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 23. "CHAN7_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN7_BLOCK_DONE_IRQ_0_r,CHAN7_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 22. "CHAN6_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN6_BLOCK_DONE_IRQ_0_r,CHAN6_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 21. "CHAN5_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN5_BLOCK_DONE_IRQ_0_r,CHAN5_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 20. "CHAN4_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN4_BLOCK_DONE_IRQ_0_r,CHAN4_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 19. "CHAN3_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN3_BLOCK_DONE_IRQ_0_r,CHAN3_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 18. "CHAN2_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN2_BLOCK_DONE_IRQ_0_r,CHAN2_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 17. "CHAN1_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN1_BLOCK_DONE_IRQ_0_r,CHAN1_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 16. "CHAN0_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN0_BLOCK_DONE_IRQ_0_r,CHAN0_BLOCK_DONE_IRQ_1_w" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," bitfld.long 0x00 0. "BUS_ERR,BUS error" "BUS_ERR_0_r,BUS_ERR_1_w" group.long 0x34++0x03 line.long 0x00 "SIMCOP_DMA_IRQSTATUS_j_1,Per-event 'enabled' interrupt status vector Enabled status isn't set unless event is enabled" bitfld.long 0x00 31. "CHAN7_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN7_FRAME_DONE_IRQ_0_r,CHAN7_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 30. "CHAN6_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN6_FRAME_DONE_IRQ_0_r,CHAN6_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 29. "CHAN5_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN5_FRAME_DONE_IRQ_0_r,CHAN5_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 28. "CHAN4_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN4_FRAME_DONE_IRQ_0_r,CHAN4_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 27. "CHAN3_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN3_FRAME_DONE_IRQ_0_r,CHAN3_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 26. "CHAN2_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN2_FRAME_DONE_IRQ_0_r,CHAN2_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 25. "CHAN1_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN1_FRAME_DONE_IRQ_0_r,CHAN1_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 24. "CHAN0_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN0_FRAME_DONE_IRQ_0_r,CHAN0_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 23. "CHAN7_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN7_BLOCK_DONE_IRQ_0_r,CHAN7_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 22. "CHAN6_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN6_BLOCK_DONE_IRQ_0_r,CHAN6_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 21. "CHAN5_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN5_BLOCK_DONE_IRQ_0_r,CHAN5_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 20. "CHAN4_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN4_BLOCK_DONE_IRQ_0_r,CHAN4_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 19. "CHAN3_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN3_BLOCK_DONE_IRQ_0_r,CHAN3_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 18. "CHAN2_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN2_BLOCK_DONE_IRQ_0_r,CHAN2_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 17. "CHAN1_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN1_BLOCK_DONE_IRQ_0_r,CHAN1_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 16. "CHAN0_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN0_BLOCK_DONE_IRQ_0_r,CHAN0_BLOCK_DONE_IRQ_1_w" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," bitfld.long 0x00 0. "BUS_ERR,BUS error" "BUS_ERR_0_r,BUS_ERR_1_w" group.long 0x28++0x03 line.long 0x00 "SIMCOP_DMA_IRQENABLE_SET_j_0,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "CHAN7_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN7_FRAME_DONE_IRQ_0_r,CHAN7_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 30. "CHAN6_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN6_FRAME_DONE_IRQ_0_r,CHAN6_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 29. "CHAN5_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN5_FRAME_DONE_IRQ_0_r,CHAN5_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 28. "CHAN4_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN4_FRAME_DONE_IRQ_0_r,CHAN4_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 27. "CHAN3_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN3_FRAME_DONE_IRQ_0_r,CHAN3_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 26. "CHAN2_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN2_FRAME_DONE_IRQ_0_r,CHAN2_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 25. "CHAN1_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN1_FRAME_DONE_IRQ_0_r,CHAN1_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 24. "CHAN0_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN0_FRAME_DONE_IRQ_0_r,CHAN0_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 23. "CHAN7_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN7_BLOCK_DONE_IRQ_0_r,CHAN7_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 22. "CHAN6_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN6_BLOCK_DONE_IRQ_0_r,CHAN6_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 21. "CHAN5_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN5_BLOCK_DONE_IRQ_0_r,CHAN5_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 20. "CHAN4_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN4_BLOCK_DONE_IRQ_0_r,CHAN4_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 19. "CHAN3_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN3_BLOCK_DONE_IRQ_0_r,CHAN3_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 18. "CHAN2_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN2_BLOCK_DONE_IRQ_0_r,CHAN2_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 17. "CHAN1_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN1_BLOCK_DONE_IRQ_0_r,CHAN1_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 16. "CHAN0_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN0_BLOCK_DONE_IRQ_0_r,CHAN0_BLOCK_DONE_IRQ_1_w" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," bitfld.long 0x00 0. "OCP_ERR,OCP error" "OCP_ERR_0_r,OCP_ERR_1_w" group.long 0x38++0x03 line.long 0x00 "SIMCOP_DMA_IRQENABLE_SET_j_1,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "CHAN7_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN7_FRAME_DONE_IRQ_0_r,CHAN7_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 30. "CHAN6_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN6_FRAME_DONE_IRQ_0_r,CHAN6_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 29. "CHAN5_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN5_FRAME_DONE_IRQ_0_r,CHAN5_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 28. "CHAN4_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN4_FRAME_DONE_IRQ_0_r,CHAN4_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 27. "CHAN3_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN3_FRAME_DONE_IRQ_0_r,CHAN3_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 26. "CHAN2_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN2_FRAME_DONE_IRQ_0_r,CHAN2_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 25. "CHAN1_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN1_FRAME_DONE_IRQ_0_r,CHAN1_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 24. "CHAN0_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN0_FRAME_DONE_IRQ_0_r,CHAN0_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 23. "CHAN7_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN7_BLOCK_DONE_IRQ_0_r,CHAN7_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 22. "CHAN6_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN6_BLOCK_DONE_IRQ_0_r,CHAN6_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 21. "CHAN5_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN5_BLOCK_DONE_IRQ_0_r,CHAN5_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 20. "CHAN4_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN4_BLOCK_DONE_IRQ_0_r,CHAN4_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 19. "CHAN3_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN3_BLOCK_DONE_IRQ_0_r,CHAN3_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 18. "CHAN2_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN2_BLOCK_DONE_IRQ_0_r,CHAN2_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 17. "CHAN1_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN1_BLOCK_DONE_IRQ_0_r,CHAN1_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 16. "CHAN0_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN0_BLOCK_DONE_IRQ_0_r,CHAN0_BLOCK_DONE_IRQ_1_w" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," bitfld.long 0x00 0. "OCP_ERR,OCP error" "OCP_ERR_0_r,OCP_ERR_1_w" group.long 0x2C++0x03 line.long 0x00 "SIMCOP_DMA_IRQENABLE_CLR_j_0,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "CHAN7_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN7_FRAME_DONE_IRQ_0_r,CHAN7_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 30. "CHAN6_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN6_FRAME_DONE_IRQ_0_r,CHAN6_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 29. "CHAN5_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN5_FRAME_DONE_IRQ_0_r,CHAN5_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 28. "CHAN4_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN4_FRAME_DONE_IRQ_0_r,CHAN4_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 27. "CHAN3_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN3_FRAME_DONE_IRQ_0_r,CHAN3_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 26. "CHAN2_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN2_FRAME_DONE_IRQ_0_r,CHAN2_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 25. "CHAN1_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN1_FRAME_DONE_IRQ_0_r,CHAN1_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 24. "CHAN0_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN0_FRAME_DONE_IRQ_0_r,CHAN0_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 23. "CHAN7_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN7_BLOCK_DONE_IRQ_0_r,CHAN7_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 22. "CHAN6_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN6_BLOCK_DONE_IRQ_0_r,CHAN6_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 21. "CHAN5_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN5_BLOCK_DONE_IRQ_0_r,CHAN5_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 20. "CHAN4_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN4_BLOCK_DONE_IRQ_0_r,CHAN4_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 19. "CHAN3_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN3_BLOCK_DONE_IRQ_0_r,CHAN3_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 18. "CHAN2_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN2_BLOCK_DONE_IRQ_0_r,CHAN2_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 17. "CHAN1_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN1_BLOCK_DONE_IRQ_0_r,CHAN1_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 16. "CHAN0_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN0_BLOCK_DONE_IRQ_0_r,CHAN0_BLOCK_DONE_IRQ_1_w" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," bitfld.long 0x00 0. "OCP_ERR,OCP error" "OCP_ERR_0_r,OCP_ERR_1_w" group.long 0x3C++0x03 line.long 0x00 "SIMCOP_DMA_IRQENABLE_CLR_j_1,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "CHAN7_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN7_FRAME_DONE_IRQ_0_r,CHAN7_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 30. "CHAN6_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN6_FRAME_DONE_IRQ_0_r,CHAN6_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 29. "CHAN5_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN5_FRAME_DONE_IRQ_0_r,CHAN5_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 28. "CHAN4_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN4_FRAME_DONE_IRQ_0_r,CHAN4_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 27. "CHAN3_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN3_FRAME_DONE_IRQ_0_r,CHAN3_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 26. "CHAN2_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN2_FRAME_DONE_IRQ_0_r,CHAN2_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 25. "CHAN1_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN1_FRAME_DONE_IRQ_0_r,CHAN1_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 24. "CHAN0_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN0_FRAME_DONE_IRQ_0_r,CHAN0_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 23. "CHAN7_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN7_BLOCK_DONE_IRQ_0_r,CHAN7_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 22. "CHAN6_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN6_BLOCK_DONE_IRQ_0_r,CHAN6_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 21. "CHAN5_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN5_BLOCK_DONE_IRQ_0_r,CHAN5_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 20. "CHAN4_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN4_BLOCK_DONE_IRQ_0_r,CHAN4_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 19. "CHAN3_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN3_BLOCK_DONE_IRQ_0_r,CHAN3_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 18. "CHAN2_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN2_BLOCK_DONE_IRQ_0_r,CHAN2_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 17. "CHAN1_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN1_BLOCK_DONE_IRQ_0_r,CHAN1_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 16. "CHAN0_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN0_BLOCK_DONE_IRQ_0_r,CHAN0_BLOCK_DONE_IRQ_1_w" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," bitfld.long 0x00 0. "OCP_ERR,OCP error" "OCP_ERR_0_r,OCP_ERR_1_w" group.long 0x80++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_0,Logical channel control register" hexmask.long.word 0x00 23.--31. 1. "RESERVED," bitfld.long 0x00 20.--22. "HWSTOP,DMA logical channel HW synchronization" "HWSTOP_0,?,?,?,HWSTOP_4,HWSTOP_5,HWSTOP_6,HWSTOP_7" newline bitfld.long 0x00 17.--19. "HWSTART,DMA logical channel HW synchronization" "HWSTART_0,?,?,?,HWSTART_4,HWSTART_5,HWSTART_6,HWSTART_7" bitfld.long 0x00 12.--16. "LINKED,DMA logical channel linking" "LINKED_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,LINKED_16,LINKED_17,LINKED_18,LINKED_19,LINKED_20,LINKED_21,LINKED_22,LINKED_23,?,?,?,?,?,?,?,?" newline rbitfld.long 0x00 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 7.--8. "GRID,Selects the grid to be used when TILERMODE=1" "GRID_0,GRID_1,GRID_2,GRID_3" newline bitfld.long 0x00 6. "TILERMODE,Selects OCP transaction breakdown algorithm" "TILERMODE_0,TILERMODE_1" bitfld.long 0x00 5. "DIR,Transfer direction" "DIR_0,DIR_1" newline rbitfld.long 0x00 3.--4. "STATUS,SW could poll this bit to know the state of the channel" "STATUS_0_r,STATUS_1_r,STATUS_2_r,STATUS_3_r" bitfld.long 0x00 2. "SWTRIGGER,Software trigger of the DMA channel" "SWTRIGGER_0_w,SWTRIGGER_1_w" newline bitfld.long 0x00 1. "DISABLE,Disable control of the logical channel" "DISABLE_0_w,DISABLE_1_w" bitfld.long 0x00 0. "ENABLE,Enable control of the logical channel" "ENABLE_0_w,ENABLE_1_w" group.long 0xB0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_1,Logical channel control register" hexmask.long.word 0x00 23.--31. 1. "RESERVED," bitfld.long 0x00 20.--22. "HWSTOP,DMA logical channel HW synchronization" "HWSTOP_0,?,?,?,HWSTOP_4,HWSTOP_5,HWSTOP_6,HWSTOP_7" newline bitfld.long 0x00 17.--19. "HWSTART,DMA logical channel HW synchronization" "HWSTART_0,?,?,?,HWSTART_4,HWSTART_5,HWSTART_6,HWSTART_7" bitfld.long 0x00 12.--16. "LINKED,DMA logical channel linking" "LINKED_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,LINKED_16,LINKED_17,LINKED_18,LINKED_19,LINKED_20,LINKED_21,LINKED_22,LINKED_23,?,?,?,?,?,?,?,?" newline rbitfld.long 0x00 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 7.--8. "GRID,Selects the grid to be used when TILERMODE=1" "GRID_0,GRID_1,GRID_2,GRID_3" newline bitfld.long 0x00 6. "TILERMODE,Selects OCP transaction breakdown algorithm" "TILERMODE_0,TILERMODE_1" bitfld.long 0x00 5. "DIR,Transfer direction" "DIR_0,DIR_1" newline rbitfld.long 0x00 3.--4. "STATUS,SW could poll this bit to know the state of the channel" "STATUS_0_r,STATUS_1_r,STATUS_2_r,STATUS_3_r" bitfld.long 0x00 2. "SWTRIGGER,Software trigger of the DMA channel" "SWTRIGGER_0_w,SWTRIGGER_1_w" newline bitfld.long 0x00 1. "DISABLE,Disable control of the logical channel" "DISABLE_0_w,DISABLE_1_w" bitfld.long 0x00 0. "ENABLE,Enable control of the logical channel" "ENABLE_0_w,ENABLE_1_w" group.long 0xE0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_2,Logical channel control register" hexmask.long.word 0x00 23.--31. 1. "RESERVED," bitfld.long 0x00 20.--22. "HWSTOP,DMA logical channel HW synchronization" "HWSTOP_0,?,?,?,HWSTOP_4,HWSTOP_5,HWSTOP_6,HWSTOP_7" newline bitfld.long 0x00 17.--19. "HWSTART,DMA logical channel HW synchronization" "HWSTART_0,?,?,?,HWSTART_4,HWSTART_5,HWSTART_6,HWSTART_7" bitfld.long 0x00 12.--16. "LINKED,DMA logical channel linking" "LINKED_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,LINKED_16,LINKED_17,LINKED_18,LINKED_19,LINKED_20,LINKED_21,LINKED_22,LINKED_23,?,?,?,?,?,?,?,?" newline rbitfld.long 0x00 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 7.--8. "GRID,Selects the grid to be used when TILERMODE=1" "GRID_0,GRID_1,GRID_2,GRID_3" newline bitfld.long 0x00 6. "TILERMODE,Selects OCP transaction breakdown algorithm" "TILERMODE_0,TILERMODE_1" bitfld.long 0x00 5. "DIR,Transfer direction" "DIR_0,DIR_1" newline rbitfld.long 0x00 3.--4. "STATUS,SW could poll this bit to know the state of the channel" "STATUS_0_r,STATUS_1_r,STATUS_2_r,STATUS_3_r" bitfld.long 0x00 2. "SWTRIGGER,Software trigger of the DMA channel" "SWTRIGGER_0_w,SWTRIGGER_1_w" newline bitfld.long 0x00 1. "DISABLE,Disable control of the logical channel" "DISABLE_0_w,DISABLE_1_w" bitfld.long 0x00 0. "ENABLE,Enable control of the logical channel" "ENABLE_0_w,ENABLE_1_w" group.long 0x110++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_3,Logical channel control register" hexmask.long.word 0x00 23.--31. 1. "RESERVED," bitfld.long 0x00 20.--22. "HWSTOP,DMA logical channel HW synchronization" "HWSTOP_0,?,?,?,HWSTOP_4,HWSTOP_5,HWSTOP_6,HWSTOP_7" newline bitfld.long 0x00 17.--19. "HWSTART,DMA logical channel HW synchronization" "HWSTART_0,?,?,?,HWSTART_4,HWSTART_5,HWSTART_6,HWSTART_7" bitfld.long 0x00 12.--16. "LINKED,DMA logical channel linking" "LINKED_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,LINKED_16,LINKED_17,LINKED_18,LINKED_19,LINKED_20,LINKED_21,LINKED_22,LINKED_23,?,?,?,?,?,?,?,?" newline rbitfld.long 0x00 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 7.--8. "GRID,Selects the grid to be used when TILERMODE=1" "GRID_0,GRID_1,GRID_2,GRID_3" newline bitfld.long 0x00 6. "TILERMODE,Selects OCP transaction breakdown algorithm" "TILERMODE_0,TILERMODE_1" bitfld.long 0x00 5. "DIR,Transfer direction" "DIR_0,DIR_1" newline rbitfld.long 0x00 3.--4. "STATUS,SW could poll this bit to know the state of the channel" "STATUS_0_r,STATUS_1_r,STATUS_2_r,STATUS_3_r" bitfld.long 0x00 2. "SWTRIGGER,Software trigger of the DMA channel" "SWTRIGGER_0_w,SWTRIGGER_1_w" newline bitfld.long 0x00 1. "DISABLE,Disable control of the logical channel" "DISABLE_0_w,DISABLE_1_w" bitfld.long 0x00 0. "ENABLE,Enable control of the logical channel" "ENABLE_0_w,ENABLE_1_w" group.long 0x140++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_4,Logical channel control register" hexmask.long.word 0x00 23.--31. 1. "RESERVED," bitfld.long 0x00 20.--22. "HWSTOP,DMA logical channel HW synchronization" "HWSTOP_0,?,?,?,HWSTOP_4,HWSTOP_5,HWSTOP_6,HWSTOP_7" newline bitfld.long 0x00 17.--19. "HWSTART,DMA logical channel HW synchronization" "HWSTART_0,?,?,?,HWSTART_4,HWSTART_5,HWSTART_6,HWSTART_7" bitfld.long 0x00 12.--16. "LINKED,DMA logical channel linking" "LINKED_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,LINKED_16,LINKED_17,LINKED_18,LINKED_19,LINKED_20,LINKED_21,LINKED_22,LINKED_23,?,?,?,?,?,?,?,?" newline rbitfld.long 0x00 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 7.--8. "GRID,Selects the grid to be used when TILERMODE=1" "GRID_0,GRID_1,GRID_2,GRID_3" newline bitfld.long 0x00 6. "TILERMODE,Selects OCP transaction breakdown algorithm" "TILERMODE_0,TILERMODE_1" bitfld.long 0x00 5. "DIR,Transfer direction" "DIR_0,DIR_1" newline rbitfld.long 0x00 3.--4. "STATUS,SW could poll this bit to know the state of the channel" "STATUS_0_r,STATUS_1_r,STATUS_2_r,STATUS_3_r" bitfld.long 0x00 2. "SWTRIGGER,Software trigger of the DMA channel" "SWTRIGGER_0_w,SWTRIGGER_1_w" newline bitfld.long 0x00 1. "DISABLE,Disable control of the logical channel" "DISABLE_0_w,DISABLE_1_w" bitfld.long 0x00 0. "ENABLE,Enable control of the logical channel" "ENABLE_0_w,ENABLE_1_w" group.long 0x170++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_5,Logical channel control register" hexmask.long.word 0x00 23.--31. 1. "RESERVED," bitfld.long 0x00 20.--22. "HWSTOP,DMA logical channel HW synchronization" "HWSTOP_0,?,?,?,HWSTOP_4,HWSTOP_5,HWSTOP_6,HWSTOP_7" newline bitfld.long 0x00 17.--19. "HWSTART,DMA logical channel HW synchronization" "HWSTART_0,?,?,?,HWSTART_4,HWSTART_5,HWSTART_6,HWSTART_7" bitfld.long 0x00 12.--16. "LINKED,DMA logical channel linking" "LINKED_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,LINKED_16,LINKED_17,LINKED_18,LINKED_19,LINKED_20,LINKED_21,LINKED_22,LINKED_23,?,?,?,?,?,?,?,?" newline rbitfld.long 0x00 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 7.--8. "GRID,Selects the grid to be used when TILERMODE=1" "GRID_0,GRID_1,GRID_2,GRID_3" newline bitfld.long 0x00 6. "TILERMODE,Selects OCP transaction breakdown algorithm" "TILERMODE_0,TILERMODE_1" bitfld.long 0x00 5. "DIR,Transfer direction" "DIR_0,DIR_1" newline rbitfld.long 0x00 3.--4. "STATUS,SW could poll this bit to know the state of the channel" "STATUS_0_r,STATUS_1_r,STATUS_2_r,STATUS_3_r" bitfld.long 0x00 2. "SWTRIGGER,Software trigger of the DMA channel" "SWTRIGGER_0_w,SWTRIGGER_1_w" newline bitfld.long 0x00 1. "DISABLE,Disable control of the logical channel" "DISABLE_0_w,DISABLE_1_w" bitfld.long 0x00 0. "ENABLE,Enable control of the logical channel" "ENABLE_0_w,ENABLE_1_w" group.long 0x1A0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_6,Logical channel control register" hexmask.long.word 0x00 23.--31. 1. "RESERVED," bitfld.long 0x00 20.--22. "HWSTOP,DMA logical channel HW synchronization" "HWSTOP_0,?,?,?,HWSTOP_4,HWSTOP_5,HWSTOP_6,HWSTOP_7" newline bitfld.long 0x00 17.--19. "HWSTART,DMA logical channel HW synchronization" "HWSTART_0,?,?,?,HWSTART_4,HWSTART_5,HWSTART_6,HWSTART_7" bitfld.long 0x00 12.--16. "LINKED,DMA logical channel linking" "LINKED_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,LINKED_16,LINKED_17,LINKED_18,LINKED_19,LINKED_20,LINKED_21,LINKED_22,LINKED_23,?,?,?,?,?,?,?,?" newline rbitfld.long 0x00 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 7.--8. "GRID,Selects the grid to be used when TILERMODE=1" "GRID_0,GRID_1,GRID_2,GRID_3" newline bitfld.long 0x00 6. "TILERMODE,Selects OCP transaction breakdown algorithm" "TILERMODE_0,TILERMODE_1" bitfld.long 0x00 5. "DIR,Transfer direction" "DIR_0,DIR_1" newline rbitfld.long 0x00 3.--4. "STATUS,SW could poll this bit to know the state of the channel" "STATUS_0_r,STATUS_1_r,STATUS_2_r,STATUS_3_r" bitfld.long 0x00 2. "SWTRIGGER,Software trigger of the DMA channel" "SWTRIGGER_0_w,SWTRIGGER_1_w" newline bitfld.long 0x00 1. "DISABLE,Disable control of the logical channel" "DISABLE_0_w,DISABLE_1_w" bitfld.long 0x00 0. "ENABLE,Enable control of the logical channel" "ENABLE_0_w,ENABLE_1_w" group.long 0x1D0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_7,Logical channel control register" hexmask.long.word 0x00 23.--31. 1. "RESERVED," bitfld.long 0x00 20.--22. "HWSTOP,DMA logical channel HW synchronization" "HWSTOP_0,?,?,?,HWSTOP_4,HWSTOP_5,HWSTOP_6,HWSTOP_7" newline bitfld.long 0x00 17.--19. "HWSTART,DMA logical channel HW synchronization" "HWSTART_0,?,?,?,HWSTART_4,HWSTART_5,HWSTART_6,HWSTART_7" bitfld.long 0x00 12.--16. "LINKED,DMA logical channel linking" "LINKED_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,LINKED_16,LINKED_17,LINKED_18,LINKED_19,LINKED_20,LINKED_21,LINKED_22,LINKED_23,?,?,?,?,?,?,?,?" newline rbitfld.long 0x00 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 7.--8. "GRID,Selects the grid to be used when TILERMODE=1" "GRID_0,GRID_1,GRID_2,GRID_3" newline bitfld.long 0x00 6. "TILERMODE,Selects OCP transaction breakdown algorithm" "TILERMODE_0,TILERMODE_1" bitfld.long 0x00 5. "DIR,Transfer direction" "DIR_0,DIR_1" newline rbitfld.long 0x00 3.--4. "STATUS,SW could poll this bit to know the state of the channel" "STATUS_0_r,STATUS_1_r,STATUS_2_r,STATUS_3_r" bitfld.long 0x00 2. "SWTRIGGER,Software trigger of the DMA channel" "SWTRIGGER_0_w,SWTRIGGER_1_w" newline bitfld.long 0x00 1. "DISABLE,Disable control of the logical channel" "DISABLE_0_w,DISABLE_1_w" bitfld.long 0x00 0. "ENABLE,Enable control of the logical channel" "ENABLE_0_w,ENABLE_1_w" group.long 0x84++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_0,System memory address" hexmask.long 0x00 4.--31. 1. "ADDR,Address in 128-bit words" rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_1,System memory address" hexmask.long 0x00 4.--31. 1. "ADDR,Address in 128-bit words" rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xE4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_2,System memory address" hexmask.long 0x00 4.--31. 1. "ADDR,Address in 128-bit words" rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x114++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_3,System memory address" hexmask.long 0x00 4.--31. 1. "ADDR,Address in 128-bit words" rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x144++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_4,System memory address" hexmask.long 0x00 4.--31. 1. "ADDR,Address in 128-bit words" rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x174++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_5,System memory address" hexmask.long 0x00 4.--31. 1. "ADDR,Address in 128-bit words" rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1A4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_6,System memory address" hexmask.long 0x00 4.--31. 1. "ADDR,Address in 128-bit words" rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1D4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_7,System memory address" hexmask.long 0x00 4.--31. 1. "ADDR,Address in 128-bit words" rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x88++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_OFST_i_0,System memory line offset in 128-bit words" hexmask.long.word 0x00 20.--31. 1. "RESERVED," hexmask.long.word 0x00 4.--19. 1. "OFST,Line offset" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB8++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_OFST_i_1,System memory line offset in 128-bit words" hexmask.long.word 0x00 20.--31. 1. "RESERVED," hexmask.long.word 0x00 4.--19. 1. "OFST,Line offset" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xE8++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_OFST_i_2,System memory line offset in 128-bit words" hexmask.long.word 0x00 20.--31. 1. "RESERVED," hexmask.long.word 0x00 4.--19. 1. "OFST,Line offset" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x118++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_OFST_i_3,System memory line offset in 128-bit words" hexmask.long.word 0x00 20.--31. 1. "RESERVED," hexmask.long.word 0x00 4.--19. 1. "OFST,Line offset" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x148++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_OFST_i_4,System memory line offset in 128-bit words" hexmask.long.word 0x00 20.--31. 1. "RESERVED," hexmask.long.word 0x00 4.--19. 1. "OFST,Line offset" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x178++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_OFST_i_5,System memory line offset in 128-bit words" hexmask.long.word 0x00 20.--31. 1. "RESERVED," hexmask.long.word 0x00 4.--19. 1. "OFST,Line offset" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1A8++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_OFST_i_6,System memory line offset in 128-bit words" hexmask.long.word 0x00 20.--31. 1. "RESERVED," hexmask.long.word 0x00 4.--19. 1. "OFST,Line offset" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1D8++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_OFST_i_7,System memory line offset in 128-bit words" hexmask.long.word 0x00 20.--31. 1. "RESERVED," hexmask.long.word 0x00 4.--19. 1. "OFST,Line offset" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8C++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_0,SIMCOP memory line offset" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 4.--23. 1. "OFST,Line offset" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xBC++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_1,SIMCOP memory line offset" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 4.--23. 1. "OFST,Line offset" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEC++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_2,SIMCOP memory line offset" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 4.--23. 1. "OFST,Line offset" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x11C++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_3,SIMCOP memory line offset" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 4.--23. 1. "OFST,Line offset" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x14C++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_4,SIMCOP memory line offset" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 4.--23. 1. "OFST,Line offset" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x17C++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_5,SIMCOP memory line offset" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 4.--23. 1. "OFST,Line offset" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1AC++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_6,SIMCOP memory line offset" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 4.--23. 1. "OFST,Line offset" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1DC++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_7,SIMCOP memory line offset" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 4.--23. 1. "OFST,Line offset" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x90++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_0,SIMCOP memory address" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Address in 128-bit words" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_1,SIMCOP memory address" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Address in 128-bit words" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xF0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_2,SIMCOP memory address" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Address in 128-bit words" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x120++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_3,SIMCOP memory address" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Address in 128-bit words" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x150++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_4,SIMCOP memory address" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Address in 128-bit words" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x180++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_5,SIMCOP memory address" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Address in 128-bit words" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1B0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_6,SIMCOP memory address" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Address in 128-bit words" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1E0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_7,SIMCOP memory address" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Address in 128-bit words" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x94++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_0,2D block size" rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "YNUM,Height in lines per 2D block Valid values are 1- 8191" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 4.--13. 1. "XNUM,Width in 128-bit words per 2D block" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_1,2D block size" rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "YNUM,Height in lines per 2D block Valid values are 1- 8191" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 4.--13. 1. "XNUM,Width in 128-bit words per 2D block" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xF4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_2,2D block size" rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "YNUM,Height in lines per 2D block Valid values are 1- 8191" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 4.--13. 1. "XNUM,Width in 128-bit words per 2D block" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x124++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_3,2D block size" rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "YNUM,Height in lines per 2D block Valid values are 1- 8191" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 4.--13. 1. "XNUM,Width in 128-bit words per 2D block" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x154++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_4,2D block size" rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "YNUM,Height in lines per 2D block Valid values are 1- 8191" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 4.--13. 1. "XNUM,Width in 128-bit words per 2D block" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x184++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_5,2D block size" rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "YNUM,Height in lines per 2D block Valid values are 1- 8191" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 4.--13. 1. "XNUM,Width in 128-bit words per 2D block" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1B4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_6,2D block size" rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "YNUM,Height in lines per 2D block Valid values are 1- 8191" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 4.--13. 1. "XNUM,Width in 128-bit words per 2D block" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1E4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_7,2D block size" rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "YNUM,Height in lines per 2D block Valid values are 1- 8191" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 4.--13. 1. "XNUM,Width in 128-bit words per 2D block" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x98++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_0,Defines a frame" rbitfld.long 0x00 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "YCNT,Vertical count of 2D blocks per frame" newline rbitfld.long 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. "XCNT,Horizontal count of 2D blocks per frame" group.long 0xC8++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_1,Defines a frame" rbitfld.long 0x00 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "YCNT,Vertical count of 2D blocks per frame" newline rbitfld.long 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. "XCNT,Horizontal count of 2D blocks per frame" group.long 0xF8++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_2,Defines a frame" rbitfld.long 0x00 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "YCNT,Vertical count of 2D blocks per frame" newline rbitfld.long 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. "XCNT,Horizontal count of 2D blocks per frame" group.long 0x128++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_3,Defines a frame" rbitfld.long 0x00 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "YCNT,Vertical count of 2D blocks per frame" newline rbitfld.long 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. "XCNT,Horizontal count of 2D blocks per frame" group.long 0x158++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_4,Defines a frame" rbitfld.long 0x00 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "YCNT,Vertical count of 2D blocks per frame" newline rbitfld.long 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. "XCNT,Horizontal count of 2D blocks per frame" group.long 0x188++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_5,Defines a frame" rbitfld.long 0x00 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "YCNT,Vertical count of 2D blocks per frame" newline rbitfld.long 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. "XCNT,Horizontal count of 2D blocks per frame" group.long 0x1B8++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_6,Defines a frame" rbitfld.long 0x00 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "YCNT,Vertical count of 2D blocks per frame" newline rbitfld.long 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. "XCNT,Horizontal count of 2D blocks per frame" group.long 0x1E8++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_7,Defines a frame" rbitfld.long 0x00 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "YCNT,Vertical count of 2D blocks per frame" newline rbitfld.long 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. "XCNT,Horizontal count of 2D blocks per frame" rgroup.long 0xA0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_0,SW could read the coordinates of the last transferred block" bitfld.long 0x00 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "BY,Vertical position of the last transferred 2D block in the frame" newline bitfld.long 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. "BX,Horizontal position of the last transferred 2D block in the frame" rgroup.long 0xD0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_1,SW could read the coordinates of the last transferred block" bitfld.long 0x00 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "BY,Vertical position of the last transferred 2D block in the frame" newline bitfld.long 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. "BX,Horizontal position of the last transferred 2D block in the frame" rgroup.long 0x100++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_2,SW could read the coordinates of the last transferred block" bitfld.long 0x00 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "BY,Vertical position of the last transferred 2D block in the frame" newline bitfld.long 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. "BX,Horizontal position of the last transferred 2D block in the frame" rgroup.long 0x130++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_3,SW could read the coordinates of the last transferred block" bitfld.long 0x00 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "BY,Vertical position of the last transferred 2D block in the frame" newline bitfld.long 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. "BX,Horizontal position of the last transferred 2D block in the frame" rgroup.long 0x160++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_4,SW could read the coordinates of the last transferred block" bitfld.long 0x00 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "BY,Vertical position of the last transferred 2D block in the frame" newline bitfld.long 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. "BX,Horizontal position of the last transferred 2D block in the frame" rgroup.long 0x190++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_5,SW could read the coordinates of the last transferred block" bitfld.long 0x00 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "BY,Vertical position of the last transferred 2D block in the frame" newline bitfld.long 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. "BX,Horizontal position of the last transferred 2D block in the frame" rgroup.long 0x1C0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_6,SW could read the coordinates of the last transferred block" bitfld.long 0x00 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "BY,Vertical position of the last transferred 2D block in the frame" newline bitfld.long 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. "BX,Horizontal position of the last transferred 2D block in the frame" rgroup.long 0x1F0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_7,SW could read the coordinates of the last transferred block" bitfld.long 0x00 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "BY,Vertical position of the last transferred 2D block in the frame" newline bitfld.long 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. "BX,Horizontal position of the last transferred 2D block in the frame" group.long 0xA4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_0,Offset between 2D blocks" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "YSTEP,Vertical offset in lines between rows of 2D blocks" newline rbitfld.long 0x00 15. "RESERVED," "0,1" hexmask.long.word 0x00 4.--14. 1. "XSTEP,Horizontal offset in 128-bit words between 2D block columns" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_1,Offset between 2D blocks" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "YSTEP,Vertical offset in lines between rows of 2D blocks" newline rbitfld.long 0x00 15. "RESERVED," "0,1" hexmask.long.word 0x00 4.--14. 1. "XSTEP,Horizontal offset in 128-bit words between 2D block columns" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x104++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_2,Offset between 2D blocks" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "YSTEP,Vertical offset in lines between rows of 2D blocks" newline rbitfld.long 0x00 15. "RESERVED," "0,1" hexmask.long.word 0x00 4.--14. 1. "XSTEP,Horizontal offset in 128-bit words between 2D block columns" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x134++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_3,Offset between 2D blocks" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "YSTEP,Vertical offset in lines between rows of 2D blocks" newline rbitfld.long 0x00 15. "RESERVED," "0,1" hexmask.long.word 0x00 4.--14. 1. "XSTEP,Horizontal offset in 128-bit words between 2D block columns" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x164++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_4,Offset between 2D blocks" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "YSTEP,Vertical offset in lines between rows of 2D blocks" newline rbitfld.long 0x00 15. "RESERVED," "0,1" hexmask.long.word 0x00 4.--14. 1. "XSTEP,Horizontal offset in 128-bit words between 2D block columns" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x194++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_5,Offset between 2D blocks" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "YSTEP,Vertical offset in lines between rows of 2D blocks" newline rbitfld.long 0x00 15. "RESERVED," "0,1" hexmask.long.word 0x00 4.--14. 1. "XSTEP,Horizontal offset in 128-bit words between 2D block columns" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_6,Offset between 2D blocks" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "YSTEP,Vertical offset in lines between rows of 2D blocks" newline rbitfld.long 0x00 15. "RESERVED," "0,1" hexmask.long.word 0x00 4.--14. 1. "XSTEP,Horizontal offset in 128-bit words between 2D block columns" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1F4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_7,Offset between 2D blocks" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "YSTEP,Vertical offset in lines between rows of 2D blocks" newline rbitfld.long 0x00 15. "RESERVED," "0,1" hexmask.long.word 0x00 4.--14. 1. "XSTEP,Horizontal offset in 128-bit words between 2D block columns" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "DRM" base ad:0x54160000 group.long 0x280++0x03 line.long 0x00 "DRM_SUSPEND_CTRL32," hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4.--8. "SUSPEND_SEL,Suspend signal selection.Selects which suspend signal affects the peripheral" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 3. "SUSPEND_DEFAULT_OVERRIDE,Enable or disable the override value in SUSPEND_SEL.0: SUSPEND_SEL field will select which suspend signal reaches the peripheral.1: SUSPEND_SEL field ignored.Default suspend signal will reach the peripheral" "0,1" newline rbitfld.long 0x00 1.--2. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x00 0. "SENSCTRL,Sensitivity Control for suspend signals.When SUSPEND_DEFAULT_OVERRIDE=1 this bit is ignored and read as a 1" "Suspend signal will not reach the peripheral,Suspend signal will reach the peripheral" repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x240)++0x03 line.long 0x00 "DRM_SUSPEND_CTRL$1," hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4.--8. "SUSPEND_SEL,Suspend signal selection.Selects which suspend signal affects the peripheral" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 3. "SUSPEND_DEFAULT_OVERRIDE,Enable or disable the override value in SUSPEND_SEL.0: SUSPEND_SEL field will select which suspend signal reaches the peripheral.1: SUSPEND_SEL field ignored.Default suspend signal will reach the peripheral" "0,1" rbitfld.long 0x00 1.--2. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 0. "SENSCTRL,Sensitivity Control for suspend signals.When SUSPEND_DEFAULT_OVERRIDE=1 this bit is ignored and read as a 1" "Suspend signal will not reach the peripheral,Suspend signal will reach the peripheral" repeat.end repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x200)++0x03 line.long 0x00 "DRM_SUSPEND_CTRL$1," hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4.--8. "SUSPEND_SEL,Suspend signal selection.Selects which suspend signal affects the peripheral" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 3. "SUSPEND_DEFAULT_OVERRIDE,Enable or disable the override value in SUSPEND_SEL.0: SUSPEND_SEL field will select which suspend signal reaches the peripheral.1: SUSPEND_SEL field ignored.Default suspend signal will reach the peripheral" "0,1" rbitfld.long 0x00 1.--2. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 0. "SENSCTRL,Sensitivity Control for suspend signals.When SUSPEND_DEFAULT_OVERRIDE=1 this bit is ignored and read as a 1" "Suspend signal will not reach the peripheral,Suspend signal will reach the peripheral" repeat.end width 0x0B tree.end tree "DSP1_CM_CORE_AON" base ad:0x4A005400 group.long 0x00++0x0B line.long 0x00 "CM_DSP1_CLKSTCTRL,This register enables the DSP domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_DSP1_GFCLK,This field indicates the state of the DSP_ROOT_CLK clock in the domain" "CLKACTIVITY_DSP1_GFCLK_0,CLKACTIVITY_DSP1_GFCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_DSP1_STATICDEP,This register controls the static domain depedencies from DSP domain towards 'target' domains" rbitfld.long 0x04 31. "RESERVED," "0,1" bitfld.long 0x04 30. "CRC_STATDEP,Static dependency towards L3INIT clock domain" "CRC_STATDEP_0,CRC_STATDEP_1" newline bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE cLOCK dOMAIN" "PCIE_STATDEP_0,PCIE_STATDEP_1" bitfld.long 0x04 28. "ISS_STATDEP,Static dependency towards ISS Clock Domain" "ISS_STATDEP_0,ISS_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 Clock Domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 Clock Domain" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC Clock Domain" "GMAC_STATDEP_0,GMAC_STATDEP_1" bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPUClock Domain" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain" "IPU1_STATDEP_0,IPU1_STATDEP_1" bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 Clock Domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" newline bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 Clock Domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2CLOCK dOMAIN" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 CLOCK dOMAIN" "EVE1_STATDEP_0,EVE1_STATDEP_1" bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain" "CUSTEFUSE_STATDEP_0,?" rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC Clock Domain" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" rbitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,?" newline rbitfld.long 0x04 11. "RESERVED," "0,1" bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU Clock Domain" "GPU_STATDEP_0,GPU_STATDEP_1" newline bitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain" "CAM_STATDEP_0,CAM_STATDEP_1" bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" rbitfld.long 0x04 6. "RESERVED," "0,1" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 3. "RESERVED," "0,1" bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline rbitfld.long 0x04 1. "RESERVED," "0,1" bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_DSP1_DYNAMICDEP,This register controls the dynamic domain depedencies from DSP domain towards 'target' domains" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.tbyte 0x08 6.--23. 1. "RESERVED," rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20++0x03 line.long 0x00 "CM_DSP1_DSP1_CLKCTRL,This register manages the DSP clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "DSP1_EDMA_TPCC" base ad:0x40D10000 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x04 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x04 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" newline rbitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x04 22.--23. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x04 19. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x04 15. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x04 11. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7" group.long 0xFC++0x113 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" line.long 0x04 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x04 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x08 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x08 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x0C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x10 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x14 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x18 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x1C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" hexmask.long.tbyte 0x20 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x20 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" hexmask.long.tbyte 0x24 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x24 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" hexmask.long.tbyte 0x28 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x28 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x28 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x2C "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.tbyte 0x2C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x2C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x2C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" hexmask.long.tbyte 0x30 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x30 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x30 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" hexmask.long.tbyte 0x34 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x34 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x34 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x38 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" hexmask.long.tbyte 0x38 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x38 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x38 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x3C "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" hexmask.long.tbyte 0x3C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x3C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x3C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" hexmask.long.tbyte 0x40 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x40 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x40 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x44 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" hexmask.long.tbyte 0x44 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x44 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x44 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x48 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" hexmask.long.tbyte 0x48 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x48 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x48 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x4C "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" hexmask.long.tbyte 0x4C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x4C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" hexmask.long.tbyte 0x50 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x50 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x50 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x54 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" hexmask.long.tbyte 0x54 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x54 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x54 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x58 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" hexmask.long.tbyte 0x58 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x58 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x58 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x5C "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" hexmask.long.tbyte 0x5C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x5C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x5C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x60 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" hexmask.long.tbyte 0x60 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x60 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x60 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x64 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" hexmask.long.tbyte 0x64 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x64 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x64 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x68 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" hexmask.long.tbyte 0x68 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x68 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x68 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x6C "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" hexmask.long.tbyte 0x6C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x6C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x6C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x70 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" hexmask.long.tbyte 0x70 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x70 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x70 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x74 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" hexmask.long.tbyte 0x74 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x74 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x74 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x78 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" hexmask.long.tbyte 0x78 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x78 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x78 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x7C "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" hexmask.long.tbyte 0x7C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x7C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x7C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x80 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" hexmask.long.tbyte 0x80 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x80 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x80 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x84 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" hexmask.long.tbyte 0x84 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x84 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x84 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x88 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" hexmask.long.tbyte 0x88 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x88 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x88 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x8C "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" hexmask.long.tbyte 0x8C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x8C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x8C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x90 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" hexmask.long.tbyte 0x90 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x90 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x90 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x94 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" hexmask.long.tbyte 0x94 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x94 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x94 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x98 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" hexmask.long.tbyte 0x98 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x98 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x98 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x9C "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" hexmask.long.tbyte 0x9C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x9C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x9C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA0 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA4 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA8 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xAC "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" hexmask.long.tbyte 0xAC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xAC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xAC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB0 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB4 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB8 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xBC "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" hexmask.long.tbyte 0xBC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xBC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xBC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC0 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC4 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC8 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xCC "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" hexmask.long.tbyte 0xCC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xCC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xCC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD0 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD4 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD8 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xDC "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" hexmask.long.tbyte 0xDC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xDC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xDC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE0 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE4 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE8 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xEC "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" hexmask.long.tbyte 0xEC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xEC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xEC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF0 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF4 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF8 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xFC "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" hexmask.long.tbyte 0xFC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xFC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xFC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x100 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" hexmask.long.tbyte 0x100 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x100 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x100 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x104 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x104 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x104 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x104 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x104 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x108 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x108 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x108 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x108 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x108 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x10C "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x10C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10C 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x10C 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x10C 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x110 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x110 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x110 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x110 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x110 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x240++0x23 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x00 31. "RESERVED,Reserved" "0,1" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 27. "RESERVED,Reserved" "0,1" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 23. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Reserved" "0,1" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 15. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x04 31. "RESERVED,Reserved" "0,1" bitfld.long 0x04 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 27. "RESERVED,Reserved" "0,1" bitfld.long 0x04 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 23. "RESERVED,Reserved" "0,1" bitfld.long 0x04 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED,Reserved" "0,1" bitfld.long 0x04 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 15. "RESERVED,Reserved" "0,1" bitfld.long 0x04 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 11. "RESERVED,Reserved" "0,1" bitfld.long 0x04 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED,Reserved" "0,1" bitfld.long 0x04 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x08 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x08 31. "RESERVED,Reserved" "0,1" bitfld.long 0x08 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 27. "RESERVED,Reserved" "0,1" bitfld.long 0x08 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 23. "RESERVED,Reserved" "0,1" bitfld.long 0x08 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED,Reserved" "0,1" bitfld.long 0x08 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 15. "RESERVED,Reserved" "0,1" bitfld.long 0x08 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 11. "RESERVED,Reserved" "0,1" bitfld.long 0x08 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED,Reserved" "0,1" bitfld.long 0x08 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x0C "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x0C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x10 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x10 31. "RESERVED,Reserved" "0,1" bitfld.long 0x10 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED,Reserved" "0,1" bitfld.long 0x10 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED,Reserved" "0,1" bitfld.long 0x10 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "RESERVED,Reserved" "0,1" bitfld.long 0x10 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 15. "RESERVED,Reserved" "0,1" bitfld.long 0x10 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 11. "RESERVED,Reserved" "0,1" bitfld.long 0x10 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" bitfld.long 0x10 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 3. "RESERVED,Reserved" "0,1" bitfld.long 0x10 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x14 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x14 31. "RESERVED,Reserved" "0,1" bitfld.long 0x14 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED,Reserved" "0,1" bitfld.long 0x14 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED,Reserved" "0,1" bitfld.long 0x14 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED,Reserved" "0,1" bitfld.long 0x14 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED,Reserved" "0,1" bitfld.long 0x14 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" bitfld.long 0x14 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED,Reserved" "0,1" bitfld.long 0x14 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x18 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x18 31. "RESERVED,Reserved" "0,1" bitfld.long 0x18 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED,Reserved" "0,1" bitfld.long 0x18 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED,Reserved" "0,1" bitfld.long 0x18 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED,Reserved" "0,1" bitfld.long 0x18 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED,Reserved" "0,1" bitfld.long 0x18 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED,Reserved" "0,1" bitfld.long 0x18 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED,Reserved" "0,1" bitfld.long 0x18 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED,Reserved" "0,1" bitfld.long 0x18 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x1C "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x1C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x20 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" rbitfld.long 0x20 31. "RESERVED," "0,1" bitfld.long 0x20 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 27. "RESERVED," "0,1" bitfld.long 0x20 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 23. "RESERVED," "0,1" bitfld.long 0x20 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 19. "RESERVED," "0,1" bitfld.long 0x20 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 15. "RESERVED," "0,1" bitfld.long 0x20 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 11. "RESERVED," "0,1" bitfld.long 0x20 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 7. "RESERVED," "0,1" bitfld.long 0x20 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 3. "RESERVED," "0,1" bitfld.long 0x20 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x280++0x07 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_QUEPRI,Queue Priority" hexmask.long 0x04 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" rgroup.long 0x300++0x23 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" newline bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" newline bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" newline bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" newline bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" newline bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" newline bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" newline bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" newline bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" newline bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" newline bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" newline bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" newline bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" newline bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" newline bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" newline bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" newline bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" newline bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" newline bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" newline bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" newline bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" line.long 0x08 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1" newline bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1" bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1" newline bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1" newline bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1" bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1" newline bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1" newline bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1" bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1" newline bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1" newline bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1" bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1" newline bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1" newline bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1" bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1" newline bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1" line.long 0x0C "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1" bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1" bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1" bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1" bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1" bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1" line.long 0x10 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,Event Missed #7" "0,1" newline bitfld.long 0x10 6. "E6,Event Missed #6" "0,1" bitfld.long 0x10 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x10 4. "E4,Event Missed #4" "0,1" bitfld.long 0x10 3. "E3,Event Missed #3" "0,1" newline bitfld.long 0x10 2. "E2,Event Missed #2" "0,1" bitfld.long 0x10 1. "E1,Event Missed #1" "0,1" newline bitfld.long 0x10 0. "E0,Event Missed #0" "0,1" line.long 0x14 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1" newline bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1" newline bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1" bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1" newline bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1" line.long 0x18 "EDMA_TPCC_CCERR,CC Error Register" hexmask.long.word 0x18 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 16. "TCERR,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register" "TCERR_0,TCERR_1" newline hexmask.long.byte 0x18 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD7_0,QTHRXCD7_1" newline bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD6_0,QTHRXCD6_1" bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD5_0,QTHRXCD5_1" newline bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD4_0,QTHRXCD4_1" bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD3_0,QTHRXCD3_1" newline bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD1_0,QTHRXCD1_1" newline bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x1C "EDMA_TPCC_CCERRCLR,CC Error Clear Register" hexmask.long.word 0x1C 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR" "0,1" newline hexmask.long.byte 0x1C 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect" "0,1" bitfld.long 0x1C 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect" "0,1" bitfld.long 0x1C 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" newline bitfld.long 0x1C 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect" "0,1" bitfld.long 0x1C 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" newline bitfld.long 0x1C 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect" "0,1" line.long 0x20 "EDMA_TPCC_EEVAL,Error Eval Register" hexmask.long 0x20 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 1. "SET,Error Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x20 0. "EVAL,Error Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x348++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x350++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x358++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x360++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x368++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x370++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x378++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x344++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x34C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x354++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x35C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x364++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x36C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x374++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x37C++0x23 line.long 0x00 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" line.long 0x04 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x04 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x04 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x04 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x04 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x04 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x04 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x04 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x08 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x08 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x08 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x08 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x08 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x08 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x08 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x08 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x0C "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x0C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x0C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x0C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x0C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x0C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x0C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x0C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x10 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x10 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x10 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x10 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x10 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x10 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x10 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x10 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x14 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x14 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x14 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x14 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x14 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x14 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x14 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x14 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x18 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x18 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x18 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x18 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x18 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x18 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x18 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x18 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x1C "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x1C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x1C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x1C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x1C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x1C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x1C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x1C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x20 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x20 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x20 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x20 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x20 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x20 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x20 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x20 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" rgroup.long 0x400++0x7F line.long 0x00 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x04 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x08 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x10 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x14 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x18 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x1C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x20 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x24 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x28 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x2C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x30 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x30 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x30 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x34 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x34 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x38 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x38 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x3C "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x3C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x40 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x40 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x44 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x44 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x44 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x48 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x48 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x48 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x4C "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x4C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x4C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x50 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x50 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x50 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x54 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x54 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x54 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x54 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x58 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x58 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x58 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x58 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x5C "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x5C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x5C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x5C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x60 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x60 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x60 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x60 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x64 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x64 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x64 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x64 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x68 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x68 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x68 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x68 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x6C "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x6C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x6C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x6C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x70 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x70 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x70 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x70 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x74 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x74 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x74 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x74 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x78 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x78 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x78 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x78 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x7C "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x7C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x7C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x7C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x600++0x07 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" line.long 0x04 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" hexmask.long.byte 0x04 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" rbitfld.long 0x00 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" rbitfld.long 0x04 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,reads return 0's" rbitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" newline rbitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" rbitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" newline rbitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" rbitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" newline bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2" rbitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" newline rbitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 14.--15. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" rbitfld.long 0x00 5.--7. "RESERVED,reads return 0's" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" rbitfld.long 0x00 3. "RESERVED,reads return 0's" "0,1" newline bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.." rbitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" newline rbitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" group.long 0x700++0x0B line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" hexmask.long.tbyte 0x00 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" line.long 0x08 "EDMA_TPCC_AETCMD,AET Command" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "CLR,AET Clear commandCPU writes 0x0 has no effect" "0,1" rgroup.long 0x800++0x2F line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" line.long 0x04 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" newline rbitfld.long 0x04 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" rbitfld.long 0x04 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" newline rbitfld.long 0x04 2. "URE,User Read Error" "URE_0,URE_1" rbitfld.long 0x04 1. "UWE,User Write Error" "UWE_0,UWE_1" newline rbitfld.long 0x04 0. "UXE,User Execute Error" "UXE_0,UXE_1" line.long 0x08 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" line.long 0x0C "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x0C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x0C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x0C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x0C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x0C 10. "AID0,Allowed ID 0" "AID0_0,AID0_1" bitfld.long 0x0C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x0C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x0C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x0C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x0C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x0C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x0C 0. "UX,User Execute permission" "UX_0,UX_1" line.long 0x10 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x10 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x10 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x10 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x10 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x10 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x10 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x10 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x10 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x10 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x10 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x10 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x10 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x10 0. "UX,User Execute permission" "UX_0,?" line.long 0x14 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x14 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x14 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x14 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x14 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x14 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x14 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x14 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x14 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x14 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x14 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x14 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x14 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x14 0. "UX,User Execute permission" "UX_0,?" line.long 0x18 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x18 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x18 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x18 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x18 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x18 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x18 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x18 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x18 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x18 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x18 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x18 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x18 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x18 0. "UX,User Execute permission" "UX_0,?" line.long 0x1C "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x1C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x1C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x1C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x1C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x1C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x1C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x1C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x1C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x1C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x1C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x1C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x1C 0. "UX,User Execute permission" "UX_0,?" line.long 0x20 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x20 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x20 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x20 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x20 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x20 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x20 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x20 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x20 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x20 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x20 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x20 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x20 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x20 0. "UX,User Execute permission" "UX_0,?" line.long 0x24 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x24 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x24 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x24 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x24 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x24 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x24 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x24 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x24 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x24 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x24 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x24 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x24 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x24 0. "UX,User Execute permission" "UX_0,?" line.long 0x28 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" hexmask.long.word 0x28 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x28 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x28 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x28 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x28 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x28 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x28 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x28 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x28 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x28 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x28 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x28 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x28 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x28 0. "UX,User Execute permission" "UX_0,?" line.long 0x2C "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" hexmask.long.word 0x2C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x2C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x2C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x2C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x2C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x2C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x2C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x2C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x2C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x2C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x2C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x2C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x2C 0. "UX,User Execute permission" "UX_0,?" rgroup.long 0x1000++0x47 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" newline bitfld.long 0x04 29. "E61,Event #61" "0,1" bitfld.long 0x04 28. "E60,Event #60" "0,1" newline bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" newline bitfld.long 0x04 23. "E55,Event #55" "0,1" bitfld.long 0x04 22. "E54,Event #54" "0,1" newline bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" newline bitfld.long 0x04 17. "E49,Event #49" "0,1" bitfld.long 0x04 16. "E48,Event #48" "0,1" newline bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" newline bitfld.long 0x04 11. "E43,Event #43" "0,1" bitfld.long 0x04 10. "E42,Event #42" "0,1" newline bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" newline bitfld.long 0x04 5. "E37,Event #37" "0,1" bitfld.long 0x04 4. "E36,Event #36" "0,1" newline bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" line.long 0x08 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event #31" "0,1" bitfld.long 0x08 30. "E30,Event #30" "0,1" newline bitfld.long 0x08 29. "E29,Event #29" "0,1" bitfld.long 0x08 28. "E28,Event #28" "0,1" newline bitfld.long 0x08 27. "E27,Event #27" "0,1" bitfld.long 0x08 26. "E26,Event #26" "0,1" newline bitfld.long 0x08 25. "E25,Event #25" "0,1" bitfld.long 0x08 24. "E24,Event #24" "0,1" newline bitfld.long 0x08 23. "E23,Event #23" "0,1" bitfld.long 0x08 22. "E22,Event #22" "0,1" newline bitfld.long 0x08 21. "E21,Event #21" "0,1" bitfld.long 0x08 20. "E20,Event #20" "0,1" newline bitfld.long 0x08 19. "E19,Event #19" "0,1" bitfld.long 0x08 18. "E18,Event #18" "0,1" newline bitfld.long 0x08 17. "E17,Event #17" "0,1" bitfld.long 0x08 16. "E16,Event #16" "0,1" newline bitfld.long 0x08 15. "E15,Event #15" "0,1" bitfld.long 0x08 14. "E14,Event #14" "0,1" newline bitfld.long 0x08 13. "E13,Event #13" "0,1" bitfld.long 0x08 12. "E12,Event #12" "0,1" newline bitfld.long 0x08 11. "E11,Event #11" "0,1" bitfld.long 0x08 10. "E10,Event #10" "0,1" newline bitfld.long 0x08 9. "E9,Event #9" "0,1" bitfld.long 0x08 8. "E8,Event #8" "0,1" newline bitfld.long 0x08 7. "E7,Event #7" "0,1" bitfld.long 0x08 6. "E6,Event #6" "0,1" newline bitfld.long 0x08 5. "E5,Event #5" "0,1" bitfld.long 0x08 4. "E4,Event #4" "0,1" newline bitfld.long 0x08 3. "E3,Event #3" "0,1" bitfld.long 0x08 2. "E2,Event #2" "0,1" newline bitfld.long 0x08 1. "E1,Event #1" "0,1" bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event #63" "0,1" bitfld.long 0x0C 30. "E62,Event #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event #61" "0,1" bitfld.long 0x0C 28. "E60,Event #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event #59" "0,1" bitfld.long 0x0C 26. "E58,Event #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event #57" "0,1" bitfld.long 0x0C 24. "E56,Event #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event #55" "0,1" bitfld.long 0x0C 22. "E54,Event #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event #53" "0,1" bitfld.long 0x0C 20. "E52,Event #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event #51" "0,1" bitfld.long 0x0C 18. "E50,Event #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event #49" "0,1" bitfld.long 0x0C 16. "E48,Event #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event #47" "0,1" bitfld.long 0x0C 14. "E46,Event #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event #45" "0,1" bitfld.long 0x0C 12. "E44,Event #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event #43" "0,1" bitfld.long 0x0C 10. "E42,Event #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event #41" "0,1" bitfld.long 0x0C 8. "E40,Event #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event #39" "0,1" bitfld.long 0x0C 6. "E38,Event #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event #37" "0,1" bitfld.long 0x0C 4. "E36,Event #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event #35" "0,1" bitfld.long 0x0C 2. "E34,Event #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event #33" "0,1" bitfld.long 0x0C 0. "E32,Event #32" "0,1" line.long 0x10 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x10 31. "E31,Event #31" "0,1" bitfld.long 0x10 30. "E30,Event #30" "0,1" newline bitfld.long 0x10 29. "E29,Event #29" "0,1" bitfld.long 0x10 28. "E28,Event #28" "0,1" newline bitfld.long 0x10 27. "E27,Event #27" "0,1" bitfld.long 0x10 26. "E26,Event #26" "0,1" newline bitfld.long 0x10 25. "E25,Event #25" "0,1" bitfld.long 0x10 24. "E24,Event #24" "0,1" newline bitfld.long 0x10 23. "E23,Event #23" "0,1" bitfld.long 0x10 22. "E22,Event #22" "0,1" newline bitfld.long 0x10 21. "E21,Event #21" "0,1" bitfld.long 0x10 20. "E20,Event #20" "0,1" newline bitfld.long 0x10 19. "E19,Event #19" "0,1" bitfld.long 0x10 18. "E18,Event #18" "0,1" newline bitfld.long 0x10 17. "E17,Event #17" "0,1" bitfld.long 0x10 16. "E16,Event #16" "0,1" newline bitfld.long 0x10 15. "E15,Event #15" "0,1" bitfld.long 0x10 14. "E14,Event #14" "0,1" newline bitfld.long 0x10 13. "E13,Event #13" "0,1" bitfld.long 0x10 12. "E12,Event #12" "0,1" newline bitfld.long 0x10 11. "E11,Event #11" "0,1" bitfld.long 0x10 10. "E10,Event #10" "0,1" newline bitfld.long 0x10 9. "E9,Event #9" "0,1" bitfld.long 0x10 8. "E8,Event #8" "0,1" newline bitfld.long 0x10 7. "E7,Event #7" "0,1" bitfld.long 0x10 6. "E6,Event #6" "0,1" newline bitfld.long 0x10 5. "E5,Event #5" "0,1" bitfld.long 0x10 4. "E4,Event #4" "0,1" newline bitfld.long 0x10 3. "E3,Event #3" "0,1" bitfld.long 0x10 2. "E2,Event #2" "0,1" newline bitfld.long 0x10 1. "E1,Event #1" "0,1" bitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x14 31. "E63,Event #63" "0,1" bitfld.long 0x14 30. "E62,Event #62" "0,1" newline bitfld.long 0x14 29. "E61,Event #61" "0,1" bitfld.long 0x14 28. "E60,Event #60" "0,1" newline bitfld.long 0x14 27. "E59,Event #59" "0,1" bitfld.long 0x14 26. "E58,Event #58" "0,1" newline bitfld.long 0x14 25. "E57,Event #57" "0,1" bitfld.long 0x14 24. "E56,Event #56" "0,1" newline bitfld.long 0x14 23. "E55,Event #55" "0,1" bitfld.long 0x14 22. "E54,Event #54" "0,1" newline bitfld.long 0x14 21. "E53,Event #53" "0,1" bitfld.long 0x14 20. "E52,Event #52" "0,1" newline bitfld.long 0x14 19. "E51,Event #51" "0,1" bitfld.long 0x14 18. "E50,Event #50" "0,1" newline bitfld.long 0x14 17. "E49,Event #49" "0,1" bitfld.long 0x14 16. "E48,Event #48" "0,1" newline bitfld.long 0x14 15. "E47,Event #47" "0,1" bitfld.long 0x14 14. "E46,Event #46" "0,1" newline bitfld.long 0x14 13. "E45,Event #45" "0,1" bitfld.long 0x14 12. "E44,Event #44" "0,1" newline bitfld.long 0x14 11. "E43,Event #43" "0,1" bitfld.long 0x14 10. "E42,Event #42" "0,1" newline bitfld.long 0x14 9. "E41,Event #41" "0,1" bitfld.long 0x14 8. "E40,Event #40" "0,1" newline bitfld.long 0x14 7. "E39,Event #39" "0,1" bitfld.long 0x14 6. "E38,Event #38" "0,1" newline bitfld.long 0x14 5. "E37,Event #37" "0,1" bitfld.long 0x14 4. "E36,Event #36" "0,1" newline bitfld.long 0x14 3. "E35,Event #35" "0,1" bitfld.long 0x14 2. "E34,Event #34" "0,1" newline bitfld.long 0x14 1. "E33,Event #33" "0,1" bitfld.long 0x14 0. "E32,Event #32" "0,1" line.long 0x18 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x18 31. "E31,Event #31" "0,1" bitfld.long 0x18 30. "E30,Event #30" "0,1" newline bitfld.long 0x18 29. "E29,Event #29" "0,1" bitfld.long 0x18 28. "E28,Event #28" "0,1" newline bitfld.long 0x18 27. "E27,Event #27" "0,1" bitfld.long 0x18 26. "E26,Event #26" "0,1" newline bitfld.long 0x18 25. "E25,Event #25" "0,1" bitfld.long 0x18 24. "E24,Event #24" "0,1" newline bitfld.long 0x18 23. "E23,Event #23" "0,1" bitfld.long 0x18 22. "E22,Event #22" "0,1" newline bitfld.long 0x18 21. "E21,Event #21" "0,1" bitfld.long 0x18 20. "E20,Event #20" "0,1" newline bitfld.long 0x18 19. "E19,Event #19" "0,1" bitfld.long 0x18 18. "E18,Event #18" "0,1" newline bitfld.long 0x18 17. "E17,Event #17" "0,1" bitfld.long 0x18 16. "E16,Event #16" "0,1" newline bitfld.long 0x18 15. "E15,Event #15" "0,1" bitfld.long 0x18 14. "E14,Event #14" "0,1" newline bitfld.long 0x18 13. "E13,Event #13" "0,1" bitfld.long 0x18 12. "E12,Event #12" "0,1" newline bitfld.long 0x18 11. "E11,Event #11" "0,1" bitfld.long 0x18 10. "E10,Event #10" "0,1" newline bitfld.long 0x18 9. "E9,Event #9" "0,1" bitfld.long 0x18 8. "E8,Event #8" "0,1" newline bitfld.long 0x18 7. "E7,Event #7" "0,1" bitfld.long 0x18 6. "E6,Event #6" "0,1" newline bitfld.long 0x18 5. "E5,Event #5" "0,1" bitfld.long 0x18 4. "E4,Event #4" "0,1" newline bitfld.long 0x18 3. "E3,Event #3" "0,1" bitfld.long 0x18 2. "E2,Event #2" "0,1" newline bitfld.long 0x18 1. "E1,Event #1" "0,1" bitfld.long 0x18 0. "E0,Event #0" "0,1" line.long 0x1C "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x1C 31. "E63,Event #63" "0,1" bitfld.long 0x1C 30. "E62,Event #62" "0,1" newline bitfld.long 0x1C 29. "E61,Event #61" "0,1" bitfld.long 0x1C 28. "E60,Event #60" "0,1" newline bitfld.long 0x1C 27. "E59,Event #59" "0,1" bitfld.long 0x1C 26. "E58,Event #58" "0,1" newline bitfld.long 0x1C 25. "E57,Event #57" "0,1" bitfld.long 0x1C 24. "E56,Event #56" "0,1" newline bitfld.long 0x1C 23. "E55,Event #55" "0,1" bitfld.long 0x1C 22. "E54,Event #54" "0,1" newline bitfld.long 0x1C 21. "E53,Event #53" "0,1" bitfld.long 0x1C 20. "E52,Event #52" "0,1" newline bitfld.long 0x1C 19. "E51,Event #51" "0,1" bitfld.long 0x1C 18. "E50,Event #50" "0,1" newline bitfld.long 0x1C 17. "E49,Event #49" "0,1" bitfld.long 0x1C 16. "E48,Event #48" "0,1" newline bitfld.long 0x1C 15. "E47,Event #47" "0,1" bitfld.long 0x1C 14. "E46,Event #46" "0,1" newline bitfld.long 0x1C 13. "E45,Event #45" "0,1" bitfld.long 0x1C 12. "E44,Event #44" "0,1" newline bitfld.long 0x1C 11. "E43,Event #43" "0,1" bitfld.long 0x1C 10. "E42,Event #42" "0,1" newline bitfld.long 0x1C 9. "E41,Event #41" "0,1" bitfld.long 0x1C 8. "E40,Event #40" "0,1" newline bitfld.long 0x1C 7. "E39,Event #39" "0,1" bitfld.long 0x1C 6. "E38,Event #38" "0,1" newline bitfld.long 0x1C 5. "E37,Event #37" "0,1" bitfld.long 0x1C 4. "E36,Event #36" "0,1" newline bitfld.long 0x1C 3. "E35,Event #35" "0,1" bitfld.long 0x1C 2. "E34,Event #34" "0,1" newline bitfld.long 0x1C 1. "E33,Event #33" "0,1" bitfld.long 0x1C 0. "E32,Event #32" "0,1" line.long 0x20 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x20 31. "E31,Event #31" "0,1" bitfld.long 0x20 30. "E30,Event #30" "0,1" newline bitfld.long 0x20 29. "E29,Event #29" "0,1" bitfld.long 0x20 28. "E28,Event #28" "0,1" newline bitfld.long 0x20 27. "E27,Event #27" "0,1" bitfld.long 0x20 26. "E26,Event #26" "0,1" newline bitfld.long 0x20 25. "E25,Event #25" "0,1" bitfld.long 0x20 24. "E24,Event #24" "0,1" newline bitfld.long 0x20 23. "E23,Event #23" "0,1" bitfld.long 0x20 22. "E22,Event #22" "0,1" newline bitfld.long 0x20 21. "E21,Event #21" "0,1" bitfld.long 0x20 20. "E20,Event #20" "0,1" newline bitfld.long 0x20 19. "E19,Event #19" "0,1" bitfld.long 0x20 18. "E18,Event #18" "0,1" newline bitfld.long 0x20 17. "E17,Event #17" "0,1" bitfld.long 0x20 16. "E16,Event #16" "0,1" newline bitfld.long 0x20 15. "E15,Event #15" "0,1" bitfld.long 0x20 14. "E14,Event #14" "0,1" newline bitfld.long 0x20 13. "E13,Event #13" "0,1" bitfld.long 0x20 12. "E12,Event #12" "0,1" newline bitfld.long 0x20 11. "E11,Event #11" "0,1" bitfld.long 0x20 10. "E10,Event #10" "0,1" newline bitfld.long 0x20 9. "E9,Event #9" "0,1" bitfld.long 0x20 8. "E8,Event #8" "0,1" newline bitfld.long 0x20 7. "E7,Event #7" "0,1" bitfld.long 0x20 6. "E6,Event #6" "0,1" newline bitfld.long 0x20 5. "E5,Event #5" "0,1" bitfld.long 0x20 4. "E4,Event #4" "0,1" newline bitfld.long 0x20 3. "E3,Event #3" "0,1" bitfld.long 0x20 2. "E2,Event #2" "0,1" newline bitfld.long 0x20 1. "E1,Event #1" "0,1" bitfld.long 0x20 0. "E0,Event #0" "0,1" line.long 0x24 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x24 31. "E63,Event #63" "0,1" bitfld.long 0x24 30. "E62,Event #62" "0,1" newline bitfld.long 0x24 29. "E61,Event #61" "0,1" bitfld.long 0x24 28. "E60,Event #60" "0,1" newline bitfld.long 0x24 27. "E59,Event #59" "0,1" bitfld.long 0x24 26. "E58,Event #58" "0,1" newline bitfld.long 0x24 25. "E57,Event #57" "0,1" bitfld.long 0x24 24. "E56,Event #56" "0,1" newline bitfld.long 0x24 23. "E55,Event #55" "0,1" bitfld.long 0x24 22. "E54,Event #54" "0,1" newline bitfld.long 0x24 21. "E53,Event #53" "0,1" bitfld.long 0x24 20. "E52,Event #52" "0,1" newline bitfld.long 0x24 19. "E51,Event #51" "0,1" bitfld.long 0x24 18. "E50,Event #50" "0,1" newline bitfld.long 0x24 17. "E49,Event #49" "0,1" bitfld.long 0x24 16. "E48,Event #48" "0,1" newline bitfld.long 0x24 15. "E47,Event #47" "0,1" bitfld.long 0x24 14. "E46,Event #46" "0,1" newline bitfld.long 0x24 13. "E45,Event #45" "0,1" bitfld.long 0x24 12. "E44,Event #44" "0,1" newline bitfld.long 0x24 11. "E43,Event #43" "0,1" bitfld.long 0x24 10. "E42,Event #42" "0,1" newline bitfld.long 0x24 9. "E41,Event #41" "0,1" bitfld.long 0x24 8. "E40,Event #40" "0,1" newline bitfld.long 0x24 7. "E39,Event #39" "0,1" bitfld.long 0x24 6. "E38,Event #38" "0,1" newline bitfld.long 0x24 5. "E37,Event #37" "0,1" bitfld.long 0x24 4. "E36,Event #36" "0,1" newline bitfld.long 0x24 3. "E35,Event #35" "0,1" bitfld.long 0x24 2. "E34,Event #34" "0,1" newline bitfld.long 0x24 1. "E33,Event #33" "0,1" bitfld.long 0x24 0. "E32,Event #32" "0,1" line.long 0x28 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x28 31. "E31,Event #31" "0,1" bitfld.long 0x28 30. "E30,Event #30" "0,1" newline bitfld.long 0x28 29. "E29,Event #29" "0,1" bitfld.long 0x28 28. "E28,Event #28" "0,1" newline bitfld.long 0x28 27. "E27,Event #27" "0,1" bitfld.long 0x28 26. "E26,Event #26" "0,1" newline bitfld.long 0x28 25. "E25,Event #25" "0,1" bitfld.long 0x28 24. "E24,Event #24" "0,1" newline bitfld.long 0x28 23. "E23,Event #23" "0,1" bitfld.long 0x28 22. "E22,Event #22" "0,1" newline bitfld.long 0x28 21. "E21,Event #21" "0,1" bitfld.long 0x28 20. "E20,Event #20" "0,1" newline bitfld.long 0x28 19. "E19,Event #19" "0,1" bitfld.long 0x28 18. "E18,Event #18" "0,1" newline bitfld.long 0x28 17. "E17,Event #17" "0,1" bitfld.long 0x28 16. "E16,Event #16" "0,1" newline bitfld.long 0x28 15. "E15,Event #15" "0,1" bitfld.long 0x28 14. "E14,Event #14" "0,1" newline bitfld.long 0x28 13. "E13,Event #13" "0,1" bitfld.long 0x28 12. "E12,Event #12" "0,1" newline bitfld.long 0x28 11. "E11,Event #11" "0,1" bitfld.long 0x28 10. "E10,Event #10" "0,1" newline bitfld.long 0x28 9. "E9,Event #9" "0,1" bitfld.long 0x28 8. "E8,Event #8" "0,1" newline bitfld.long 0x28 7. "E7,Event #7" "0,1" bitfld.long 0x28 6. "E6,Event #6" "0,1" newline bitfld.long 0x28 5. "E5,Event #5" "0,1" bitfld.long 0x28 4. "E4,Event #4" "0,1" newline bitfld.long 0x28 3. "E3,Event #3" "0,1" bitfld.long 0x28 2. "E2,Event #2" "0,1" newline bitfld.long 0x28 1. "E1,Event #1" "0,1" bitfld.long 0x28 0. "E0,Event #0" "0,1" line.long 0x2C "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x2C 31. "E63,Event #63" "0,1" bitfld.long 0x2C 30. "E62,Event #62" "0,1" newline bitfld.long 0x2C 29. "E61,Event #61" "0,1" bitfld.long 0x2C 28. "E60,Event #60" "0,1" newline bitfld.long 0x2C 27. "E59,Event #59" "0,1" bitfld.long 0x2C 26. "E58,Event #58" "0,1" newline bitfld.long 0x2C 25. "E57,Event #57" "0,1" bitfld.long 0x2C 24. "E56,Event #56" "0,1" newline bitfld.long 0x2C 23. "E55,Event #55" "0,1" bitfld.long 0x2C 22. "E54,Event #54" "0,1" newline bitfld.long 0x2C 21. "E53,Event #53" "0,1" bitfld.long 0x2C 20. "E52,Event #52" "0,1" newline bitfld.long 0x2C 19. "E51,Event #51" "0,1" bitfld.long 0x2C 18. "E50,Event #50" "0,1" newline bitfld.long 0x2C 17. "E49,Event #49" "0,1" bitfld.long 0x2C 16. "E48,Event #48" "0,1" newline bitfld.long 0x2C 15. "E47,Event #47" "0,1" bitfld.long 0x2C 14. "E46,Event #46" "0,1" newline bitfld.long 0x2C 13. "E45,Event #45" "0,1" bitfld.long 0x2C 12. "E44,Event #44" "0,1" newline bitfld.long 0x2C 11. "E43,Event #43" "0,1" bitfld.long 0x2C 10. "E42,Event #42" "0,1" newline bitfld.long 0x2C 9. "E41,Event #41" "0,1" bitfld.long 0x2C 8. "E40,Event #40" "0,1" newline bitfld.long 0x2C 7. "E39,Event #39" "0,1" bitfld.long 0x2C 6. "E38,Event #38" "0,1" newline bitfld.long 0x2C 5. "E37,Event #37" "0,1" bitfld.long 0x2C 4. "E36,Event #36" "0,1" newline bitfld.long 0x2C 3. "E35,Event #35" "0,1" bitfld.long 0x2C 2. "E34,Event #34" "0,1" newline bitfld.long 0x2C 1. "E33,Event #33" "0,1" bitfld.long 0x2C 0. "E32,Event #32" "0,1" line.long 0x30 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x30 31. "E31,Event #31" "0,1" bitfld.long 0x30 30. "E30,Event #30" "0,1" newline bitfld.long 0x30 29. "E29,Event #29" "0,1" bitfld.long 0x30 28. "E28,Event #28" "0,1" newline bitfld.long 0x30 27. "E27,Event #27" "0,1" bitfld.long 0x30 26. "E26,Event #26" "0,1" newline bitfld.long 0x30 25. "E25,Event #25" "0,1" bitfld.long 0x30 24. "E24,Event #24" "0,1" newline bitfld.long 0x30 23. "E23,Event #23" "0,1" bitfld.long 0x30 22. "E22,Event #22" "0,1" newline bitfld.long 0x30 21. "E21,Event #21" "0,1" bitfld.long 0x30 20. "E20,Event #20" "0,1" newline bitfld.long 0x30 19. "E19,Event #19" "0,1" bitfld.long 0x30 18. "E18,Event #18" "0,1" newline bitfld.long 0x30 17. "E17,Event #17" "0,1" bitfld.long 0x30 16. "E16,Event #16" "0,1" newline bitfld.long 0x30 15. "E15,Event #15" "0,1" bitfld.long 0x30 14. "E14,Event #14" "0,1" newline bitfld.long 0x30 13. "E13,Event #13" "0,1" bitfld.long 0x30 12. "E12,Event #12" "0,1" newline bitfld.long 0x30 11. "E11,Event #11" "0,1" bitfld.long 0x30 10. "E10,Event #10" "0,1" newline bitfld.long 0x30 9. "E9,Event #9" "0,1" bitfld.long 0x30 8. "E8,Event #8" "0,1" newline bitfld.long 0x30 7. "E7,Event #7" "0,1" bitfld.long 0x30 6. "E6,Event #6" "0,1" newline bitfld.long 0x30 5. "E5,Event #5" "0,1" bitfld.long 0x30 4. "E4,Event #4" "0,1" newline bitfld.long 0x30 3. "E3,Event #3" "0,1" bitfld.long 0x30 2. "E2,Event #2" "0,1" newline bitfld.long 0x30 1. "E1,Event #1" "0,1" bitfld.long 0x30 0. "E0,Event #0" "0,1" line.long 0x34 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x34 31. "E63,Event #63" "0,1" bitfld.long 0x34 30. "E62,Event #62" "0,1" newline bitfld.long 0x34 29. "E61,Event #61" "0,1" bitfld.long 0x34 28. "E60,Event #60" "0,1" newline bitfld.long 0x34 27. "E59,Event #59" "0,1" bitfld.long 0x34 26. "E58,Event #58" "0,1" newline bitfld.long 0x34 25. "E57,Event #57" "0,1" bitfld.long 0x34 24. "E56,Event #56" "0,1" newline bitfld.long 0x34 23. "E55,Event #55" "0,1" bitfld.long 0x34 22. "E54,Event #54" "0,1" newline bitfld.long 0x34 21. "E53,Event #53" "0,1" bitfld.long 0x34 20. "E52,Event #52" "0,1" newline bitfld.long 0x34 19. "E51,Event #51" "0,1" bitfld.long 0x34 18. "E50,Event #50" "0,1" newline bitfld.long 0x34 17. "E49,Event #49" "0,1" bitfld.long 0x34 16. "E48,Event #48" "0,1" newline bitfld.long 0x34 15. "E47,Event #47" "0,1" bitfld.long 0x34 14. "E46,Event #46" "0,1" newline bitfld.long 0x34 13. "E45,Event #45" "0,1" bitfld.long 0x34 12. "E44,Event #44" "0,1" newline bitfld.long 0x34 11. "E43,Event #43" "0,1" bitfld.long 0x34 10. "E42,Event #42" "0,1" newline bitfld.long 0x34 9. "E41,Event #41" "0,1" bitfld.long 0x34 8. "E40,Event #40" "0,1" newline bitfld.long 0x34 7. "E39,Event #39" "0,1" bitfld.long 0x34 6. "E38,Event #38" "0,1" newline bitfld.long 0x34 5. "E37,Event #37" "0,1" bitfld.long 0x34 4. "E36,Event #36" "0,1" newline bitfld.long 0x34 3. "E35,Event #35" "0,1" bitfld.long 0x34 2. "E34,Event #34" "0,1" newline bitfld.long 0x34 1. "E33,Event #33" "0,1" bitfld.long 0x34 0. "E32,Event #32" "0,1" line.long 0x38 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x38 31. "E31,Event #31" "0,1" bitfld.long 0x38 30. "E30,Event #30" "0,1" newline bitfld.long 0x38 29. "E29,Event #29" "0,1" bitfld.long 0x38 28. "E28,Event #28" "0,1" newline bitfld.long 0x38 27. "E27,Event #27" "0,1" bitfld.long 0x38 26. "E26,Event #26" "0,1" newline bitfld.long 0x38 25. "E25,Event #25" "0,1" bitfld.long 0x38 24. "E24,Event #24" "0,1" newline bitfld.long 0x38 23. "E23,Event #23" "0,1" bitfld.long 0x38 22. "E22,Event #22" "0,1" newline bitfld.long 0x38 21. "E21,Event #21" "0,1" bitfld.long 0x38 20. "E20,Event #20" "0,1" newline bitfld.long 0x38 19. "E19,Event #19" "0,1" bitfld.long 0x38 18. "E18,Event #18" "0,1" newline bitfld.long 0x38 17. "E17,Event #17" "0,1" bitfld.long 0x38 16. "E16,Event #16" "0,1" newline bitfld.long 0x38 15. "E15,Event #15" "0,1" bitfld.long 0x38 14. "E14,Event #14" "0,1" newline bitfld.long 0x38 13. "E13,Event #13" "0,1" bitfld.long 0x38 12. "E12,Event #12" "0,1" newline bitfld.long 0x38 11. "E11,Event #11" "0,1" bitfld.long 0x38 10. "E10,Event #10" "0,1" newline bitfld.long 0x38 9. "E9,Event #9" "0,1" bitfld.long 0x38 8. "E8,Event #8" "0,1" newline bitfld.long 0x38 7. "E7,Event #7" "0,1" bitfld.long 0x38 6. "E6,Event #6" "0,1" newline bitfld.long 0x38 5. "E5,Event #5" "0,1" bitfld.long 0x38 4. "E4,Event #4" "0,1" newline bitfld.long 0x38 3. "E3,Event #3" "0,1" bitfld.long 0x38 2. "E2,Event #2" "0,1" newline bitfld.long 0x38 1. "E1,Event #1" "0,1" bitfld.long 0x38 0. "E0,Event #0" "0,1" line.long 0x3C "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x3C 31. "E63,Event #63" "0,1" bitfld.long 0x3C 30. "E62,Event #62" "0,1" newline bitfld.long 0x3C 29. "E61,Event #61" "0,1" bitfld.long 0x3C 28. "E60,Event #60" "0,1" newline bitfld.long 0x3C 27. "E59,Event #59" "0,1" bitfld.long 0x3C 26. "E58,Event #58" "0,1" newline bitfld.long 0x3C 25. "E57,Event #57" "0,1" bitfld.long 0x3C 24. "E56,Event #56" "0,1" newline bitfld.long 0x3C 23. "E55,Event #55" "0,1" bitfld.long 0x3C 22. "E54,Event #54" "0,1" newline bitfld.long 0x3C 21. "E53,Event #53" "0,1" bitfld.long 0x3C 20. "E52,Event #52" "0,1" newline bitfld.long 0x3C 19. "E51,Event #51" "0,1" bitfld.long 0x3C 18. "E50,Event #50" "0,1" newline bitfld.long 0x3C 17. "E49,Event #49" "0,1" bitfld.long 0x3C 16. "E48,Event #48" "0,1" newline bitfld.long 0x3C 15. "E47,Event #47" "0,1" bitfld.long 0x3C 14. "E46,Event #46" "0,1" newline bitfld.long 0x3C 13. "E45,Event #45" "0,1" bitfld.long 0x3C 12. "E44,Event #44" "0,1" newline bitfld.long 0x3C 11. "E43,Event #43" "0,1" bitfld.long 0x3C 10. "E42,Event #42" "0,1" newline bitfld.long 0x3C 9. "E41,Event #41" "0,1" bitfld.long 0x3C 8. "E40,Event #40" "0,1" newline bitfld.long 0x3C 7. "E39,Event #39" "0,1" bitfld.long 0x3C 6. "E38,Event #38" "0,1" newline bitfld.long 0x3C 5. "E37,Event #37" "0,1" bitfld.long 0x3C 4. "E36,Event #36" "0,1" newline bitfld.long 0x3C 3. "E35,Event #35" "0,1" bitfld.long 0x3C 2. "E34,Event #34" "0,1" newline bitfld.long 0x3C 1. "E33,Event #33" "0,1" bitfld.long 0x3C 0. "E32,Event #32" "0,1" line.long 0x40 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x40 31. "E31,Event #31" "0,1" bitfld.long 0x40 30. "E30,Event #30" "0,1" newline bitfld.long 0x40 29. "E29,Event #29" "0,1" bitfld.long 0x40 28. "E28,Event #28" "0,1" newline bitfld.long 0x40 27. "E27,Event #27" "0,1" bitfld.long 0x40 26. "E26,Event #26" "0,1" newline bitfld.long 0x40 25. "E25,Event #25" "0,1" bitfld.long 0x40 24. "E24,Event #24" "0,1" newline bitfld.long 0x40 23. "E23,Event #23" "0,1" bitfld.long 0x40 22. "E22,Event #22" "0,1" newline bitfld.long 0x40 21. "E21,Event #21" "0,1" bitfld.long 0x40 20. "E20,Event #20" "0,1" newline bitfld.long 0x40 19. "E19,Event #19" "0,1" bitfld.long 0x40 18. "E18,Event #18" "0,1" newline bitfld.long 0x40 17. "E17,Event #17" "0,1" bitfld.long 0x40 16. "E16,Event #16" "0,1" newline bitfld.long 0x40 15. "E15,Event #15" "0,1" bitfld.long 0x40 14. "E14,Event #14" "0,1" newline bitfld.long 0x40 13. "E13,Event #13" "0,1" bitfld.long 0x40 12. "E12,Event #12" "0,1" newline bitfld.long 0x40 11. "E11,Event #11" "0,1" bitfld.long 0x40 10. "E10,Event #10" "0,1" newline bitfld.long 0x40 9. "E9,Event #9" "0,1" bitfld.long 0x40 8. "E8,Event #8" "0,1" newline bitfld.long 0x40 7. "E7,Event #7" "0,1" bitfld.long 0x40 6. "E6,Event #6" "0,1" newline bitfld.long 0x40 5. "E5,Event #5" "0,1" bitfld.long 0x40 4. "E4,Event #4" "0,1" newline bitfld.long 0x40 3. "E3,Event #3" "0,1" bitfld.long 0x40 2. "E2,Event #2" "0,1" newline bitfld.long 0x40 1. "E1,Event #1" "0,1" bitfld.long 0x40 0. "E0,Event #0" "0,1" line.long 0x44 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x44 31. "E63,Event #63" "0,1" bitfld.long 0x44 30. "E62,Event #62" "0,1" newline bitfld.long 0x44 29. "E61,Event #61" "0,1" bitfld.long 0x44 28. "E60,Event #60" "0,1" newline bitfld.long 0x44 27. "E59,Event #59" "0,1" bitfld.long 0x44 26. "E58,Event #58" "0,1" newline bitfld.long 0x44 25. "E57,Event #57" "0,1" bitfld.long 0x44 24. "E56,Event #56" "0,1" newline bitfld.long 0x44 23. "E55,Event #55" "0,1" bitfld.long 0x44 22. "E54,Event #54" "0,1" newline bitfld.long 0x44 21. "E53,Event #53" "0,1" bitfld.long 0x44 20. "E52,Event #52" "0,1" newline bitfld.long 0x44 19. "E51,Event #51" "0,1" bitfld.long 0x44 18. "E50,Event #50" "0,1" newline bitfld.long 0x44 17. "E49,Event #49" "0,1" bitfld.long 0x44 16. "E48,Event #48" "0,1" newline bitfld.long 0x44 15. "E47,Event #47" "0,1" bitfld.long 0x44 14. "E46,Event #46" "0,1" newline bitfld.long 0x44 13. "E45,Event #45" "0,1" bitfld.long 0x44 12. "E44,Event #44" "0,1" newline bitfld.long 0x44 11. "E43,Event #43" "0,1" bitfld.long 0x44 10. "E42,Event #42" "0,1" newline bitfld.long 0x44 9. "E41,Event #41" "0,1" bitfld.long 0x44 8. "E40,Event #40" "0,1" newline bitfld.long 0x44 7. "E39,Event #39" "0,1" bitfld.long 0x44 6. "E38,Event #38" "0,1" newline bitfld.long 0x44 5. "E37,Event #37" "0,1" bitfld.long 0x44 4. "E36,Event #36" "0,1" newline bitfld.long 0x44 3. "E35,Event #35" "0,1" bitfld.long 0x44 2. "E34,Event #34" "0,1" newline bitfld.long 0x44 1. "E33,Event #33" "0,1" bitfld.long 0x44 0. "E32,Event #32" "0,1" rgroup.long 0x1050++0x2B line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x08 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x0C "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x10 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x14 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x18 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x1C "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x20 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x24 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x28 "EDMA_TPCC_IEVAL,Interrupt Eval Register" hexmask.long 0x28 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" newline bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1080++0x17 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 7. "E7,Event #7" "0,1" newline rbitfld.long 0x04 6. "E6,Event #6" "0,1" rbitfld.long 0x04 5. "E5,Event #5" "0,1" newline rbitfld.long 0x04 4. "E4,Event #4" "0,1" rbitfld.long 0x04 3. "E3,Event #3" "0,1" newline rbitfld.long 0x04 2. "E2,Event #2" "0,1" rbitfld.long 0x04 1. "E1,Event #1" "0,1" newline rbitfld.long 0x04 0. "E0,Event #0" "0,1" line.long 0x08 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,Event #7" "0,1" newline bitfld.long 0x08 6. "E6,Event #6" "0,1" bitfld.long 0x08 5. "E5,Event #5" "0,1" newline bitfld.long 0x08 4. "E4,Event #4" "0,1" bitfld.long 0x08 3. "E3,Event #3" "0,1" newline bitfld.long 0x08 2. "E2,Event #2" "0,1" bitfld.long 0x08 1. "E1,Event #1" "0,1" newline bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,Event #7" "0,1" newline bitfld.long 0x0C 6. "E6,Event #6" "0,1" bitfld.long 0x0C 5. "E5,Event #5" "0,1" newline bitfld.long 0x0C 4. "E4,Event #4" "0,1" bitfld.long 0x0C 3. "E3,Event #3" "0,1" newline bitfld.long 0x0C 2. "E2,Event #2" "0,1" bitfld.long 0x0C 1. "E1,Event #1" "0,1" newline bitfld.long 0x0C 0. "E0,Event #0" "0,1" line.long 0x10 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 7. "E7,Event #7" "0,1" newline rbitfld.long 0x10 6. "E6,Event #6" "0,1" rbitfld.long 0x10 5. "E5,Event #5" "0,1" newline rbitfld.long 0x10 4. "E4,Event #4" "0,1" rbitfld.long 0x10 3. "E3,Event #3" "0,1" newline rbitfld.long 0x10 2. "E2,Event #2" "0,1" rbitfld.long 0x10 1. "E1,Event #1" "0,1" newline rbitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event #7" "0,1" newline bitfld.long 0x14 6. "E6,Event #6" "0,1" bitfld.long 0x14 5. "E5,Event #5" "0,1" newline bitfld.long 0x14 4. "E4,Event #4" "0,1" bitfld.long 0x14 3. "E3,Event #3" "0,1" newline bitfld.long 0x14 2. "E2,Event #2" "0,1" bitfld.long 0x14 1. "E1,Event #1" "0,1" newline bitfld.long 0x14 0. "E0,Event #0" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2200++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2600++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2204++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2604++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2208++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2608++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x220C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x260C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2210++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2610++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2214++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2614++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2218++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2618++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x221C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x261C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2220++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2620++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2224++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2624++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2228++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2628++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x222C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x262C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2230++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2630++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2234++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2634++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2238++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2638++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x223C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x263C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2240++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2640++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2244++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2644++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2250++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2650++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2254++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2654++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2258++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2658++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x225C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x265C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2260++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2660++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2264++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2664++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2268++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2668++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x226C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x266C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2270++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2670++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2274++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2674++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2278++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2678++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2A78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2C78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2E78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2280++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2680++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2284++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2684++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2288++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2688++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x228C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x268C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2290++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2690++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2294++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2694++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4020++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_1,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4060++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_3,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_5,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_6,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_7,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4100++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_8,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4120++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_9,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4140++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4160++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_11,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4180++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_12,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_13,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_14,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_15,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4200++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4220++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_17,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4240++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_18,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4260++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_19,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4280++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_20,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_21,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_22,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_23,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4300++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_24,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4320++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_25,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4340++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_26,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4360++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_27,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4380++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_28,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_29,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_30,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_31,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4400++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4420++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_33,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4440++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_34,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4460++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_35,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4480++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_36,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_37,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_38,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_39,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4500++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_40,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4520++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_41,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4540++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_42,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4560++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_43,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4580++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_44,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_45,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_46,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_47,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4600++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4620++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_49,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4640++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_50,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4660++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_51,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4680++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_52,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_53,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_54,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_55,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4700++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_56,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4720++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_57,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4740++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_58,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4760++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_59,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4780++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_60,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_61,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_62,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_63,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4800++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4820++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_65,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4840++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_66,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4860++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_67,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4880++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_68,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_69,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_70,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_71,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4900++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_72,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4920++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_73,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4940++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_74,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4960++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_75,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4980++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_76,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_77,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_78,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_79,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_81,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_82,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_83,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_84,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_85,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_86,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_87,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_88,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_89,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_90,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_91,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_92,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_93,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_94,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_95,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_96,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_97,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_98,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_99,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_101,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_102,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_103,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_104,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_105,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_106,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_107,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_108,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_109,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_110,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_111,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_113,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_114,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_115,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_116,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_117,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_118,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_119,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_120,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_121,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_122,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_123,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_124,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_125,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_126,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_127,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" group.long 0x4024++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_1,Source Address" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" group.long 0x4064++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_3,Source Address" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" group.long 0x40A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_5,Source Address" group.long 0x40C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_6,Source Address" group.long 0x40E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_7,Source Address" group.long 0x4104++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_8,Source Address" group.long 0x4124++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_9,Source Address" group.long 0x4144++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_10,Source Address" group.long 0x4164++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_11,Source Address" group.long 0x4184++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_12,Source Address" group.long 0x41A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_13,Source Address" group.long 0x41C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_14,Source Address" group.long 0x41E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_15,Source Address" group.long 0x4204++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_16,Source Address" group.long 0x4224++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_17,Source Address" group.long 0x4244++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_18,Source Address" group.long 0x4264++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_19,Source Address" group.long 0x4284++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_20,Source Address" group.long 0x42A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_21,Source Address" group.long 0x42C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_22,Source Address" group.long 0x42E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_23,Source Address" group.long 0x4304++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_24,Source Address" group.long 0x4324++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_25,Source Address" group.long 0x4344++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_26,Source Address" group.long 0x4364++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_27,Source Address" group.long 0x4384++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_28,Source Address" group.long 0x43A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_29,Source Address" group.long 0x43C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_30,Source Address" group.long 0x43E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_31,Source Address" group.long 0x4404++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_32,Source Address" group.long 0x4424++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_33,Source Address" group.long 0x4444++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_34,Source Address" group.long 0x4464++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_35,Source Address" group.long 0x4484++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_36,Source Address" group.long 0x44A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_37,Source Address" group.long 0x44C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_38,Source Address" group.long 0x44E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_39,Source Address" group.long 0x4504++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_40,Source Address" group.long 0x4524++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_41,Source Address" group.long 0x4544++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_42,Source Address" group.long 0x4564++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_43,Source Address" group.long 0x4584++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_44,Source Address" group.long 0x45A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_45,Source Address" group.long 0x45C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_46,Source Address" group.long 0x45E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_47,Source Address" group.long 0x4604++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_48,Source Address" group.long 0x4624++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_49,Source Address" group.long 0x4644++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_50,Source Address" group.long 0x4664++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_51,Source Address" group.long 0x4684++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_52,Source Address" group.long 0x46A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_53,Source Address" group.long 0x46C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_54,Source Address" group.long 0x46E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_55,Source Address" group.long 0x4704++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_56,Source Address" group.long 0x4724++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_57,Source Address" group.long 0x4744++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_58,Source Address" group.long 0x4764++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_59,Source Address" group.long 0x4784++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_60,Source Address" group.long 0x47A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_61,Source Address" group.long 0x47C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_62,Source Address" group.long 0x47E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_63,Source Address" group.long 0x4804++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_64,Source Address" group.long 0x4824++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_65,Source Address" group.long 0x4844++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_66,Source Address" group.long 0x4864++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_67,Source Address" group.long 0x4884++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_68,Source Address" group.long 0x48A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_69,Source Address" group.long 0x48C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_70,Source Address" group.long 0x48E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_71,Source Address" group.long 0x4904++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_72,Source Address" group.long 0x4924++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_73,Source Address" group.long 0x4944++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_74,Source Address" group.long 0x4964++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_75,Source Address" group.long 0x4984++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_76,Source Address" group.long 0x49A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_77,Source Address" group.long 0x49C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_78,Source Address" group.long 0x49E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_79,Source Address" group.long 0x4A04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_80,Source Address" group.long 0x4A24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_81,Source Address" group.long 0x4A44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_82,Source Address" group.long 0x4A64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_83,Source Address" group.long 0x4A84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_84,Source Address" group.long 0x4AA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_85,Source Address" group.long 0x4AC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_86,Source Address" group.long 0x4AE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_87,Source Address" group.long 0x4B04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_88,Source Address" group.long 0x4B24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_89,Source Address" group.long 0x4B44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_90,Source Address" group.long 0x4B64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_91,Source Address" group.long 0x4B84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_92,Source Address" group.long 0x4BA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_93,Source Address" group.long 0x4BC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_94,Source Address" group.long 0x4BE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_95,Source Address" group.long 0x4C04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_96,Source Address" group.long 0x4C24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_97,Source Address" group.long 0x4C44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_98,Source Address" group.long 0x4C64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_99,Source Address" group.long 0x4C84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_100,Source Address" group.long 0x4CA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_101,Source Address" group.long 0x4CC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_102,Source Address" group.long 0x4CE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_103,Source Address" group.long 0x4D04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_104,Source Address" group.long 0x4D24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_105,Source Address" group.long 0x4D44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_106,Source Address" group.long 0x4D64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_107,Source Address" group.long 0x4D84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_108,Source Address" group.long 0x4DA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_109,Source Address" group.long 0x4DC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_110,Source Address" group.long 0x4DE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_111,Source Address" group.long 0x4E04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_112,Source Address" group.long 0x4E24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_113,Source Address" group.long 0x4E44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_114,Source Address" group.long 0x4E64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_115,Source Address" group.long 0x4E84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_116,Source Address" group.long 0x4EA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_117,Source Address" group.long 0x4EC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_118,Source Address" group.long 0x4EE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_119,Source Address" group.long 0x4F04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_120,Source Address" group.long 0x4F24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_121,Source Address" group.long 0x4F44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_122,Source Address" group.long 0x4F64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_123,Source Address" group.long 0x4F84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_124,Source Address" group.long 0x4FA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_125,Source Address" group.long 0x4FC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_126,Source Address" group.long 0x4FE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_127,Source Address" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x402C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_1,Destination Address" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x406C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_3,Destination Address" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x40AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_5,Destination Address" group.long 0x40CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_6,Destination Address" group.long 0x40EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_7,Destination Address" group.long 0x410C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_8,Destination Address" group.long 0x412C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_9,Destination Address" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x416C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_11,Destination Address" group.long 0x418C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_12,Destination Address" group.long 0x41AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_13,Destination Address" group.long 0x41CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_14,Destination Address" group.long 0x41EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_15,Destination Address" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x422C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_17,Destination Address" group.long 0x424C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_18,Destination Address" group.long 0x426C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_19,Destination Address" group.long 0x428C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_20,Destination Address" group.long 0x42AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_21,Destination Address" group.long 0x42CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_22,Destination Address" group.long 0x42EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_23,Destination Address" group.long 0x430C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_24,Destination Address" group.long 0x432C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_25,Destination Address" group.long 0x434C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_26,Destination Address" group.long 0x436C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_27,Destination Address" group.long 0x438C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_28,Destination Address" group.long 0x43AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_29,Destination Address" group.long 0x43CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_30,Destination Address" group.long 0x43EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_31,Destination Address" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x442C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_33,Destination Address" group.long 0x444C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_34,Destination Address" group.long 0x446C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_35,Destination Address" group.long 0x448C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_36,Destination Address" group.long 0x44AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_37,Destination Address" group.long 0x44CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_38,Destination Address" group.long 0x44EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_39,Destination Address" group.long 0x450C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_40,Destination Address" group.long 0x452C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_41,Destination Address" group.long 0x454C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_42,Destination Address" group.long 0x456C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_43,Destination Address" group.long 0x458C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_44,Destination Address" group.long 0x45AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_45,Destination Address" group.long 0x45CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_46,Destination Address" group.long 0x45EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_47,Destination Address" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x462C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_49,Destination Address" group.long 0x464C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_50,Destination Address" group.long 0x466C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_51,Destination Address" group.long 0x468C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_52,Destination Address" group.long 0x46AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_53,Destination Address" group.long 0x46CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_54,Destination Address" group.long 0x46EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_55,Destination Address" group.long 0x470C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_56,Destination Address" group.long 0x472C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_57,Destination Address" group.long 0x474C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_58,Destination Address" group.long 0x476C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_59,Destination Address" group.long 0x478C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_60,Destination Address" group.long 0x47AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_61,Destination Address" group.long 0x47CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_62,Destination Address" group.long 0x47EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_63,Destination Address" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x482C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_65,Destination Address" group.long 0x484C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_66,Destination Address" group.long 0x486C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_67,Destination Address" group.long 0x488C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_68,Destination Address" group.long 0x48AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_69,Destination Address" group.long 0x48CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_70,Destination Address" group.long 0x48EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_71,Destination Address" group.long 0x490C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_72,Destination Address" group.long 0x492C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_73,Destination Address" group.long 0x494C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_74,Destination Address" group.long 0x496C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_75,Destination Address" group.long 0x498C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_76,Destination Address" group.long 0x49AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_77,Destination Address" group.long 0x49CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_78,Destination Address" group.long 0x49EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_79,Destination Address" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_81,Destination Address" group.long 0x4A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_82,Destination Address" group.long 0x4A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_83,Destination Address" group.long 0x4A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_84,Destination Address" group.long 0x4AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_85,Destination Address" group.long 0x4ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_86,Destination Address" group.long 0x4AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_87,Destination Address" group.long 0x4B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_88,Destination Address" group.long 0x4B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_89,Destination Address" group.long 0x4B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_90,Destination Address" group.long 0x4B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_91,Destination Address" group.long 0x4B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_92,Destination Address" group.long 0x4BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_93,Destination Address" group.long 0x4BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_94,Destination Address" group.long 0x4BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_95,Destination Address" group.long 0x4C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_96,Destination Address" group.long 0x4C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_97,Destination Address" group.long 0x4C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_98,Destination Address" group.long 0x4C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_99,Destination Address" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_101,Destination Address" group.long 0x4CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_102,Destination Address" group.long 0x4CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_103,Destination Address" group.long 0x4D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_104,Destination Address" group.long 0x4D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_105,Destination Address" group.long 0x4D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_106,Destination Address" group.long 0x4D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_107,Destination Address" group.long 0x4D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_108,Destination Address" group.long 0x4DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_109,Destination Address" group.long 0x4DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_110,Destination Address" group.long 0x4DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_111,Destination Address" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_113,Destination Address" group.long 0x4E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_114,Destination Address" group.long 0x4E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_115,Destination Address" group.long 0x4E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_116,Destination Address" group.long 0x4EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_117,Destination Address" group.long 0x4ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_118,Destination Address" group.long 0x4EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_119,Destination Address" group.long 0x4F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_120,Destination Address" group.long 0x4F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_121,Destination Address" group.long 0x4F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_122,Destination Address" group.long 0x4F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_123,Destination Address" group.long 0x4F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_124,Destination Address" group.long 0x4FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_125,Destination Address" group.long 0x4FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_126,Destination Address" group.long 0x4FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_127,Destination Address" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_1," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_3," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_5," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_6," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_7," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_8," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_9," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_11," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_12," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_13," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_14," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_15," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_17," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_18," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_19," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_20," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_21," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_22," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_23," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_24," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_25," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_26," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_27," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_28," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_29," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_30," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_31," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_33," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_34," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_35," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_36," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_37," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_38," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_39," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_40," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_41," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_42," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_43," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_44," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_45," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_46," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_47," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_49," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_50," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_51," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_52," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_53," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_54," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_55," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_56," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_57," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_58," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_59," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_60," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_61," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_62," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_63," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_65," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_66," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_67," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_68," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_69," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_70," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_71," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_72," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_73," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_74," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_75," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_76," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_77," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_78," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_79," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_81," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_82," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_83," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_84," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_85," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_86," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_87," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_88," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_89," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_90," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_91," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_92," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_93," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_94," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_95," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_96," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_97," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_98," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_99," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_101," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_102," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_103," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_104," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_105," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_106," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_107," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_108," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_109," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_110," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_111," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_113," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_114," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_115," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_116," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_117," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_118," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_119," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_120," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_121," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_122," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_123," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_124," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_125," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_126," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_127," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x403C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x407C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x411C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x413C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x417C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x419C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x423C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x425C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x427C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x429C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x431C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x433C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x435C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x437C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x439C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x443C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x445C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x447C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x449C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x451C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x453C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x455C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x457C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x459C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x463C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x465C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x467C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x469C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x471C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x473C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x475C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x477C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x479C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x483C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x485C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x487C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x489C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x491C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x493C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x495C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x497C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x499C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x40D05000 ad:0x40D06000 ) tree "DSP1_EDMA_TPTC$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPTCn_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPTCn_TCCFG,TC Configuration Register" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 8.--9. "DREGDEPTH,Destination Register FIFO Depth Parameterization" "0,1,2,3" bitfld.long 0x04 6.--7. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" group.long 0x100++0x13 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 11.--12. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" rbitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" rbitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" line.long 0x04 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" rbitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x08 "EDMA_TPTCn_INTEN,Interrupt Enable Register" hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x0C "EDMA_TPTCn_INTCLR,Interrupt Clear Register" hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x10 "EDMA_TPTCn_INTCMD,Interrupt Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" group.long 0x120++0x13 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" rbitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 1. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" line.long 0x04 "EDMA_TPTCn_ERREN,Error Enable Register" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x04 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x04 1. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" line.long 0x08 "EDMA_TPTCn_ERRCLR,Error Clear Register" hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x08 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x08 1. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" line.long 0x0C "EDMA_TPTCn_ERRDET,Error Details Register" hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0C 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" rbitfld.long 0x0C 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 14.--15. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EDMA_TPTCn_ERRCMD,Error Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" group.long 0x200++0x17 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" rbitfld.long 0x00 21. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" rbitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "Highest priority,Priority 1,?,?,?,?,?,Lowest priority" newline rbitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" line.long 0x08 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count" line.long 0x0C "EDMA_TPTCn_PDST,Program Set Destination Address" line.long 0x10 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" line.long 0x14 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x240++0x23 line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" line.long 0x08 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" line.long 0x0C "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved. return 0x0 w/o AERROR" line.long 0x10 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" line.long 0x14 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" line.long 0x1C "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" line.long 0x20 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" group.long 0x280++0x0B line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" line.long 0x04 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" line.long 0x08 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" group.long 0x300++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x304++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x344++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x308++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x348++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x30C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x34C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x350++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" group.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x354++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end repeat.end tree "DSP1_FW_CFG_TARG" base ad:0x4A172000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DSP1_FW_L2_NOC_CFG" base ad:0x40D03000 group.long 0x00++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0,Core 0 Error log register" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" newline rbitfld.long 0x00 26. "RESERVED," "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" bitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x40++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 2.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x88++0x17 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" line.long 0x08 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1,Start physical address of region 1" hexmask.long 0x08 4.--31. 1. "RESERVED," bitfld.long 0x08 0.--3. "START_REGION_1,Physical target start address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1,End physical address of region 1" bitfld.long 0x0C 31. "END_REGION_1_ENABLE,End Region 1 enable" "0,1" hexmask.long 0x0C 4.--30. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "END_REGION_1,Physical target end address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_1,RM_PERMISSION_REGION_1_LOW register" hexmask.long.word 0x10 16.--31. 1. "RESERVED," bitfld.long 0x10 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x10 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x10 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x10 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x10 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x10 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x10 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x10 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x10 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_1,RM_PERMISSION_REGION_1_HIGH register" bitfld.long 0x14 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x14 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x14 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x14 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x14 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x14 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x14 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x14 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x14 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x14 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x14 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x14 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x14 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x14 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x14 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x14 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x14 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x14 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x14 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x14 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x14 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x14 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x14 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x14 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x14 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x14 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x14 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x14 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x14 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x14 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x14 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x14 0. "R0,Initiator ID0 permission" "0,1" group.long 0x1000++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0,Core 0 Error log register" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" newline rbitfld.long 0x00 26. "RESERVED," "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" bitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x1040++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 2.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x1088++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" rgroup.long 0x4000++0x17 line.long 0x00 "DSPNOC_FLAGMUX_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_FLAGMUX_ID_REVISIONID," line.long 0x08 "DSPNOC_FLAGMUX_FAULTEN," hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "FAULTEN,Global Fault Enable register" "0,1" line.long 0x0C "DSPNOC_FLAGMUX_FAULTSTATUS," hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "FAULTSTATUS,Global Fault Status register" "0,1" line.long 0x10 "DSPNOC_FLAGMUX_FLAGINEN0," hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" line.long 0x14 "DSPNOC_FLAGMUX_FLAGINSTATUS0," hexmask.long 0x14 1.--31. 1. "RESERVED," bitfld.long 0x14 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" rgroup.long 0x4200++0x1B line.long 0x00 "DSPNOC_ERRORLOG_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_ERRORLOG_ID_REVISIONID," line.long 0x08 "DSPNOC_ERRORLOG_FAULTEN," hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "FAULTEN,Enable Fault output" "0,1" line.long 0x0C "DSPNOC_ERRORLOG_ERRVLD," hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "ERRVLD,Error logged Valid" "0,1" line.long 0x10 "DSPNOC_ERRORLOG_ERRCLR," hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "ERRCLR,Clr ErrVld status" "0,1" line.long 0x14 "DSPNOC_ERRORLOG_ERRLOG0,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x14 31. "FORMAT,Format of ErrLog0 register" "0,1" bitfld.long 0x14 28.--30. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--27. 1. "LEN1,Header: Len1 value" bitfld.long 0x14 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x14 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0. "LOCK,Header: Lock bit value" "0,1" line.long 0x18 "DSPNOC_ERRORLOG_ERRLOG1," hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED," hexmask.long.word 0x18 0.--14. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x4220++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG3," bitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 0.--30. 1. "ERRLOG3,Header: Addr lsb value" rgroup.long 0x4228++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG5," hexmask.long.word 0x00 22.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--21. 1. "ERRLOG5,Header: User lsb value" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x40D01000 ad:0x40D02000 ) tree "DSP1_MMU$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Write 0's for future compatibility" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" rbitfld.long 0x00 5.--7. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x00 2. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" hexmask.long 0x08 5.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" newline bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0_w,EMUMISS_1_r" bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" hexmask.long 0x0C 5.--31. 1. "RESERVED,Write 0's for future compatibility Read returns 0" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" newline bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0,EMUMISS_1" bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" hexmask.long 0x00 1.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" hexmask.long 0x04 4.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable" "TWLENABLE_0,TWLENABLE_1" newline bitfld.long 0x04 1. "MMUENABLE,MMU enable" "MMUENABLE_0,MMUENABLE_1" rbitfld.long 0x04 0. "RESERVED,Write 0's for future compatibility" "0,1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" hexmask.long.byte 0x0C 0.--6. 1. "RESERVED,Write 0's for future compatibility" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 9. "RESERVED,Write 0's for future compatibility" "0,1" newline bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 0.--3. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" hexmask.long 0x14 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x18 4.--11. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x18 3. "P,Preserved bit" "P_0,P_1" newline bitfld.long 0x18 2. "V,Valid bit" "V_0,V_1" bitfld.long 0x18 0.--1. "PAGESIZE,Page size" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x1C 0.--11. 1. "RESERVED,Write 0's for future compatibility" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" hexmask.long 0x20 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" hexmask.long 0x24 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x28 4.--11. 1. "RESERVED,Reads return 0" bitfld.long 0x28 3. "P,Preserved bit" "P_0_r,P_1_r" newline bitfld.long 0x28 2. "V,Valid bit" "V_0_r,V_1_r" bitfld.long 0x28 0.--1. "PAGESIZE,Page size" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x2C 0.--11. 1. "RESERVED,Reads return 0" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" newline rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "0,1,2,3" bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "0,1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" hexmask.long.word 0x08 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 0.--15. 1. "RESERVED,Reserved" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 0.--15. 1. "RESERVED,Reserved" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 0.--15. 1. "RESERVED,Reserved" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the fourth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 0.--15. 1. "RESERVED,Reserved" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of fourth NO TRANSLATION REGION for 2D bursts" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" width 0x0B tree.end repeat.end tree "DSP1_PRM" base ad:0x4AE06400 group.long 0x00++0x07 line.long 0x00 "PM_DSP1_PWRSTCTRL,This register controls the DSP power state to reach upon a domain sleep transition" hexmask.long.word 0x00 22.--31. 1. "RESERVED," rbitfld.long 0x00 20.--21. "DSP1_EDMA_ONSTATE,DSP_EDMA state when domain is ON" "?,?,?,DSP1_EDMA_ONSTATE_3" rbitfld.long 0x00 18.--19. "DSP1_L2_ONSTATE,DSP_L2 state when domain is ON" "?,?,?,DSP1_L2_ONSTATE_3" newline rbitfld.long 0x00 16.--17. "DSP1_L1_ONSTATE,DSP_L1 state when domain is ON" "?,?,?,DSP1_L1_ONSTATE_3" hexmask.long.word 0x00 5.--15. 1. "RESERVED," bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_DSP1_PWRSTST,This register provides a status on the DSP domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" hexmask.long.word 0x04 10.--19. 1. "RESERVED," rbitfld.long 0x04 8.--9. "DSP1_EDMA_STATEST,DSP_EDMA memory state status" "DSP1_EDMA_STATEST_0,DSP1_EDMA_STATEST_1,DSP1_EDMA_STATEST_2,DSP1_EDMA_STATEST_3" newline rbitfld.long 0x04 6.--7. "DSP1_L2_STATEST,DSP_L2 memory state status" "DSP1_L2_STATEST_0,DSP1_L2_STATEST_1,DSP1_L2_STATEST_2,DSP1_L2_STATEST_3" rbitfld.long 0x04 4.--5. "DSP1_L1_STATEST,DSP_L1 memory state status" "DSP1_L1_STATEST_0,DSP1_L1_STATEST_1,DSP1_L1_STATEST_2,DSP1_L1_STATEST_3" rbitfld.long 0x04 3. "RESERVED," "0,1" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_DSP1_RSTCTRL,This register controls the release of the DSP sub-system resets" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "RST_DSP1,DSP reset control" "RST_DSP1_0,RST_DSP1_1" bitfld.long 0x00 0. "RST_DSP1_LRST,DSP Local reset control" "RST_DSP1_LRST_0,RST_DSP1_LRST_1" line.long 0x04 "RM_DSP1_RSTST,This register logs the different reset sources of the DSP domain" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "RST_DSP1_EMU_REQ,DSP processor has been reset due to DSP emulation reset request driven from DSP-SS" "RST_DSP1_EMU_REQ_0,RST_DSP1_EMU_REQ_1" bitfld.long 0x04 2. "RST_DSP1_EMU,DSP domain has been reset due to emulation reset source e.g" "RST_DSP1_EMU_0,RST_DSP1_EMU_1" newline bitfld.long 0x04 1. "RST_DSP1,DSP SW reset status" "RST_DSP1_0,RST_DSP1_1" bitfld.long 0x04 0. "RST_DSP1_LRST,DSP Local SW reset" "RST_DSP1_LRST_0,RST_DSP1_LRST_1" group.long 0x24++0x03 line.long 0x00 "RM_DSP1_DSP1_CONTEXT,This register contains dedicated DSP context statuses" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," bitfld.long 0x00 10. "LOSTMEM_DSP_EDMA,Specify if memory-based context in DSP_EDMA memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_EDMA_0,LOSTMEM_DSP_EDMA_1" bitfld.long 0x00 9. "LOSTMEM_DSP_L2,Specify if memory-based context in DSP_L2 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_L2_0,LOSTMEM_DSP_L2_1" newline bitfld.long 0x00 8. "LOSTMEM_DSP_L1,Specify if memory-based context in DSP_L1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_L1_0,LOSTMEM_DSP_L1_1" hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "DSP1_SDMA_FW" base ad:0x4A171000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "DSP1_SDMA_TARG" base ad:0x44000300 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "DSP1_SYSTEM" base ad:0x40D00000 rgroup.long 0x00++0x1B line.long 0x00 "DSP_SYS_REVISION," line.long 0x04 "DSP_SYS_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," bitfld.long 0x04 0.--3. "NUM,Instance Number Set by subsystem input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DSP_SYS_SYSCONFIG," hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 8. "RESERVED,Reserved" "0,1" rbitfld.long 0x08 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x08 4.--5. "STANDBYMODE," "?,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x08 2.--3. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x08 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x0C "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode" hexmask.long 0x0C 6.--31. 1. "RESERVED," bitfld.long 0x0C 4.--5. "OCPI_DISC_STAT,L3_MAIN (OCP) Initiator(s) Disconnect Status" "OCPI_DISC_STAT_0_r,OCPI_DISC_STAT_1_r,OCPI_DISC_STAT_2_r,?" bitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "TC1_STAT,EDMA TC1 Status" "TC1_STAT_0,TC1_STAT_1" bitfld.long 0x0C 1. "TC0_STAT,EDMA TC0 Status" "TC0_STAT_0,TC0_STAT_1" bitfld.long 0x0C 0. "C66X_STAT,C66x Status" "C66X_STAT_0,C66X_STAT_1" line.long 0x10 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "OCPI_DISC,OCP Initiator (on L3_MAIN) Disconnect request" "OCPI_DISC_0_w,OCPI_DISC_1_w" line.long 0x14 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators" rbitfld.long 0x14 31. "RESERVED," "0,1" bitfld.long 0x14 28.--30. "SDMA_PRI,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port" "0,1,2,3,4,5,6,7" rbitfld.long 0x14 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 24. "NOPOSTOVERRIDE,OCP Posted Write vs Non-Posted Write override" "NOPOSTOVERRIDE_0,NOPOSTOVERRIDE_1" rbitfld.long 0x14 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x14 20.--21. "SDMA_L2PRES,OCP Target port L2 Interconnect Pressure" "SDMA_L2PRES_0,SDMA_L2PRES_1,SDMA_L2PRES_2,SDMA_L2PRES_3" newline rbitfld.long 0x14 18.--19. "RESERVED," "0,1,2,3" bitfld.long 0x14 16.--17. "CFG_L2PRES,DSP CFG L2 Interconnect Pressure" "CFG_L2PRES_0,CFG_L2PRES_1,CFG_L2PRES_2,CFG_L2PRES_3" rbitfld.long 0x14 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 12.--13. "TC1_L2PRES,TC1 L2 Interconnect Pressure" "TC1_L2PRES_0,TC1_L2PRES_1,TC1_L2PRES_2,TC1_L2PRES_3" rbitfld.long 0x14 10.--11. "RESERVED," "0,1,2,3" bitfld.long 0x14 8.--9. "TC0_L2PRES,TC0 L2 Interconnect Pressure" "TC0_L2PRES_0,TC0_L2PRES_1,TC0_L2PRES_2,TC0_L2PRES_3" newline rbitfld.long 0x14 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x14 4.--5. "TC1_DBS,TC1 Default Burst size" "TC1_DBS_0,TC1_DBS_1,TC1_DBS_2,TC1_DBS_3" rbitfld.long 0x14 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 0.--1. "TC0_DBS,TC0 Default Burst size" "TC0_DBS_0,TC0_DBS_1,TC0_DBS_2,TC0_DBS_3" line.long 0x18 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs" hexmask.long.tbyte 0x18 13.--31. 1. "RESERVED," bitfld.long 0x18 12. "MMU1_ABORT,MU1 Abort" "MMU1_ABORT_0,MMU1_ABORT_1" rbitfld.long 0x18 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "MMU0_ABORT,MU0 Abort" "MMU0_ABORT_0,MMU0_ABORT_1" rbitfld.long 0x18 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 4. "MMU1_EN,MU1 Enable" "MMU1_EN_0,MMU1_EN_1" newline rbitfld.long 0x18 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 0. "MMU0_EN,MU1 Enable" "MMU0_EN_0,MMU0_EN_1" group.long 0x20++0x07 line.long 0x00 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x30++0x07 line.long 0x00 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x40++0x07 line.long 0x00 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state" line.long 0x04 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state" group.long 0x50++0x2F line.long 0x00 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.word 0x00 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--18. 1. "EVENT,Settable raw status for event #n" line.long 0x04 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector" hexmask.long.word 0x04 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x04 0.--18. 1. "EVENT,Clearable enabled status for event #n" line.long 0x08 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" hexmask.long.word 0x08 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x08 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x0C "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" hexmask.long.word 0x0C 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x0C 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x10 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x14 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x18 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x1C "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" line.long 0x20 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x24 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x28 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x2C "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" group.long 0xF8++0x07 line.long 0x00 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus" hexmask.long 0x00 4.--31. 1. "RESERVED," bitfld.long 0x00 0.--3. "GROUP,Debug Group output control mux selectN: GN = select output group N" "GROUP_0,GROUP_1,GROUP_2,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group" width 0x0B tree.end tree "DSP2_CM_CORE_AON" base ad:0x4A005600 group.long 0x00++0x0B line.long 0x00 "CM_DSP2_CLKSTCTRL,This register enables the DSP domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_DSP2_GFCLK,This field indicates the state of the DSP_ROOT_CLK clock in the domain" "CLKACTIVITY_DSP2_GFCLK_0,CLKACTIVITY_DSP2_GFCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_DSP2_STATICDEP,This register controls the static domain depedencies from DSP domain towards 'target' domains" rbitfld.long 0x04 31. "RESERVED," "0,1" bitfld.long 0x04 30. "CRC_STATDEP,Static dependency towards L3INIT clock domain" "CRC_STATDEP_0,CRC_STATDEP_1" newline bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE cLOCK dOMAIN" "PCIE_STATDEP_0,PCIE_STATDEP_1" bitfld.long 0x04 28. "ISS_STATDEP,Static dependency towards ISS Clock Domain" "ISS_STATDEP_0,ISS_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 Clock Domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 Clock Domain" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC Clock Domain" "GMAC_STATDEP_0,GMAC_STATDEP_1" bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPUClock Domain" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain" "IPU1_STATDEP_0,IPU1_STATDEP_1" bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 Clock Domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" newline bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 Clock Domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2CLOCK dOMAIN" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 CLOCK dOMAIN" "EVE1_STATDEP_0,EVE1_STATDEP_1" rbitfld.long 0x04 18. "RESERVED," "0,1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain" "CUSTEFUSE_STATDEP_0,?" rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC Clock Domain" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" rbitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,?" newline rbitfld.long 0x04 11. "RESERVED," "0,1" bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU Clock Domain" "GPU_STATDEP_0,GPU_STATDEP_1" newline bitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain" "CAM_STATDEP_0,CAM_STATDEP_1" bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" rbitfld.long 0x04 6. "RESERVED," "0,1" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 3. "RESERVED," "0,1" bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP1 clock domain" "DSP1_STATDEP_0,DSP1_STATDEP_1" bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_DSP2_DYNAMICDEP,This register controls the dynamic domain depedencies from DSP domain towards 'target' domains" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.tbyte 0x08 6.--23. 1. "RESERVED," rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20++0x03 line.long 0x00 "CM_DSP2_DSP2_CLKCTRL,This register manages the DSP clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "DSP2_EDMA_TPCC" base ad:0x41510000 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x04 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x04 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" newline rbitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x04 22.--23. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x04 19. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x04 15. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x04 11. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7" group.long 0xFC++0x113 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" line.long 0x04 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x04 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x08 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x08 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x0C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x10 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x14 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x18 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x1C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" hexmask.long.tbyte 0x20 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x20 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" hexmask.long.tbyte 0x24 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x24 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" hexmask.long.tbyte 0x28 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x28 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x28 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x2C "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.tbyte 0x2C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x2C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x2C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" hexmask.long.tbyte 0x30 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x30 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x30 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" hexmask.long.tbyte 0x34 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x34 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x34 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x38 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" hexmask.long.tbyte 0x38 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x38 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x38 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x3C "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" hexmask.long.tbyte 0x3C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x3C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x3C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" hexmask.long.tbyte 0x40 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x40 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x40 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x44 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" hexmask.long.tbyte 0x44 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x44 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x44 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x48 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" hexmask.long.tbyte 0x48 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x48 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x48 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x4C "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" hexmask.long.tbyte 0x4C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x4C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" hexmask.long.tbyte 0x50 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x50 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x50 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x54 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" hexmask.long.tbyte 0x54 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x54 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x54 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x58 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" hexmask.long.tbyte 0x58 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x58 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x58 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x5C "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" hexmask.long.tbyte 0x5C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x5C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x5C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x60 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" hexmask.long.tbyte 0x60 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x60 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x60 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x64 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" hexmask.long.tbyte 0x64 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x64 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x64 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x68 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" hexmask.long.tbyte 0x68 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x68 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x68 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x6C "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" hexmask.long.tbyte 0x6C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x6C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x6C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x70 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" hexmask.long.tbyte 0x70 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x70 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x70 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x74 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" hexmask.long.tbyte 0x74 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x74 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x74 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x78 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" hexmask.long.tbyte 0x78 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x78 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x78 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x7C "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" hexmask.long.tbyte 0x7C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x7C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x7C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x80 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" hexmask.long.tbyte 0x80 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x80 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x80 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x84 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" hexmask.long.tbyte 0x84 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x84 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x84 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x88 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" hexmask.long.tbyte 0x88 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x88 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x88 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x8C "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" hexmask.long.tbyte 0x8C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x8C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x8C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x90 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" hexmask.long.tbyte 0x90 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x90 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x90 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x94 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" hexmask.long.tbyte 0x94 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x94 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x94 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x98 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" hexmask.long.tbyte 0x98 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x98 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x98 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x9C "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" hexmask.long.tbyte 0x9C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x9C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x9C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA0 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA4 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA8 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xAC "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" hexmask.long.tbyte 0xAC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xAC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xAC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB0 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB4 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB8 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xBC "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" hexmask.long.tbyte 0xBC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xBC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xBC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC0 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC4 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC8 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xCC "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" hexmask.long.tbyte 0xCC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xCC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xCC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD0 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD4 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD8 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xDC "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" hexmask.long.tbyte 0xDC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xDC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xDC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE0 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE4 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE8 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xEC "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" hexmask.long.tbyte 0xEC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xEC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xEC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF0 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF4 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF8 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xFC "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" hexmask.long.tbyte 0xFC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xFC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xFC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x100 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" hexmask.long.tbyte 0x100 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x100 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x100 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x104 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x104 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x104 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x104 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x104 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x108 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x108 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x108 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x108 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x108 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x10C "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x10C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10C 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x10C 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x10C 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x110 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x110 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x110 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x110 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x110 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x240++0x23 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x00 31. "RESERVED,Reserved" "0,1" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 27. "RESERVED,Reserved" "0,1" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 23. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Reserved" "0,1" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 15. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x04 31. "RESERVED,Reserved" "0,1" bitfld.long 0x04 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 27. "RESERVED,Reserved" "0,1" bitfld.long 0x04 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 23. "RESERVED,Reserved" "0,1" bitfld.long 0x04 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED,Reserved" "0,1" bitfld.long 0x04 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 15. "RESERVED,Reserved" "0,1" bitfld.long 0x04 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 11. "RESERVED,Reserved" "0,1" bitfld.long 0x04 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED,Reserved" "0,1" bitfld.long 0x04 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x08 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x08 31. "RESERVED,Reserved" "0,1" bitfld.long 0x08 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 27. "RESERVED,Reserved" "0,1" bitfld.long 0x08 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 23. "RESERVED,Reserved" "0,1" bitfld.long 0x08 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED,Reserved" "0,1" bitfld.long 0x08 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 15. "RESERVED,Reserved" "0,1" bitfld.long 0x08 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 11. "RESERVED,Reserved" "0,1" bitfld.long 0x08 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED,Reserved" "0,1" bitfld.long 0x08 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x0C "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x0C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x10 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x10 31. "RESERVED,Reserved" "0,1" bitfld.long 0x10 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED,Reserved" "0,1" bitfld.long 0x10 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED,Reserved" "0,1" bitfld.long 0x10 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "RESERVED,Reserved" "0,1" bitfld.long 0x10 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 15. "RESERVED,Reserved" "0,1" bitfld.long 0x10 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 11. "RESERVED,Reserved" "0,1" bitfld.long 0x10 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" bitfld.long 0x10 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 3. "RESERVED,Reserved" "0,1" bitfld.long 0x10 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x14 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x14 31. "RESERVED,Reserved" "0,1" bitfld.long 0x14 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED,Reserved" "0,1" bitfld.long 0x14 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED,Reserved" "0,1" bitfld.long 0x14 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED,Reserved" "0,1" bitfld.long 0x14 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED,Reserved" "0,1" bitfld.long 0x14 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" bitfld.long 0x14 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED,Reserved" "0,1" bitfld.long 0x14 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x18 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x18 31. "RESERVED,Reserved" "0,1" bitfld.long 0x18 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED,Reserved" "0,1" bitfld.long 0x18 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED,Reserved" "0,1" bitfld.long 0x18 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED,Reserved" "0,1" bitfld.long 0x18 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED,Reserved" "0,1" bitfld.long 0x18 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED,Reserved" "0,1" bitfld.long 0x18 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED,Reserved" "0,1" bitfld.long 0x18 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED,Reserved" "0,1" bitfld.long 0x18 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x1C "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x1C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x20 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" rbitfld.long 0x20 31. "RESERVED," "0,1" bitfld.long 0x20 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 27. "RESERVED," "0,1" bitfld.long 0x20 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 23. "RESERVED," "0,1" bitfld.long 0x20 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 19. "RESERVED," "0,1" bitfld.long 0x20 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 15. "RESERVED," "0,1" bitfld.long 0x20 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 11. "RESERVED," "0,1" bitfld.long 0x20 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 7. "RESERVED," "0,1" bitfld.long 0x20 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 3. "RESERVED," "0,1" bitfld.long 0x20 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x280++0x07 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_QUEPRI,Queue Priority" hexmask.long 0x04 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" rgroup.long 0x300++0x23 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" newline bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" newline bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" newline bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" newline bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" newline bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" newline bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" newline bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" newline bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" newline bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" newline bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" newline bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" newline bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" newline bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" newline bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" newline bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" newline bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" newline bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" newline bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" newline bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" newline bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" line.long 0x08 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1" newline bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1" bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1" newline bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1" newline bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1" bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1" newline bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1" newline bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1" bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1" newline bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1" newline bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1" bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1" newline bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1" newline bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1" bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1" newline bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1" line.long 0x0C "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1" bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1" bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1" bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1" bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1" bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1" line.long 0x10 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,Event Missed #7" "0,1" newline bitfld.long 0x10 6. "E6,Event Missed #6" "0,1" bitfld.long 0x10 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x10 4. "E4,Event Missed #4" "0,1" bitfld.long 0x10 3. "E3,Event Missed #3" "0,1" newline bitfld.long 0x10 2. "E2,Event Missed #2" "0,1" bitfld.long 0x10 1. "E1,Event Missed #1" "0,1" newline bitfld.long 0x10 0. "E0,Event Missed #0" "0,1" line.long 0x14 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1" newline bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1" newline bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1" bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1" newline bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1" line.long 0x18 "EDMA_TPCC_CCERR,CC Error Register" hexmask.long.word 0x18 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 16. "TCERR,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register" "TCERR_0,TCERR_1" newline hexmask.long.byte 0x18 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD7_0,QTHRXCD7_1" newline bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD6_0,QTHRXCD6_1" bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD5_0,QTHRXCD5_1" newline bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD4_0,QTHRXCD4_1" bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD3_0,QTHRXCD3_1" newline bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD1_0,QTHRXCD1_1" newline bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x1C "EDMA_TPCC_CCERRCLR,CC Error Clear Register" hexmask.long.word 0x1C 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR" "0,1" newline hexmask.long.byte 0x1C 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect" "0,1" bitfld.long 0x1C 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect" "0,1" bitfld.long 0x1C 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" newline bitfld.long 0x1C 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect" "0,1" bitfld.long 0x1C 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" newline bitfld.long 0x1C 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect" "0,1" line.long 0x20 "EDMA_TPCC_EEVAL,Error Eval Register" hexmask.long 0x20 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 1. "SET,Error Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x20 0. "EVAL,Error Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x348++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x350++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x358++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x360++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x368++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x370++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x378++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x344++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x34C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x354++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x35C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x364++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x36C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x374++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x37C++0x23 line.long 0x00 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" line.long 0x04 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x04 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x04 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x04 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x04 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x04 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x04 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x04 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x08 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x08 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x08 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x08 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x08 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x08 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x08 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x08 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x0C "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x0C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x0C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x0C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x0C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x0C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x0C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x0C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x10 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x10 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x10 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x10 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x10 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x10 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x10 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x10 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x14 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x14 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x14 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x14 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x14 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x14 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x14 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x14 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x18 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x18 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x18 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x18 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x18 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x18 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x18 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x18 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x1C "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x1C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x1C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x1C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x1C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x1C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x1C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x1C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x20 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x20 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x20 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x20 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x20 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x20 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x20 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x20 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" rgroup.long 0x400++0x7F line.long 0x00 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x04 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x08 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x10 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x14 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x18 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x1C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x20 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x24 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x28 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x2C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x30 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x30 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x30 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x34 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x34 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x38 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x38 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x3C "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x3C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x40 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x40 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x44 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x44 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x44 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x48 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x48 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x48 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x4C "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x4C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x4C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x50 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x50 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x50 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x54 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x54 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x54 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x54 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x58 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x58 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x58 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x58 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x5C "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x5C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x5C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x5C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x60 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x60 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x60 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x60 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x64 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x64 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x64 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x64 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x68 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x68 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x68 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x68 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x6C "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x6C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x6C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x6C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x70 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x70 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x70 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x70 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x74 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x74 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x74 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x74 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x78 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x78 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x78 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x78 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x7C "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x7C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x7C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x7C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x600++0x07 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" line.long 0x04 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" hexmask.long.byte 0x04 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" rbitfld.long 0x00 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" rbitfld.long 0x04 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,reads return 0's" rbitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" newline rbitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" rbitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" newline rbitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" rbitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" newline bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2" rbitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" newline rbitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 14.--15. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" rbitfld.long 0x00 5.--7. "RESERVED,reads return 0's" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" rbitfld.long 0x00 3. "RESERVED,reads return 0's" "0,1" newline bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.." rbitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" newline rbitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" group.long 0x700++0x0B line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" hexmask.long.tbyte 0x00 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" line.long 0x08 "EDMA_TPCC_AETCMD,AET Command" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "CLR,AET Clear commandCPU writes 0x0 has no effect" "0,1" rgroup.long 0x800++0x2F line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" line.long 0x04 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" newline rbitfld.long 0x04 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" rbitfld.long 0x04 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" newline rbitfld.long 0x04 2. "URE,User Read Error" "URE_0,URE_1" rbitfld.long 0x04 1. "UWE,User Write Error" "UWE_0,UWE_1" newline rbitfld.long 0x04 0. "UXE,User Execute Error" "UXE_0,UXE_1" line.long 0x08 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" line.long 0x0C "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x0C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x0C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x0C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x0C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x0C 10. "AID0,Allowed ID 0" "AID0_0,AID0_1" bitfld.long 0x0C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x0C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x0C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x0C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x0C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x0C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x0C 0. "UX,User Execute permission" "UX_0,UX_1" line.long 0x10 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x10 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x10 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x10 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x10 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x10 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x10 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x10 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x10 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x10 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x10 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x10 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x10 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x10 0. "UX,User Execute permission" "UX_0,?" line.long 0x14 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x14 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x14 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x14 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x14 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x14 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x14 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x14 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x14 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x14 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x14 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x14 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x14 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x14 0. "UX,User Execute permission" "UX_0,?" line.long 0x18 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x18 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x18 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x18 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x18 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x18 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x18 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x18 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x18 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x18 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x18 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x18 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x18 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x18 0. "UX,User Execute permission" "UX_0,?" line.long 0x1C "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x1C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x1C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x1C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x1C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x1C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x1C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x1C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x1C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x1C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x1C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x1C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x1C 0. "UX,User Execute permission" "UX_0,?" line.long 0x20 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x20 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x20 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x20 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x20 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x20 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x20 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x20 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x20 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x20 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x20 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x20 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x20 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x20 0. "UX,User Execute permission" "UX_0,?" line.long 0x24 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x24 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x24 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x24 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x24 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x24 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x24 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x24 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x24 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x24 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x24 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x24 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x24 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x24 0. "UX,User Execute permission" "UX_0,?" line.long 0x28 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" hexmask.long.word 0x28 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x28 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x28 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x28 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x28 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x28 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x28 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x28 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x28 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x28 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x28 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x28 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x28 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x28 0. "UX,User Execute permission" "UX_0,?" line.long 0x2C "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" hexmask.long.word 0x2C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x2C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x2C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x2C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x2C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x2C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x2C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x2C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x2C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x2C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x2C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x2C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x2C 0. "UX,User Execute permission" "UX_0,?" rgroup.long 0x1000++0x47 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" newline bitfld.long 0x04 29. "E61,Event #61" "0,1" bitfld.long 0x04 28. "E60,Event #60" "0,1" newline bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" newline bitfld.long 0x04 23. "E55,Event #55" "0,1" bitfld.long 0x04 22. "E54,Event #54" "0,1" newline bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" newline bitfld.long 0x04 17. "E49,Event #49" "0,1" bitfld.long 0x04 16. "E48,Event #48" "0,1" newline bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" newline bitfld.long 0x04 11. "E43,Event #43" "0,1" bitfld.long 0x04 10. "E42,Event #42" "0,1" newline bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" newline bitfld.long 0x04 5. "E37,Event #37" "0,1" bitfld.long 0x04 4. "E36,Event #36" "0,1" newline bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" line.long 0x08 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event #31" "0,1" bitfld.long 0x08 30. "E30,Event #30" "0,1" newline bitfld.long 0x08 29. "E29,Event #29" "0,1" bitfld.long 0x08 28. "E28,Event #28" "0,1" newline bitfld.long 0x08 27. "E27,Event #27" "0,1" bitfld.long 0x08 26. "E26,Event #26" "0,1" newline bitfld.long 0x08 25. "E25,Event #25" "0,1" bitfld.long 0x08 24. "E24,Event #24" "0,1" newline bitfld.long 0x08 23. "E23,Event #23" "0,1" bitfld.long 0x08 22. "E22,Event #22" "0,1" newline bitfld.long 0x08 21. "E21,Event #21" "0,1" bitfld.long 0x08 20. "E20,Event #20" "0,1" newline bitfld.long 0x08 19. "E19,Event #19" "0,1" bitfld.long 0x08 18. "E18,Event #18" "0,1" newline bitfld.long 0x08 17. "E17,Event #17" "0,1" bitfld.long 0x08 16. "E16,Event #16" "0,1" newline bitfld.long 0x08 15. "E15,Event #15" "0,1" bitfld.long 0x08 14. "E14,Event #14" "0,1" newline bitfld.long 0x08 13. "E13,Event #13" "0,1" bitfld.long 0x08 12. "E12,Event #12" "0,1" newline bitfld.long 0x08 11. "E11,Event #11" "0,1" bitfld.long 0x08 10. "E10,Event #10" "0,1" newline bitfld.long 0x08 9. "E9,Event #9" "0,1" bitfld.long 0x08 8. "E8,Event #8" "0,1" newline bitfld.long 0x08 7. "E7,Event #7" "0,1" bitfld.long 0x08 6. "E6,Event #6" "0,1" newline bitfld.long 0x08 5. "E5,Event #5" "0,1" bitfld.long 0x08 4. "E4,Event #4" "0,1" newline bitfld.long 0x08 3. "E3,Event #3" "0,1" bitfld.long 0x08 2. "E2,Event #2" "0,1" newline bitfld.long 0x08 1. "E1,Event #1" "0,1" bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event #63" "0,1" bitfld.long 0x0C 30. "E62,Event #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event #61" "0,1" bitfld.long 0x0C 28. "E60,Event #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event #59" "0,1" bitfld.long 0x0C 26. "E58,Event #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event #57" "0,1" bitfld.long 0x0C 24. "E56,Event #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event #55" "0,1" bitfld.long 0x0C 22. "E54,Event #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event #53" "0,1" bitfld.long 0x0C 20. "E52,Event #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event #51" "0,1" bitfld.long 0x0C 18. "E50,Event #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event #49" "0,1" bitfld.long 0x0C 16. "E48,Event #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event #47" "0,1" bitfld.long 0x0C 14. "E46,Event #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event #45" "0,1" bitfld.long 0x0C 12. "E44,Event #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event #43" "0,1" bitfld.long 0x0C 10. "E42,Event #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event #41" "0,1" bitfld.long 0x0C 8. "E40,Event #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event #39" "0,1" bitfld.long 0x0C 6. "E38,Event #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event #37" "0,1" bitfld.long 0x0C 4. "E36,Event #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event #35" "0,1" bitfld.long 0x0C 2. "E34,Event #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event #33" "0,1" bitfld.long 0x0C 0. "E32,Event #32" "0,1" line.long 0x10 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x10 31. "E31,Event #31" "0,1" bitfld.long 0x10 30. "E30,Event #30" "0,1" newline bitfld.long 0x10 29. "E29,Event #29" "0,1" bitfld.long 0x10 28. "E28,Event #28" "0,1" newline bitfld.long 0x10 27. "E27,Event #27" "0,1" bitfld.long 0x10 26. "E26,Event #26" "0,1" newline bitfld.long 0x10 25. "E25,Event #25" "0,1" bitfld.long 0x10 24. "E24,Event #24" "0,1" newline bitfld.long 0x10 23. "E23,Event #23" "0,1" bitfld.long 0x10 22. "E22,Event #22" "0,1" newline bitfld.long 0x10 21. "E21,Event #21" "0,1" bitfld.long 0x10 20. "E20,Event #20" "0,1" newline bitfld.long 0x10 19. "E19,Event #19" "0,1" bitfld.long 0x10 18. "E18,Event #18" "0,1" newline bitfld.long 0x10 17. "E17,Event #17" "0,1" bitfld.long 0x10 16. "E16,Event #16" "0,1" newline bitfld.long 0x10 15. "E15,Event #15" "0,1" bitfld.long 0x10 14. "E14,Event #14" "0,1" newline bitfld.long 0x10 13. "E13,Event #13" "0,1" bitfld.long 0x10 12. "E12,Event #12" "0,1" newline bitfld.long 0x10 11. "E11,Event #11" "0,1" bitfld.long 0x10 10. "E10,Event #10" "0,1" newline bitfld.long 0x10 9. "E9,Event #9" "0,1" bitfld.long 0x10 8. "E8,Event #8" "0,1" newline bitfld.long 0x10 7. "E7,Event #7" "0,1" bitfld.long 0x10 6. "E6,Event #6" "0,1" newline bitfld.long 0x10 5. "E5,Event #5" "0,1" bitfld.long 0x10 4. "E4,Event #4" "0,1" newline bitfld.long 0x10 3. "E3,Event #3" "0,1" bitfld.long 0x10 2. "E2,Event #2" "0,1" newline bitfld.long 0x10 1. "E1,Event #1" "0,1" bitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x14 31. "E63,Event #63" "0,1" bitfld.long 0x14 30. "E62,Event #62" "0,1" newline bitfld.long 0x14 29. "E61,Event #61" "0,1" bitfld.long 0x14 28. "E60,Event #60" "0,1" newline bitfld.long 0x14 27. "E59,Event #59" "0,1" bitfld.long 0x14 26. "E58,Event #58" "0,1" newline bitfld.long 0x14 25. "E57,Event #57" "0,1" bitfld.long 0x14 24. "E56,Event #56" "0,1" newline bitfld.long 0x14 23. "E55,Event #55" "0,1" bitfld.long 0x14 22. "E54,Event #54" "0,1" newline bitfld.long 0x14 21. "E53,Event #53" "0,1" bitfld.long 0x14 20. "E52,Event #52" "0,1" newline bitfld.long 0x14 19. "E51,Event #51" "0,1" bitfld.long 0x14 18. "E50,Event #50" "0,1" newline bitfld.long 0x14 17. "E49,Event #49" "0,1" bitfld.long 0x14 16. "E48,Event #48" "0,1" newline bitfld.long 0x14 15. "E47,Event #47" "0,1" bitfld.long 0x14 14. "E46,Event #46" "0,1" newline bitfld.long 0x14 13. "E45,Event #45" "0,1" bitfld.long 0x14 12. "E44,Event #44" "0,1" newline bitfld.long 0x14 11. "E43,Event #43" "0,1" bitfld.long 0x14 10. "E42,Event #42" "0,1" newline bitfld.long 0x14 9. "E41,Event #41" "0,1" bitfld.long 0x14 8. "E40,Event #40" "0,1" newline bitfld.long 0x14 7. "E39,Event #39" "0,1" bitfld.long 0x14 6. "E38,Event #38" "0,1" newline bitfld.long 0x14 5. "E37,Event #37" "0,1" bitfld.long 0x14 4. "E36,Event #36" "0,1" newline bitfld.long 0x14 3. "E35,Event #35" "0,1" bitfld.long 0x14 2. "E34,Event #34" "0,1" newline bitfld.long 0x14 1. "E33,Event #33" "0,1" bitfld.long 0x14 0. "E32,Event #32" "0,1" line.long 0x18 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x18 31. "E31,Event #31" "0,1" bitfld.long 0x18 30. "E30,Event #30" "0,1" newline bitfld.long 0x18 29. "E29,Event #29" "0,1" bitfld.long 0x18 28. "E28,Event #28" "0,1" newline bitfld.long 0x18 27. "E27,Event #27" "0,1" bitfld.long 0x18 26. "E26,Event #26" "0,1" newline bitfld.long 0x18 25. "E25,Event #25" "0,1" bitfld.long 0x18 24. "E24,Event #24" "0,1" newline bitfld.long 0x18 23. "E23,Event #23" "0,1" bitfld.long 0x18 22. "E22,Event #22" "0,1" newline bitfld.long 0x18 21. "E21,Event #21" "0,1" bitfld.long 0x18 20. "E20,Event #20" "0,1" newline bitfld.long 0x18 19. "E19,Event #19" "0,1" bitfld.long 0x18 18. "E18,Event #18" "0,1" newline bitfld.long 0x18 17. "E17,Event #17" "0,1" bitfld.long 0x18 16. "E16,Event #16" "0,1" newline bitfld.long 0x18 15. "E15,Event #15" "0,1" bitfld.long 0x18 14. "E14,Event #14" "0,1" newline bitfld.long 0x18 13. "E13,Event #13" "0,1" bitfld.long 0x18 12. "E12,Event #12" "0,1" newline bitfld.long 0x18 11. "E11,Event #11" "0,1" bitfld.long 0x18 10. "E10,Event #10" "0,1" newline bitfld.long 0x18 9. "E9,Event #9" "0,1" bitfld.long 0x18 8. "E8,Event #8" "0,1" newline bitfld.long 0x18 7. "E7,Event #7" "0,1" bitfld.long 0x18 6. "E6,Event #6" "0,1" newline bitfld.long 0x18 5. "E5,Event #5" "0,1" bitfld.long 0x18 4. "E4,Event #4" "0,1" newline bitfld.long 0x18 3. "E3,Event #3" "0,1" bitfld.long 0x18 2. "E2,Event #2" "0,1" newline bitfld.long 0x18 1. "E1,Event #1" "0,1" bitfld.long 0x18 0. "E0,Event #0" "0,1" line.long 0x1C "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x1C 31. "E63,Event #63" "0,1" bitfld.long 0x1C 30. "E62,Event #62" "0,1" newline bitfld.long 0x1C 29. "E61,Event #61" "0,1" bitfld.long 0x1C 28. "E60,Event #60" "0,1" newline bitfld.long 0x1C 27. "E59,Event #59" "0,1" bitfld.long 0x1C 26. "E58,Event #58" "0,1" newline bitfld.long 0x1C 25. "E57,Event #57" "0,1" bitfld.long 0x1C 24. "E56,Event #56" "0,1" newline bitfld.long 0x1C 23. "E55,Event #55" "0,1" bitfld.long 0x1C 22. "E54,Event #54" "0,1" newline bitfld.long 0x1C 21. "E53,Event #53" "0,1" bitfld.long 0x1C 20. "E52,Event #52" "0,1" newline bitfld.long 0x1C 19. "E51,Event #51" "0,1" bitfld.long 0x1C 18. "E50,Event #50" "0,1" newline bitfld.long 0x1C 17. "E49,Event #49" "0,1" bitfld.long 0x1C 16. "E48,Event #48" "0,1" newline bitfld.long 0x1C 15. "E47,Event #47" "0,1" bitfld.long 0x1C 14. "E46,Event #46" "0,1" newline bitfld.long 0x1C 13. "E45,Event #45" "0,1" bitfld.long 0x1C 12. "E44,Event #44" "0,1" newline bitfld.long 0x1C 11. "E43,Event #43" "0,1" bitfld.long 0x1C 10. "E42,Event #42" "0,1" newline bitfld.long 0x1C 9. "E41,Event #41" "0,1" bitfld.long 0x1C 8. "E40,Event #40" "0,1" newline bitfld.long 0x1C 7. "E39,Event #39" "0,1" bitfld.long 0x1C 6. "E38,Event #38" "0,1" newline bitfld.long 0x1C 5. "E37,Event #37" "0,1" bitfld.long 0x1C 4. "E36,Event #36" "0,1" newline bitfld.long 0x1C 3. "E35,Event #35" "0,1" bitfld.long 0x1C 2. "E34,Event #34" "0,1" newline bitfld.long 0x1C 1. "E33,Event #33" "0,1" bitfld.long 0x1C 0. "E32,Event #32" "0,1" line.long 0x20 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x20 31. "E31,Event #31" "0,1" bitfld.long 0x20 30. "E30,Event #30" "0,1" newline bitfld.long 0x20 29. "E29,Event #29" "0,1" bitfld.long 0x20 28. "E28,Event #28" "0,1" newline bitfld.long 0x20 27. "E27,Event #27" "0,1" bitfld.long 0x20 26. "E26,Event #26" "0,1" newline bitfld.long 0x20 25. "E25,Event #25" "0,1" bitfld.long 0x20 24. "E24,Event #24" "0,1" newline bitfld.long 0x20 23. "E23,Event #23" "0,1" bitfld.long 0x20 22. "E22,Event #22" "0,1" newline bitfld.long 0x20 21. "E21,Event #21" "0,1" bitfld.long 0x20 20. "E20,Event #20" "0,1" newline bitfld.long 0x20 19. "E19,Event #19" "0,1" bitfld.long 0x20 18. "E18,Event #18" "0,1" newline bitfld.long 0x20 17. "E17,Event #17" "0,1" bitfld.long 0x20 16. "E16,Event #16" "0,1" newline bitfld.long 0x20 15. "E15,Event #15" "0,1" bitfld.long 0x20 14. "E14,Event #14" "0,1" newline bitfld.long 0x20 13. "E13,Event #13" "0,1" bitfld.long 0x20 12. "E12,Event #12" "0,1" newline bitfld.long 0x20 11. "E11,Event #11" "0,1" bitfld.long 0x20 10. "E10,Event #10" "0,1" newline bitfld.long 0x20 9. "E9,Event #9" "0,1" bitfld.long 0x20 8. "E8,Event #8" "0,1" newline bitfld.long 0x20 7. "E7,Event #7" "0,1" bitfld.long 0x20 6. "E6,Event #6" "0,1" newline bitfld.long 0x20 5. "E5,Event #5" "0,1" bitfld.long 0x20 4. "E4,Event #4" "0,1" newline bitfld.long 0x20 3. "E3,Event #3" "0,1" bitfld.long 0x20 2. "E2,Event #2" "0,1" newline bitfld.long 0x20 1. "E1,Event #1" "0,1" bitfld.long 0x20 0. "E0,Event #0" "0,1" line.long 0x24 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x24 31. "E63,Event #63" "0,1" bitfld.long 0x24 30. "E62,Event #62" "0,1" newline bitfld.long 0x24 29. "E61,Event #61" "0,1" bitfld.long 0x24 28. "E60,Event #60" "0,1" newline bitfld.long 0x24 27. "E59,Event #59" "0,1" bitfld.long 0x24 26. "E58,Event #58" "0,1" newline bitfld.long 0x24 25. "E57,Event #57" "0,1" bitfld.long 0x24 24. "E56,Event #56" "0,1" newline bitfld.long 0x24 23. "E55,Event #55" "0,1" bitfld.long 0x24 22. "E54,Event #54" "0,1" newline bitfld.long 0x24 21. "E53,Event #53" "0,1" bitfld.long 0x24 20. "E52,Event #52" "0,1" newline bitfld.long 0x24 19. "E51,Event #51" "0,1" bitfld.long 0x24 18. "E50,Event #50" "0,1" newline bitfld.long 0x24 17. "E49,Event #49" "0,1" bitfld.long 0x24 16. "E48,Event #48" "0,1" newline bitfld.long 0x24 15. "E47,Event #47" "0,1" bitfld.long 0x24 14. "E46,Event #46" "0,1" newline bitfld.long 0x24 13. "E45,Event #45" "0,1" bitfld.long 0x24 12. "E44,Event #44" "0,1" newline bitfld.long 0x24 11. "E43,Event #43" "0,1" bitfld.long 0x24 10. "E42,Event #42" "0,1" newline bitfld.long 0x24 9. "E41,Event #41" "0,1" bitfld.long 0x24 8. "E40,Event #40" "0,1" newline bitfld.long 0x24 7. "E39,Event #39" "0,1" bitfld.long 0x24 6. "E38,Event #38" "0,1" newline bitfld.long 0x24 5. "E37,Event #37" "0,1" bitfld.long 0x24 4. "E36,Event #36" "0,1" newline bitfld.long 0x24 3. "E35,Event #35" "0,1" bitfld.long 0x24 2. "E34,Event #34" "0,1" newline bitfld.long 0x24 1. "E33,Event #33" "0,1" bitfld.long 0x24 0. "E32,Event #32" "0,1" line.long 0x28 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x28 31. "E31,Event #31" "0,1" bitfld.long 0x28 30. "E30,Event #30" "0,1" newline bitfld.long 0x28 29. "E29,Event #29" "0,1" bitfld.long 0x28 28. "E28,Event #28" "0,1" newline bitfld.long 0x28 27. "E27,Event #27" "0,1" bitfld.long 0x28 26. "E26,Event #26" "0,1" newline bitfld.long 0x28 25. "E25,Event #25" "0,1" bitfld.long 0x28 24. "E24,Event #24" "0,1" newline bitfld.long 0x28 23. "E23,Event #23" "0,1" bitfld.long 0x28 22. "E22,Event #22" "0,1" newline bitfld.long 0x28 21. "E21,Event #21" "0,1" bitfld.long 0x28 20. "E20,Event #20" "0,1" newline bitfld.long 0x28 19. "E19,Event #19" "0,1" bitfld.long 0x28 18. "E18,Event #18" "0,1" newline bitfld.long 0x28 17. "E17,Event #17" "0,1" bitfld.long 0x28 16. "E16,Event #16" "0,1" newline bitfld.long 0x28 15. "E15,Event #15" "0,1" bitfld.long 0x28 14. "E14,Event #14" "0,1" newline bitfld.long 0x28 13. "E13,Event #13" "0,1" bitfld.long 0x28 12. "E12,Event #12" "0,1" newline bitfld.long 0x28 11. "E11,Event #11" "0,1" bitfld.long 0x28 10. "E10,Event #10" "0,1" newline bitfld.long 0x28 9. "E9,Event #9" "0,1" bitfld.long 0x28 8. "E8,Event #8" "0,1" newline bitfld.long 0x28 7. "E7,Event #7" "0,1" bitfld.long 0x28 6. "E6,Event #6" "0,1" newline bitfld.long 0x28 5. "E5,Event #5" "0,1" bitfld.long 0x28 4. "E4,Event #4" "0,1" newline bitfld.long 0x28 3. "E3,Event #3" "0,1" bitfld.long 0x28 2. "E2,Event #2" "0,1" newline bitfld.long 0x28 1. "E1,Event #1" "0,1" bitfld.long 0x28 0. "E0,Event #0" "0,1" line.long 0x2C "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x2C 31. "E63,Event #63" "0,1" bitfld.long 0x2C 30. "E62,Event #62" "0,1" newline bitfld.long 0x2C 29. "E61,Event #61" "0,1" bitfld.long 0x2C 28. "E60,Event #60" "0,1" newline bitfld.long 0x2C 27. "E59,Event #59" "0,1" bitfld.long 0x2C 26. "E58,Event #58" "0,1" newline bitfld.long 0x2C 25. "E57,Event #57" "0,1" bitfld.long 0x2C 24. "E56,Event #56" "0,1" newline bitfld.long 0x2C 23. "E55,Event #55" "0,1" bitfld.long 0x2C 22. "E54,Event #54" "0,1" newline bitfld.long 0x2C 21. "E53,Event #53" "0,1" bitfld.long 0x2C 20. "E52,Event #52" "0,1" newline bitfld.long 0x2C 19. "E51,Event #51" "0,1" bitfld.long 0x2C 18. "E50,Event #50" "0,1" newline bitfld.long 0x2C 17. "E49,Event #49" "0,1" bitfld.long 0x2C 16. "E48,Event #48" "0,1" newline bitfld.long 0x2C 15. "E47,Event #47" "0,1" bitfld.long 0x2C 14. "E46,Event #46" "0,1" newline bitfld.long 0x2C 13. "E45,Event #45" "0,1" bitfld.long 0x2C 12. "E44,Event #44" "0,1" newline bitfld.long 0x2C 11. "E43,Event #43" "0,1" bitfld.long 0x2C 10. "E42,Event #42" "0,1" newline bitfld.long 0x2C 9. "E41,Event #41" "0,1" bitfld.long 0x2C 8. "E40,Event #40" "0,1" newline bitfld.long 0x2C 7. "E39,Event #39" "0,1" bitfld.long 0x2C 6. "E38,Event #38" "0,1" newline bitfld.long 0x2C 5. "E37,Event #37" "0,1" bitfld.long 0x2C 4. "E36,Event #36" "0,1" newline bitfld.long 0x2C 3. "E35,Event #35" "0,1" bitfld.long 0x2C 2. "E34,Event #34" "0,1" newline bitfld.long 0x2C 1. "E33,Event #33" "0,1" bitfld.long 0x2C 0. "E32,Event #32" "0,1" line.long 0x30 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x30 31. "E31,Event #31" "0,1" bitfld.long 0x30 30. "E30,Event #30" "0,1" newline bitfld.long 0x30 29. "E29,Event #29" "0,1" bitfld.long 0x30 28. "E28,Event #28" "0,1" newline bitfld.long 0x30 27. "E27,Event #27" "0,1" bitfld.long 0x30 26. "E26,Event #26" "0,1" newline bitfld.long 0x30 25. "E25,Event #25" "0,1" bitfld.long 0x30 24. "E24,Event #24" "0,1" newline bitfld.long 0x30 23. "E23,Event #23" "0,1" bitfld.long 0x30 22. "E22,Event #22" "0,1" newline bitfld.long 0x30 21. "E21,Event #21" "0,1" bitfld.long 0x30 20. "E20,Event #20" "0,1" newline bitfld.long 0x30 19. "E19,Event #19" "0,1" bitfld.long 0x30 18. "E18,Event #18" "0,1" newline bitfld.long 0x30 17. "E17,Event #17" "0,1" bitfld.long 0x30 16. "E16,Event #16" "0,1" newline bitfld.long 0x30 15. "E15,Event #15" "0,1" bitfld.long 0x30 14. "E14,Event #14" "0,1" newline bitfld.long 0x30 13. "E13,Event #13" "0,1" bitfld.long 0x30 12. "E12,Event #12" "0,1" newline bitfld.long 0x30 11. "E11,Event #11" "0,1" bitfld.long 0x30 10. "E10,Event #10" "0,1" newline bitfld.long 0x30 9. "E9,Event #9" "0,1" bitfld.long 0x30 8. "E8,Event #8" "0,1" newline bitfld.long 0x30 7. "E7,Event #7" "0,1" bitfld.long 0x30 6. "E6,Event #6" "0,1" newline bitfld.long 0x30 5. "E5,Event #5" "0,1" bitfld.long 0x30 4. "E4,Event #4" "0,1" newline bitfld.long 0x30 3. "E3,Event #3" "0,1" bitfld.long 0x30 2. "E2,Event #2" "0,1" newline bitfld.long 0x30 1. "E1,Event #1" "0,1" bitfld.long 0x30 0. "E0,Event #0" "0,1" line.long 0x34 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x34 31. "E63,Event #63" "0,1" bitfld.long 0x34 30. "E62,Event #62" "0,1" newline bitfld.long 0x34 29. "E61,Event #61" "0,1" bitfld.long 0x34 28. "E60,Event #60" "0,1" newline bitfld.long 0x34 27. "E59,Event #59" "0,1" bitfld.long 0x34 26. "E58,Event #58" "0,1" newline bitfld.long 0x34 25. "E57,Event #57" "0,1" bitfld.long 0x34 24. "E56,Event #56" "0,1" newline bitfld.long 0x34 23. "E55,Event #55" "0,1" bitfld.long 0x34 22. "E54,Event #54" "0,1" newline bitfld.long 0x34 21. "E53,Event #53" "0,1" bitfld.long 0x34 20. "E52,Event #52" "0,1" newline bitfld.long 0x34 19. "E51,Event #51" "0,1" bitfld.long 0x34 18. "E50,Event #50" "0,1" newline bitfld.long 0x34 17. "E49,Event #49" "0,1" bitfld.long 0x34 16. "E48,Event #48" "0,1" newline bitfld.long 0x34 15. "E47,Event #47" "0,1" bitfld.long 0x34 14. "E46,Event #46" "0,1" newline bitfld.long 0x34 13. "E45,Event #45" "0,1" bitfld.long 0x34 12. "E44,Event #44" "0,1" newline bitfld.long 0x34 11. "E43,Event #43" "0,1" bitfld.long 0x34 10. "E42,Event #42" "0,1" newline bitfld.long 0x34 9. "E41,Event #41" "0,1" bitfld.long 0x34 8. "E40,Event #40" "0,1" newline bitfld.long 0x34 7. "E39,Event #39" "0,1" bitfld.long 0x34 6. "E38,Event #38" "0,1" newline bitfld.long 0x34 5. "E37,Event #37" "0,1" bitfld.long 0x34 4. "E36,Event #36" "0,1" newline bitfld.long 0x34 3. "E35,Event #35" "0,1" bitfld.long 0x34 2. "E34,Event #34" "0,1" newline bitfld.long 0x34 1. "E33,Event #33" "0,1" bitfld.long 0x34 0. "E32,Event #32" "0,1" line.long 0x38 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x38 31. "E31,Event #31" "0,1" bitfld.long 0x38 30. "E30,Event #30" "0,1" newline bitfld.long 0x38 29. "E29,Event #29" "0,1" bitfld.long 0x38 28. "E28,Event #28" "0,1" newline bitfld.long 0x38 27. "E27,Event #27" "0,1" bitfld.long 0x38 26. "E26,Event #26" "0,1" newline bitfld.long 0x38 25. "E25,Event #25" "0,1" bitfld.long 0x38 24. "E24,Event #24" "0,1" newline bitfld.long 0x38 23. "E23,Event #23" "0,1" bitfld.long 0x38 22. "E22,Event #22" "0,1" newline bitfld.long 0x38 21. "E21,Event #21" "0,1" bitfld.long 0x38 20. "E20,Event #20" "0,1" newline bitfld.long 0x38 19. "E19,Event #19" "0,1" bitfld.long 0x38 18. "E18,Event #18" "0,1" newline bitfld.long 0x38 17. "E17,Event #17" "0,1" bitfld.long 0x38 16. "E16,Event #16" "0,1" newline bitfld.long 0x38 15. "E15,Event #15" "0,1" bitfld.long 0x38 14. "E14,Event #14" "0,1" newline bitfld.long 0x38 13. "E13,Event #13" "0,1" bitfld.long 0x38 12. "E12,Event #12" "0,1" newline bitfld.long 0x38 11. "E11,Event #11" "0,1" bitfld.long 0x38 10. "E10,Event #10" "0,1" newline bitfld.long 0x38 9. "E9,Event #9" "0,1" bitfld.long 0x38 8. "E8,Event #8" "0,1" newline bitfld.long 0x38 7. "E7,Event #7" "0,1" bitfld.long 0x38 6. "E6,Event #6" "0,1" newline bitfld.long 0x38 5. "E5,Event #5" "0,1" bitfld.long 0x38 4. "E4,Event #4" "0,1" newline bitfld.long 0x38 3. "E3,Event #3" "0,1" bitfld.long 0x38 2. "E2,Event #2" "0,1" newline bitfld.long 0x38 1. "E1,Event #1" "0,1" bitfld.long 0x38 0. "E0,Event #0" "0,1" line.long 0x3C "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x3C 31. "E63,Event #63" "0,1" bitfld.long 0x3C 30. "E62,Event #62" "0,1" newline bitfld.long 0x3C 29. "E61,Event #61" "0,1" bitfld.long 0x3C 28. "E60,Event #60" "0,1" newline bitfld.long 0x3C 27. "E59,Event #59" "0,1" bitfld.long 0x3C 26. "E58,Event #58" "0,1" newline bitfld.long 0x3C 25. "E57,Event #57" "0,1" bitfld.long 0x3C 24. "E56,Event #56" "0,1" newline bitfld.long 0x3C 23. "E55,Event #55" "0,1" bitfld.long 0x3C 22. "E54,Event #54" "0,1" newline bitfld.long 0x3C 21. "E53,Event #53" "0,1" bitfld.long 0x3C 20. "E52,Event #52" "0,1" newline bitfld.long 0x3C 19. "E51,Event #51" "0,1" bitfld.long 0x3C 18. "E50,Event #50" "0,1" newline bitfld.long 0x3C 17. "E49,Event #49" "0,1" bitfld.long 0x3C 16. "E48,Event #48" "0,1" newline bitfld.long 0x3C 15. "E47,Event #47" "0,1" bitfld.long 0x3C 14. "E46,Event #46" "0,1" newline bitfld.long 0x3C 13. "E45,Event #45" "0,1" bitfld.long 0x3C 12. "E44,Event #44" "0,1" newline bitfld.long 0x3C 11. "E43,Event #43" "0,1" bitfld.long 0x3C 10. "E42,Event #42" "0,1" newline bitfld.long 0x3C 9. "E41,Event #41" "0,1" bitfld.long 0x3C 8. "E40,Event #40" "0,1" newline bitfld.long 0x3C 7. "E39,Event #39" "0,1" bitfld.long 0x3C 6. "E38,Event #38" "0,1" newline bitfld.long 0x3C 5. "E37,Event #37" "0,1" bitfld.long 0x3C 4. "E36,Event #36" "0,1" newline bitfld.long 0x3C 3. "E35,Event #35" "0,1" bitfld.long 0x3C 2. "E34,Event #34" "0,1" newline bitfld.long 0x3C 1. "E33,Event #33" "0,1" bitfld.long 0x3C 0. "E32,Event #32" "0,1" line.long 0x40 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x40 31. "E31,Event #31" "0,1" bitfld.long 0x40 30. "E30,Event #30" "0,1" newline bitfld.long 0x40 29. "E29,Event #29" "0,1" bitfld.long 0x40 28. "E28,Event #28" "0,1" newline bitfld.long 0x40 27. "E27,Event #27" "0,1" bitfld.long 0x40 26. "E26,Event #26" "0,1" newline bitfld.long 0x40 25. "E25,Event #25" "0,1" bitfld.long 0x40 24. "E24,Event #24" "0,1" newline bitfld.long 0x40 23. "E23,Event #23" "0,1" bitfld.long 0x40 22. "E22,Event #22" "0,1" newline bitfld.long 0x40 21. "E21,Event #21" "0,1" bitfld.long 0x40 20. "E20,Event #20" "0,1" newline bitfld.long 0x40 19. "E19,Event #19" "0,1" bitfld.long 0x40 18. "E18,Event #18" "0,1" newline bitfld.long 0x40 17. "E17,Event #17" "0,1" bitfld.long 0x40 16. "E16,Event #16" "0,1" newline bitfld.long 0x40 15. "E15,Event #15" "0,1" bitfld.long 0x40 14. "E14,Event #14" "0,1" newline bitfld.long 0x40 13. "E13,Event #13" "0,1" bitfld.long 0x40 12. "E12,Event #12" "0,1" newline bitfld.long 0x40 11. "E11,Event #11" "0,1" bitfld.long 0x40 10. "E10,Event #10" "0,1" newline bitfld.long 0x40 9. "E9,Event #9" "0,1" bitfld.long 0x40 8. "E8,Event #8" "0,1" newline bitfld.long 0x40 7. "E7,Event #7" "0,1" bitfld.long 0x40 6. "E6,Event #6" "0,1" newline bitfld.long 0x40 5. "E5,Event #5" "0,1" bitfld.long 0x40 4. "E4,Event #4" "0,1" newline bitfld.long 0x40 3. "E3,Event #3" "0,1" bitfld.long 0x40 2. "E2,Event #2" "0,1" newline bitfld.long 0x40 1. "E1,Event #1" "0,1" bitfld.long 0x40 0. "E0,Event #0" "0,1" line.long 0x44 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x44 31. "E63,Event #63" "0,1" bitfld.long 0x44 30. "E62,Event #62" "0,1" newline bitfld.long 0x44 29. "E61,Event #61" "0,1" bitfld.long 0x44 28. "E60,Event #60" "0,1" newline bitfld.long 0x44 27. "E59,Event #59" "0,1" bitfld.long 0x44 26. "E58,Event #58" "0,1" newline bitfld.long 0x44 25. "E57,Event #57" "0,1" bitfld.long 0x44 24. "E56,Event #56" "0,1" newline bitfld.long 0x44 23. "E55,Event #55" "0,1" bitfld.long 0x44 22. "E54,Event #54" "0,1" newline bitfld.long 0x44 21. "E53,Event #53" "0,1" bitfld.long 0x44 20. "E52,Event #52" "0,1" newline bitfld.long 0x44 19. "E51,Event #51" "0,1" bitfld.long 0x44 18. "E50,Event #50" "0,1" newline bitfld.long 0x44 17. "E49,Event #49" "0,1" bitfld.long 0x44 16. "E48,Event #48" "0,1" newline bitfld.long 0x44 15. "E47,Event #47" "0,1" bitfld.long 0x44 14. "E46,Event #46" "0,1" newline bitfld.long 0x44 13. "E45,Event #45" "0,1" bitfld.long 0x44 12. "E44,Event #44" "0,1" newline bitfld.long 0x44 11. "E43,Event #43" "0,1" bitfld.long 0x44 10. "E42,Event #42" "0,1" newline bitfld.long 0x44 9. "E41,Event #41" "0,1" bitfld.long 0x44 8. "E40,Event #40" "0,1" newline bitfld.long 0x44 7. "E39,Event #39" "0,1" bitfld.long 0x44 6. "E38,Event #38" "0,1" newline bitfld.long 0x44 5. "E37,Event #37" "0,1" bitfld.long 0x44 4. "E36,Event #36" "0,1" newline bitfld.long 0x44 3. "E35,Event #35" "0,1" bitfld.long 0x44 2. "E34,Event #34" "0,1" newline bitfld.long 0x44 1. "E33,Event #33" "0,1" bitfld.long 0x44 0. "E32,Event #32" "0,1" rgroup.long 0x1050++0x2B line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x08 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x0C "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x10 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x14 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x18 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x1C "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x20 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x24 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x28 "EDMA_TPCC_IEVAL,Interrupt Eval Register" hexmask.long 0x28 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" newline bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1080++0x17 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 7. "E7,Event #7" "0,1" newline rbitfld.long 0x04 6. "E6,Event #6" "0,1" rbitfld.long 0x04 5. "E5,Event #5" "0,1" newline rbitfld.long 0x04 4. "E4,Event #4" "0,1" rbitfld.long 0x04 3. "E3,Event #3" "0,1" newline rbitfld.long 0x04 2. "E2,Event #2" "0,1" rbitfld.long 0x04 1. "E1,Event #1" "0,1" newline rbitfld.long 0x04 0. "E0,Event #0" "0,1" line.long 0x08 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,Event #7" "0,1" newline bitfld.long 0x08 6. "E6,Event #6" "0,1" bitfld.long 0x08 5. "E5,Event #5" "0,1" newline bitfld.long 0x08 4. "E4,Event #4" "0,1" bitfld.long 0x08 3. "E3,Event #3" "0,1" newline bitfld.long 0x08 2. "E2,Event #2" "0,1" bitfld.long 0x08 1. "E1,Event #1" "0,1" newline bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,Event #7" "0,1" newline bitfld.long 0x0C 6. "E6,Event #6" "0,1" bitfld.long 0x0C 5. "E5,Event #5" "0,1" newline bitfld.long 0x0C 4. "E4,Event #4" "0,1" bitfld.long 0x0C 3. "E3,Event #3" "0,1" newline bitfld.long 0x0C 2. "E2,Event #2" "0,1" bitfld.long 0x0C 1. "E1,Event #1" "0,1" newline bitfld.long 0x0C 0. "E0,Event #0" "0,1" line.long 0x10 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 7. "E7,Event #7" "0,1" newline rbitfld.long 0x10 6. "E6,Event #6" "0,1" rbitfld.long 0x10 5. "E5,Event #5" "0,1" newline rbitfld.long 0x10 4. "E4,Event #4" "0,1" rbitfld.long 0x10 3. "E3,Event #3" "0,1" newline rbitfld.long 0x10 2. "E2,Event #2" "0,1" rbitfld.long 0x10 1. "E1,Event #1" "0,1" newline rbitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event #7" "0,1" newline bitfld.long 0x14 6. "E6,Event #6" "0,1" bitfld.long 0x14 5. "E5,Event #5" "0,1" newline bitfld.long 0x14 4. "E4,Event #4" "0,1" bitfld.long 0x14 3. "E3,Event #3" "0,1" newline bitfld.long 0x14 2. "E2,Event #2" "0,1" bitfld.long 0x14 1. "E1,Event #1" "0,1" newline bitfld.long 0x14 0. "E0,Event #0" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2200++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2600++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2204++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2604++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2208++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2608++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x220C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x260C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2210++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2610++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2214++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2614++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2218++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2618++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x221C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x261C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2220++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2620++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2224++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2624++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2228++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2628++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x222C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x262C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2230++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2630++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2234++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2634++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2238++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2638++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x223C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x263C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2240++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2640++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2244++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2644++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2250++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2650++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2254++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2654++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2258++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2658++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x225C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x265C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2260++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2660++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2264++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2664++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2268++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2668++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x226C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x266C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2270++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2670++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2274++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2674++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2278++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2678++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2A78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2C78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2E78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2280++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2680++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2284++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2684++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2288++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2688++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x228C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x268C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2290++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2690++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2294++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2694++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4020++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_1,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4060++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_3,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_5,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_6,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_7,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4100++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_8,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4120++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_9,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4140++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4160++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_11,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4180++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_12,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_13,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_14,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_15,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4200++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4220++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_17,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4240++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_18,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4260++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_19,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4280++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_20,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_21,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_22,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_23,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4300++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_24,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4320++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_25,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4340++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_26,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4360++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_27,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4380++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_28,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_29,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_30,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_31,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4400++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4420++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_33,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4440++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_34,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4460++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_35,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4480++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_36,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_37,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_38,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_39,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4500++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_40,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4520++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_41,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4540++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_42,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4560++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_43,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4580++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_44,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_45,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_46,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_47,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4600++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4620++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_49,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4640++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_50,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4660++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_51,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4680++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_52,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_53,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_54,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_55,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4700++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_56,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4720++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_57,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4740++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_58,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4760++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_59,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4780++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_60,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_61,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_62,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_63,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4800++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4820++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_65,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4840++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_66,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4860++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_67,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4880++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_68,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_69,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_70,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_71,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4900++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_72,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4920++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_73,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4940++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_74,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4960++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_75,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4980++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_76,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_77,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_78,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_79,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_81,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_82,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_83,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_84,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_85,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_86,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_87,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_88,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_89,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_90,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_91,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_92,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_93,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_94,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_95,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_96,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_97,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_98,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_99,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_101,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_102,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_103,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_104,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_105,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_106,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_107,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_108,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_109,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_110,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_111,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_113,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_114,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_115,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_116,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_117,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_118,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_119,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_120,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_121,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_122,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_123,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_124,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_125,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_126,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_127,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" group.long 0x4024++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_1,Source Address" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" group.long 0x4064++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_3,Source Address" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" group.long 0x40A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_5,Source Address" group.long 0x40C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_6,Source Address" group.long 0x40E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_7,Source Address" group.long 0x4104++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_8,Source Address" group.long 0x4124++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_9,Source Address" group.long 0x4144++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_10,Source Address" group.long 0x4164++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_11,Source Address" group.long 0x4184++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_12,Source Address" group.long 0x41A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_13,Source Address" group.long 0x41C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_14,Source Address" group.long 0x41E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_15,Source Address" group.long 0x4204++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_16,Source Address" group.long 0x4224++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_17,Source Address" group.long 0x4244++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_18,Source Address" group.long 0x4264++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_19,Source Address" group.long 0x4284++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_20,Source Address" group.long 0x42A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_21,Source Address" group.long 0x42C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_22,Source Address" group.long 0x42E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_23,Source Address" group.long 0x4304++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_24,Source Address" group.long 0x4324++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_25,Source Address" group.long 0x4344++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_26,Source Address" group.long 0x4364++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_27,Source Address" group.long 0x4384++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_28,Source Address" group.long 0x43A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_29,Source Address" group.long 0x43C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_30,Source Address" group.long 0x43E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_31,Source Address" group.long 0x4404++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_32,Source Address" group.long 0x4424++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_33,Source Address" group.long 0x4444++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_34,Source Address" group.long 0x4464++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_35,Source Address" group.long 0x4484++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_36,Source Address" group.long 0x44A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_37,Source Address" group.long 0x44C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_38,Source Address" group.long 0x44E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_39,Source Address" group.long 0x4504++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_40,Source Address" group.long 0x4524++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_41,Source Address" group.long 0x4544++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_42,Source Address" group.long 0x4564++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_43,Source Address" group.long 0x4584++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_44,Source Address" group.long 0x45A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_45,Source Address" group.long 0x45C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_46,Source Address" group.long 0x45E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_47,Source Address" group.long 0x4604++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_48,Source Address" group.long 0x4624++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_49,Source Address" group.long 0x4644++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_50,Source Address" group.long 0x4664++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_51,Source Address" group.long 0x4684++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_52,Source Address" group.long 0x46A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_53,Source Address" group.long 0x46C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_54,Source Address" group.long 0x46E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_55,Source Address" group.long 0x4704++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_56,Source Address" group.long 0x4724++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_57,Source Address" group.long 0x4744++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_58,Source Address" group.long 0x4764++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_59,Source Address" group.long 0x4784++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_60,Source Address" group.long 0x47A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_61,Source Address" group.long 0x47C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_62,Source Address" group.long 0x47E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_63,Source Address" group.long 0x4804++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_64,Source Address" group.long 0x4824++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_65,Source Address" group.long 0x4844++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_66,Source Address" group.long 0x4864++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_67,Source Address" group.long 0x4884++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_68,Source Address" group.long 0x48A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_69,Source Address" group.long 0x48C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_70,Source Address" group.long 0x48E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_71,Source Address" group.long 0x4904++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_72,Source Address" group.long 0x4924++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_73,Source Address" group.long 0x4944++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_74,Source Address" group.long 0x4964++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_75,Source Address" group.long 0x4984++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_76,Source Address" group.long 0x49A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_77,Source Address" group.long 0x49C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_78,Source Address" group.long 0x49E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_79,Source Address" group.long 0x4A04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_80,Source Address" group.long 0x4A24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_81,Source Address" group.long 0x4A44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_82,Source Address" group.long 0x4A64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_83,Source Address" group.long 0x4A84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_84,Source Address" group.long 0x4AA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_85,Source Address" group.long 0x4AC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_86,Source Address" group.long 0x4AE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_87,Source Address" group.long 0x4B04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_88,Source Address" group.long 0x4B24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_89,Source Address" group.long 0x4B44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_90,Source Address" group.long 0x4B64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_91,Source Address" group.long 0x4B84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_92,Source Address" group.long 0x4BA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_93,Source Address" group.long 0x4BC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_94,Source Address" group.long 0x4BE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_95,Source Address" group.long 0x4C04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_96,Source Address" group.long 0x4C24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_97,Source Address" group.long 0x4C44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_98,Source Address" group.long 0x4C64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_99,Source Address" group.long 0x4C84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_100,Source Address" group.long 0x4CA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_101,Source Address" group.long 0x4CC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_102,Source Address" group.long 0x4CE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_103,Source Address" group.long 0x4D04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_104,Source Address" group.long 0x4D24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_105,Source Address" group.long 0x4D44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_106,Source Address" group.long 0x4D64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_107,Source Address" group.long 0x4D84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_108,Source Address" group.long 0x4DA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_109,Source Address" group.long 0x4DC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_110,Source Address" group.long 0x4DE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_111,Source Address" group.long 0x4E04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_112,Source Address" group.long 0x4E24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_113,Source Address" group.long 0x4E44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_114,Source Address" group.long 0x4E64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_115,Source Address" group.long 0x4E84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_116,Source Address" group.long 0x4EA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_117,Source Address" group.long 0x4EC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_118,Source Address" group.long 0x4EE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_119,Source Address" group.long 0x4F04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_120,Source Address" group.long 0x4F24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_121,Source Address" group.long 0x4F44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_122,Source Address" group.long 0x4F64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_123,Source Address" group.long 0x4F84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_124,Source Address" group.long 0x4FA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_125,Source Address" group.long 0x4FC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_126,Source Address" group.long 0x4FE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_127,Source Address" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x402C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_1,Destination Address" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x406C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_3,Destination Address" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x40AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_5,Destination Address" group.long 0x40CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_6,Destination Address" group.long 0x40EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_7,Destination Address" group.long 0x410C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_8,Destination Address" group.long 0x412C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_9,Destination Address" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x416C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_11,Destination Address" group.long 0x418C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_12,Destination Address" group.long 0x41AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_13,Destination Address" group.long 0x41CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_14,Destination Address" group.long 0x41EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_15,Destination Address" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x422C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_17,Destination Address" group.long 0x424C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_18,Destination Address" group.long 0x426C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_19,Destination Address" group.long 0x428C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_20,Destination Address" group.long 0x42AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_21,Destination Address" group.long 0x42CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_22,Destination Address" group.long 0x42EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_23,Destination Address" group.long 0x430C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_24,Destination Address" group.long 0x432C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_25,Destination Address" group.long 0x434C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_26,Destination Address" group.long 0x436C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_27,Destination Address" group.long 0x438C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_28,Destination Address" group.long 0x43AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_29,Destination Address" group.long 0x43CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_30,Destination Address" group.long 0x43EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_31,Destination Address" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x442C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_33,Destination Address" group.long 0x444C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_34,Destination Address" group.long 0x446C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_35,Destination Address" group.long 0x448C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_36,Destination Address" group.long 0x44AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_37,Destination Address" group.long 0x44CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_38,Destination Address" group.long 0x44EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_39,Destination Address" group.long 0x450C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_40,Destination Address" group.long 0x452C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_41,Destination Address" group.long 0x454C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_42,Destination Address" group.long 0x456C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_43,Destination Address" group.long 0x458C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_44,Destination Address" group.long 0x45AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_45,Destination Address" group.long 0x45CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_46,Destination Address" group.long 0x45EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_47,Destination Address" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x462C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_49,Destination Address" group.long 0x464C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_50,Destination Address" group.long 0x466C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_51,Destination Address" group.long 0x468C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_52,Destination Address" group.long 0x46AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_53,Destination Address" group.long 0x46CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_54,Destination Address" group.long 0x46EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_55,Destination Address" group.long 0x470C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_56,Destination Address" group.long 0x472C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_57,Destination Address" group.long 0x474C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_58,Destination Address" group.long 0x476C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_59,Destination Address" group.long 0x478C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_60,Destination Address" group.long 0x47AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_61,Destination Address" group.long 0x47CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_62,Destination Address" group.long 0x47EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_63,Destination Address" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x482C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_65,Destination Address" group.long 0x484C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_66,Destination Address" group.long 0x486C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_67,Destination Address" group.long 0x488C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_68,Destination Address" group.long 0x48AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_69,Destination Address" group.long 0x48CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_70,Destination Address" group.long 0x48EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_71,Destination Address" group.long 0x490C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_72,Destination Address" group.long 0x492C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_73,Destination Address" group.long 0x494C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_74,Destination Address" group.long 0x496C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_75,Destination Address" group.long 0x498C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_76,Destination Address" group.long 0x49AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_77,Destination Address" group.long 0x49CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_78,Destination Address" group.long 0x49EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_79,Destination Address" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_81,Destination Address" group.long 0x4A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_82,Destination Address" group.long 0x4A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_83,Destination Address" group.long 0x4A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_84,Destination Address" group.long 0x4AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_85,Destination Address" group.long 0x4ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_86,Destination Address" group.long 0x4AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_87,Destination Address" group.long 0x4B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_88,Destination Address" group.long 0x4B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_89,Destination Address" group.long 0x4B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_90,Destination Address" group.long 0x4B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_91,Destination Address" group.long 0x4B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_92,Destination Address" group.long 0x4BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_93,Destination Address" group.long 0x4BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_94,Destination Address" group.long 0x4BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_95,Destination Address" group.long 0x4C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_96,Destination Address" group.long 0x4C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_97,Destination Address" group.long 0x4C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_98,Destination Address" group.long 0x4C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_99,Destination Address" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_101,Destination Address" group.long 0x4CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_102,Destination Address" group.long 0x4CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_103,Destination Address" group.long 0x4D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_104,Destination Address" group.long 0x4D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_105,Destination Address" group.long 0x4D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_106,Destination Address" group.long 0x4D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_107,Destination Address" group.long 0x4D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_108,Destination Address" group.long 0x4DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_109,Destination Address" group.long 0x4DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_110,Destination Address" group.long 0x4DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_111,Destination Address" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_113,Destination Address" group.long 0x4E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_114,Destination Address" group.long 0x4E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_115,Destination Address" group.long 0x4E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_116,Destination Address" group.long 0x4EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_117,Destination Address" group.long 0x4ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_118,Destination Address" group.long 0x4EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_119,Destination Address" group.long 0x4F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_120,Destination Address" group.long 0x4F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_121,Destination Address" group.long 0x4F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_122,Destination Address" group.long 0x4F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_123,Destination Address" group.long 0x4F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_124,Destination Address" group.long 0x4FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_125,Destination Address" group.long 0x4FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_126,Destination Address" group.long 0x4FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_127,Destination Address" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_1," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_3," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_5," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_6," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_7," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_8," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_9," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_11," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_12," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_13," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_14," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_15," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_17," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_18," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_19," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_20," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_21," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_22," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_23," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_24," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_25," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_26," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_27," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_28," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_29," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_30," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_31," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_33," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_34," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_35," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_36," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_37," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_38," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_39," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_40," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_41," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_42," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_43," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_44," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_45," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_46," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_47," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_49," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_50," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_51," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_52," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_53," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_54," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_55," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_56," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_57," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_58," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_59," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_60," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_61," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_62," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_63," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_65," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_66," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_67," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_68," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_69," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_70," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_71," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_72," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_73," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_74," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_75," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_76," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_77," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_78," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_79," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_81," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_82," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_83," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_84," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_85," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_86," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_87," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_88," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_89," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_90," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_91," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_92," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_93," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_94," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_95," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_96," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_97," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_98," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_99," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_101," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_102," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_103," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_104," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_105," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_106," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_107," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_108," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_109," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_110," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_111," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_113," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_114," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_115," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_116," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_117," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_118," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_119," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_120," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_121," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_122," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_123," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_124," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_125," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_126," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_127," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x403C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x407C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x411C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x413C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x417C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x419C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x423C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x425C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x427C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x429C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x431C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x433C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x435C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x437C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x439C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x443C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x445C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x447C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x449C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x451C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x453C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x455C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x457C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x459C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x463C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x465C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x467C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x469C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x471C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x473C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x475C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x477C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x479C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x483C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x485C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x487C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x489C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x491C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x493C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x495C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x497C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x499C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x41505000 ad:0x41506000 ) tree "DSP2_EDMA_TPTC$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPTCn_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPTCn_TCCFG,TC Configuration Register" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 8.--9. "DREGDEPTH,Destination Register FIFO Depth Parameterization" "0,1,2,3" bitfld.long 0x04 6.--7. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" group.long 0x100++0x13 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 11.--12. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" rbitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" rbitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" line.long 0x04 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" rbitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x08 "EDMA_TPTCn_INTEN,Interrupt Enable Register" hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x0C "EDMA_TPTCn_INTCLR,Interrupt Clear Register" hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x10 "EDMA_TPTCn_INTCMD,Interrupt Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" group.long 0x120++0x13 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" rbitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 1. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" line.long 0x04 "EDMA_TPTCn_ERREN,Error Enable Register" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x04 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x04 1. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" line.long 0x08 "EDMA_TPTCn_ERRCLR,Error Clear Register" hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x08 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x08 1. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" line.long 0x0C "EDMA_TPTCn_ERRDET,Error Details Register" hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0C 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" rbitfld.long 0x0C 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 14.--15. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EDMA_TPTCn_ERRCMD,Error Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" group.long 0x200++0x17 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" rbitfld.long 0x00 21. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" rbitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "Highest priority,Priority 1,?,?,?,?,?,Lowest priority" newline rbitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" line.long 0x08 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count" line.long 0x0C "EDMA_TPTCn_PDST,Program Set Destination Address" line.long 0x10 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" line.long 0x14 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x240++0x23 line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" line.long 0x08 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" line.long 0x0C "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved. return 0x0 w/o AERROR" line.long 0x10 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" line.long 0x14 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" line.long 0x1C "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" line.long 0x20 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" group.long 0x280++0x0B line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" line.long 0x04 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" line.long 0x08 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" group.long 0x300++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x304++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x344++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x308++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x348++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x30C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x34C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x350++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" group.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x354++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end repeat.end tree "DSP2_FW_CFG_TARG" base ad:0x4A174000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DSP2_FW_L2_NOC_CFG" base ad:0x41503000 group.long 0x00++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0,Core 0 Error log register" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" newline rbitfld.long 0x00 26. "RESERVED," "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" bitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x40++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 2.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x88++0x17 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" line.long 0x08 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1,Start physical address of region 1" hexmask.long 0x08 4.--31. 1. "RESERVED," bitfld.long 0x08 0.--3. "START_REGION_1,Physical target start address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1,End physical address of region 1" bitfld.long 0x0C 31. "END_REGION_1_ENABLE,End Region 1 enable" "0,1" hexmask.long 0x0C 4.--30. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "END_REGION_1,Physical target end address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_1,RM_PERMISSION_REGION_1_LOW register" hexmask.long.word 0x10 16.--31. 1. "RESERVED," bitfld.long 0x10 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x10 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x10 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x10 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x10 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x10 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x10 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x10 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x10 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_1,RM_PERMISSION_REGION_1_HIGH register" bitfld.long 0x14 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x14 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x14 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x14 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x14 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x14 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x14 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x14 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x14 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x14 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x14 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x14 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x14 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x14 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x14 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x14 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x14 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x14 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x14 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x14 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x14 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x14 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x14 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x14 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x14 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x14 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x14 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x14 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x14 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x14 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x14 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x14 0. "R0,Initiator ID0 permission" "0,1" group.long 0x1000++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0,Core 0 Error log register" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" newline rbitfld.long 0x00 26. "RESERVED," "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" bitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x1040++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 2.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x1088++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" rgroup.long 0x4000++0x17 line.long 0x00 "DSPNOC_FLAGMUX_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_FLAGMUX_ID_REVISIONID," line.long 0x08 "DSPNOC_FLAGMUX_FAULTEN," hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "FAULTEN,Global Fault Enable register" "0,1" line.long 0x0C "DSPNOC_FLAGMUX_FAULTSTATUS," hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "FAULTSTATUS,Global Fault Status register" "0,1" line.long 0x10 "DSPNOC_FLAGMUX_FLAGINEN0," hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" line.long 0x14 "DSPNOC_FLAGMUX_FLAGINSTATUS0," hexmask.long 0x14 1.--31. 1. "RESERVED," bitfld.long 0x14 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" rgroup.long 0x4200++0x1B line.long 0x00 "DSPNOC_ERRORLOG_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_ERRORLOG_ID_REVISIONID," line.long 0x08 "DSPNOC_ERRORLOG_FAULTEN," hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "FAULTEN,Enable Fault output" "0,1" line.long 0x0C "DSPNOC_ERRORLOG_ERRVLD," hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "ERRVLD,Error logged Valid" "0,1" line.long 0x10 "DSPNOC_ERRORLOG_ERRCLR," hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "ERRCLR,Clr ErrVld status" "0,1" line.long 0x14 "DSPNOC_ERRORLOG_ERRLOG0,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x14 31. "FORMAT,Format of ErrLog0 register" "0,1" bitfld.long 0x14 28.--30. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--27. 1. "LEN1,Header: Len1 value" bitfld.long 0x14 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x14 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0. "LOCK,Header: Lock bit value" "0,1" line.long 0x18 "DSPNOC_ERRORLOG_ERRLOG1," hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED," hexmask.long.word 0x18 0.--14. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x4220++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG3," bitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 0.--30. 1. "ERRLOG3,Header: Addr lsb value" rgroup.long 0x4228++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG5," hexmask.long.word 0x00 22.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--21. 1. "ERRLOG5,Header: User lsb value" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x41501000 ad:0x41502000 ) tree "DSP2_MMU$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Write 0's for future compatibility" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" rbitfld.long 0x00 5.--7. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x00 2. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" hexmask.long 0x08 5.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" newline bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0_w,EMUMISS_1_r" bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" hexmask.long 0x0C 5.--31. 1. "RESERVED,Write 0's for future compatibility Read returns 0" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" newline bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0,EMUMISS_1" bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" hexmask.long 0x00 1.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" hexmask.long 0x04 4.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable" "TWLENABLE_0,TWLENABLE_1" newline bitfld.long 0x04 1. "MMUENABLE,MMU enable" "MMUENABLE_0,MMUENABLE_1" rbitfld.long 0x04 0. "RESERVED,Write 0's for future compatibility" "0,1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" hexmask.long.byte 0x0C 0.--6. 1. "RESERVED,Write 0's for future compatibility" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 9. "RESERVED,Write 0's for future compatibility" "0,1" newline bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 0.--3. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" hexmask.long 0x14 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x18 4.--11. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x18 3. "P,Preserved bit" "P_0,P_1" newline bitfld.long 0x18 2. "V,Valid bit" "V_0,V_1" bitfld.long 0x18 0.--1. "PAGESIZE,Page size" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x1C 0.--11. 1. "RESERVED,Write 0's for future compatibility" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" hexmask.long 0x20 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" hexmask.long 0x24 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x28 4.--11. 1. "RESERVED,Reads return 0" bitfld.long 0x28 3. "P,Preserved bit" "P_0_r,P_1_r" newline bitfld.long 0x28 2. "V,Valid bit" "V_0_r,V_1_r" bitfld.long 0x28 0.--1. "PAGESIZE,Page size" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x2C 0.--11. 1. "RESERVED,Reads return 0" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" newline rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "0,1,2,3" bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "0,1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" hexmask.long.word 0x08 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 0.--15. 1. "RESERVED,Reserved" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 0.--15. 1. "RESERVED,Reserved" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 0.--15. 1. "RESERVED,Reserved" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the fourth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 0.--15. 1. "RESERVED,Reserved" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of fourth NO TRANSLATION REGION for 2D bursts" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" width 0x0B tree.end repeat.end tree "DSP2_PRM" base ad:0x4AE07B00 group.long 0x00++0x07 line.long 0x00 "PM_DSP2_PWRSTCTRL,This register controls the DSP power state to reach upon a domain sleep transition" hexmask.long.word 0x00 22.--31. 1. "RESERVED," rbitfld.long 0x00 20.--21. "DSP2_EDMA_ONSTATE,DSP_EDMA state when domain is ON" "?,?,?,DSP2_EDMA_ONSTATE_3" rbitfld.long 0x00 18.--19. "DSP2_L2_ONSTATE,DSP_L2 state when domain is ON" "?,?,?,DSP2_L2_ONSTATE_3" newline rbitfld.long 0x00 16.--17. "DSP2_L1_ONSTATE,DSP_L1 state when domain is ON" "?,?,?,DSP2_L1_ONSTATE_3" hexmask.long.word 0x00 5.--15. 1. "RESERVED," bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_DSP2_PWRSTST,This register provides a status on the DSP domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" hexmask.long.word 0x04 10.--19. 1. "RESERVED," rbitfld.long 0x04 8.--9. "DSP2_EDMA_STATEST,DSP_EDMA memory state status" "DSP2_EDMA_STATEST_0,DSP2_EDMA_STATEST_1,DSP2_EDMA_STATEST_2,DSP2_EDMA_STATEST_3" newline rbitfld.long 0x04 6.--7. "DSP2_L2_STATEST,DSP_L2 memory state status" "DSP2_L2_STATEST_0,DSP2_L2_STATEST_1,DSP2_L2_STATEST_2,DSP2_L2_STATEST_3" rbitfld.long 0x04 4.--5. "DSP2_L1_STATEST,DSP_L1 memory state status" "DSP2_L1_STATEST_0,DSP2_L1_STATEST_1,DSP2_L1_STATEST_2,DSP2_L1_STATEST_3" rbitfld.long 0x04 3. "RESERVED," "0,1" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_DSP2_RSTCTRL,This register controls the release of the DSP sub-system resets" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "RST_DSP2,DSP SW reset control" "RST_DSP2_0,RST_DSP2_1" bitfld.long 0x00 0. "RST_DSP2_LRST,DSP Local reset control" "RST_DSP2_LRST_0,RST_DSP2_LRST_1" line.long 0x04 "RM_DSP2_RSTST,This register logs the different reset sources of the DSP domain" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "RST_DSP2_EMU_REQ,DSP processor has been reset due to DSP emulation reset request driven from DSP-SS" "RST_DSP2_EMU_REQ_0,RST_DSP2_EMU_REQ_1" bitfld.long 0x04 2. "RST_DSP2_EMU,DSP domain has been reset due to emulation reset source e.g" "RST_DSP2_EMU_0,RST_DSP2_EMU_1" newline bitfld.long 0x04 1. "RST_DSP2,DSP SW reset status" "RST_DSP2_0,RST_DSP2_1" bitfld.long 0x04 0. "RST_DSP2_LRST,DSP Local SW reset" "RST_DSP2_LRST_0,RST_DSP2_LRST_1" group.long 0x24++0x03 line.long 0x00 "RM_DSP2_DSP2_CONTEXT,This register contains dedicated DSP context statuses" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," bitfld.long 0x00 10. "LOSTMEM_DSP_EDMA,Specify if memory-based context in DSP_EDMA memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_EDMA_0,LOSTMEM_DSP_EDMA_1" bitfld.long 0x00 9. "LOSTMEM_DSP_L2,Specify if memory-based context in DSP_L2 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_L2_0,LOSTMEM_DSP_L2_1" newline bitfld.long 0x00 8. "LOSTMEM_DSP_L1,Specify if memory-based context in DSP_L1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_L1_0,LOSTMEM_DSP_L1_1" hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "DSP2_SDMA_FW" base ad:0x4A173000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "DSP2_SDMA_TARG" base ad:0x44000600 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "DSP2_SYSTEM" base ad:0x41500000 rgroup.long 0x00++0x1B line.long 0x00 "DSP_SYS_REVISION," line.long 0x04 "DSP_SYS_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," bitfld.long 0x04 0.--3. "NUM,Instance Number Set by subsystem input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DSP_SYS_SYSCONFIG," hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 8. "RESERVED,Reserved" "0,1" rbitfld.long 0x08 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x08 4.--5. "STANDBYMODE," "?,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x08 2.--3. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x08 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x0C "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode" hexmask.long 0x0C 6.--31. 1. "RESERVED," bitfld.long 0x0C 4.--5. "OCPI_DISC_STAT,L3_MAIN (OCP) Initiator(s) Disconnect Status" "OCPI_DISC_STAT_0_r,OCPI_DISC_STAT_1_r,OCPI_DISC_STAT_2_r,?" bitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "TC1_STAT,EDMA TC1 Status" "TC1_STAT_0,TC1_STAT_1" bitfld.long 0x0C 1. "TC0_STAT,EDMA TC0 Status" "TC0_STAT_0,TC0_STAT_1" bitfld.long 0x0C 0. "C66X_STAT,C66x Status" "C66X_STAT_0,C66X_STAT_1" line.long 0x10 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "OCPI_DISC,OCP Initiator (on L3_MAIN) Disconnect request" "OCPI_DISC_0_w,OCPI_DISC_1_w" line.long 0x14 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators" rbitfld.long 0x14 31. "RESERVED," "0,1" bitfld.long 0x14 28.--30. "SDMA_PRI,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port" "0,1,2,3,4,5,6,7" rbitfld.long 0x14 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 24. "NOPOSTOVERRIDE,OCP Posted Write vs Non-Posted Write override" "NOPOSTOVERRIDE_0,NOPOSTOVERRIDE_1" rbitfld.long 0x14 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x14 20.--21. "SDMA_L2PRES,OCP Target port L2 Interconnect Pressure" "SDMA_L2PRES_0,SDMA_L2PRES_1,SDMA_L2PRES_2,SDMA_L2PRES_3" newline rbitfld.long 0x14 18.--19. "RESERVED," "0,1,2,3" bitfld.long 0x14 16.--17. "CFG_L2PRES,DSP CFG L2 Interconnect Pressure" "CFG_L2PRES_0,CFG_L2PRES_1,CFG_L2PRES_2,CFG_L2PRES_3" rbitfld.long 0x14 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 12.--13. "TC1_L2PRES,TC1 L2 Interconnect Pressure" "TC1_L2PRES_0,TC1_L2PRES_1,TC1_L2PRES_2,TC1_L2PRES_3" rbitfld.long 0x14 10.--11. "RESERVED," "0,1,2,3" bitfld.long 0x14 8.--9. "TC0_L2PRES,TC0 L2 Interconnect Pressure" "TC0_L2PRES_0,TC0_L2PRES_1,TC0_L2PRES_2,TC0_L2PRES_3" newline rbitfld.long 0x14 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x14 4.--5. "TC1_DBS,TC1 Default Burst size" "TC1_DBS_0,TC1_DBS_1,TC1_DBS_2,TC1_DBS_3" rbitfld.long 0x14 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 0.--1. "TC0_DBS,TC0 Default Burst size" "TC0_DBS_0,TC0_DBS_1,TC0_DBS_2,TC0_DBS_3" line.long 0x18 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs" hexmask.long.tbyte 0x18 13.--31. 1. "RESERVED," bitfld.long 0x18 12. "MMU1_ABORT,MU1 Abort" "MMU1_ABORT_0,MMU1_ABORT_1" rbitfld.long 0x18 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "MMU0_ABORT,MU0 Abort" "MMU0_ABORT_0,MMU0_ABORT_1" rbitfld.long 0x18 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 4. "MMU1_EN,MU1 Enable" "MMU1_EN_0,MMU1_EN_1" newline rbitfld.long 0x18 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 0. "MMU0_EN,MU1 Enable" "MMU0_EN_0,MMU0_EN_1" group.long 0x20++0x07 line.long 0x00 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x30++0x07 line.long 0x00 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x40++0x07 line.long 0x00 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state" line.long 0x04 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state" group.long 0x50++0x2F line.long 0x00 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.word 0x00 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--18. 1. "EVENT,Settable raw status for event #n" line.long 0x04 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector" hexmask.long.word 0x04 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x04 0.--18. 1. "EVENT,Clearable enabled status for event #n" line.long 0x08 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" hexmask.long.word 0x08 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x08 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x0C "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" hexmask.long.word 0x0C 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x0C 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x10 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x14 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x18 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x1C "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" line.long 0x20 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x24 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x28 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x2C "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" group.long 0xF8++0x07 line.long 0x00 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus" hexmask.long 0x00 4.--31. 1. "RESERVED," bitfld.long 0x00 0.--3. "GROUP,Debug Group output control mux selectN: GN = select output group N" "GROUP_0,GROUP_1,GROUP_2,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group" width 0x0B tree.end tree "DSP_EDMA_TPCC" base ad:0x1D10000 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x04 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x04 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" newline rbitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x04 22.--23. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x04 19. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x04 15. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x04 11. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7" group.long 0xFC++0x113 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" line.long 0x04 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x04 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x08 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x08 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x0C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x10 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x14 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x18 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x1C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" hexmask.long.tbyte 0x20 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x20 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" hexmask.long.tbyte 0x24 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x24 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" hexmask.long.tbyte 0x28 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x28 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x28 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x2C "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.tbyte 0x2C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x2C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x2C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" hexmask.long.tbyte 0x30 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x30 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x30 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" hexmask.long.tbyte 0x34 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x34 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x34 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x38 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" hexmask.long.tbyte 0x38 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x38 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x38 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x3C "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" hexmask.long.tbyte 0x3C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x3C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x3C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" hexmask.long.tbyte 0x40 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x40 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x40 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x44 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" hexmask.long.tbyte 0x44 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x44 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x44 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x48 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" hexmask.long.tbyte 0x48 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x48 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x48 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x4C "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" hexmask.long.tbyte 0x4C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x4C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" hexmask.long.tbyte 0x50 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x50 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x50 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x54 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" hexmask.long.tbyte 0x54 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x54 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x54 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x58 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" hexmask.long.tbyte 0x58 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x58 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x58 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x5C "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" hexmask.long.tbyte 0x5C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x5C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x5C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x60 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" hexmask.long.tbyte 0x60 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x60 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x60 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x64 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" hexmask.long.tbyte 0x64 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x64 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x64 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x68 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" hexmask.long.tbyte 0x68 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x68 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x68 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x6C "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" hexmask.long.tbyte 0x6C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x6C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x6C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x70 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" hexmask.long.tbyte 0x70 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x70 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x70 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x74 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" hexmask.long.tbyte 0x74 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x74 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x74 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x78 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" hexmask.long.tbyte 0x78 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x78 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x78 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x7C "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" hexmask.long.tbyte 0x7C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x7C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x7C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x80 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" hexmask.long.tbyte 0x80 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x80 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x80 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x84 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" hexmask.long.tbyte 0x84 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x84 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x84 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x88 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" hexmask.long.tbyte 0x88 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x88 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x88 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x8C "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" hexmask.long.tbyte 0x8C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x8C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x8C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x90 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" hexmask.long.tbyte 0x90 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x90 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x90 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x94 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" hexmask.long.tbyte 0x94 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x94 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x94 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x98 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" hexmask.long.tbyte 0x98 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x98 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x98 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x9C "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" hexmask.long.tbyte 0x9C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x9C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x9C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA0 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA4 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA8 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xAC "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" hexmask.long.tbyte 0xAC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xAC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xAC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB0 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB4 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB8 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xBC "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" hexmask.long.tbyte 0xBC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xBC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xBC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC0 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC4 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC8 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xCC "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" hexmask.long.tbyte 0xCC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xCC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xCC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD0 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD4 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD8 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xDC "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" hexmask.long.tbyte 0xDC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xDC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xDC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE0 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE4 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE8 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xEC "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" hexmask.long.tbyte 0xEC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xEC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xEC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF0 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF4 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF8 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xFC "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" hexmask.long.tbyte 0xFC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xFC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xFC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x100 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" hexmask.long.tbyte 0x100 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x100 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x100 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x104 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x104 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x104 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x104 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x104 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x108 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x108 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x108 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x108 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x108 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x10C "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x10C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10C 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x10C 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x10C 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x110 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x110 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x110 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x110 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x110 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x240++0x23 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x00 31. "RESERVED,Reserved" "0,1" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 27. "RESERVED,Reserved" "0,1" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 23. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Reserved" "0,1" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 15. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x04 31. "RESERVED,Reserved" "0,1" bitfld.long 0x04 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 27. "RESERVED,Reserved" "0,1" bitfld.long 0x04 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 23. "RESERVED,Reserved" "0,1" bitfld.long 0x04 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED,Reserved" "0,1" bitfld.long 0x04 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 15. "RESERVED,Reserved" "0,1" bitfld.long 0x04 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 11. "RESERVED,Reserved" "0,1" bitfld.long 0x04 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED,Reserved" "0,1" bitfld.long 0x04 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x08 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x08 31. "RESERVED,Reserved" "0,1" bitfld.long 0x08 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 27. "RESERVED,Reserved" "0,1" bitfld.long 0x08 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 23. "RESERVED,Reserved" "0,1" bitfld.long 0x08 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED,Reserved" "0,1" bitfld.long 0x08 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 15. "RESERVED,Reserved" "0,1" bitfld.long 0x08 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 11. "RESERVED,Reserved" "0,1" bitfld.long 0x08 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED,Reserved" "0,1" bitfld.long 0x08 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x0C "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x0C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x10 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x10 31. "RESERVED,Reserved" "0,1" bitfld.long 0x10 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED,Reserved" "0,1" bitfld.long 0x10 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED,Reserved" "0,1" bitfld.long 0x10 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "RESERVED,Reserved" "0,1" bitfld.long 0x10 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 15. "RESERVED,Reserved" "0,1" bitfld.long 0x10 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 11. "RESERVED,Reserved" "0,1" bitfld.long 0x10 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" bitfld.long 0x10 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 3. "RESERVED,Reserved" "0,1" bitfld.long 0x10 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x14 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x14 31. "RESERVED,Reserved" "0,1" bitfld.long 0x14 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED,Reserved" "0,1" bitfld.long 0x14 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED,Reserved" "0,1" bitfld.long 0x14 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED,Reserved" "0,1" bitfld.long 0x14 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED,Reserved" "0,1" bitfld.long 0x14 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" bitfld.long 0x14 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED,Reserved" "0,1" bitfld.long 0x14 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x18 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x18 31. "RESERVED,Reserved" "0,1" bitfld.long 0x18 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED,Reserved" "0,1" bitfld.long 0x18 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED,Reserved" "0,1" bitfld.long 0x18 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED,Reserved" "0,1" bitfld.long 0x18 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED,Reserved" "0,1" bitfld.long 0x18 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED,Reserved" "0,1" bitfld.long 0x18 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED,Reserved" "0,1" bitfld.long 0x18 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED,Reserved" "0,1" bitfld.long 0x18 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x1C "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x1C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x20 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" rbitfld.long 0x20 31. "RESERVED," "0,1" bitfld.long 0x20 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 27. "RESERVED," "0,1" bitfld.long 0x20 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 23. "RESERVED," "0,1" bitfld.long 0x20 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 19. "RESERVED," "0,1" bitfld.long 0x20 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 15. "RESERVED," "0,1" bitfld.long 0x20 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 11. "RESERVED," "0,1" bitfld.long 0x20 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 7. "RESERVED," "0,1" bitfld.long 0x20 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 3. "RESERVED," "0,1" bitfld.long 0x20 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x280++0x07 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_QUEPRI,Queue Priority" hexmask.long 0x04 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" rgroup.long 0x300++0x23 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" newline bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" newline bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" newline bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" newline bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" newline bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" newline bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" newline bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" newline bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" newline bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" newline bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" newline bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" newline bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" newline bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" newline bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" newline bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" newline bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" newline bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" newline bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" newline bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" newline bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" line.long 0x08 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1" newline bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1" bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1" newline bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1" newline bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1" bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1" newline bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1" newline bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1" bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1" newline bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1" newline bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1" bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1" newline bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1" newline bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1" bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1" newline bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1" line.long 0x0C "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1" bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1" bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1" bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1" bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1" bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1" line.long 0x10 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,Event Missed #7" "0,1" newline bitfld.long 0x10 6. "E6,Event Missed #6" "0,1" bitfld.long 0x10 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x10 4. "E4,Event Missed #4" "0,1" bitfld.long 0x10 3. "E3,Event Missed #3" "0,1" newline bitfld.long 0x10 2. "E2,Event Missed #2" "0,1" bitfld.long 0x10 1. "E1,Event Missed #1" "0,1" newline bitfld.long 0x10 0. "E0,Event Missed #0" "0,1" line.long 0x14 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1" newline bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1" newline bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1" bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1" newline bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1" line.long 0x18 "EDMA_TPCC_CCERR,CC Error Register" hexmask.long.word 0x18 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 16. "TCERR,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register" "TCERR_0,TCERR_1" newline hexmask.long.byte 0x18 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD7_0,QTHRXCD7_1" newline bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD6_0,QTHRXCD6_1" bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD5_0,QTHRXCD5_1" newline bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD4_0,QTHRXCD4_1" bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD3_0,QTHRXCD3_1" newline bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD1_0,QTHRXCD1_1" newline bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x1C "EDMA_TPCC_CCERRCLR,CC Error Clear Register" hexmask.long.word 0x1C 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR" "0,1" newline hexmask.long.byte 0x1C 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect" "0,1" bitfld.long 0x1C 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect" "0,1" bitfld.long 0x1C 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" newline bitfld.long 0x1C 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect" "0,1" bitfld.long 0x1C 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" newline bitfld.long 0x1C 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect" "0,1" line.long 0x20 "EDMA_TPCC_EEVAL,Error Eval Register" hexmask.long 0x20 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 1. "SET,Error Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x20 0. "EVAL,Error Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x348++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x350++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x358++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x360++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x368++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x370++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x378++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x344++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x34C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x354++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x35C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x364++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x36C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x374++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x37C++0x23 line.long 0x00 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" line.long 0x04 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x04 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x04 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x04 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x04 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x04 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x04 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x04 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x08 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x08 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x08 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x08 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x08 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x08 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x08 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x08 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x0C "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x0C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x0C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x0C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x0C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x0C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x0C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x0C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x10 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x10 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x10 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x10 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x10 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x10 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x10 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x10 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x14 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x14 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x14 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x14 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x14 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x14 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x14 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x14 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x18 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x18 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x18 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x18 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x18 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x18 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x18 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x18 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x1C "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x1C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x1C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x1C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x1C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x1C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x1C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x1C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x20 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x20 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x20 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x20 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x20 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x20 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x20 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x20 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" rgroup.long 0x400++0x7F line.long 0x00 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x04 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x08 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x10 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x14 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x18 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x1C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x20 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x24 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x28 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x2C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x30 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x30 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x30 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x34 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x34 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x38 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x38 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x3C "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x3C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x40 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x40 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x44 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x44 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x44 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x48 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x48 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x48 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x4C "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x4C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x4C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x50 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x50 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x50 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x54 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x54 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x54 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x54 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x58 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x58 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x58 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x58 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x5C "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x5C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x5C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x5C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x60 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x60 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x60 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x60 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x64 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x64 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x64 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x64 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x68 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x68 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x68 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x68 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x6C "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x6C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x6C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x6C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x70 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x70 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x70 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x70 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x74 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x74 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x74 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x74 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x78 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x78 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x78 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x78 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x7C "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x7C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x7C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x7C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x600++0x07 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" line.long 0x04 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" hexmask.long.byte 0x04 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" rbitfld.long 0x00 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" rbitfld.long 0x04 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,reads return 0's" rbitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" newline rbitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" rbitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" newline rbitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" rbitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" newline bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2" rbitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" newline rbitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 14.--15. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" rbitfld.long 0x00 5.--7. "RESERVED,reads return 0's" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" rbitfld.long 0x00 3. "RESERVED,reads return 0's" "0,1" newline bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.." rbitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" newline rbitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" group.long 0x700++0x0B line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" hexmask.long.tbyte 0x00 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" line.long 0x08 "EDMA_TPCC_AETCMD,AET Command" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "CLR,AET Clear commandCPU writes 0x0 has no effect" "0,1" rgroup.long 0x800++0x2F line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" line.long 0x04 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" newline rbitfld.long 0x04 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" rbitfld.long 0x04 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" newline rbitfld.long 0x04 2. "URE,User Read Error" "URE_0,URE_1" rbitfld.long 0x04 1. "UWE,User Write Error" "UWE_0,UWE_1" newline rbitfld.long 0x04 0. "UXE,User Execute Error" "UXE_0,UXE_1" line.long 0x08 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" line.long 0x0C "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x0C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x0C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x0C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x0C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x0C 10. "AID0,Allowed ID 0" "AID0_0,AID0_1" bitfld.long 0x0C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x0C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x0C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x0C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x0C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x0C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x0C 0. "UX,User Execute permission" "UX_0,UX_1" line.long 0x10 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x10 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x10 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x10 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x10 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x10 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x10 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x10 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x10 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x10 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x10 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x10 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x10 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x10 0. "UX,User Execute permission" "UX_0,?" line.long 0x14 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x14 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x14 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x14 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x14 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x14 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x14 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x14 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x14 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x14 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x14 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x14 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x14 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x14 0. "UX,User Execute permission" "UX_0,?" line.long 0x18 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x18 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x18 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x18 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x18 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x18 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x18 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x18 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x18 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x18 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x18 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x18 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x18 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x18 0. "UX,User Execute permission" "UX_0,?" line.long 0x1C "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x1C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x1C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x1C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x1C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x1C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x1C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x1C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x1C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x1C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x1C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x1C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x1C 0. "UX,User Execute permission" "UX_0,?" line.long 0x20 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x20 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x20 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x20 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x20 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x20 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x20 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x20 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x20 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x20 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x20 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x20 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x20 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x20 0. "UX,User Execute permission" "UX_0,?" line.long 0x24 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x24 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x24 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x24 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x24 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x24 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x24 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x24 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x24 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x24 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x24 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x24 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x24 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x24 0. "UX,User Execute permission" "UX_0,?" line.long 0x28 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" hexmask.long.word 0x28 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x28 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x28 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x28 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x28 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x28 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x28 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x28 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x28 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x28 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x28 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x28 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x28 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x28 0. "UX,User Execute permission" "UX_0,?" line.long 0x2C "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" hexmask.long.word 0x2C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x2C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x2C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x2C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x2C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x2C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x2C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x2C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x2C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x2C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x2C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x2C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x2C 0. "UX,User Execute permission" "UX_0,?" rgroup.long 0x1000++0x47 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" newline bitfld.long 0x04 29. "E61,Event #61" "0,1" bitfld.long 0x04 28. "E60,Event #60" "0,1" newline bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" newline bitfld.long 0x04 23. "E55,Event #55" "0,1" bitfld.long 0x04 22. "E54,Event #54" "0,1" newline bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" newline bitfld.long 0x04 17. "E49,Event #49" "0,1" bitfld.long 0x04 16. "E48,Event #48" "0,1" newline bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" newline bitfld.long 0x04 11. "E43,Event #43" "0,1" bitfld.long 0x04 10. "E42,Event #42" "0,1" newline bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" newline bitfld.long 0x04 5. "E37,Event #37" "0,1" bitfld.long 0x04 4. "E36,Event #36" "0,1" newline bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" line.long 0x08 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event #31" "0,1" bitfld.long 0x08 30. "E30,Event #30" "0,1" newline bitfld.long 0x08 29. "E29,Event #29" "0,1" bitfld.long 0x08 28. "E28,Event #28" "0,1" newline bitfld.long 0x08 27. "E27,Event #27" "0,1" bitfld.long 0x08 26. "E26,Event #26" "0,1" newline bitfld.long 0x08 25. "E25,Event #25" "0,1" bitfld.long 0x08 24. "E24,Event #24" "0,1" newline bitfld.long 0x08 23. "E23,Event #23" "0,1" bitfld.long 0x08 22. "E22,Event #22" "0,1" newline bitfld.long 0x08 21. "E21,Event #21" "0,1" bitfld.long 0x08 20. "E20,Event #20" "0,1" newline bitfld.long 0x08 19. "E19,Event #19" "0,1" bitfld.long 0x08 18. "E18,Event #18" "0,1" newline bitfld.long 0x08 17. "E17,Event #17" "0,1" bitfld.long 0x08 16. "E16,Event #16" "0,1" newline bitfld.long 0x08 15. "E15,Event #15" "0,1" bitfld.long 0x08 14. "E14,Event #14" "0,1" newline bitfld.long 0x08 13. "E13,Event #13" "0,1" bitfld.long 0x08 12. "E12,Event #12" "0,1" newline bitfld.long 0x08 11. "E11,Event #11" "0,1" bitfld.long 0x08 10. "E10,Event #10" "0,1" newline bitfld.long 0x08 9. "E9,Event #9" "0,1" bitfld.long 0x08 8. "E8,Event #8" "0,1" newline bitfld.long 0x08 7. "E7,Event #7" "0,1" bitfld.long 0x08 6. "E6,Event #6" "0,1" newline bitfld.long 0x08 5. "E5,Event #5" "0,1" bitfld.long 0x08 4. "E4,Event #4" "0,1" newline bitfld.long 0x08 3. "E3,Event #3" "0,1" bitfld.long 0x08 2. "E2,Event #2" "0,1" newline bitfld.long 0x08 1. "E1,Event #1" "0,1" bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event #63" "0,1" bitfld.long 0x0C 30. "E62,Event #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event #61" "0,1" bitfld.long 0x0C 28. "E60,Event #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event #59" "0,1" bitfld.long 0x0C 26. "E58,Event #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event #57" "0,1" bitfld.long 0x0C 24. "E56,Event #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event #55" "0,1" bitfld.long 0x0C 22. "E54,Event #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event #53" "0,1" bitfld.long 0x0C 20. "E52,Event #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event #51" "0,1" bitfld.long 0x0C 18. "E50,Event #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event #49" "0,1" bitfld.long 0x0C 16. "E48,Event #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event #47" "0,1" bitfld.long 0x0C 14. "E46,Event #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event #45" "0,1" bitfld.long 0x0C 12. "E44,Event #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event #43" "0,1" bitfld.long 0x0C 10. "E42,Event #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event #41" "0,1" bitfld.long 0x0C 8. "E40,Event #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event #39" "0,1" bitfld.long 0x0C 6. "E38,Event #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event #37" "0,1" bitfld.long 0x0C 4. "E36,Event #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event #35" "0,1" bitfld.long 0x0C 2. "E34,Event #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event #33" "0,1" bitfld.long 0x0C 0. "E32,Event #32" "0,1" line.long 0x10 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x10 31. "E31,Event #31" "0,1" bitfld.long 0x10 30. "E30,Event #30" "0,1" newline bitfld.long 0x10 29. "E29,Event #29" "0,1" bitfld.long 0x10 28. "E28,Event #28" "0,1" newline bitfld.long 0x10 27. "E27,Event #27" "0,1" bitfld.long 0x10 26. "E26,Event #26" "0,1" newline bitfld.long 0x10 25. "E25,Event #25" "0,1" bitfld.long 0x10 24. "E24,Event #24" "0,1" newline bitfld.long 0x10 23. "E23,Event #23" "0,1" bitfld.long 0x10 22. "E22,Event #22" "0,1" newline bitfld.long 0x10 21. "E21,Event #21" "0,1" bitfld.long 0x10 20. "E20,Event #20" "0,1" newline bitfld.long 0x10 19. "E19,Event #19" "0,1" bitfld.long 0x10 18. "E18,Event #18" "0,1" newline bitfld.long 0x10 17. "E17,Event #17" "0,1" bitfld.long 0x10 16. "E16,Event #16" "0,1" newline bitfld.long 0x10 15. "E15,Event #15" "0,1" bitfld.long 0x10 14. "E14,Event #14" "0,1" newline bitfld.long 0x10 13. "E13,Event #13" "0,1" bitfld.long 0x10 12. "E12,Event #12" "0,1" newline bitfld.long 0x10 11. "E11,Event #11" "0,1" bitfld.long 0x10 10. "E10,Event #10" "0,1" newline bitfld.long 0x10 9. "E9,Event #9" "0,1" bitfld.long 0x10 8. "E8,Event #8" "0,1" newline bitfld.long 0x10 7. "E7,Event #7" "0,1" bitfld.long 0x10 6. "E6,Event #6" "0,1" newline bitfld.long 0x10 5. "E5,Event #5" "0,1" bitfld.long 0x10 4. "E4,Event #4" "0,1" newline bitfld.long 0x10 3. "E3,Event #3" "0,1" bitfld.long 0x10 2. "E2,Event #2" "0,1" newline bitfld.long 0x10 1. "E1,Event #1" "0,1" bitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x14 31. "E63,Event #63" "0,1" bitfld.long 0x14 30. "E62,Event #62" "0,1" newline bitfld.long 0x14 29. "E61,Event #61" "0,1" bitfld.long 0x14 28. "E60,Event #60" "0,1" newline bitfld.long 0x14 27. "E59,Event #59" "0,1" bitfld.long 0x14 26. "E58,Event #58" "0,1" newline bitfld.long 0x14 25. "E57,Event #57" "0,1" bitfld.long 0x14 24. "E56,Event #56" "0,1" newline bitfld.long 0x14 23. "E55,Event #55" "0,1" bitfld.long 0x14 22. "E54,Event #54" "0,1" newline bitfld.long 0x14 21. "E53,Event #53" "0,1" bitfld.long 0x14 20. "E52,Event #52" "0,1" newline bitfld.long 0x14 19. "E51,Event #51" "0,1" bitfld.long 0x14 18. "E50,Event #50" "0,1" newline bitfld.long 0x14 17. "E49,Event #49" "0,1" bitfld.long 0x14 16. "E48,Event #48" "0,1" newline bitfld.long 0x14 15. "E47,Event #47" "0,1" bitfld.long 0x14 14. "E46,Event #46" "0,1" newline bitfld.long 0x14 13. "E45,Event #45" "0,1" bitfld.long 0x14 12. "E44,Event #44" "0,1" newline bitfld.long 0x14 11. "E43,Event #43" "0,1" bitfld.long 0x14 10. "E42,Event #42" "0,1" newline bitfld.long 0x14 9. "E41,Event #41" "0,1" bitfld.long 0x14 8. "E40,Event #40" "0,1" newline bitfld.long 0x14 7. "E39,Event #39" "0,1" bitfld.long 0x14 6. "E38,Event #38" "0,1" newline bitfld.long 0x14 5. "E37,Event #37" "0,1" bitfld.long 0x14 4. "E36,Event #36" "0,1" newline bitfld.long 0x14 3. "E35,Event #35" "0,1" bitfld.long 0x14 2. "E34,Event #34" "0,1" newline bitfld.long 0x14 1. "E33,Event #33" "0,1" bitfld.long 0x14 0. "E32,Event #32" "0,1" line.long 0x18 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x18 31. "E31,Event #31" "0,1" bitfld.long 0x18 30. "E30,Event #30" "0,1" newline bitfld.long 0x18 29. "E29,Event #29" "0,1" bitfld.long 0x18 28. "E28,Event #28" "0,1" newline bitfld.long 0x18 27. "E27,Event #27" "0,1" bitfld.long 0x18 26. "E26,Event #26" "0,1" newline bitfld.long 0x18 25. "E25,Event #25" "0,1" bitfld.long 0x18 24. "E24,Event #24" "0,1" newline bitfld.long 0x18 23. "E23,Event #23" "0,1" bitfld.long 0x18 22. "E22,Event #22" "0,1" newline bitfld.long 0x18 21. "E21,Event #21" "0,1" bitfld.long 0x18 20. "E20,Event #20" "0,1" newline bitfld.long 0x18 19. "E19,Event #19" "0,1" bitfld.long 0x18 18. "E18,Event #18" "0,1" newline bitfld.long 0x18 17. "E17,Event #17" "0,1" bitfld.long 0x18 16. "E16,Event #16" "0,1" newline bitfld.long 0x18 15. "E15,Event #15" "0,1" bitfld.long 0x18 14. "E14,Event #14" "0,1" newline bitfld.long 0x18 13. "E13,Event #13" "0,1" bitfld.long 0x18 12. "E12,Event #12" "0,1" newline bitfld.long 0x18 11. "E11,Event #11" "0,1" bitfld.long 0x18 10. "E10,Event #10" "0,1" newline bitfld.long 0x18 9. "E9,Event #9" "0,1" bitfld.long 0x18 8. "E8,Event #8" "0,1" newline bitfld.long 0x18 7. "E7,Event #7" "0,1" bitfld.long 0x18 6. "E6,Event #6" "0,1" newline bitfld.long 0x18 5. "E5,Event #5" "0,1" bitfld.long 0x18 4. "E4,Event #4" "0,1" newline bitfld.long 0x18 3. "E3,Event #3" "0,1" bitfld.long 0x18 2. "E2,Event #2" "0,1" newline bitfld.long 0x18 1. "E1,Event #1" "0,1" bitfld.long 0x18 0. "E0,Event #0" "0,1" line.long 0x1C "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x1C 31. "E63,Event #63" "0,1" bitfld.long 0x1C 30. "E62,Event #62" "0,1" newline bitfld.long 0x1C 29. "E61,Event #61" "0,1" bitfld.long 0x1C 28. "E60,Event #60" "0,1" newline bitfld.long 0x1C 27. "E59,Event #59" "0,1" bitfld.long 0x1C 26. "E58,Event #58" "0,1" newline bitfld.long 0x1C 25. "E57,Event #57" "0,1" bitfld.long 0x1C 24. "E56,Event #56" "0,1" newline bitfld.long 0x1C 23. "E55,Event #55" "0,1" bitfld.long 0x1C 22. "E54,Event #54" "0,1" newline bitfld.long 0x1C 21. "E53,Event #53" "0,1" bitfld.long 0x1C 20. "E52,Event #52" "0,1" newline bitfld.long 0x1C 19. "E51,Event #51" "0,1" bitfld.long 0x1C 18. "E50,Event #50" "0,1" newline bitfld.long 0x1C 17. "E49,Event #49" "0,1" bitfld.long 0x1C 16. "E48,Event #48" "0,1" newline bitfld.long 0x1C 15. "E47,Event #47" "0,1" bitfld.long 0x1C 14. "E46,Event #46" "0,1" newline bitfld.long 0x1C 13. "E45,Event #45" "0,1" bitfld.long 0x1C 12. "E44,Event #44" "0,1" newline bitfld.long 0x1C 11. "E43,Event #43" "0,1" bitfld.long 0x1C 10. "E42,Event #42" "0,1" newline bitfld.long 0x1C 9. "E41,Event #41" "0,1" bitfld.long 0x1C 8. "E40,Event #40" "0,1" newline bitfld.long 0x1C 7. "E39,Event #39" "0,1" bitfld.long 0x1C 6. "E38,Event #38" "0,1" newline bitfld.long 0x1C 5. "E37,Event #37" "0,1" bitfld.long 0x1C 4. "E36,Event #36" "0,1" newline bitfld.long 0x1C 3. "E35,Event #35" "0,1" bitfld.long 0x1C 2. "E34,Event #34" "0,1" newline bitfld.long 0x1C 1. "E33,Event #33" "0,1" bitfld.long 0x1C 0. "E32,Event #32" "0,1" line.long 0x20 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x20 31. "E31,Event #31" "0,1" bitfld.long 0x20 30. "E30,Event #30" "0,1" newline bitfld.long 0x20 29. "E29,Event #29" "0,1" bitfld.long 0x20 28. "E28,Event #28" "0,1" newline bitfld.long 0x20 27. "E27,Event #27" "0,1" bitfld.long 0x20 26. "E26,Event #26" "0,1" newline bitfld.long 0x20 25. "E25,Event #25" "0,1" bitfld.long 0x20 24. "E24,Event #24" "0,1" newline bitfld.long 0x20 23. "E23,Event #23" "0,1" bitfld.long 0x20 22. "E22,Event #22" "0,1" newline bitfld.long 0x20 21. "E21,Event #21" "0,1" bitfld.long 0x20 20. "E20,Event #20" "0,1" newline bitfld.long 0x20 19. "E19,Event #19" "0,1" bitfld.long 0x20 18. "E18,Event #18" "0,1" newline bitfld.long 0x20 17. "E17,Event #17" "0,1" bitfld.long 0x20 16. "E16,Event #16" "0,1" newline bitfld.long 0x20 15. "E15,Event #15" "0,1" bitfld.long 0x20 14. "E14,Event #14" "0,1" newline bitfld.long 0x20 13. "E13,Event #13" "0,1" bitfld.long 0x20 12. "E12,Event #12" "0,1" newline bitfld.long 0x20 11. "E11,Event #11" "0,1" bitfld.long 0x20 10. "E10,Event #10" "0,1" newline bitfld.long 0x20 9. "E9,Event #9" "0,1" bitfld.long 0x20 8. "E8,Event #8" "0,1" newline bitfld.long 0x20 7. "E7,Event #7" "0,1" bitfld.long 0x20 6. "E6,Event #6" "0,1" newline bitfld.long 0x20 5. "E5,Event #5" "0,1" bitfld.long 0x20 4. "E4,Event #4" "0,1" newline bitfld.long 0x20 3. "E3,Event #3" "0,1" bitfld.long 0x20 2. "E2,Event #2" "0,1" newline bitfld.long 0x20 1. "E1,Event #1" "0,1" bitfld.long 0x20 0. "E0,Event #0" "0,1" line.long 0x24 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x24 31. "E63,Event #63" "0,1" bitfld.long 0x24 30. "E62,Event #62" "0,1" newline bitfld.long 0x24 29. "E61,Event #61" "0,1" bitfld.long 0x24 28. "E60,Event #60" "0,1" newline bitfld.long 0x24 27. "E59,Event #59" "0,1" bitfld.long 0x24 26. "E58,Event #58" "0,1" newline bitfld.long 0x24 25. "E57,Event #57" "0,1" bitfld.long 0x24 24. "E56,Event #56" "0,1" newline bitfld.long 0x24 23. "E55,Event #55" "0,1" bitfld.long 0x24 22. "E54,Event #54" "0,1" newline bitfld.long 0x24 21. "E53,Event #53" "0,1" bitfld.long 0x24 20. "E52,Event #52" "0,1" newline bitfld.long 0x24 19. "E51,Event #51" "0,1" bitfld.long 0x24 18. "E50,Event #50" "0,1" newline bitfld.long 0x24 17. "E49,Event #49" "0,1" bitfld.long 0x24 16. "E48,Event #48" "0,1" newline bitfld.long 0x24 15. "E47,Event #47" "0,1" bitfld.long 0x24 14. "E46,Event #46" "0,1" newline bitfld.long 0x24 13. "E45,Event #45" "0,1" bitfld.long 0x24 12. "E44,Event #44" "0,1" newline bitfld.long 0x24 11. "E43,Event #43" "0,1" bitfld.long 0x24 10. "E42,Event #42" "0,1" newline bitfld.long 0x24 9. "E41,Event #41" "0,1" bitfld.long 0x24 8. "E40,Event #40" "0,1" newline bitfld.long 0x24 7. "E39,Event #39" "0,1" bitfld.long 0x24 6. "E38,Event #38" "0,1" newline bitfld.long 0x24 5. "E37,Event #37" "0,1" bitfld.long 0x24 4. "E36,Event #36" "0,1" newline bitfld.long 0x24 3. "E35,Event #35" "0,1" bitfld.long 0x24 2. "E34,Event #34" "0,1" newline bitfld.long 0x24 1. "E33,Event #33" "0,1" bitfld.long 0x24 0. "E32,Event #32" "0,1" line.long 0x28 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x28 31. "E31,Event #31" "0,1" bitfld.long 0x28 30. "E30,Event #30" "0,1" newline bitfld.long 0x28 29. "E29,Event #29" "0,1" bitfld.long 0x28 28. "E28,Event #28" "0,1" newline bitfld.long 0x28 27. "E27,Event #27" "0,1" bitfld.long 0x28 26. "E26,Event #26" "0,1" newline bitfld.long 0x28 25. "E25,Event #25" "0,1" bitfld.long 0x28 24. "E24,Event #24" "0,1" newline bitfld.long 0x28 23. "E23,Event #23" "0,1" bitfld.long 0x28 22. "E22,Event #22" "0,1" newline bitfld.long 0x28 21. "E21,Event #21" "0,1" bitfld.long 0x28 20. "E20,Event #20" "0,1" newline bitfld.long 0x28 19. "E19,Event #19" "0,1" bitfld.long 0x28 18. "E18,Event #18" "0,1" newline bitfld.long 0x28 17. "E17,Event #17" "0,1" bitfld.long 0x28 16. "E16,Event #16" "0,1" newline bitfld.long 0x28 15. "E15,Event #15" "0,1" bitfld.long 0x28 14. "E14,Event #14" "0,1" newline bitfld.long 0x28 13. "E13,Event #13" "0,1" bitfld.long 0x28 12. "E12,Event #12" "0,1" newline bitfld.long 0x28 11. "E11,Event #11" "0,1" bitfld.long 0x28 10. "E10,Event #10" "0,1" newline bitfld.long 0x28 9. "E9,Event #9" "0,1" bitfld.long 0x28 8. "E8,Event #8" "0,1" newline bitfld.long 0x28 7. "E7,Event #7" "0,1" bitfld.long 0x28 6. "E6,Event #6" "0,1" newline bitfld.long 0x28 5. "E5,Event #5" "0,1" bitfld.long 0x28 4. "E4,Event #4" "0,1" newline bitfld.long 0x28 3. "E3,Event #3" "0,1" bitfld.long 0x28 2. "E2,Event #2" "0,1" newline bitfld.long 0x28 1. "E1,Event #1" "0,1" bitfld.long 0x28 0. "E0,Event #0" "0,1" line.long 0x2C "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x2C 31. "E63,Event #63" "0,1" bitfld.long 0x2C 30. "E62,Event #62" "0,1" newline bitfld.long 0x2C 29. "E61,Event #61" "0,1" bitfld.long 0x2C 28. "E60,Event #60" "0,1" newline bitfld.long 0x2C 27. "E59,Event #59" "0,1" bitfld.long 0x2C 26. "E58,Event #58" "0,1" newline bitfld.long 0x2C 25. "E57,Event #57" "0,1" bitfld.long 0x2C 24. "E56,Event #56" "0,1" newline bitfld.long 0x2C 23. "E55,Event #55" "0,1" bitfld.long 0x2C 22. "E54,Event #54" "0,1" newline bitfld.long 0x2C 21. "E53,Event #53" "0,1" bitfld.long 0x2C 20. "E52,Event #52" "0,1" newline bitfld.long 0x2C 19. "E51,Event #51" "0,1" bitfld.long 0x2C 18. "E50,Event #50" "0,1" newline bitfld.long 0x2C 17. "E49,Event #49" "0,1" bitfld.long 0x2C 16. "E48,Event #48" "0,1" newline bitfld.long 0x2C 15. "E47,Event #47" "0,1" bitfld.long 0x2C 14. "E46,Event #46" "0,1" newline bitfld.long 0x2C 13. "E45,Event #45" "0,1" bitfld.long 0x2C 12. "E44,Event #44" "0,1" newline bitfld.long 0x2C 11. "E43,Event #43" "0,1" bitfld.long 0x2C 10. "E42,Event #42" "0,1" newline bitfld.long 0x2C 9. "E41,Event #41" "0,1" bitfld.long 0x2C 8. "E40,Event #40" "0,1" newline bitfld.long 0x2C 7. "E39,Event #39" "0,1" bitfld.long 0x2C 6. "E38,Event #38" "0,1" newline bitfld.long 0x2C 5. "E37,Event #37" "0,1" bitfld.long 0x2C 4. "E36,Event #36" "0,1" newline bitfld.long 0x2C 3. "E35,Event #35" "0,1" bitfld.long 0x2C 2. "E34,Event #34" "0,1" newline bitfld.long 0x2C 1. "E33,Event #33" "0,1" bitfld.long 0x2C 0. "E32,Event #32" "0,1" line.long 0x30 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x30 31. "E31,Event #31" "0,1" bitfld.long 0x30 30. "E30,Event #30" "0,1" newline bitfld.long 0x30 29. "E29,Event #29" "0,1" bitfld.long 0x30 28. "E28,Event #28" "0,1" newline bitfld.long 0x30 27. "E27,Event #27" "0,1" bitfld.long 0x30 26. "E26,Event #26" "0,1" newline bitfld.long 0x30 25. "E25,Event #25" "0,1" bitfld.long 0x30 24. "E24,Event #24" "0,1" newline bitfld.long 0x30 23. "E23,Event #23" "0,1" bitfld.long 0x30 22. "E22,Event #22" "0,1" newline bitfld.long 0x30 21. "E21,Event #21" "0,1" bitfld.long 0x30 20. "E20,Event #20" "0,1" newline bitfld.long 0x30 19. "E19,Event #19" "0,1" bitfld.long 0x30 18. "E18,Event #18" "0,1" newline bitfld.long 0x30 17. "E17,Event #17" "0,1" bitfld.long 0x30 16. "E16,Event #16" "0,1" newline bitfld.long 0x30 15. "E15,Event #15" "0,1" bitfld.long 0x30 14. "E14,Event #14" "0,1" newline bitfld.long 0x30 13. "E13,Event #13" "0,1" bitfld.long 0x30 12. "E12,Event #12" "0,1" newline bitfld.long 0x30 11. "E11,Event #11" "0,1" bitfld.long 0x30 10. "E10,Event #10" "0,1" newline bitfld.long 0x30 9. "E9,Event #9" "0,1" bitfld.long 0x30 8. "E8,Event #8" "0,1" newline bitfld.long 0x30 7. "E7,Event #7" "0,1" bitfld.long 0x30 6. "E6,Event #6" "0,1" newline bitfld.long 0x30 5. "E5,Event #5" "0,1" bitfld.long 0x30 4. "E4,Event #4" "0,1" newline bitfld.long 0x30 3. "E3,Event #3" "0,1" bitfld.long 0x30 2. "E2,Event #2" "0,1" newline bitfld.long 0x30 1. "E1,Event #1" "0,1" bitfld.long 0x30 0. "E0,Event #0" "0,1" line.long 0x34 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x34 31. "E63,Event #63" "0,1" bitfld.long 0x34 30. "E62,Event #62" "0,1" newline bitfld.long 0x34 29. "E61,Event #61" "0,1" bitfld.long 0x34 28. "E60,Event #60" "0,1" newline bitfld.long 0x34 27. "E59,Event #59" "0,1" bitfld.long 0x34 26. "E58,Event #58" "0,1" newline bitfld.long 0x34 25. "E57,Event #57" "0,1" bitfld.long 0x34 24. "E56,Event #56" "0,1" newline bitfld.long 0x34 23. "E55,Event #55" "0,1" bitfld.long 0x34 22. "E54,Event #54" "0,1" newline bitfld.long 0x34 21. "E53,Event #53" "0,1" bitfld.long 0x34 20. "E52,Event #52" "0,1" newline bitfld.long 0x34 19. "E51,Event #51" "0,1" bitfld.long 0x34 18. "E50,Event #50" "0,1" newline bitfld.long 0x34 17. "E49,Event #49" "0,1" bitfld.long 0x34 16. "E48,Event #48" "0,1" newline bitfld.long 0x34 15. "E47,Event #47" "0,1" bitfld.long 0x34 14. "E46,Event #46" "0,1" newline bitfld.long 0x34 13. "E45,Event #45" "0,1" bitfld.long 0x34 12. "E44,Event #44" "0,1" newline bitfld.long 0x34 11. "E43,Event #43" "0,1" bitfld.long 0x34 10. "E42,Event #42" "0,1" newline bitfld.long 0x34 9. "E41,Event #41" "0,1" bitfld.long 0x34 8. "E40,Event #40" "0,1" newline bitfld.long 0x34 7. "E39,Event #39" "0,1" bitfld.long 0x34 6. "E38,Event #38" "0,1" newline bitfld.long 0x34 5. "E37,Event #37" "0,1" bitfld.long 0x34 4. "E36,Event #36" "0,1" newline bitfld.long 0x34 3. "E35,Event #35" "0,1" bitfld.long 0x34 2. "E34,Event #34" "0,1" newline bitfld.long 0x34 1. "E33,Event #33" "0,1" bitfld.long 0x34 0. "E32,Event #32" "0,1" line.long 0x38 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x38 31. "E31,Event #31" "0,1" bitfld.long 0x38 30. "E30,Event #30" "0,1" newline bitfld.long 0x38 29. "E29,Event #29" "0,1" bitfld.long 0x38 28. "E28,Event #28" "0,1" newline bitfld.long 0x38 27. "E27,Event #27" "0,1" bitfld.long 0x38 26. "E26,Event #26" "0,1" newline bitfld.long 0x38 25. "E25,Event #25" "0,1" bitfld.long 0x38 24. "E24,Event #24" "0,1" newline bitfld.long 0x38 23. "E23,Event #23" "0,1" bitfld.long 0x38 22. "E22,Event #22" "0,1" newline bitfld.long 0x38 21. "E21,Event #21" "0,1" bitfld.long 0x38 20. "E20,Event #20" "0,1" newline bitfld.long 0x38 19. "E19,Event #19" "0,1" bitfld.long 0x38 18. "E18,Event #18" "0,1" newline bitfld.long 0x38 17. "E17,Event #17" "0,1" bitfld.long 0x38 16. "E16,Event #16" "0,1" newline bitfld.long 0x38 15. "E15,Event #15" "0,1" bitfld.long 0x38 14. "E14,Event #14" "0,1" newline bitfld.long 0x38 13. "E13,Event #13" "0,1" bitfld.long 0x38 12. "E12,Event #12" "0,1" newline bitfld.long 0x38 11. "E11,Event #11" "0,1" bitfld.long 0x38 10. "E10,Event #10" "0,1" newline bitfld.long 0x38 9. "E9,Event #9" "0,1" bitfld.long 0x38 8. "E8,Event #8" "0,1" newline bitfld.long 0x38 7. "E7,Event #7" "0,1" bitfld.long 0x38 6. "E6,Event #6" "0,1" newline bitfld.long 0x38 5. "E5,Event #5" "0,1" bitfld.long 0x38 4. "E4,Event #4" "0,1" newline bitfld.long 0x38 3. "E3,Event #3" "0,1" bitfld.long 0x38 2. "E2,Event #2" "0,1" newline bitfld.long 0x38 1. "E1,Event #1" "0,1" bitfld.long 0x38 0. "E0,Event #0" "0,1" line.long 0x3C "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x3C 31. "E63,Event #63" "0,1" bitfld.long 0x3C 30. "E62,Event #62" "0,1" newline bitfld.long 0x3C 29. "E61,Event #61" "0,1" bitfld.long 0x3C 28. "E60,Event #60" "0,1" newline bitfld.long 0x3C 27. "E59,Event #59" "0,1" bitfld.long 0x3C 26. "E58,Event #58" "0,1" newline bitfld.long 0x3C 25. "E57,Event #57" "0,1" bitfld.long 0x3C 24. "E56,Event #56" "0,1" newline bitfld.long 0x3C 23. "E55,Event #55" "0,1" bitfld.long 0x3C 22. "E54,Event #54" "0,1" newline bitfld.long 0x3C 21. "E53,Event #53" "0,1" bitfld.long 0x3C 20. "E52,Event #52" "0,1" newline bitfld.long 0x3C 19. "E51,Event #51" "0,1" bitfld.long 0x3C 18. "E50,Event #50" "0,1" newline bitfld.long 0x3C 17. "E49,Event #49" "0,1" bitfld.long 0x3C 16. "E48,Event #48" "0,1" newline bitfld.long 0x3C 15. "E47,Event #47" "0,1" bitfld.long 0x3C 14. "E46,Event #46" "0,1" newline bitfld.long 0x3C 13. "E45,Event #45" "0,1" bitfld.long 0x3C 12. "E44,Event #44" "0,1" newline bitfld.long 0x3C 11. "E43,Event #43" "0,1" bitfld.long 0x3C 10. "E42,Event #42" "0,1" newline bitfld.long 0x3C 9. "E41,Event #41" "0,1" bitfld.long 0x3C 8. "E40,Event #40" "0,1" newline bitfld.long 0x3C 7. "E39,Event #39" "0,1" bitfld.long 0x3C 6. "E38,Event #38" "0,1" newline bitfld.long 0x3C 5. "E37,Event #37" "0,1" bitfld.long 0x3C 4. "E36,Event #36" "0,1" newline bitfld.long 0x3C 3. "E35,Event #35" "0,1" bitfld.long 0x3C 2. "E34,Event #34" "0,1" newline bitfld.long 0x3C 1. "E33,Event #33" "0,1" bitfld.long 0x3C 0. "E32,Event #32" "0,1" line.long 0x40 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x40 31. "E31,Event #31" "0,1" bitfld.long 0x40 30. "E30,Event #30" "0,1" newline bitfld.long 0x40 29. "E29,Event #29" "0,1" bitfld.long 0x40 28. "E28,Event #28" "0,1" newline bitfld.long 0x40 27. "E27,Event #27" "0,1" bitfld.long 0x40 26. "E26,Event #26" "0,1" newline bitfld.long 0x40 25. "E25,Event #25" "0,1" bitfld.long 0x40 24. "E24,Event #24" "0,1" newline bitfld.long 0x40 23. "E23,Event #23" "0,1" bitfld.long 0x40 22. "E22,Event #22" "0,1" newline bitfld.long 0x40 21. "E21,Event #21" "0,1" bitfld.long 0x40 20. "E20,Event #20" "0,1" newline bitfld.long 0x40 19. "E19,Event #19" "0,1" bitfld.long 0x40 18. "E18,Event #18" "0,1" newline bitfld.long 0x40 17. "E17,Event #17" "0,1" bitfld.long 0x40 16. "E16,Event #16" "0,1" newline bitfld.long 0x40 15. "E15,Event #15" "0,1" bitfld.long 0x40 14. "E14,Event #14" "0,1" newline bitfld.long 0x40 13. "E13,Event #13" "0,1" bitfld.long 0x40 12. "E12,Event #12" "0,1" newline bitfld.long 0x40 11. "E11,Event #11" "0,1" bitfld.long 0x40 10. "E10,Event #10" "0,1" newline bitfld.long 0x40 9. "E9,Event #9" "0,1" bitfld.long 0x40 8. "E8,Event #8" "0,1" newline bitfld.long 0x40 7. "E7,Event #7" "0,1" bitfld.long 0x40 6. "E6,Event #6" "0,1" newline bitfld.long 0x40 5. "E5,Event #5" "0,1" bitfld.long 0x40 4. "E4,Event #4" "0,1" newline bitfld.long 0x40 3. "E3,Event #3" "0,1" bitfld.long 0x40 2. "E2,Event #2" "0,1" newline bitfld.long 0x40 1. "E1,Event #1" "0,1" bitfld.long 0x40 0. "E0,Event #0" "0,1" line.long 0x44 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x44 31. "E63,Event #63" "0,1" bitfld.long 0x44 30. "E62,Event #62" "0,1" newline bitfld.long 0x44 29. "E61,Event #61" "0,1" bitfld.long 0x44 28. "E60,Event #60" "0,1" newline bitfld.long 0x44 27. "E59,Event #59" "0,1" bitfld.long 0x44 26. "E58,Event #58" "0,1" newline bitfld.long 0x44 25. "E57,Event #57" "0,1" bitfld.long 0x44 24. "E56,Event #56" "0,1" newline bitfld.long 0x44 23. "E55,Event #55" "0,1" bitfld.long 0x44 22. "E54,Event #54" "0,1" newline bitfld.long 0x44 21. "E53,Event #53" "0,1" bitfld.long 0x44 20. "E52,Event #52" "0,1" newline bitfld.long 0x44 19. "E51,Event #51" "0,1" bitfld.long 0x44 18. "E50,Event #50" "0,1" newline bitfld.long 0x44 17. "E49,Event #49" "0,1" bitfld.long 0x44 16. "E48,Event #48" "0,1" newline bitfld.long 0x44 15. "E47,Event #47" "0,1" bitfld.long 0x44 14. "E46,Event #46" "0,1" newline bitfld.long 0x44 13. "E45,Event #45" "0,1" bitfld.long 0x44 12. "E44,Event #44" "0,1" newline bitfld.long 0x44 11. "E43,Event #43" "0,1" bitfld.long 0x44 10. "E42,Event #42" "0,1" newline bitfld.long 0x44 9. "E41,Event #41" "0,1" bitfld.long 0x44 8. "E40,Event #40" "0,1" newline bitfld.long 0x44 7. "E39,Event #39" "0,1" bitfld.long 0x44 6. "E38,Event #38" "0,1" newline bitfld.long 0x44 5. "E37,Event #37" "0,1" bitfld.long 0x44 4. "E36,Event #36" "0,1" newline bitfld.long 0x44 3. "E35,Event #35" "0,1" bitfld.long 0x44 2. "E34,Event #34" "0,1" newline bitfld.long 0x44 1. "E33,Event #33" "0,1" bitfld.long 0x44 0. "E32,Event #32" "0,1" rgroup.long 0x1050++0x2B line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x08 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x0C "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x10 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x14 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x18 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x1C "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x20 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x24 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x28 "EDMA_TPCC_IEVAL,Interrupt Eval Register" hexmask.long 0x28 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" newline bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1080++0x17 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 7. "E7,Event #7" "0,1" newline rbitfld.long 0x04 6. "E6,Event #6" "0,1" rbitfld.long 0x04 5. "E5,Event #5" "0,1" newline rbitfld.long 0x04 4. "E4,Event #4" "0,1" rbitfld.long 0x04 3. "E3,Event #3" "0,1" newline rbitfld.long 0x04 2. "E2,Event #2" "0,1" rbitfld.long 0x04 1. "E1,Event #1" "0,1" newline rbitfld.long 0x04 0. "E0,Event #0" "0,1" line.long 0x08 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,Event #7" "0,1" newline bitfld.long 0x08 6. "E6,Event #6" "0,1" bitfld.long 0x08 5. "E5,Event #5" "0,1" newline bitfld.long 0x08 4. "E4,Event #4" "0,1" bitfld.long 0x08 3. "E3,Event #3" "0,1" newline bitfld.long 0x08 2. "E2,Event #2" "0,1" bitfld.long 0x08 1. "E1,Event #1" "0,1" newline bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,Event #7" "0,1" newline bitfld.long 0x0C 6. "E6,Event #6" "0,1" bitfld.long 0x0C 5. "E5,Event #5" "0,1" newline bitfld.long 0x0C 4. "E4,Event #4" "0,1" bitfld.long 0x0C 3. "E3,Event #3" "0,1" newline bitfld.long 0x0C 2. "E2,Event #2" "0,1" bitfld.long 0x0C 1. "E1,Event #1" "0,1" newline bitfld.long 0x0C 0. "E0,Event #0" "0,1" line.long 0x10 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 7. "E7,Event #7" "0,1" newline rbitfld.long 0x10 6. "E6,Event #6" "0,1" rbitfld.long 0x10 5. "E5,Event #5" "0,1" newline rbitfld.long 0x10 4. "E4,Event #4" "0,1" rbitfld.long 0x10 3. "E3,Event #3" "0,1" newline rbitfld.long 0x10 2. "E2,Event #2" "0,1" rbitfld.long 0x10 1. "E1,Event #1" "0,1" newline rbitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event #7" "0,1" newline bitfld.long 0x14 6. "E6,Event #6" "0,1" bitfld.long 0x14 5. "E5,Event #5" "0,1" newline bitfld.long 0x14 4. "E4,Event #4" "0,1" bitfld.long 0x14 3. "E3,Event #3" "0,1" newline bitfld.long 0x14 2. "E2,Event #2" "0,1" bitfld.long 0x14 1. "E1,Event #1" "0,1" newline bitfld.long 0x14 0. "E0,Event #0" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2200++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2600++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2204++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2604++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2208++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2608++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x220C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x260C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2210++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2610++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2214++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2614++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2218++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2618++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x221C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x261C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2220++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2620++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2224++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2624++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2228++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2628++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x222C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x262C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2230++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2630++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2234++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2634++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2238++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2638++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x223C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x263C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2240++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2640++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2244++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2644++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2250++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2650++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2254++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2654++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2258++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2658++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x225C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x265C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2260++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2660++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2264++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2664++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2268++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2668++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x226C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x266C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2270++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2670++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2274++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2674++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2278++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2678++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2A78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2C78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2E78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2280++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2680++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2284++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2684++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2288++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2688++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x228C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x268C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2290++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2690++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2294++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2694++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4020++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_1,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4060++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_3,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_5,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_6,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_7,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4100++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_8,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4120++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_9,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4140++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4160++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_11,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4180++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_12,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_13,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_14,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_15,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4200++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4220++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_17,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4240++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_18,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4260++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_19,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4280++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_20,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_21,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_22,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_23,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4300++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_24,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4320++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_25,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4340++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_26,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4360++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_27,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4380++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_28,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_29,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_30,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_31,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4400++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4420++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_33,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4440++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_34,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4460++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_35,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4480++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_36,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_37,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_38,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_39,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4500++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_40,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4520++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_41,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4540++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_42,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4560++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_43,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4580++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_44,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_45,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_46,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_47,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4600++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4620++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_49,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4640++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_50,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4660++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_51,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4680++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_52,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_53,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_54,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_55,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4700++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_56,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4720++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_57,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4740++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_58,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4760++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_59,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4780++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_60,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_61,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_62,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_63,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4800++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4820++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_65,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4840++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_66,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4860++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_67,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4880++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_68,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_69,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_70,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_71,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4900++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_72,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4920++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_73,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4940++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_74,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4960++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_75,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4980++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_76,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_77,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_78,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_79,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_81,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_82,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_83,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_84,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_85,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_86,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_87,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_88,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_89,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_90,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_91,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_92,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_93,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_94,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_95,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_96,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_97,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_98,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_99,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_101,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_102,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_103,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_104,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_105,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_106,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_107,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_108,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_109,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_110,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_111,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_113,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_114,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_115,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_116,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_117,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_118,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_119,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_120,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_121,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_122,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_123,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_124,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_125,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_126,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_127,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" group.long 0x4024++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_1,Source Address" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" group.long 0x4064++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_3,Source Address" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" group.long 0x40A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_5,Source Address" group.long 0x40C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_6,Source Address" group.long 0x40E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_7,Source Address" group.long 0x4104++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_8,Source Address" group.long 0x4124++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_9,Source Address" group.long 0x4144++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_10,Source Address" group.long 0x4164++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_11,Source Address" group.long 0x4184++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_12,Source Address" group.long 0x41A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_13,Source Address" group.long 0x41C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_14,Source Address" group.long 0x41E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_15,Source Address" group.long 0x4204++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_16,Source Address" group.long 0x4224++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_17,Source Address" group.long 0x4244++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_18,Source Address" group.long 0x4264++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_19,Source Address" group.long 0x4284++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_20,Source Address" group.long 0x42A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_21,Source Address" group.long 0x42C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_22,Source Address" group.long 0x42E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_23,Source Address" group.long 0x4304++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_24,Source Address" group.long 0x4324++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_25,Source Address" group.long 0x4344++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_26,Source Address" group.long 0x4364++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_27,Source Address" group.long 0x4384++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_28,Source Address" group.long 0x43A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_29,Source Address" group.long 0x43C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_30,Source Address" group.long 0x43E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_31,Source Address" group.long 0x4404++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_32,Source Address" group.long 0x4424++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_33,Source Address" group.long 0x4444++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_34,Source Address" group.long 0x4464++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_35,Source Address" group.long 0x4484++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_36,Source Address" group.long 0x44A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_37,Source Address" group.long 0x44C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_38,Source Address" group.long 0x44E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_39,Source Address" group.long 0x4504++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_40,Source Address" group.long 0x4524++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_41,Source Address" group.long 0x4544++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_42,Source Address" group.long 0x4564++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_43,Source Address" group.long 0x4584++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_44,Source Address" group.long 0x45A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_45,Source Address" group.long 0x45C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_46,Source Address" group.long 0x45E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_47,Source Address" group.long 0x4604++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_48,Source Address" group.long 0x4624++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_49,Source Address" group.long 0x4644++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_50,Source Address" group.long 0x4664++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_51,Source Address" group.long 0x4684++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_52,Source Address" group.long 0x46A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_53,Source Address" group.long 0x46C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_54,Source Address" group.long 0x46E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_55,Source Address" group.long 0x4704++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_56,Source Address" group.long 0x4724++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_57,Source Address" group.long 0x4744++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_58,Source Address" group.long 0x4764++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_59,Source Address" group.long 0x4784++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_60,Source Address" group.long 0x47A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_61,Source Address" group.long 0x47C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_62,Source Address" group.long 0x47E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_63,Source Address" group.long 0x4804++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_64,Source Address" group.long 0x4824++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_65,Source Address" group.long 0x4844++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_66,Source Address" group.long 0x4864++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_67,Source Address" group.long 0x4884++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_68,Source Address" group.long 0x48A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_69,Source Address" group.long 0x48C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_70,Source Address" group.long 0x48E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_71,Source Address" group.long 0x4904++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_72,Source Address" group.long 0x4924++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_73,Source Address" group.long 0x4944++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_74,Source Address" group.long 0x4964++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_75,Source Address" group.long 0x4984++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_76,Source Address" group.long 0x49A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_77,Source Address" group.long 0x49C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_78,Source Address" group.long 0x49E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_79,Source Address" group.long 0x4A04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_80,Source Address" group.long 0x4A24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_81,Source Address" group.long 0x4A44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_82,Source Address" group.long 0x4A64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_83,Source Address" group.long 0x4A84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_84,Source Address" group.long 0x4AA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_85,Source Address" group.long 0x4AC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_86,Source Address" group.long 0x4AE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_87,Source Address" group.long 0x4B04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_88,Source Address" group.long 0x4B24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_89,Source Address" group.long 0x4B44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_90,Source Address" group.long 0x4B64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_91,Source Address" group.long 0x4B84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_92,Source Address" group.long 0x4BA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_93,Source Address" group.long 0x4BC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_94,Source Address" group.long 0x4BE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_95,Source Address" group.long 0x4C04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_96,Source Address" group.long 0x4C24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_97,Source Address" group.long 0x4C44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_98,Source Address" group.long 0x4C64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_99,Source Address" group.long 0x4C84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_100,Source Address" group.long 0x4CA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_101,Source Address" group.long 0x4CC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_102,Source Address" group.long 0x4CE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_103,Source Address" group.long 0x4D04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_104,Source Address" group.long 0x4D24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_105,Source Address" group.long 0x4D44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_106,Source Address" group.long 0x4D64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_107,Source Address" group.long 0x4D84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_108,Source Address" group.long 0x4DA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_109,Source Address" group.long 0x4DC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_110,Source Address" group.long 0x4DE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_111,Source Address" group.long 0x4E04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_112,Source Address" group.long 0x4E24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_113,Source Address" group.long 0x4E44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_114,Source Address" group.long 0x4E64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_115,Source Address" group.long 0x4E84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_116,Source Address" group.long 0x4EA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_117,Source Address" group.long 0x4EC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_118,Source Address" group.long 0x4EE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_119,Source Address" group.long 0x4F04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_120,Source Address" group.long 0x4F24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_121,Source Address" group.long 0x4F44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_122,Source Address" group.long 0x4F64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_123,Source Address" group.long 0x4F84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_124,Source Address" group.long 0x4FA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_125,Source Address" group.long 0x4FC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_126,Source Address" group.long 0x4FE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_127,Source Address" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x402C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_1,Destination Address" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x406C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_3,Destination Address" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x40AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_5,Destination Address" group.long 0x40CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_6,Destination Address" group.long 0x40EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_7,Destination Address" group.long 0x410C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_8,Destination Address" group.long 0x412C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_9,Destination Address" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x416C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_11,Destination Address" group.long 0x418C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_12,Destination Address" group.long 0x41AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_13,Destination Address" group.long 0x41CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_14,Destination Address" group.long 0x41EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_15,Destination Address" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x422C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_17,Destination Address" group.long 0x424C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_18,Destination Address" group.long 0x426C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_19,Destination Address" group.long 0x428C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_20,Destination Address" group.long 0x42AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_21,Destination Address" group.long 0x42CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_22,Destination Address" group.long 0x42EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_23,Destination Address" group.long 0x430C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_24,Destination Address" group.long 0x432C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_25,Destination Address" group.long 0x434C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_26,Destination Address" group.long 0x436C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_27,Destination Address" group.long 0x438C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_28,Destination Address" group.long 0x43AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_29,Destination Address" group.long 0x43CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_30,Destination Address" group.long 0x43EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_31,Destination Address" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x442C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_33,Destination Address" group.long 0x444C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_34,Destination Address" group.long 0x446C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_35,Destination Address" group.long 0x448C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_36,Destination Address" group.long 0x44AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_37,Destination Address" group.long 0x44CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_38,Destination Address" group.long 0x44EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_39,Destination Address" group.long 0x450C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_40,Destination Address" group.long 0x452C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_41,Destination Address" group.long 0x454C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_42,Destination Address" group.long 0x456C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_43,Destination Address" group.long 0x458C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_44,Destination Address" group.long 0x45AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_45,Destination Address" group.long 0x45CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_46,Destination Address" group.long 0x45EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_47,Destination Address" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x462C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_49,Destination Address" group.long 0x464C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_50,Destination Address" group.long 0x466C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_51,Destination Address" group.long 0x468C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_52,Destination Address" group.long 0x46AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_53,Destination Address" group.long 0x46CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_54,Destination Address" group.long 0x46EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_55,Destination Address" group.long 0x470C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_56,Destination Address" group.long 0x472C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_57,Destination Address" group.long 0x474C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_58,Destination Address" group.long 0x476C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_59,Destination Address" group.long 0x478C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_60,Destination Address" group.long 0x47AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_61,Destination Address" group.long 0x47CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_62,Destination Address" group.long 0x47EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_63,Destination Address" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x482C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_65,Destination Address" group.long 0x484C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_66,Destination Address" group.long 0x486C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_67,Destination Address" group.long 0x488C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_68,Destination Address" group.long 0x48AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_69,Destination Address" group.long 0x48CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_70,Destination Address" group.long 0x48EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_71,Destination Address" group.long 0x490C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_72,Destination Address" group.long 0x492C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_73,Destination Address" group.long 0x494C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_74,Destination Address" group.long 0x496C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_75,Destination Address" group.long 0x498C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_76,Destination Address" group.long 0x49AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_77,Destination Address" group.long 0x49CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_78,Destination Address" group.long 0x49EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_79,Destination Address" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_81,Destination Address" group.long 0x4A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_82,Destination Address" group.long 0x4A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_83,Destination Address" group.long 0x4A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_84,Destination Address" group.long 0x4AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_85,Destination Address" group.long 0x4ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_86,Destination Address" group.long 0x4AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_87,Destination Address" group.long 0x4B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_88,Destination Address" group.long 0x4B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_89,Destination Address" group.long 0x4B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_90,Destination Address" group.long 0x4B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_91,Destination Address" group.long 0x4B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_92,Destination Address" group.long 0x4BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_93,Destination Address" group.long 0x4BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_94,Destination Address" group.long 0x4BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_95,Destination Address" group.long 0x4C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_96,Destination Address" group.long 0x4C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_97,Destination Address" group.long 0x4C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_98,Destination Address" group.long 0x4C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_99,Destination Address" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_101,Destination Address" group.long 0x4CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_102,Destination Address" group.long 0x4CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_103,Destination Address" group.long 0x4D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_104,Destination Address" group.long 0x4D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_105,Destination Address" group.long 0x4D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_106,Destination Address" group.long 0x4D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_107,Destination Address" group.long 0x4D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_108,Destination Address" group.long 0x4DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_109,Destination Address" group.long 0x4DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_110,Destination Address" group.long 0x4DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_111,Destination Address" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_113,Destination Address" group.long 0x4E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_114,Destination Address" group.long 0x4E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_115,Destination Address" group.long 0x4E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_116,Destination Address" group.long 0x4EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_117,Destination Address" group.long 0x4ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_118,Destination Address" group.long 0x4EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_119,Destination Address" group.long 0x4F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_120,Destination Address" group.long 0x4F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_121,Destination Address" group.long 0x4F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_122,Destination Address" group.long 0x4F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_123,Destination Address" group.long 0x4F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_124,Destination Address" group.long 0x4FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_125,Destination Address" group.long 0x4FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_126,Destination Address" group.long 0x4FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_127,Destination Address" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_1," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_3," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_5," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_6," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_7," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_8," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_9," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_11," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_12," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_13," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_14," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_15," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_17," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_18," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_19," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_20," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_21," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_22," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_23," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_24," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_25," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_26," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_27," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_28," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_29," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_30," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_31," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_33," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_34," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_35," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_36," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_37," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_38," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_39," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_40," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_41," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_42," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_43," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_44," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_45," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_46," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_47," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_49," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_50," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_51," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_52," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_53," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_54," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_55," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_56," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_57," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_58," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_59," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_60," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_61," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_62," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_63," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_65," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_66," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_67," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_68," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_69," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_70," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_71," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_72," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_73," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_74," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_75," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_76," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_77," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_78," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_79," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_81," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_82," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_83," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_84," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_85," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_86," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_87," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_88," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_89," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_90," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_91," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_92," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_93," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_94," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_95," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_96," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_97," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_98," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_99," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_101," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_102," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_103," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_104," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_105," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_106," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_107," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_108," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_109," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_110," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_111," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_113," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_114," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_115," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_116," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_117," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_118," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_119," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_120," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_121," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_122," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_123," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_124," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_125," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_126," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_127," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x403C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x407C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x411C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x413C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x417C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x419C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x423C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x425C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x427C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x429C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x431C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x433C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x435C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x437C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x439C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x443C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x445C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x447C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x449C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x451C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x453C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x455C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x457C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x459C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x463C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x465C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x467C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x469C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x471C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x473C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x475C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x477C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x479C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x483C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x485C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x487C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x489C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x491C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x493C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x495C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x497C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x499C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x1D05000 ad:0x1D06000 ) tree "DSP_EDMA_TPTC$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPTCn_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPTCn_TCCFG,TC Configuration Register" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 8.--9. "DREGDEPTH,Destination Register FIFO Depth Parameterization" "0,1,2,3" bitfld.long 0x04 6.--7. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" group.long 0x100++0x13 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 11.--12. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" rbitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" rbitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" line.long 0x04 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" rbitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x08 "EDMA_TPTCn_INTEN,Interrupt Enable Register" hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x0C "EDMA_TPTCn_INTCLR,Interrupt Clear Register" hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x10 "EDMA_TPTCn_INTCMD,Interrupt Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" group.long 0x120++0x13 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" rbitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 1. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" line.long 0x04 "EDMA_TPTCn_ERREN,Error Enable Register" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x04 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x04 1. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" line.long 0x08 "EDMA_TPTCn_ERRCLR,Error Clear Register" hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x08 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x08 1. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" line.long 0x0C "EDMA_TPTCn_ERRDET,Error Details Register" hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0C 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" rbitfld.long 0x0C 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 14.--15. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EDMA_TPTCn_ERRCMD,Error Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" group.long 0x200++0x17 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" rbitfld.long 0x00 21. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" rbitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "Highest priority,Priority 1,?,?,?,?,?,Lowest priority" newline rbitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" line.long 0x08 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count" line.long 0x0C "EDMA_TPTCn_PDST,Program Set Destination Address" line.long 0x10 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" line.long 0x14 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x240++0x23 line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" line.long 0x08 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" line.long 0x0C "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved. return 0x0 w/o AERROR" line.long 0x10 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" line.long 0x14 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" line.long 0x1C "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" line.long 0x20 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" group.long 0x280++0x0B line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" line.long 0x04 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" line.long 0x08 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" group.long 0x300++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x304++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x344++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x308++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x348++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x30C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x34C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x350++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" group.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x354++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end repeat.end tree "DSP_FW_L2_NOC_CFG" base ad:0x1D03000 group.long 0x00++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0,Core 0 Error log register" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" newline rbitfld.long 0x00 26. "RESERVED," "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" bitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x40++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 2.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x88++0x17 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" line.long 0x08 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1,Start physical address of region 1" hexmask.long 0x08 4.--31. 1. "RESERVED," bitfld.long 0x08 0.--3. "START_REGION_1,Physical target start address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1,End physical address of region 1" bitfld.long 0x0C 31. "END_REGION_1_ENABLE,End Region 1 enable" "0,1" hexmask.long 0x0C 4.--30. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "END_REGION_1,Physical target end address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_1,RM_PERMISSION_REGION_1_LOW register" hexmask.long.word 0x10 16.--31. 1. "RESERVED," bitfld.long 0x10 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x10 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x10 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x10 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x10 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x10 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x10 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x10 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x10 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_1,RM_PERMISSION_REGION_1_HIGH register" bitfld.long 0x14 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x14 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x14 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x14 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x14 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x14 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x14 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x14 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x14 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x14 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x14 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x14 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x14 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x14 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x14 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x14 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x14 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x14 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x14 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x14 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x14 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x14 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x14 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x14 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x14 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x14 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x14 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x14 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x14 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x14 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x14 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x14 0. "R0,Initiator ID0 permission" "0,1" group.long 0x1000++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0,Core 0 Error log register" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" newline rbitfld.long 0x00 26. "RESERVED," "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" bitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x1040++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 2.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x1088++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" rgroup.long 0x4000++0x17 line.long 0x00 "DSPNOC_FLAGMUX_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_FLAGMUX_ID_REVISIONID," line.long 0x08 "DSPNOC_FLAGMUX_FAULTEN," hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "FAULTEN,Global Fault Enable register" "0,1" line.long 0x0C "DSPNOC_FLAGMUX_FAULTSTATUS," hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "FAULTSTATUS,Global Fault Status register" "0,1" line.long 0x10 "DSPNOC_FLAGMUX_FLAGINEN0," hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" line.long 0x14 "DSPNOC_FLAGMUX_FLAGINSTATUS0," hexmask.long 0x14 1.--31. 1. "RESERVED," bitfld.long 0x14 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" rgroup.long 0x4200++0x1B line.long 0x00 "DSPNOC_ERRORLOG_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_ERRORLOG_ID_REVISIONID," line.long 0x08 "DSPNOC_ERRORLOG_FAULTEN," hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "FAULTEN,Enable Fault output" "0,1" line.long 0x0C "DSPNOC_ERRORLOG_ERRVLD," hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "ERRVLD,Error logged Valid" "0,1" line.long 0x10 "DSPNOC_ERRORLOG_ERRCLR," hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "ERRCLR,Clr ErrVld status" "0,1" line.long 0x14 "DSPNOC_ERRORLOG_ERRLOG0,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x14 31. "FORMAT,Format of ErrLog0 register" "0,1" bitfld.long 0x14 28.--30. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--27. 1. "LEN1,Header: Len1 value" bitfld.long 0x14 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x14 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0. "LOCK,Header: Lock bit value" "0,1" line.long 0x18 "DSPNOC_ERRORLOG_ERRLOG1," hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED," hexmask.long.word 0x18 0.--14. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x4220++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG3," bitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 0.--30. 1. "ERRLOG3,Header: Addr lsb value" rgroup.long 0x4228++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG5," hexmask.long.word 0x00 22.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--21. 1. "ERRLOG5,Header: User lsb value" width 0x0B tree.end tree "DSP_SYSTEM" base ad:0x1D00000 rgroup.long 0x00++0x1B line.long 0x00 "DSP_SYS_REVISION," line.long 0x04 "DSP_SYS_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," bitfld.long 0x04 0.--3. "NUM,Instance Number Set by subsystem input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DSP_SYS_SYSCONFIG," hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 8. "RESERVED,Reserved" "0,1" rbitfld.long 0x08 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x08 4.--5. "STANDBYMODE," "?,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x08 2.--3. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x08 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x0C "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode" hexmask.long 0x0C 6.--31. 1. "RESERVED," bitfld.long 0x0C 4.--5. "OCPI_DISC_STAT,L3_MAIN (OCP) Initiator(s) Disconnect Status" "OCPI_DISC_STAT_0_r,OCPI_DISC_STAT_1_r,OCPI_DISC_STAT_2_r,?" bitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "TC1_STAT,EDMA TC1 Status" "TC1_STAT_0,TC1_STAT_1" bitfld.long 0x0C 1. "TC0_STAT,EDMA TC0 Status" "TC0_STAT_0,TC0_STAT_1" bitfld.long 0x0C 0. "C66X_STAT,C66x Status" "C66X_STAT_0,C66X_STAT_1" line.long 0x10 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "OCPI_DISC,OCP Initiator (on L3_MAIN) Disconnect request" "OCPI_DISC_0_w,OCPI_DISC_1_w" line.long 0x14 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators" rbitfld.long 0x14 31. "RESERVED," "0,1" bitfld.long 0x14 28.--30. "SDMA_PRI,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port" "0,1,2,3,4,5,6,7" rbitfld.long 0x14 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 24. "NOPOSTOVERRIDE,OCP Posted Write vs Non-Posted Write override" "NOPOSTOVERRIDE_0,NOPOSTOVERRIDE_1" rbitfld.long 0x14 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x14 20.--21. "SDMA_L2PRES,OCP Target port L2 Interconnect Pressure" "SDMA_L2PRES_0,SDMA_L2PRES_1,SDMA_L2PRES_2,SDMA_L2PRES_3" newline rbitfld.long 0x14 18.--19. "RESERVED," "0,1,2,3" bitfld.long 0x14 16.--17. "CFG_L2PRES,DSP CFG L2 Interconnect Pressure" "CFG_L2PRES_0,CFG_L2PRES_1,CFG_L2PRES_2,CFG_L2PRES_3" rbitfld.long 0x14 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 12.--13. "TC1_L2PRES,TC1 L2 Interconnect Pressure" "TC1_L2PRES_0,TC1_L2PRES_1,TC1_L2PRES_2,TC1_L2PRES_3" rbitfld.long 0x14 10.--11. "RESERVED," "0,1,2,3" bitfld.long 0x14 8.--9. "TC0_L2PRES,TC0 L2 Interconnect Pressure" "TC0_L2PRES_0,TC0_L2PRES_1,TC0_L2PRES_2,TC0_L2PRES_3" newline rbitfld.long 0x14 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x14 4.--5. "TC1_DBS,TC1 Default Burst size" "TC1_DBS_0,TC1_DBS_1,TC1_DBS_2,TC1_DBS_3" rbitfld.long 0x14 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 0.--1. "TC0_DBS,TC0 Default Burst size" "TC0_DBS_0,TC0_DBS_1,TC0_DBS_2,TC0_DBS_3" line.long 0x18 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs" hexmask.long.tbyte 0x18 13.--31. 1. "RESERVED," bitfld.long 0x18 12. "MMU1_ABORT,MU1 Abort" "MMU1_ABORT_0,MMU1_ABORT_1" rbitfld.long 0x18 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "MMU0_ABORT,MU0 Abort" "MMU0_ABORT_0,MMU0_ABORT_1" rbitfld.long 0x18 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 4. "MMU1_EN,MU1 Enable" "MMU1_EN_0,MMU1_EN_1" newline rbitfld.long 0x18 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 0. "MMU0_EN,MU1 Enable" "MMU0_EN_0,MMU0_EN_1" group.long 0x20++0x07 line.long 0x00 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x30++0x07 line.long 0x00 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x40++0x07 line.long 0x00 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state" line.long 0x04 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state" group.long 0x50++0x2F line.long 0x00 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.word 0x00 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--18. 1. "EVENT,Settable raw status for event #n" line.long 0x04 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector" hexmask.long.word 0x04 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x04 0.--18. 1. "EVENT,Clearable enabled status for event #n" line.long 0x08 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" hexmask.long.word 0x08 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x08 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x0C "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" hexmask.long.word 0x0C 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x0C 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x10 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x14 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x18 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x1C "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" line.long 0x20 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x24 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x28 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x2C "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" group.long 0xF8++0x07 line.long 0x00 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus" hexmask.long 0x00 4.--31. 1. "RESERVED," bitfld.long 0x00 0.--3. "GROUP,Debug Group output control mux selectN: GN = select output group N" "GROUP_0,GROUP_1,GROUP_2,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group" width 0x0B tree.end tree "DSS" base ad:0x58000000 rgroup.long 0x00++0x03 line.long 0x00 "DSS_REVISION,This register contains the DSS revision number" group.long 0x10++0x0F line.long 0x00 "DSS_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long.word 0x00 17.--31. 1. "RESERVED," rbitfld.long 0x00 16. "RESERVED," "0,1" hexmask.long.word 0x00 5.--15. 1. "RESERVED," newline rbitfld.long 0x00 4. "RESERVED," "0,1" rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "SIDLEMODE," "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" line.long 0x04 "DSS_SYSSTATUS,This register provides status information about the module" hexmask.long 0x04 7.--31. 1. "RESERVED," bitfld.long 0x04 6. "VENC_RESETDONE,Reset status of VENC module" "VENC_RESETDONE_0,VENC_RESETDONE_1" bitfld.long 0x04 5. "RESERVED," "0,1" newline bitfld.long 0x04 4. "RESERVED," "0,1" bitfld.long 0x04 3. "RESERVED," "0,1" bitfld.long 0x04 2. "RESERVED," "0,1" newline bitfld.long 0x04 1. "RESERVED," "0,1" bitfld.long 0x04 0. "DSS_RESETDONE,Reset status of DISPC/DSS" "DSS_RESETDONE_0,DSS_RESETDONE_1" line.long 0x08 "DSS_VENC_CTRL,This register contains control bits corresponding to the VENC instance in DSS" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 2. "DAC_POWERDN_BGZ,DAC power down band gap control" "DAC_POWERDN_BGZ_0,DAC_POWERDN_BGZ_1" bitfld.long 0x08 1. "DAC_DEMEN,DAC Dynamic Element Matching Enable" "DAC_DEMEN_0,DAC_DEMEN_1" newline bitfld.long 0x08 0. "VENC_CLOCK_4X_ENABLE,VENC Clock CLK4X Enable" "VENC_CLOCK_4X_ENABLE_0,VENC_CLOCK_4X_ENABLE_1" line.long 0x0C "DSS_DPI_CTRL,This register contains control bits corresponding to the DPI interface in DSS" hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "DPI_ENABLE,Enable DPI interface" "DPI_ENABLE_0,DPI_ENABLE_1" group.long 0x40++0x03 line.long 0x00 "DSS_DEBUG_CFG,Debug configuration" hexmask.long 0x00 3.--31. 1. "RESERVED," bitfld.long 0x00 0.--2. "CFG,Defines which debug bus to provide on the DSS debug bus connected at the top" "CFG_0,CFG_1,CFG_2,CFG_3,CFG_4,CFG_5,?,?" width 0x0B tree.end tree "DSS_CM_CORE" base ad:0x4A009100 group.long 0x00++0x0B line.long 0x00 "CM_DSS_CLKSTCTRL,This register enables the DSS domain power state transition" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "CLKACTIVITY_HDMI_PHY_GFCLK,This field indicates the state of the HDMI_PHY_GFCLK clock in the domain" "CLKACTIVITY_HDMI_PHY_GFCLK_0,CLKACTIVITY_HDMI_PHY_GFCLK_1" newline rbitfld.long 0x00 17. "CLKACTIVITY_HDMI_CEC_GFCLK,This field indicates the state of the HDMI_CEC_GFCLK clock in the domain" "CLKACTIVITY_HDMI_CEC_GFCLK_0,CLKACTIVITY_HDMI_CEC_GFCLK_1" rbitfld.long 0x00 16. "CLKACTIVITY_DSS_SYS_GFCLK,This field indicates the state of the DSS_SYS_GFCLK clock in the domain" "CLKACTIVITY_DSS_SYS_GFCLK_0,CLKACTIVITY_DSS_SYS_GFCLK_1" newline rbitfld.long 0x00 15. "CLKACTIVITY_DSS_L4_GICLK,This field indicates the state of the DSS_L4_GICLK clock in the domain" "CLKACTIVITY_DSS_L4_GICLK_0,CLKACTIVITY_DSS_L4_GICLK_1" rbitfld.long 0x00 14. "CLKACTIVITY_SDVENC_GFCLK,This field indicates the state of the SDVENC_GFCLK clock in the domain" "CLKACTIVITY_SDVENC_GFCLK_0,CLKACTIVITY_SDVENC_GFCLK_1" newline rbitfld.long 0x00 13. "CLKACTIVITY_BB2D_GFCLK,This field indicates the state of the BB2D_GFCLK clock in the domain" "CLKACTIVITY_BB2D_GFCLK_0,CLKACTIVITY_BB2D_GFCLK_1" rbitfld.long 0x00 12. "CLKACTIVITY_VIDEO2_DPLL_CLK,This field indicates the state of the VIDEO2_PHY_GFCLK clock in the domain" "CLKACTIVITY_VIDEO2_DPLL_CLK_0,CLKACTIVITY_VIDEO2_DPLL_CLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_HDMI_DPLL_CLK,This field indicates the state of the HDMI_DPLL_CLK clock in the domain" "CLKACTIVITY_HDMI_DPLL_CLK_0,CLKACTIVITY_HDMI_DPLL_CLK_1" rbitfld.long 0x00 10. "CLKACTIVITY_VIDEO1_DPLL_CLK,This field indicates the state of the VIDEO1_DPLL_CLK clock in the domain" "CLKACTIVITY_VIDEO1_DPLL_CLK_0,CLKACTIVITY_VIDEO1_DPLL_CLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_DSS_GFCLK,This field indicates the state of the DSS_GFCLK clock in the domain" "CLKACTIVITY_DSS_GFCLK_0,CLKACTIVITY_DSS_GFCLK_1" rbitfld.long 0x00 8. "CLKACTIVITY_DSS_L3_GICLK,This field indicates the state of the DSS_L3_GICLK clock in the domain" "CLKACTIVITY_DSS_L3_GICLK_0,CLKACTIVITY_DSS_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSS clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_DSS_STATICDEP,This register controls the static domain depedencies from DSS domain towards 'target' domains" hexmask.long 0x04 6.--31. 1. "RESERVED," rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" line.long 0x08 "CM_DSS_DYNAMICDEP,This register controls the dynamic domain depedencies from DSS domain towards 'target' domains" hexmask.long 0x08 6.--31. 1. "RESERVED," bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 domain" "L3MAIN1_DYNDEP_0,?" newline bitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20++0x03 line.long 0x00 "CM_DSS_DSS_CLKCTRL,This register manages the DSS clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 13. "OPTFCLKEN_VIDEO2_CLK,Optional functional clock control" "OPTFCLKEN_VIDEO2_CLK_0,OPTFCLKEN_VIDEO2_CLK_1" bitfld.long 0x00 12. "OPTFCLKEN_VIDEO1_CLK,Optional functional clock control" "OPTFCLKEN_VIDEO1_CLK_0,OPTFCLKEN_VIDEO1_CLK_1" newline bitfld.long 0x00 11. "OPTFCLKEN_32KHZ_CLK,Optional functional clock control" "OPTFCLKEN_32KHZ_CLK_0,OPTFCLKEN_32KHZ_CLK_1" bitfld.long 0x00 10. "OPTFCLKEN_HDMI_CLK,Optional functional clock control" "OPTFCLKEN_HDMI_CLK_0,OPTFCLKEN_HDMI_CLK_1" newline bitfld.long 0x00 9. "OPTFCLKEN_48MHZ_CLK,Optional functional clock control" "OPTFCLKEN_48MHZ_CLK_0,OPTFCLKEN_48MHZ_CLK_1" bitfld.long 0x00 8. "OPTFCLKEN_DSSCLK,Optional functional clock control" "OPTFCLKEN_DSSCLK_0,OPTFCLKEN_DSSCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x30++0x03 line.long 0x00 "CM_DSS_BB2D_CLKCTRL,This register manages the BB2D clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x3C++0x03 line.long 0x00 "CM_DSS_SDVENC_CLKCTRL,This register manages the SDVENC clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "DSS_FW" base ad:0x4A21C000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "DSS_FW_CFG_TARG" base ad:0x4A21D000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DSS_PRM" base ad:0x4AE07100 group.long 0x00++0x07 line.long 0x00 "PM_DSS_PWRSTCTRL,This register controls the DSS power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "DSS_MEM_ONSTATE,DSS_MEM state when domain is ON" "?,?,?,DSS_MEM_ONSTATE_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," rbitfld.long 0x00 8. "DSS_MEM_RETSTATE,DSS_MEM state when domain is RETENTION" "DSS_MEM_RETSTATE_0,?" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" rbitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION" "LOGICRETSTATE_0,?" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_DSS_PWRSTST,This register provides a status on the current DSS power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "DSS_MEM_STATEST,DSS_MEM state status" "DSS_MEM_STATEST_0,DSS_MEM_STATEST_1,DSS_MEM_STATEST_2,DSS_MEM_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x20++0x0B line.long 0x00 "PM_DSS_DSS_WKDEP,This register controls wakeup dependency based on DSS service requests" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x00 29. "WKUPDEP_DSI1_B_EVE4,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_EVE4_0,WKUPDEP_DSI1_B_EVE4_1" newline bitfld.long 0x00 28. "WKUPDEP_DSI1_B_EVE3,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_EVE3_0,WKUPDEP_DSI1_B_EVE3_1" bitfld.long 0x00 27. "WKUPDEP_DSI1_B_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_EVE2_0,WKUPDEP_DSI1_B_EVE2_1" newline bitfld.long 0x00 26. "WKUPDEP_DSI1_B_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_EVE1_0,WKUPDEP_DSI1_B_EVE1_1" bitfld.long 0x00 25. "WKUPDEP_DSI1_B_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_DSP2_0,WKUPDEP_DSI1_B_DSP2_1" newline bitfld.long 0x00 24. "WKUPDEP_DSI1_B_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_IPU1_0,WKUPDEP_DSI1_B_IPU1_1" bitfld.long 0x00 23. "WKUPDEP_DSI1_B_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_SDMA_0,WKUPDEP_DSI1_B_SDMA_1" newline bitfld.long 0x00 22. "WKUPDEP_DSI1_B_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_DSP1_0,WKUPDEP_DSI1_B_DSP1_1" bitfld.long 0x00 21. "WKUPDEP_DSI1_B_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_IPU2_0,WKUPDEP_DSI1_B_IPU2_1" newline bitfld.long 0x00 20. "WKUPDEP_DSI1_B_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_MPU_0,WKUPDEP_DSI1_B_MPU_1" bitfld.long 0x00 19. "WKUPDEP_DSI1_A_EVE4,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_EVE4_0,WKUPDEP_DSI1_A_EVE4_1" newline bitfld.long 0x00 18. "WKUPDEP_DSI1_A_EVE3,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_EVE3_0,WKUPDEP_DSI1_A_EVE3_1" bitfld.long 0x00 17. "WKUPDEP_DSI1_A_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_EVE2_0,WKUPDEP_DSI1_A_EVE2_1" newline bitfld.long 0x00 16. "WKUPDEP_DSI1_A_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_EVE1_0,WKUPDEP_DSI1_A_EVE1_1" bitfld.long 0x00 15. "WKUPDEP_DSI1_A_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_DSP2_0,WKUPDEP_DSI1_A_DSP2_1" newline bitfld.long 0x00 14. "WKUPDEP_DSI1_A_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_IPU1_0,WKUPDEP_DSI1_A_IPU1_1" bitfld.long 0x00 13. "WKUPDEP_DSI1_A_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_SDMA_0,WKUPDEP_DSI1_A_SDMA_1" newline bitfld.long 0x00 12. "WKUPDEP_DSI1_A_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_DSP1_0,WKUPDEP_DSI1_A_DSP1_1" bitfld.long 0x00 11. "WKUPDEP_DSI1_A_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_IPU2_0,WKUPDEP_DSI1_A_IPU2_1" newline bitfld.long 0x00 10. "WKUPDEP_DSI1_A_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_MPU_0,WKUPDEP_DSI1_A_MPU_1" bitfld.long 0x00 9. "WKUPDEP_DISPC_EVE4,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_EVE4_0,WKUPDEP_DISPC_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_DISPC_EVE3,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_EVE3_0,WKUPDEP_DISPC_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_DISPC_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_EVE2_0,WKUPDEP_DISPC_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_DISPC_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_EVE1_0,WKUPDEP_DISPC_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_DISPC_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_DSP2_0,WKUPDEP_DISPC_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_DISPC_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_IPU1_0,WKUPDEP_DISPC_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_DISPC_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_SDMA_0,WKUPDEP_DISPC_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_DISPC_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_DSP1_0,WKUPDEP_DISPC_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_DISPC_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_IPU2_0,WKUPDEP_DISPC_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_DISPC_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_MPU_0,WKUPDEP_DISPC_MPU_1" line.long 0x04 "RM_DSS_DSS_CONTEXT,This register contains dedicated DSS context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_DSS_MEM,Specify if memory-based context in DSS_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSS_MEM_0,LOSTMEM_DSS_MEM_1" newline rbitfld.long 0x04 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_DSS_DSS2_WKDEP,This register controls wakeup dependency based on DSS service requests" rbitfld.long 0x08 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 25. "WKUPDEP_HDMIDMA_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIDMA_DSP2_0,WKUPDEP_HDMIDMA_DSP2_1" newline rbitfld.long 0x08 24. "RESERVED," "0,1" bitfld.long 0x08 23. "WKUPDEP_HDMIDMA_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIDMA_SDMA_0,WKUPDEP_HDMIDMA_SDMA_1" newline bitfld.long 0x08 22. "WKUPDEP_HDMIDMA_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIDMA_DSP1_0,WKUPDEP_HDMIDMA_DSP1_1" rbitfld.long 0x08 20.--21. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 19. "WKUPDEP_DSI1_C_EVE4,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_EVE4_0,WKUPDEP_DSI1_C_EVE4_1" bitfld.long 0x08 18. "WKUPDEP_DSI1_C_EVE3,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_EVE3_0,WKUPDEP_DSI1_C_EVE3_1" newline bitfld.long 0x08 17. "WKUPDEP_DSI1_C_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_EVE2_0,WKUPDEP_DSI1_C_EVE2_1" bitfld.long 0x08 16. "WKUPDEP_DSI1_C_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_EVE1_0,WKUPDEP_DSI1_C_EVE1_1" newline bitfld.long 0x08 15. "WKUPDEP_DSI1_C_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_DSP2_0,WKUPDEP_DSI1_C_DSP2_1" bitfld.long 0x08 14. "WKUPDEP_DSI1_C_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_IPU1_0,WKUPDEP_DSI1_C_IPU1_1" newline bitfld.long 0x08 13. "WKUPDEP_DSI1_C_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_SDMA_0,WKUPDEP_DSI1_C_SDMA_1" bitfld.long 0x08 12. "WKUPDEP_DSI1_C_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_DSP1_0,WKUPDEP_DSI1_C_DSP1_1" newline bitfld.long 0x08 11. "WKUPDEP_DSI1_C_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_IPU2_0,WKUPDEP_DSI1_C_IPU2_1" bitfld.long 0x08 10. "WKUPDEP_DSI1_C_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_MPU_0,WKUPDEP_DSI1_C_MPU_1" newline bitfld.long 0x08 9. "WKUPDEP_HDMIIRQ_EVE4,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_EVE4_0,WKUPDEP_HDMIIRQ_EVE4_1" bitfld.long 0x08 8. "WKUPDEP_HDMIIRQ_EVE3,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_EVE3_0,WKUPDEP_HDMIIRQ_EVE3_1" newline bitfld.long 0x08 7. "WKUPDEP_HDMIIRQ_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_EVE2_0,WKUPDEP_HDMIIRQ_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_HDMIIRQ_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_EVE1_0,WKUPDEP_HDMIIRQ_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_HDMIIRQ_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_DSP2_0,WKUPDEP_HDMIIRQ_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_HDMIIRQ_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_IPU1_0,WKUPDEP_HDMIIRQ_IPU1_1" newline rbitfld.long 0x08 3. "RESERVED," "0,1" bitfld.long 0x08 2. "WKUPDEP_HDMIIRQ_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_DSP1_0,WKUPDEP_HDMIIRQ_DSP1_1" newline bitfld.long 0x08 1. "WKUPDEP_HDMIIRQ_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_IPU2_0,WKUPDEP_HDMIIRQ_IPU2_1" bitfld.long 0x08 0. "WKUPDEP_HDMIIRQ_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_MPU_0,WKUPDEP_HDMIIRQ_MPU_1" group.long 0x34++0x03 line.long 0x00 "RM_DSS_BB2D_CONTEXT,This register contains dedicated BB2B context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_DSS_MEM,Specify if memory-based context in DSS_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSS_MEM_0,LOSTMEM_DSS_MEM_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x3C++0x03 line.long 0x00 "RM_DSS_SDVENC_CONTEXT,This register contains dedicated SDVENC context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "DSS_TARG" base ad:0x44002900 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "EDMA_TC0_FW_CFG_TARG" base ad:0x4A164000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "EDMA_TPCC_FW" base ad:0x4A161000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "EDMA_TPCC_FW_CFG_TARG" base ad:0x4A162000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "EDMA_TPCC_TARG" base ad:0x44002000 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "ELM" base ad:0x48078000 rgroup.long 0x00++0x03 line.long 0x00 "ELM_REVISION,This register contains the IP revision code" group.long 0x10++0x13 line.long 0x00 "ELM_SYSCONFIG,This register allows controlling various parameters of the OCP interface" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "CLOCKACTIVITYOCP,OCP clock activity when module is in IDLE mode (during wake-up mode period)" "CLOCKACTIVITYOCP_0,CLOCKACTIVITYOCP_1" newline rbitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3.--4. "SIDLEMODE,Slave interface power management (IDLE req/ack control)" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" newline rbitfld.long 0x00 2. "RESERVED,Reserved" "0,1" bitfld.long 0x00 1. "SOFTRESET,Module software reset This bit is automatically reset by hardware (during reads it always returns 0)" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOGATING,Internal OCP clock gating strategy (no module visible effect other than saving power)" "AUTOGATING_0,AUTOGATING_1" line.long 0x04 "ELM_SYSSTATUS,Internal reset monitoring (OCP domain) Undefined since: From hardware perspective. the reset state is 0" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring (OCP domain) Undefined since: From hardware perspective the reset state is 0" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "ELM_IRQSTATUS,Interrupt status" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 8. "PAGE_VALID,Error-location status for a full page based on the mask definition Read" "No effect,Clear interrupt" newline bitfld.long 0x08 7. "LOC_VALID_7,Error-location status for syndrome polynomial 7" "No effect,Clear interrupt" bitfld.long 0x08 6. "LOC_VALID_6,Error-location status for syndrome polynomial 6" "0,1" newline bitfld.long 0x08 5. "LOC_VALID_5,Error-location status for syndrome polynomial 5" "0,1" bitfld.long 0x08 4. "LOC_VALID_4,Error-location status for syndrome polynomial 4" "0,1" newline bitfld.long 0x08 3. "LOC_VALID_3,Error-location status for syndrome polynomial 3" "0,1" bitfld.long 0x08 2. "LOC_VALID_2,Error-location status for syndrome polynomial 2" "0,1" newline bitfld.long 0x08 1. "LOC_VALID_1,Error-location status for syndrome polynomial 1" "0,1" bitfld.long 0x08 0. "LOC_VALID_0,Error-location status for syndrome polynomial 0" "0,1" line.long 0x0C "ELM_IRQENABLE,Interrupt enable" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 8. "PAGE_MASK,Page interrupt mask bit" "Disable interrupt,Enable interrupt" newline bitfld.long 0x0C 7. "LOCATION_MASK_7,Error-location interrupt mask bit for syndrome polynomial 7" "0,1" bitfld.long 0x0C 6. "LOCATION_MASK_6,Error-location interrupt mask bit for syndrome polynomial 6" "0,1" newline bitfld.long 0x0C 5. "LOCATION_MASK_5,Error-location interrupt mask bit for syndrome polynomial 5" "0,1" bitfld.long 0x0C 4. "LOCATION_MASK_4,Error-location interrupt mask bit for syndrome polynomial 4" "0,1" newline bitfld.long 0x0C 3. "LOCATION_MASK_3,Error-location interrupt mask bit for syndrome polynomial 3" "0,1" bitfld.long 0x0C 2. "LOCATION_MASK_2,Error-location interrupt mask bit for syndrome polynomial 2" "0,1" newline bitfld.long 0x0C 1. "LOCATION_MASK_1,Error-location interrupt mask bit for syndrome polynomial 1" "0,1" bitfld.long 0x0C 0. "LOCATION_MASK_0,Error-location interrupt mask bit for syndrome polynomial 0" "Disable interrupt,Enable interrupt" line.long 0x10 "ELM_LOCATION_CONFIG,ECC algorithm parameters" rbitfld.long 0x10 27.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x10 16.--26. 1. "ECC_SIZE,Maximum size of the buffers for which the error-location engine is used in number of nibbles (4-bit entities)" newline hexmask.long.word 0x10 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x10 0.--1. "ECC_BCH_LEVEL,Error correction level" "4 bits,8 bits,16 bits,Reserved" group.long 0x80++0x03 line.long 0x00 "ELM_PAGE_CTRL,Page definition" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "SECTOR_7,Set to 1 if syndrome polynomial 7 is part of the page in page mode" "0,1" newline bitfld.long 0x00 6. "SECTOR_6,Set to 1 if syndrome polynomial 6 is part of the page in page mode" "0,1" bitfld.long 0x00 5. "SECTOR_5,Set to 1 if syndrome polynomial 5 is part of the page in page mode" "0,1" newline bitfld.long 0x00 4. "SECTOR_4,Set to 1 if syndrome polynomial 4 is part of the page in page mode" "0,1" bitfld.long 0x00 3. "SECTOR_3,Set to 1 if syndrome polynomial 3 is part of the page in page mode" "0,1" newline bitfld.long 0x00 2. "SECTOR_2,Set to 1 if syndrome polynomial 2 is part of the page in page mode" "0,1" bitfld.long 0x00 1. "SECTOR_1,Set to 1 if syndrome polynomial 1 is part of the page in page mode" "0,1" newline bitfld.long 0x00 0. "SECTOR_0,Set to 1 if syndrome polynomial 0 is part of the page in page mode" "0,1" group.long 0x400++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_0,Input syndrome polynomial bits 0 to 31" group.long 0x440++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_1,Input syndrome polynomial bits 0 to 31" group.long 0x480++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_2,Input syndrome polynomial bits 0 to 31" group.long 0x4C0++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_3,Input syndrome polynomial bits 0 to 31" group.long 0x500++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_4,Input syndrome polynomial bits 0 to 31" group.long 0x540++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_5,Input syndrome polynomial bits 0 to 31" group.long 0x580++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_6,Input syndrome polynomial bits 0 to 31" group.long 0x5C0++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_7,Input syndrome polynomial bits 0 to 31" group.long 0x404++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_0,Input syndrome polynomial bits 32 to 63" group.long 0x444++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_1,Input syndrome polynomial bits 32 to 63" group.long 0x484++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_2,Input syndrome polynomial bits 32 to 63" group.long 0x4C4++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_3,Input syndrome polynomial bits 32 to 63" group.long 0x504++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_4,Input syndrome polynomial bits 32 to 63" group.long 0x544++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_5,Input syndrome polynomial bits 32 to 63" group.long 0x584++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_6,Input syndrome polynomial bits 32 to 63" group.long 0x5C4++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_7,Input syndrome polynomial bits 32 to 63" group.long 0x408++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_0,Input syndrome polynomial bits 64 to 95" group.long 0x448++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_1,Input syndrome polynomial bits 64 to 95" group.long 0x488++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_2,Input syndrome polynomial bits 64 to 95" group.long 0x4C8++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_3,Input syndrome polynomial bits 64 to 95" group.long 0x508++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_4,Input syndrome polynomial bits 64 to 95" group.long 0x548++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_5,Input syndrome polynomial bits 64 to 95" group.long 0x588++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_6,Input syndrome polynomial bits 64 to 95" group.long 0x5C8++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_7,Input syndrome polynomial bits 64 to 95" group.long 0x40C++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_0,Input syndrome polynomial bits 96 to 127" group.long 0x44C++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_1,Input syndrome polynomial bits 96 to 127" group.long 0x48C++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_2,Input syndrome polynomial bits 96 to 127" group.long 0x4CC++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_3,Input syndrome polynomial bits 96 to 127" group.long 0x50C++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_4,Input syndrome polynomial bits 96 to 127" group.long 0x54C++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_5,Input syndrome polynomial bits 96 to 127" group.long 0x58C++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_6,Input syndrome polynomial bits 96 to 127" group.long 0x5CC++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_7,Input syndrome polynomial bits 96 to 127" group.long 0x410++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_0,Input syndrome polynomial bits 128 to 159" group.long 0x450++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_1,Input syndrome polynomial bits 128 to 159" group.long 0x490++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_2,Input syndrome polynomial bits 128 to 159" group.long 0x4D0++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_3,Input syndrome polynomial bits 128 to 159" group.long 0x510++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_4,Input syndrome polynomial bits 128 to 159" group.long 0x550++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_5,Input syndrome polynomial bits 128 to 159" group.long 0x590++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_6,Input syndrome polynomial bits 128 to 159" group.long 0x5D0++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_7,Input syndrome polynomial bits 128 to 159" group.long 0x414++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_0,Input syndrome polynomial bits 160 to 191" group.long 0x454++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_1,Input syndrome polynomial bits 160 to 191" group.long 0x494++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_2,Input syndrome polynomial bits 160 to 191" group.long 0x4D4++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_3,Input syndrome polynomial bits 160 to 191" group.long 0x514++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_4,Input syndrome polynomial bits 160 to 191" group.long 0x554++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_5,Input syndrome polynomial bits 160 to 191" group.long 0x594++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_6,Input syndrome polynomial bits 160 to 191" group.long 0x5D4++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_7,Input syndrome polynomial bits 160 to 191" group.long 0x418++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_0,Input syndrome polynomial bits 192 to 207" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" newline hexmask.long.word 0x00 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" group.long 0x458++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_1,Input syndrome polynomial bits 192 to 207" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" newline hexmask.long.word 0x00 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" group.long 0x498++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_2,Input syndrome polynomial bits 192 to 207" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" newline hexmask.long.word 0x00 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" group.long 0x4D8++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_3,Input syndrome polynomial bits 192 to 207" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" newline hexmask.long.word 0x00 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" group.long 0x518++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_4,Input syndrome polynomial bits 192 to 207" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" newline hexmask.long.word 0x00 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" group.long 0x558++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_5,Input syndrome polynomial bits 192 to 207" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" newline hexmask.long.word 0x00 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" group.long 0x598++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_6,Input syndrome polynomial bits 192 to 207" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" newline hexmask.long.word 0x00 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" group.long 0x5D8++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_7,Input syndrome polynomial bits 192 to 207" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" newline hexmask.long.word 0x00 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" rgroup.long 0x800++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_0,Exit status for the syndrome polynomial processing" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x900++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_1,Exit status for the syndrome polynomial processing" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_2,Exit status for the syndrome polynomial processing" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xB00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_3,Exit status for the syndrome polynomial processing" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xC00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_4,Exit status for the syndrome polynomial processing" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xD00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_5,Exit status for the syndrome polynomial processing" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xE00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_6,Exit status for the syndrome polynomial processing" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xF00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_7,Exit status for the syndrome polynomial processing" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x880++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x980++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x884++0x03 line.long 0x00 "ELM_ERROR_LOCATION_1_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x984++0x03 line.long 0x00 "ELM_ERROR_LOCATION_1_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA84++0x03 line.long 0x00 "ELM_ERROR_LOCATION_1_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB84++0x03 line.long 0x00 "ELM_ERROR_LOCATION_1_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC84++0x03 line.long 0x00 "ELM_ERROR_LOCATION_1_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD84++0x03 line.long 0x00 "ELM_ERROR_LOCATION_1_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE84++0x03 line.long 0x00 "ELM_ERROR_LOCATION_1_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF84++0x03 line.long 0x00 "ELM_ERROR_LOCATION_1_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x888++0x03 line.long 0x00 "ELM_ERROR_LOCATION_2_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x988++0x03 line.long 0x00 "ELM_ERROR_LOCATION_2_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA88++0x03 line.long 0x00 "ELM_ERROR_LOCATION_2_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB88++0x03 line.long 0x00 "ELM_ERROR_LOCATION_2_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC88++0x03 line.long 0x00 "ELM_ERROR_LOCATION_2_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD88++0x03 line.long 0x00 "ELM_ERROR_LOCATION_2_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE88++0x03 line.long 0x00 "ELM_ERROR_LOCATION_2_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF88++0x03 line.long 0x00 "ELM_ERROR_LOCATION_2_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x88C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_3_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x98C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_3_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA8C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_3_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB8C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_3_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC8C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_3_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD8C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_3_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE8C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_3_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF8C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_3_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x890++0x03 line.long 0x00 "ELM_ERROR_LOCATION_4_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x990++0x03 line.long 0x00 "ELM_ERROR_LOCATION_4_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA90++0x03 line.long 0x00 "ELM_ERROR_LOCATION_4_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB90++0x03 line.long 0x00 "ELM_ERROR_LOCATION_4_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC90++0x03 line.long 0x00 "ELM_ERROR_LOCATION_4_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD90++0x03 line.long 0x00 "ELM_ERROR_LOCATION_4_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE90++0x03 line.long 0x00 "ELM_ERROR_LOCATION_4_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF90++0x03 line.long 0x00 "ELM_ERROR_LOCATION_4_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x894++0x03 line.long 0x00 "ELM_ERROR_LOCATION_5_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x994++0x03 line.long 0x00 "ELM_ERROR_LOCATION_5_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA94++0x03 line.long 0x00 "ELM_ERROR_LOCATION_5_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB94++0x03 line.long 0x00 "ELM_ERROR_LOCATION_5_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC94++0x03 line.long 0x00 "ELM_ERROR_LOCATION_5_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD94++0x03 line.long 0x00 "ELM_ERROR_LOCATION_5_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE94++0x03 line.long 0x00 "ELM_ERROR_LOCATION_5_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF94++0x03 line.long 0x00 "ELM_ERROR_LOCATION_5_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x898++0x03 line.long 0x00 "ELM_ERROR_LOCATION_6_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x998++0x03 line.long 0x00 "ELM_ERROR_LOCATION_6_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA98++0x03 line.long 0x00 "ELM_ERROR_LOCATION_6_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB98++0x03 line.long 0x00 "ELM_ERROR_LOCATION_6_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC98++0x03 line.long 0x00 "ELM_ERROR_LOCATION_6_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD98++0x03 line.long 0x00 "ELM_ERROR_LOCATION_6_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE98++0x03 line.long 0x00 "ELM_ERROR_LOCATION_6_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF98++0x03 line.long 0x00 "ELM_ERROR_LOCATION_6_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x89C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_7_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x99C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_7_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA9C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_7_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB9C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_7_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC9C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_7_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD9C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_7_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE9C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_7_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF9C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_7_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8A0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_8_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9A0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_8_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xAA0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_8_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBA0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_8_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCA0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_8_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDA0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_8_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEA0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_8_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFA0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_8_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8A4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_9_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9A4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_9_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xAA4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_9_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBA4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_9_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCA4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_9_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDA4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_9_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEA4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_9_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFA4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_9_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8A8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_10_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9A8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_10_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xAA8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_10_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBA8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_10_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCA8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_10_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDA8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_10_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEA8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_10_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFA8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_10_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8AC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_11_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9AC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_11_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xAAC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_11_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBAC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_11_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCAC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_11_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDAC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_11_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEAC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_11_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFAC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_11_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8B0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_12_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9B0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_12_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xAB0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_12_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBB0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_12_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCB0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_12_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDB0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_12_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEB0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_12_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFB0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_12_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8B4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_13_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9B4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_13_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xAB4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_13_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBB4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_13_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCB4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_13_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDB4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_13_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEB4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_13_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFB4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_13_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8B8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_14_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9B8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_14_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xAB8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_14_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBB8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_14_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCB8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_14_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDB8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_14_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEB8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_14_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFB8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_14_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8BC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_15_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9BC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_15_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xABC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_15_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBBC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_15_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCBC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_15_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDBC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_15_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEBC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_15_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFBC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_15_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" width 0x0B tree.end tree "ELM_TARG" base ad:0x48079000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "EMIF" base ad:0x4C000000 rgroup.long 0x00++0x43 line.long 0x00 "EMIF_REVISION,Revision number register" line.long 0x04 "EMIF_STATUS,SDRAM Status Register (STATUS)" bitfld.long 0x04 31. "BE,Big endian mode select for 8 and 16-bit devices set to 1 for big endian or 0 for little endian operation" "0,1" newline bitfld.long 0x04 30. "DUAL_CLK_MODE,Dual Clock mode" "0,1" newline bitfld.long 0x04 29. "FAST_INIT,Fast Init" "0,1" newline hexmask.long.tbyte 0x04 7.--28. 1. "RESERVED,Reserved" newline bitfld.long 0x04 6. "RDLVLGATETO,Read DQS Gate Training Timeout" "0,1" newline bitfld.long 0x04 5. "RDLVLTO,Read Data Eye Training Timeout" "0,1" newline bitfld.long 0x04 4. "WRLVLTO,Write Leveling Timeout" "0,1" newline bitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "PHY_DLL_READY,DDR PHY Ready" "0,1" newline bitfld.long 0x04 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x08 "EMIF_SDRAM_CONFIG,SDRAM Config Register" bitfld.long 0x08 29.--31. "SDRAM_TYPE,SDRAM Type selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 27.--28. "IBANK_POS,Internal bank position" "0,1,2,3" newline bitfld.long 0x08 24.--26. "DDR_TERM,DDR3 termination resistor value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 23. "DDR2_DDQS,Differential DQS enable" "0,1" newline bitfld.long 0x08 21.--22. "DYN_ODT,DDR3 Dynamic ODT.Not supported" "0,1,2,3" newline bitfld.long 0x08 20. "DDR_DISABLE_DLL,Disable DLL select" "0,1" newline bitfld.long 0x08 18.--19. "SDRAM_DRIVE,SDRAM drive strength" "0,1,2,3" newline bitfld.long 0x08 16.--17. "CWL,DDR3 CAS Write latency" "0,1,2,3" newline bitfld.long 0x08 14.--15. "NARROW_MODE,SDRAM data bus width" "0,1,2,3" newline bitfld.long 0x08 10.--13. "CL,CAS Latency (referred to as read latency (RL) in some SDRAM specs)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 7.--9. "ROWSIZE,Row Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 4.--6. "IBANK,Internal Bank setup" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 0.--2. "PAGESIZE,Page Size" "0,1,2,3,4,5,6,7" line.long 0x0C "EMIF_SDRAM_CONFIG_2,SDRAM Config Register 2 CAUTION: This register is loaded with values by control module at device reset" rbitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 27. "EBANK_POS,External bank position" "0,1" newline hexmask.long 0x0C 0.--26. 1. "RESERVED," line.long 0x10 "EMIF_SDRAM_REFRESH_CONTROL,SDRAM Refresh Control Register" bitfld.long 0x10 31. "INITREF_DIS,Initialization and Refresh disable" "0,1" newline rbitfld.long 0x10 30. "RESERVED," "0,1" newline bitfld.long 0x10 29. "SRT,DDR3 Self Refresh temperature range" "0,1" newline bitfld.long 0x10 28. "ASR,DDR3 Auto Self Refresh enable" "0,1" newline rbitfld.long 0x10 27. "RESERVED," "0,1" newline bitfld.long 0x10 24.--26. "PASR,Partial Array Self Refresh" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 16.--23. 1. "RESERVED," newline hexmask.long.word 0x10 0.--15. 1. "REFRESH_RATE,Refresh Rate" line.long 0x14 "EMIF_SDRAM_REFRESH_CONTROL_SHADOW,SDRAM Refresh Control Shadow Register" hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x14 0.--15. 1. "REFRESH_RATE_SHDW,Shadow field for REFRESH_RATE" line.long 0x18 "EMIF_SDRAM_TIMING_1,SDRAM Timing 1 Register" bitfld.long 0x18 29.--31. "T_RTW,Minimum number of DDR clock cycles between Read to Write data phases minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 25.--28. "T_RP,Minimum number of DDR clock cycles from Precharge to Activate or Refresh minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 21.--24. "T_RCD,Minimum number of DDR clock cycles from Activate to Read or Write minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 17.--20. "T_WR,Minimum number of DDR clock cycles from last Write transfer to Precharge minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 12.--16. "T_RAS,Minimum number of DDR clock cycles from Activate to Precharge minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 6.--11. "T_RC,Minimum number of DDR clock cycles from Activate to Activate minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x18 3.--5. "T_RRD,Minimum number of DDR clock cycles from Activate to Activate for a different bank minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "T_WTR,Minimum number of DDR clock cycles from last Write to Read minus one" "0,1,2,3,4,5,6,7" line.long 0x1C "EMIF_SDRAM_TIMING_1_SHADOW,SDRAM Timing 1 Shadow Register" bitfld.long 0x1C 29.--31. "T_RTW_SHDW,Shadow field for T_RTW" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 25.--28. "T_RP_SHDW,Shadow field for T_RP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 21.--24. "T_RCD_SHDW,Shadow field for T_RCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 17.--20. "T_WR_SHDW,Shadow field for T_WR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 12.--16. "T_RAS_SHDW,Shadow field for T_RAS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 6.--11. "T_RC_SHDW,Shadow field for T_RC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x1C 3.--5. "T_RRD_SHDW,Shadow field for T_RRD" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0.--2. "T_WTR_SHDW,Shadow field for T_WTR" "0,1,2,3,4,5,6,7" line.long 0x20 "EMIF_SDRAM_TIMING_2,SDRAM Timing 2 Register" rbitfld.long 0x20 31. "RESERVED,Reserved" "0,1" newline bitfld.long 0x20 28.--30. "T_XP,Minimum number of DDR clock cycles from power-down exit to any command other than a read command minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 25.--27. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 16.--24. 1. "T_XSNR,Minimum number of DDR clock cycles from Self-Refresh exit to any command other than a Read command minus one" newline hexmask.long.word 0x20 6.--15. 1. "T_XSRD,Minimum number of DDR clock cycles from Self-Refresh exit to a Read command minus one" newline bitfld.long 0x20 3.--5. "T_RTP,Minimum number of DDR clock cycles for the last read command to a Precharge command minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "T_CKE,Minimum number of DDR clock cycles between CKE pin changes minus one" "0,1,2,3,4,5,6,7" line.long 0x24 "EMIF_SDRAM_TIMING_2_SHADOW,SDRAM Timing 2 Shadow Register" rbitfld.long 0x24 31. "RESERVED,Reserved" "0,1" newline bitfld.long 0x24 28.--30. "T_XP_SHDW,Shadow field for T_XP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 25.--27. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x24 16.--24. 1. "T_XSNR_SHDW,Shadow field for T_XSNR" newline hexmask.long.word 0x24 6.--15. 1. "T_XSRD_SHDW,Shadow field for T_XSRD" newline bitfld.long 0x24 3.--5. "T_RTP_SHDW,Shadow field for T_RTP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0.--2. "T_CKE_SHDW,Shadow field for T_CKE" "0,1,2,3,4,5,6,7" line.long 0x28 "EMIF_SDRAM_TIMING_3,SDRAM Timing 3 Register" bitfld.long 0x28 28.--31. "T_PDLL_UL,Minimum number of DDR clock cycles for PHY DLL to unlock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x28 24.--27. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 21.--23. "T_CKESR,Minimum number of DDR clock cycles for which SDRAM must remain in Self Refresh minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 15.--20. "ZQ_ZQCS,Number of DDR clock cycles for a ZQCS command minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x28 13.--14. "T_TDQSCKMAX,Number of DDR clock that satisfies tDQSCKmax for LPDDR2 minus one" "0,1,2,3" newline hexmask.long.word 0x28 4.--12. 1. "T_RFC,Minimum number of DDR clock cycles from Refresh or Load Mode to Refresh or Activate minus one" newline bitfld.long 0x28 0.--3. "T_RAS_MAX,Maximum number of REFRESH_RATE intervals from Activate to Precharge command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "EMIF_SDRAM_TIMING_3_SHADOW,SDRAM Timing 3 Shadow Register" bitfld.long 0x2C 28.--31. "T_PDLL_UL_SHDW,Shadow field for T_PDLL_UL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C 24.--27. "T_CSTA_SHDW,Shadow field for T_CSTA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C 21.--23. "T_CKESR_SHDW,Shadow field for T_CKESR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 15.--20. "ZQ_ZQCS_SHDW,Shadow field for ZQ_ZQCS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x2C 13.--14. "T_TDQSCKMAX_SHDW,Shadow field for T_TDQSCKMAX" "0,1,2,3" newline hexmask.long.word 0x2C 4.--12. 1. "T_RFC_SHDW,Shadow field for T_RFC" newline bitfld.long 0x2C 0.--3. "T_RAS_MAX_SHDW,Shadow field for T_RAS_MAX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x30 "EMIF_LPDDR2_NVM_TIMING,NOTE: This register is not supported" line.long 0x34 "EMIF_LPDDR2_NVM_TIMING_SHADOW,NOTE: This register is not supported" line.long 0x38 "EMIF_POWER_MANAGEMENT_CONTROL,Power Management Control Register" hexmask.long.word 0x38 16.--31. 1. "RESERVED," newline bitfld.long 0x38 12.--15. "PD_TIM,Power Management timer for Power-Down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x38 11. "DPD_EN,Deep Power Down enable" "0,1" newline bitfld.long 0x38 8.--10. "LP_MODE,Automatic Power Management enable" "Disable automatic power management,Reserved,Self Refresh mode,Disable automatic power management,Power-Down mode All other values disable..,?..." newline bitfld.long 0x38 4.--7. "SR_TIM,Power Management timer for Self Refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x38 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x3C "EMIF_POWER_MANAGEMENT_CONTROL_SHADOW,Power Management Control Shadow Register" hexmask.long.word 0x3C 16.--31. 1. "RESERVED," newline bitfld.long 0x3C 12.--15. "PD_TIM_SHDW,Shadow field for PD_TIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x3C 8.--11. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3C 4.--7. "SR_TIM_SHDW,Shadow field for SR_TIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3C 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x40 "EMIF_LPDDR2_MODE_REG_DATA,LPDDR2 Mode Reg Data Register A write to this register will cause a Mode Register write command to be sent to the LPDDR2 device with write data as specified in the VALUE_0 field" hexmask.long 0x40 7.--31. 1. "RESERVED," newline hexmask.long.byte 0x40 0.--6. 1. "VALUE_0,Mode register value" group.long 0x50++0x13 line.long 0x00 "EMIF_LPDDR2_MODE_REG_CONFIG,LPDDR2 Mode Reg Config Register" bitfld.long 0x00 31. "CS,Chip select to issue mode register command" "0,1" newline bitfld.long 0x00 30. "REFRESH_EN,Refresh Enable after MRW" "0,1" newline hexmask.long.tbyte 0x00 8.--29. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "ADDRESS,Mode register address" line.long 0x04 "EMIF_OCP_CONFIG,OCP Config Register" rbitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 24.--27. "SYS_THRESH_MAX,System OCP Threshold Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.tbyte 0x04 0.--23. 1. "RESERVED," line.long 0x08 "EMIF_OCP_CONFIG_VALUE_1,OCP Config Value 1 Register" bitfld.long 0x08 30.--31. "SYS_BUS_WIDTH,System OCP data bus width" "32-bit wide,64-bit wide,128-bit wide,Reserved" newline hexmask.long.word 0x08 16.--29. 1. "RESERVED," newline hexmask.long.byte 0x08 8.--15. 1. "WR_FIFO_DEPTH,Write Data FIFO depth" newline hexmask.long.byte 0x08 0.--7. 1. "CMD_FIFO_DEPTH,Command FIFO depth" line.long 0x0C "EMIF_OCP_CONFIG_VALUE_2,OCP Config Value 2 Register" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0C 16.--23. 1. "RREG_FIFO_DEPTH,Register Read Data FIFO depth" newline hexmask.long.byte 0x0C 8.--15. 1. "RSD_FIFO_DEPTH,SDRAM Read Data FIFO depth" newline hexmask.long.byte 0x0C 0.--7. 1. "RCMD_FIFO_DEPTH,Read Command FIFO depth" line.long 0x10 "EMIF_IODFT_TLGC," hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x10 15. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 14. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 13. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 12. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x10 11. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 10. "RESET_PHY,Reset the DDR PHY" "0,1" newline rbitfld.long 0x10 9. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 8. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x10 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x10 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x10 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0. "RESERVED,Reserved" "0,1" rgroup.long 0x80++0x27 line.long 0x00 "EMIF_PERFORMANCE_COUNTER_1,Performance Counter 1 Register" line.long 0x04 "EMIF_PERFORMANCE_COUNTER_2,Performance Counter 2 Register" line.long 0x08 "EMIF_PERFORMANCE_COUNTER_CONFIG,Performance Counter Config Register" bitfld.long 0x08 31. "CNTR2_MCONNID_EN,MConnID filter enable forEMIF_PERFORMANCE_COUNTER_2 register" "0,1" newline bitfld.long 0x08 30. "CNTR2_REGION_EN,Chip Select filter enable forEMIF_PERFORMANCE_COUNTER_2 register" "0,1" newline hexmask.long.word 0x08 20.--29. 1. "RESERVED,Reserved for future use" newline bitfld.long 0x08 16.--19. "CNTR2_CFG,Filter configuration forEMIF_PERFORMANCE_COUNTER_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 15. "CNTR1_MCONNID_EN,MConnID filter enable forEMIF_PERFORMANCE_COUNTER_1 register" "0,1" newline bitfld.long 0x08 14. "CNTR1_REGION_EN,Chip Select filter enable forEMIF_PERFORMANCE_COUNTER_1 register" "0,1" newline hexmask.long.word 0x08 4.--13. 1. "RESERVED,Reserved for future use" newline bitfld.long 0x08 0.--3. "CNTR1_CFG,Filter configuration forEMIF_PERFORMANCE_COUNTER_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT,Performance Counter Master Region Select Register The values programmed into the MCONNIDx fields are those in the ConnID Valuestable in . Interconnect" hexmask.long.byte 0x0C 24.--31. 1. "MCONNID2,MConnID forEMIF_PERFORMANCE_COUNTER_2 register" newline hexmask.long.byte 0x0C 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0C 8.--15. 1. "MCONNID1,MConnID forEMIF_PERFORMANCE_COUNTER_1 register" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Reserved" line.long 0x10 "EMIF_PERFORMANCE_COUNTER_TIME,Performance Counter Time Register" line.long 0x14 "EMIF_MISC_REG," hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "DLL_CALIB_OS,Phy_dll_calib one shot : Setting bit to 1 generates a phy_pll_calib pulse" "0,1" line.long 0x18 "EMIF_DLL_CALIB_CTRL,Control register to force idle window time to generate a phy_dll_calib that can be used for updating PHY DLLs during voltage ramps" hexmask.long.word 0x18 20.--31. 1. "RESERVED," newline bitfld.long 0x18 16.--19. "ACK_WAIT,The ack_wait determines the required wait time after a phy_dll_calib is generated before another command can be sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x18 9.--15. 1. "RESERVED," newline hexmask.long.word 0x18 0.--8. 1. "DLL_CALIB_INTERVAL,This field determines the interval between phy_dll_calib generation" line.long 0x1C "EMIF_DLL_CALIB_CTRL_SHADOW,Read Idle Control Shadow Register" hexmask.long.word 0x1C 20.--31. 1. "RESERVED," newline bitfld.long 0x1C 16.--19. "ACK_WAIT_SHDW,Shadow field for ACK_WAIT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x1C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x1C 0.--8. 1. "DLL_CALIB_INTERVAL_SHDW,Shadow field for DLL_CALIB_INTERVAL" line.long 0x20 "EMIF_END_OF_INTERRUPT," hexmask.long 0x20 1.--31. 1. "RESERVED," newline bitfld.long 0x20 0. "EOI,Software End Of Interrupt (EOI) control" "0,1" line.long 0x24 "EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS,System OCP Interrupt Raw Status Register" hexmask.long 0x24 6.--31. 1. "RESERVED," newline bitfld.long 0x24 5. "ONEBIT_ECC_ERR_SYS,Raw status of system ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x24 4. "TWOBIT_ECC_ERR_SYS,Raw status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x24 3. "WR_ECC_ERR_SYS,Raw status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location" "0,1" newline rbitfld.long 0x24 2. "RESERVED," "0,1" newline bitfld.long 0x24 1. "TA_SYS,Raw status of system OCP interrupt for SDRAM temperature alert" "0,1" newline bitfld.long 0x24 0. "ERR_SYS,Raw status of system OCP interrupt for command or address error" "0,1" group.long 0xAC++0x03 line.long 0x00 "EMIF_SYSTEM_OCP_INTERRUPT_STATUS,System OCP Interrupt Status Register" hexmask.long 0x00 6.--31. 1. "RESERVED," newline bitfld.long 0x00 5. "ONEBIT_ECC_ERR_SYS,Enabled status of system ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x00 4. "TWOBIT_ECC_ERR_SYS,Enabled status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location" "0,1" newline rbitfld.long 0x00 2. "RESERVED," "0,1" newline bitfld.long 0x00 1. "TA_SYS,Enabled status of system OCP interrupt for SDRAM temperature alert" "0,1" newline bitfld.long 0x00 0. "ERR_SYS,Enabled status of system OCP interrupt interrupt for command or address error" "0,1" group.long 0xB4++0x03 line.long 0x00 "EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET,System OCP Interrupt Enable Set Register" hexmask.long 0x00 6.--31. 1. "RESERVED," newline bitfld.long 0x00 5. "ONEBIT_ECC_ERR_SYS,Enabled status of sysem ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x00 4. "TWOBIT_ECC_ERR_SYS,Enabled status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location" "0,1" newline rbitfld.long 0x00 2. "RESERVED," "0,1" newline bitfld.long 0x00 1. "EN_TA_SYS,Enable set for system OCP interrupt for SDRAM temperature alert" "0,1" newline bitfld.long 0x00 0. "EN_ERR_SYS,Enable set for system OCP interrupt for command or address error" "0,1" group.long 0xBC++0x03 line.long 0x00 "EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR,System OCP Interrupt Enable Clear Register" hexmask.long 0x00 6.--31. 1. "RESERVED," newline bitfld.long 0x00 5. "ONEBIT_ECC_ERR_SYS,Enabled status of system ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x00 4. "TWOBIT_ECC_ERR_SYS,Enabled status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location" "0,1" newline rbitfld.long 0x00 2. "RESERVED," "0,1" newline bitfld.long 0x00 1. "EN_TA_SYS,Enable clear for system OCP interrupt for SDRAM temperature alert" "0,1" newline bitfld.long 0x00 0. "EN_ERR_SYS,Enable clear for system OCP interrupt for command or address error" "0,1" group.long 0xC8++0x17 line.long 0x00 "EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG,SDRAM Output Impedance Calibration Config Register" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 30. "ZQ_CS0EN,Writing a 1 enables ZQ calibration for CSN0" "0,1" newline rbitfld.long 0x00 29. "RESERVED," "0,1" newline bitfld.long 0x00 28. "ZQ_SFEXITEN,Writing a 1 enables the issuing of ZQCL on Self-Refresh Active Power-Down and Precharge Power-Down exit" "0,1" newline hexmask.long.byte 0x00 20.--27. 1. "RESERVED," newline bitfld.long 0x00 18.--19. "ZQ_ZQINIT_MULT,Indicates the number of ZQCL durations that make up a ZQINIT duration minus one" "0,1,2,3" newline bitfld.long 0x00 16.--17. "ZQ_ZQCL_MULT,Indicates the number of ZQCS intervals that make up a ZQCL duration minus one" "0,1,2,3" newline hexmask.long.word 0x00 0.--15. 1. "ZQ_REFINTERVAL,Number of refresh periods between ZQCS commands" line.long 0x04 "EMIF_TEMPERATURE_ALERT_CONFIG,Temperature Alert Config Register" rbitfld.long 0x04 31. "RESERVED," "0,1" newline bitfld.long 0x04 30. "TA_CS0EN,Writing a 1 enables temperature alert polling for CSN0" "0,1" newline rbitfld.long 0x04 29. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 28. "TA_SFEXITEN,Temperature Alert Poll on Self-Refresh Active Power-Down and Precharge Power-Down exit enable" "0,1" newline bitfld.long 0x04 26.--27. "TA_DEVWDT,This field indicates how wide a physical device is" "8-bit wide,16- bit wide,32-bit wide,?..." newline bitfld.long 0x04 24.--25. "TA_DEVCNT,This field indicates which external byte lanes contain a device for temperature monitoring" "one device,two devices,four devices,?..." newline rbitfld.long 0x04 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.tbyte 0x04 0.--21. 1. "TA_REFINTERVAL,Number of refresh periods between temperature alert polls" line.long 0x08 "EMIF_OCP_ERROR_LOG,OCP Error Log Register" hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED,Reserved for future use" newline bitfld.long 0x08 11.--13. "MBURSTSEQ,Addressing mode of the first errored transaction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 8.--10. "MCMD,Command type of the first errored transaction" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 0.--7. 1. "MCONNID,Connection ID of the first errored transaction" line.long 0x0C "EMIF_READ_WRITE_LEVELING_RAMP_WINDOW,Read/write leveling ramp window register" hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--12. 1. "RDWRLVLINC_RMP_WIN,Incremental leveling ramp window in number of refresh periods" line.long 0x10 "EMIF_READ_WRITE_LEVELING_RAMP_CONTROL,Read/write leveling ramp control register" bitfld.long 0x10 31. "RDWRLVL_EN,Read-Write Leveling enable" "0,1" newline hexmask.long.byte 0x10 24.--30. 1. "RDWRLVLINC_RMP_PRE,Incremental leveling pre-scalar in number of refresh periods during ramp window" newline hexmask.long.byte 0x10 16.--23. 1. "RDLVLINC_RMP_INT,Incremental read data eye training interval during ramp window" newline hexmask.long.byte 0x10 8.--15. 1. "RDLVLGATEINC_RMP_INT,Incremental read DQS gate training interval during ramp window" newline hexmask.long.byte 0x10 0.--7. 1. "WRLVLINC_RMP_INT,Incremental write leveling interval during ramp window" line.long 0x14 "EMIF_READ_WRITE_LEVELING_CONTROL,Read/write leveling control register" bitfld.long 0x14 31. "RDWRLVLFULL_START,Full leveling trigger" "0,1" newline hexmask.long.byte 0x14 24.--30. 1. "RDWRLVLINC_PRE,Incremental leveling pre-scalar in number of refresh periods" newline hexmask.long.byte 0x14 16.--23. 1. "RDLVLINC_INT,Incremental read data eye training interval" newline hexmask.long.byte 0x14 8.--15. 1. "RDLVLGATEINC_INT,Incremental read DQS gate training interval" newline hexmask.long.byte 0x14 0.--7. 1. "WRLVLINC_INT,Incremental write leveling interval" group.long 0xE4++0x0B line.long 0x00 "EMIF_DDR_PHY_CONTROL_1,PHY control register 1" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RDLVL_MASK,Writing a 1 to this field will mask read data eye training during full leveling command plus drives reg_phy_use_rd_data_eye_level control low to allow user to use programmed ratio values" "0,1" newline bitfld.long 0x00 26. "RDLVLGATE_MASK,Writing a 1 to this field will mask dqs gate training during full leveling command plus drives reg_phy_use_rd_dqs_level control low to allow user to use programmed ratio values" "0,1" newline bitfld.long 0x00 25. "WRLVL_MASK,Writing a 1 to this field will mask write leveling training during full leveling command plus drives reg_phy_use_wr_level control low to allow user to use programmed ratio values" "0,1" newline bitfld.long 0x00 22.--24. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 21. "PHY_HALF_DELAYS,Adjust slave delay line delays to support 2x mode" "1x mode ( MDLL clock rate is same as PHY),2x mode (MDLL clock is half the rate of PHY)" newline bitfld.long 0x00 20. "PHY_CLK_STALL_LEVEL,Enable variable idle value for delay lines" "0,1" newline bitfld.long 0x00 19. "PHY_DIS_CALIB_RST,Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of data PHYs" "0,1" newline bitfld.long 0x00 18. "PHY_INVERT_CLKOUT,Inverts the polarity of DRAM clock" "core clock is passed on to DRAM,inverted core clock is passed on to DRAM" newline hexmask.long.byte 0x00 10.--17. 1. "PHY_DLL_LOCK_DIFF,The maximum number of delay line taps variation while maintaining the master DLL lock" newline bitfld.long 0x00 9. "PHY_FAST_DLL_LOCK,Controls master DLL to lock fast or average logic must be part of locking process" "MDLL lock is asserted based on average of 16..,MDLL lock is asserted based on single sample" newline bitfld.long 0x00 5.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--4. "READ_LATENCY,This field defines the read latency for the read data from SDRAM in number of DDR clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EMIF_DDR_PHY_CONTROL_1_SHADOW," bitfld.long 0x04 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 27. "RDLVL_MASK_SHDW,Shadow field for RDLVL_MASK" "0,1" newline bitfld.long 0x04 26. "RDLVLGATE_MASK_SHDW,Shadow field for RDLVLGATE_MASK" "0,1" newline bitfld.long 0x04 25. "WRLVL_MASK_SHDW,Shadow field for WRLVL_MASK" "0,1" newline bitfld.long 0x04 22.--24. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 21. "PHY_HALF_DELAYS_SHDW,Shadow field for PHY_HALF_DELAYS" "0,1" newline bitfld.long 0x04 20. "PHY_CLK_STALL_LEVEL_SHDW,Shadow field for PHY_CLK_STALL_LEVEL" "0,1" newline bitfld.long 0x04 19. "PHY_DIS_CALIB_RST_SHDW,Shadow field for PHY_DIS_CALIB_RST" "0,1" newline bitfld.long 0x04 18. "PHY_INVERT_CLKOUT_SHDW,Shadow field for PHY_INVERT_CLKOUT" "0,1" newline hexmask.long.byte 0x04 10.--17. 1. "PHY_DLL_LOCK_DIFF_SHDW,Shadow field for PHY_DLL_LOCK_DIFF" newline bitfld.long 0x04 9. "PHY_FAST_DLL_SHDW,Shadow field for PHY_FAST_DLL" "0,1" newline bitfld.long 0x04 5.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--4. "READ_LATENCY_SHDW,Shadow field for READ_LATENCY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "EMIF_DDR_PHY_CONTROL_2," group.long 0x100++0x0B line.long 0x00 "EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING," bitfld.long 0x00 31. "PRI_COS_MAP_EN,Set 1 to enable priority to class of service mapping" "0,1" newline hexmask.long.word 0x00 16.--30. 1. "RESERVED," newline bitfld.long 0x00 14.--15. "PRI_7_COS,Class of service for commands with priority of 7" "0,1,2,3" newline bitfld.long 0x00 12.--13. "PRI_6_COS,Class of service for commands with priority of 6" "0,1,2,3" newline bitfld.long 0x00 10.--11. "PRI_5_COS,Class of service for commands with priority of 5" "0,1,2,3" newline bitfld.long 0x00 8.--9. "PRI_4_COS,Class of service for commands with priority of 4" "0,1,2,3" newline bitfld.long 0x00 6.--7. "PRI_3_COS,Class of service for commands with priority of 3" "0,1,2,3" newline bitfld.long 0x00 4.--5. "PRI_2_COS,Class of service for commands with priority of 2" "0,1,2,3" newline bitfld.long 0x00 2.--3. "PRI_1_COS,Class of service for commands with priority of 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. "PRI_0_COS,Class of service for commands with priority of 0" "0,1,2,3" line.long 0x04 "EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING," bitfld.long 0x04 31. "CONNID_COS_1_MAP_EN,Set 1 to enable Connection ID to class of service 1 mapping" "0,1" newline hexmask.long.byte 0x04 23.--30. 1. "CONNID_1_COS_1,Connection ID value 1 for class of service 1" newline bitfld.long 0x04 20.--22. "MSK_1_COS_1,Mask for Connection ID value 1 for class of service 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x04 12.--19. 1. "CONNID_2_COS_1,Connection ID value 2 for class of service 1" newline bitfld.long 0x04 10.--11. "MSK_2_COS_1,Mask for Connection ID value 2 for class of service 1" "0,1,2,3" newline hexmask.long.byte 0x04 2.--9. 1. "CONNID_3_COS_1,Connection ID value 3 for class of service 1" newline bitfld.long 0x04 0.--1. "MSK_3_COS_1,Mask for Connection ID value 3 for class of service 1" "0,1,2,3" line.long 0x08 "EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING," bitfld.long 0x08 31. "CONNID_COS_2_MAP_EN,Set 1 to enable Connection ID to class of service 2 mapping" "0,1" newline hexmask.long.byte 0x08 23.--30. 1. "CONNID_1_COS_2,Connection ID value 1 for class of service 2" newline bitfld.long 0x08 20.--22. "MSK_1_COS_2,Mask for Connection ID value 1 for class of service 2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 12.--19. 1. "CONNID_2_COS_2,Connection ID value 2 for class of service 2" newline bitfld.long 0x08 10.--11. "MSK_2_COS_2,Mask for Connection ID value 2 for class of service 2" "0,1,2,3" newline hexmask.long.byte 0x08 2.--9. 1. "CONNID_3_COS_2,Connection ID value 3 for class of service 2" newline bitfld.long 0x08 0.--1. "MSK_3_COS_2,Mask for Connection ID value 3 for class of service 2" "0,1,2,3" group.long 0x110++0x0B line.long 0x00 "EMIF_ECC_CTRL_REG," bitfld.long 0x00 31. "REG_ECC_EN,Set 1 to enable ECC" "0,1" newline bitfld.long 0x00 30. "REG_ECC_ADDR_RGN_PROT,Setting this field to 1 and reg_ecc_en to a 1 will enable ECC calculation for accesses within the address ranges and disable ECC calculation for accesses outside the address ranges" "0,1" newline hexmask.long 0x00 2.--29. 1. "RESERVED," newline bitfld.long 0x00 1. "REG_ECC_ADDR_RGN_2_EN,Set 1 to enable ECC address range 2" "0,1" newline bitfld.long 0x00 0. "REG_ECC_ADDR_RGN_1_EN,Set 1 to enable ECC address range 1" "0,1" line.long 0x04 "EMIF_ECC_ADDRESS_RANGE_1," hexmask.long.word 0x04 16.--31. 1. "REG_ECC_END_ADDR_1,End address[32:17] for ECC address range 1" newline hexmask.long.word 0x04 0.--15. 1. "REG_ECC_STRT_ADDR_1,Start address[32:17] for ECC address range 1" line.long 0x08 "EMIF_ECC_ADDRESS_RANGE_2," hexmask.long.word 0x08 16.--31. 1. "REG_ECC_END_ADDR_2,End address[32:17] for ECC address range 2" newline hexmask.long.word 0x08 0.--15. 1. "REG_ECC_STRT_ADDR_2,Start address[32:17] for ECC address range 2" group.long 0x120++0x07 line.long 0x00 "EMIF_READ_WRITE_EXECUTION_THRESHOLD," bitfld.long 0x00 31. "MFLAG_OVERRIDE,Mflag override" "MFLAG_OVERRIDE_0,MFLAG_OVERRIDE_1" newline hexmask.long.tbyte 0x00 13.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 8.--12. "WR_THRSH,Write Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 0.--4. "RD_THRSH,Read threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EMIF_COS_CONFIG,Priority Raise Counter Register" hexmask.long.byte 0x04 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x04 16.--23. 1. "COS_COUNT_1,Priority Raise Counter for class of service 1" newline hexmask.long.byte 0x04 8.--15. 1. "COS_COUNT_2,Priority Raise Counter for class of service 2" newline hexmask.long.byte 0x04 0.--7. 1. "PR_OLD_COUNT,Priority Raise Old Counter" group.long 0x130++0x83 line.long 0x00 "EMIF_1B_ECC_ERR_CNT," line.long 0x04 "EMIF_1B_ECC_ERR_THRSH," hexmask.long.byte 0x04 24.--31. 1. "REG_1B_ECC_ERR_THRSH,1-bit ECC error threshold" newline hexmask.long.byte 0x04 16.--23. 1. "RESERVED," newline hexmask.long.word 0x04 0.--15. 1. "REG_1B_ECC_ERR_WIN,1-bit ECC error window in number of refresh periods" line.long 0x08 "EMIF_1B_ECC_ERR_DIST_1," line.long 0x0C "EMIF_1B_ECC_ERR_ADDR_LOG," line.long 0x10 "EMIF_2B_ECC_ERR_ADDR_LOG," line.long 0x14 "EMIF_PHY_STATUS_1," bitfld.long 0x14 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.tbyte 0x14 12.--29. 1. "PHY_REG_PHY_CTRL_DLL_SLAVE_VALUE,DLL Slave Value" newline bitfld.long 0x14 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 4.--8. "PHY_REG_STATUS_DLL_LOCK,Lock Status for Data DLLs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 0.--1. "PHY_REG_PHY_CTRL_DLL_LOCK,Lock Status for Command DLLs" "0,1,2,3" line.long 0x18 "EMIF_PHY_STATUS_2," line.long 0x1C "EMIF_PHY_STATUS_3," bitfld.long 0x1C 31. "RESERVED," "0,1" newline hexmask.long.word 0x1C 16.--30. 1. "PHY_REG_RDFIFO_RDPTR,Read FIFO Read Pointer" newline bitfld.long 0x1C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1C 0.--12. 1. "PHY_REG_STATUS_DLL_SLAVE_VALUE_HI,Bits 44:32 of Phy_reg_status_dll_slave_value" line.long 0x20 "EMIF_PHY_STATUS_4," bitfld.long 0x20 31. "RESERVED," "0,1" newline hexmask.long.word 0x20 16.--30. 1. "PHY_REG_GATELVL_FSM,Gate Levelling FSM" newline bitfld.long 0x20 15. "RESERVED," "0,1" newline hexmask.long.word 0x20 0.--14. 1. "PHY_REG_RDFIFO_WRPTR,Read FIFO Write Pointer" line.long 0x24 "EMIF_PHY_STATUS_5," hexmask.long.word 0x24 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x24 0.--19. 1. "PHY_REG_RD_LEVEL_FSM,Read Levelling FSM" line.long 0x28 "EMIF_PHY_STATUS_6," hexmask.long.tbyte 0x28 15.--31. 1. "RESERVED," newline hexmask.long.word 0x28 0.--14. 1. "PHY_REG_WR_LEVEL_FSM,Writel Levelling FSM" line.long 0x2C "EMIF_PHY_STATUS_7," bitfld.long 0x2C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x2C 16.--25. 1. "PHY_REG_RDLVL_DQS_RATIO1,Read levelling DQS ratio1" newline bitfld.long 0x2C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x2C 0.--9. 1. "PHY_REG_RDLVL_DQS_RATIO0,Read levelling DQS ratio0" line.long 0x30 "EMIF_PHY_STATUS_8," bitfld.long 0x30 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x30 16.--25. 1. "PHY_REG_RDLVL_DQS_RATIO3,Read levelling DQS ratio3" newline bitfld.long 0x30 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x30 0.--9. 1. "PHY_REG_RDLVL_DQS_RATIO2,Read levelling DQS ratio2" line.long 0x34 "EMIF_PHY_STATUS_9," bitfld.long 0x34 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x34 16.--25. 1. "PHY_REG_RDLVL_DQS_RATIO5,Read Levelling DQS ratio5" newline bitfld.long 0x34 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x34 0.--9. 1. "PHY_REG_RDLVL_DQS_RATIO4,Read Levelling DQS ratio4" line.long 0x38 "EMIF_PHY_STATUS_10," bitfld.long 0x38 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x38 16.--25. 1. "PHY_REG_RDLVL_DQS_RATIO7,Read levelling DQS ratio7" newline bitfld.long 0x38 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x38 0.--9. 1. "PHY_REG_RDLVL_DQS_RATIO6,Read levelling DQS ratio6" line.long 0x3C "EMIF_PHY_STATUS_11," bitfld.long 0x3C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x3C 16.--25. 1. "PHY_REG_RDLVL_DQS_RATIO9,Read levelling DQS ratio9" newline bitfld.long 0x3C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x3C 0.--9. 1. "PHY_REG_RDLVL_DQS_RATIO8,Read levelling DQS ratio8" line.long 0x40 "EMIF_PHY_STATUS_12," bitfld.long 0x40 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x40 16.--26. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO1,Read levelling FIFO Write Enable Ratio1" newline bitfld.long 0x40 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x40 0.--10. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO0,Read levelling FIFO Write Enable Ratio0" line.long 0x44 "EMIF_PHY_STATUS_13," bitfld.long 0x44 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x44 16.--26. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO3,Read levelling FIFO Write Enable Ratio3" newline bitfld.long 0x44 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x44 0.--10. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO2,Read levelling FIFO Write Enable Ratio2" line.long 0x48 "EMIF_PHY_STATUS_14," bitfld.long 0x48 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 16.--26. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO5,Read levelling FIFO Write Enable Ratio5" newline bitfld.long 0x48 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 0.--10. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO4,Read levelling FIFO Write Enable Ratio4" line.long 0x4C "EMIF_PHY_STATUS_15," bitfld.long 0x4C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x4C 16.--26. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO7,Read levelling FIFO Wrie Enable Ratio7" newline bitfld.long 0x4C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x4C 0.--10. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO6,Read levelling FIFO Wrie Enable Ratio6" line.long 0x50 "EMIF_PHY_STATUS_16," bitfld.long 0x50 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x50 16.--26. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO9,Read levelling FIFO Write Enable Ratio9" newline bitfld.long 0x50 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x50 0.--10. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO8,Read levelling FIFO Write Enable Ratio8" line.long 0x54 "EMIF_PHY_STATUS_17," bitfld.long 0x54 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x54 16.--25. 1. "PHY_REG_WRLVL_DQ_RATIO1,Write levelling DQ ratio1" newline bitfld.long 0x54 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x54 0.--9. 1. "PHY_REG_WRLVL_DQ_RATIO0,Write levelling DQ ratio0" line.long 0x58 "EMIF_PHY_STATUS_18," bitfld.long 0x58 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x58 16.--25. 1. "PHY_REG_WRLVL_DQ_RATIO3,Write levelling DQ ratio3" newline bitfld.long 0x58 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x58 0.--9. 1. "PHY_REG_WRLVL_DQ_RATIO2,Write levelling DQ ratio2" line.long 0x5C "EMIF_PHY_STATUS_19," bitfld.long 0x5C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x5C 16.--25. 1. "PHY_REG_WRLVL_DQ_RATIO5,Write levelling DQ ratio5" newline bitfld.long 0x5C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x5C 0.--9. 1. "PHY_REG_WRLVL_DQ_RATIO4,Write levelling DQ ratio4" line.long 0x60 "EMIF_PHY_STATUS_20," bitfld.long 0x60 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x60 16.--25. 1. "PHY_REG_WRLVL_DQ_RATIO7,Write levelling DQ ratio7" newline bitfld.long 0x60 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x60 0.--9. 1. "PHY_REG_WRLVL_DQ_RATIO6,Write levelling DQ ratio6" line.long 0x64 "EMIF_PHY_STATUS_21," bitfld.long 0x64 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x64 16.--25. 1. "PHY_REG_WRLVL_DQ_RATIO9,Write levelling DQ ratio9" newline bitfld.long 0x64 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x64 0.--9. 1. "PHY_REG_WRLVL_DQ_RATIO8,Write levelling DQ ratio8" line.long 0x68 "EMIF_PHY_STATUS_22," bitfld.long 0x68 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x68 16.--25. 1. "PHY_REG_WRLVL_DQS_RATIO1,Write levelling DQS ratio 1" newline bitfld.long 0x68 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x68 0.--9. 1. "PHY_REG_WRLVL_DQS_RATIO0,Write levelling DQS ratio 0" line.long 0x6C "EMIF_PHY_STATUS_23," bitfld.long 0x6C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x6C 16.--25. 1. "PHY_REG_WRLVL_DQS_RATIO3,Write levelling DQS ratio3" newline bitfld.long 0x6C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x6C 0.--9. 1. "PHY_REG_WRLVL_DQS_RATIO2,Write levelling DQS ratio2" line.long 0x70 "EMIF_PHY_STATUS_24," bitfld.long 0x70 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x70 16.--25. 1. "PHY_REG_WRLVL_DQS_RATIO5,Write levelling DQS ratio5" newline bitfld.long 0x70 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x70 0.--9. 1. "PHY_REG_WRLVL_DQS_RATIO4,Write levelling DQS ratio4" line.long 0x74 "EMIF_PHY_STATUS_25," bitfld.long 0x74 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x74 16.--25. 1. "PHY_REG_WRLVL_DQS_RATIO7,Write levelling DQS ratio7" newline bitfld.long 0x74 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x74 0.--9. 1. "PHY_REG_WRLVL_DQS_RATIO6,Write levelling DQS ratio6" line.long 0x78 "EMIF_PHY_STATUS_26," bitfld.long 0x78 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x78 16.--25. 1. "PHY_REG_WRLVL_DQS_RATIO9,Write levelling DQS ratio9" newline bitfld.long 0x78 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x78 0.--9. 1. "PHY_REG_WRLVL_DQS_RATIO8,Write levelling DQS ratio8" line.long 0x7C "EMIF_PHY_STATUS_27," bitfld.long 0x7C 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x7C 28.--29. "PHY_REG_PHY_CONTROL_MDLL_UNLOCK_STICKY,Phy control MDLL unlock sticky" "0,1,2,3" newline bitfld.long 0x7C 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x7C 20.--24. "PHY_REG_STATUS_MDLL_UNLOCK_STICKY,Phy data MDLL unlock sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.tbyte 0x7C 0.--19. 1. "PHY_REG_RDC_FIFO_RST_ERR_CNT,RDC FIFO reset error count" line.long 0x80 "EMIF_PHY_STATUS_28," bitfld.long 0x80 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 24.--28. "PHY_REG_GATELVL_INC_FAIL,Gate levelling failure.NOTE: Incremental leveling is not supported on this device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x80 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 16.--20. "PHY_REG_WRLVL_INC_FAIL,Write levelling failure.NOTE: Incremental leveling is not supported on this device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x80 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 8.--12. "PHY_REG_RDLVL_INC_FAIL,Read levelling failure.NOTE: Incremental leveling is not supported on this device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x80 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 0.--4. "PHY_REG_FIFO_WE_IN_MIASALIGNED_STICKY,FIFO write enable in misaligned stickly" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x200++0x11F line.long 0x00 "EMIF_EXT_PHY_CONTROL_1,Control DLL Slave Ratio Register" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 20.--29. 1. "PHY_REG_CTRL_SLAVE_RATIO2,The user programmable ratio value for address/command launch timing in PHY control macro 2" newline hexmask.long.word 0x00 10.--19. 1. "PHY_REG_CTRL_SLAVE_RATIO1,The user programmable ratio value for address/command launch timing in PHY control macro 1" newline hexmask.long.word 0x00 0.--9. 1. "PHY_REG_CTRL_SLAVE_RATIO0,The user programmable ratio value for address/command launch timing in PHY control macro 0" line.long 0x04 "EMIF_EXT_PHY_CONTROL_1_SHADOW,Control DLL Slave Ratio Shadow Register" rbitfld.long 0x04 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x04 20.--29. 1. "PHY_REG_CTRL_SLAVE_RATIO2,The user programmable ratio value for address/command launch timing in PHY control macro 2" newline hexmask.long.word 0x04 10.--19. 1. "PHY_REG_CTRL_SLAVE_RATIO1,The user programmable ratio value for address/command launch timing in PHY control macro 1" newline hexmask.long.word 0x04 0.--9. 1. "PHY_REG_CTRL_SLAVE_RATIO0,The user programmable ratio value for address/command launch timing in PHY control macro 0" line.long 0x08 "EMIF_EXT_PHY_CONTROL_2,Data macro 0. FIFO write enable (read DQS gate) DLL Slave Ratio Register" rbitfld.long 0x08 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x08 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO1,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0x08 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x08 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO0,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0 chip select 0" line.long 0x0C "EMIF_EXT_PHY_CONTROL_2_SHADOW,Data macro 0. FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register" rbitfld.long 0x0C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x0C 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO1,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0x0C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x0C 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO0,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0 chip select 0" line.long 0x10 "EMIF_EXT_PHY_CONTROL_3,Data macro 1. FIFO write enable (read DQS gate) DLL Slave Ratio Register" rbitfld.long 0x10 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x10 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO3,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0x10 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x10 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO2,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1 chip select 0" line.long 0x14 "EMIF_EXT_PHY_CONTROL_3_SHADOW,Data macro 1. FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register" rbitfld.long 0x14 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x14 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO3,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0x14 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x14 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO2,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1 chip select 0" line.long 0x18 "EMIF_EXT_PHY_CONTROL_4,Data macro 2. FIFO write enable (read DQS gate) DLL Slave Ratio Register" rbitfld.long 0x18 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x18 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO5,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x18 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x18 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO4,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2 chip select 0" line.long 0x1C "EMIF_EXT_PHY_CONTROL_4_SHADOW,Data macro 2. FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register" rbitfld.long 0x1C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x1C 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO5,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x1C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x1C 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO4,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2 chip select 0" line.long 0x20 "EMIF_EXT_PHY_CONTROL_5,Data macro 3. FIFO write enable (read DQS gate) DLL Slave Ratio Register" rbitfld.long 0x20 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x20 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO7,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x20 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x20 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO6,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3 chip select 0" line.long 0x24 "EMIF_EXT_PHY_CONTROL_5_SHADOW,Data macro 3. FIFO write enable (read DQS gate) DLL Slave Ratio Register" rbitfld.long 0x24 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x24 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO7,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x24 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x24 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO6,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3 chip select 0" line.long 0x28 "EMIF_EXT_PHY_CONTROL_6,ECC Data macro. FIFO write enable (read DQS gate) DLL Slave Ratio Register" rbitfld.long 0x28 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x28 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO9,The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0x28 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x28 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO8,The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro chip select 0" line.long 0x2C "EMIF_EXT_PHY_CONTROL_6_SHADOW,ECC Data macro. FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register" rbitfld.long 0x2C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x2C 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO9,The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0x2C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x2C 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO8,The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro chip select 0" line.long 0x30 "EMIF_EXT_PHY_CONTROL_7,Data macro 0. read DQS DLL Slave Ratio Register" rbitfld.long 0x30 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x30 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO1,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0x30 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x30 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO0,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0 chip select 0" line.long 0x34 "EMIF_EXT_PHY_CONTROL_7_SHADOW,Data macro 0. read DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x34 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x34 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO1,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0x34 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x34 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO0,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0 chip select 0" line.long 0x38 "EMIF_EXT_PHY_CONTROL_8,Data macro 1. read DQS DLL Slave Ratio Register" rbitfld.long 0x38 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x38 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO3,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0x38 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x38 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO2,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1 chip select 0" line.long 0x3C "EMIF_EXT_PHY_CONTROL_8_SHADOW,Data macro 1. read DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x3C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x3C 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO3,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0x3C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x3C 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO2,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1 chip select 0" line.long 0x40 "EMIF_EXT_PHY_CONTROL_9,Data macro 2. read DQS DLL Slave Ratio Register" rbitfld.long 0x40 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x40 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO5,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x40 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x40 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO4,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x44 "EMIF_EXT_PHY_CONTROL_9_SHADOW,Data macro 2. read DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x44 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x44 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO5,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x44 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x44 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO4,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x48 "EMIF_EXT_PHY_CONTROL_10,Data macro 3. read DQS DLL Slave Ratio Register" rbitfld.long 0x48 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x48 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO7,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x48 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x48 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO6,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3 chip select 0" line.long 0x4C "EMIF_EXT_PHY_CONTROL_10_SHADOW,Data macro 3. read DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x4C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x4C 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO7,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x4C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x4C 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO6,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3 chip select 0" line.long 0x50 "EMIF_EXT_PHY_CONTROL_11,ECC Data macro. read DQS DLL Slave Ratio Register" rbitfld.long 0x50 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x50 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO9,The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0x50 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x50 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO8,The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro chip select 0" line.long 0x54 "EMIF_EXT_PHY_CONTROL_11_SHADOW,ECC Data macro. read DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x54 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x54 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO9,The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0x54 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x54 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO8,The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro chip select 0" line.long 0x58 "EMIF_EXT_PHY_CONTROL_12,Data macro 0. write DQ (data) DLL Slave Ratio Register" rbitfld.long 0x58 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x58 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO1,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0x58 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x58 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO0,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0 chip select 0" line.long 0x5C "EMIF_EXT_PHY_CONTROL_12_SHADOW,Data macro 0. write DQ (data) DLL Slave Ratio Shadow Register" rbitfld.long 0x5C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x5C 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO1,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0x5C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x5C 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO0,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0 chip select 0" line.long 0x60 "EMIF_EXT_PHY_CONTROL_13,Data macro 1. write DQ (data) DLL Slave Ratio Register" rbitfld.long 0x60 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x60 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO3,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0x60 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x60 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO2,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1 chip select 0" line.long 0x64 "EMIF_EXT_PHY_CONTROL_13_SHADOW,Data macro 1. write DQ (data) DLL Slave Ratio Shadow Register" rbitfld.long 0x64 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x64 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO3,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0x64 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x64 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO2,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1 chip select 0" line.long 0x68 "EMIF_EXT_PHY_CONTROL_14,Data macro 2. write DQ (data) DLL Slave Ratio Register" rbitfld.long 0x68 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x68 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO5,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x68 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x68 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO4,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2 chip select 0" line.long 0x6C "EMIF_EXT_PHY_CONTROL_14_SHADOW,Data macro 2. write DQ (data) DLL Slave Ratio Shadow Register" rbitfld.long 0x6C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x6C 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO5,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x6C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x6C 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO4,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2 chip select 0" line.long 0x70 "EMIF_EXT_PHY_CONTROL_15,Data macro 3. write DQ (data) DLL Slave Ratio Register" rbitfld.long 0x70 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x70 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO7,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x70 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x70 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO6,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3 chip select 0" line.long 0x74 "EMIF_EXT_PHY_CONTROL_15_SHADOW,Data macro 3. write DQ (data) DLL Slave Ratio Shadow Register" rbitfld.long 0x74 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x74 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO7,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x74 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x74 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO6,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3 chip select 0" line.long 0x78 "EMIF_EXT_PHY_CONTROL_16,ECC Data macro. write DQ (data) DLL Slave Ratio Register" rbitfld.long 0x78 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x78 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO9,The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0x78 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x78 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO8,The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro chip select 0" line.long 0x7C "EMIF_EXT_PHY_CONTROL_16_SHADOW,ECC Data macro. write DQ (data) DLL Slave Ratio Shadow Register" rbitfld.long 0x7C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x7C 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO9,The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0x7C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x7C 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO8,The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro chip select 0" line.long 0x80 "EMIF_EXT_PHY_CONTROL_17,Data macro 0. write DQS DLL Slave Ratio Register" rbitfld.long 0x80 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x80 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO1,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0x80 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x80 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO0,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0 chip select 0" line.long 0x84 "EMIF_EXT_PHY_CONTROL_17_SHADOW,Data macro 0. write DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x84 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x84 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO1,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0x84 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x84 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO0,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0 chip select 0" line.long 0x88 "EMIF_EXT_PHY_CONTROL_18,Data macro 1. write DQS DLL Slave Ratio Register" rbitfld.long 0x88 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x88 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO3,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0x88 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x88 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO2,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1 chip select 0" line.long 0x8C "EMIF_EXT_PHY_CONTROL_18_SHADOW,Data macro 1. write DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x8C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x8C 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO3,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0x8C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x8C 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO2,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1 chip select 0" line.long 0x90 "EMIF_EXT_PHY_CONTROL_19,Data macro 2. write DQS DLL Slave Ratio Register" rbitfld.long 0x90 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x90 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO5,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x90 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x90 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO4,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x94 "EMIF_EXT_PHY_CONTROL_19_SHADOW,Data macro 2. write DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x94 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x94 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO5,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x94 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x94 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO4,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x98 "EMIF_EXT_PHY_CONTROL_20,Data macro 3. write DQS DLL Slave Ratio Register" rbitfld.long 0x98 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x98 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO7,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x98 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x98 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO6,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3 chip select 0" line.long 0x9C "EMIF_EXT_PHY_CONTROL_20_SHADOW,Data macro 3. write DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x9C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x9C 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO7,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x9C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x9C 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO6,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3 chip select 0" line.long 0xA0 "EMIF_EXT_PHY_CONTROL_21,ECC Data macro. write DQS DLL Slave Ratio Register" rbitfld.long 0xA0 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xA0 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO9,The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0xA0 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xA0 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO8,The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro chip select 0" line.long 0xA4 "EMIF_EXT_PHY_CONTROL_21_SHADOW,ECC Data macro. write DQS DLL Slave Ratio Shadow Register" rbitfld.long 0xA4 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xA4 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO9,The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0xA4 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xA4 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO8,The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro chip select 0" line.long 0xA8 "EMIF_EXT_PHY_CONTROL_22," hexmask.long.byte 0xA8 25.--31. 1. "RESERVED," newline hexmask.long.word 0xA8 16.--24. 1. "PHY_REG_FIFO_WE_IN_DELAY,The user programmable FIFO write enable delay value used when DLL_OVERRIDE = 1" newline hexmask.long.byte 0xA8 9.--15. 1. "RESERVED," newline hexmask.long.word 0xA8 0.--8. 1. "PHY_REG_CTRL_SLAVE_DELAY,The user programmable command delay value used when DLL_OVERRIDE = 1" line.long 0xAC "EMIF_EXT_PHY_CONTROL_22_SHADOW," hexmask.long.byte 0xAC 25.--31. 1. "RESERVED," newline hexmask.long.word 0xAC 16.--24. 1. "PHY_REG_FIFO_WE_IN_DELAY,The user programmable FIFO write enable delay value used when DLL_OVERRIDE = 1" newline hexmask.long.byte 0xAC 9.--15. 1. "RESERVED," newline hexmask.long.word 0xAC 0.--8. 1. "PHY_REG_CTRL_SLAVE_DELAY,The user programmable command delay value used when DLL_OVERRIDE = 1" line.long 0xB0 "EMIF_EXT_PHY_CONTROL_23," hexmask.long.byte 0xB0 25.--31. 1. "RESERVED," newline hexmask.long.word 0xB0 16.--24. 1. "PHY_REG_WR_DQS_SLAVE_DELAY,The user programmable write DQS delay value used when DLL_OVERRIDE = 1" newline hexmask.long.byte 0xB0 9.--15. 1. "RESERVED," newline hexmask.long.word 0xB0 0.--8. 1. "PHY_REG_RD_DQS_SLAVE_DELAY,The user programmable read DQS delay value used when DLL_OVERRIDE = 1" line.long 0xB4 "EMIF_EXT_PHY_CONTROL_23_SHADOW," hexmask.long.byte 0xB4 25.--31. 1. "RESERVED," newline hexmask.long.word 0xB4 16.--24. 1. "PHY_REG_WR_DQS_SLAVE_DELAY,The user programmable write DQS delay value used when DLL_OVERRIDE = 1" newline hexmask.long.byte 0xB4 9.--15. 1. "RESERVED," newline hexmask.long.word 0xB4 0.--8. 1. "PHY_REG_RD_DQS_SLAVE_DELAY,The user programmable read DQS delay value used when DLL_OVERRIDE = 1" line.long 0xB8 "EMIF_EXT_PHY_CONTROL_24," rbitfld.long 0xB8 31. "RESERVED," "0,1" newline hexmask.long.byte 0xB8 24.--30. 1. "REG_PHY_DQ_OFFSET_HI,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xB8 17.--23. 1. "RESERVED," newline bitfld.long 0xB8 16. "REG_PHY_GATELVL_INIT_MODE,The user programmable init ratio selection mode" "0,1" newline rbitfld.long 0xB8 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 12. "REG_PHY_USE_RANK0_DELAYS,Delay selection" "0,1" newline rbitfld.long 0xB8 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xB8 0.--8. 1. "REG_PHY_WR_DATA_SLAVE_DELAY,The user programmable write DQ delay value used when DLL_OVERRIDE = 1" line.long 0xBC "EMIF_EXT_PHY_CONTROL_24_SHADOW," rbitfld.long 0xBC 31. "RESERVED," "0,1" newline hexmask.long.byte 0xBC 24.--30. 1. "REG_PHY_DQ_OFFSET_HI,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xBC 17.--23. 1. "RESERVED," newline bitfld.long 0xBC 16. "REG_PHY_GATELVL_INIT_MODE,The user programmable init ratio selection mode" "0,1" newline rbitfld.long 0xBC 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0xBC 12. "REG_PHY_USE_RANK0_DELAYS,Delay selection" "0,1" newline rbitfld.long 0xBC 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xBC 0.--8. 1. "REG_PHY_WR_DATA_SLAVE_DELAY,The user programmable write DQ delay value used when DLL_OVERRIDE = 1" line.long 0xC0 "EMIF_EXT_PHY_CONTROL_25,DQ DLL Slave Ratio Offset Register" rbitfld.long 0xC0 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0xC0 21.--27. 1. "REG_PHY_DQ_OFFSET3,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC0 14.--20. 1. "REG_PHY_DQ_OFFSET2,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC0 7.--13. 1. "REG_PHY_DQ_OFFSET1,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC0 0.--6. 1. "REG_PHY_DQ_OFFSET0,The user programmable offset ratio value from write DQS to write DQ" line.long 0xC4 "EMIF_EXT_PHY_CONTROL_25_SHADOW,DQ DLL Slave Ratio Offset Shadow Register" rbitfld.long 0xC4 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0xC4 21.--27. 1. "REG_PHY_DQ_OFFSET3,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC4 14.--20. 1. "REG_PHY_DQ_OFFSET2,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC4 7.--13. 1. "REG_PHY_DQ_OFFSET1,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC4 0.--6. 1. "REG_PHY_DQ_OFFSET0,The user programmable offset ratio value from write DQS to write DQ" line.long 0xC8 "EMIF_EXT_PHY_CONTROL_26,Data macro 0. FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" rbitfld.long 0xC8 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xC8 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO1,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0xC8 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xC8 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO0,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0 chip select 0" line.long 0xCC "EMIF_EXT_PHY_CONTROL_26_SHADOW,Data macro 0. FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register" rbitfld.long 0xCC 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xCC 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO1,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0xCC 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xCC 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO0,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0 chip select 0" line.long 0xD0 "EMIF_EXT_PHY_CONTROL_27,Data macro 1. FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" rbitfld.long 0xD0 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xD0 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO3,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0xD0 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xD0 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO2,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1 chip select 0" line.long 0xD4 "EMIF_EXT_PHY_CONTROL_27_SHADOW,Data macro 1. FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register" rbitfld.long 0xD4 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xD4 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO3,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0xD4 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xD4 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO2,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1 chip select 0" line.long 0xD8 "EMIF_EXT_PHY_CONTROL_28,Data macro 2. FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" rbitfld.long 0xD8 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xD8 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO5,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0xD8 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xD8 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO4,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2 chip select 0" line.long 0xDC "EMIF_EXT_PHY_CONTROL_28_SHADOW,Data macro 2. FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register" rbitfld.long 0xDC 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xDC 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO5,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0xDC 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xDC 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO4,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2 chip select 0" line.long 0xE0 "EMIF_EXT_PHY_CONTROL_29,Data macro 3. FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" rbitfld.long 0xE0 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xE0 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO7,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0xE0 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xE0 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO6,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3 chip select 0" line.long 0xE4 "EMIF_EXT_PHY_CONTROL_29_SHADOW,Data macro 3. FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register" rbitfld.long 0xE4 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xE4 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO7,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0xE4 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xE4 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO6,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3 chip select 0" line.long 0xE8 "EMIF_EXT_PHY_CONTROL_30,ECC Data macro. FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" rbitfld.long 0xE8 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xE8 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO9,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0xE8 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xE8 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO8,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro chip select 0" line.long 0xEC "EMIF_EXT_PHY_CONTROL_30_SHADOW,ECC Data macro. FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register" rbitfld.long 0xEC 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xEC 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO9,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0xEC 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xEC 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO8,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro chip select 0" line.long 0xF0 "EMIF_EXT_PHY_CONTROL_31,Data macro 0. write DQS DLL Slave Init Ratio Register" rbitfld.long 0xF0 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xF0 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO1,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0xF0 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xF0 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO0,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0 chip select 0" line.long 0xF4 "EMIF_EXT_PHY_CONTROL_31_SHADOW,Data macro 0. write DQS DLL Slave Init Ratio Shadow Register" rbitfld.long 0xF4 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xF4 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO1,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0xF4 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xF4 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO0,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0 chip select 0" line.long 0xF8 "EMIF_EXT_PHY_CONTROL_32,Data macro 1. write DQS DLL Slave Init Ratio Register" rbitfld.long 0xF8 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xF8 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO3,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0xF8 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xF8 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO2,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1 chip select 0" line.long 0xFC "EMIF_EXT_PHY_CONTROL_32_SHADOW,Data macro 1. write DQS DLL Slave Init Ratio Shadow Register" rbitfld.long 0xFC 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xFC 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO3,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0xFC 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xFC 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO2,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1 chip select 0" line.long 0x100 "EMIF_EXT_PHY_CONTROL_33,Data macro 2. write DQS DLL Slave Init Ratio Register" rbitfld.long 0x100 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x100 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO5,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x100 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x100 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO4,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x104 "EMIF_EXT_PHY_CONTROL_33_SHADOW,Data macro 2. write DQS DLL Slave Init Ratio Shadow Register" rbitfld.long 0x104 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x104 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO5,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x104 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x104 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO4,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x108 "EMIF_EXT_PHY_CONTROL_34,Data macro 3. write DQS DLL Slave Init Ratio Register" rbitfld.long 0x108 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x108 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO7,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x108 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x108 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO6,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3 chip select 0" line.long 0x10C "EMIF_EXT_PHY_CONTROL_34_SHADOW,Data macro 3. write DQS DLL Slave Init Ratio Shadow Register" rbitfld.long 0x10C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x10C 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO7,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x10C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x10C 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO6,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3 chip select 0" line.long 0x110 "EMIF_EXT_PHY_CONTROL_35,ECC Data macro. write DQS DLL Slave Init Ratio Register" rbitfld.long 0x110 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x110 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO9,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0x110 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x110 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO8,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro chip select 0" line.long 0x114 "EMIF_EXT_PHY_CONTROL_35_SHADOW,ECC Data macro. write DQS DLL Slave Init Ratio Shadow Register" rbitfld.long 0x114 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x114 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO9,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0x114 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x114 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO8,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro chip select 0" line.long 0x118 "EMIF_EXT_PHY_CONTROL_36," hexmask.long.tbyte 0x118 11.--31. 1. "RESERVED," newline bitfld.long 0x118 10. "REG_PHY_RDC_FIFO_RST_ERR_CNT_CLR,Clear/reset the phy_reg_rdc_fifo_rst_err_cnt phy_reg_rdfifo_wrptr and phy_reg_rdfifo_rdptr status flags" "0,1" newline bitfld.long 0x118 9. "REG_PHY_MDLL_UNLOCK_CLR,Clears the phy_reg_status_mdll_unlock_sticky flag" "0,1" newline bitfld.long 0x118 8. "REG_PHY_FIFO_WE_IN_MISALIGNED_CLR,Clears the phy_reg_fifo_we_in_misaligned_sticky status flag" "0,1" newline bitfld.long 0x118 4.--7. "REG_PHY_WRLVL_NUM_OF_DQ0,Determines the number of samples fordq0_in for each ratio increment by the write leveling finite state machine (hardware leveling)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x118 0.--3. "REG_PHY_GATELVL_NUM_OF_DQ0,Determines the number of samples fordq0_in for each ratio increment by the gate training finite state machine (hardware leveling)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x11C "EMIF_EXT_PHY_CONTROL_36_SHADOW," hexmask.long.tbyte 0x11C 11.--31. 1. "RESERVED," newline bitfld.long 0x11C 10. "REG_PHY_RDC_FIFO_RST_ERR_CNT_CLR,Clear/reset the phy_reg_rdc_fifo_rst_err_cnt phy_reg_rdfifo_wrptr and phy_reg_rdfifo_rdptr status flags" "0,1" newline bitfld.long 0x11C 9. "REG_PHY_MDLL_UNLOCK_CLR,Clears the phy_reg_status_mdll_unlock_sticky flag" "0,1" newline bitfld.long 0x11C 8. "REG_PHY_FIFO_WE_IN_MISALIGNED_CLR,Clears the phy_reg_fifo_we_in_misaligned_sticky status flag" "0,1" newline bitfld.long 0x11C 4.--7. "REG_PHY_WRLVL_NUM_OF_DQ0,Determines the number of samples fordq0_in for each ratio increment by the write leveling finite state machine (hardware leveling)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x11C 0.--3. "REG_PHY_GATELVL_NUM_OF_DQ0,Determines the number of samples fordq0_in for each ratio increment by the gate training finite state machine (hardware leveling)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "EMIF_FW" base ad:0x4A20C000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" newline rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x100++0x03 line.long 0x00 "START_REGION_i_8,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x110++0x03 line.long 0x00 "START_REGION_i_9,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x120++0x03 line.long 0x00 "START_REGION_i_10,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x130++0x03 line.long 0x00 "START_REGION_i_11,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x140++0x03 line.long 0x00 "START_REGION_i_12,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x150++0x03 line.long 0x00 "START_REGION_i_13,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x160++0x03 line.long 0x00 "START_REGION_i_14,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x170++0x03 line.long 0x00 "START_REGION_i_15,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x180++0x03 line.long 0x00 "START_REGION_i_16,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x190++0x03 line.long 0x00 "START_REGION_i_17,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1A0++0x03 line.long 0x00 "START_REGION_i_18,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1B0++0x03 line.long 0x00 "START_REGION_i_19,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1C0++0x03 line.long 0x00 "START_REGION_i_20,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1D0++0x03 line.long 0x00 "START_REGION_i_21,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1E0++0x03 line.long 0x00 "START_REGION_i_22,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1F0++0x03 line.long 0x00 "START_REGION_i_23,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x104++0x03 line.long 0x00 "END_REGION_i_8,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x114++0x03 line.long 0x00 "END_REGION_i_9,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x124++0x03 line.long 0x00 "END_REGION_i_10,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x134++0x03 line.long 0x00 "END_REGION_i_11,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x144++0x03 line.long 0x00 "END_REGION_i_12,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x154++0x03 line.long 0x00 "END_REGION_i_13,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x164++0x03 line.long 0x00 "END_REGION_i_14,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x174++0x03 line.long 0x00 "END_REGION_i_15,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x184++0x03 line.long 0x00 "END_REGION_i_16,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x194++0x03 line.long 0x00 "END_REGION_i_17,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1A4++0x03 line.long 0x00 "END_REGION_i_18,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1B4++0x03 line.long 0x00 "END_REGION_i_19,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1C4++0x03 line.long 0x00 "END_REGION_i_20,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1D4++0x03 line.long 0x00 "END_REGION_i_21,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1E4++0x03 line.long 0x00 "END_REGION_i_22,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1F4++0x03 line.long 0x00 "END_REGION_i_23,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x108++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_8,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x118++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_9,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x128++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_10,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x138++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_11,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x148++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_12,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x158++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_13,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x168++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_14,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x178++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_15,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x188++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_16,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x198++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_17,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1A8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_18,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1B8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_19,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_20,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1D8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_21,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_22,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1F8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_23,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x10C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_8,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x11C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_9,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x12C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_10,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x13C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_11,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x14C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_12,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x15C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_13,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x16C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_14,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x17C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_15,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x18C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_16,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x19C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_17,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1AC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_18,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1BC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_19,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1CC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_20,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1DC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_21,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1EC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_22,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1FC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_23,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "EMIF_FW_CFG_TARG" base ad:0x4A20D000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "EMIF_P1_TARG" base ad:0x44000200 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "EMU_CM" base ad:0x4AE07A00 group.long 0x00++0x0F line.long 0x00 "CM_EMU_CLKSTCTRL,This register enables the EMU domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_EMU_SYS_CLK,This field indicates the state of the EMU_SYS_CLK clock in the domain" "CLKACTIVITY_EMU_SYS_CLK_0,CLKACTIVITY_EMU_SYS_CLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the EMU clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_EMU_DEBUGSS_CLKCTRL,This register manages the DEBUGSS clocks" hexmask.long.word 0x04 19.--31. 1. "RESERVED," bitfld.long 0x04 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline bitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x04 2.--15. 1. "RESERVED," newline bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" line.long 0x08 "CM_EMU_DYNAMICDEP,This register controls the dynamic domain depedencies from EMU domain towards 'target' domains" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.tbyte 0x08 6.--23. 1. "RESERVED," rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "CM_EMU_MPU_EMU_DBG_CLKCTRL,This register manages the MPU_EMU_DBG clocks" hexmask.long.word 0x0C 18.--31. 1. "RESERVED," bitfld.long 0x0C 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x0C 2.--15. 1. "RESERVED," bitfld.long 0x0C 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" width 0x0B tree.end tree "EMU_PRM" base ad:0x4AE07900 rgroup.long 0x00++0x07 line.long 0x00 "PM_EMU_PWRSTCTRL,This register controls the EMU power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," bitfld.long 0x00 16.--17. "EMU_BANK_ONSTATE,EMU memory state when domain is ON" "?,?,?,EMU_BANK_ONSTATE_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,?,?,?" line.long 0x04 "PM_EMU_PWRSTST,This register provides a status on the EMU domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "EMU_BANK_STATEST,EMU memory bank state status" "EMU_BANK_STATEST_0,EMU_BANK_STATEST_1,EMU_BANK_STATEST_2,EMU_BANK_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,?,?,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_EMU_DEBUGSS_CONTEXT,This register contains dedicated DEBUGSS context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_EMU_BANK,Specify if memory-based context in EMU_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EMU_BANK_0,LOSTMEM_EMU_BANK_1" hexmask.long.byte 0x00 1.--7. 1. "RESERVED," newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "ESM" base ad:0x4A23C000 group.long 0x00++0x17 line.long 0x00 "ESMIEPSR1,ESM Influence Error Pin Set/Status Register 1" line.long 0x04 "ESMIEPCR1,ESM Influence Error Pin Clear/Status Register 1" line.long 0x08 "ESMIESR1,ESM Interrupt Enable Set/Status Register 1" line.long 0x0C "ESMIECR1,ESM Interrupt Enable Clear/Status Register 1" line.long 0x10 "ESMILSR1,ESM Interrupt Level Set/Status Register 1" line.long 0x14 "ESMILCR1,ESM Interrupt Level Clear/Status Register 1" group.long 0x20++0x37 line.long 0x00 "ESMSR3,ESM Status Register 3" line.long 0x04 "ESMEPSR,ESM Error Pin Status Register" hexmask.long 0x04 1.--31. 1. "RES,Reads return 0 and writes have no effect" bitfld.long 0x04 0. "EPSF,Provides status information for the Error Pin" "Error Pin is low (active) if any error has..,Error Pin is high if no error has occurred User.." line.long 0x08 "ESMIOFFHR,ESM Interrupt Offset High Register" hexmask.long.tbyte 0x08 9.--31. 1. "RES,Reads return 0 and writes have no effect" abitfld.long 0x08 0.--8. "INTOFFH,This vector gives the channel number of the highest pending interrupt request for the high level interrupt line" "0x000=no pending interrupt,0x001=interrupt pending for channel 0 error group1,0x020=interrupt pending for channel 31 error..,0x021=interrupt pending for channel 0 error group2,0x040=interrupt pending for channel 31 error..,0x041=interrupt pending for channel 32 error..,0x060=interrupt pending for channel 63 error..,0x061=interrupt pending for channel 32 error..,0x080=interrupt pending for channel 63 error..,0x081=interrupt pending for channel 64 error..,0x0A0=interrupt pending for channel 95 error..,0x0A1=interrupt pending for channel 64 error..,0x0C0=interrupt pending for channel 95 error..,0x0C1=interrupt pending for channel 96 error..,0x0E0=interrupt pending for channel 127 error..,0x0E1=interrupt pending for channel 96 error..,0x100=interrupt pending for channel 127 error.." line.long 0x0C "ESMIOFFLR,ESM Interrupt Offset Low Register" hexmask.long.tbyte 0x0C 8.--31. 1. "RES,Reads return 0 and writes have no effect" abitfld.long 0x0C 0.--7. "INTOFFL,This vector gives the channel number of the highest pending interrupt request for the low level interrupt line" "0x00=no pending interrupt,0x01=interrupt pending for channel 0 error group1,0x20=interrupt pending for channel 31 error group1,0x41=interrupt pending for channel 32 error group1,0x60=interrupt pending for channel 63 error group1,0x81=interrupt pending for channel 64 error group1,0xA0=interrupt pending for channel 95 error group1,0xC1=interrupt pending for channel 96 error group1,0xE0=interrupt pending for channel 127 error.." line.long 0x10 "ESMLTCR,ESM Low-Time Counter Register" hexmask.long.word 0x10 16.--31. 1. "RES,Reads return 0 and writes have no effect" hexmask.long.word 0x10 0.--15. 1. "LTC,16bit pre-loadable down-counter to control low-time of error pin" line.long 0x14 "ESMLTCPR,ESM Low-Time Counter Preload Register" hexmask.long.word 0x14 16.--31. 1. "RES,Reads return 0 and writes have no effect" bitfld.long 0x14 14.--15. "LTCPW,LTCP.15 and LTCP.14 are configurable (privilege mode write) to ensure a minimum low time of 100us running at a maximum frequency of 100MHz" "0,1,2,3" hexmask.long.word 0x14 0.--13. 1. "LTCPR,pre-load value for the error pin low-time counter" line.long 0x18 "ESMEKR,ESM Error Key Register" hexmask.long 0x18 4.--31. 1. "RES,Reads return 0 and writes have no effect" bitfld.long 0x18 0.--3. "EKEY,Key to reset the error pin or to force an error on the error pin" "activates normal mode (recommended default mode),?,?,?,?,error pin will be set to high when the low time..,?,?,?,?,forces error on error pin,?..." line.long 0x1C "ESMSSR2,ESM Status Shadow Register 2" line.long 0x20 "ESMIEPSR4,ESM Influence Error Pin Set/Status Register 4" line.long 0x24 "ESMIEPCR4,ESM Influence Error Pin Clear/Status Register 4" line.long 0x28 "ESMIESR4,ESM Interrupt Enable Set/Status Register 4" line.long 0x2C "ESMIECR4,ESM Interrupt Enable Clear/Status Register 4" line.long 0x30 "ESMILSR4,ESM Interrupt Level Set/Status Register 4" line.long 0x34 "ESMILCR4,ESM Interrupt Level Clear/Status Register 4" group.long 0x5C++0x0B line.long 0x00 "ESMSR5,ESM Status Register 5" line.long 0x04 "ESMSR6,ESM Status Register 6" line.long 0x08 "ESMSSR5,ESM Status Shadow Register 5" group.long 0x80++0x17 line.long 0x00 "ESMIEPSR7,ESM Influence Error Pin Set/Status Register 7" line.long 0x04 "ESMIEPCR7,ESM Influence Error Pin Clear/Status Register 7" line.long 0x08 "ESMIESR7,ESM Interrupt Enable Set/Status Register 7" line.long 0x0C "ESMIECR7,ESM Interrupt Enable Clear/Status Register 7" line.long 0x10 "ESMILSR7,ESM Interrupt Level Set/Status Register 7" line.long 0x14 "ESMILCR7,ESM Interrupt Level Clear/Status Register 7" group.long 0x9C++0x0B line.long 0x00 "ESMSR8,ESM Status Register 8" line.long 0x04 "ESMSR9,ESM Status Register 9" line.long 0x08 "ESMSSR8,ESM Status Shadow Register 8" group.long 0xC0++0x17 line.long 0x00 "ESMIEPSR10,ESM Influence Error Pin Set/Status Register 10" line.long 0x04 "ESMIEPCR10,ESM Influence Error Pin Clear/Status Register 10" line.long 0x08 "ESMIESR10,ESM Interrupt Enable Set/Status Register 10" line.long 0x0C "ESMIECR10,ESM Interrupt Enable Clear/Status Register 10" line.long 0x10 "ESMILSR10,ESM Interrupt Level Set/Status Register 10" line.long 0x14 "ESMILCR10,ESM Interrupt Level Clear/Status Register 10" group.long 0xDC++0x0B line.long 0x00 "ESMSR11,ESM Status Register 11" line.long 0x04 "ESMSR12,ESM Status Register 12" line.long 0x08 "ESMSSR11,ESM Status Shadow Register 11" repeat 5. (list 1. 2. 4. 7. 10. )(list 0x00 0x04 0x40 0x80 0xC0 ) group.long ($2+0x18)++0x03 line.long 0x00 "ESMSR$1,ESM Status Register 1" repeat.end width 0x0B tree.end tree "ESM_TARG" base ad:0x4A23D000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "EVE" base ad:0x42000000 rgroup.long 0x80000++0x2F line.long 0x00 "EVE_REVISION," line.long 0x04 "EVE_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," newline bitfld.long 0x04 0.--3. "EVENUM,EVE instance number set by eve_num inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EVE_SYSCONFIG," hexmask.long 0x08 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x08 4.--5. "STANDBYMODE," "?,No-Standby,Smart-Standby,Smart-Standby-Wkup" newline bitfld.long 0x08 2.--3. "IDLEMODE," "?,No-idle,Smart-idle,SmartIdleWkup" newline rbitfld.long 0x08 1. "FREEEMU,Resered" "0,1" newline rbitfld.long 0x08 0. "SOFTRESET,Reserved" "0,1" line.long 0x0C "EVE_STAT," hexmask.long.word 0x0C 22.--31. 1. "RESERVED," newline bitfld.long 0x0C 20.--21. "OCPI_DISC_STAT,OCP Initiator(s) Disconnect status2" "OCPI_DISC_STAT_0,OCPI_DISC_STAT_1,OCPI_DISC_STAT_2,?" newline bitfld.long 0x0C 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 16.--17. "ARP32_DISC_STATUS,ARP32 Program/Data Bus Disconnect Status 2" "ARP32_DISC_STATUS_0,ARP32_DISC_STATUS_1,ARP32_DISC_STATUS_2,?" newline hexmask.long.byte 0x0C 9.--15. 1. "RESERVED," newline bitfld.long 0x0C 8. "INT_OUT_STAT,Interrupt Output status" "INT_OUT_STAT_0,INT_OUT_STAT_1" newline bitfld.long 0x0C 7. "ARP32_INTC_STAT,Interrupt Controller Status" "ARP32_INTC_STAT_0,ARP32_INTC_STAT_1" newline bitfld.long 0x0C 6. "RESERVED," "0,1" newline bitfld.long 0x0C 5. "TC1_STAT,Transfer Controller1 Status" "TC1_STAT_0,TC1_STAT_1" newline bitfld.long 0x0C 4. "TC0_STAT,Transfer Controller0 Status" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "PC_STAT,Program Cache Status" "PC_STAT_0,PC_STAT_1" newline bitfld.long 0x0C 1. "VCOP_STAT,VCOP Status" "VCOP_STAT_0,VCOP_STAT_1" newline bitfld.long 0x0C 0. "ARP32_STAT,Program Cache Status" "ARP32_STAT_0,ARP32_STAT_1" line.long 0x10 "EVE_DISC_CONFIG,Color 0 noise threshold" hexmask.long 0x10 5.--31. 1. "RESERVED," newline bitfld.long 0x10 4. "OCPI_DISC,OCP Initiator Disconnect request" "OCPI_DISC_0_r,OCPI_DISC_1_w" newline rbitfld.long 0x10 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0. "ARP32_DISC,ARP32 Initiator Disconnect request" "?,ARP32_DISC_1_r" line.long 0x14 "EVE_BUS_CONFIG,Color 0 noise threshold" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED," newline bitfld.long 0x14 12.--13. "TC1_DBS,TC1 default burst size" "16 byte,32 byte,64 byte,128 byte.." newline rbitfld.long 0x14 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 8.--9. "TC0_DBS,TC0 default burst size" "16 byte,32 byte,64 byte,128 byte.." newline rbitfld.long 0x14 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 4. "DBP_ENABLE,Program Cache Demand Based Prefetch enable" "DBP_ENABLE_0,DBP_ENABLE_1" newline bitfld.long 0x14 0.--3. "MAX_IN_FLIGHT,Defines maximum number of OCP requests in flight" "Reserved,1 request in flight allowed,2 requests in flight allowed,?..." line.long 0x18 "EVE_VCOP_HALT_CONFIG," hexmask.long 0x18 3.--31. 1. "RESERVED," newline bitfld.long 0x18 2. "FORCE_ABORT,VCOP Force Abort Write: Read always returns 0sWrite 0 has no effect" "?,FORCE_ABORT_1_w" newline bitfld.long 0x18 1. "MSW_EN,VCOP Memory Seitch Error Halt Enable" "MSW_EN_0,MSW_EN_1" newline bitfld.long 0x18 0. "ED_EN,VCOP Parity Error Detect Halt Enable" "ED_EN_0,ED_EN_1" line.long 0x1C "EVE_MMU_CONFIG," hexmask.long.tbyte 0x1C 13.--31. 1. "RESERVED," newline bitfld.long 0x1C 12. "MMU1_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" newline rbitfld.long 0x1C 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "MMU0_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" newline rbitfld.long 0x1C 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 4. "MMU1_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" newline rbitfld.long 0x1C 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "MMU0_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" line.long 0x20 "EVE_MEMMAP," hexmask.long 0x20 5.--31. 1. "RESERVED," newline bitfld.long 0x20 4. "LCL_EDMA_ALIAS," "?,LCL_EDMA_ALIAS_1" newline rbitfld.long 0x20 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0. "VCOP_ALIAS," "?,VCOP_ALIAS_1" line.long 0x24 "EVE_MSW_CTL,Memory switch control register" hexmask.long.word 0x24 17.--31. 1. "RESERVED," newline bitfld.long 0x24 16. "WBUF,Working buffer onwership" "WBUF_0,WBUF_1" newline rbitfld.long 0x24 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 12. "IBUFHB,Image buffer high B ownership" "IBUFHB_0,IBUFHB_1" newline rbitfld.long 0x24 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8. "IBUFLB,Image buffer low B ownership" "IBUFLB_0,IBUFLB_1" newline rbitfld.long 0x24 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 4. "IBUFHA,Image buffer high A ownership" "IBUFHA_0,IBUFHA_1" newline rbitfld.long 0x24 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "IBUFLA,Image buffer low A ownership" "IBUFLA_0,IBUFLA_1" line.long 0x28 "EVE_MSW_ERR,Memory Switch Error register" hexmask.long.byte 0x28 25.--31. 1. "RESERVED," newline hexmask.long.word 0x28 16.--24. 1. "CONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x28 4.--15. 1. "RESERVED," newline bitfld.long 0x28 3. "SYSERR," "0,1" newline bitfld.long 0x28 2. "DMAERR," "0,1" newline bitfld.long 0x28 1. "VERR," "0,1" newline bitfld.long 0x28 0. "ARP32ERR," "0,1" line.long 0x2C "EVE_MSW_ERRADDR,Memory switch error address register" group.long 0x80040++0x03 line.long 0x00 "EVE_PC_INV,Invalidate all register" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "I,Invalidate all:Read" "Invalidate operation complete / or not in progress,Invalidate operation still in progress" group.long 0x80050++0x17 line.long 0x00 "EVE_PC_IBAR,Invalidate Base Address register" line.long 0x04 "EVE_PC_IBC,Invalidate byte count register" hexmask.long.word 0x04 16.--31. 1. "RESERVED," newline hexmask.long.word 0x04 0.--15. 1. "BC,Invalidate Byte Count register" line.long 0x08 "EVE_PC_ISAR,Invalidate single address register" line.long 0x0C "EVE_PC_ISAR_DONE,Invalidate single address done register" hexmask.long 0x0C 1.--31. 1. "RESERVED," newline bitfld.long 0x0C 0. "DONE,Reads return 0x1 when the invalidate operation is complete" "0,1" line.long 0x10 "EVE_PC_PBAR,Program cache preload base address register" line.long 0x14 "EVE_PC_PBC," hexmask.long.word 0x14 16.--31. 1. "RESERVED," newline hexmask.long.word 0x14 0.--15. 1. "BC,Preload Byte Count register" group.long 0x80080++0x0B line.long 0x00 "EVE_PMEM_ED_CTL,Program Memory Error Detection Control register" hexmask.long 0x00 2.--31. 1. "RESERVED," newline bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_PMEM_ED_STAT,Error detection status register" hexmask.long.byte 0x04 25.--31. 1. "RESERVED," newline hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_PMEM_EDADDR,Program memory error detection address" group.long 0x80090++0x2F line.long 0x00 "EVE_DMEM_ED_CTL,DMEM error detection control" hexmask.long 0x00 2.--31. 1. "RESERVED," newline bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_DMEM_ED_STAT,DMEM error detection status register" hexmask.long.byte 0x04 25.--31. 1. "RESERVED," newline hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_DMEM_EDADDR,DMEM error detection address register" line.long 0x0C "EVE_DMEM_EDADDR_BO,DMEM error detection address byte offset register" line.long 0x10 "EVE_WBUF_ED_CTL,WBUF error detection control" hexmask.long 0x10 2.--31. 1. "RESERVED," newline bitfld.long 0x10 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x10 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x14 "EVE_WBUF_ED_STAT,WBUF error detection status register" hexmask.long.byte 0x14 25.--31. 1. "RESERVED," newline hexmask.long.word 0x14 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x14 4.--15. 1. "RESERVED," newline bitfld.long 0x14 3. "SYSERR," "0,1" newline bitfld.long 0x14 2. "DMAERR," "0,1" newline bitfld.long 0x14 1. "VERR," "0,1" newline bitfld.long 0x14 0. "ARP32ERR," "0,1" line.long 0x18 "EVE_WBUF_EDADDR,WBUF error detection address register" line.long 0x1C "EVE_WBUF_EDADDR_BO,WBUF error detection address byte offset register" line.long 0x20 "EVE_IBUF_ED_CTL,IBUF error detection control" hexmask.long 0x20 2.--31. 1. "RESERVED," newline bitfld.long 0x20 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x20 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x24 "EVE_IBUF_ED_STAT,IBUF error detection status register" hexmask.long.byte 0x24 25.--31. 1. "RESERVED," newline hexmask.long.word 0x24 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x24 4.--15. 1. "RESERVED," newline bitfld.long 0x24 3. "SYSERR," "0,1" newline bitfld.long 0x24 2. "DMAERR," "0,1" newline bitfld.long 0x24 1. "VERR," "0,1" newline bitfld.long 0x24 0. "ARP32ERR," "0,1" line.long 0x28 "EVE_IBUF_EDADDR,IBUF error detection address register" line.long 0x2C "EVE_IBUF_EDADDR_BO,IBUF error detection address byte offset register" group.long 0x800F8++0x07 line.long 0x00 "EVE_ED_ARP32_DISC_EN,ARP32 disconnect enable register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline abitfld.long 0x00 0.--15. "ENABLE,Disconnect Enable for Event #n" "0x0000=Disconnect disabled,0x0001=Disconnect enabled" line.long 0x04 "EVE_ED_OCPI_DISC_EN,OCP interface disconnect enable register" hexmask.long.word 0x04 16.--31. 1. "RESERVED," newline abitfld.long 0x04 0.--15. "ENABLE,Disconnect Enable for Event #n" "0x0000=Disconnect disabled,0x0001=Disconnect enabled" group.long 0x80110++0x1F line.long 0x00 "EVE_MSW_ERR_IRQSTATUS_RAW,Per event memory switch error interrupt status register" hexmask.long 0x00 4.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "EVENT,settable raw status for event #n" "No event pending,Set event (for debug),?..." line.long 0x04 "EVE_MSW_ERR_IRQSTATUS,Memory switch error interrupt status register" hexmask.long 0x04 4.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--3. "EVENT,Clearable / enabled status for event #N" "No (enabled) event pending,Clear raw event,?..." line.long 0x08 "EVE_MSW_ERR_IRQENABLE_SET,Memory switch error interrupt enable register" hexmask.long 0x08 4.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--3. "ENABLE,Enable for event #n" "Interrupt disabled,Enable interrupt,?..." line.long 0x0C "EVE_MSW_ERR_IRQENABLE_CLR,Memory switch error interrupt clear register" hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "ENABLE,Enable for event #n" "Interrupt disabled,Disable interrupt (i.e. / clear ENABLEn bit),?..." line.long 0x10 "EVE_ED_LCL_IRQSTATUS_RAW,Per event error detection local interrupt status register" hexmask.long.word 0x10 16.--31. 1. "RESERVED," newline abitfld.long 0x10 0.--15. "EVENT,settable raw status for event #n" "0x0000=No event pending,0x0001=Set event (for debug)" line.long 0x14 "EVE_ED_LCL_IRQSTATUS,Error detection local interrupt status register" hexmask.long.word 0x14 16.--31. 1. "RESERVED," newline abitfld.long 0x14 0.--15. "EVENT,Clearable / enabled status for event #N" "0x0000=No (enabled) event pending,0x0001=Clear raw event" line.long 0x18 "EVE_ED_LCL_IRQENABLE_SET,Error detection local interrupt enable register" hexmask.long.word 0x18 16.--31. 1. "RESERVED," newline abitfld.long 0x18 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Enable interrupt" line.long 0x1C "EVE_ED_LCL_IRQENABLE_CLR,Error detection local interrupt clear register" hexmask.long.word 0x1C 16.--31. 1. "RESERVED," newline abitfld.long 0x1C 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Disable interrupt (i.e. / clear ENABLEn.." group.long 0x80210++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_4," group.long 0x80220++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_5," group.long 0x80230++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_6," group.long 0x80240++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_7," group.long 0x80214++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_4," group.long 0x80224++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_5," group.long 0x80234++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_6," group.long 0x80244++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_7," group.long 0x80218++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_4," group.long 0x80228++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_5," group.long 0x80238++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_6," group.long 0x80248++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_7," group.long 0x8021C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_4," group.long 0x8022C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_5," group.long 0x8023C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_6," group.long 0x8024C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_7," group.long 0x80200++0x0F line.long 0x00 "ARP32_NMI_IRQSTATUS_RAW," line.long 0x04 "ARP32_NMI_IRQSTATUS," line.long 0x08 "ARP32_NMI_IRQENABLE_SET," line.long 0x0C "ARP32_NMI_IRQENABLE_CLR," group.long 0x802FC++0x2B line.long 0x00 "ARP32_IRQWAKEEN,Wake enable register" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," newline abitfld.long 0x00 0.--23. "ENABLE,Wakeup Enable for event EVE_EVT_INT #n" "0x000000=Interrupt #n disabled for wakeup,0x000001=Interrupt #n enabled for wakeup" line.long 0x04 "MMR_LOCKi_0,MMR Lock/Unlock register" line.long 0x08 "MMR_LOCKi_1,MMR Lock/Unlock register" line.long 0x0C "MMR_LOCKi_2,MMR Lock/Unlock register" line.long 0x10 "MMR_LOCKi_3,MMR Lock/Unlock register" line.long 0x14 "MMR_LOCKi_4,MMR Lock/Unlock register" line.long 0x18 "MMR_LOCKi_5,MMR Lock/Unlock register" line.long 0x1C "MMR_LOCKi_6,MMR Lock/Unlock register" line.long 0x20 "MMR_LOCKi_7,MMR Lock/Unlock register" line.long 0x24 "MMR_LOCKi_8,MMR Lock/Unlock register" line.long 0x28 "MMR_LOCKi_9,MMR Lock/Unlock register" group.long 0x80400++0x07 line.long 0x00 "MISR_CTL," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "ENABLE,MISR Enable #N" "ARP32 PMEM path Bit,ARP32 DMEM path Bit,INTC WBUF path,?..." line.long 0x04 "MISR_CLEAR," hexmask.long 0x04 3.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--2. "CLEAR,MISR Clear #N" "Previous MISR clear command has completed,MISR Clear in progress (this state may never..,?..." group.long 0x80410++0x1F line.long 0x00 "MISR0_A," line.long 0x04 "MISR0_D," line.long 0x08 "MISR1_A," line.long 0x0C "MISR1_D," line.long 0x10 "MISR2_Dk_0," line.long 0x14 "MISR2_Dk_1," line.long 0x18 "MISR2_Dk_2," line.long 0x1C "MISR2_Dk_3," group.long 0x80500++0x03 line.long 0x00 "EVE_IRQ_EOI," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0,1,2,3,4,5,6,7" group.long 0x80510++0x13 line.long 0x00 "EVE_ED_OUT_IRQSTATUS_RAW," hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline abitfld.long 0x00 0.--15. "EVENT,Settable raw status for event #n" "0x0000=No event pending,0x0001=Set event (for debug)" line.long 0x04 "EVE_ED_OUT_IRQSTATUS," hexmask.long.word 0x04 16.--31. 1. "RESERVED," newline abitfld.long 0x04 0.--15. "EVENT,Clearable / enabled status for event #N" "0x0000=No (enabled) event pending,0x0001=Clear raw event" line.long 0x08 "EVE_ED_OUT_IRQENABLE_SET," hexmask.long.word 0x08 16.--31. 1. "RESERVED," newline abitfld.long 0x08 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Enable interrupt" line.long 0x0C "EVE_ED_OUT_IRQENABLE_CLR," hexmask.long.word 0x0C 16.--31. 1. "RESERVED," newline abitfld.long 0x0C 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Disable interrupt (i.e. / clear ENABLEn.." line.long 0x10 "EVE_INTk_OUT_IRQSTATUS_RAW_0," group.long 0x80530++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_1," group.long 0x80540++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_2," group.long 0x80550++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_3," group.long 0x80524++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_0," group.long 0x80534++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_1," group.long 0x80544++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_2," group.long 0x80554++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_3," group.long 0x80528++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_0," group.long 0x80538++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_1," group.long 0x80548++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_2," group.long 0x80558++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_3," group.long 0x8052C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_0," group.long 0x8053C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_1," group.long 0x8054C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_2," group.long 0x8055C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_3," rgroup.long 0x80600++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_8," rgroup.long 0x80610++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_9," rgroup.long 0x80620++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_10," rgroup.long 0x80630++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_11," rgroup.long 0x80640++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_12," rgroup.long 0x80650++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_13," group.long 0x80604++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_8," group.long 0x80614++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_9," group.long 0x80624++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_10," group.long 0x80634++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_11," group.long 0x80644++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_12," group.long 0x80654++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_13," group.long 0x80608++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_8," group.long 0x80618++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_9," group.long 0x80628++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_10," group.long 0x80638++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_11," group.long 0x80648++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_12," group.long 0x80658++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_13," group.long 0x8060C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_8," group.long 0x8061C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_9," group.long 0x8062C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_10," group.long 0x8063C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_11," group.long 0x8064C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_12," group.long 0x8065C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_13," rgroup.long 0x80680++0x1F line.long 0x00 "ARP32_INT14_IRQSTATUS_RAW," line.long 0x04 "ARP32_INT14_IRQSTATUS," line.long 0x08 "ARP32_INT14_IRQENABLE_SET," line.long 0x0C "ARP32_INT14_IRQENABLE_CLR," line.long 0x10 "ARP32_INT15_IRQSTATUS_RAW," line.long 0x14 "ARP32_INT15_IRQSTATUS," line.long 0x18 "ARP32_INT15_IRQENABLE_SET," line.long 0x1C "ARP32_INT15_IRQENABLE_CLR," group.long 0x80700++0x03 line.long 0x00 "EVE_GPOUTm_0," group.long 0x80710++0x03 line.long 0x00 "EVE_GPOUTm_1," group.long 0x80704++0x03 line.long 0x00 "EVE_GPOUTm_SET_0," group.long 0x80714++0x03 line.long 0x00 "EVE_GPOUTm_SET_1," group.long 0x80708++0x03 line.long 0x00 "EVE_GPOUTm_CLR_0," group.long 0x80718++0x03 line.long 0x00 "EVE_GPOUTm_CLR_1," group.long 0x8070C++0x03 line.long 0x00 "EVE_GPOUTm_PULSE_0," group.long 0x8071C++0x03 line.long 0x00 "EVE_GPOUTm_PULSE_1," group.long 0x80780++0x17 line.long 0x00 "EVE_CME_DONE_GPOUT," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," newline abitfld.long 0x00 0.--7. "EVENT,Internal CME Done Output #n" "0x00=Drive Internal CME Done #n is low/0,0x01=Internal CME Done is high/1" line.long 0x04 "EVE_CME_DONE_GPOUT_SET," hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," newline abitfld.long 0x04 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done is high/1" line.long 0x08 "EVE_CME_DONE_GPOUT_CLR," hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED," newline abitfld.long 0x08 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done #n is high/1" line.long 0x0C "EVE_CME_DONE_GPOUT_PULSE," hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED," newline abitfld.long 0x0C 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done #n is high/1" line.long 0x10 "EVE_CME_DONE_SEL," bitfld.long 0x10 28.--31. "SEL7,CME Done Output select for Bit #7 (n=7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 24.--27. "SEL6,CME Done Output select for Bit #6 (n=6)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 20.--23. "SEL5,CME Done Output select for Bit #5 (n=5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 16.--19. "SEL4,CME Done Output select for Bit #4 (n=4)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 12.--15. "SEL3,CME Done Output select for Bit #3 (n=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 8.--11. "SEL2,CME Done Output select for Bit #2 (n=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 4.--7. "SEL1,CME Done Output select for Bit #1 (n=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--3. "SEL0,CME Done Output select for Bit #0 (n=0)" "Driven by EDMA cc_int0,Driven by EDMA cc_int1,Driven by EDMA cc_int2,Driven by EDMA cc_int3,Driven by EDMA cc_int4,Driven by EDMA cc_int5,Driven by EDMA cc_int6,Driven by EDMA cc_int7,Driven by EVE_CME_DONE_GPOUTn,driven by eve_cme_done_gpout[0+n] (from EVE),driven by eve_cme_done_gpout[8+n] (from EVE2),driven by eve_cme_done_gpout[16+n] (from EVE3),driven by eve_cme_done_gpout[24+n] (from EVE4),driven by eve_cme_done_gpout[32+n] (from EVE5),driven by eve_cme_done_gpout[40+n] (from EVE6),driven by eve_cme_done_gpout[48+n] (from EVE7)" line.long 0x14 "EVE_CME_DONE_EN," hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," newline abitfld.long 0x14 0.--7. "EN,EVE CME Done EN #n" "0x00=EVE CME Done #n is disabled,0x01=EVE CME Done #n is enabled" rgroup.long 0x80FE0++0x0B line.long 0x00 "EVE_PM_STAT0," bitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 28.--30. "OCPM1_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 26.--27. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 24.--25. "OCPM1_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 23. "RESERVED," "0,1" newline bitfld.long 0x00 20.--22. "OCPM0_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 16.--17. "OCPM0_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 12.--14. "OCPS_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 8.--9. "OCPS_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 5. "MWAIT,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 4. "MSTANDBY,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 3. "SWAKEUP,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 1.--2. "SIDLEACK,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 0. "SIDLEREQ,Readable state of OCP Power management handshake" "0,1" line.long 0x04 "EVE_PM_STAT1," hexmask.long.byte 0x04 24.--31. 1. "RESERVED," newline rbitfld.long 0x04 22.--23. "STBY_MDISCACK_OCPM1,Readable state of internal power management handshake" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "STBY_MDISCACK_OCPM0,Readable state of internal power management handshake" "0,1,2,3" newline rbitfld.long 0x04 19. "STBY_MDISCREQ_OCPM1,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 18. "STBY_MDISCREQ_OCPM0,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 17. "IDLE_SDISCONNECT_ACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 16. "IDLE_SDISCONNECT_REQ,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 15. "EVE_IDLE_INTR_DISABLE,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 14. "TPTC1_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 13. "TPTC0_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 12. "EVE_PCACHE_OCP_BUSY,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 11. "EVE_CONTROL_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 10. "SMSET_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 9. "L2_EVE_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 8. "MMU1_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 7. "MMU1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 6. "MMU0_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 5. "MMU0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 4. "SCTM_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 3. "TPCC_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 2. "TPTC1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 1. "TPTC0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline bitfld.long 0x04 0. "SUBMODULE_IDLE_REQ," "0,1" line.long 0x08 "EVE_DBGOUT," hexmask.long.tbyte 0x08 8.--31. 1. "VALUE,Read returns state of eve_dbgout bus" newline rbitfld.long 0x08 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. "GROUP,Debug Group Output control : mux select" "disabled / all debug outputs driven to 0x0,select output group1,select output group2,?..." group.long 0x80FFC++0x03 line.long 0x00 "EVE_TEST," repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x80FF4)++0x03 line.long 0x00 "EVE_RSVD$1," repeat.end repeat 2. (list 0. 1. )(list 0x00 0x04 ) rgroup.long ($2+0x80740)++0x03 line.long 0x00 "EVE_GPIN$1," repeat.end width 0x0B tree.end tree "EVE1_CM_CORE_AON" base ad:0x4A005640 group.long 0x00++0x07 line.long 0x00 "CM_EVE1_CLKSTCTRL,This register enables the EVE domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_EVE1_GFCLK,This field indicates the state of the EVE1_GFCLK clock in the domain" "CLKACTIVITY_EVE1_GFCLK_0,CLKACTIVITY_EVE1_GFCLK_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_EVE1_STATICDEP,This register controls the static domain depedencies from EVE1 domain towards 'target' domains" hexmask.long.word 0x04 23.--31. 1. "RESERVED," bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain" "EVE2_STATDEP_0,EVE2_STATDEP_1" hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 3. "RESERVED," "0,1" bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" group.long 0x20++0x03 line.long 0x00 "CM_EVE1_EVE1_CLKCTRL,This register manages the EVE clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "EVE1_PRM" base ad:0x4AE07B40 group.long 0x00++0x07 line.long 0x00 "PM_EVE1_PWRSTCTRL,This register controls the EVE power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "EVE1_BANK_ONSTATE,EVE1 state when domain is ON" "?,?,?,EVE1_BANK_ONSTATE_3" newline hexmask.long.word 0x00 5.--15. 1. "RESERVED," bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_EVE1_PWRSTST,This register provides a status on the EVE domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "EVE1_BANK_STATEST,EVE0 memory state status" "EVE1_BANK_STATEST_0,EVE1_BANK_STATEST_1,EVE1_BANK_STATEST_2,EVE1_BANK_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_EVE1_RSTCTRL,This register controls the release of the EVE sub-system resets" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "RST_EVE1,EVE reset control" "RST_EVE1_0,RST_EVE1_1" newline bitfld.long 0x00 0. "RST_EVE1_LRST,EVE Local reset control" "RST_EVE1_LRST_0,RST_EVE1_LRST_1" line.long 0x04 "RM_EVE1_RSTST,This register logs the different reset sources of the EVE domain" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "RST_EVE1_EMU_REQ,EVE1 processor has been reset due to EVE emulation reset request driven from EVE1-SS" "RST_EVE1_EMU_REQ_0,RST_EVE1_EMU_REQ_1" newline bitfld.long 0x04 2. "RST_EVE1_EMU,EVE1 domain has been reset due to emulation reset source e.g" "RST_EVE1_EMU_0,RST_EVE1_EMU_1" bitfld.long 0x04 1. "RST_EVE1,EVE0 SW reset status" "RST_EVE1_0,RST_EVE1_1" newline bitfld.long 0x04 0. "RST_EVE1_LRST,EVE0 Local SW reset" "RST_EVE1_LRST_0,RST_EVE1_LRST_1" group.long 0x20++0x07 line.long 0x00 "PM_EVE1_EVE1_WKDEP,This register controls wakeup dependency based on EVE1 service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_EVE1_EVE4,Wakeup dependency from EVE1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_EVE4_0,WKUPDEP_EVE1_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_EVE1_EVE3,Wakeup dependency from EVE1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_EVE3_0,WKUPDEP_EVE1_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_EVE1_EVE2,Wakeup dependency from EVE1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_EVE2_0,WKUPDEP_EVE1_EVE2_1" newline rbitfld.long 0x00 6. "RESERVED," "0,1" bitfld.long 0x00 5. "WKUPDEP_EVE1_DSP2,Wakeup dependency from EVE1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_DSP2_0,WKUPDEP_EVE1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_EVE1_IPU1,Wakeup dependency from EVE1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_IPU1_0,WKUPDEP_EVE1_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_EVE1_SDMA,Wakeup dependency from EVE1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_SDMA_0,WKUPDEP_EVE1_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_EVE1_DSP1,Wakeup dependency from EVE1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_DSP1_0,WKUPDEP_EVE1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_EVE1_IPU2,Wakeup dependency from EVE1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_IPU2_0,WKUPDEP_EVE1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_EVE1_MPU,Wakeup dependency from EVE1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_MPU_0,WKUPDEP_EVE1_MPU_1" line.long 0x04 "RM_EVE1_EVE1_CONTEXT,This register contains dedicated EVE context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_EVE_BANK,Specify if memory-based context in EVE1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EVE_BANK_0,LOSTMEM_EVE_BANK_1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "EVE2_CM_CORE_AON" base ad:0x4A005680 group.long 0x00++0x07 line.long 0x00 "CM_EVE2_CLKSTCTRL,This register enables the EVE domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_EVE2_GFCLK,This field indicates the state of the EVE2_GFCLK clock in the domain" "CLKACTIVITY_EVE2_GFCLK_0,CLKACTIVITY_EVE2_GFCLK_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_EVE2_STATICDEP,This register controls the static domain depedencies from EVE2 domain towards 'target' domains" hexmask.long.word 0x04 23.--31. 1. "RESERVED," bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" newline rbitfld.long 0x04 20. "RESERVED," "0,1" bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain" "EVE1_STATDEP_0,EVE1_STATDEP_1" hexmask.long.word 0x04 6.--18. 1. "RESERVED," newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" group.long 0x20++0x03 line.long 0x00 "CM_EVE2_EVE2_CLKCTRL,This register manages the EVE clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "EVE2_PRM" base ad:0x4AE07B80 group.long 0x00++0x07 line.long 0x00 "PM_EVE2_PWRSTCTRL,This register controls the EVE power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "EVE2_BANK_ONSTATE,EVE2 state when domain is ON" "?,?,?,EVE2_BANK_ONSTATE_3" newline hexmask.long.word 0x00 5.--15. 1. "RESERVED," bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_EVE2_PWRSTST,This register provides a status on the EVE domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "EVE2_BANK_STATEST,EVE2 memory state status" "EVE2_BANK_STATEST_0,EVE2_BANK_STATEST_1,EVE2_BANK_STATEST_2,EVE2_BANK_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_EVE2_RSTCTRL,This register controls the release of the EVE sub-system resets" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "RST_EVE2,EVE SW reset control" "RST_EVE2_0,RST_EVE2_1" newline bitfld.long 0x00 0. "RST_EVE2_LRST,EVE Local reset control" "RST_EVE2_LRST_0,RST_EVE2_LRST_1" line.long 0x04 "RM_EVE2_RSTST,This register logs the different reset sources of the EVE domain" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "RST_EVE2_EMU_REQ,EVE2 processor has been reset due to EVE emulation reset request driven from EVE2-SS" "RST_EVE2_EMU_REQ_0,RST_EVE2_EMU_REQ_1" newline bitfld.long 0x04 2. "RST_EVE2_EMU,EVE2 domain has been reset due to emulation reset source e.g" "RST_EVE2_EMU_0,RST_EVE2_EMU_1" bitfld.long 0x04 1. "RST_EVE2,EVE SW reset status" "RST_EVE2_0,RST_EVE2_1" newline bitfld.long 0x04 0. "RST_EVE2_LRST,EVE Local SW reset" "RST_EVE2_LRST_0,RST_EVE2_LRST_1" group.long 0x20++0x07 line.long 0x00 "PM_EVE2_EVE2_WKDEP,This register controls wakeup dependency based on EVE2 service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_EVE2_EVE4,Wakeup dependency from EVE2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_EVE4_0,WKUPDEP_EVE2_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_EVE2_EVE3,Wakeup dependency from EVE2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_EVE3_0,WKUPDEP_EVE2_EVE3_1" rbitfld.long 0x00 7. "RESERVED," "0,1" newline bitfld.long 0x00 6. "WKUPDEP_EVE2_EVE1,Wakeup dependency from EVE2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_EVE1_0,WKUPDEP_EVE2_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_EVE2_DSP2,Wakeup dependency from EVE2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_DSP2_0,WKUPDEP_EVE2_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_EVE2_IPU1,Wakeup dependency from EVE2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_IPU1_0,WKUPDEP_EVE2_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_EVE2_SDMA,Wakeup dependency from EVE2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_SDMA_0,WKUPDEP_EVE2_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_EVE2_DSP1,Wakeup dependency from EVE2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_DSP1_0,WKUPDEP_EVE2_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_EVE2_IPU2,Wakeup dependency from EVE2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_IPU2_0,WKUPDEP_EVE2_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_EVE2_MPU,Wakeup dependency from EVE2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_MPU_0,WKUPDEP_EVE2_MPU_1" line.long 0x04 "RM_EVE2_EVE2_CONTEXT,This register contains dedicated EVE context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_EVE_BANK,Specify if memory-based context in EVE2 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EVE_BANK_0,LOSTMEM_EVE_BANK_1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "EVE3_CM_CORE_AON" base ad:0x4A0056C0 group.long 0x00++0x07 line.long 0x00 "CM_EVE3_CLKSTCTRL,This register enables the EVE domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_EVE3_GFCLK,This field indicates the state of the EVE3_GFCLK clock in the domain" "CLKACTIVITY_EVE3_GFCLK_0,CLKACTIVITY_EVE3_GFCLK_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_EVE3_STATICDEP,This register controls the static domain depedencies from EVE3 domain towards 'target' domains" hexmask.long.word 0x04 23.--31. 1. "RESERVED," bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" rbitfld.long 0x04 21. "RESERVED," "0,1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain" "EVE2_STATDEP_0,EVE2_STATDEP_1" bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain" "EVE1_STATDEP_0,EVE1_STATDEP_1" hexmask.long.word 0x04 6.--18. 1. "RESERVED," newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" group.long 0x20++0x03 line.long 0x00 "CM_EVE3_EVE3_CLKCTRL,This register manages the EVE clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "EVE3_PRM" base ad:0x4AE07BC0 group.long 0x00++0x07 line.long 0x00 "PM_EVE3_PWRSTCTRL,This register controls the EVE power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "EVE3_BANK_ONSTATE,EVE3 state when domain is ON" "?,?,?,EVE3_BANK_ONSTATE_3" newline hexmask.long.word 0x00 5.--15. 1. "RESERVED," bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_EVE3_PWRSTST,This register provides a status on the EVE domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "EVE3_BANK_STATEST,EVE3 memory state status" "EVE3_BANK_STATEST_0,EVE3_BANK_STATEST_1,EVE3_BANK_STATEST_2,EVE3_BANK_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_EVE3_RSTCTRL,This register controls the release of the EVE sub-system resets" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "RST_EVE3,EVE SW reset control" "RST_EVE3_0,RST_EVE3_1" newline bitfld.long 0x00 0. "RST_EVE3_LRST,EVE3 Local reset control" "RST_EVE3_LRST_0,RST_EVE3_LRST_1" line.long 0x04 "RM_EVE3_RSTST,This register logs the different reset sources of the EVE domain" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "RST_EVE3_EMU_REQ,EVE3 processor has been reset due to EVE emulation reset request driven from EVE3-SS" "RST_EVE3_EMU_REQ_0,RST_EVE3_EMU_REQ_1" newline bitfld.long 0x04 2. "RST_EVE3_EMU,EVE3 domain has been reset due to emulation reset source e.g" "RST_EVE3_EMU_0,RST_EVE3_EMU_1" bitfld.long 0x04 1. "RST_EVE3,EVE3 SW reset status" "RST_EVE3_0,RST_EVE3_1" newline bitfld.long 0x04 0. "RST_EVE3_LRST,EVE3 Local SW reset" "RST_EVE3_LRST_0,RST_EVE3_LRST_1" group.long 0x20++0x07 line.long 0x00 "PM_EVE3_EVE3_WKDEP,This register controls wakeup dependency based on EVE3 service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_EVE3_EVE4,Wakeup dependency from EVE3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_EVE4_0,WKUPDEP_EVE3_EVE4_1" newline rbitfld.long 0x00 8. "RESERVED," "0,1" bitfld.long 0x00 7. "WKUPDEP_EVE3_EVE2,Wakeup dependency from EVE3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_EVE2_0,WKUPDEP_EVE3_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_EVE3_EVE1,Wakeup dependency from EVE3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_EVE1_0,WKUPDEP_EVE3_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_EVE3_DSP2,Wakeup dependency from EVE3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_DSP2_0,WKUPDEP_EVE3_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_EVE3_IPU1,Wakeup dependency from EVE3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_IPU1_0,WKUPDEP_EVE3_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_EVE3_SDMA,Wakeup dependency from EVE3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_SDMA_0,WKUPDEP_EVE3_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_EVE3_DSP1,Wakeup dependency from EVE3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_DSP1_0,WKUPDEP_EVE3_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_EVE3_IPU2,Wakeup dependency from EVE3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_IPU2_0,WKUPDEP_EVE3_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_EVE3_MPU,Wakeup dependency from EVE3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_MPU_0,WKUPDEP_EVE3_MPU_1" line.long 0x04 "RM_EVE3_EVE3_CONTEXT,This register contains dedicated EVE context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_EVE_BANK,Specify if memory-based context in EVE3 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EVE_BANK_0,LOSTMEM_EVE_BANK_1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "EVE4_CM_CORE_AON" base ad:0x4A005700 group.long 0x00++0x07 line.long 0x00 "CM_EVE4_CLKSTCTRL,This register enables the EVE domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_EVE4_GFCLK,This field indicates the state of the EVE3_GFCLK clock in the domain" "CLKACTIVITY_EVE4_GFCLK_0,CLKACTIVITY_EVE4_GFCLK_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_EVE4_STATICDEP,This register controls the static domain depedencies from EVE4 domain towards 'target' domains" hexmask.long.word 0x04 22.--31. 1. "RESERVED," bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain" "EVE1_STATDEP_0,EVE1_STATDEP_1" hexmask.long.word 0x04 6.--18. 1. "RESERVED," rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 3. "RESERVED," "0,1" bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" group.long 0x20++0x03 line.long 0x00 "CM_EVE4_EVE4_CLKCTRL,This register manages the EVE clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "EVE4_PRM" base ad:0x4AE07C00 group.long 0x00++0x07 line.long 0x00 "PM_EVE4_PWRSTCTRL,This register controls the EVE power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "EVE4_BANK_ONSTATE,EVE4 state when domain is ON" "?,?,?,EVE4_BANK_ONSTATE_3" newline hexmask.long.word 0x00 5.--15. 1. "RESERVED," bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_EVE4_PWRSTST,This register provides a status on the EVE domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "EVE4_BANK_STATEST,EVE4 memory state status" "EVE4_BANK_STATEST_0,EVE4_BANK_STATEST_1,EVE4_BANK_STATEST_2,EVE4_BANK_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_EVE4_RSTCTRL,This register controls the release of the EVE sub-system resets" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "RST_EVE4,EVE SW reset control" "RST_EVE4_0,RST_EVE4_1" newline bitfld.long 0x00 0. "RST_EVE4_LRST,EVE4 Local reset control" "RST_EVE4_LRST_0,RST_EVE4_LRST_1" line.long 0x04 "RM_EVE4_RSTST,This register logs the different reset sources of the EVE domain" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "RST_EVE4_EMU_REQ,EVE4 processor has been reset due to EVE emulation reset request driven from EVE4-SS" "RST_EVE4_EMU_REQ_0,RST_EVE4_EMU_REQ_1" newline bitfld.long 0x04 2. "RST_EVE4_EMU,EVE4 domain has been reset due to emulation reset source e.g" "RST_EVE4_EMU_0,RST_EVE4_EMU_1" bitfld.long 0x04 1. "RST_EVE4,EVE4 SW reset status" "RST_EVE4_0,RST_EVE4_1" newline bitfld.long 0x04 0. "RST_EVE4_LRST,EVE4 Local SW reset" "RST_EVE4_LRST_0,RST_EVE4_LRST_1" group.long 0x20++0x07 line.long 0x00 "PM_EVE4_EVE4_WKDEP,This register controls wakeup dependency based on EVE4 service requests" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "WKUPDEP_EVE4_EVE3,Wakeup dependency from EVE4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_EVE3_0,WKUPDEP_EVE4_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_EVE4_EVE2,Wakeup dependency from EVE4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_EVE2_0,WKUPDEP_EVE4_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_EVE4_EVE1,Wakeup dependency from EVE4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_EVE1_0,WKUPDEP_EVE4_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_EVE4_DSP2,Wakeup dependency from EVE4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_DSP2_0,WKUPDEP_EVE4_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_EVE4_IPU1,Wakeup dependency from EVE4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_IPU1_0,WKUPDEP_EVE4_IPU1_1" newline bitfld.long 0x00 3. "WKUPDEP_EVE4_SDMA,Wakeup dependency from EVE4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_SDMA_0,WKUPDEP_EVE4_SDMA_1" bitfld.long 0x00 2. "WKUPDEP_EVE4_DSP1,Wakeup dependency from EVE4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_DSP1_0,WKUPDEP_EVE4_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_EVE4_IPU2,Wakeup dependency from EVE4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_IPU2_0,WKUPDEP_EVE4_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_EVE4_MPU,Wakeup dependency from EVE4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_MPU_0,WKUPDEP_EVE4_MPU_1" line.long 0x04 "RM_EVE4_EVE4_CONTEXT,This register contains dedicated EVE context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_EVE_BANK,Specify if memory-based context in EVE4 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EVE_BANK_0,LOSTMEM_EVE_BANK_1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "EVE_DSP" base ad:0x2000000 rgroup.long 0x80000++0x2F line.long 0x00 "EVE_REVISION," line.long 0x04 "EVE_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," newline bitfld.long 0x04 0.--3. "EVENUM,EVE instance number set by eve_num inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EVE_SYSCONFIG," hexmask.long 0x08 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x08 4.--5. "STANDBYMODE," "?,No-Standby,Smart-Standby,Smart-Standby-Wkup" newline bitfld.long 0x08 2.--3. "IDLEMODE," "?,No-idle,Smart-idle,SmartIdleWkup" newline rbitfld.long 0x08 1. "FREEEMU,Resered" "0,1" newline rbitfld.long 0x08 0. "SOFTRESET,Reserved" "0,1" line.long 0x0C "EVE_STAT," hexmask.long.word 0x0C 22.--31. 1. "RESERVED," newline bitfld.long 0x0C 20.--21. "OCPI_DISC_STAT,OCP Initiator(s) Disconnect status2" "OCPI_DISC_STAT_0,OCPI_DISC_STAT_1,OCPI_DISC_STAT_2,?" newline bitfld.long 0x0C 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 16.--17. "ARP32_DISC_STATUS,ARP32 Program/Data Bus Disconnect Status 2" "ARP32_DISC_STATUS_0,ARP32_DISC_STATUS_1,ARP32_DISC_STATUS_2,?" newline hexmask.long.byte 0x0C 9.--15. 1. "RESERVED," newline bitfld.long 0x0C 8. "INT_OUT_STAT,Interrupt Output status" "INT_OUT_STAT_0,INT_OUT_STAT_1" newline bitfld.long 0x0C 7. "ARP32_INTC_STAT,Interrupt Controller Status" "ARP32_INTC_STAT_0,ARP32_INTC_STAT_1" newline bitfld.long 0x0C 6. "RESERVED," "0,1" newline bitfld.long 0x0C 5. "TC1_STAT,Transfer Controller1 Status" "TC1_STAT_0,TC1_STAT_1" newline bitfld.long 0x0C 4. "TC0_STAT,Transfer Controller0 Status" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "PC_STAT,Program Cache Status" "PC_STAT_0,PC_STAT_1" newline bitfld.long 0x0C 1. "VCOP_STAT,VCOP Status" "VCOP_STAT_0,VCOP_STAT_1" newline bitfld.long 0x0C 0. "ARP32_STAT,Program Cache Status" "ARP32_STAT_0,ARP32_STAT_1" line.long 0x10 "EVE_DISC_CONFIG,Color 0 noise threshold" hexmask.long 0x10 5.--31. 1. "RESERVED," newline bitfld.long 0x10 4. "OCPI_DISC,OCP Initiator Disconnect request" "OCPI_DISC_0_r,OCPI_DISC_1_w" newline rbitfld.long 0x10 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0. "ARP32_DISC,ARP32 Initiator Disconnect request" "?,ARP32_DISC_1_r" line.long 0x14 "EVE_BUS_CONFIG,Color 0 noise threshold" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED," newline bitfld.long 0x14 12.--13. "TC1_DBS,TC1 default burst size" "16 byte,32 byte,64 byte,128 byte.." newline rbitfld.long 0x14 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 8.--9. "TC0_DBS,TC0 default burst size" "16 byte,32 byte,64 byte,128 byte.." newline rbitfld.long 0x14 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 4. "DBP_ENABLE,Program Cache Demand Based Prefetch enable" "DBP_ENABLE_0,DBP_ENABLE_1" newline bitfld.long 0x14 0.--3. "MAX_IN_FLIGHT,Defines maximum number of OCP requests in flight" "Reserved,1 request in flight allowed,2 requests in flight allowed,?..." line.long 0x18 "EVE_VCOP_HALT_CONFIG," hexmask.long 0x18 3.--31. 1. "RESERVED," newline bitfld.long 0x18 2. "FORCE_ABORT,VCOP Force Abort Write: Read always returns 0sWrite 0 has no effect" "?,FORCE_ABORT_1_w" newline bitfld.long 0x18 1. "MSW_EN,VCOP Memory Seitch Error Halt Enable" "MSW_EN_0,MSW_EN_1" newline bitfld.long 0x18 0. "ED_EN,VCOP Parity Error Detect Halt Enable" "ED_EN_0,ED_EN_1" line.long 0x1C "EVE_MMU_CONFIG," hexmask.long.tbyte 0x1C 13.--31. 1. "RESERVED," newline bitfld.long 0x1C 12. "MMU1_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" newline rbitfld.long 0x1C 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "MMU0_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" newline rbitfld.long 0x1C 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 4. "MMU1_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" newline rbitfld.long 0x1C 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "MMU0_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" line.long 0x20 "EVE_MEMMAP," hexmask.long 0x20 5.--31. 1. "RESERVED," newline bitfld.long 0x20 4. "LCL_EDMA_ALIAS," "?,LCL_EDMA_ALIAS_1" newline rbitfld.long 0x20 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0. "VCOP_ALIAS," "?,VCOP_ALIAS_1" line.long 0x24 "EVE_MSW_CTL,Memory switch control register" hexmask.long.word 0x24 17.--31. 1. "RESERVED," newline bitfld.long 0x24 16. "WBUF,Working buffer onwership" "WBUF_0,WBUF_1" newline rbitfld.long 0x24 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 12. "IBUFHB,Image buffer high B ownership" "IBUFHB_0,IBUFHB_1" newline rbitfld.long 0x24 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8. "IBUFLB,Image buffer low B ownership" "IBUFLB_0,IBUFLB_1" newline rbitfld.long 0x24 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 4. "IBUFHA,Image buffer high A ownership" "IBUFHA_0,IBUFHA_1" newline rbitfld.long 0x24 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "IBUFLA,Image buffer low A ownership" "IBUFLA_0,IBUFLA_1" line.long 0x28 "EVE_MSW_ERR,Memory Switch Error register" hexmask.long.byte 0x28 25.--31. 1. "RESERVED," newline hexmask.long.word 0x28 16.--24. 1. "CONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x28 4.--15. 1. "RESERVED," newline bitfld.long 0x28 3. "SYSERR," "0,1" newline bitfld.long 0x28 2. "DMAERR," "0,1" newline bitfld.long 0x28 1. "VERR," "0,1" newline bitfld.long 0x28 0. "ARP32ERR," "0,1" line.long 0x2C "EVE_MSW_ERRADDR,Memory switch error address register" group.long 0x80040++0x03 line.long 0x00 "EVE_PC_INV,Invalidate all register" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "I,Invalidate all:Read" "Invalidate operation complete / or not in progress,Invalidate operation still in progress" group.long 0x80050++0x17 line.long 0x00 "EVE_PC_IBAR,Invalidate Base Address register" line.long 0x04 "EVE_PC_IBC,Invalidate byte count register" hexmask.long.word 0x04 16.--31. 1. "RESERVED," newline hexmask.long.word 0x04 0.--15. 1. "BC,Invalidate Byte Count register" line.long 0x08 "EVE_PC_ISAR,Invalidate single address register" line.long 0x0C "EVE_PC_ISAR_DONE,Invalidate single address done register" hexmask.long 0x0C 1.--31. 1. "RESERVED," newline bitfld.long 0x0C 0. "DONE,Reads return 0x1 when the invalidate operation is complete" "0,1" line.long 0x10 "EVE_PC_PBAR,Program cache preload base address register" line.long 0x14 "EVE_PC_PBC," hexmask.long.word 0x14 16.--31. 1. "RESERVED," newline hexmask.long.word 0x14 0.--15. 1. "BC,Preload Byte Count register" group.long 0x80080++0x0B line.long 0x00 "EVE_PMEM_ED_CTL,Program Memory Error Detection Control register" hexmask.long 0x00 2.--31. 1. "RESERVED," newline bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_PMEM_ED_STAT,Error detection status register" hexmask.long.byte 0x04 25.--31. 1. "RESERVED," newline hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_PMEM_EDADDR,Program memory error detection address" group.long 0x80090++0x2F line.long 0x00 "EVE_DMEM_ED_CTL,DMEM error detection control" hexmask.long 0x00 2.--31. 1. "RESERVED," newline bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_DMEM_ED_STAT,DMEM error detection status register" hexmask.long.byte 0x04 25.--31. 1. "RESERVED," newline hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_DMEM_EDADDR,DMEM error detection address register" line.long 0x0C "EVE_DMEM_EDADDR_BO,DMEM error detection address byte offset register" line.long 0x10 "EVE_WBUF_ED_CTL,WBUF error detection control" hexmask.long 0x10 2.--31. 1. "RESERVED," newline bitfld.long 0x10 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x10 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x14 "EVE_WBUF_ED_STAT,WBUF error detection status register" hexmask.long.byte 0x14 25.--31. 1. "RESERVED," newline hexmask.long.word 0x14 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x14 4.--15. 1. "RESERVED," newline bitfld.long 0x14 3. "SYSERR," "0,1" newline bitfld.long 0x14 2. "DMAERR," "0,1" newline bitfld.long 0x14 1. "VERR," "0,1" newline bitfld.long 0x14 0. "ARP32ERR," "0,1" line.long 0x18 "EVE_WBUF_EDADDR,WBUF error detection address register" line.long 0x1C "EVE_WBUF_EDADDR_BO,WBUF error detection address byte offset register" line.long 0x20 "EVE_IBUF_ED_CTL,IBUF error detection control" hexmask.long 0x20 2.--31. 1. "RESERVED," newline bitfld.long 0x20 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x20 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x24 "EVE_IBUF_ED_STAT,IBUF error detection status register" hexmask.long.byte 0x24 25.--31. 1. "RESERVED," newline hexmask.long.word 0x24 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x24 4.--15. 1. "RESERVED," newline bitfld.long 0x24 3. "SYSERR," "0,1" newline bitfld.long 0x24 2. "DMAERR," "0,1" newline bitfld.long 0x24 1. "VERR," "0,1" newline bitfld.long 0x24 0. "ARP32ERR," "0,1" line.long 0x28 "EVE_IBUF_EDADDR,IBUF error detection address register" line.long 0x2C "EVE_IBUF_EDADDR_BO,IBUF error detection address byte offset register" group.long 0x800F8++0x07 line.long 0x00 "EVE_ED_ARP32_DISC_EN,ARP32 disconnect enable register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline abitfld.long 0x00 0.--15. "ENABLE,Disconnect Enable for Event #n" "0x0000=Disconnect disabled,0x0001=Disconnect enabled" line.long 0x04 "EVE_ED_OCPI_DISC_EN,OCP interface disconnect enable register" hexmask.long.word 0x04 16.--31. 1. "RESERVED," newline abitfld.long 0x04 0.--15. "ENABLE,Disconnect Enable for Event #n" "0x0000=Disconnect disabled,0x0001=Disconnect enabled" group.long 0x80110++0x1F line.long 0x00 "EVE_MSW_ERR_IRQSTATUS_RAW,Per event memory switch error interrupt status register" hexmask.long 0x00 4.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "EVENT,settable raw status for event #n" "No event pending,Set event (for debug),?..." line.long 0x04 "EVE_MSW_ERR_IRQSTATUS,Memory switch error interrupt status register" hexmask.long 0x04 4.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--3. "EVENT,Clearable / enabled status for event #N" "No (enabled) event pending,Clear raw event,?..." line.long 0x08 "EVE_MSW_ERR_IRQENABLE_SET,Memory switch error interrupt enable register" hexmask.long 0x08 4.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--3. "ENABLE,Enable for event #n" "Interrupt disabled,Enable interrupt,?..." line.long 0x0C "EVE_MSW_ERR_IRQENABLE_CLR,Memory switch error interrupt clear register" hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "ENABLE,Enable for event #n" "Interrupt disabled,Disable interrupt (i.e. / clear ENABLEn bit),?..." line.long 0x10 "EVE_ED_LCL_IRQSTATUS_RAW,Per event error detection local interrupt status register" hexmask.long.word 0x10 16.--31. 1. "RESERVED," newline abitfld.long 0x10 0.--15. "EVENT,settable raw status for event #n" "0x0000=No event pending,0x0001=Set event (for debug)" line.long 0x14 "EVE_ED_LCL_IRQSTATUS,Error detection local interrupt status register" hexmask.long.word 0x14 16.--31. 1. "RESERVED," newline abitfld.long 0x14 0.--15. "EVENT,Clearable / enabled status for event #N" "0x0000=No (enabled) event pending,0x0001=Clear raw event" line.long 0x18 "EVE_ED_LCL_IRQENABLE_SET,Error detection local interrupt enable register" hexmask.long.word 0x18 16.--31. 1. "RESERVED," newline abitfld.long 0x18 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Enable interrupt" line.long 0x1C "EVE_ED_LCL_IRQENABLE_CLR,Error detection local interrupt clear register" hexmask.long.word 0x1C 16.--31. 1. "RESERVED," newline abitfld.long 0x1C 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Disable interrupt (i.e. / clear ENABLEn.." group.long 0x80210++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_4," group.long 0x80220++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_5," group.long 0x80230++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_6," group.long 0x80240++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_7," group.long 0x80214++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_4," group.long 0x80224++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_5," group.long 0x80234++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_6," group.long 0x80244++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_7," group.long 0x80218++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_4," group.long 0x80228++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_5," group.long 0x80238++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_6," group.long 0x80248++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_7," group.long 0x8021C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_4," group.long 0x8022C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_5," group.long 0x8023C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_6," group.long 0x8024C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_7," group.long 0x80200++0x0F line.long 0x00 "ARP32_NMI_IRQSTATUS_RAW," line.long 0x04 "ARP32_NMI_IRQSTATUS," line.long 0x08 "ARP32_NMI_IRQENABLE_SET," line.long 0x0C "ARP32_NMI_IRQENABLE_CLR," group.long 0x802FC++0x2B line.long 0x00 "ARP32_IRQWAKEEN,Wake enable register" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," newline abitfld.long 0x00 0.--23. "ENABLE,Wakeup Enable for event EVE_EVT_INT #n" "0x000000=Interrupt #n disabled for wakeup,0x000001=Interrupt #n enabled for wakeup" line.long 0x04 "MMR_LOCKi_0,MMR Lock/Unlock register" line.long 0x08 "MMR_LOCKi_1,MMR Lock/Unlock register" line.long 0x0C "MMR_LOCKi_2,MMR Lock/Unlock register" line.long 0x10 "MMR_LOCKi_3,MMR Lock/Unlock register" line.long 0x14 "MMR_LOCKi_4,MMR Lock/Unlock register" line.long 0x18 "MMR_LOCKi_5,MMR Lock/Unlock register" line.long 0x1C "MMR_LOCKi_6,MMR Lock/Unlock register" line.long 0x20 "MMR_LOCKi_7,MMR Lock/Unlock register" line.long 0x24 "MMR_LOCKi_8,MMR Lock/Unlock register" line.long 0x28 "MMR_LOCKi_9,MMR Lock/Unlock register" group.long 0x80400++0x07 line.long 0x00 "MISR_CTL," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "ENABLE,MISR Enable #N" "ARP32 PMEM path Bit,ARP32 DMEM path Bit,INTC WBUF path,?..." line.long 0x04 "MISR_CLEAR," hexmask.long 0x04 3.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--2. "CLEAR,MISR Clear #N" "Previous MISR clear command has completed,MISR Clear in progress (this state may never..,?..." group.long 0x80410++0x1F line.long 0x00 "MISR0_A," line.long 0x04 "MISR0_D," line.long 0x08 "MISR1_A," line.long 0x0C "MISR1_D," line.long 0x10 "MISR2_Dk_0," line.long 0x14 "MISR2_Dk_1," line.long 0x18 "MISR2_Dk_2," line.long 0x1C "MISR2_Dk_3," group.long 0x80500++0x03 line.long 0x00 "EVE_IRQ_EOI," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0,1,2,3,4,5,6,7" group.long 0x80510++0x13 line.long 0x00 "EVE_ED_OUT_IRQSTATUS_RAW," hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline abitfld.long 0x00 0.--15. "EVENT,Settable raw status for event #n" "0x0000=No event pending,0x0001=Set event (for debug)" line.long 0x04 "EVE_ED_OUT_IRQSTATUS," hexmask.long.word 0x04 16.--31. 1. "RESERVED," newline abitfld.long 0x04 0.--15. "EVENT,Clearable / enabled status for event #N" "0x0000=No (enabled) event pending,0x0001=Clear raw event" line.long 0x08 "EVE_ED_OUT_IRQENABLE_SET," hexmask.long.word 0x08 16.--31. 1. "RESERVED," newline abitfld.long 0x08 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Enable interrupt" line.long 0x0C "EVE_ED_OUT_IRQENABLE_CLR," hexmask.long.word 0x0C 16.--31. 1. "RESERVED," newline abitfld.long 0x0C 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Disable interrupt (i.e. / clear ENABLEn.." line.long 0x10 "EVE_INTk_OUT_IRQSTATUS_RAW_0," group.long 0x80530++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_1," group.long 0x80540++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_2," group.long 0x80550++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_3," group.long 0x80524++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_0," group.long 0x80534++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_1," group.long 0x80544++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_2," group.long 0x80554++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_3," group.long 0x80528++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_0," group.long 0x80538++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_1," group.long 0x80548++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_2," group.long 0x80558++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_3," group.long 0x8052C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_0," group.long 0x8053C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_1," group.long 0x8054C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_2," group.long 0x8055C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_3," rgroup.long 0x80600++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_8," rgroup.long 0x80610++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_9," rgroup.long 0x80620++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_10," rgroup.long 0x80630++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_11," rgroup.long 0x80640++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_12," rgroup.long 0x80650++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_13," group.long 0x80604++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_8," group.long 0x80614++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_9," group.long 0x80624++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_10," group.long 0x80634++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_11," group.long 0x80644++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_12," group.long 0x80654++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_13," group.long 0x80608++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_8," group.long 0x80618++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_9," group.long 0x80628++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_10," group.long 0x80638++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_11," group.long 0x80648++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_12," group.long 0x80658++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_13," group.long 0x8060C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_8," group.long 0x8061C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_9," group.long 0x8062C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_10," group.long 0x8063C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_11," group.long 0x8064C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_12," group.long 0x8065C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_13," rgroup.long 0x80680++0x1F line.long 0x00 "ARP32_INT14_IRQSTATUS_RAW," line.long 0x04 "ARP32_INT14_IRQSTATUS," line.long 0x08 "ARP32_INT14_IRQENABLE_SET," line.long 0x0C "ARP32_INT14_IRQENABLE_CLR," line.long 0x10 "ARP32_INT15_IRQSTATUS_RAW," line.long 0x14 "ARP32_INT15_IRQSTATUS," line.long 0x18 "ARP32_INT15_IRQENABLE_SET," line.long 0x1C "ARP32_INT15_IRQENABLE_CLR," group.long 0x80700++0x03 line.long 0x00 "EVE_GPOUTm_0," group.long 0x80710++0x03 line.long 0x00 "EVE_GPOUTm_1," group.long 0x80704++0x03 line.long 0x00 "EVE_GPOUTm_SET_0," group.long 0x80714++0x03 line.long 0x00 "EVE_GPOUTm_SET_1," group.long 0x80708++0x03 line.long 0x00 "EVE_GPOUTm_CLR_0," group.long 0x80718++0x03 line.long 0x00 "EVE_GPOUTm_CLR_1," group.long 0x8070C++0x03 line.long 0x00 "EVE_GPOUTm_PULSE_0," group.long 0x8071C++0x03 line.long 0x00 "EVE_GPOUTm_PULSE_1," group.long 0x80780++0x17 line.long 0x00 "EVE_CME_DONE_GPOUT," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," newline abitfld.long 0x00 0.--7. "EVENT,Internal CME Done Output #n" "0x00=Drive Internal CME Done #n is low/0,0x01=Internal CME Done is high/1" line.long 0x04 "EVE_CME_DONE_GPOUT_SET," hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," newline abitfld.long 0x04 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done is high/1" line.long 0x08 "EVE_CME_DONE_GPOUT_CLR," hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED," newline abitfld.long 0x08 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done #n is high/1" line.long 0x0C "EVE_CME_DONE_GPOUT_PULSE," hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED," newline abitfld.long 0x0C 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done #n is high/1" line.long 0x10 "EVE_CME_DONE_SEL," bitfld.long 0x10 28.--31. "SEL7,CME Done Output select for Bit #7 (n=7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 24.--27. "SEL6,CME Done Output select for Bit #6 (n=6)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 20.--23. "SEL5,CME Done Output select for Bit #5 (n=5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 16.--19. "SEL4,CME Done Output select for Bit #4 (n=4)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 12.--15. "SEL3,CME Done Output select for Bit #3 (n=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 8.--11. "SEL2,CME Done Output select for Bit #2 (n=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 4.--7. "SEL1,CME Done Output select for Bit #1 (n=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--3. "SEL0,CME Done Output select for Bit #0 (n=0)" "Driven by EDMA cc_int0,Driven by EDMA cc_int1,Driven by EDMA cc_int2,Driven by EDMA cc_int3,Driven by EDMA cc_int4,Driven by EDMA cc_int5,Driven by EDMA cc_int6,Driven by EDMA cc_int7,Driven by EVE_CME_DONE_GPOUTn,driven by eve_cme_done_gpout[0+n] (from EVE),driven by eve_cme_done_gpout[8+n] (from EVE2),driven by eve_cme_done_gpout[16+n] (from EVE3),driven by eve_cme_done_gpout[24+n] (from EVE4),driven by eve_cme_done_gpout[32+n] (from EVE5),driven by eve_cme_done_gpout[40+n] (from EVE6),driven by eve_cme_done_gpout[48+n] (from EVE7)" line.long 0x14 "EVE_CME_DONE_EN," hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," newline abitfld.long 0x14 0.--7. "EN,EVE CME Done EN #n" "0x00=EVE CME Done #n is disabled,0x01=EVE CME Done #n is enabled" rgroup.long 0x80FE0++0x0B line.long 0x00 "EVE_PM_STAT0," bitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 28.--30. "OCPM1_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 26.--27. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 24.--25. "OCPM1_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 23. "RESERVED," "0,1" newline bitfld.long 0x00 20.--22. "OCPM0_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 16.--17. "OCPM0_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 12.--14. "OCPS_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 8.--9. "OCPS_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 5. "MWAIT,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 4. "MSTANDBY,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 3. "SWAKEUP,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 1.--2. "SIDLEACK,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 0. "SIDLEREQ,Readable state of OCP Power management handshake" "0,1" line.long 0x04 "EVE_PM_STAT1," hexmask.long.byte 0x04 24.--31. 1. "RESERVED," newline rbitfld.long 0x04 22.--23. "STBY_MDISCACK_OCPM1,Readable state of internal power management handshake" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "STBY_MDISCACK_OCPM0,Readable state of internal power management handshake" "0,1,2,3" newline rbitfld.long 0x04 19. "STBY_MDISCREQ_OCPM1,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 18. "STBY_MDISCREQ_OCPM0,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 17. "IDLE_SDISCONNECT_ACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 16. "IDLE_SDISCONNECT_REQ,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 15. "EVE_IDLE_INTR_DISABLE,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 14. "TPTC1_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 13. "TPTC0_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 12. "EVE_PCACHE_OCP_BUSY,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 11. "EVE_CONTROL_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 10. "SMSET_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 9. "L2_EVE_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 8. "MMU1_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 7. "MMU1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 6. "MMU0_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 5. "MMU0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 4. "SCTM_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 3. "TPCC_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 2. "TPTC1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 1. "TPTC0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline bitfld.long 0x04 0. "SUBMODULE_IDLE_REQ," "0,1" line.long 0x08 "EVE_DBGOUT," hexmask.long.tbyte 0x08 8.--31. 1. "VALUE,Read returns state of eve_dbgout bus" newline rbitfld.long 0x08 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. "GROUP,Debug Group Output control : mux select" "disabled / all debug outputs driven to 0x0,select output group1,select output group2,?..." group.long 0x80FFC++0x03 line.long 0x00 "EVE_TEST," repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x80FF4)++0x03 line.long 0x00 "EVE_RSVD$1," repeat.end repeat 2. (list 0. 1. )(list 0x00 0x04 ) rgroup.long ($2+0x80740)++0x03 line.long 0x00 "EVE_GPIN$1," repeat.end width 0x0B tree.end tree "EVE_EDMA_TPCC" base ad:0x420A0000 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x04 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x04 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" newline rbitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x04 22.--23. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x04 19. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x04 15. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x04 11. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7" group.long 0xFC++0x43 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" line.long 0x04 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x04 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x08 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x08 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x0C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x10 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x14 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x18 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x1C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" hexmask.long.tbyte 0x20 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x20 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" hexmask.long.tbyte 0x24 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x24 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" hexmask.long.tbyte 0x28 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x28 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x28 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x2C "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.tbyte 0x2C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x2C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x2C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" hexmask.long.tbyte 0x30 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x30 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x30 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" hexmask.long.tbyte 0x34 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x34 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x34 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x38 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" hexmask.long.tbyte 0x38 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x38 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x38 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x3C "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" hexmask.long.tbyte 0x3C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x3C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x3C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" hexmask.long.tbyte 0x40 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x40 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x40 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x200++0x1F line.long 0x00 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x04 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x04 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x08 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x08 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x08 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x0C "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0C 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x0C 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x10 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x10 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x10 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x14 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x14 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x14 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x18 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x18 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x18 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x1C "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x1C 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x1C 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x240++0x23 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x00 31. "RESERVED,Reserved" "0,1" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 27. "RESERVED,Reserved" "0,1" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 23. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Reserved" "0,1" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 15. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x04 31. "RESERVED,Reserved" "0,1" bitfld.long 0x04 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 27. "RESERVED,Reserved" "0,1" bitfld.long 0x04 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 23. "RESERVED,Reserved" "0,1" bitfld.long 0x04 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED,Reserved" "0,1" bitfld.long 0x04 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 15. "RESERVED,Reserved" "0,1" bitfld.long 0x04 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 11. "RESERVED,Reserved" "0,1" bitfld.long 0x04 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED,Reserved" "0,1" bitfld.long 0x04 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x08 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x08 31. "RESERVED,Reserved" "0,1" bitfld.long 0x08 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 27. "RESERVED,Reserved" "0,1" bitfld.long 0x08 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 23. "RESERVED,Reserved" "0,1" bitfld.long 0x08 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED,Reserved" "0,1" bitfld.long 0x08 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 15. "RESERVED,Reserved" "0,1" bitfld.long 0x08 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 11. "RESERVED,Reserved" "0,1" bitfld.long 0x08 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED,Reserved" "0,1" bitfld.long 0x08 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x0C "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x0C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x10 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x10 31. "RESERVED,Reserved" "0,1" bitfld.long 0x10 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED,Reserved" "0,1" bitfld.long 0x10 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED,Reserved" "0,1" bitfld.long 0x10 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "RESERVED,Reserved" "0,1" bitfld.long 0x10 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 15. "RESERVED,Reserved" "0,1" bitfld.long 0x10 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 11. "RESERVED,Reserved" "0,1" bitfld.long 0x10 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" bitfld.long 0x10 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 3. "RESERVED,Reserved" "0,1" bitfld.long 0x10 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x14 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x14 31. "RESERVED,Reserved" "0,1" bitfld.long 0x14 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED,Reserved" "0,1" bitfld.long 0x14 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED,Reserved" "0,1" bitfld.long 0x14 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED,Reserved" "0,1" bitfld.long 0x14 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED,Reserved" "0,1" bitfld.long 0x14 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" bitfld.long 0x14 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED,Reserved" "0,1" bitfld.long 0x14 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x18 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x18 31. "RESERVED,Reserved" "0,1" bitfld.long 0x18 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED,Reserved" "0,1" bitfld.long 0x18 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED,Reserved" "0,1" bitfld.long 0x18 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED,Reserved" "0,1" bitfld.long 0x18 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED,Reserved" "0,1" bitfld.long 0x18 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED,Reserved" "0,1" bitfld.long 0x18 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED,Reserved" "0,1" bitfld.long 0x18 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED,Reserved" "0,1" bitfld.long 0x18 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x1C "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x1C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x20 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" rbitfld.long 0x20 31. "RESERVED," "0,1" bitfld.long 0x20 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 27. "RESERVED," "0,1" bitfld.long 0x20 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 23. "RESERVED," "0,1" bitfld.long 0x20 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 19. "RESERVED," "0,1" bitfld.long 0x20 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 15. "RESERVED," "0,1" bitfld.long 0x20 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 11. "RESERVED," "0,1" bitfld.long 0x20 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 7. "RESERVED," "0,1" bitfld.long 0x20 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 3. "RESERVED," "0,1" bitfld.long 0x20 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x280++0x07 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_QUEPRI,Queue Priority" hexmask.long 0x04 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" rgroup.long 0x300++0x23 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" newline bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" newline bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" newline bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" newline bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" newline bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" newline bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" newline bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" newline bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" newline bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" newline bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" newline bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" newline bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" newline bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" newline bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" newline bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" newline bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" newline bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" newline bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" newline bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" newline bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" line.long 0x08 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1" newline bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1" bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1" newline bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1" newline bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1" bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1" newline bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1" newline bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1" bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1" newline bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1" newline bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1" bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1" newline bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1" newline bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1" bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1" newline bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1" line.long 0x0C "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1" bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1" bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1" bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1" bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1" bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1" line.long 0x10 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,Event Missed #7" "0,1" newline bitfld.long 0x10 6. "E6,Event Missed #6" "0,1" bitfld.long 0x10 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x10 4. "E4,Event Missed #4" "0,1" bitfld.long 0x10 3. "E3,Event Missed #3" "0,1" newline bitfld.long 0x10 2. "E2,Event Missed #2" "0,1" bitfld.long 0x10 1. "E1,Event Missed #1" "0,1" newline bitfld.long 0x10 0. "E0,Event Missed #0" "0,1" line.long 0x14 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1" newline bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1" newline bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1" bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1" newline bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1" line.long 0x18 "EDMA_TPCC_CCERR,CC Error Register" hexmask.long.word 0x18 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 16. "TCERR,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register" "TCERR_0,TCERR_1" newline hexmask.long.byte 0x18 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD7_0,QTHRXCD7_1" newline bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD6_0,QTHRXCD6_1" bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD5_0,QTHRXCD5_1" newline bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD4_0,QTHRXCD4_1" bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD3_0,QTHRXCD3_1" newline bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD1_0,QTHRXCD1_1" newline bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x1C "EDMA_TPCC_CCERRCLR,CC Error Clear Register" hexmask.long.word 0x1C 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR" "0,1" newline hexmask.long.byte 0x1C 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect" "0,1" bitfld.long 0x1C 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect" "0,1" bitfld.long 0x1C 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" newline bitfld.long 0x1C 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect" "0,1" bitfld.long 0x1C 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" newline bitfld.long 0x1C 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect" "0,1" line.long 0x20 "EDMA_TPCC_EEVAL,Error Eval Register" hexmask.long 0x20 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 1. "SET,Error Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x20 0. "EVAL,Error Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x380++0x1F line.long 0x00 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x04 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x04 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x04 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x04 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x04 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x04 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x04 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x04 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x08 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x08 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x08 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x08 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x08 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x08 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x08 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x08 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x0C "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x0C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x0C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x0C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x0C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x0C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x0C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x0C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x10 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x10 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x10 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x10 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x10 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x10 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x10 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x10 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x14 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x14 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x14 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x14 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x14 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x14 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x14 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x14 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x18 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x18 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x18 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x18 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x18 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x18 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x18 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x18 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x1C "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x1C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x1C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x1C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x1C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x1C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x1C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x1C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x600++0x07 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" line.long 0x04 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" hexmask.long.byte 0x04 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" rbitfld.long 0x00 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" rbitfld.long 0x04 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,reads return 0's" rbitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" newline rbitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" rbitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" newline rbitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" rbitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" newline bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2" rbitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" newline rbitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 14.--15. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" rbitfld.long 0x00 5.--7. "RESERVED,reads return 0's" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" rbitfld.long 0x00 3. "RESERVED,reads return 0's" "0,1" newline bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.." rbitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" newline rbitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" group.long 0x700++0x0B line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" hexmask.long.tbyte 0x00 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" line.long 0x08 "EDMA_TPCC_AETCMD,AET Command" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "CLR,AET Clear commandCPU writes 0x0 has no effect" "0,1" rgroup.long 0x800++0x2F line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" line.long 0x04 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" newline rbitfld.long 0x04 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" rbitfld.long 0x04 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" newline rbitfld.long 0x04 2. "URE,User Read Error" "URE_0,URE_1" rbitfld.long 0x04 1. "UWE,User Write Error" "UWE_0,UWE_1" newline rbitfld.long 0x04 0. "UXE,User Execute Error" "UXE_0,UXE_1" line.long 0x08 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" line.long 0x0C "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x0C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x0C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x0C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x0C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x0C 10. "AID0,Allowed ID 0" "AID0_0,AID0_1" bitfld.long 0x0C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x0C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x0C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x0C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x0C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x0C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x0C 0. "UX,User Execute permission" "UX_0,UX_1" line.long 0x10 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x10 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x10 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x10 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x10 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x10 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x10 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x10 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x10 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x10 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x10 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x10 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x10 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x10 0. "UX,User Execute permission" "UX_0,?" line.long 0x14 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x14 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x14 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x14 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x14 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x14 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x14 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x14 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x14 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x14 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x14 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x14 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x14 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x14 0. "UX,User Execute permission" "UX_0,?" line.long 0x18 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x18 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x18 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x18 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x18 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x18 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x18 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x18 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x18 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x18 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x18 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x18 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x18 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x18 0. "UX,User Execute permission" "UX_0,?" line.long 0x1C "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x1C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x1C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x1C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x1C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x1C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x1C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x1C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x1C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x1C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x1C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x1C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x1C 0. "UX,User Execute permission" "UX_0,?" line.long 0x20 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x20 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x20 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x20 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x20 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x20 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x20 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x20 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x20 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x20 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x20 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x20 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x20 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x20 0. "UX,User Execute permission" "UX_0,?" line.long 0x24 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x24 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x24 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x24 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x24 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x24 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x24 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x24 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x24 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x24 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x24 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x24 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x24 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x24 0. "UX,User Execute permission" "UX_0,?" line.long 0x28 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" hexmask.long.word 0x28 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x28 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x28 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x28 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x28 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x28 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x28 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x28 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x28 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x28 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x28 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x28 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x28 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x28 0. "UX,User Execute permission" "UX_0,?" line.long 0x2C "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" hexmask.long.word 0x2C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x2C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x2C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x2C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x2C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x2C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x2C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x2C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x2C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x2C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x2C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x2C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x2C 0. "UX,User Execute permission" "UX_0,?" rgroup.long 0x1000++0x47 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" newline bitfld.long 0x04 29. "E61,Event #61" "0,1" bitfld.long 0x04 28. "E60,Event #60" "0,1" newline bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" newline bitfld.long 0x04 23. "E55,Event #55" "0,1" bitfld.long 0x04 22. "E54,Event #54" "0,1" newline bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" newline bitfld.long 0x04 17. "E49,Event #49" "0,1" bitfld.long 0x04 16. "E48,Event #48" "0,1" newline bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" newline bitfld.long 0x04 11. "E43,Event #43" "0,1" bitfld.long 0x04 10. "E42,Event #42" "0,1" newline bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" newline bitfld.long 0x04 5. "E37,Event #37" "0,1" bitfld.long 0x04 4. "E36,Event #36" "0,1" newline bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" line.long 0x08 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event #31" "0,1" bitfld.long 0x08 30. "E30,Event #30" "0,1" newline bitfld.long 0x08 29. "E29,Event #29" "0,1" bitfld.long 0x08 28. "E28,Event #28" "0,1" newline bitfld.long 0x08 27. "E27,Event #27" "0,1" bitfld.long 0x08 26. "E26,Event #26" "0,1" newline bitfld.long 0x08 25. "E25,Event #25" "0,1" bitfld.long 0x08 24. "E24,Event #24" "0,1" newline bitfld.long 0x08 23. "E23,Event #23" "0,1" bitfld.long 0x08 22. "E22,Event #22" "0,1" newline bitfld.long 0x08 21. "E21,Event #21" "0,1" bitfld.long 0x08 20. "E20,Event #20" "0,1" newline bitfld.long 0x08 19. "E19,Event #19" "0,1" bitfld.long 0x08 18. "E18,Event #18" "0,1" newline bitfld.long 0x08 17. "E17,Event #17" "0,1" bitfld.long 0x08 16. "E16,Event #16" "0,1" newline bitfld.long 0x08 15. "E15,Event #15" "0,1" bitfld.long 0x08 14. "E14,Event #14" "0,1" newline bitfld.long 0x08 13. "E13,Event #13" "0,1" bitfld.long 0x08 12. "E12,Event #12" "0,1" newline bitfld.long 0x08 11. "E11,Event #11" "0,1" bitfld.long 0x08 10. "E10,Event #10" "0,1" newline bitfld.long 0x08 9. "E9,Event #9" "0,1" bitfld.long 0x08 8. "E8,Event #8" "0,1" newline bitfld.long 0x08 7. "E7,Event #7" "0,1" bitfld.long 0x08 6. "E6,Event #6" "0,1" newline bitfld.long 0x08 5. "E5,Event #5" "0,1" bitfld.long 0x08 4. "E4,Event #4" "0,1" newline bitfld.long 0x08 3. "E3,Event #3" "0,1" bitfld.long 0x08 2. "E2,Event #2" "0,1" newline bitfld.long 0x08 1. "E1,Event #1" "0,1" bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event #63" "0,1" bitfld.long 0x0C 30. "E62,Event #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event #61" "0,1" bitfld.long 0x0C 28. "E60,Event #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event #59" "0,1" bitfld.long 0x0C 26. "E58,Event #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event #57" "0,1" bitfld.long 0x0C 24. "E56,Event #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event #55" "0,1" bitfld.long 0x0C 22. "E54,Event #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event #53" "0,1" bitfld.long 0x0C 20. "E52,Event #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event #51" "0,1" bitfld.long 0x0C 18. "E50,Event #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event #49" "0,1" bitfld.long 0x0C 16. "E48,Event #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event #47" "0,1" bitfld.long 0x0C 14. "E46,Event #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event #45" "0,1" bitfld.long 0x0C 12. "E44,Event #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event #43" "0,1" bitfld.long 0x0C 10. "E42,Event #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event #41" "0,1" bitfld.long 0x0C 8. "E40,Event #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event #39" "0,1" bitfld.long 0x0C 6. "E38,Event #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event #37" "0,1" bitfld.long 0x0C 4. "E36,Event #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event #35" "0,1" bitfld.long 0x0C 2. "E34,Event #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event #33" "0,1" bitfld.long 0x0C 0. "E32,Event #32" "0,1" line.long 0x10 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x10 31. "E31,Event #31" "0,1" bitfld.long 0x10 30. "E30,Event #30" "0,1" newline bitfld.long 0x10 29. "E29,Event #29" "0,1" bitfld.long 0x10 28. "E28,Event #28" "0,1" newline bitfld.long 0x10 27. "E27,Event #27" "0,1" bitfld.long 0x10 26. "E26,Event #26" "0,1" newline bitfld.long 0x10 25. "E25,Event #25" "0,1" bitfld.long 0x10 24. "E24,Event #24" "0,1" newline bitfld.long 0x10 23. "E23,Event #23" "0,1" bitfld.long 0x10 22. "E22,Event #22" "0,1" newline bitfld.long 0x10 21. "E21,Event #21" "0,1" bitfld.long 0x10 20. "E20,Event #20" "0,1" newline bitfld.long 0x10 19. "E19,Event #19" "0,1" bitfld.long 0x10 18. "E18,Event #18" "0,1" newline bitfld.long 0x10 17. "E17,Event #17" "0,1" bitfld.long 0x10 16. "E16,Event #16" "0,1" newline bitfld.long 0x10 15. "E15,Event #15" "0,1" bitfld.long 0x10 14. "E14,Event #14" "0,1" newline bitfld.long 0x10 13. "E13,Event #13" "0,1" bitfld.long 0x10 12. "E12,Event #12" "0,1" newline bitfld.long 0x10 11. "E11,Event #11" "0,1" bitfld.long 0x10 10. "E10,Event #10" "0,1" newline bitfld.long 0x10 9. "E9,Event #9" "0,1" bitfld.long 0x10 8. "E8,Event #8" "0,1" newline bitfld.long 0x10 7. "E7,Event #7" "0,1" bitfld.long 0x10 6. "E6,Event #6" "0,1" newline bitfld.long 0x10 5. "E5,Event #5" "0,1" bitfld.long 0x10 4. "E4,Event #4" "0,1" newline bitfld.long 0x10 3. "E3,Event #3" "0,1" bitfld.long 0x10 2. "E2,Event #2" "0,1" newline bitfld.long 0x10 1. "E1,Event #1" "0,1" bitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x14 31. "E63,Event #63" "0,1" bitfld.long 0x14 30. "E62,Event #62" "0,1" newline bitfld.long 0x14 29. "E61,Event #61" "0,1" bitfld.long 0x14 28. "E60,Event #60" "0,1" newline bitfld.long 0x14 27. "E59,Event #59" "0,1" bitfld.long 0x14 26. "E58,Event #58" "0,1" newline bitfld.long 0x14 25. "E57,Event #57" "0,1" bitfld.long 0x14 24. "E56,Event #56" "0,1" newline bitfld.long 0x14 23. "E55,Event #55" "0,1" bitfld.long 0x14 22. "E54,Event #54" "0,1" newline bitfld.long 0x14 21. "E53,Event #53" "0,1" bitfld.long 0x14 20. "E52,Event #52" "0,1" newline bitfld.long 0x14 19. "E51,Event #51" "0,1" bitfld.long 0x14 18. "E50,Event #50" "0,1" newline bitfld.long 0x14 17. "E49,Event #49" "0,1" bitfld.long 0x14 16. "E48,Event #48" "0,1" newline bitfld.long 0x14 15. "E47,Event #47" "0,1" bitfld.long 0x14 14. "E46,Event #46" "0,1" newline bitfld.long 0x14 13. "E45,Event #45" "0,1" bitfld.long 0x14 12. "E44,Event #44" "0,1" newline bitfld.long 0x14 11. "E43,Event #43" "0,1" bitfld.long 0x14 10. "E42,Event #42" "0,1" newline bitfld.long 0x14 9. "E41,Event #41" "0,1" bitfld.long 0x14 8. "E40,Event #40" "0,1" newline bitfld.long 0x14 7. "E39,Event #39" "0,1" bitfld.long 0x14 6. "E38,Event #38" "0,1" newline bitfld.long 0x14 5. "E37,Event #37" "0,1" bitfld.long 0x14 4. "E36,Event #36" "0,1" newline bitfld.long 0x14 3. "E35,Event #35" "0,1" bitfld.long 0x14 2. "E34,Event #34" "0,1" newline bitfld.long 0x14 1. "E33,Event #33" "0,1" bitfld.long 0x14 0. "E32,Event #32" "0,1" line.long 0x18 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x18 31. "E31,Event #31" "0,1" bitfld.long 0x18 30. "E30,Event #30" "0,1" newline bitfld.long 0x18 29. "E29,Event #29" "0,1" bitfld.long 0x18 28. "E28,Event #28" "0,1" newline bitfld.long 0x18 27. "E27,Event #27" "0,1" bitfld.long 0x18 26. "E26,Event #26" "0,1" newline bitfld.long 0x18 25. "E25,Event #25" "0,1" bitfld.long 0x18 24. "E24,Event #24" "0,1" newline bitfld.long 0x18 23. "E23,Event #23" "0,1" bitfld.long 0x18 22. "E22,Event #22" "0,1" newline bitfld.long 0x18 21. "E21,Event #21" "0,1" bitfld.long 0x18 20. "E20,Event #20" "0,1" newline bitfld.long 0x18 19. "E19,Event #19" "0,1" bitfld.long 0x18 18. "E18,Event #18" "0,1" newline bitfld.long 0x18 17. "E17,Event #17" "0,1" bitfld.long 0x18 16. "E16,Event #16" "0,1" newline bitfld.long 0x18 15. "E15,Event #15" "0,1" bitfld.long 0x18 14. "E14,Event #14" "0,1" newline bitfld.long 0x18 13. "E13,Event #13" "0,1" bitfld.long 0x18 12. "E12,Event #12" "0,1" newline bitfld.long 0x18 11. "E11,Event #11" "0,1" bitfld.long 0x18 10. "E10,Event #10" "0,1" newline bitfld.long 0x18 9. "E9,Event #9" "0,1" bitfld.long 0x18 8. "E8,Event #8" "0,1" newline bitfld.long 0x18 7. "E7,Event #7" "0,1" bitfld.long 0x18 6. "E6,Event #6" "0,1" newline bitfld.long 0x18 5. "E5,Event #5" "0,1" bitfld.long 0x18 4. "E4,Event #4" "0,1" newline bitfld.long 0x18 3. "E3,Event #3" "0,1" bitfld.long 0x18 2. "E2,Event #2" "0,1" newline bitfld.long 0x18 1. "E1,Event #1" "0,1" bitfld.long 0x18 0. "E0,Event #0" "0,1" line.long 0x1C "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x1C 31. "E63,Event #63" "0,1" bitfld.long 0x1C 30. "E62,Event #62" "0,1" newline bitfld.long 0x1C 29. "E61,Event #61" "0,1" bitfld.long 0x1C 28. "E60,Event #60" "0,1" newline bitfld.long 0x1C 27. "E59,Event #59" "0,1" bitfld.long 0x1C 26. "E58,Event #58" "0,1" newline bitfld.long 0x1C 25. "E57,Event #57" "0,1" bitfld.long 0x1C 24. "E56,Event #56" "0,1" newline bitfld.long 0x1C 23. "E55,Event #55" "0,1" bitfld.long 0x1C 22. "E54,Event #54" "0,1" newline bitfld.long 0x1C 21. "E53,Event #53" "0,1" bitfld.long 0x1C 20. "E52,Event #52" "0,1" newline bitfld.long 0x1C 19. "E51,Event #51" "0,1" bitfld.long 0x1C 18. "E50,Event #50" "0,1" newline bitfld.long 0x1C 17. "E49,Event #49" "0,1" bitfld.long 0x1C 16. "E48,Event #48" "0,1" newline bitfld.long 0x1C 15. "E47,Event #47" "0,1" bitfld.long 0x1C 14. "E46,Event #46" "0,1" newline bitfld.long 0x1C 13. "E45,Event #45" "0,1" bitfld.long 0x1C 12. "E44,Event #44" "0,1" newline bitfld.long 0x1C 11. "E43,Event #43" "0,1" bitfld.long 0x1C 10. "E42,Event #42" "0,1" newline bitfld.long 0x1C 9. "E41,Event #41" "0,1" bitfld.long 0x1C 8. "E40,Event #40" "0,1" newline bitfld.long 0x1C 7. "E39,Event #39" "0,1" bitfld.long 0x1C 6. "E38,Event #38" "0,1" newline bitfld.long 0x1C 5. "E37,Event #37" "0,1" bitfld.long 0x1C 4. "E36,Event #36" "0,1" newline bitfld.long 0x1C 3. "E35,Event #35" "0,1" bitfld.long 0x1C 2. "E34,Event #34" "0,1" newline bitfld.long 0x1C 1. "E33,Event #33" "0,1" bitfld.long 0x1C 0. "E32,Event #32" "0,1" line.long 0x20 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x20 31. "E31,Event #31" "0,1" bitfld.long 0x20 30. "E30,Event #30" "0,1" newline bitfld.long 0x20 29. "E29,Event #29" "0,1" bitfld.long 0x20 28. "E28,Event #28" "0,1" newline bitfld.long 0x20 27. "E27,Event #27" "0,1" bitfld.long 0x20 26. "E26,Event #26" "0,1" newline bitfld.long 0x20 25. "E25,Event #25" "0,1" bitfld.long 0x20 24. "E24,Event #24" "0,1" newline bitfld.long 0x20 23. "E23,Event #23" "0,1" bitfld.long 0x20 22. "E22,Event #22" "0,1" newline bitfld.long 0x20 21. "E21,Event #21" "0,1" bitfld.long 0x20 20. "E20,Event #20" "0,1" newline bitfld.long 0x20 19. "E19,Event #19" "0,1" bitfld.long 0x20 18. "E18,Event #18" "0,1" newline bitfld.long 0x20 17. "E17,Event #17" "0,1" bitfld.long 0x20 16. "E16,Event #16" "0,1" newline bitfld.long 0x20 15. "E15,Event #15" "0,1" bitfld.long 0x20 14. "E14,Event #14" "0,1" newline bitfld.long 0x20 13. "E13,Event #13" "0,1" bitfld.long 0x20 12. "E12,Event #12" "0,1" newline bitfld.long 0x20 11. "E11,Event #11" "0,1" bitfld.long 0x20 10. "E10,Event #10" "0,1" newline bitfld.long 0x20 9. "E9,Event #9" "0,1" bitfld.long 0x20 8. "E8,Event #8" "0,1" newline bitfld.long 0x20 7. "E7,Event #7" "0,1" bitfld.long 0x20 6. "E6,Event #6" "0,1" newline bitfld.long 0x20 5. "E5,Event #5" "0,1" bitfld.long 0x20 4. "E4,Event #4" "0,1" newline bitfld.long 0x20 3. "E3,Event #3" "0,1" bitfld.long 0x20 2. "E2,Event #2" "0,1" newline bitfld.long 0x20 1. "E1,Event #1" "0,1" bitfld.long 0x20 0. "E0,Event #0" "0,1" line.long 0x24 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x24 31. "E63,Event #63" "0,1" bitfld.long 0x24 30. "E62,Event #62" "0,1" newline bitfld.long 0x24 29. "E61,Event #61" "0,1" bitfld.long 0x24 28. "E60,Event #60" "0,1" newline bitfld.long 0x24 27. "E59,Event #59" "0,1" bitfld.long 0x24 26. "E58,Event #58" "0,1" newline bitfld.long 0x24 25. "E57,Event #57" "0,1" bitfld.long 0x24 24. "E56,Event #56" "0,1" newline bitfld.long 0x24 23. "E55,Event #55" "0,1" bitfld.long 0x24 22. "E54,Event #54" "0,1" newline bitfld.long 0x24 21. "E53,Event #53" "0,1" bitfld.long 0x24 20. "E52,Event #52" "0,1" newline bitfld.long 0x24 19. "E51,Event #51" "0,1" bitfld.long 0x24 18. "E50,Event #50" "0,1" newline bitfld.long 0x24 17. "E49,Event #49" "0,1" bitfld.long 0x24 16. "E48,Event #48" "0,1" newline bitfld.long 0x24 15. "E47,Event #47" "0,1" bitfld.long 0x24 14. "E46,Event #46" "0,1" newline bitfld.long 0x24 13. "E45,Event #45" "0,1" bitfld.long 0x24 12. "E44,Event #44" "0,1" newline bitfld.long 0x24 11. "E43,Event #43" "0,1" bitfld.long 0x24 10. "E42,Event #42" "0,1" newline bitfld.long 0x24 9. "E41,Event #41" "0,1" bitfld.long 0x24 8. "E40,Event #40" "0,1" newline bitfld.long 0x24 7. "E39,Event #39" "0,1" bitfld.long 0x24 6. "E38,Event #38" "0,1" newline bitfld.long 0x24 5. "E37,Event #37" "0,1" bitfld.long 0x24 4. "E36,Event #36" "0,1" newline bitfld.long 0x24 3. "E35,Event #35" "0,1" bitfld.long 0x24 2. "E34,Event #34" "0,1" newline bitfld.long 0x24 1. "E33,Event #33" "0,1" bitfld.long 0x24 0. "E32,Event #32" "0,1" line.long 0x28 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x28 31. "E31,Event #31" "0,1" bitfld.long 0x28 30. "E30,Event #30" "0,1" newline bitfld.long 0x28 29. "E29,Event #29" "0,1" bitfld.long 0x28 28. "E28,Event #28" "0,1" newline bitfld.long 0x28 27. "E27,Event #27" "0,1" bitfld.long 0x28 26. "E26,Event #26" "0,1" newline bitfld.long 0x28 25. "E25,Event #25" "0,1" bitfld.long 0x28 24. "E24,Event #24" "0,1" newline bitfld.long 0x28 23. "E23,Event #23" "0,1" bitfld.long 0x28 22. "E22,Event #22" "0,1" newline bitfld.long 0x28 21. "E21,Event #21" "0,1" bitfld.long 0x28 20. "E20,Event #20" "0,1" newline bitfld.long 0x28 19. "E19,Event #19" "0,1" bitfld.long 0x28 18. "E18,Event #18" "0,1" newline bitfld.long 0x28 17. "E17,Event #17" "0,1" bitfld.long 0x28 16. "E16,Event #16" "0,1" newline bitfld.long 0x28 15. "E15,Event #15" "0,1" bitfld.long 0x28 14. "E14,Event #14" "0,1" newline bitfld.long 0x28 13. "E13,Event #13" "0,1" bitfld.long 0x28 12. "E12,Event #12" "0,1" newline bitfld.long 0x28 11. "E11,Event #11" "0,1" bitfld.long 0x28 10. "E10,Event #10" "0,1" newline bitfld.long 0x28 9. "E9,Event #9" "0,1" bitfld.long 0x28 8. "E8,Event #8" "0,1" newline bitfld.long 0x28 7. "E7,Event #7" "0,1" bitfld.long 0x28 6. "E6,Event #6" "0,1" newline bitfld.long 0x28 5. "E5,Event #5" "0,1" bitfld.long 0x28 4. "E4,Event #4" "0,1" newline bitfld.long 0x28 3. "E3,Event #3" "0,1" bitfld.long 0x28 2. "E2,Event #2" "0,1" newline bitfld.long 0x28 1. "E1,Event #1" "0,1" bitfld.long 0x28 0. "E0,Event #0" "0,1" line.long 0x2C "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x2C 31. "E63,Event #63" "0,1" bitfld.long 0x2C 30. "E62,Event #62" "0,1" newline bitfld.long 0x2C 29. "E61,Event #61" "0,1" bitfld.long 0x2C 28. "E60,Event #60" "0,1" newline bitfld.long 0x2C 27. "E59,Event #59" "0,1" bitfld.long 0x2C 26. "E58,Event #58" "0,1" newline bitfld.long 0x2C 25. "E57,Event #57" "0,1" bitfld.long 0x2C 24. "E56,Event #56" "0,1" newline bitfld.long 0x2C 23. "E55,Event #55" "0,1" bitfld.long 0x2C 22. "E54,Event #54" "0,1" newline bitfld.long 0x2C 21. "E53,Event #53" "0,1" bitfld.long 0x2C 20. "E52,Event #52" "0,1" newline bitfld.long 0x2C 19. "E51,Event #51" "0,1" bitfld.long 0x2C 18. "E50,Event #50" "0,1" newline bitfld.long 0x2C 17. "E49,Event #49" "0,1" bitfld.long 0x2C 16. "E48,Event #48" "0,1" newline bitfld.long 0x2C 15. "E47,Event #47" "0,1" bitfld.long 0x2C 14. "E46,Event #46" "0,1" newline bitfld.long 0x2C 13. "E45,Event #45" "0,1" bitfld.long 0x2C 12. "E44,Event #44" "0,1" newline bitfld.long 0x2C 11. "E43,Event #43" "0,1" bitfld.long 0x2C 10. "E42,Event #42" "0,1" newline bitfld.long 0x2C 9. "E41,Event #41" "0,1" bitfld.long 0x2C 8. "E40,Event #40" "0,1" newline bitfld.long 0x2C 7. "E39,Event #39" "0,1" bitfld.long 0x2C 6. "E38,Event #38" "0,1" newline bitfld.long 0x2C 5. "E37,Event #37" "0,1" bitfld.long 0x2C 4. "E36,Event #36" "0,1" newline bitfld.long 0x2C 3. "E35,Event #35" "0,1" bitfld.long 0x2C 2. "E34,Event #34" "0,1" newline bitfld.long 0x2C 1. "E33,Event #33" "0,1" bitfld.long 0x2C 0. "E32,Event #32" "0,1" line.long 0x30 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x30 31. "E31,Event #31" "0,1" bitfld.long 0x30 30. "E30,Event #30" "0,1" newline bitfld.long 0x30 29. "E29,Event #29" "0,1" bitfld.long 0x30 28. "E28,Event #28" "0,1" newline bitfld.long 0x30 27. "E27,Event #27" "0,1" bitfld.long 0x30 26. "E26,Event #26" "0,1" newline bitfld.long 0x30 25. "E25,Event #25" "0,1" bitfld.long 0x30 24. "E24,Event #24" "0,1" newline bitfld.long 0x30 23. "E23,Event #23" "0,1" bitfld.long 0x30 22. "E22,Event #22" "0,1" newline bitfld.long 0x30 21. "E21,Event #21" "0,1" bitfld.long 0x30 20. "E20,Event #20" "0,1" newline bitfld.long 0x30 19. "E19,Event #19" "0,1" bitfld.long 0x30 18. "E18,Event #18" "0,1" newline bitfld.long 0x30 17. "E17,Event #17" "0,1" bitfld.long 0x30 16. "E16,Event #16" "0,1" newline bitfld.long 0x30 15. "E15,Event #15" "0,1" bitfld.long 0x30 14. "E14,Event #14" "0,1" newline bitfld.long 0x30 13. "E13,Event #13" "0,1" bitfld.long 0x30 12. "E12,Event #12" "0,1" newline bitfld.long 0x30 11. "E11,Event #11" "0,1" bitfld.long 0x30 10. "E10,Event #10" "0,1" newline bitfld.long 0x30 9. "E9,Event #9" "0,1" bitfld.long 0x30 8. "E8,Event #8" "0,1" newline bitfld.long 0x30 7. "E7,Event #7" "0,1" bitfld.long 0x30 6. "E6,Event #6" "0,1" newline bitfld.long 0x30 5. "E5,Event #5" "0,1" bitfld.long 0x30 4. "E4,Event #4" "0,1" newline bitfld.long 0x30 3. "E3,Event #3" "0,1" bitfld.long 0x30 2. "E2,Event #2" "0,1" newline bitfld.long 0x30 1. "E1,Event #1" "0,1" bitfld.long 0x30 0. "E0,Event #0" "0,1" line.long 0x34 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x34 31. "E63,Event #63" "0,1" bitfld.long 0x34 30. "E62,Event #62" "0,1" newline bitfld.long 0x34 29. "E61,Event #61" "0,1" bitfld.long 0x34 28. "E60,Event #60" "0,1" newline bitfld.long 0x34 27. "E59,Event #59" "0,1" bitfld.long 0x34 26. "E58,Event #58" "0,1" newline bitfld.long 0x34 25. "E57,Event #57" "0,1" bitfld.long 0x34 24. "E56,Event #56" "0,1" newline bitfld.long 0x34 23. "E55,Event #55" "0,1" bitfld.long 0x34 22. "E54,Event #54" "0,1" newline bitfld.long 0x34 21. "E53,Event #53" "0,1" bitfld.long 0x34 20. "E52,Event #52" "0,1" newline bitfld.long 0x34 19. "E51,Event #51" "0,1" bitfld.long 0x34 18. "E50,Event #50" "0,1" newline bitfld.long 0x34 17. "E49,Event #49" "0,1" bitfld.long 0x34 16. "E48,Event #48" "0,1" newline bitfld.long 0x34 15. "E47,Event #47" "0,1" bitfld.long 0x34 14. "E46,Event #46" "0,1" newline bitfld.long 0x34 13. "E45,Event #45" "0,1" bitfld.long 0x34 12. "E44,Event #44" "0,1" newline bitfld.long 0x34 11. "E43,Event #43" "0,1" bitfld.long 0x34 10. "E42,Event #42" "0,1" newline bitfld.long 0x34 9. "E41,Event #41" "0,1" bitfld.long 0x34 8. "E40,Event #40" "0,1" newline bitfld.long 0x34 7. "E39,Event #39" "0,1" bitfld.long 0x34 6. "E38,Event #38" "0,1" newline bitfld.long 0x34 5. "E37,Event #37" "0,1" bitfld.long 0x34 4. "E36,Event #36" "0,1" newline bitfld.long 0x34 3. "E35,Event #35" "0,1" bitfld.long 0x34 2. "E34,Event #34" "0,1" newline bitfld.long 0x34 1. "E33,Event #33" "0,1" bitfld.long 0x34 0. "E32,Event #32" "0,1" line.long 0x38 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x38 31. "E31,Event #31" "0,1" bitfld.long 0x38 30. "E30,Event #30" "0,1" newline bitfld.long 0x38 29. "E29,Event #29" "0,1" bitfld.long 0x38 28. "E28,Event #28" "0,1" newline bitfld.long 0x38 27. "E27,Event #27" "0,1" bitfld.long 0x38 26. "E26,Event #26" "0,1" newline bitfld.long 0x38 25. "E25,Event #25" "0,1" bitfld.long 0x38 24. "E24,Event #24" "0,1" newline bitfld.long 0x38 23. "E23,Event #23" "0,1" bitfld.long 0x38 22. "E22,Event #22" "0,1" newline bitfld.long 0x38 21. "E21,Event #21" "0,1" bitfld.long 0x38 20. "E20,Event #20" "0,1" newline bitfld.long 0x38 19. "E19,Event #19" "0,1" bitfld.long 0x38 18. "E18,Event #18" "0,1" newline bitfld.long 0x38 17. "E17,Event #17" "0,1" bitfld.long 0x38 16. "E16,Event #16" "0,1" newline bitfld.long 0x38 15. "E15,Event #15" "0,1" bitfld.long 0x38 14. "E14,Event #14" "0,1" newline bitfld.long 0x38 13. "E13,Event #13" "0,1" bitfld.long 0x38 12. "E12,Event #12" "0,1" newline bitfld.long 0x38 11. "E11,Event #11" "0,1" bitfld.long 0x38 10. "E10,Event #10" "0,1" newline bitfld.long 0x38 9. "E9,Event #9" "0,1" bitfld.long 0x38 8. "E8,Event #8" "0,1" newline bitfld.long 0x38 7. "E7,Event #7" "0,1" bitfld.long 0x38 6. "E6,Event #6" "0,1" newline bitfld.long 0x38 5. "E5,Event #5" "0,1" bitfld.long 0x38 4. "E4,Event #4" "0,1" newline bitfld.long 0x38 3. "E3,Event #3" "0,1" bitfld.long 0x38 2. "E2,Event #2" "0,1" newline bitfld.long 0x38 1. "E1,Event #1" "0,1" bitfld.long 0x38 0. "E0,Event #0" "0,1" line.long 0x3C "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x3C 31. "E63,Event #63" "0,1" bitfld.long 0x3C 30. "E62,Event #62" "0,1" newline bitfld.long 0x3C 29. "E61,Event #61" "0,1" bitfld.long 0x3C 28. "E60,Event #60" "0,1" newline bitfld.long 0x3C 27. "E59,Event #59" "0,1" bitfld.long 0x3C 26. "E58,Event #58" "0,1" newline bitfld.long 0x3C 25. "E57,Event #57" "0,1" bitfld.long 0x3C 24. "E56,Event #56" "0,1" newline bitfld.long 0x3C 23. "E55,Event #55" "0,1" bitfld.long 0x3C 22. "E54,Event #54" "0,1" newline bitfld.long 0x3C 21. "E53,Event #53" "0,1" bitfld.long 0x3C 20. "E52,Event #52" "0,1" newline bitfld.long 0x3C 19. "E51,Event #51" "0,1" bitfld.long 0x3C 18. "E50,Event #50" "0,1" newline bitfld.long 0x3C 17. "E49,Event #49" "0,1" bitfld.long 0x3C 16. "E48,Event #48" "0,1" newline bitfld.long 0x3C 15. "E47,Event #47" "0,1" bitfld.long 0x3C 14. "E46,Event #46" "0,1" newline bitfld.long 0x3C 13. "E45,Event #45" "0,1" bitfld.long 0x3C 12. "E44,Event #44" "0,1" newline bitfld.long 0x3C 11. "E43,Event #43" "0,1" bitfld.long 0x3C 10. "E42,Event #42" "0,1" newline bitfld.long 0x3C 9. "E41,Event #41" "0,1" bitfld.long 0x3C 8. "E40,Event #40" "0,1" newline bitfld.long 0x3C 7. "E39,Event #39" "0,1" bitfld.long 0x3C 6. "E38,Event #38" "0,1" newline bitfld.long 0x3C 5. "E37,Event #37" "0,1" bitfld.long 0x3C 4. "E36,Event #36" "0,1" newline bitfld.long 0x3C 3. "E35,Event #35" "0,1" bitfld.long 0x3C 2. "E34,Event #34" "0,1" newline bitfld.long 0x3C 1. "E33,Event #33" "0,1" bitfld.long 0x3C 0. "E32,Event #32" "0,1" line.long 0x40 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x40 31. "E31,Event #31" "0,1" bitfld.long 0x40 30. "E30,Event #30" "0,1" newline bitfld.long 0x40 29. "E29,Event #29" "0,1" bitfld.long 0x40 28. "E28,Event #28" "0,1" newline bitfld.long 0x40 27. "E27,Event #27" "0,1" bitfld.long 0x40 26. "E26,Event #26" "0,1" newline bitfld.long 0x40 25. "E25,Event #25" "0,1" bitfld.long 0x40 24. "E24,Event #24" "0,1" newline bitfld.long 0x40 23. "E23,Event #23" "0,1" bitfld.long 0x40 22. "E22,Event #22" "0,1" newline bitfld.long 0x40 21. "E21,Event #21" "0,1" bitfld.long 0x40 20. "E20,Event #20" "0,1" newline bitfld.long 0x40 19. "E19,Event #19" "0,1" bitfld.long 0x40 18. "E18,Event #18" "0,1" newline bitfld.long 0x40 17. "E17,Event #17" "0,1" bitfld.long 0x40 16. "E16,Event #16" "0,1" newline bitfld.long 0x40 15. "E15,Event #15" "0,1" bitfld.long 0x40 14. "E14,Event #14" "0,1" newline bitfld.long 0x40 13. "E13,Event #13" "0,1" bitfld.long 0x40 12. "E12,Event #12" "0,1" newline bitfld.long 0x40 11. "E11,Event #11" "0,1" bitfld.long 0x40 10. "E10,Event #10" "0,1" newline bitfld.long 0x40 9. "E9,Event #9" "0,1" bitfld.long 0x40 8. "E8,Event #8" "0,1" newline bitfld.long 0x40 7. "E7,Event #7" "0,1" bitfld.long 0x40 6. "E6,Event #6" "0,1" newline bitfld.long 0x40 5. "E5,Event #5" "0,1" bitfld.long 0x40 4. "E4,Event #4" "0,1" newline bitfld.long 0x40 3. "E3,Event #3" "0,1" bitfld.long 0x40 2. "E2,Event #2" "0,1" newline bitfld.long 0x40 1. "E1,Event #1" "0,1" bitfld.long 0x40 0. "E0,Event #0" "0,1" line.long 0x44 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x44 31. "E63,Event #63" "0,1" bitfld.long 0x44 30. "E62,Event #62" "0,1" newline bitfld.long 0x44 29. "E61,Event #61" "0,1" bitfld.long 0x44 28. "E60,Event #60" "0,1" newline bitfld.long 0x44 27. "E59,Event #59" "0,1" bitfld.long 0x44 26. "E58,Event #58" "0,1" newline bitfld.long 0x44 25. "E57,Event #57" "0,1" bitfld.long 0x44 24. "E56,Event #56" "0,1" newline bitfld.long 0x44 23. "E55,Event #55" "0,1" bitfld.long 0x44 22. "E54,Event #54" "0,1" newline bitfld.long 0x44 21. "E53,Event #53" "0,1" bitfld.long 0x44 20. "E52,Event #52" "0,1" newline bitfld.long 0x44 19. "E51,Event #51" "0,1" bitfld.long 0x44 18. "E50,Event #50" "0,1" newline bitfld.long 0x44 17. "E49,Event #49" "0,1" bitfld.long 0x44 16. "E48,Event #48" "0,1" newline bitfld.long 0x44 15. "E47,Event #47" "0,1" bitfld.long 0x44 14. "E46,Event #46" "0,1" newline bitfld.long 0x44 13. "E45,Event #45" "0,1" bitfld.long 0x44 12. "E44,Event #44" "0,1" newline bitfld.long 0x44 11. "E43,Event #43" "0,1" bitfld.long 0x44 10. "E42,Event #42" "0,1" newline bitfld.long 0x44 9. "E41,Event #41" "0,1" bitfld.long 0x44 8. "E40,Event #40" "0,1" newline bitfld.long 0x44 7. "E39,Event #39" "0,1" bitfld.long 0x44 6. "E38,Event #38" "0,1" newline bitfld.long 0x44 5. "E37,Event #37" "0,1" bitfld.long 0x44 4. "E36,Event #36" "0,1" newline bitfld.long 0x44 3. "E35,Event #35" "0,1" bitfld.long 0x44 2. "E34,Event #34" "0,1" newline bitfld.long 0x44 1. "E33,Event #33" "0,1" bitfld.long 0x44 0. "E32,Event #32" "0,1" rgroup.long 0x1050++0x2B line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x08 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x0C "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x10 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x14 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x18 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x1C "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x20 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x24 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x28 "EDMA_TPCC_IEVAL,Interrupt Eval Register" hexmask.long 0x28 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" newline bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1080++0x17 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 7. "E7,Event #7" "0,1" newline rbitfld.long 0x04 6. "E6,Event #6" "0,1" rbitfld.long 0x04 5. "E5,Event #5" "0,1" newline rbitfld.long 0x04 4. "E4,Event #4" "0,1" rbitfld.long 0x04 3. "E3,Event #3" "0,1" newline rbitfld.long 0x04 2. "E2,Event #2" "0,1" rbitfld.long 0x04 1. "E1,Event #1" "0,1" newline rbitfld.long 0x04 0. "E0,Event #0" "0,1" line.long 0x08 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,Event #7" "0,1" newline bitfld.long 0x08 6. "E6,Event #6" "0,1" bitfld.long 0x08 5. "E5,Event #5" "0,1" newline bitfld.long 0x08 4. "E4,Event #4" "0,1" bitfld.long 0x08 3. "E3,Event #3" "0,1" newline bitfld.long 0x08 2. "E2,Event #2" "0,1" bitfld.long 0x08 1. "E1,Event #1" "0,1" newline bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,Event #7" "0,1" newline bitfld.long 0x0C 6. "E6,Event #6" "0,1" bitfld.long 0x0C 5. "E5,Event #5" "0,1" newline bitfld.long 0x0C 4. "E4,Event #4" "0,1" bitfld.long 0x0C 3. "E3,Event #3" "0,1" newline bitfld.long 0x0C 2. "E2,Event #2" "0,1" bitfld.long 0x0C 1. "E1,Event #1" "0,1" newline bitfld.long 0x0C 0. "E0,Event #0" "0,1" line.long 0x10 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 7. "E7,Event #7" "0,1" newline rbitfld.long 0x10 6. "E6,Event #6" "0,1" rbitfld.long 0x10 5. "E5,Event #5" "0,1" newline rbitfld.long 0x10 4. "E4,Event #4" "0,1" rbitfld.long 0x10 3. "E3,Event #3" "0,1" newline rbitfld.long 0x10 2. "E2,Event #2" "0,1" rbitfld.long 0x10 1. "E1,Event #1" "0,1" newline rbitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event #7" "0,1" newline bitfld.long 0x14 6. "E6,Event #6" "0,1" bitfld.long 0x14 5. "E5,Event #5" "0,1" newline bitfld.long 0x14 4. "E4,Event #4" "0,1" bitfld.long 0x14 3. "E3,Event #3" "0,1" newline bitfld.long 0x14 2. "E2,Event #2" "0,1" bitfld.long 0x14 1. "E1,Event #1" "0,1" newline bitfld.long 0x14 0. "E0,Event #0" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2200++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2600++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2204++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2604++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2208++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2608++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x220C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x260C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2210++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2610++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2214++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2614++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2218++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2618++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x221C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x261C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2220++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2620++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2224++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2624++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2228++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2628++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x222C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x262C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2230++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2630++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2234++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2634++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2238++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2638++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x223C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x263C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2240++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2640++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2244++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2644++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2250++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2650++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2254++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2654++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2258++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2658++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x225C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x265C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2260++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2660++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2264++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2664++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2268++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2668++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x226C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x266C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2270++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2670++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2274++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2674++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2278++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2678++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2A78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2C78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2E78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2280++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2680++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2284++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2684++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2288++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2688++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x228C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x268C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2290++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2690++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2294++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2694++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4020++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_1,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4060++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_3,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_5,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_6,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_7,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4100++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_8,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4120++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_9,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4140++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4160++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_11,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4180++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_12,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_13,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_14,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_15,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4200++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4220++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_17,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4240++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_18,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4260++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_19,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4280++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_20,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_21,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_22,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_23,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4300++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_24,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4320++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_25,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4340++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_26,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4360++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_27,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4380++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_28,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_29,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_30,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_31,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4400++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4420++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_33,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4440++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_34,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4460++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_35,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4480++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_36,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_37,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_38,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_39,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4500++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_40,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4520++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_41,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4540++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_42,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4560++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_43,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4580++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_44,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_45,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_46,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_47,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4600++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4620++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_49,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4640++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_50,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4660++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_51,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4680++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_52,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_53,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_54,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_55,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4700++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_56,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4720++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_57,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4740++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_58,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4760++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_59,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4780++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_60,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_61,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_62,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_63,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4800++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4820++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_65,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4840++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_66,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4860++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_67,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4880++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_68,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_69,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_70,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_71,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4900++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_72,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4920++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_73,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4940++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_74,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4960++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_75,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4980++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_76,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_77,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_78,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_79,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_81,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_82,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_83,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_84,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_85,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_86,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_87,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_88,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_89,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_90,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_91,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_92,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_93,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_94,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_95,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_96,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_97,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_98,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_99,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_101,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_102,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_103,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_104,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_105,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_106,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_107,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_108,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_109,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_110,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_111,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_113,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_114,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_115,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_116,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_117,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_118,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_119,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_120,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_121,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_122,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_123,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_124,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_125,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_126,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_127,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" group.long 0x4024++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_1,Source Address" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" group.long 0x4064++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_3,Source Address" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" group.long 0x40A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_5,Source Address" group.long 0x40C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_6,Source Address" group.long 0x40E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_7,Source Address" group.long 0x4104++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_8,Source Address" group.long 0x4124++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_9,Source Address" group.long 0x4144++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_10,Source Address" group.long 0x4164++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_11,Source Address" group.long 0x4184++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_12,Source Address" group.long 0x41A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_13,Source Address" group.long 0x41C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_14,Source Address" group.long 0x41E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_15,Source Address" group.long 0x4204++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_16,Source Address" group.long 0x4224++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_17,Source Address" group.long 0x4244++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_18,Source Address" group.long 0x4264++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_19,Source Address" group.long 0x4284++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_20,Source Address" group.long 0x42A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_21,Source Address" group.long 0x42C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_22,Source Address" group.long 0x42E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_23,Source Address" group.long 0x4304++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_24,Source Address" group.long 0x4324++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_25,Source Address" group.long 0x4344++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_26,Source Address" group.long 0x4364++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_27,Source Address" group.long 0x4384++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_28,Source Address" group.long 0x43A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_29,Source Address" group.long 0x43C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_30,Source Address" group.long 0x43E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_31,Source Address" group.long 0x4404++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_32,Source Address" group.long 0x4424++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_33,Source Address" group.long 0x4444++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_34,Source Address" group.long 0x4464++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_35,Source Address" group.long 0x4484++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_36,Source Address" group.long 0x44A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_37,Source Address" group.long 0x44C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_38,Source Address" group.long 0x44E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_39,Source Address" group.long 0x4504++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_40,Source Address" group.long 0x4524++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_41,Source Address" group.long 0x4544++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_42,Source Address" group.long 0x4564++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_43,Source Address" group.long 0x4584++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_44,Source Address" group.long 0x45A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_45,Source Address" group.long 0x45C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_46,Source Address" group.long 0x45E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_47,Source Address" group.long 0x4604++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_48,Source Address" group.long 0x4624++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_49,Source Address" group.long 0x4644++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_50,Source Address" group.long 0x4664++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_51,Source Address" group.long 0x4684++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_52,Source Address" group.long 0x46A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_53,Source Address" group.long 0x46C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_54,Source Address" group.long 0x46E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_55,Source Address" group.long 0x4704++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_56,Source Address" group.long 0x4724++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_57,Source Address" group.long 0x4744++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_58,Source Address" group.long 0x4764++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_59,Source Address" group.long 0x4784++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_60,Source Address" group.long 0x47A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_61,Source Address" group.long 0x47C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_62,Source Address" group.long 0x47E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_63,Source Address" group.long 0x4804++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_64,Source Address" group.long 0x4824++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_65,Source Address" group.long 0x4844++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_66,Source Address" group.long 0x4864++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_67,Source Address" group.long 0x4884++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_68,Source Address" group.long 0x48A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_69,Source Address" group.long 0x48C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_70,Source Address" group.long 0x48E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_71,Source Address" group.long 0x4904++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_72,Source Address" group.long 0x4924++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_73,Source Address" group.long 0x4944++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_74,Source Address" group.long 0x4964++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_75,Source Address" group.long 0x4984++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_76,Source Address" group.long 0x49A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_77,Source Address" group.long 0x49C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_78,Source Address" group.long 0x49E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_79,Source Address" group.long 0x4A04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_80,Source Address" group.long 0x4A24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_81,Source Address" group.long 0x4A44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_82,Source Address" group.long 0x4A64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_83,Source Address" group.long 0x4A84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_84,Source Address" group.long 0x4AA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_85,Source Address" group.long 0x4AC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_86,Source Address" group.long 0x4AE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_87,Source Address" group.long 0x4B04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_88,Source Address" group.long 0x4B24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_89,Source Address" group.long 0x4B44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_90,Source Address" group.long 0x4B64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_91,Source Address" group.long 0x4B84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_92,Source Address" group.long 0x4BA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_93,Source Address" group.long 0x4BC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_94,Source Address" group.long 0x4BE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_95,Source Address" group.long 0x4C04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_96,Source Address" group.long 0x4C24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_97,Source Address" group.long 0x4C44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_98,Source Address" group.long 0x4C64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_99,Source Address" group.long 0x4C84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_100,Source Address" group.long 0x4CA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_101,Source Address" group.long 0x4CC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_102,Source Address" group.long 0x4CE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_103,Source Address" group.long 0x4D04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_104,Source Address" group.long 0x4D24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_105,Source Address" group.long 0x4D44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_106,Source Address" group.long 0x4D64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_107,Source Address" group.long 0x4D84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_108,Source Address" group.long 0x4DA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_109,Source Address" group.long 0x4DC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_110,Source Address" group.long 0x4DE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_111,Source Address" group.long 0x4E04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_112,Source Address" group.long 0x4E24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_113,Source Address" group.long 0x4E44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_114,Source Address" group.long 0x4E64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_115,Source Address" group.long 0x4E84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_116,Source Address" group.long 0x4EA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_117,Source Address" group.long 0x4EC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_118,Source Address" group.long 0x4EE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_119,Source Address" group.long 0x4F04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_120,Source Address" group.long 0x4F24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_121,Source Address" group.long 0x4F44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_122,Source Address" group.long 0x4F64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_123,Source Address" group.long 0x4F84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_124,Source Address" group.long 0x4FA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_125,Source Address" group.long 0x4FC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_126,Source Address" group.long 0x4FE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_127,Source Address" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x402C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_1,Destination Address" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x406C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_3,Destination Address" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x40AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_5,Destination Address" group.long 0x40CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_6,Destination Address" group.long 0x40EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_7,Destination Address" group.long 0x410C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_8,Destination Address" group.long 0x412C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_9,Destination Address" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x416C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_11,Destination Address" group.long 0x418C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_12,Destination Address" group.long 0x41AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_13,Destination Address" group.long 0x41CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_14,Destination Address" group.long 0x41EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_15,Destination Address" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x422C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_17,Destination Address" group.long 0x424C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_18,Destination Address" group.long 0x426C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_19,Destination Address" group.long 0x428C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_20,Destination Address" group.long 0x42AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_21,Destination Address" group.long 0x42CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_22,Destination Address" group.long 0x42EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_23,Destination Address" group.long 0x430C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_24,Destination Address" group.long 0x432C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_25,Destination Address" group.long 0x434C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_26,Destination Address" group.long 0x436C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_27,Destination Address" group.long 0x438C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_28,Destination Address" group.long 0x43AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_29,Destination Address" group.long 0x43CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_30,Destination Address" group.long 0x43EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_31,Destination Address" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x442C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_33,Destination Address" group.long 0x444C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_34,Destination Address" group.long 0x446C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_35,Destination Address" group.long 0x448C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_36,Destination Address" group.long 0x44AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_37,Destination Address" group.long 0x44CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_38,Destination Address" group.long 0x44EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_39,Destination Address" group.long 0x450C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_40,Destination Address" group.long 0x452C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_41,Destination Address" group.long 0x454C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_42,Destination Address" group.long 0x456C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_43,Destination Address" group.long 0x458C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_44,Destination Address" group.long 0x45AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_45,Destination Address" group.long 0x45CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_46,Destination Address" group.long 0x45EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_47,Destination Address" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x462C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_49,Destination Address" group.long 0x464C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_50,Destination Address" group.long 0x466C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_51,Destination Address" group.long 0x468C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_52,Destination Address" group.long 0x46AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_53,Destination Address" group.long 0x46CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_54,Destination Address" group.long 0x46EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_55,Destination Address" group.long 0x470C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_56,Destination Address" group.long 0x472C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_57,Destination Address" group.long 0x474C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_58,Destination Address" group.long 0x476C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_59,Destination Address" group.long 0x478C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_60,Destination Address" group.long 0x47AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_61,Destination Address" group.long 0x47CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_62,Destination Address" group.long 0x47EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_63,Destination Address" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x482C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_65,Destination Address" group.long 0x484C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_66,Destination Address" group.long 0x486C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_67,Destination Address" group.long 0x488C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_68,Destination Address" group.long 0x48AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_69,Destination Address" group.long 0x48CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_70,Destination Address" group.long 0x48EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_71,Destination Address" group.long 0x490C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_72,Destination Address" group.long 0x492C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_73,Destination Address" group.long 0x494C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_74,Destination Address" group.long 0x496C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_75,Destination Address" group.long 0x498C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_76,Destination Address" group.long 0x49AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_77,Destination Address" group.long 0x49CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_78,Destination Address" group.long 0x49EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_79,Destination Address" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_81,Destination Address" group.long 0x4A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_82,Destination Address" group.long 0x4A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_83,Destination Address" group.long 0x4A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_84,Destination Address" group.long 0x4AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_85,Destination Address" group.long 0x4ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_86,Destination Address" group.long 0x4AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_87,Destination Address" group.long 0x4B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_88,Destination Address" group.long 0x4B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_89,Destination Address" group.long 0x4B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_90,Destination Address" group.long 0x4B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_91,Destination Address" group.long 0x4B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_92,Destination Address" group.long 0x4BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_93,Destination Address" group.long 0x4BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_94,Destination Address" group.long 0x4BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_95,Destination Address" group.long 0x4C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_96,Destination Address" group.long 0x4C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_97,Destination Address" group.long 0x4C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_98,Destination Address" group.long 0x4C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_99,Destination Address" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_101,Destination Address" group.long 0x4CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_102,Destination Address" group.long 0x4CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_103,Destination Address" group.long 0x4D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_104,Destination Address" group.long 0x4D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_105,Destination Address" group.long 0x4D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_106,Destination Address" group.long 0x4D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_107,Destination Address" group.long 0x4D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_108,Destination Address" group.long 0x4DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_109,Destination Address" group.long 0x4DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_110,Destination Address" group.long 0x4DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_111,Destination Address" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_113,Destination Address" group.long 0x4E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_114,Destination Address" group.long 0x4E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_115,Destination Address" group.long 0x4E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_116,Destination Address" group.long 0x4EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_117,Destination Address" group.long 0x4ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_118,Destination Address" group.long 0x4EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_119,Destination Address" group.long 0x4F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_120,Destination Address" group.long 0x4F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_121,Destination Address" group.long 0x4F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_122,Destination Address" group.long 0x4F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_123,Destination Address" group.long 0x4F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_124,Destination Address" group.long 0x4FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_125,Destination Address" group.long 0x4FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_126,Destination Address" group.long 0x4FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_127,Destination Address" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_1," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_3," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_5," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_6," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_7," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_8," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_9," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_11," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_12," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_13," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_14," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_15," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_17," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_18," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_19," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_20," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_21," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_22," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_23," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_24," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_25," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_26," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_27," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_28," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_29," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_30," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_31," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_33," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_34," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_35," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_36," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_37," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_38," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_39," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_40," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_41," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_42," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_43," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_44," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_45," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_46," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_47," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_49," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_50," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_51," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_52," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_53," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_54," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_55," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_56," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_57," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_58," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_59," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_60," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_61," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_62," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_63," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_65," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_66," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_67," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_68," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_69," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_70," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_71," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_72," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_73," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_74," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_75," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_76," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_77," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_78," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_79," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_81," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_82," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_83," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_84," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_85," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_86," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_87," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_88," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_89," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_90," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_91," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_92," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_93," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_94," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_95," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_96," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_97," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_98," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_99," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_101," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_102," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_103," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_104," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_105," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_106," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_107," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_108," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_109," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_110," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_111," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_113," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_114," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_115," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_116," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_117," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_118," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_119," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_120," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_121," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_122," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_123," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_124," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_125," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_126," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_127," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x403C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x407C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x411C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x413C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x417C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x419C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x423C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x425C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x427C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x429C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x431C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x433C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x435C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x437C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x439C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x443C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x445C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x447C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x449C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x451C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x453C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x455C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x457C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x459C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x463C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x465C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x467C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x469C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x471C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x473C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x475C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x477C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x479C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x483C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x485C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x487C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x489C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x491C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x493C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x495C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x497C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x499C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x42086000 ad:0x42087000 ) tree "EVE_EDMA_TPTC$1" base $2 group.long 0x100++0x13 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 11.--12. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" rbitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" rbitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" line.long 0x04 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" rbitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x08 "EDMA_TPTCn_INTEN,Interrupt Enable Register" hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x0C "EDMA_TPTCn_INTCLR,Interrupt Clear Register" hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x10 "EDMA_TPTCn_INTCMD,Interrupt Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" group.long 0x120++0x13 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" rbitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 1. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" line.long 0x04 "EDMA_TPTCn_ERREN,Error Enable Register" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x04 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x04 1. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" line.long 0x08 "EDMA_TPTCn_ERRCLR,Error Clear Register" hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x08 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x08 1. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" line.long 0x0C "EDMA_TPTCn_ERRDET,Error Details Register" hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0C 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" rbitfld.long 0x0C 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 14.--15. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EDMA_TPTCn_ERRCMD,Error Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" group.long 0x200++0x17 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" rbitfld.long 0x00 21. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" rbitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "Highest priority,Priority 1,?,?,?,?,?,Lowest priority" newline rbitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" line.long 0x08 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count" line.long 0x0C "EDMA_TPTCn_PDST,Program Set Destination Address" line.long 0x10 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" line.long 0x14 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x240++0x0B line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" line.long 0x08 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" rgroup.long 0x250++0x13 line.long 0x00 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" line.long 0x04 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x08 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" line.long 0x0C "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" line.long 0x10 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" group.long 0x280++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" line.long 0x04 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" group.long 0x300++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x304++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x344++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x308++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x348++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x30C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x34C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x350++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" group.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x354++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end repeat.end tree "EVE_FW" base ad:0x4A151000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "EVE_FW_CFG_TARG" base ad:0x4A152000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "EVE_L2_FNOC" base ad:0x208A000 rgroup.long 0x00++0x03 line.long 0x00 "ERRLOGGER_i_ID_COREID_0," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" rgroup.long 0x200++0x03 line.long 0x00 "ERRLOGGER_i_ID_COREID_1," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" rgroup.long 0x04++0x03 line.long 0x00 "ERRLOGGER_i_ID_REVISIONID_0," hexmask.long.tbyte 0x00 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code" hexmask.long.byte 0x00 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself" rgroup.long 0x204++0x03 line.long 0x00 "ERRLOGGER_i_ID_REVISIONID_1," hexmask.long.tbyte 0x00 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code" hexmask.long.byte 0x00 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself" group.long 0x08++0x03 line.long 0x00 "ERRLOGGER_i_FAULTEN_0," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FAULTEN,Enable Fault output" "0,1" group.long 0x208++0x03 line.long 0x00 "ERRLOGGER_i_FAULTEN_1," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FAULTEN,Enable Fault output" "0,1" rgroup.long 0x0C++0x03 line.long 0x00 "ERRLOGGER_i_ERRVLD_0," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "ERRVLD,Error logged Valid" "0,1" rgroup.long 0x20C++0x03 line.long 0x00 "ERRLOGGER_i_ERRVLD_1," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "ERRVLD,Error logged Valid" "0,1" group.long 0x10++0x03 line.long 0x00 "ERRLOGGER_i_ERRCLR_0," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "ERRCLR,Clr ErrVld status" "0,1" group.long 0x210++0x03 line.long 0x00 "ERRLOGGER_i_ERRCLR_1," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "ERRCLR,Clr ErrVld status" "0,1" rgroup.long 0x14++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG0_0,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x00 31. "FORMAT,Format of ErrLog0 register" "0,1" bitfld.long 0x00 26.--30. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. "LEN1,Header: Len1 value" bitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "LOCK,Header: Lock bit value" "0,1" rgroup.long 0x214++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG0_1,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x00 31. "FORMAT,Format of ErrLog0 register" "0,1" bitfld.long 0x00 26.--30. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. "LEN1,Header: Len1 value" bitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "LOCK,Header: Lock bit value" "0,1" rgroup.long 0x18++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG1_0," hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED," hexmask.long.word 0x00 0.--13. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x218++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG1_1," hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED," hexmask.long.word 0x00 0.--13. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x20++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG3_0," rgroup.long 0x220++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG3_1," rgroup.long 0x28++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG5_0," hexmask.long.word 0x00 17.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--16. 1. "ERRLOG5,Header: User lsb value" rgroup.long 0x228++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG5_1," hexmask.long.word 0x00 17.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--16. 1. "ERRLOG5,Header: User lsb value" rgroup.long 0x100++0x03 line.long 0x00 "FLAGMUX_i_ID_COREID_0," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" rgroup.long 0x300++0x03 line.long 0x00 "FLAGMUX_i_ID_COREID_1," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" rgroup.long 0x104++0x03 line.long 0x00 "FLAGMUX_i_ID_REVISIONID_0," hexmask.long.tbyte 0x00 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code" hexmask.long.byte 0x00 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself" rgroup.long 0x304++0x03 line.long 0x00 "FLAGMUX_i_ID_REVISIONID_1," hexmask.long.tbyte 0x00 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code" hexmask.long.byte 0x00 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself" group.long 0x108++0x03 line.long 0x00 "FLAGMUX_i_FAULTEN_0," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FAULTEN,Global Fault Enable register" "0,1" group.long 0x308++0x03 line.long 0x00 "FLAGMUX_i_FAULTEN_1," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FAULTEN,Global Fault Enable register" "0,1" rgroup.long 0x10C++0x03 line.long 0x00 "FLAGMUX_i_FAULTSTATUS_0," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FAULTSTATUS,Global Fault Status register" "0,1" rgroup.long 0x30C++0x03 line.long 0x00 "FLAGMUX_i_FAULTSTATUS_1," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FAULTSTATUS,Global Fault Status register" "0,1" group.long 0x110++0x03 line.long 0x00 "FLAGMUX_i_FLAGINEN0_0," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" group.long 0x310++0x03 line.long 0x00 "FLAGMUX_i_FLAGINEN0_1," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" rgroup.long 0x114++0x03 line.long 0x00 "FLAGMUX_i_FLAGINSTATUS0_0," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" rgroup.long 0x314++0x03 line.long 0x00 "FLAGMUX_i_FLAGINSTATUS0_1," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x42081000 ad:0x42082000 ) tree "EVE_MMU$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Write 0's for future compatibility" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" rbitfld.long 0x00 5.--7. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x00 2. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" hexmask.long 0x08 5.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" newline bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0_w,EMUMISS_1_r" bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" hexmask.long 0x0C 5.--31. 1. "RESERVED,Write 0's for future compatibility Read returns 0" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" newline bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0,EMUMISS_1" bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" hexmask.long 0x00 1.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" hexmask.long 0x04 4.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable" "TWLENABLE_0,TWLENABLE_1" newline bitfld.long 0x04 1. "MMUENABLE,MMU enable" "MMUENABLE_0,MMUENABLE_1" rbitfld.long 0x04 0. "RESERVED,Write 0's for future compatibility" "0,1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" hexmask.long.byte 0x0C 0.--6. 1. "RESERVED,Write 0's for future compatibility" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 9. "RESERVED,Write 0's for future compatibility" "0,1" newline bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 0.--3. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" hexmask.long 0x14 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x18 4.--11. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x18 3. "P,Preserved bit" "P_0,P_1" newline bitfld.long 0x18 2. "V,Valid bit" "V_0,V_1" bitfld.long 0x18 0.--1. "PAGESIZE,Page size" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x1C 0.--11. 1. "RESERVED,Write 0's for future compatibility" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" hexmask.long 0x20 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" hexmask.long 0x24 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x28 4.--11. 1. "RESERVED,Reads return 0" bitfld.long 0x28 3. "P,Preserved bit" "P_0_r,P_1_r" newline bitfld.long 0x28 2. "V,Valid bit" "V_0_r,V_1_r" bitfld.long 0x28 0.--1. "PAGESIZE,Page size" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x2C 0.--11. 1. "RESERVED,Reads return 0" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" newline rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "0,1,2,3" bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "0,1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" hexmask.long.word 0x08 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 0.--15. 1. "RESERVED,Reserved" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 0.--15. 1. "RESERVED,Reserved" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 0.--15. 1. "RESERVED,Reserved" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the fourth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 0.--15. 1. "RESERVED,Reserved" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of fourth NO TRANSLATION REGION for 2D bursts" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" width 0x0B tree.end repeat.end tree "EVE_SCTM" base ad:0x42085000 group.long 0x00++0x03 line.long 0x00 "SCTM_CTCNTL," rbitfld.long 0x00 26.--31. "NUMSTM,Number of timers that can export through STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 18.--25. 1. "NUMINPT,Number of event input signals" rbitfld.long 0x00 13.--17. "NUMTIMR,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 7.--12. "NUMCNTR,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 3.--6. "REVID,Revision ID of SCTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1.--2. "IDLEMODE,Idle mode control" "Force Idle mode,Ths SCTM will acknoledge the idle request but..,Ths SCTM uses the smart idle protocol,Since the SCTM does not support internal wakeup.." bitfld.long 0x00 0. "ENBL,SCTM global enable" "ENBL_0,ENBL_1" group.long 0x20++0x0F line.long 0x00 "SCTM_CTSTMCNTL,This register contains the control and status settings for STM export" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," rbitfld.long 0x00 10. "XPORTACT,Indicates if a frame is currently being written to the STM" "0,1" bitfld.long 0x00 5.--9. "NUMXPORT,The total number of counters designated for export" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. "CCMXPORT,SW control of CCM message export" "0,1" rbitfld.long 0x00 3. "CCMVAIL,SCTM supports CCM export" "0,1" newline bitfld.long 0x00 2. "CSMXPORT,SW control of CSM message export" "0,1" bitfld.long 0x00 1. "SENDOVR,Send overflow data in CSM frame" "0,1" bitfld.long 0x00 0. "ENBL,STM global enable" "ENBL_0,ENBL_1" line.long 0x04 "SCTM_CTSTMMSTID," hexmask.long 0x04 7.--31. 1. "RESERVED," hexmask.long.byte 0x04 0.--6. 1. "MASTID,HW Master ID for this module" line.long 0x08 "SCTM_CTSTMINTVL," hexmask.long.word 0x08 16.--31. 1. "RESERVED," hexmask.long.word 0x08 0.--15. 1. "INTERVAL,Periodic export interval" line.long 0x0C "SCTM_CTSTMSEL,These registers mark the counters selected for export in the CSM" group.long 0x40++0x1F line.long 0x00 "SCTM_TINTVLR_i_0,These registers contain the interval match value for the corresponding timers in the SCTM" line.long 0x04 "SCTM_TINTVLR_i_1,These registers contain the interval match value for the corresponding timers in the SCTM" line.long 0x08 "SCTM_TINTVLR_i_2,These registers contain the interval match value for the corresponding timers in the SCTM" line.long 0x0C "SCTM_TINTVLR_i_3,These registers contain the interval match value for the corresponding timers in the SCTM" line.long 0x10 "SCTM_TINTVLR_i_4,These registers contain the interval match value for the corresponding timers in the SCTM" line.long 0x14 "SCTM_TINTVLR_i_5,These registers contain the interval match value for the corresponding timers in the SCTM" line.long 0x18 "SCTM_TINTVLR_i_6,These registers contain the interval match value for the corresponding timers in the SCTM" line.long 0x1C "SCTM_TINTVLR_i_7,These registers contain the interval match value for the corresponding timers in the SCTM" rgroup.long 0x7C++0x07 line.long 0x00 "SCTM_CTDBGNUM,Counter Timer Number Debug Event Register" hexmask.long 0x00 3.--31. 1. "RESERVED," bitfld.long 0x00 0.--2. "NUMEVT,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" line.long 0x04 "SCTM_CTDBGEVT,Counter Timer Debug Event Register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," hexmask.long.byte 0x04 0.--7. 1. "INPSEL,Index of event input signal on the module boundary" group.long 0xF0++0x03 line.long 0x00 "SCTM_CTGNBL,These registers provide for simultaneous enable/disable of 32 counters" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," hexmask.long.byte 0x00 0.--7. 1. "ENABLE,The counter enable bit field" group.long 0xF8++0x03 line.long 0x00 "SCTM_CTGRST,These registers provide for simultaneous reset of 32 counters" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," hexmask.long.byte 0x00 0.--7. 1. "RESET,The counter reset bit field" group.long 0x100++0x1F line.long 0x00 "SCTM_CTCR_WT_m_0,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x00 21.--31. 1. "RESERVED," bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" newline bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 7. "RESERVED," "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" newline bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" line.long 0x04 "SCTM_CTCR_WT_m_1,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x04 21.--31. 1. "RESERVED," bitfld.long 0x04 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x04 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x04 9. "DBG,Signal debug logic on interval match" "0,1" newline bitfld.long 0x04 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x04 7. "RESERVED," "0,1" rbitfld.long 0x04 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x04 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x04 4. "FREE,Counter ignores processor debug halt state" "0,1" newline bitfld.long 0x04 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x04 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x04 1. "RESET,Counter reset control" "0,1" bitfld.long 0x04 0. "ENBL,Counter enable control" "0,1" line.long 0x08 "SCTM_CTCR_WOT_n_0,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x08 21.--31. 1. "RESERVED," bitfld.long 0x08 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x08 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x08 9. "DBG,Signal debug logic on interval match" "0,1" newline bitfld.long 0x08 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x08 7. "RESERVED," "0,1" rbitfld.long 0x08 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x08 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x08 4. "FREE,Counter ignores processor debug halt state" "0,1" newline bitfld.long 0x08 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x08 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x08 1. "RESET,Counter reset control" "0,1" bitfld.long 0x08 0. "ENBL,Counter enable control" "0,1" line.long 0x0C "SCTM_CTCR_WOT_n_1,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x0C 21.--31. 1. "RESERVED," bitfld.long 0x0C 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x0C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x0C 9. "DBG,Signal debug logic on interval match" "0,1" newline bitfld.long 0x0C 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x0C 7. "RESERVED," "0,1" rbitfld.long 0x0C 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x0C 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x0C 4. "FREE,Counter ignores processor debug halt state" "0,1" newline bitfld.long 0x0C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x0C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0C 1. "RESET,Counter reset control" "0,1" bitfld.long 0x0C 0. "ENBL,Counter enable control" "0,1" line.long 0x10 "SCTM_CTCR_WOT_n_2,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x10 21.--31. 1. "RESERVED," bitfld.long 0x10 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x10 9. "DBG,Signal debug logic on interval match" "0,1" newline bitfld.long 0x10 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x10 7. "RESERVED," "0,1" rbitfld.long 0x10 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x10 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x10 4. "FREE,Counter ignores processor debug halt state" "0,1" newline bitfld.long 0x10 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x10 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x10 1. "RESET,Counter reset control" "0,1" bitfld.long 0x10 0. "ENBL,Counter enable control" "0,1" line.long 0x14 "SCTM_CTCR_WOT_n_3,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x14 21.--31. 1. "RESERVED," bitfld.long 0x14 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x14 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x14 9. "DBG,Signal debug logic on interval match" "0,1" newline bitfld.long 0x14 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x14 7. "RESERVED," "0,1" rbitfld.long 0x14 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x14 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x14 4. "FREE,Counter ignores processor debug halt state" "0,1" newline bitfld.long 0x14 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x14 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x14 1. "RESET,Counter reset control" "0,1" bitfld.long 0x14 0. "ENBL,Counter enable control" "0,1" line.long 0x18 "SCTM_CTCR_WOT_n_4,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x18 21.--31. 1. "RESERVED," bitfld.long 0x18 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x18 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x18 9. "DBG,Signal debug logic on interval match" "0,1" newline bitfld.long 0x18 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x18 7. "RESERVED," "0,1" rbitfld.long 0x18 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x18 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x18 4. "FREE,Counter ignores processor debug halt state" "0,1" newline bitfld.long 0x18 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x18 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x18 1. "RESET,Counter reset control" "0,1" bitfld.long 0x18 0. "ENBL,Counter enable control" "0,1" line.long 0x1C "SCTM_CTCR_WOT_n_5,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x1C 21.--31. 1. "RESERVED," bitfld.long 0x1C 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x1C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x1C 9. "DBG,Signal debug logic on interval match" "0,1" newline bitfld.long 0x1C 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x1C 7. "RESERVED," "0,1" rbitfld.long 0x1C 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x1C 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x1C 4. "FREE,Counter ignores processor debug halt state" "0,1" newline bitfld.long 0x1C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x1C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x1C 1. "RESET,Counter reset control" "0,1" bitfld.long 0x1C 0. "ENBL,Counter enable control" "0,1" rgroup.long 0x180++0x1F line.long 0x00 "SCTM_CTCNTR_k_0,These registers contain the value of an individual counter in the moduel" line.long 0x04 "SCTM_CTCNTR_k_1,These registers contain the value of an individual counter in the moduel" line.long 0x08 "SCTM_CTCNTR_k_2,These registers contain the value of an individual counter in the moduel" line.long 0x0C "SCTM_CTCNTR_k_3,These registers contain the value of an individual counter in the moduel" line.long 0x10 "SCTM_CTCNTR_k_4,These registers contain the value of an individual counter in the moduel" line.long 0x14 "SCTM_CTCNTR_k_5,These registers contain the value of an individual counter in the moduel" line.long 0x18 "SCTM_CTCNTR_k_6,These registers contain the value of an individual counter in the moduel" line.long 0x1C "SCTM_CTCNTR_k_7,These registers contain the value of an individual counter in the moduel" width 0x0B tree.end tree "EVE_SMSET" base ad:0x42088000 rgroup.long 0x00++0x03 line.long 0x00 "SMSET_ID,SMSET identification register" group.long 0x10++0x07 line.long 0x00 "SMSET_SCFG,SMSET system configuration register" hexmask.long 0x00 4.--31. 1. "RESERVED," rbitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "0,1,2,3" rbitfld.long 0x00 1. "RESERVED," "0,1" newline bitfld.long 0x00 0. "SOFTRESET,Triggers System Event Trace module reset" "0,1" line.long 0x04 "SMSET_SR,SMSET Status Register" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "SWFIFOEMPTY,SW message FIFO empty" "0,1" bitfld.long 0x04 8. "HWFIFOEMPTY,System event trace FIFO empty" "0,1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "RESETDONE,Reset completed" "0,1" group.long 0x24++0x07 line.long 0x00 "SMSET_CFG,SMSET Configuration register" bitfld.long 0x00 30.--31. "OWNERSHIP,Read to get current ownership status" "Release ownership,Claim ownership,Enable unit,No operation" bitfld.long 0x00 29. "DEBUGGEROVERRIDE,Reading from the DebuggerOverride bit returns a 1" "0,1" rbitfld.long 0x00 28. "CURRENTOWNER,This value reflects the SMSET ownership when the register is in a non-Available state" "0,1" newline hexmask.long.tbyte 0x00 8.--27. 1. "RESERVED," bitfld.long 0x00 7. "CAPTUREEN,When high the sytem event capture is enabled" "0,1" rbitfld.long 0x00 5.--6. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 4. "EVENTLEVEL,This applies to all selected events" "low level event detection,high level evnet detection" bitfld.long 0x00 3. "EVENTMSG,essage generated based on" "sampling window,event detection" bitfld.long 0x00 2. "STOP,Stop capturing system events from external trigger detection [EMU1 HIGH to LOW]" "0,1" newline bitfld.long 0x00 1. "START,Start capturing system events from external trigger detection [EMU0 HIGH to LOW]" "0,1" rbitfld.long 0x00 0. "RESERVED," "0,1" line.long 0x04 "SMSET_SESW,System Event Sampling Window register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," hexmask.long.byte 0x04 0.--7. 1. "SAMPLINGWINDOWSIZE,System events sampling window size expressed as SMSET cycles" group.long 0x30++0x1F line.long 0x00 "SMSET_SEDEN_i_1,System Event Detection Enable register 1" bitfld.long 0x00 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x00 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x00 29. "EVENT30EN,Event 30 detection enable" "0,1" newline bitfld.long 0x00 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x00 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x00 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x00 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x00 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x00 23. "EVENT24EN,Event 24 detection enable" "0,1" newline bitfld.long 0x00 22. "EVENT23EN,Event 23 detection enable" "0,1" bitfld.long 0x00 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x00 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x00 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x00 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x00 17. "EVENT18EN,Event 18 detection enable" "0,1" newline bitfld.long 0x00 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x00 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x00 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x00 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x00 12. "EVENT13EN,Event 13 detection enable" "0,1" bitfld.long 0x00 11. "EVENT12EN,Event 12 detection enable" "0,1" newline bitfld.long 0x00 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x00 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x00 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x00 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x00 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x00 5. "EVENT6EN,Event 6 detection enable" "0,1" newline bitfld.long 0x00 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x00 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x00 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x00 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x00 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x04 "SMSET_SEDEN_i_2,System Event Detection Enable register 1" bitfld.long 0x04 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x04 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x04 29. "EVENT30EN,Event 30 detection enable" "0,1" newline bitfld.long 0x04 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x04 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x04 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x04 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x04 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x04 23. "EVENT24EN,Event 24 detection enable" "0,1" newline bitfld.long 0x04 22. "EVENT23EN,Event 23 detection enable" "0,1" bitfld.long 0x04 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x04 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x04 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x04 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x04 17. "EVENT18EN,Event 18 detection enable" "0,1" newline bitfld.long 0x04 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x04 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x04 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x04 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x04 12. "EVENT13EN,Event 13 detection enable" "0,1" bitfld.long 0x04 11. "EVENT12EN,Event 12 detection enable" "0,1" newline bitfld.long 0x04 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x04 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x04 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x04 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x04 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x04 5. "EVENT6EN,Event 6 detection enable" "0,1" newline bitfld.long 0x04 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x04 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x04 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x04 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x04 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x08 "SMSET_SEDEN_i_3,System Event Detection Enable register 1" bitfld.long 0x08 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x08 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x08 29. "EVENT30EN,Event 30 detection enable" "0,1" newline bitfld.long 0x08 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x08 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x08 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x08 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x08 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x08 23. "EVENT24EN,Event 24 detection enable" "0,1" newline bitfld.long 0x08 22. "EVENT23EN,Event 23 detection enable" "0,1" bitfld.long 0x08 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x08 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x08 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x08 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x08 17. "EVENT18EN,Event 18 detection enable" "0,1" newline bitfld.long 0x08 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x08 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x08 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x08 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x08 12. "EVENT13EN,Event 13 detection enable" "0,1" bitfld.long 0x08 11. "EVENT12EN,Event 12 detection enable" "0,1" newline bitfld.long 0x08 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x08 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x08 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x08 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x08 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x08 5. "EVENT6EN,Event 6 detection enable" "0,1" newline bitfld.long 0x08 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x08 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x08 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x08 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x08 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x0C "SMSET_SEDEN_i_4,System Event Detection Enable register 1" bitfld.long 0x0C 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x0C 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x0C 29. "EVENT30EN,Event 30 detection enable" "0,1" newline bitfld.long 0x0C 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x0C 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x0C 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x0C 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x0C 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x0C 23. "EVENT24EN,Event 24 detection enable" "0,1" newline bitfld.long 0x0C 22. "EVENT23EN,Event 23 detection enable" "0,1" bitfld.long 0x0C 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x0C 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x0C 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x0C 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x0C 17. "EVENT18EN,Event 18 detection enable" "0,1" newline bitfld.long 0x0C 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x0C 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x0C 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x0C 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x0C 12. "EVENT13EN,Event 13 detection enable" "0,1" bitfld.long 0x0C 11. "EVENT12EN,Event 12 detection enable" "0,1" newline bitfld.long 0x0C 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x0C 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x0C 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x0C 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x0C 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x0C 5. "EVENT6EN,Event 6 detection enable" "0,1" newline bitfld.long 0x0C 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x0C 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x0C 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x0C 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x0C 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x10 "SMSET_SEDEN_i_5,System Event Detection Enable register 1" bitfld.long 0x10 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x10 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x10 29. "EVENT30EN,Event 30 detection enable" "0,1" newline bitfld.long 0x10 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x10 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x10 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x10 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x10 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x10 23. "EVENT24EN,Event 24 detection enable" "0,1" newline bitfld.long 0x10 22. "EVENT23EN,Event 23 detection enable" "0,1" bitfld.long 0x10 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x10 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x10 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x10 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x10 17. "EVENT18EN,Event 18 detection enable" "0,1" newline bitfld.long 0x10 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x10 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x10 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x10 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x10 12. "EVENT13EN,Event 13 detection enable" "0,1" bitfld.long 0x10 11. "EVENT12EN,Event 12 detection enable" "0,1" newline bitfld.long 0x10 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x10 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x10 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x10 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x10 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x10 5. "EVENT6EN,Event 6 detection enable" "0,1" newline bitfld.long 0x10 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x10 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x10 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x10 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x10 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x14 "SMSET_SEDEN_i_6,System Event Detection Enable register 1" bitfld.long 0x14 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x14 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x14 29. "EVENT30EN,Event 30 detection enable" "0,1" newline bitfld.long 0x14 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x14 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x14 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x14 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x14 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x14 23. "EVENT24EN,Event 24 detection enable" "0,1" newline bitfld.long 0x14 22. "EVENT23EN,Event 23 detection enable" "0,1" bitfld.long 0x14 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x14 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x14 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x14 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x14 17. "EVENT18EN,Event 18 detection enable" "0,1" newline bitfld.long 0x14 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x14 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x14 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x14 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x14 12. "EVENT13EN,Event 13 detection enable" "0,1" bitfld.long 0x14 11. "EVENT12EN,Event 12 detection enable" "0,1" newline bitfld.long 0x14 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x14 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x14 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x14 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x14 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x14 5. "EVENT6EN,Event 6 detection enable" "0,1" newline bitfld.long 0x14 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x14 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x14 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x14 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x14 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x18 "SMSET_SEDEN_i_7,System Event Detection Enable register 1" bitfld.long 0x18 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x18 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x18 29. "EVENT30EN,Event 30 detection enable" "0,1" newline bitfld.long 0x18 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x18 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x18 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x18 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x18 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x18 23. "EVENT24EN,Event 24 detection enable" "0,1" newline bitfld.long 0x18 22. "EVENT23EN,Event 23 detection enable" "0,1" bitfld.long 0x18 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x18 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x18 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x18 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x18 17. "EVENT18EN,Event 18 detection enable" "0,1" newline bitfld.long 0x18 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x18 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x18 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x18 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x18 12. "EVENT13EN,Event 13 detection enable" "0,1" bitfld.long 0x18 11. "EVENT12EN,Event 12 detection enable" "0,1" newline bitfld.long 0x18 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x18 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x18 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x18 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x18 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x18 5. "EVENT6EN,Event 6 detection enable" "0,1" newline bitfld.long 0x18 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x18 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x18 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x18 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x18 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x1C "SMSET_SEDEN_i_8,System Event Detection Enable register 1" bitfld.long 0x1C 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x1C 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x1C 29. "EVENT30EN,Event 30 detection enable" "0,1" newline bitfld.long 0x1C 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x1C 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x1C 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x1C 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x1C 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x1C 23. "EVENT24EN,Event 24 detection enable" "0,1" newline bitfld.long 0x1C 22. "EVENT23EN,Event 23 detection enable" "0,1" bitfld.long 0x1C 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x1C 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x1C 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x1C 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x1C 17. "EVENT18EN,Event 18 detection enable" "0,1" newline bitfld.long 0x1C 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x1C 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x1C 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x1C 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x1C 12. "EVENT13EN,Event 13 detection enable" "0,1" bitfld.long 0x1C 11. "EVENT12EN,Event 12 detection enable" "0,1" newline bitfld.long 0x1C 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x1C 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x1C 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x1C 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x1C 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x1C 5. "EVENT6EN,Event 6 detection enable" "0,1" newline bitfld.long 0x1C 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x1C 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x1C 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x1C 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x1C 0. "EVENT1EN,Event 1 detection enable" "0,1" width 0x0B tree.end tree "EVE_TARG" base ad:0x44000A00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "EVE_VCOP" base ad:0x42084000 rgroup.long 0x00++0x13 line.long 0x00 "VCOP_PID," line.long 0x04 "VCOP_CTRL,VCOP Control Register" hexmask.long 0x04 2.--31. 1. "RESERVED," bitfld.long 0x04 1. "STEP_GO,Starts executing a single i4 iteration" "STEP_GO_0,STEP_GO_1" bitfld.long 0x04 0. "STEP_EN,Enable Single Step mode" "STEP_EN_0,STEP_EN_1" line.long 0x08 "VCOP_STATUS,VCOP status register" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "VEC_RDY,Vector core ready to accept next vector instruction" "0,1" bitfld.long 0x08 1. "VEC_DONE,Vector core has completed execution of submitted vector loops" "0,1" bitfld.long 0x08 0. "STEP_RDY,Ready for next step (single step)" "STEP_RDY_0,STEP_RDY_1" line.long 0x0C "VCOP_MAX_ITERS," hexmask.long.word 0x0C 16.--31. 1. "RESESERVED,Reserved" hexmask.long.word 0x0C 0.--15. 1. "MAX_ITERS,Maximum iteration count" line.long 0x10 "VCOP_ERROR,Error interrupt enalbe and status register" hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 23. "ERR_DIS7,Error Interrupt disable" "ERR_DIS7_0,ERR_DIS7_1" bitfld.long 0x10 22. "ERR_DIS6,Error Interrupt disable" "ERR_DIS6_0,ERR_DIS6_1" bitfld.long 0x10 21. "ERR_DIS5,Error Interrupt disable" "ERR_DIS5_0,ERR_DIS5_1" bitfld.long 0x10 20. "ERR_DIS4,Error Interrupt disable" "ERR_DIS4_0,ERR_DIS4_1" newline bitfld.long 0x10 19. "ERR_DIS3,Error Interrupt disable" "ERR_DIS3_0,ERR_DIS3_1" bitfld.long 0x10 18. "ERR_DIS2,Error Interrupt disable" "ERR_DIS2_0,ERR_DIS2_1" bitfld.long 0x10 17. "ERR_DIS1,Error Interrupt disable" "ERR_DIS1_0,ERR_DIS1_1" bitfld.long 0x10 16. "ERR_DIS0,Error Interrupt disable" "ERR_DIS0_0,ERR_DIS0_1" hexmask.long.byte 0x10 8.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x10 7. "ERR_ST7,ST_PDDA bank conflict error status" "ERR_ST7_0,ERR_ST7_1" bitfld.long 0x10 6. "ERR_ST6,ST WBUF out-of-bound error status" "ERR_ST6_0,ERR_ST6_1" bitfld.long 0x10 5. "ERR_ST5,ST IBUF out-of-bound error status" "ERR_ST5_0,ERR_ST5_1" bitfld.long 0x10 4. "ERR_ST4,LD WBUF out-of-bound error status" "ERR_ST4_0,ERR_ST4_1" bitfld.long 0x10 3. "ERR_ST3,LD IBUF out-of-bound error status" "ERR_ST3_0,ERR_ST3_1" newline bitfld.long 0x10 2. "ERR_ST2,Illegal parameter error status" "ERR_ST2_0,ERR_ST2_1" bitfld.long 0x10 1. "ERR_ST1,Illegal instruction error status" "ERR_ST1_0,ERR_ST1_1" bitfld.long 0x10 0. "ERR_ST0,Illegal instruction error status" "ERR_ST0_0,ERR_ST0_1" rgroup.long 0x20++0x07 line.long 0x00 "VCOP_VLOOP_PTR,The VLOOP pointer" line.long 0x04 "VCOP_PARAM_PTR," rgroup.long 0x30++0x0B line.long 0x00 "VCOP_I0_I1,I0. I1 loop variables register provides a snapshot of i0 and i1" hexmask.long.word 0x00 16.--31. 1. "I1,Snapshot of I1 loop variable" hexmask.long.word 0x00 0.--15. 1. "I0,Snapshot of I0 loop variable" line.long 0x04 "VCOP_I2_I3,I2. I3 loop variables register provides a snapshot of i2 and i3" hexmask.long.word 0x04 16.--31. 1. "I3,Snapshot of I2 loop variable" hexmask.long.word 0x04 0.--15. 1. "I2,Snapshot of I3 loop variable" line.long 0x08 "VCOP_I4,I4 loop variables register provides a snapshot of i4" hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved Read returns 0s" hexmask.long.word 0x08 0.--15. 1. "I4,Snapshot of I4 loop variable" rgroup.long 0x40++0x3F line.long 0x00 "VCOP_LD_PTR_i_0,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" line.long 0x04 "VCOP_LD_PTR_i_1,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" line.long 0x08 "VCOP_LD_PTR_i_2,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" line.long 0x0C "VCOP_LD_PTR_i_3,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" line.long 0x10 "VCOP_LD_PTR_i_4,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" line.long 0x14 "VCOP_LD_PTR_i_5,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" line.long 0x18 "VCOP_LD_PTR_i_6,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" line.long 0x1C "VCOP_LD_PTR_i_7,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" line.long 0x20 "VCOP_ST_PTR_j_0,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" line.long 0x24 "VCOP_ST_PTR_j_1,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" line.long 0x28 "VCOP_ST_PTR_j_2,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" line.long 0x2C "VCOP_ST_PTR_j_3,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" line.long 0x30 "VCOP_ST_PTR_j_4,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" line.long 0x34 "VCOP_ST_PTR_j_5,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" line.long 0x38 "VCOP_ST_PTR_j_6,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" line.long 0x3C "VCOP_ST_PTR_j_7,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" width 0x0B tree.end tree "GMAC_SW_TARG" base ad:0x48488000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end repeat 4. (list 2. 3. 4. 1. )(list ad:0x48055000 ad:0x48057000 ad:0x48059000 ad:0x4AE10000 ) tree "GPIO$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "GPIO_REVISION,IP revision identifier (X.Y.R)" group.long 0x10++0x03 line.long 0x00 "GPIO_SYSCONFIG,System configuration register" hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 3.--4. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wake-up control" "ENAWAKEUP_0,ENAWAKEUP_1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOIDLE,OCP clock gating control" "AUTOIDLE_0,AUTOIDLE_1" group.long 0x20++0x2B line.long 0x00 "GPIO_EOI,Software end of interrupt" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1" line.long 0x04 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. showing all active events (enabled and not enabled). (corresponding to first line of interrupt)" line.long 0x08 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. showing all active events (enabled and not enabled). (corresponding to second line of interrupt)" line.long 0x0C "GPIO_IRQSTATUS_0,Per-event interrupt status vector. showing all active and enabled events (corresponding to first line of interrupt)" line.long 0x10 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector. showing all active and enabled events (corresponding to second line of interrupt)" line.long 0x14 "GPIO_IRQSTATUS_SET_0,Per-event interrupt-enable set vector (corresponding to first line of interrupt)" line.long 0x18 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" line.long 0x1C "GPIO_IRQSTATUS_CLR_0,Per-event interrupt-enable clear vector (corresponding to first line of interrupt)" line.long 0x20 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" line.long 0x24 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" line.long 0x28 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" rgroup.long 0x114++0x03 line.long 0x00 "GPIO_SYSSTATUS,System status register" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "RESETDONE," "RESETDONE_0_r,RESETDONE_1_r" group.long 0x130++0x27 line.long 0x00 "GPIO_CTRL,GPIO control register" hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1.--2. "GATINGRATIO,Clock gating ratio for event detection" "GATINGRATIO_0,GATINGRATIO_1,GATINGRATIO_2,GATINGRATIO_3" bitfld.long 0x00 0. "DISABLEMODULE," "DISABLEMODULE_0,DISABLEMODULE_1" line.long 0x04 "GPIO_OE,Output enable register" line.long 0x08 "GPIO_DATAIN,Data input register (with sampled input data)" line.long 0x0C "GPIO_DATAOUT,Data-output register (data to set on output pins)" line.long 0x10 "GPIO_LEVELDETECT0,Detect low-level register" line.long 0x14 "GPIO_LEVELDETECT1,Detect high-level register" line.long 0x18 "GPIO_RISINGDETECT,Detect rising edge register" line.long 0x1C "GPIO_FALLINGDETECT,Detect falling edge register" line.long 0x20 "GPIO_DEBOUNCENABLE,Debouncing enable register" line.long 0x24 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x24 0.--7. 1. "DEBOUNCETIME,8-bit values specifying the debouncing time" group.long 0x190++0x07 line.long 0x00 "GPIO_CLEARDATAOUT,Clear data-output register" line.long 0x04 "GPIO_SETDATAOUT,Set data-output register" width 0x0B tree.end repeat.end tree "GPIO1_TARG" base ad:0x4AE11000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPIO2_TARG" base ad:0x48056000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPIO3_TARG" base ad:0x48058000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPIO4_TARG" base ad:0x4805A000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPMC" base ad:0x50000000 rgroup.long 0x00++0x03 line.long 0x00 "GPMC_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "GPMC_SYSCONFIG,This register controls the various parameters of the interconnect" hexmask.long 0x00 5.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 3.--4. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 2. "RESERVED,Write 0 for future compatibility Read returns 0" "0,1" newline bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOIDLE,Internal interface clock-gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "GPMC_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED,Read returns 0 (reserved for interconnect-socket status information)" newline bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0,RESETDONE_1" line.long 0x08 "GPMC_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x08 9. "WAIT1EDGEDETECTIONSTATUS,Status of the Wait1 Edge Detection interrupt" "WAIT1EDGEDETECTIONSTATUS_0_w,WAIT1EDGEDETECTIONSTATUS_1_w" newline bitfld.long 0x08 8. "WAIT0EDGEDETECTIONSTATUS,Status of the Wait0 Edge Detection interrupt" "WAIT0EDGEDETECTIONSTATUS_0_w,WAIT0EDGEDETECTIONSTATUS_1_w" newline bitfld.long 0x08 2.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 1. "TERMINALCOUNTSTATUS,Status of the TerminalCountEvent interrupt" "TERMINALCOUNTSTATUS_0_w,TERMINALCOUNTSTATUS_1_w" newline bitfld.long 0x08 0. "FIFOEVENTSTATUS,Status of the FIFOEvent interrupt" "FIFOEVENTSTATUS_0_w,FIFOEVENTSTATUS_1_w" line.long 0x0C "GPMC_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x0C 9. "WAIT1EDGEDETECTIONENABLE,Enables the Wait1 Edge Detection interrupt" "WAIT1EDGEDETECTIONENABLE_0,WAIT1EDGEDETECTIONENABLE_1" newline bitfld.long 0x0C 8. "WAIT0EDGEDETECTIONENABLE,Enables the Wait0 Edge Detection interrupt" "WAIT0EDGEDETECTIONENABLE_0,WAIT0EDGEDETECTIONENABLE_1" newline bitfld.long 0x0C 2.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 1. "TERMINALCOUNTEVENTENABLE,Enables TerminalCountEvent interrupt issuing in prefetch or write-posting mode" "TERMINALCOUNTEVENTENABLE_0,TERMINALCOUNTEVENTENABLE_1" newline bitfld.long 0x0C 0. "FIFOEVENTENABLE,Enables the FIFOEvent interrupt" "FIFOEVENTENABLE_0,FIFOEVENTENABLE_1" group.long 0x40++0x0B line.long 0x00 "GPMC_TIMEOUT_CONTROL,The register allows the user to set the start value of the timeout counter" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Write 0s for future compatibility" newline abitfld.long 0x00 4.--12. "TIMEOUTSTARTVALUE,Start value of the time-out counter" "0x000=Zero GPMC_FCLK cycle,0x001=One GPMC_FCLK cycle,0x1FF=511 GPMC_FCLK cycles" newline bitfld.long 0x00 1.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0. "TIMEOUTENABLE,Enable bit of the TimeOut feature" "TIMEOUTENABLE_0,TIMEOUTENABLE_1" line.long 0x04 "GPMC_ERR_ADDRESS,The register stores the address of the illegal access when an error occurs" bitfld.long 0x04 31. "RESERVED,Write 0s for future compatibility" "0,1" newline hexmask.long 0x04 0.--30. 1. "ILLEGALADD,Address of illegal access A30: 0 for memory region 1 for GPMC register region A29-A0: 1 GiB maximum" line.long 0x08 "GPMC_ERR_TYPE,The register stores the type of error when an error occurs" hexmask.long.tbyte 0x08 11.--31. 1. "RESERVED,Write 0s for future compatibility" newline rbitfld.long 0x08 8.--10. "ILLEGALMCMD,System command of the transaction that caused the error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 4. "ERRORNOTSUPPADD,Not supported address error" "ERRORNOTSUPPADD_0,ERRORNOTSUPPADD_1" newline rbitfld.long 0x08 3. "ERRORNOTSUPPMCMD,Not supported command error" "ERRORNOTSUPPMCMD_0,ERRORNOTSUPPMCMD_1" newline rbitfld.long 0x08 2. "ERRORTIMEOUT,Time-out error" "ERRORTIMEOUT_0,ERRORTIMEOUT_1" newline bitfld.long 0x08 1. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x08 0. "ERRORVALID,Error validity status - Must be explicitly cleared with a write 1 transaction" "ERRORVALID_0,ERRORVALID_1" group.long 0x50++0x07 line.long 0x00 "GPMC_CONFIG,The configuration register allows global configuration of the GPMC" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 9. "WAIT1PINPOLARITY,Selects the polarity of input pin WAIT1" "WAIT1PINPOLARITY_0,WAIT1PINPOLARITY_1" newline bitfld.long 0x00 8. "WAIT0PINPOLARITY,Selects the polarity of input pin WAIT0" "WAIT0PINPOLARITY_0,WAIT0PINPOLARITY_1" newline bitfld.long 0x00 2.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 1. "RESERVED,Write 0 for future compatibility" "0,1" newline bitfld.long 0x00 0. "NANDFORCEPOSTEDWRITE,Enables the Force Posted Write feature to NAND Cmd/Add/Data location" "NANDFORCEPOSTEDWRITE_0,NANDFORCEPOSTEDWRITE_1" line.long 0x04 "GPMC_STATUS,The status register provides global status bits of the GPMC" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Write 0s for future compatibility" newline rbitfld.long 0x04 9. "WAIT1STATUS,Is a copy of input pin WAIT1" "WAIT1STATUS_0,WAIT1STATUS_1" newline rbitfld.long 0x04 8. "WAIT0STATUS,Is a copy of input pin WAIT0" "WAIT0STATUS_0,WAIT0STATUS_1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED,Write 0s for future compatibility" newline rbitfld.long 0x04 0. "EMPTYWRITEBUFFERSTATUS,Stores the empty status of the write buffer" "EMPTYWRITEBUFFERSTATUS_0,EMPTYWRITEBUFFERSTATUS_1" group.long 0x60++0x03 line.long 0x00 "GPMC_CONFIG1_i_0,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" newline bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" newline bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" newline bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" newline bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" newline bitfld.long 0x00 20. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2 " "WAITPINSELECT_0,WAITPINSELECT_1,?,?" newline bitfld.long 0x00 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" newline bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" newline bitfld.long 0x00 2.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" group.long 0x90++0x03 line.long 0x00 "GPMC_CONFIG1_i_1,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" newline bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" newline bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" newline bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" newline bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" newline bitfld.long 0x00 20. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2 " "WAITPINSELECT_0,WAITPINSELECT_1,?,?" newline bitfld.long 0x00 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" newline bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" newline bitfld.long 0x00 2.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" group.long 0xC0++0x03 line.long 0x00 "GPMC_CONFIG1_i_2,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" newline bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" newline bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" newline bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" newline bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" newline bitfld.long 0x00 20. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2 " "WAITPINSELECT_0,WAITPINSELECT_1,?,?" newline bitfld.long 0x00 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" newline bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" newline bitfld.long 0x00 2.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" group.long 0xF0++0x03 line.long 0x00 "GPMC_CONFIG1_i_3,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" newline bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" newline bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" newline bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" newline bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" newline bitfld.long 0x00 20. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2 " "WAITPINSELECT_0,WAITPINSELECT_1,?,?" newline bitfld.long 0x00 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" newline bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" newline bitfld.long 0x00 2.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" group.long 0x120++0x03 line.long 0x00 "GPMC_CONFIG1_i_4,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" newline bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" newline bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" newline bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" newline bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" newline bitfld.long 0x00 20. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2 " "WAITPINSELECT_0,WAITPINSELECT_1,?,?" newline bitfld.long 0x00 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" newline bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" newline bitfld.long 0x00 2.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" group.long 0x150++0x03 line.long 0x00 "GPMC_CONFIG1_i_5,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" newline bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" newline bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" newline bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" newline bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" newline bitfld.long 0x00 20. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2 " "WAITPINSELECT_0,WAITPINSELECT_1,?,?" newline bitfld.long 0x00 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" newline bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" newline bitfld.long 0x00 2.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" group.long 0x180++0x03 line.long 0x00 "GPMC_CONFIG1_i_6,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" newline bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" newline bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" newline bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" newline bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" newline bitfld.long 0x00 20. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2 " "WAITPINSELECT_0,WAITPINSELECT_1,?,?" newline bitfld.long 0x00 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" newline bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" newline bitfld.long 0x00 2.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" group.long 0x1B0++0x03 line.long 0x00 "GPMC_CONFIG1_i_7,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" newline bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" newline bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" newline bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" newline bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" newline bitfld.long 0x00 20. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2 " "WAITPINSELECT_0,WAITPINSELECT_1,?,?" newline bitfld.long 0x00 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" newline bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" newline bitfld.long 0x00 2.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" group.long 0x64++0x03 line.long 0x00 "GPMC_CONFIG2_i_0,CS signal timing parameter configuration" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x94++0x03 line.long 0x00 "GPMC_CONFIG2_i_1,CS signal timing parameter configuration" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0xC4++0x03 line.long 0x00 "GPMC_CONFIG2_i_2,CS signal timing parameter configuration" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0xF4++0x03 line.long 0x00 "GPMC_CONFIG2_i_3,CS signal timing parameter configuration" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x124++0x03 line.long 0x00 "GPMC_CONFIG2_i_4,CS signal timing parameter configuration" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x154++0x03 line.long 0x00 "GPMC_CONFIG2_i_5,CS signal timing parameter configuration" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x184++0x03 line.long 0x00 "GPMC_CONFIG2_i_6,CS signal timing parameter configuration" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x1B4++0x03 line.long 0x00 "GPMC_CONFIG2_i_7,CS signal timing parameter configuration" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x68++0x03 line.long 0x00 "GPMC_CONFIG3_i_0,nADV signal timing parameter configuration" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x98++0x03 line.long 0x00 "GPMC_CONFIG3_i_1,nADV signal timing parameter configuration" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0xC8++0x03 line.long 0x00 "GPMC_CONFIG3_i_2,nADV signal timing parameter configuration" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0xF8++0x03 line.long 0x00 "GPMC_CONFIG3_i_3,nADV signal timing parameter configuration" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x128++0x03 line.long 0x00 "GPMC_CONFIG3_i_4,nADV signal timing parameter configuration" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x158++0x03 line.long 0x00 "GPMC_CONFIG3_i_5,nADV signal timing parameter configuration" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x188++0x03 line.long 0x00 "GPMC_CONFIG3_i_6,nADV signal timing parameter configuration" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x1B8++0x03 line.long 0x00 "GPMC_CONFIG3_i_7,nADV signal timing parameter configuration" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x6C++0x03 line.long 0x00 "GPMC_CONFIG4_i_0,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 29.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x9C++0x03 line.long 0x00 "GPMC_CONFIG4_i_1,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 29.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0xCC++0x03 line.long 0x00 "GPMC_CONFIG4_i_2,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 29.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0xFC++0x03 line.long 0x00 "GPMC_CONFIG4_i_3,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 29.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x12C++0x03 line.long 0x00 "GPMC_CONFIG4_i_4,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 29.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x15C++0x03 line.long 0x00 "GPMC_CONFIG4_i_5,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 29.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x18C++0x03 line.long 0x00 "GPMC_CONFIG4_i_6,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 29.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x1BC++0x03 line.long 0x00 "GPMC_CONFIG4_i_7,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 29.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x70++0x03 line.long 0x00 "GPMC_CONFIG5_i_0,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" group.long 0xA0++0x03 line.long 0x00 "GPMC_CONFIG5_i_1,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" group.long 0xD0++0x03 line.long 0x00 "GPMC_CONFIG5_i_2,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" group.long 0x100++0x03 line.long 0x00 "GPMC_CONFIG5_i_3,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" group.long 0x130++0x03 line.long 0x00 "GPMC_CONFIG5_i_4,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" group.long 0x160++0x03 line.long 0x00 "GPMC_CONFIG5_i_5,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" group.long 0x190++0x03 line.long 0x00 "GPMC_CONFIG5_i_6,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" group.long 0x1C0++0x03 line.long 0x00 "GPMC_CONFIG5_i_7,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" group.long 0x74++0x03 line.long 0x00 "GPMC_CONFIG6_i_0,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x00 29.--30. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 20.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x00 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" newline bitfld.long 0x00 4.--5. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0xA4++0x03 line.long 0x00 "GPMC_CONFIG6_i_1,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x00 29.--30. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 20.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x00 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" newline bitfld.long 0x00 4.--5. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0xD4++0x03 line.long 0x00 "GPMC_CONFIG6_i_2,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x00 29.--30. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 20.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x00 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" newline bitfld.long 0x00 4.--5. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x104++0x03 line.long 0x00 "GPMC_CONFIG6_i_3,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x00 29.--30. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 20.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x00 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" newline bitfld.long 0x00 4.--5. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x134++0x03 line.long 0x00 "GPMC_CONFIG6_i_4,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x00 29.--30. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 20.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x00 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" newline bitfld.long 0x00 4.--5. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x164++0x03 line.long 0x00 "GPMC_CONFIG6_i_5,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x00 29.--30. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 20.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x00 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" newline bitfld.long 0x00 4.--5. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x194++0x03 line.long 0x00 "GPMC_CONFIG6_i_6,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x00 29.--30. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 20.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x00 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" newline bitfld.long 0x00 4.--5. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x1C4++0x03 line.long 0x00 "GPMC_CONFIG6_i_7,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x00 29.--30. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 20.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x00 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" newline bitfld.long 0x00 4.--5. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x78++0x03 line.long 0x00 "GPMC_CONFIG7_i_0,CS address mapping configuration" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x00 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "GPMC_CONFIG7_i_1,CS address mapping configuration" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x00 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD8++0x03 line.long 0x00 "GPMC_CONFIG7_i_2,CS address mapping configuration" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x00 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x108++0x03 line.long 0x00 "GPMC_CONFIG7_i_3,CS address mapping configuration" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x00 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x138++0x03 line.long 0x00 "GPMC_CONFIG7_i_4,CS address mapping configuration" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x00 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x168++0x03 line.long 0x00 "GPMC_CONFIG7_i_5,CS address mapping configuration" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x00 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x198++0x03 line.long 0x00 "GPMC_CONFIG7_i_6,CS address mapping configuration" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x00 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C8++0x03 line.long 0x00 "GPMC_CONFIG7_i_7,CS address mapping configuration" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x00 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x7C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_0,This register is not a true register. only an address location" group.long 0xAC++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_1,This register is not a true register. only an address location" group.long 0xDC++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_2,This register is not a true register. only an address location" group.long 0x10C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_3,This register is not a true register. only an address location" group.long 0x13C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_4,This register is not a true register. only an address location" group.long 0x16C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_5,This register is not a true register. only an address location" group.long 0x19C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_6,This register is not a true register. only an address location" group.long 0x1CC++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_7,This register is not a true register. only an address location" group.long 0x80++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_0,This register is not a true register. only an address location" group.long 0xB0++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_1,This register is not a true register. only an address location" group.long 0xE0++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_2,This register is not a true register. only an address location" group.long 0x110++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_3,This register is not a true register. only an address location" group.long 0x140++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_4,This register is not a true register. only an address location" group.long 0x170++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_5,This register is not a true register. only an address location" group.long 0x1A0++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_6,This register is not a true register. only an address location" group.long 0x1D0++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_7,This register is not a true register. only an address location" group.long 0x84++0x03 line.long 0x00 "GPMC_NAND_DATA_i_0,This register is not a true register.only an address location" group.long 0xB4++0x03 line.long 0x00 "GPMC_NAND_DATA_i_1,This register is not a true register.only an address location" group.long 0xE4++0x03 line.long 0x00 "GPMC_NAND_DATA_i_2,This register is not a true register.only an address location" group.long 0x114++0x03 line.long 0x00 "GPMC_NAND_DATA_i_3,This register is not a true register.only an address location" group.long 0x144++0x03 line.long 0x00 "GPMC_NAND_DATA_i_4,This register is not a true register.only an address location" group.long 0x174++0x03 line.long 0x00 "GPMC_NAND_DATA_i_5,This register is not a true register.only an address location" group.long 0x1A4++0x03 line.long 0x00 "GPMC_NAND_DATA_i_6,This register is not a true register.only an address location" group.long 0x1D4++0x03 line.long 0x00 "GPMC_NAND_DATA_i_7,This register is not a true register.only an address location" group.long 0x1E0++0x07 line.long 0x00 "GPMC_PREFETCH_CONFIG1,Prefetch engine configuration 1" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "CYCLEOPTIMIZATION,Define the number of GPMC_FCLK cycles to be subtracted from RDCYCLETIME WRCYCLETIME RDACCESSTIME CSRDOFFTIME CSWROFFTIME ADVRDOFFTIME ADVWROFFTIME OEOFFTIME WEOFFTIME" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "ENABLEOPTIMIZEDACCESS,Enables access cycle optimization" "ENABLEOPTIMIZEDACCESS_0,ENABLEOPTIMIZEDACCESS_1" newline bitfld.long 0x00 24.--26. "ENGINECSSELECTOR,Selects the chip-select where Prefetch Postwrite engine is active" "CS0,CS1,CS2,CS3,CS4,CS5,CS6,CS7" newline bitfld.long 0x00 23. "PFPWENROUNDROBIN,Enables the PFPW RoundRobin arbitration" "PFPWENROUNDROBIN_0,PFPWENROUNDROBIN_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "PFPWWEIGHTEDPRIO,When an arbitration occurs between a DMA and a PFPW engine access the DMA is always serviced" "The next access is granted to the PFPW engine,The next two accesses are granted to the PFPW..,?,?,?,?,?,?,?,?,?,?,?,?,?,The next 16 accesses are granted to the PFPW.." newline bitfld.long 0x00 15. "RESERVED,Write 0s for future compatibility" "0,1" newline abitfld.long 0x00 8.--14. "FIFOTHRESHOLD,Selects the maximum number of bytes read from the FIFO or written to the FIFO by the host on a DMA or interrupt request" "0x00=0 byte,0x01=1 byte,0x40=64 bytes" newline bitfld.long 0x00 7. "ENABLEENGINE,Enables the Prefetch Postwite engine" "ENABLEENGINE_0,ENABLEENGINE_1" newline bitfld.long 0x00 6. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 4.--5. "WAITPINSELECTOR,Select which wait pin edge detector should start the engine in synchronized mode0x2 " "WAITPINSELECTOR_0,WAITPINSELECTOR_1,?,?" newline bitfld.long 0x00 3. "SYNCHROMODE,Selects when the engine starts the access to chip-select" "SYNCHROMODE_0,SYNCHROMODE_1" newline bitfld.long 0x00 2. "DMAMODE,Selects interrupt synchronization or DMA request synchronization" "DMAMODE_0,DMAMODE_1" newline bitfld.long 0x00 1. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 0. "ACCESSMODE,Selects prefetch read or write-posting accesses" "ACCESSMODE_0,ACCESSMODE_1" line.long 0x04 "GPMC_PREFETCH_CONFIG2,Prefetch engine configuration 2" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Write 0s for future compatibility" newline abitfld.long 0x04 0.--13. "TRANSFERCOUNT,Selects the number of bytes to be read or written by the engine to the selected chip-select" "0x0000=0 byte,0x0001=1 byte,0x2000=8 Kbytes" group.long 0x1EC++0x37 line.long 0x00 "GPMC_PREFETCH_CONTROL,Prefetch engine control" hexmask.long 0x00 1.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 0. "STARTENGINE,Resets the FIFO pointer and starts the engine" "STARTENGINE_0_w,STARTENGINE_1_w" line.long 0x04 "GPMC_PREFETCH_STATUS,Prefetch engine status" bitfld.long 0x04 31. "RESERVED,Write 0s for future compatibility" "0,1" newline abitfld.long 0x04 24.--30. "FIFOPOINTER,Number of available bytes to be read or number of free empty byte places to be written" "0x00=0 byte available to be read or 0 free empty..,0x40=64 bytes available to be read or 64 empty.." newline hexmask.long.byte 0x04 17.--23. 1. "RESERVED,Write 0s for future compatibility" newline rbitfld.long 0x04 16. "FIFOTHRESHOLDSTATUS,Set when FIFOPointer exceeds FIFOThreshold value" "FIFOTHRESHOLDSTATUS_0,FIFOTHRESHOLDSTATUS_1" newline bitfld.long 0x04 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline abitfld.long 0x04 0.--13. "COUNTVALUE,Number of remaining bytes to be read or to be written by the engine according to the TransferCount value" "0x0000=0 byte remaining to be read or to be..,0x0001=1 byte remaining to be read or to be..,0x2000=8 KiB remaining to be read or to be written" line.long 0x08 "GPMC_ECC_CONFIG,ECC configuration" hexmask.long.word 0x08 17.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x08 16. "ECCALGORITHM,ECC algorithm used" "ECCALGORITHM_0,ECCALGORITHM_1" newline bitfld.long 0x08 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x08 12.--13. "ECCBCHTSEL,Error correction capability used for BCH" "ECCBCHTSEL_0,ECCBCHTSEL_1,ECCBCHTSEL_2,ECCBCHTSEL_3" newline bitfld.long 0x08 8.--11. "ECCWRAPMODE,Spare area organization definition for the BCH algorithm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 7. "ECC16B,Selects an ECC calculated on 16 columns" "ECC16B_0,ECC16B_1" newline bitfld.long 0x08 4.--6. "ECCTOPSECTOR,Number of sectors to process with the BCH algorithm" "1 sector (512-kB page),2 sectors,?,4 sectors (2-kB page),?,?,?,8 sectors (4-kB page)" newline bitfld.long 0x08 1.--3. "ECCCS,Selects the CS where ECC is" "ECCCS_0,ECCCS_1,ECCCS_2,ECCCS_3,?,?,?,?" newline bitfld.long 0x08 0. "ECCENABLE,Enables the ECC feature" "ECCENABLE_0,ECCENABLE_1" line.long 0x0C "GPMC_ECC_CONTROL,ECC control" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x0C 8. "ECCCLEAR,Clear all ECC result registers Reads return 0" "0,1" newline bitfld.long 0x0C 4.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. "ECCPOINTER,Selects ECC result register (Reads to this field give the dynamic position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored.); Other enums: writing other values disables.." "ECCPOINTER_0,ECCPOINTER_1,ECCPOINTER_2,ECCPOINTER_3,ECCPOINTER_4,ECCPOINTER_5,ECCPOINTER_6,ECCPOINTER_7,ECCPOINTER_8,ECCPOINTER_9,?,?,?,?,?,?" line.long 0x10 "GPMC_ECC_SIZE_CONFIG,ECC size" bitfld.long 0x10 30.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline abitfld.long 0x10 22.--29. "ECCSIZE1,Defines Hamming code ECC size 1 in bytes" "0x00=2 bytes,0x01=4 bytes,0x02=6 bytes,0x03=8 bytes,0xFF=512 bytes For BCH.." newline bitfld.long 0x10 20.--21. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline abitfld.long 0x10 12.--19. "ECCSIZE0,Defines Hamming code ECC size 0 in bytes" "0x00=2 bytes,0x01=4 bytes,0x02=6 bytes,0x03=8 bytes,0xFF=512 bytes For BCH.." newline bitfld.long 0x10 9.--11. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "ECC9RESULTSIZE,Selects ECC size for ECC 9 result register" "ECC9RESULTSIZE_0,ECC9RESULTSIZE_1" newline bitfld.long 0x10 7. "ECC8RESULTSIZE,Selects ECC size for ECC 8 result register" "ECC8RESULTSIZE_0,ECC8RESULTSIZE_1" newline bitfld.long 0x10 6. "ECC7RESULTSIZE,Selects ECC size for ECC 7 result register" "ECC7RESULTSIZE_0,ECC7RESULTSIZE_1" newline bitfld.long 0x10 5. "ECC6RESULTSIZE,Selects ECC size for ECC 6 result register" "ECC6RESULTSIZE_0,ECC6RESULTSIZE_1" newline bitfld.long 0x10 4. "ECC5RESULTSIZE,Selects ECC size for ECC 5 result register" "ECC5RESULTSIZE_0,ECC5RESULTSIZE_1" newline bitfld.long 0x10 3. "ECC4RESULTSIZE,Selects ECC size for ECC 4 result register" "ECC4RESULTSIZE_0,ECC4RESULTSIZE_1" newline bitfld.long 0x10 2. "ECC3RESULTSIZE,Selects ECC size for ECC 3 result register" "ECC3RESULTSIZE_0,ECC3RESULTSIZE_1" newline bitfld.long 0x10 1. "ECC2RESULTSIZE,Selects ECC size for ECC 2 result register" "ECC2RESULTSIZE_0,ECC2RESULTSIZE_1" newline bitfld.long 0x10 0. "ECC1RESULTSIZE,Selects ECC size for ECC 1 result register" "ECC1RESULTSIZE_0,ECC1RESULTSIZE_1" line.long 0x14 "GPMC_ECCj_RESULT_0,ECC result register" bitfld.long 0x14 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x14 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x14 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x14 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x14 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x14 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x14 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x14 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x14 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x14 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x14 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x14 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x14 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x14 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x14 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x14 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x14 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x14 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x14 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x14 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x14 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x14 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x14 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x14 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x14 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x14 0. "P1E,Even column parity bit 1" "0,1" line.long 0x18 "GPMC_ECCj_RESULT_1,ECC result register" bitfld.long 0x18 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x18 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x18 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x18 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x18 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x18 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x18 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x18 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x18 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x18 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x18 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x18 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x18 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x18 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x18 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x18 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x18 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x18 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x18 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x18 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x18 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x18 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x18 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x18 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x18 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x18 0. "P1E,Even column parity bit 1" "0,1" line.long 0x1C "GPMC_ECCj_RESULT_2,ECC result register" bitfld.long 0x1C 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x1C 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x1C 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x1C 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x1C 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x1C 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x1C 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x1C 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x1C 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x1C 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x1C 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x1C 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x1C 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x1C 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x1C 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x1C 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x1C 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x1C 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x1C 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x1C 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x1C 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x1C 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x1C 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x1C 0. "P1E,Even column parity bit 1" "0,1" line.long 0x20 "GPMC_ECCj_RESULT_3,ECC result register" bitfld.long 0x20 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x20 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x20 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x20 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x20 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x20 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x20 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x20 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x20 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x20 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x20 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x20 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x20 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x20 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x20 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x20 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x20 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x20 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x20 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x20 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x20 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x20 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x20 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x20 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x20 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x20 0. "P1E,Even column parity bit 1" "0,1" line.long 0x24 "GPMC_ECCj_RESULT_4,ECC result register" bitfld.long 0x24 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x24 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x24 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x24 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x24 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x24 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x24 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x24 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x24 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x24 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x24 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x24 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x24 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x24 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x24 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x24 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x24 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x24 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x24 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x24 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x24 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x24 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x24 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x24 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x24 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x24 0. "P1E,Even column parity bit 1" "0,1" line.long 0x28 "GPMC_ECCj_RESULT_5,ECC result register" bitfld.long 0x28 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x28 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x28 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x28 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x28 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x28 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x28 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x28 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x28 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x28 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x28 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x28 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x28 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x28 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x28 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x28 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x28 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x28 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x28 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x28 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x28 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x28 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x28 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x28 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x28 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x28 0. "P1E,Even column parity bit 1" "0,1" line.long 0x2C "GPMC_ECCj_RESULT_6,ECC result register" bitfld.long 0x2C 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x2C 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x2C 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x2C 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x2C 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x2C 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x2C 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x2C 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x2C 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x2C 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x2C 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x2C 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x2C 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x2C 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x2C 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x2C 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x2C 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x2C 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x2C 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x2C 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x2C 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x2C 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x2C 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x2C 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x2C 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x2C 0. "P1E,Even column parity bit 1" "0,1" line.long 0x30 "GPMC_ECCj_RESULT_7,ECC result register" bitfld.long 0x30 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x30 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x30 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x30 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x30 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x30 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x30 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x30 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x30 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x30 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x30 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x30 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x30 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x30 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x30 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x30 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x30 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x30 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x30 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x30 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x30 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x30 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x30 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x30 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x30 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x30 0. "P1E,Even column parity bit 1" "0,1" line.long 0x34 "GPMC_ECCj_RESULT_8,ECC result register" bitfld.long 0x34 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x34 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x34 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x34 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x34 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x34 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x34 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x34 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x34 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x34 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x34 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x34 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x34 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x34 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x34 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x34 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x34 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x34 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x34 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x34 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x34 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x34 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x34 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x34 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x34 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x34 0. "P1E,Even column parity bit 1" "0,1" group.long 0x240++0x03 line.long 0x00 "GPMC_BCH_RESULT0_i_0,BCH ECC result (bits 0 to 31)" group.long 0x250++0x03 line.long 0x00 "GPMC_BCH_RESULT0_i_1,BCH ECC result (bits 0 to 31)" group.long 0x260++0x03 line.long 0x00 "GPMC_BCH_RESULT0_i_2,BCH ECC result (bits 0 to 31)" group.long 0x270++0x03 line.long 0x00 "GPMC_BCH_RESULT0_i_3,BCH ECC result (bits 0 to 31)" group.long 0x280++0x03 line.long 0x00 "GPMC_BCH_RESULT0_i_4,BCH ECC result (bits 0 to 31)" group.long 0x290++0x03 line.long 0x00 "GPMC_BCH_RESULT0_i_5,BCH ECC result (bits 0 to 31)" group.long 0x2A0++0x03 line.long 0x00 "GPMC_BCH_RESULT0_i_6,BCH ECC result (bits 0 to 31)" group.long 0x2B0++0x03 line.long 0x00 "GPMC_BCH_RESULT0_i_7,BCH ECC result (bits 0 to 31)" group.long 0x244++0x03 line.long 0x00 "GPMC_BCH_RESULT1_i_0,BCH ECC result (bits 32 to 63)" group.long 0x254++0x03 line.long 0x00 "GPMC_BCH_RESULT1_i_1,BCH ECC result (bits 32 to 63)" group.long 0x264++0x03 line.long 0x00 "GPMC_BCH_RESULT1_i_2,BCH ECC result (bits 32 to 63)" group.long 0x274++0x03 line.long 0x00 "GPMC_BCH_RESULT1_i_3,BCH ECC result (bits 32 to 63)" group.long 0x284++0x03 line.long 0x00 "GPMC_BCH_RESULT1_i_4,BCH ECC result (bits 32 to 63)" group.long 0x294++0x03 line.long 0x00 "GPMC_BCH_RESULT1_i_5,BCH ECC result (bits 32 to 63)" group.long 0x2A4++0x03 line.long 0x00 "GPMC_BCH_RESULT1_i_6,BCH ECC result (bits 32 to 63)" group.long 0x2B4++0x03 line.long 0x00 "GPMC_BCH_RESULT1_i_7,BCH ECC result (bits 32 to 63)" group.long 0x248++0x03 line.long 0x00 "GPMC_BCH_RESULT2_i_0,BCH ECC result (bits 64 to 95)" group.long 0x258++0x03 line.long 0x00 "GPMC_BCH_RESULT2_i_1,BCH ECC result (bits 64 to 95)" group.long 0x268++0x03 line.long 0x00 "GPMC_BCH_RESULT2_i_2,BCH ECC result (bits 64 to 95)" group.long 0x278++0x03 line.long 0x00 "GPMC_BCH_RESULT2_i_3,BCH ECC result (bits 64 to 95)" group.long 0x288++0x03 line.long 0x00 "GPMC_BCH_RESULT2_i_4,BCH ECC result (bits 64 to 95)" group.long 0x298++0x03 line.long 0x00 "GPMC_BCH_RESULT2_i_5,BCH ECC result (bits 64 to 95)" group.long 0x2A8++0x03 line.long 0x00 "GPMC_BCH_RESULT2_i_6,BCH ECC result (bits 64 to 95)" group.long 0x2B8++0x03 line.long 0x00 "GPMC_BCH_RESULT2_i_7,BCH ECC result (bits 64 to 95)" group.long 0x24C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_i_0,BCH ECC result (bits 96 to 127)" group.long 0x25C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_i_1,BCH ECC result (bits 96 to 127)" group.long 0x26C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_i_2,BCH ECC result (bits 96 to 127)" group.long 0x27C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_i_3,BCH ECC result (bits 96 to 127)" group.long 0x28C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_i_4,BCH ECC result (bits 96 to 127)" group.long 0x29C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_i_5,BCH ECC result (bits 96 to 127)" group.long 0x2AC++0x03 line.long 0x00 "GPMC_BCH_RESULT3_i_6,BCH ECC result (bits 96 to 127)" group.long 0x2BC++0x03 line.long 0x00 "GPMC_BCH_RESULT3_i_7,BCH ECC result (bits 96 to 127)" group.long 0x2D0++0x03 line.long 0x00 "GPMC_BCH_SWDATA,This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND flash interface" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_DATA,Data to be included in the BCH calculation Only bits 0 to 7 are considered if the calculator is configured to use 8-bit data (GPMC_ECC_CONFIG[7] ECC16B = 0)" group.long 0x300++0x03 line.long 0x00 "GPMC_BCH_RESULT4_i_0,BCH ECC result (bits 128 to 159)" group.long 0x310++0x03 line.long 0x00 "GPMC_BCH_RESULT4_i_1,BCH ECC result (bits 128 to 159)" group.long 0x320++0x03 line.long 0x00 "GPMC_BCH_RESULT4_i_2,BCH ECC result (bits 128 to 159)" group.long 0x330++0x03 line.long 0x00 "GPMC_BCH_RESULT4_i_3,BCH ECC result (bits 128 to 159)" group.long 0x340++0x03 line.long 0x00 "GPMC_BCH_RESULT4_i_4,BCH ECC result (bits 128 to 159)" group.long 0x350++0x03 line.long 0x00 "GPMC_BCH_RESULT4_i_5,BCH ECC result (bits 128 to 159)" group.long 0x360++0x03 line.long 0x00 "GPMC_BCH_RESULT4_i_6,BCH ECC result (bits 128 to 159)" group.long 0x370++0x03 line.long 0x00 "GPMC_BCH_RESULT4_i_7,BCH ECC result (bits 128 to 159)" group.long 0x304++0x03 line.long 0x00 "GPMC_BCH_RESULT5_i_0,BCH ECC result (bits 160 to 191)" group.long 0x314++0x03 line.long 0x00 "GPMC_BCH_RESULT5_i_1,BCH ECC result (bits 160 to 191)" group.long 0x324++0x03 line.long 0x00 "GPMC_BCH_RESULT5_i_2,BCH ECC result (bits 160 to 191)" group.long 0x334++0x03 line.long 0x00 "GPMC_BCH_RESULT5_i_3,BCH ECC result (bits 160 to 191)" group.long 0x344++0x03 line.long 0x00 "GPMC_BCH_RESULT5_i_4,BCH ECC result (bits 160 to 191)" group.long 0x354++0x03 line.long 0x00 "GPMC_BCH_RESULT5_i_5,BCH ECC result (bits 160 to 191)" group.long 0x364++0x03 line.long 0x00 "GPMC_BCH_RESULT5_i_6,BCH ECC result (bits 160 to 191)" group.long 0x374++0x03 line.long 0x00 "GPMC_BCH_RESULT5_i_7,BCH ECC result (bits 160 to 191)" group.long 0x308++0x03 line.long 0x00 "GPMC_BCH_RESULT6_i_0,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x318++0x03 line.long 0x00 "GPMC_BCH_RESULT6_i_1,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x328++0x03 line.long 0x00 "GPMC_BCH_RESULT6_i_2,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x338++0x03 line.long 0x00 "GPMC_BCH_RESULT6_i_3,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x348++0x03 line.long 0x00 "GPMC_BCH_RESULT6_i_4,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x358++0x03 line.long 0x00 "GPMC_BCH_RESULT6_i_5,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x368++0x03 line.long 0x00 "GPMC_BCH_RESULT6_i_6,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x378++0x03 line.long 0x00 "GPMC_BCH_RESULT6_i_7,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" width 0x0B tree.end tree "GPMC_FW" base ad:0x4A210000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "GPMC_FW_CFG_TARG" base ad:0x4A211000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPMC_TARG" base ad:0x44000100 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "GPU_CM_CORE" base ad:0x4A009200 group.long 0x00++0x0B line.long 0x00 "CM_GPU_CLKSTCTRL,This register enables the GPU domain power state transition" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," rbitfld.long 0x00 10. "CLKACTIVITY_GPU_HYD_GCLK,This field indicates the state of the GPU_HYD_GCLK clock in the domain" "CLKACTIVITY_GPU_HYD_GCLK_0,CLKACTIVITY_GPU_HYD_GCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_GPU_CORE_GCLK,This field indicates the state of the GPU_CORE_GCLK clock in the domain" "CLKACTIVITY_GPU_CORE_GCLK_0,CLKACTIVITY_GPU_CORE_GCLK_1" rbitfld.long 0x00 8. "CLKACTIVITY_GPU_L3_GICLK,This field indicates the state of the GPU_L3_GICLK clock in the domain" "CLKACTIVITY_GPU_L3_GICLK_0,CLKACTIVITY_GPU_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the GPU clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_GPU_STATICDEP,This register controls the static domain depedencies from GPU domain towards 'target' domains" hexmask.long 0x04 6.--31. 1. "RESERVED," rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" line.long 0x08 "CM_GPU_DYNAMICDEP,This register controls the dynamic domain depedencies from GPU domain towards 'target' domains" hexmask.long 0x08 7.--31. 1. "RESERVED," bitfld.long 0x08 6. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "L3MAIN1_DYNDEP_0,?" newline bitfld.long 0x08 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x20++0x03 line.long 0x00 "CM_GPU_GPU_CLKCTRL,This register manages the GPU clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 26.--27. "CLKSEL_HYD_CLK,Select the source of the functional clock" "CLKSEL_HYD_CLK_0,CLKSEL_HYD_CLK_1,CLKSEL_HYD_CLK_2,CLKSEL_HYD_CLK_3" newline bitfld.long 0x00 24.--25. "CLKSEL_CORE_CLK,Select the source of the functional clock" "CLKSEL_CORE_CLK_0,CLKSEL_CORE_CLK_1,CLKSEL_CORE_CLK_2,CLKSEL_CORE_CLK_3" rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "GPU_PRM" base ad:0x4AE07200 group.long 0x00++0x07 line.long 0x00 "PM_GPU_PWRSTCTRL,This register controls the GPU power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "GPU_MEM_ONSTATE,GPU_MEM memory bank state when domain is ON" "?,?,?,GPU_MEM_ONSTATE_3" hexmask.long.word 0x00 5.--15. 1. "RESERVED," newline bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_GPU_PWRSTST,This register provides a status on the current GPU power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "GPU_MEM_STATEST,GPU_MEM memory bank state status" "GPU_MEM_STATEST_0,GPU_MEM_STATEST_1,GPU_MEM_STATEST_2,GPU_MEM_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_GPU_GPU_CONTEXT,This register contains dedicated GPU context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_GPU_MEM,Specify if memory-based context in GPU_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_GPU_MEM_0,LOSTMEM_GPU_MEM_1" hexmask.long.byte 0x00 1.--7. 1. "RESERVED," newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "HWSEQ" base ad:0x52020000 group.long 0x68++0x1B line.long 0x00 "SIMCOP_HWSEQ_CTRL,SIMCOP HW sequencer control register" hexmask.long.word 0x00 16.--31. 1. "HW_SEQ_STEP_COUNTER,Number of steps executed by the HW sequencer" bitfld.long 0x00 15. "BBM_LDC,This bit field is reserved and users should write the reset value to this bit location" "BBM_LDC_0,BBM_LDC_1" rbitfld.long 0x00 13.--14. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" newline bitfld.long 0x00 11.--12. "STEP,This register is automatically updated by the HW sequencer when it is active" "0,1,2,3" bitfld.long 0x00 10. "CPU_PROC_DONE,Used by the CPU to tell that it has completed data processing" "CPU_PROC_DONE_0,CPU_PROC_DONE_1" bitfld.long 0x00 8.--9. "BBM_SYNC_CHAN,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" newline rbitfld.long 0x00 7. "BBM_STATUS,This bit field is reserved and users should write the reset value to this bit location" "BBM_STATUS_0,BBM_STATUS_1" bitfld.long 0x00 4.--6. "BITSTREAM,This bit field is reserved and users should write the reset value to this bit location" "BITSTREAM_0,BITSTREAM_1,BITSTREAM_2,BITSTREAM_3,BITSTREAM_4,BITSTREAM_5,BITSTREAM_6,?" bitfld.long 0x00 2.--3. "BITSTR_XFER_SIZE,This bit field is reserved and users should write the reset value to this bit location" "BITSTR_XFER_SIZE_0,BITSTR_XFER_SIZE_1,BITSTR_XFER_SIZE_2,BITSTR_XFER_SIZE_3" newline bitfld.long 0x00 1. "HW_SEQ_STOP,Stop the HW sequencer" "HW_SEQ_STOP_0,HW_SEQ_STOP_1" bitfld.long 0x00 0. "HW_SEQ_START,Start the HW sequencer" "HW_SEQ_START_0,HW_SEQ_START_1" line.long 0x04 "SIMCOP_HWSEQ_STATUS,HW sequencer status register" hexmask.long.word 0x04 16.--31. 1. "HW_SEQ_STEP_COUNTER,Current step number" hexmask.long.word 0x04 1.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x04 0. "STATE,Current state" "STATE_0,STATE_1" line.long 0x08 "SIMCOP_HWSEQ_OVERRIDE,HW sequencer override control register" hexmask.long.word 0x08 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x08 19. "VTNF_IO_OFST_OVR," "0,1" bitfld.long 0x08 18. "COEFF_B,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x08 17. "COEFF_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 16. "IMBUFF_H," "0,1" bitfld.long 0x08 15. "IMBUFF_G," "0,1" newline bitfld.long 0x08 14. "IMBUFF_F," "0,1" bitfld.long 0x08 13. "IMBUFF_E," "0,1" bitfld.long 0x08 12. "IMBUFF_D,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x08 11. "IMBUFF_C,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 10. "IMBUFF_B,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 9. "IMBUFF_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x08 8. "LDC_O_OFST_OVR," "0,1" bitfld.long 0x08 7. "ROT_O_OFST_OVR,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 6. "ROT_I_OFST_OVR,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x08 5. "NSF_IO_OFST_OVR,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 4. "DCT_F_OFST_OVR,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 3. "DCT_S_OFST_OVR,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x08 2. "VLCDJ_IO_OFST_OVR,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 1. "IMX_B_D_OFST_OVR,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 0. "IMX_A_D_OFST_OVR,This bit field is reserved and users should write the reset value to this bit location" "0,1" line.long 0x0C "SIMCOP_HWSEQ_STEP_CTRL_OVERRIDE,HW sequencer override register" rbitfld.long 0x0C 28.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 26.--27. "ROT_O_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_O_OFST_0,ROT_O_OFST_1,ROT_O_OFST_2,ROT_O_OFST_3" bitfld.long 0x0C 24.--25. "ROT_I_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_I_OFST_0,ROT_I_OFST_1,ROT_I_OFST_2,ROT_I_OFST_3" newline rbitfld.long 0x0C 23. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x0C 20.--22. "DCT_F_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_F_OFST_0,DCT_F_OFST_1,DCT_F_OFST_2,DCT_F_OFST_3,DCT_F_OFST_4,DCT_F_OFST_5,?,?" bitfld.long 0x0C 18.--19. "DCT_S_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_S_OFST_0,DCT_S_OFST_1,DCT_S_OFST_2,DCT_S_OFST_3" newline bitfld.long 0x0C 15.--17. "VLCDJ_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_IO_OFST_0,VLCDJ_IO_OFST_1,VLCDJ_IO_OFST_2,VLCDJ_IO_OFST_3,VLCDJ_IO_OFST_4,VLCDJ_IO_OFST_5,?,?" bitfld.long 0x0C 13.--14. "IMX_B_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_D_OFST_0,IMX_B_D_OFST_1,IMX_B_D_OFST_2,IMX_B_D_OFST_3" bitfld.long 0x0C 11.--12. "IMX_A_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_D_OFST_0,IMX_A_D_OFST_1,IMX_A_D_OFST_2,IMX_A_D_OFST_3" newline rbitfld.long 0x0C 9.--10. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x0C 8. "VTNF_TRIGGER,SW controlled START/DONE synchronization" "VTNF_TRIGGER_0,VTNF_TRIGGER_1" bitfld.long 0x0C 5.--7. "DMA_TRIGGER,SW controlled START/DONE synchronization" "DMA_TRIGGER_0,DMA_TRIGGER_1,DMA_TRIGGER_2,DMA_TRIGGER_3,DMA_TRIGGER_4,DMA_TRIGGER_5,DMA_TRIGGER_6,DMA_TRIGGER_7" newline bitfld.long 0x0C 4. "ROT_A_TRIGGER,This bit field is reserved and users should write the reset value to this bit location" "ROT_A_TRIGGER_0,ROT_A_TRIGGER_1" bitfld.long 0x0C 3. "NSF_TRIGGER,This bit field is reserved and users should write the reset value to this bit location" "NSF_TRIGGER_0,NSF_TRIGGER_1" bitfld.long 0x0C 2. "VLCDJ_TRIGGER,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_TRIGGER_0,VLCDJ_TRIGGER_1" newline bitfld.long 0x0C 1. "DCT_TRIGGER,This bit field is reserved and users should write the reset value to this bit location" "DCT_TRIGGER_0,DCT_TRIGGER_1" bitfld.long 0x0C 0. "LDC_TRIGGER,SW controlled START/DONE synchronization" "LDC_TRIGGER_0,LDC_TRIGGER_1" line.long 0x10 "SIMCOP_HWSEQ_STEP_SWITCH_OVERRIDE,HW sequencer override register" bitfld.long 0x10 28.--31. "IMBUFF_H,Switch for image buffer #h" "IMBUFF_H_0,IMBUFF_H_1,?,?,?,?,?,?,?,IMBUFF_H_9,IMBUFF_H_10,?,?,?,?,?" bitfld.long 0x10 24.--27. "IMBUFF_G,Switch for image buffer #g" "IMBUFF_G_0,IMBUFF_G_1,?,?,?,?,?,?,?,IMBUFF_G_9,IMBUFF_G_10,?,?,?,?,?" bitfld.long 0x10 20.--23. "IMBUFF_F,Switch for image buffer #f" "IMBUFF_F_0,IMBUFF_F_1,?,?,?,?,IMBUFF_F_6,?,IMBUFF_F_8,?,?,?,?,?,?,?" newline bitfld.long 0x10 16.--19. "IMBUFF_E,Switch for image buffer #e" "IMBUFF_E_0,IMBUFF_E_1,?,?,?,?,IMBUFF_E_6,?,IMBUFF_E_8,?,?,?,?,?,?,?" rbitfld.long 0x10 15. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x10 12.--14. "IMBUFF_D,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_D_0,IMBUFF_D_1,IMBUFF_D_2,IMBUFF_D_3,IMBUFF_D_4,IMBUFF_D_5,IMBUFF_D_6,IMBUFF_D_7" newline rbitfld.long 0x10 11. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x10 8.--10. "IMBUFF_C,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_C_0,IMBUFF_C_1,IMBUFF_C_2,IMBUFF_C_3,IMBUFF_C_4,IMBUFF_C_5,IMBUFF_C_6,IMBUFF_C_7" rbitfld.long 0x10 7. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x10 4.--6. "IMBUFF_B,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_B_0,IMBUFF_B_1,IMBUFF_B_2,IMBUFF_B_3,IMBUFF_B_4,IMBUFF_B_5,IMBUFF_B_6,IMBUFF_B_7" rbitfld.long 0x10 3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x10 0.--2. "IMBUFF_A,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_A_0,IMBUFF_A_1,IMBUFF_A_2,IMBUFF_A_3,IMBUFF_A_4,IMBUFF_A_5,IMBUFF_A_6,IMBUFF_A_7" line.long 0x14 "SIMCOP_HWSEQ_STEP_CTRL2_OVERRIDE,HW sequencer override register" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x14 12.--13. "VTNF_IO_OFST,Controls VTNF_IO bus mapping to image buffers: 0x0000 0x1000" "VTNF_IO_OFST_0,VTNF_IO_OFST_1,VTNF_IO_OFST_2,VTNF_IO_OFST_3" bitfld.long 0x14 10.--11. "NSF2_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "NSF2_IO_OFST_0,NSF2_IO_OFST_1,NSF2_IO_OFST_2,NSF2_IO_OFST_3" newline bitfld.long 0x14 8.--9. "LDC_O_OFST,Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000" "LDC_O_OFST_0,LDC_O_OFST_1,LDC_O_OFST_2,LDC_O_OFST_3" rbitfld.long 0x14 7. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x14 4.--6. "COEFF_B,This bit field is reserved and users should write the reset value to this bit location" "COEFF_B_0,COEFF_B_1,COEFF_B_2,COEFF_B_3,COEFF_B_4,COEFF_B_5,COEFF_B_6,COEFF_B_7" newline rbitfld.long 0x14 3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x14 0.--2. "COEFF_A,This bit field is reserved and users should write the reset value to this bit location" "COEFF_A_0,COEFF_A_1,COEFF_A_2,COEFF_A_3,COEFF_A_4,COEFF_A_5,COEFF_A_6,COEFF_A_7" line.long 0x18 "SIMCOP_HWSEQ_STEP_CTRL_i_0,HW sequencer step control register" bitfld.long 0x18 31. "CPU_SYNC,Enable HW synchronization with the CPU so that it could be used for some processing on in the macro-block pipeline" "CPU_SYNC_0,CPU_SYNC_1" bitfld.long 0x18 28.--30. "DMA_OFST,Controls DMA bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000" "DMA_OFST_0,DMA_OFST_1,DMA_OFST_2,DMA_OFST_3,DMA_OFST_4,DMA_OFST_5,DMA_OFST_6,DMA_OFST_7" bitfld.long 0x18 26.--27. "ROT_O_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_O_OFST_0,ROT_O_OFST_1,ROT_O_OFST_2,ROT_O_OFST_3" newline bitfld.long 0x18 24.--25. "ROT_I_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_I_OFST_0,ROT_I_OFST_1,ROT_I_OFST_2,ROT_I_OFST_3" bitfld.long 0x18 23. "EXT_SYNC,The HW sequencer waits for an external start pulse i(START_STEP signal) n addition to internally selected synchronization events" "0,1" bitfld.long 0x18 20.--22. "DCT_F_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_F_OFST_0,DCT_F_OFST_1,DCT_F_OFST_2,DCT_F_OFST_3,DCT_F_OFST_4,DCT_F_OFST_5,?,?" newline bitfld.long 0x18 18.--19. "DCT_S_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_S_OFST_0,DCT_S_OFST_1,DCT_S_OFST_2,DCT_S_OFST_3" bitfld.long 0x18 15.--17. "VLCDJ_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_IO_OFST_0,VLCDJ_IO_OFST_1,VLCDJ_IO_OFST_2,VLCDJ_IO_OFST_3,VLCDJ_IO_OFST_4,VLCDJ_IO_OFST_5,?,?" bitfld.long 0x18 13.--14. "IMX_B_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_D_OFST_0,IMX_B_D_OFST_1,IMX_B_D_OFST_2,IMX_B_D_OFST_3" newline bitfld.long 0x18 11.--12. "IMX_A_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_D_OFST_0,IMX_A_D_OFST_1,IMX_A_D_OFST_2,IMX_A_D_OFST_3" bitfld.long 0x18 9.--10. "NEXT,Next channel in the sync chain" "NEXT_0,NEXT_1,NEXT_2,NEXT_3" bitfld.long 0x18 8. "VTNF_SYNC,Enable HW synchronization with the VTNF module" "VTNF_SYNC_0,VTNF_SYNC_1" newline bitfld.long 0x18 5.--7. "DMA_SYNC,Enable HW synchronization with the SIMCOP DMA" "DMA_SYNC_0,DMA_SYNC_1,DMA_SYNC_2,DMA_SYNC_3,DMA_SYNC_4,DMA_SYNC_5,DMA_SYNC_6,DMA_SYNC_7" bitfld.long 0x18 4. "ROT_A_SYNC,This bit field is reserved and users should write the reset value to this bit location" "ROT_A_SYNC_0,ROT_A_SYNC_1" bitfld.long 0x18 3. "NSF_SYNC,This bit field is reserved and users should write the reset value to this bit location" "NSF_SYNC_0,NSF_SYNC_1" newline bitfld.long 0x18 2. "VLCDJ_SYNC,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_SYNC_0,VLCDJ_SYNC_1" bitfld.long 0x18 1. "DCT_SYNC,Enable HW synchronization with the DCT module" "DCT_SYNC_0,DCT_SYNC_1" bitfld.long 0x18 0. "LDC_SYNC,Enable HW synchronization with the LDC module" "LDC_SYNC_0,LDC_SYNC_1" group.long 0x90++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL_i_1,HW sequencer step control register" bitfld.long 0x00 31. "CPU_SYNC,Enable HW synchronization with the CPU so that it could be used for some processing on in the macro-block pipeline" "CPU_SYNC_0,CPU_SYNC_1" bitfld.long 0x00 28.--30. "DMA_OFST,Controls DMA bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000" "DMA_OFST_0,DMA_OFST_1,DMA_OFST_2,DMA_OFST_3,DMA_OFST_4,DMA_OFST_5,DMA_OFST_6,DMA_OFST_7" bitfld.long 0x00 26.--27. "ROT_O_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_O_OFST_0,ROT_O_OFST_1,ROT_O_OFST_2,ROT_O_OFST_3" newline bitfld.long 0x00 24.--25. "ROT_I_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_I_OFST_0,ROT_I_OFST_1,ROT_I_OFST_2,ROT_I_OFST_3" bitfld.long 0x00 23. "EXT_SYNC,The HW sequencer waits for an external start pulse i(START_STEP signal) n addition to internally selected synchronization events" "0,1" bitfld.long 0x00 20.--22. "DCT_F_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_F_OFST_0,DCT_F_OFST_1,DCT_F_OFST_2,DCT_F_OFST_3,DCT_F_OFST_4,DCT_F_OFST_5,?,?" newline bitfld.long 0x00 18.--19. "DCT_S_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_S_OFST_0,DCT_S_OFST_1,DCT_S_OFST_2,DCT_S_OFST_3" bitfld.long 0x00 15.--17. "VLCDJ_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_IO_OFST_0,VLCDJ_IO_OFST_1,VLCDJ_IO_OFST_2,VLCDJ_IO_OFST_3,VLCDJ_IO_OFST_4,VLCDJ_IO_OFST_5,?,?" bitfld.long 0x00 13.--14. "IMX_B_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_D_OFST_0,IMX_B_D_OFST_1,IMX_B_D_OFST_2,IMX_B_D_OFST_3" newline bitfld.long 0x00 11.--12. "IMX_A_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_D_OFST_0,IMX_A_D_OFST_1,IMX_A_D_OFST_2,IMX_A_D_OFST_3" bitfld.long 0x00 9.--10. "NEXT,Next channel in the sync chain" "NEXT_0,NEXT_1,NEXT_2,NEXT_3" bitfld.long 0x00 8. "VTNF_SYNC,Enable HW synchronization with the VTNF module" "VTNF_SYNC_0,VTNF_SYNC_1" newline bitfld.long 0x00 5.--7. "DMA_SYNC,Enable HW synchronization with the SIMCOP DMA" "DMA_SYNC_0,DMA_SYNC_1,DMA_SYNC_2,DMA_SYNC_3,DMA_SYNC_4,DMA_SYNC_5,DMA_SYNC_6,DMA_SYNC_7" bitfld.long 0x00 4. "ROT_A_SYNC,This bit field is reserved and users should write the reset value to this bit location" "ROT_A_SYNC_0,ROT_A_SYNC_1" bitfld.long 0x00 3. "NSF_SYNC,This bit field is reserved and users should write the reset value to this bit location" "NSF_SYNC_0,NSF_SYNC_1" newline bitfld.long 0x00 2. "VLCDJ_SYNC,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_SYNC_0,VLCDJ_SYNC_1" bitfld.long 0x00 1. "DCT_SYNC,Enable HW synchronization with the DCT module" "DCT_SYNC_0,DCT_SYNC_1" bitfld.long 0x00 0. "LDC_SYNC,Enable HW synchronization with the LDC module" "LDC_SYNC_0,LDC_SYNC_1" group.long 0xA0++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL_i_2,HW sequencer step control register" bitfld.long 0x00 31. "CPU_SYNC,Enable HW synchronization with the CPU so that it could be used for some processing on in the macro-block pipeline" "CPU_SYNC_0,CPU_SYNC_1" bitfld.long 0x00 28.--30. "DMA_OFST,Controls DMA bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000" "DMA_OFST_0,DMA_OFST_1,DMA_OFST_2,DMA_OFST_3,DMA_OFST_4,DMA_OFST_5,DMA_OFST_6,DMA_OFST_7" bitfld.long 0x00 26.--27. "ROT_O_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_O_OFST_0,ROT_O_OFST_1,ROT_O_OFST_2,ROT_O_OFST_3" newline bitfld.long 0x00 24.--25. "ROT_I_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_I_OFST_0,ROT_I_OFST_1,ROT_I_OFST_2,ROT_I_OFST_3" bitfld.long 0x00 23. "EXT_SYNC,The HW sequencer waits for an external start pulse i(START_STEP signal) n addition to internally selected synchronization events" "0,1" bitfld.long 0x00 20.--22. "DCT_F_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_F_OFST_0,DCT_F_OFST_1,DCT_F_OFST_2,DCT_F_OFST_3,DCT_F_OFST_4,DCT_F_OFST_5,?,?" newline bitfld.long 0x00 18.--19. "DCT_S_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_S_OFST_0,DCT_S_OFST_1,DCT_S_OFST_2,DCT_S_OFST_3" bitfld.long 0x00 15.--17. "VLCDJ_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_IO_OFST_0,VLCDJ_IO_OFST_1,VLCDJ_IO_OFST_2,VLCDJ_IO_OFST_3,VLCDJ_IO_OFST_4,VLCDJ_IO_OFST_5,?,?" bitfld.long 0x00 13.--14. "IMX_B_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_D_OFST_0,IMX_B_D_OFST_1,IMX_B_D_OFST_2,IMX_B_D_OFST_3" newline bitfld.long 0x00 11.--12. "IMX_A_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_D_OFST_0,IMX_A_D_OFST_1,IMX_A_D_OFST_2,IMX_A_D_OFST_3" bitfld.long 0x00 9.--10. "NEXT,Next channel in the sync chain" "NEXT_0,NEXT_1,NEXT_2,NEXT_3" bitfld.long 0x00 8. "VTNF_SYNC,Enable HW synchronization with the VTNF module" "VTNF_SYNC_0,VTNF_SYNC_1" newline bitfld.long 0x00 5.--7. "DMA_SYNC,Enable HW synchronization with the SIMCOP DMA" "DMA_SYNC_0,DMA_SYNC_1,DMA_SYNC_2,DMA_SYNC_3,DMA_SYNC_4,DMA_SYNC_5,DMA_SYNC_6,DMA_SYNC_7" bitfld.long 0x00 4. "ROT_A_SYNC,This bit field is reserved and users should write the reset value to this bit location" "ROT_A_SYNC_0,ROT_A_SYNC_1" bitfld.long 0x00 3. "NSF_SYNC,This bit field is reserved and users should write the reset value to this bit location" "NSF_SYNC_0,NSF_SYNC_1" newline bitfld.long 0x00 2. "VLCDJ_SYNC,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_SYNC_0,VLCDJ_SYNC_1" bitfld.long 0x00 1. "DCT_SYNC,Enable HW synchronization with the DCT module" "DCT_SYNC_0,DCT_SYNC_1" bitfld.long 0x00 0. "LDC_SYNC,Enable HW synchronization with the LDC module" "LDC_SYNC_0,LDC_SYNC_1" group.long 0xB0++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL_i_3,HW sequencer step control register" bitfld.long 0x00 31. "CPU_SYNC,Enable HW synchronization with the CPU so that it could be used for some processing on in the macro-block pipeline" "CPU_SYNC_0,CPU_SYNC_1" bitfld.long 0x00 28.--30. "DMA_OFST,Controls DMA bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000" "DMA_OFST_0,DMA_OFST_1,DMA_OFST_2,DMA_OFST_3,DMA_OFST_4,DMA_OFST_5,DMA_OFST_6,DMA_OFST_7" bitfld.long 0x00 26.--27. "ROT_O_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_O_OFST_0,ROT_O_OFST_1,ROT_O_OFST_2,ROT_O_OFST_3" newline bitfld.long 0x00 24.--25. "ROT_I_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_I_OFST_0,ROT_I_OFST_1,ROT_I_OFST_2,ROT_I_OFST_3" bitfld.long 0x00 23. "EXT_SYNC,The HW sequencer waits for an external start pulse i(START_STEP signal) n addition to internally selected synchronization events" "0,1" bitfld.long 0x00 20.--22. "DCT_F_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_F_OFST_0,DCT_F_OFST_1,DCT_F_OFST_2,DCT_F_OFST_3,DCT_F_OFST_4,DCT_F_OFST_5,?,?" newline bitfld.long 0x00 18.--19. "DCT_S_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_S_OFST_0,DCT_S_OFST_1,DCT_S_OFST_2,DCT_S_OFST_3" bitfld.long 0x00 15.--17. "VLCDJ_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_IO_OFST_0,VLCDJ_IO_OFST_1,VLCDJ_IO_OFST_2,VLCDJ_IO_OFST_3,VLCDJ_IO_OFST_4,VLCDJ_IO_OFST_5,?,?" bitfld.long 0x00 13.--14. "IMX_B_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_D_OFST_0,IMX_B_D_OFST_1,IMX_B_D_OFST_2,IMX_B_D_OFST_3" newline bitfld.long 0x00 11.--12. "IMX_A_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_D_OFST_0,IMX_A_D_OFST_1,IMX_A_D_OFST_2,IMX_A_D_OFST_3" bitfld.long 0x00 9.--10. "NEXT,Next channel in the sync chain" "NEXT_0,NEXT_1,NEXT_2,NEXT_3" bitfld.long 0x00 8. "VTNF_SYNC,Enable HW synchronization with the VTNF module" "VTNF_SYNC_0,VTNF_SYNC_1" newline bitfld.long 0x00 5.--7. "DMA_SYNC,Enable HW synchronization with the SIMCOP DMA" "DMA_SYNC_0,DMA_SYNC_1,DMA_SYNC_2,DMA_SYNC_3,DMA_SYNC_4,DMA_SYNC_5,DMA_SYNC_6,DMA_SYNC_7" bitfld.long 0x00 4. "ROT_A_SYNC,This bit field is reserved and users should write the reset value to this bit location" "ROT_A_SYNC_0,ROT_A_SYNC_1" bitfld.long 0x00 3. "NSF_SYNC,This bit field is reserved and users should write the reset value to this bit location" "NSF_SYNC_0,NSF_SYNC_1" newline bitfld.long 0x00 2. "VLCDJ_SYNC,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_SYNC_0,VLCDJ_SYNC_1" bitfld.long 0x00 1. "DCT_SYNC,Enable HW synchronization with the DCT module" "DCT_SYNC_0,DCT_SYNC_1" bitfld.long 0x00 0. "LDC_SYNC,Enable HW synchronization with the LDC module" "LDC_SYNC_0,LDC_SYNC_1" group.long 0x84++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_SWITCH_i_0,Image buffer switch control" bitfld.long 0x00 28.--31. "IMBUFF_H,Switch for image buffer #h" "IMBUFF_H_0,IMBUFF_H_1,IMBUFF_H_2,IMBUFF_H_3,IMBUFF_H_4,IMBUFF_H_5,IMBUFF_H_6,IMBUFF_H_7,IMBUFF_H_8,IMBUFF_H_9,IMBUFF_H_10,?,?,?,?,?" bitfld.long 0x00 24.--27. "IMBUFF_G,Switch for image buffer #g" "IMBUFF_G_0,IMBUFF_G_1,IMBUFF_G_2,IMBUFF_G_3,IMBUFF_G_4,IMBUFF_G_5,IMBUFF_G_6,IMBUFF_G_7,IMBUFF_G_8,IMBUFF_G_9,IMBUFF_G_10,?,?,?,?,?" bitfld.long 0x00 20.--23. "IMBUFF_F,Switch for image buffer #f" "IMBUFF_F_0,IMBUFF_F_1,IMBUFF_F_2,IMBUFF_F_3,IMBUFF_F_4,IMBUFF_F_5,IMBUFF_F_6,IMBUFF_F_7,IMBUFF_F_8,?,?,?,?,?,?,?" newline bitfld.long 0x00 16.--19. "IMBUFF_E,Switch for image buffer #e" "IMBUFF_E_0,IMBUFF_E_1,IMBUFF_E_2,IMBUFF_E_3,IMBUFF_E_4,IMBUFF_E_5,IMBUFF_E_6,IMBUFF_E_7,IMBUFF_E_8,?,?,?,?,?,?,?" rbitfld.long 0x00 15. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 12.--14. "IMBUFF_D,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_D_0,IMBUFF_D_1,IMBUFF_D_2,IMBUFF_D_3,IMBUFF_D_4,IMBUFF_D_5,IMBUFF_D_6,IMBUFF_D_7" newline rbitfld.long 0x00 11. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 8.--10. "IMBUFF_C,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_C_0,IMBUFF_C_1,IMBUFF_C_2,IMBUFF_C_3,IMBUFF_C_4,IMBUFF_C_5,IMBUFF_C_6,IMBUFF_C_7" rbitfld.long 0x00 7. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 4.--6. "IMBUFF_B,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_B_0,IMBUFF_B_1,IMBUFF_B_2,IMBUFF_B_3,IMBUFF_B_4,IMBUFF_B_5,IMBUFF_B_6,IMBUFF_B_7" rbitfld.long 0x00 3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 0.--2. "IMBUFF_A,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_A_0,IMBUFF_A_1,IMBUFF_A_2,IMBUFF_A_3,IMBUFF_A_4,IMBUFF_A_5,IMBUFF_A_6,IMBUFF_A_7" group.long 0x94++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_SWITCH_i_1,Image buffer switch control" bitfld.long 0x00 28.--31. "IMBUFF_H,Switch for image buffer #h" "IMBUFF_H_0,IMBUFF_H_1,IMBUFF_H_2,IMBUFF_H_3,IMBUFF_H_4,IMBUFF_H_5,IMBUFF_H_6,IMBUFF_H_7,IMBUFF_H_8,IMBUFF_H_9,IMBUFF_H_10,?,?,?,?,?" bitfld.long 0x00 24.--27. "IMBUFF_G,Switch for image buffer #g" "IMBUFF_G_0,IMBUFF_G_1,IMBUFF_G_2,IMBUFF_G_3,IMBUFF_G_4,IMBUFF_G_5,IMBUFF_G_6,IMBUFF_G_7,IMBUFF_G_8,IMBUFF_G_9,IMBUFF_G_10,?,?,?,?,?" bitfld.long 0x00 20.--23. "IMBUFF_F,Switch for image buffer #f" "IMBUFF_F_0,IMBUFF_F_1,IMBUFF_F_2,IMBUFF_F_3,IMBUFF_F_4,IMBUFF_F_5,IMBUFF_F_6,IMBUFF_F_7,IMBUFF_F_8,?,?,?,?,?,?,?" newline bitfld.long 0x00 16.--19. "IMBUFF_E,Switch for image buffer #e" "IMBUFF_E_0,IMBUFF_E_1,IMBUFF_E_2,IMBUFF_E_3,IMBUFF_E_4,IMBUFF_E_5,IMBUFF_E_6,IMBUFF_E_7,IMBUFF_E_8,?,?,?,?,?,?,?" rbitfld.long 0x00 15. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 12.--14. "IMBUFF_D,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_D_0,IMBUFF_D_1,IMBUFF_D_2,IMBUFF_D_3,IMBUFF_D_4,IMBUFF_D_5,IMBUFF_D_6,IMBUFF_D_7" newline rbitfld.long 0x00 11. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 8.--10. "IMBUFF_C,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_C_0,IMBUFF_C_1,IMBUFF_C_2,IMBUFF_C_3,IMBUFF_C_4,IMBUFF_C_5,IMBUFF_C_6,IMBUFF_C_7" rbitfld.long 0x00 7. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 4.--6. "IMBUFF_B,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_B_0,IMBUFF_B_1,IMBUFF_B_2,IMBUFF_B_3,IMBUFF_B_4,IMBUFF_B_5,IMBUFF_B_6,IMBUFF_B_7" rbitfld.long 0x00 3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 0.--2. "IMBUFF_A,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_A_0,IMBUFF_A_1,IMBUFF_A_2,IMBUFF_A_3,IMBUFF_A_4,IMBUFF_A_5,IMBUFF_A_6,IMBUFF_A_7" group.long 0xA4++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_SWITCH_i_2,Image buffer switch control" bitfld.long 0x00 28.--31. "IMBUFF_H,Switch for image buffer #h" "IMBUFF_H_0,IMBUFF_H_1,IMBUFF_H_2,IMBUFF_H_3,IMBUFF_H_4,IMBUFF_H_5,IMBUFF_H_6,IMBUFF_H_7,IMBUFF_H_8,IMBUFF_H_9,IMBUFF_H_10,?,?,?,?,?" bitfld.long 0x00 24.--27. "IMBUFF_G,Switch for image buffer #g" "IMBUFF_G_0,IMBUFF_G_1,IMBUFF_G_2,IMBUFF_G_3,IMBUFF_G_4,IMBUFF_G_5,IMBUFF_G_6,IMBUFF_G_7,IMBUFF_G_8,IMBUFF_G_9,IMBUFF_G_10,?,?,?,?,?" bitfld.long 0x00 20.--23. "IMBUFF_F,Switch for image buffer #f" "IMBUFF_F_0,IMBUFF_F_1,IMBUFF_F_2,IMBUFF_F_3,IMBUFF_F_4,IMBUFF_F_5,IMBUFF_F_6,IMBUFF_F_7,IMBUFF_F_8,?,?,?,?,?,?,?" newline bitfld.long 0x00 16.--19. "IMBUFF_E,Switch for image buffer #e" "IMBUFF_E_0,IMBUFF_E_1,IMBUFF_E_2,IMBUFF_E_3,IMBUFF_E_4,IMBUFF_E_5,IMBUFF_E_6,IMBUFF_E_7,IMBUFF_E_8,?,?,?,?,?,?,?" rbitfld.long 0x00 15. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 12.--14. "IMBUFF_D,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_D_0,IMBUFF_D_1,IMBUFF_D_2,IMBUFF_D_3,IMBUFF_D_4,IMBUFF_D_5,IMBUFF_D_6,IMBUFF_D_7" newline rbitfld.long 0x00 11. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 8.--10. "IMBUFF_C,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_C_0,IMBUFF_C_1,IMBUFF_C_2,IMBUFF_C_3,IMBUFF_C_4,IMBUFF_C_5,IMBUFF_C_6,IMBUFF_C_7" rbitfld.long 0x00 7. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 4.--6. "IMBUFF_B,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_B_0,IMBUFF_B_1,IMBUFF_B_2,IMBUFF_B_3,IMBUFF_B_4,IMBUFF_B_5,IMBUFF_B_6,IMBUFF_B_7" rbitfld.long 0x00 3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 0.--2. "IMBUFF_A,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_A_0,IMBUFF_A_1,IMBUFF_A_2,IMBUFF_A_3,IMBUFF_A_4,IMBUFF_A_5,IMBUFF_A_6,IMBUFF_A_7" group.long 0xB4++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_SWITCH_i_3,Image buffer switch control" bitfld.long 0x00 28.--31. "IMBUFF_H,Switch for image buffer #h" "IMBUFF_H_0,IMBUFF_H_1,IMBUFF_H_2,IMBUFF_H_3,IMBUFF_H_4,IMBUFF_H_5,IMBUFF_H_6,IMBUFF_H_7,IMBUFF_H_8,IMBUFF_H_9,IMBUFF_H_10,?,?,?,?,?" bitfld.long 0x00 24.--27. "IMBUFF_G,Switch for image buffer #g" "IMBUFF_G_0,IMBUFF_G_1,IMBUFF_G_2,IMBUFF_G_3,IMBUFF_G_4,IMBUFF_G_5,IMBUFF_G_6,IMBUFF_G_7,IMBUFF_G_8,IMBUFF_G_9,IMBUFF_G_10,?,?,?,?,?" bitfld.long 0x00 20.--23. "IMBUFF_F,Switch for image buffer #f" "IMBUFF_F_0,IMBUFF_F_1,IMBUFF_F_2,IMBUFF_F_3,IMBUFF_F_4,IMBUFF_F_5,IMBUFF_F_6,IMBUFF_F_7,IMBUFF_F_8,?,?,?,?,?,?,?" newline bitfld.long 0x00 16.--19. "IMBUFF_E,Switch for image buffer #e" "IMBUFF_E_0,IMBUFF_E_1,IMBUFF_E_2,IMBUFF_E_3,IMBUFF_E_4,IMBUFF_E_5,IMBUFF_E_6,IMBUFF_E_7,IMBUFF_E_8,?,?,?,?,?,?,?" rbitfld.long 0x00 15. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 12.--14. "IMBUFF_D,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_D_0,IMBUFF_D_1,IMBUFF_D_2,IMBUFF_D_3,IMBUFF_D_4,IMBUFF_D_5,IMBUFF_D_6,IMBUFF_D_7" newline rbitfld.long 0x00 11. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 8.--10. "IMBUFF_C,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_C_0,IMBUFF_C_1,IMBUFF_C_2,IMBUFF_C_3,IMBUFF_C_4,IMBUFF_C_5,IMBUFF_C_6,IMBUFF_C_7" rbitfld.long 0x00 7. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 4.--6. "IMBUFF_B,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_B_0,IMBUFF_B_1,IMBUFF_B_2,IMBUFF_B_3,IMBUFF_B_4,IMBUFF_B_5,IMBUFF_B_6,IMBUFF_B_7" rbitfld.long 0x00 3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 0.--2. "IMBUFF_A,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_A_0,IMBUFF_A_1,IMBUFF_A_2,IMBUFF_A_3,IMBUFF_A_4,IMBUFF_A_5,IMBUFF_A_6,IMBUFF_A_7" group.long 0x88++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_IMX_CTRL_i_0,This register is reserved and users should write the reset value to this register location" bitfld.long 0x00 31. "IMX_B_SYNC,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_SYNC_0,IMX_B_SYNC_1" rbitfld.long 0x00 29.--30. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" hexmask.long.word 0x00 16.--28. 1. "IMX_B_START,This bit field is reserved and users should write the reset value to this bit location" newline bitfld.long 0x00 15. "IMX_A_SYNC,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_SYNC_0,IMX_A_SYNC_1" rbitfld.long 0x00 13.--14. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" hexmask.long.word 0x00 0.--12. 1. "IMX_A_START,This bit field is reserved and users should write the reset value to this bit location" group.long 0x98++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_IMX_CTRL_i_1,This register is reserved and users should write the reset value to this register location" bitfld.long 0x00 31. "IMX_B_SYNC,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_SYNC_0,IMX_B_SYNC_1" rbitfld.long 0x00 29.--30. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" hexmask.long.word 0x00 16.--28. 1. "IMX_B_START,This bit field is reserved and users should write the reset value to this bit location" newline bitfld.long 0x00 15. "IMX_A_SYNC,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_SYNC_0,IMX_A_SYNC_1" rbitfld.long 0x00 13.--14. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" hexmask.long.word 0x00 0.--12. 1. "IMX_A_START,This bit field is reserved and users should write the reset value to this bit location" group.long 0xA8++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_IMX_CTRL_i_2,This register is reserved and users should write the reset value to this register location" bitfld.long 0x00 31. "IMX_B_SYNC,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_SYNC_0,IMX_B_SYNC_1" rbitfld.long 0x00 29.--30. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" hexmask.long.word 0x00 16.--28. 1. "IMX_B_START,This bit field is reserved and users should write the reset value to this bit location" newline bitfld.long 0x00 15. "IMX_A_SYNC,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_SYNC_0,IMX_A_SYNC_1" rbitfld.long 0x00 13.--14. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" hexmask.long.word 0x00 0.--12. 1. "IMX_A_START,This bit field is reserved and users should write the reset value to this bit location" group.long 0xB8++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_IMX_CTRL_i_3,This register is reserved and users should write the reset value to this register location" bitfld.long 0x00 31. "IMX_B_SYNC,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_SYNC_0,IMX_B_SYNC_1" rbitfld.long 0x00 29.--30. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" hexmask.long.word 0x00 16.--28. 1. "IMX_B_START,This bit field is reserved and users should write the reset value to this bit location" newline bitfld.long 0x00 15. "IMX_A_SYNC,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_SYNC_0,IMX_A_SYNC_1" rbitfld.long 0x00 13.--14. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" hexmask.long.word 0x00 0.--12. 1. "IMX_A_START,This bit field is reserved and users should write the reset value to this bit location" group.long 0x8C++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL2_i_0,HW sequencer step control register" hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 12.--13. "VTNF_IO_OFST,Controls VTNF_IO bus mapping to image buffers: 0x0000 0x1000" "VTNF_IO_OFST_0,VTNF_IO_OFST_1,VTNF_IO_OFST_2,VTNF_IO_OFST_3" bitfld.long 0x00 10.--11. "NSF2_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "NSF2_IO_OFST_0,NSF2_IO_OFST_1,NSF2_IO_OFST_2,NSF2_IO_OFST_3" newline bitfld.long 0x00 8.--9. "LDC_O_OFST,Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000" "LDC_O_OFST_0,LDC_O_OFST_1,LDC_O_OFST_2,LDC_O_OFST_3" rbitfld.long 0x00 7. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 4.--6. "COEFF_B,This bit field is reserved and users should write the reset value to this bit location" "COEFF_B_0,COEFF_B_1,COEFF_B_2,COEFF_B_3,COEFF_B_4,COEFF_B_5,COEFF_B_6,COEFF_B_7" newline rbitfld.long 0x00 3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 0.--2. "COEFF_A,This bit field is reserved and users should write the reset value to this bit location" "COEFF_A_0,COEFF_A_1,COEFF_A_2,COEFF_A_3,COEFF_A_4,COEFF_A_5,COEFF_A_6,COEFF_A_7" group.long 0x9C++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL2_i_1,HW sequencer step control register" hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 12.--13. "VTNF_IO_OFST,Controls VTNF_IO bus mapping to image buffers: 0x0000 0x1000" "VTNF_IO_OFST_0,VTNF_IO_OFST_1,VTNF_IO_OFST_2,VTNF_IO_OFST_3" bitfld.long 0x00 10.--11. "NSF2_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "NSF2_IO_OFST_0,NSF2_IO_OFST_1,NSF2_IO_OFST_2,NSF2_IO_OFST_3" newline bitfld.long 0x00 8.--9. "LDC_O_OFST,Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000" "LDC_O_OFST_0,LDC_O_OFST_1,LDC_O_OFST_2,LDC_O_OFST_3" rbitfld.long 0x00 7. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 4.--6. "COEFF_B,This bit field is reserved and users should write the reset value to this bit location" "COEFF_B_0,COEFF_B_1,COEFF_B_2,COEFF_B_3,COEFF_B_4,COEFF_B_5,COEFF_B_6,COEFF_B_7" newline rbitfld.long 0x00 3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 0.--2. "COEFF_A,This bit field is reserved and users should write the reset value to this bit location" "COEFF_A_0,COEFF_A_1,COEFF_A_2,COEFF_A_3,COEFF_A_4,COEFF_A_5,COEFF_A_6,COEFF_A_7" group.long 0xAC++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL2_i_2,HW sequencer step control register" hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 12.--13. "VTNF_IO_OFST,Controls VTNF_IO bus mapping to image buffers: 0x0000 0x1000" "VTNF_IO_OFST_0,VTNF_IO_OFST_1,VTNF_IO_OFST_2,VTNF_IO_OFST_3" bitfld.long 0x00 10.--11. "NSF2_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "NSF2_IO_OFST_0,NSF2_IO_OFST_1,NSF2_IO_OFST_2,NSF2_IO_OFST_3" newline bitfld.long 0x00 8.--9. "LDC_O_OFST,Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000" "LDC_O_OFST_0,LDC_O_OFST_1,LDC_O_OFST_2,LDC_O_OFST_3" rbitfld.long 0x00 7. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 4.--6. "COEFF_B,This bit field is reserved and users should write the reset value to this bit location" "COEFF_B_0,COEFF_B_1,COEFF_B_2,COEFF_B_3,COEFF_B_4,COEFF_B_5,COEFF_B_6,COEFF_B_7" newline rbitfld.long 0x00 3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 0.--2. "COEFF_A,This bit field is reserved and users should write the reset value to this bit location" "COEFF_A_0,COEFF_A_1,COEFF_A_2,COEFF_A_3,COEFF_A_4,COEFF_A_5,COEFF_A_6,COEFF_A_7" group.long 0xBC++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL2_i_3,HW sequencer step control register" hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 12.--13. "VTNF_IO_OFST,Controls VTNF_IO bus mapping to image buffers: 0x0000 0x1000" "VTNF_IO_OFST_0,VTNF_IO_OFST_1,VTNF_IO_OFST_2,VTNF_IO_OFST_3" bitfld.long 0x00 10.--11. "NSF2_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "NSF2_IO_OFST_0,NSF2_IO_OFST_1,NSF2_IO_OFST_2,NSF2_IO_OFST_3" newline bitfld.long 0x00 8.--9. "LDC_O_OFST,Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000" "LDC_O_OFST_0,LDC_O_OFST_1,LDC_O_OFST_2,LDC_O_OFST_3" rbitfld.long 0x00 7. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 4.--6. "COEFF_B,This bit field is reserved and users should write the reset value to this bit location" "COEFF_B_0,COEFF_B_1,COEFF_B_2,COEFF_B_3,COEFF_B_4,COEFF_B_5,COEFF_B_6,COEFF_B_7" newline rbitfld.long 0x00 3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 0.--2. "COEFF_A,This bit field is reserved and users should write the reset value to this bit location" "COEFF_A_0,COEFF_A_1,COEFF_A_2,COEFF_A_3,COEFF_A_4,COEFF_A_5,COEFF_A_6,COEFF_A_7" width 0x0B tree.end repeat 2. (list 1. 2. )(list ad:0x48070000 ad:0x48072000 ) tree "I2C$1" base $2 rgroup.word 0x00++0x01 line.word 0x00 "I2C_REVNB_LO,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" rgroup.word 0x04++0x01 line.word 0x00 "I2C_REVNB_HI,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" group.word 0x10++0x01 line.word 0x00 "I2C_SYSC,System Configuration register" rbitfld.word 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits" "CLKACTIVITY_0,CLKACTIVITY_1,CLKACTIVITY_2,CLKACTIVITY_3" rbitfld.word 0x00 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 3.--4. "IDLEMODE,Idle Mode selection bits" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.word 0x00 2. "ENAWAKEUP,Enable Wakeup control bit" "ENAWAKEUP_0,ENAWAKEUP_1" bitfld.word 0x00 1. "SRST,SoftReset bit" "SRST_0,SRST_1" newline bitfld.word 0x00 0. "AUTOIDLE,Autoidle bit" "AUTOIDLE_0,AUTOIDLE_1" group.word 0x20++0x01 line.word 0x00 "I2C_EOI,End Of Interrupt number specification" hexmask.word 0x00 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0,1" group.word 0x24++0x01 line.word 0x00 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.word 0x00 15. "RESERVED,Write 0s for future compatibility" "0,1" bitfld.word 0x00 14. "XDR,Transmit draining IRQ status" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive draining IRQ status" "RDR_0,RDR_1" newline rbitfld.word 0x00 12. "BB,Bus busy status" "BB_0_r,BB_1_r" bitfld.word 0x00 11. "ROVR,Receive overrun status" "ROVR_0_r,ROVR_1_r" bitfld.word 0x00 10. "XUDF,Transmit underflow status" "XUDF_0_r,XUDF_1_r" newline bitfld.word 0x00 9. "AAS,Address recognized as slave IRQ status" "AAS_0,AAS_1" bitfld.word 0x00 8. "BF,Bus Free IRQ status" "BF_0,BF_1" bitfld.word 0x00 7. "AERR,Access Error IRQ status" "AERR_0,AERR_1" newline bitfld.word 0x00 6. "STC,Start Condition IRQ status" "STC_0,STC_1" bitfld.word 0x00 5. "GC,General call IRQ status" "GC_0,GC_1" bitfld.word 0x00 4. "XRDY,Transmit data ready IRQ status" "XRDY_0,XRDY_1" newline bitfld.word 0x00 3. "RRDY,Receive data ready IRQ status" "RRDY_0,RRDY_1" bitfld.word 0x00 2. "ARDY,Register access ready IRQ status" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgement IRQ status" "NACK_0,NACK_1" newline bitfld.word 0x00 0. "AL,Arbitration lost IRQ status" "AL_0,AL_1" group.word 0x28++0x01 line.word 0x00 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.word 0x00 15. "RESERVED,Write 0s for future compatibility" "0,1" bitfld.word 0x00 14. "XDR,Transmit draining IRQ enabled status" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive draining IRQ enabled status" "RDR_0,RDR_1" newline rbitfld.word 0x00 12. "BB,Bus busy enabled status" "BB_0_r,BB_1_r" bitfld.word 0x00 11. "ROVR,Receive overrun enabled status" "ROVR_0_r,ROVR_1_r" bitfld.word 0x00 10. "XUDF,Transmit underflow enabled status" "XUDF_0_r,XUDF_1_r" newline bitfld.word 0x00 9. "AAS,Address recognized as slave IRQ enabled status" "AAS_0,AAS_1" bitfld.word 0x00 8. "BF,Bus Free IRQ enabled status" "BF_0,BF_1" bitfld.word 0x00 7. "AERR,Access Error IRQ enabled status" "AERR_0,AERR_1" newline bitfld.word 0x00 6. "STC,Start Condition IRQ enabled status" "STC_0,STC_1" bitfld.word 0x00 5. "GC,General call IRQ enabled status" "GC_0,GC_1" bitfld.word 0x00 4. "XRDY,Transmit data ready IRQ enabled status" "XRDY_0,XRDY_1" newline bitfld.word 0x00 3. "RRDY,Receive data ready IRQ enabled status" "RRDY_0,RRDY_1" bitfld.word 0x00 2. "ARDY,Register access ready IRQ enabled status" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgement IRQ enabled status" "NACK_0,NACK_1" newline bitfld.word 0x00 0. "AL,Arbitration lost IRQ enabled status" "AL_0,AL_1" group.word 0x2C++0x01 line.word 0x00 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector" rbitfld.word 0x00 15. "RESERVED,Write 0s for future compatibility" "0,1" bitfld.word 0x00 14. "XDR_IE,Transmit Draining interrupt enable set" "XDR_IE_0,XDR_IE_1" bitfld.word 0x00 13. "RDR_IE,Receive Draining interrupt enable set" "RDR_IE_0,RDR_IE_1" newline rbitfld.word 0x00 12. "RESERVED,Reserved" "0,1" bitfld.word 0x00 11. "ROVR,Receive overrun enable set.Read: enum=disable" "ROVR_0,ROVR_1" bitfld.word 0x00 10. "XUDF,Transmit underflow enable set.Read: enum=disable" "XUDF_0,XUDF_1" newline bitfld.word 0x00 9. "AAS_IE,Addressed as Slave interrupt enable set" "AAS_IE_0,AAS_IE_1" bitfld.word 0x00 8. "BF_IE,Bus Free interrupt enable set" "BF_IE_0,BF_IE_1" bitfld.word 0x00 7. "AERR_IE,Access Error interrupt enable set" "AERR_IE_0,AERR_IE_1" newline bitfld.word 0x00 6. "STC_IE,Start Condition interrupt enable set" "STC_IE_0,STC_IE_1" bitfld.word 0x00 5. "GC_IE,General call Interrupt enable set" "GC_IE_0,GC_IE_1" bitfld.word 0x00 4. "XRDY_IE,Transmit data ready interrupt enable set" "XRDY_IE_0,XRDY_IE_1" newline bitfld.word 0x00 3. "RRDY_IE,Receive data ready interrupt enable set" "RRDY_IE_0,RRDY_IE_1" bitfld.word 0x00 2. "ARDY_IE,Register access ready interrupt enable set" "ARDY_IE_0,ARDY_IE_1" bitfld.word 0x00 1. "NACK_IE,No acknowledgement interrupt enable set" "NACK_IE_0,NACK_IE_1" newline bitfld.word 0x00 0. "AL_IE,Arbitration lost interrupt enable set" "AL_IE_0,AL_IE_1" group.word 0x30++0x01 line.word 0x00 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector" rbitfld.word 0x00 15. "RESERVED,Write 0s for future compatibility" "0,1" bitfld.word 0x00 14. "XDR_IE,Transmit Draining interrupt enable clear" "XDR_IE_0,XDR_IE_1" bitfld.word 0x00 13. "RDR_IE,Receive Draining interrupt enable clear" "RDR_IE_0,RDR_IE_1" newline rbitfld.word 0x00 12. "RESERVED,Reserved" "0,1" bitfld.word 0x00 11. "ROVR,Receive overrun enable clear.Read: enum=disable" "ROVR_0,ROVR_1" bitfld.word 0x00 10. "XUDF,Transmit underflow enable clear.Read: enum=disable" "XUDF_0,XUDF_1" newline bitfld.word 0x00 9. "AAS_IE,Addressed as Slave interrupt enable clear" "AAS_IE_0,AAS_IE_1" bitfld.word 0x00 8. "BF_IE,Bus Free interrupt enable clear" "BF_IE_0,BF_IE_1" bitfld.word 0x00 7. "AERR_IE,Access Error interrupt enable clear" "AERR_IE_0,AERR_IE_1" newline bitfld.word 0x00 6. "STC_IE,Start Condition interrupt enable clear" "STC_IE_0,STC_IE_1" bitfld.word 0x00 5. "GC_IE,General call Interrupt enable clear" "GC_IE_0,GC_IE_1" bitfld.word 0x00 4. "XRDY_IE,Transmit data ready interrupt enable clear" "XRDY_IE_0,XRDY_IE_1" newline bitfld.word 0x00 3. "RRDY_IE,Receive data ready interrupt enable clear" "RRDY_IE_0,RRDY_IE_1" bitfld.word 0x00 2. "ARDY_IE,Register access ready interrupt enable clear" "ARDY_IE_0,ARDY_IE_1" bitfld.word 0x00 1. "NACK_IE,No acknowledgement interrupt enable clear" "NACK_IE_0,NACK_IE_1" newline bitfld.word 0x00 0. "AL_IE,Arbitration lost interrupt enable clear" "AL_IE_0,AL_IE_1" group.word 0x34++0x01 line.word 0x00 "I2C_WE,I2C wakeup enable vector" rbitfld.word 0x00 15. "RESERVED,Reserved" "0,1" bitfld.word 0x00 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1" newline rbitfld.word 0x00 12. "RESERVED,Reserved" "0,1" bitfld.word 0x00 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1" bitfld.word 0x00 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1" newline bitfld.word 0x00 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1" bitfld.word 0x00 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1" rbitfld.word 0x00 7. "RESERVED,Reserved" "0,1" newline bitfld.word 0x00 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1" bitfld.word 0x00 5. "GC,General call IRQ wakeup set" "GC_0,GC_1" rbitfld.word 0x00 4. "RESERVED,Reserved" "0,1" newline bitfld.word 0x00 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1" bitfld.word 0x00 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1" newline bitfld.word 0x00 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1" group.word 0x38++0x01 line.word 0x00 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set" hexmask.word 0x00 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x00 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" group.word 0x3C++0x01 line.word 0x00 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set" hexmask.word 0x00 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x00 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" group.word 0x40++0x01 line.word 0x00 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear" hexmask.word 0x00 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x00 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" group.word 0x44++0x01 line.word 0x00 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear" hexmask.word 0x00 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x00 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" group.word 0x48++0x01 line.word 0x00 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable" rbitfld.word 0x00 15. "RESERVED,Reserved" "0,1" bitfld.word 0x00 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1" newline rbitfld.word 0x00 12. "RESERVED,Reserved" "0,1" bitfld.word 0x00 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1" bitfld.word 0x00 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1" newline bitfld.word 0x00 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1" bitfld.word 0x00 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1" rbitfld.word 0x00 7. "RESERVED,Reserved" "0,1" newline bitfld.word 0x00 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1" bitfld.word 0x00 5. "GC,General call IRQ wakeup set" "GC_0,GC_1" rbitfld.word 0x00 4. "RESERVED,Reserved" "0,1" newline bitfld.word 0x00 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1" bitfld.word 0x00 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1" newline bitfld.word 0x00 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1" group.word 0x4C++0x01 line.word 0x00 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable" rbitfld.word 0x00 15. "RESERVED,Reserved" "0,1" bitfld.word 0x00 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1" newline rbitfld.word 0x00 12. "RESERVED,Reserved" "0,1" bitfld.word 0x00 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1" bitfld.word 0x00 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1" newline bitfld.word 0x00 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1" bitfld.word 0x00 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1" rbitfld.word 0x00 7. "RESERVED,Reserved" "0,1" newline bitfld.word 0x00 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1" bitfld.word 0x00 5. "GC,General call IRQ wakeup set" "GC_0,GC_1" rbitfld.word 0x00 4. "RESERVED,Reserved" "0,1" newline bitfld.word 0x00 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1" bitfld.word 0x00 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1" newline bitfld.word 0x00 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1" group.word 0x90++0x01 line.word 0x00 "I2C_SYSS,System Status register" hexmask.word 0x00 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x00 0. "RDONE,Reset done bit" "RDONE_0_r,RDONE_1_r" group.word 0x94++0x01 line.word 0x00 "I2C_BUF,Buffer Configuration register" bitfld.word 0x00 15. "RDMA_EN,Receive DMA channel enable" "RDMA_EN_0,RDMA_EN_1" bitfld.word 0x00 14. "RXFIFO_CLR,Receive FIFO clear" "RXFIFO_CLR_0,RXFIFO_CLR_1" bitfld.word 0x00 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.word 0x00 7. "XDMA_EN,Transmit DMA channel enable" "XDMA_EN_0,XDMA_EN_1" bitfld.word 0x00 6. "TXFIFO_CLR,Transmit FIFO clear" "TXFIFO_CLR_0,TXFIFO_CLR_1" bitfld.word 0x00 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x98++0x01 line.word 0x00 "I2C_CNT,Data counter register" group.word 0x9C++0x01 line.word 0x00 "I2C_DATA,Data access register" hexmask.word.byte 0x00 8.--15. 1. "RESERVED,Reserved" hexmask.word.byte 0x00 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.word 0xA4++0x01 line.word 0x00 "I2C_CON,I2C configuration register" bitfld.word 0x00 15. "I2C_EN,I2C module enable" "I2C_EN_0,I2C_EN_1" rbitfld.word 0x00 14. "RESERVED,Reserved" "0,1" bitfld.word 0x00 12.--13. "OPMODE,Operation mode selection" "OPMODE_0,OPMODE_1,OPMODE_2,OPMODE_3" newline bitfld.word 0x00 11. "STB,Start byte mode (master mode only)" "STB_0,STB_1" bitfld.word 0x00 10. "MST,Master/slave mode" "MST_0,MST_1" bitfld.word 0x00 9. "TRX,Transmitter/Receiver mode (master mode only)" "TRX_0,TRX_1" newline bitfld.word 0x00 8. "XSA,Expand Slave address" "XSA_0,XSA_1" bitfld.word 0x00 7. "XOA0,Expand Own address 0" "XOA0_0,XOA0_1" bitfld.word 0x00 6. "XOA1,Expand Own address 1" "XOA1_0,XOA1_1" newline bitfld.word 0x00 5. "XOA2,Expand Own address 2" "XOA2_0,XOA2_1" bitfld.word 0x00 4. "XOA3,Expand Own address 3" "XOA3_0,XOA3_1" rbitfld.word 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.word 0x00 1. "STP,Stop condition (master mode only)" "STP_0,STP_1" bitfld.word 0x00 0. "STT,Start condition (master mode only)" "STT_0,STT_1" group.word 0xA8++0x01 line.word 0x00 "I2C_OA,Own address register" bitfld.word 0x00 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 10.--12. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.word 0x00 0.--9. 1. "OA,Own address" group.word 0xAC++0x01 line.word 0x00 "I2C_SA,Slave address register" rbitfld.word 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.word 0x00 0.--9. 1. "SA,Slave address" group.word 0xB0++0x01 line.word 0x00 "I2C_PSC,I2C Clock Prescaler Register" hexmask.word.byte 0x00 8.--15. 1. "RESERVED,Reserved" abitfld.word 0x00 0.--7. "PSC,Fast/Standard mode prescale sampling clock divider value" "0x00=Divide by 1,0x01=Divide by 2,0xFF=Divide by 256" group.word 0xB4++0x01 line.word 0x00 "I2C_SCLL,I2C SCL Low Time Register" hexmask.word.byte 0x00 8.--15. 1. "RESERVED,Reserved" hexmask.word.byte 0x00 0.--7. 1. "SCLL,Fast/standard mode SCL low timeThe value of the bit field is automatically increased by 7" group.word 0xB8++0x01 line.word 0x00 "I2C_SCLH,I2C SCL High Time Register" hexmask.word.byte 0x00 8.--15. 1. "RESERVED,Reserved" hexmask.word.byte 0x00 0.--7. 1. "SCLH,Fast/standard mode SCL high timeThe value of the bit field is automatically increased by 5" group.word 0xBC++0x01 line.word 0x00 "I2C_SYSTEST,I2C System Test Register" bitfld.word 0x00 15. "ST_EN,System test enable" "ST_EN_0,ST_EN_1" bitfld.word 0x00 14. "FREE,Free running mode (on breakpoint)" "FREE_0,FREE_1" bitfld.word 0x00 12.--13. "TMODE,Test mode select" "TMODE_0,TMODE_1,TMODE_2,TMODE_3" newline bitfld.word 0x00 11. "SSB,Set all status bits inI2C_IRQSTATUS_RAW [14:0]" "SSB_0,SSB_1" rbitfld.word 0x00 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.word 0x00 8. "SCL_I_FUNC,SCL line input value (functional mode)" "SCL_I_FUNC_0_r,SCL_I_FUNC_1_r" newline rbitfld.word 0x00 7. "SCL_O_FUNC,SCL line output value (functional mode)" "SCL_O_FUNC_0_r,SCL_O_FUNC_1_r" rbitfld.word 0x00 6. "SDA_I_FUNC,SDA line input value (functional mode)" "SDA_I_FUNC_0_r,SDA_I_FUNC_1_r" rbitfld.word 0x00 5. "SDA_O_FUNC,SDA line output value (functional mode)" "SDA_O_FUNC_0_r,SDA_O_FUNC_1_r" newline rbitfld.word 0x00 4. "RESERVED,Reserved" "0,1" rbitfld.word 0x00 3. "SCL_I,SCL line sense input value" "SCL_I_0_r,SCL_I_1_r" bitfld.word 0x00 2. "SCL_O,SCL line drive output value" "SCL_O_0,SCL_O_1" newline rbitfld.word 0x00 1. "SDA_I,SDA line sense input value" "SDA_I_0_r,SDA_I_1_r" bitfld.word 0x00 0. "SDA_O,SDA line drive output value" "SDA_O_0,SDA_O_1" rgroup.word 0xC0++0x01 line.word 0x00 "I2C_BUFSTAT,I2C Buffer Status Register" bitfld.word 0x00 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "FIFODEPTH_0_r,FIFODEPTH_1_r,FIFODEPTH_2_r,FIFODEPTH_3_r" bitfld.word 0x00 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.word 0x00 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0xC4++0x01 line.word 0x00 "I2C_OA1,I2C Own Address 1 Register" rbitfld.word 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.word 0x00 0.--9. 1. "OA1,Own address 1" group.word 0xC8++0x01 line.word 0x00 "I2C_OA2,I2C Own Address 2 Register" rbitfld.word 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.word 0x00 0.--9. 1. "OA2,Own address 2" group.word 0xCC++0x01 line.word 0x00 "I2C_OA3,I2C Own Address 3 Register" rbitfld.word 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.word 0x00 0.--9. 1. "OA3,Own address 3" rgroup.word 0xD0++0x01 line.word 0x00 "I2C_ACTOA,I2C Active Own Address Register" hexmask.word 0x00 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x00 3. "OA3_ACT,Own Address 3 active" "OA3_ACT_0_r,OA3_ACT_1_r" bitfld.word 0x00 2. "OA2_ACT,Own Address 2 active" "OA2_ACT_0_r,OA2_ACT_1_r" newline bitfld.word 0x00 1. "OA1_ACT,Own Address 1 active" "OA1_ACT_0_r,OA1_ACT_1_r" bitfld.word 0x00 0. "OA0_ACT,Own Address 0 active" "OA0_ACT_0_r,OA0_ACT_1_r" group.word 0xD4++0x01 line.word 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register" hexmask.word 0x00 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x00 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "OA3_EN_0,OA3_EN_1" bitfld.word 0x00 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "OA2_EN_0,OA2_EN_1" newline bitfld.word 0x00 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "OA1_EN_0,OA1_EN_1" bitfld.word 0x00 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "OA0_EN_0,OA0_EN_1" width 0x0B tree.end repeat.end tree "I2C1_TARG" base ad:0x48071000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "I2C2_TARG" base ad:0x48073000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "IEEE1500_2_OCP_TARG" base ad:0x4A109000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "INSTR_CM_CORE_AON" base ad:0x4A005F00 rgroup.long 0x00++0x03 line.long 0x00 "CMI_IDENTICATION,CM profiling identification register" bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3" bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates a software compatible module family" bitfld.long 0x00 11.--15. "RTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x07 line.long 0x00 "CMI_SYS_CONFIG,CM profiling system configuartion register" hexmask.long 0x00 4.--31. 1. "RESERVED," bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "0,1,2,3" rbitfld.long 0x00 1. "RESERVED," "0,1" bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1" line.long 0x04 "CMI_STATUS,CM profiling status register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "FIFOEMPTY,PM Profiling buffer empty" "0,1" hexmask.long.byte 0x04 0.--7. 1. "RESERVED," group.long 0x24++0x0F line.long 0x00 "CMI_CONFIGURATION,CM profiling configuration register" bitfld.long 0x00 30.--31. "CLAIM_3,Ownership" "0,1,2,3" bitfld.long 0x00 29. "CLAIM_2,Debugger override qualifier" "0,1" rbitfld.long 0x00 28. "CLAIM_1,Current owner" "0,1" hexmask.long.word 0x00 16.--27. 1. "RESERVED," bitfld.long 0x00 15. "MOD_ACT_EN,When HIGH the CM Module Activity collection is enabled" "0,1" newline hexmask.long.byte 0x00 8.--14. 1. "RESERVED," bitfld.long 0x00 7. "EVT_CAPT_EN,When HIGH the CM events capture is enabled" "0,1" hexmask.long.byte 0x00 0.--6. 1. "RESERVED," line.long 0x04 "CMI_CLASS_FILTERING,CM profiling class filtering register" bitfld.long 0x04 31. "SNAP_CAPT_EN_1F,Snapshot capture enable - Class-ID = 0x1F" "0,1" bitfld.long 0x04 30. "SNAP_CAPT_EN_1E," "0,1" bitfld.long 0x04 29. "SNAP_CAPT_EN_1D," "0,1" bitfld.long 0x04 28. "SNAP_CAPT_EN_1C," "0,1" bitfld.long 0x04 27. "SNAP_CAPT_EN_1B," "0,1" newline bitfld.long 0x04 26. "SNAP_CAPT_EN_1A," "0,1" bitfld.long 0x04 25. "SNAP_CAPT_EN_19," "0,1" bitfld.long 0x04 24. "SNAP_CAPT_EN_18," "0,1" bitfld.long 0x04 23. "SNAP_CAPT_EN_17," "0,1" bitfld.long 0x04 22. "SNAP_CAPT_EN_16," "0,1" newline bitfld.long 0x04 21. "SNAP_CAPT_EN_15," "0,1" bitfld.long 0x04 20. "SNAP_CAPT_EN_14," "0,1" bitfld.long 0x04 19. "SNAP_CAPT_EN_13," "0,1" bitfld.long 0x04 18. "SNAP_CAPT_EN_12," "0,1" bitfld.long 0x04 17. "SNAP_CAPT_EN_11," "0,1" newline bitfld.long 0x04 16. "SNAP_CAPT_EN_10,Snapshot capture enable - Class-ID = 0x10" "0,1" hexmask.long.word 0x04 4.--15. 1. "RESERVED," bitfld.long 0x04 3. "SNAP_CAPT_EN_03,Snapshot capture enable - Class-ID = 0x03 [0x23]" "0,1" bitfld.long 0x04 2. "SNAP_CAPT_EN_02,Snapshot capture enable - Class-ID = 0x02 [0x22]" "0,1" bitfld.long 0x04 1. "SNAP_CAPT_EN_01,Snapshot capture enable - Class-ID = 0x01 [0x21]" "0,1" newline bitfld.long 0x04 0. "SNAP_CAPT_EN_00,Snapshot capture enable - Class-ID = 0x00 [0x20]" "0,1" line.long 0x08 "CMI_TRIGGERING,CM profiling triggering control register" hexmask.long 0x08 2.--31. 1. "RESERVED," bitfld.long 0x08 1. "TRIG_STOP_EN,Enable stop capturing CM events from external trigger detection" "0,1" bitfld.long 0x08 0. "TRIG_START_EN,Enable start capturing CM events from external trigger detection" "0,1" line.long 0x0C "CMI_SAMPLING,CM profiling sampling window register" hexmask.long.word 0x0C 20.--31. 1. "RESERVED," bitfld.long 0x0C 16.--19. "FCLK_DIV_FACOR,FunClk divide factor ranging from 1 to 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0C 8.--15. 1. "RESERVED," hexmask.long.byte 0x0C 0.--7. 1. "SAMP_WIND_SIZE,CM events sampling window size" width 0x0B tree.end tree "INSTR_PRM" base ad:0x4AE07F00 rgroup.long 0x00++0x03 line.long 0x00 "PMI_IDENTICATION,PM profiling identification register" bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3" bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates a software compatible module family" bitfld.long 0x00 11.--15. "RTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "0,1,2,3" newline bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x07 line.long 0x00 "PMI_SYS_CONFIG,PM profiling system configuartion register" hexmask.long 0x00 4.--31. 1. "RESERVED," bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "0,1,2,3" rbitfld.long 0x00 1. "RESERVED," "0,1" bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1" line.long 0x04 "PMI_STATUS,PM profiling status register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "FIFOEMPTY,PM Profiling buffer empty" "0,1" hexmask.long.byte 0x04 0.--7. 1. "RESERVED," group.long 0x24++0x0F line.long 0x00 "PMI_CONFIGURATION,PM profiling configuration register" bitfld.long 0x00 30.--31. "CLAIM_3,Ownership" "0,1,2,3" bitfld.long 0x00 29. "CLAIM_2,Debugger override qualifier" "0,1" rbitfld.long 0x00 28. "CLAIM_1,Current owner" "0,1" hexmask.long.tbyte 0x00 8.--27. 1. "RESERVED," bitfld.long 0x00 7. "EVT_CAPT_EN,When HIGH the PM events capture is enabled" "0,1" hexmask.long.byte 0x00 0.--6. 1. "RESERVED," line.long 0x04 "PMI_CLASS_FILTERING,PM profiling class filtering register" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "SNAP_CAPT_EN_03,Snapshot capture enable - Class-ID = 0x03" "0,1" bitfld.long 0x04 2. "SNAP_CAPT_EN_02,Snapshot capture enable - Class-ID = 0x02" "0,1" bitfld.long 0x04 1. "SNAP_CAPT_EN_01,Snapshot capture enable - Class-ID = 0x01" "0,1" bitfld.long 0x04 0. "SNAP_CAPT_EN_00,Snapshot capture enable - Class-ID = 0x00" "0,1" line.long 0x08 "PMI_TRIGGERING,PM profiling triggering control register" hexmask.long 0x08 2.--31. 1. "RESERVED," bitfld.long 0x08 1. "TRIG_STOP_EN,Enable stop capturing PM events from external trigger detection" "0,1" bitfld.long 0x08 0. "TRIG_START_EN,Enable start capturing PM events from external trigger detection" "0,1" line.long 0x0C "PMI_SAMPLING,PM profiling sampling window register" hexmask.long.word 0x0C 20.--31. 1. "RESERVED," bitfld.long 0x0C 16.--19. "FCLK_DIV_FACOR,FunClk divide factor ranging from 1 to 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0C 8.--15. 1. "RESERVED," hexmask.long.byte 0x0C 0.--7. 1. "SAMP_WIND_SIZE,PM events sampling window size" width 0x0B tree.end tree "IPU_C0_RW_TABLE" base ad:0xE00FE000 group.long 0x00++0x07 line.long 0x00 "CORTEXM4_RW_PID1,Peripheral Identification register- allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs)" line.long 0x04 "CORTEXM4_RW_PID2,Peripheral Identification register - allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs)" width 0x0B tree.end tree "IPU_C1_RW_TABLE" base ad:0xE00FE000 group.long 0x00++0x07 line.long 0x00 "CORTEXM4_RW_PID1,Peripheral Identification register- allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs)" line.long 0x04 "CORTEXM4_RW_PID2,Peripheral Identification register - allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs)" width 0x0B tree.end tree "IPU_CM_CORE_AON" base ad:0x4A005500 group.long 0x00++0x0B line.long 0x00 "CM_IPU1_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_IPU1_GFCLK,This field indicates the state of the IPU1_GFCLK clock in the domain" "CLKACTIVITY_IPU1_GFCLK_0,CLKACTIVITY_IPU1_GFCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the IPU1 clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_IPU1_STATICDEP,This register controls the static domain depedencies from IPU domain towards 'target' domains" rbitfld.long 0x04 31. "RESERVED," "0,1" bitfld.long 0x04 30. "CRC_STATDEP,Static dependency towards CRC clock domain" "CRC_STATDEP_0,CRC_STATDEP_1" newline bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE clock domain" "PCIE_STATDEP_0,PCIE_STATDEP_1" bitfld.long 0x04 28. "ISS_STATDEP,Static dependency towards ISS clock domain" "ISS_STATDEP_0,ISS_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain" "GMAC_STATDEP_0,GMAC_STATDEP_1" bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain" "IPU_STATDEP_0,IPU_STATDEP_1" newline rbitfld.long 0x04 23. "RESERVED," "0,1" bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" newline bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain" "EVE1_STATDEP_0,EVE1_STATDEP_1" bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain" "CUSTEFUSE_STATDEP_0,?" rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 11. "SDMA_STATDEP,Static dependency towards DMA clock domain" "SDMA_STATDEP_0,?" bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU clock domain" "GPU_STATDEP_0,GPU_STATDEP_1" newline rbitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain" "CAM_STATDEP_0,?" bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" rbitfld.long 0x04 6. "RESERVED," "0,1" newline bitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "L3MAIN1_STATDEP_0,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 3. "RESERVED," "0,1" bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP clock domain" "DSP1_STATDEP_0,DSP1_STATDEP_1" bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_IPU1_DYNAMICDEP,This register controls the dynamic domain depedencies from IPU domain towards 'target' domains" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.tbyte 0x08 6.--23. 1. "RESERVED," rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20++0x03 line.long 0x00 "CM_IPU1_IPU1_CLKCTRL,This register manages the IPU1 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects the IPU functional clock" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_IPU_CLKSTCTRL,This register enables the IPU domain power state transition" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "CLKACTIVITY_MCASP1_AHCLKR,This field indicates the state of the MCASP1_AHCLKR clock in the domain" "CLKACTIVITY_MCASP1_AHCLKR_0,CLKACTIVITY_MCASP1_AHCLKR_1" newline rbitfld.long 0x00 17. "CLKACTIVITY_MCASP1_AHCLKX,This field indicates the state of the MCASP1_AHCLKX clock in the domain" "CLKACTIVITY_MCASP1_AHCLKX_0,CLKACTIVITY_MCASP1_AHCLKX_1" rbitfld.long 0x00 16. "CLKACTIVITY_MCASP1_AUX_GFCLK,This field indicates the state of the MCASP1_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP1_AUX_GFCLK_0,CLKACTIVITY_MCASP1_AUX_GFCLK_1" newline rbitfld.long 0x00 15. "RESERVED," "0,1" rbitfld.long 0x00 14. "CLKACTIVITY_UART6_GFCLK,This field indicates the state of the UART6_GFCLK clock in the domain" "CLKACTIVITY_UART6_GFCLK_0,CLKACTIVITY_UART6_GFCLK_1" newline rbitfld.long 0x00 13. "CLKACTIVITY_IPU_96M_GFCLK,This field indicates the state of the IPU_96M_GFCLK clock in the domain" "CLKACTIVITY_IPU_96M_GFCLK_0,CLKACTIVITY_IPU_96M_GFCLK_1" rbitfld.long 0x00 12. "CLKACTIVITY_TIMER8_GFCLK,This field indicates the state of the TIMER8_GFCLK clock in the domain" "CLKACTIVITY_TIMER8_GFCLK_0,CLKACTIVITY_TIMER8_GFCLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_TIMER7_GFCLK,This field indicates the state of the TIMER7_GFCLK clock in the domain" "CLKACTIVITY_TIMER7_GFCLK_0,CLKACTIVITY_TIMER7_GFCLK_1" rbitfld.long 0x00 10. "CLKACTIVITY_TIMER6_GFCLK,This field indicates the state of the TIMER6_GFCLK clock in the domain" "CLKACTIVITY_TIMER6_GFCLK_0,CLKACTIVITY_TIMER6_GFCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_TIMER5_GFCLK,This field indicates the state of the TIMER5_GFCLK functional clock in the domain" "CLKACTIVITY_TIMER5_GFCLK_0,CLKACTIVITY_TIMER5_GFCLK_1" rbitfld.long 0x00 8. "CLKACTIVITY_IPU_L3_GICLK,This field indicates the state of the IPU_L3_GICLK interface clock in the domain" "CLKACTIVITY_IPU_L3_GICLK_0,CLKACTIVITY_IPU_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the IPU clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x50++0x03 line.long 0x00 "CM_IPU_MCASP1_CLKCTRL,This register manages the MCASP1 clocks" bitfld.long 0x00 28.--31. "CLKSEL_AHCLKR,Selects reference clock for AHCLKR" "CLKSEL_AHCLKR_0,CLKSEL_AHCLKR_1,CLKSEL_AHCLKR_2,CLKSEL_AHCLKR_3,CLKSEL_AHCLKR_4,CLKSEL_AHCLKR_5,CLKSEL_AHCLKR_6,CLKSEL_AHCLKR_7,CLKSEL_AHCLKR_8,CLKSEL_AHCLKR_9,CLKSEL_AHCLKR_10,CLKSEL_AHCLKR_11,CLKSEL_AHCLKR_12,CLKSEL_AHCLKR_13,CLKSEL_AHCLKR_14,CLKSEL_AHCLKR_15" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" newline bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x00 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x58++0x03 line.long 0x00 "CM_IPU_TIMER5_CLKCTRL,This register manages the TIMER5 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,?,?,?,?" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x60++0x03 line.long 0x00 "CM_IPU_TIMER6_CLKCTRL,This register manages the TIMER6 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,?,?,?,?" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x68++0x03 line.long 0x00 "CM_IPU_TIMER7_CLKCTRL,This register manages the TIMER7 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,?,?,?,?" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x70++0x03 line.long 0x00 "CM_IPU_TIMER8_CLKCTRL,This register manages the TIMER8 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,?,?,?,?" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x78++0x03 line.long 0x00 "CM_IPU_I2C5_CLKCTRL,This register manages the I2C5 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x80++0x03 line.long 0x00 "CM_IPU_UART6_CLKCTRL,This register manages the UART6 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "IPU_FW" base ad:0x4A15B000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" newline rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "IPU_FW_CFG_TARG" base ad:0x4A15C000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "IPU_MMU" base ad:0x55082000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Write 0's for future compatibility" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" rbitfld.long 0x00 5.--7. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x00 2. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" hexmask.long 0x08 5.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" newline bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0_w,EMUMISS_1_r" bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" hexmask.long 0x0C 5.--31. 1. "RESERVED,Write 0's for future compatibility Read returns 0" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" newline bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0,EMUMISS_1" bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" hexmask.long 0x00 1.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" hexmask.long 0x04 4.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable" "TWLENABLE_0,TWLENABLE_1" newline bitfld.long 0x04 1. "MMUENABLE,MMU enable" "MMUENABLE_0,MMUENABLE_1" rbitfld.long 0x04 0. "RESERVED,Write 0's for future compatibility" "0,1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" hexmask.long.byte 0x0C 0.--6. 1. "RESERVED,Write 0's for future compatibility" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 9. "RESERVED,Write 0's for future compatibility" "0,1" newline bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 0.--3. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" hexmask.long 0x14 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x18 4.--11. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x18 3. "P,Preserved bit" "P_0,P_1" newline bitfld.long 0x18 2. "V,Valid bit" "V_0,V_1" bitfld.long 0x18 0.--1. "PAGESIZE,Page size" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x1C 0.--11. 1. "RESERVED,Write 0's for future compatibility" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" hexmask.long 0x20 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" hexmask.long 0x24 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x28 4.--11. 1. "RESERVED,Reads return 0" bitfld.long 0x28 3. "P,Preserved bit" "P_0_r,P_1_r" newline bitfld.long 0x28 2. "V,Valid bit" "V_0_r,V_1_r" bitfld.long 0x28 0.--1. "PAGESIZE,Page size" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x2C 0.--11. 1. "RESERVED,Reads return 0" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" newline rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "0,1,2,3" bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "0,1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" hexmask.long.word 0x08 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" width 0x0B tree.end tree "IPU_PRM" base ad:0x4AE06500 group.long 0x00++0x07 line.long 0x00 "PM_IPU_PWRSTCTRL,This register controls the IPU domain power state to reach upon a domain sleep transition" hexmask.long.word 0x00 22.--31. 1. "RESERVED," rbitfld.long 0x00 20.--21. "PERIPHMEM_ONSTATE,PERIPHMEM memory state when domain is ON" "?,?,?,PERIPHMEM_ONSTATE_3" newline rbitfld.long 0x00 18.--19. "RESERVED," "0,1,2,3" rbitfld.long 0x00 16.--17. "AESSMEM_ONSTATE,AESSMEM memory state when domain is ON" "?,?,?,AESSMEM_ONSTATE_3" newline rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "PERIPHMEM_RETSTATE,PERIPHMEM memory state when domain is RETENTION" "PERIPHMEM_RETSTATE_0,PERIPHMEM_RETSTATE_1" newline rbitfld.long 0x00 9. "RESERVED," "0,1" bitfld.long 0x00 8. "AESSMEM_RETSTATE,AESSMEM memory state when domain is RETENTION" "AESSMEM_RETSTATE_0,AESSMEM_RETSTATE_1" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" rbitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION" "LOGICRETSTATE_0,?" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_IPU_PWRSTST,This register provides a status on the IPU domain current power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 10.--19. 1. "RESERVED," rbitfld.long 0x04 8.--9. "PERIPHMEM_STATEST,PERIPHMEM memory state status" "PERIPHMEM_STATEST_0,PERIPHMEM_STATEST_1,PERIPHMEM_STATEST_2,PERIPHMEM_STATEST_3" newline rbitfld.long 0x04 6.--7. "RESERVED," "0,1,2,3" rbitfld.long 0x04 4.--5. "AESSMEM_STATEST,AESSMEM memory state status" "AESSMEM_STATEST_0,AESSMEM_STATEST_1,AESSMEM_STATEST_2,AESSMEM_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_IPU1_RSTCTRL,This register controls the release of the IPU1 sub-system resets" hexmask.long 0x00 3.--31. 1. "RESERVED," bitfld.long 0x00 2. "RST_IPU,BELLINI system reset control" "RST_IPU_0,RST_IPU_1" newline bitfld.long 0x00 1. "RST_CPU1,BELLINI Cortex M3 CPU1 reset control" "RST_CPU1_0,RST_CPU1_1" bitfld.long 0x00 0. "RST_CPU0,BELLINI Cortex M3 CPU0 reset control" "RST_CPU0_0,RST_CPU0_1" line.long 0x04 "RM_IPU1_RSTST,This register logs the different reset sources of the IPU1 SS" hexmask.long 0x04 7.--31. 1. "RESERVED," bitfld.long 0x04 6. "RST_ICECRUSHER_CPU1,CPU1 has been reset due to IPU ICECRUSHER1 reset source" "RST_ICECRUSHER_CPU1_0,RST_ICECRUSHER_CPU1_1" newline bitfld.long 0x04 5. "RST_ICECRUSHER_CPU0,CPU0 has been reset due to IPU ICECRUSHER0 reset source" "RST_ICECRUSHER_CPU0_0,RST_ICECRUSHER_CPU0_1" bitfld.long 0x04 4. "RST_EMULATION_CPU1,CPU1 has been reset due to emulation reset source e.g" "RST_EMULATION_CPU1_0,RST_EMULATION_CPU1_1" newline bitfld.long 0x04 3. "RST_EMULATION_CPU0,CPU0 has been reset due to emulation reset source e.g" "RST_EMULATION_CPU0_0,RST_EMULATION_CPU0_1" bitfld.long 0x04 2. "RST_IPU,IPU system SW reset status" "RST_IPU_0,RST_IPU_1" newline bitfld.long 0x04 1. "RST_CPU1,CPU1 SW reset status" "RST_CPU1_0,RST_CPU1_1" bitfld.long 0x04 0. "RST_CPU0,CPU0 SW reset status" "RST_CPU0_0,RST_CPU0_1" group.long 0x24++0x03 line.long 0x00 "RM_IPU1_IPU1_CONTEXT,This register contains dedicated IPU1 context statuses" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "LOSTMEM_IPU_L2RAM,Specify if memory-based context in IPU_L2RAM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_IPU_L2RAM_0,LOSTMEM_IPU_L2RAM_1" newline bitfld.long 0x00 8. "LOSTMEM_IPU_UNICACHE,Specify if memory-based context in IPU_UNICACHE memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_IPU_UNICACHE_0,LOSTMEM_IPU_UNICACHE_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x50++0x37 line.long 0x00 "PM_IPU_MCASP1_WKDEP,This register controls wakeup dependency based on MCASP1 service requests" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "WKUPDEP_MCASP1_DMA_DSP2,Wakeup dependency from MCASP1 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_DMA_DSP2_0,WKUPDEP_MCASP1_DMA_DSP2_1" newline rbitfld.long 0x00 14. "RESERVED," "0,1" bitfld.long 0x00 13. "WKUPDEP_MCASP1_DMA_SDMA,Wakeup dependency from MCASP1 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_DMA_SDMA_0,WKUPDEP_MCASP1_DMA_SDMA_1" newline bitfld.long 0x00 12. "WKUPDEP_MCASP1_DMA_DSP1,Wakeup dependency from MCASP1 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_DMA_DSP1_0,WKUPDEP_MCASP1_DMA_DSP1_1" rbitfld.long 0x00 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 9. "WKUPDEP_MCASP1_IRQ_EVE4,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_EVE4_0,WKUPDEP_MCASP1_IRQ_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_MCASP1_IRQ_EVE3,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_EVE3_0,WKUPDEP_MCASP1_IRQ_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_MCASP1_IRQ_EVE2,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_EVE2_0,WKUPDEP_MCASP1_IRQ_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_MCASP1_IRQ_EVE1,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_EVE1_0,WKUPDEP_MCASP1_IRQ_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_MCASP1_IRQ_DSP2,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_DSP2_0,WKUPDEP_MCASP1_IRQ_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_MCASP1_IRQ_IPU1,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_IPU1_0,WKUPDEP_MCASP1_IRQ_IPU1_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" bitfld.long 0x00 2. "WKUPDEP_MCASP1_IRQ_DSP1,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_DSP1_0,WKUPDEP_MCASP1_IRQ_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_MCASP1_IRQ_IPU2,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_IPU2_0,WKUPDEP_MCASP1_IRQ_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_MCASP1_IRQ_MPU,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_MPU_0,WKUPDEP_MCASP1_IRQ_MPU_1" line.long 0x04 "RM_IPU_MCASP1_CONTEXT,This register contains dedicated MCASP context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_IPU_TIMER5_WKDEP,This register controls wakeup dependency based on TIMER5 service requests" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "WKUPDEP_TIMER5_EVE4,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_EVE4_0,WKUPDEP_TIMER5_EVE4_1" newline bitfld.long 0x08 8. "WKUPDEP_TIMER5_EVE3,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_EVE3_0,WKUPDEP_TIMER5_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_TIMER5_EVE2,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_EVE2_0,WKUPDEP_TIMER5_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_TIMER5_EVE1,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_EVE1_0,WKUPDEP_TIMER5_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_TIMER5_DSP2,Wakeup dependency from TIMER5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_DSP2_0,WKUPDEP_TIMER5_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_TIMER5_IPU1,Wakeup dependency from TIMER5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_IPU1_0,WKUPDEP_TIMER5_IPU1_1" rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 2. "WKUPDEP_TIMER5_DSP1,Wakeup dependency from TIMER5 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_DSP1_0,WKUPDEP_TIMER5_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_TIMER5_IPU2,Wakeup dependency from TIMER5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_IPU2_0,WKUPDEP_TIMER5_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_TIMER5_MPU,Wakeup dependency from TIMER5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_MPU_0,WKUPDEP_TIMER5_MPU_1" line.long 0x0C "RM_IPU_TIMER5_CONTEXT,This register contains dedicated TIMER5 context statuses" hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_IPU_TIMER6_WKDEP,This register controls wakeup dependency based on TIMER6 service requests" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED," bitfld.long 0x10 9. "WKUPDEP_TIMER6_EVE4,Wakeup dependency from TIMER6 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_EVE4_0,WKUPDEP_TIMER6_EVE4_1" newline bitfld.long 0x10 8. "WKUPDEP_TIMER6_EVE3,Wakeup dependency from TIMER6 (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_EVE3_0,WKUPDEP_TIMER6_EVE3_1" bitfld.long 0x10 7. "WKUPDEP_TIMER6_EVE2,Wakeup dependency from TIMER6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_EVE2_0,WKUPDEP_TIMER6_EVE2_1" newline bitfld.long 0x10 6. "WKUPDEP_TIMER6_EVE1,Wakeup dependency from TIMER6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_EVE1_0,WKUPDEP_TIMER6_EVE1_1" bitfld.long 0x10 5. "WKUPDEP_TIMER6_DSP2,Wakeup dependency from TIMER6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_DSP2_0,WKUPDEP_TIMER6_DSP2_1" newline bitfld.long 0x10 4. "WKUPDEP_TIMER6_IPU1,Wakeup dependency from TIMER6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_IPU1_0,WKUPDEP_TIMER6_IPU1_1" rbitfld.long 0x10 3. "RESERVED," "0,1" newline bitfld.long 0x10 2. "WKUPDEP_TIMER6_DSP1,Wakeup dependency from TIMER6 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_DSP1_0,WKUPDEP_TIMER6_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_TIMER6_IPU2,Wakeup dependency from TIMER6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_IPU2_0,WKUPDEP_TIMER6_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_TIMER6_MPU,Wakeup dependency from TIMER6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_MPU_0,WKUPDEP_TIMER6_MPU_1" line.long 0x14 "RM_IPU_TIMER6_CONTEXT,This register contains dedicated TIMER6 context statuses" hexmask.long 0x14 1.--31. 1. "RESERVED," bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x18 "PM_IPU_TIMER7_WKDEP,This register controls wakeup dependency based on TIMER7 service requests" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," bitfld.long 0x18 9. "WKUPDEP_TIMER7_EVE4,Wakeup dependency from TIMER7 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_EVE4_0,WKUPDEP_TIMER7_EVE4_1" newline bitfld.long 0x18 8. "WKUPDEP_TIMER7_EVE3,Wakeup dependency from TIMER7 (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_EVE3_0,WKUPDEP_TIMER7_EVE3_1" bitfld.long 0x18 7. "WKUPDEP_TIMER7_EVE2,Wakeup dependency from TIMER7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_EVE2_0,WKUPDEP_TIMER7_EVE2_1" newline bitfld.long 0x18 6. "WKUPDEP_TIMER7_EVE1,Wakeup dependency from TIMER7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_EVE1_0,WKUPDEP_TIMER7_EVE1_1" bitfld.long 0x18 5. "WKUPDEP_TIMER7_DSP2,Wakeup dependency from TIMER7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_DSP2_0,WKUPDEP_TIMER7_DSP2_1" newline bitfld.long 0x18 4. "WKUPDEP_TIMER7_IPU1,Wakeup dependency from TIMER7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_IPU1_0,WKUPDEP_TIMER7_IPU1_1" rbitfld.long 0x18 3. "RESERVED," "0,1" newline bitfld.long 0x18 2. "WKUPDEP_TIMER7_DSP1,Wakeup dependency from TIMER7 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_DSP1_0,WKUPDEP_TIMER7_DSP1_1" bitfld.long 0x18 1. "WKUPDEP_TIMER7_IPU2,Wakeup dependency from TIMER7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_IPU2_0,WKUPDEP_TIMER7_IPU2_1" newline bitfld.long 0x18 0. "WKUPDEP_TIMER7_MPU,Wakeup dependency from TIMER7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_MPU_0,WKUPDEP_TIMER7_MPU_1" line.long 0x1C "RM_IPU_TIMER7_CONTEXT,This register contains dedicated TIMER7 context statuses" hexmask.long 0x1C 1.--31. 1. "RESERVED," bitfld.long 0x1C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x20 "PM_IPU_TIMER8_WKDEP,This register controls wakeup dependency based on TIMER8 service requests" hexmask.long.tbyte 0x20 10.--31. 1. "RESERVED," bitfld.long 0x20 9. "WKUPDEP_TIMER8_EVE4,Wakeup dependency from TIMER8 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_EVE4_0,WKUPDEP_TIMER8_EVE4_1" newline bitfld.long 0x20 8. "WKUPDEP_TIMER8_EVE3,Wakeup dependency from TIMER8 (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_EVE3_0,WKUPDEP_TIMER8_EVE3_1" bitfld.long 0x20 7. "WKUPDEP_TIMER8_EVE2,Wakeup dependency from TIMER8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_EVE2_0,WKUPDEP_TIMER8_EVE2_1" newline bitfld.long 0x20 6. "WKUPDEP_TIMER8_EVE1,Wakeup dependency from TIMER8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_EVE1_0,WKUPDEP_TIMER8_EVE1_1" bitfld.long 0x20 5. "WKUPDEP_TIMER8_DSP2,Wakeup dependency from TIMER8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_DSP2_0,WKUPDEP_TIMER8_DSP2_1" newline bitfld.long 0x20 4. "WKUPDEP_TIMER8_IPU1,Wakeup dependency from TIMER8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_IPU1_0,WKUPDEP_TIMER8_IPU1_1" rbitfld.long 0x20 3. "RESERVED," "0,1" newline bitfld.long 0x20 2. "WKUPDEP_TIMER8_DSP1,Wakeup dependency from TIMER8 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_DSP1_0,WKUPDEP_TIMER8_DSP1_1" bitfld.long 0x20 1. "WKUPDEP_TIMER8_IPU2,Wakeup dependency from TIMER8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_IPU2_0,WKUPDEP_TIMER8_IPU2_1" newline bitfld.long 0x20 0. "WKUPDEP_TIMER8_MPU,Wakeup dependency from TIMER8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_MPU_0,WKUPDEP_TIMER8_MPU_1" line.long 0x24 "RM_IPU_TIMER8_CONTEXT,This register contains dedicated TIMER8 context statuses" hexmask.long 0x24 1.--31. 1. "RESERVED," bitfld.long 0x24 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x28 "PM_IPU_I2C5_WKDEP,This register controls wakeup dependency based on I2C5 service requests" hexmask.long.word 0x28 16.--31. 1. "RESERVED," bitfld.long 0x28 15. "WKUPDEP_I2C5_DMA_DSP2,Wakeup dependency from I2C5 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_DMA_DSP2_0,WKUPDEP_I2C5_DMA_DSP2_1" newline rbitfld.long 0x28 14. "RESERVED," "0,1" bitfld.long 0x28 13. "WKUPDEP_I2C5_DMA_SDMA,Wakeup dependency from I2C5 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_DMA_SDMA_0,WKUPDEP_I2C5_DMA_SDMA_1" newline bitfld.long 0x28 12. "WKUPDEP_I2C5_DMA_DSP1,Wakeup dependency from I2C5 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_DMA_DSP1_0,WKUPDEP_I2C5_DMA_DSP1_1" rbitfld.long 0x28 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x28 9. "WKUPDEP_I2C5_IRQ_EVE4,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_EVE4_0,WKUPDEP_I2C5_IRQ_EVE4_1" bitfld.long 0x28 8. "WKUPDEP_I2C5_IRQ_EVE3,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_EVE3_0,WKUPDEP_I2C5_IRQ_EVE3_1" newline bitfld.long 0x28 7. "WKUPDEP_I2C5_IRQ_EVE2,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_EVE2_0,WKUPDEP_I2C5_IRQ_EVE2_1" bitfld.long 0x28 6. "WKUPDEP_I2C5_IRQ_EVE1,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_EVE1_0,WKUPDEP_I2C5_IRQ_EVE1_1" newline bitfld.long 0x28 5. "WKUPDEP_I2C5_IRQ_DSP2,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_DSP2_0,WKUPDEP_I2C5_IRQ_DSP2_1" bitfld.long 0x28 4. "WKUPDEP_I2C5_IRQ_IPU1,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_IPU1_0,WKUPDEP_I2C5_IRQ_IPU1_1" newline rbitfld.long 0x28 3. "RESERVED," "0,1" bitfld.long 0x28 2. "WKUPDEP_I2C5_IRQ_DSP1,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_DSP1_0,WKUPDEP_I2C5_IRQ_DSP1_1" newline bitfld.long 0x28 1. "WKUPDEP_I2C5_IRQ_IPU2,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_IPU2_0,WKUPDEP_I2C5_IRQ_IPU2_1" bitfld.long 0x28 0. "WKUPDEP_I2C5_IRQ_MPU,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_MPU_0,WKUPDEP_I2C5_IRQ_MPU_1" line.long 0x2C "RM_IPU_I2C5_CONTEXT,This register contains dedicated I2C5 context statuses" hexmask.long 0x2C 1.--31. 1. "RESERVED," bitfld.long 0x2C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x30 "PM_IPU_UART6_WKDEP,This register controls wakeup dependency based on UART6 service requests" hexmask.long.tbyte 0x30 10.--31. 1. "RESERVED," bitfld.long 0x30 9. "WKUPDEP_UART6_EVE4,Wakeup dependency from UART6 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_EVE4_0,WKUPDEP_UART6_EVE4_1" newline bitfld.long 0x30 8. "WKUPDEP_UART6_EVE3,Wakeup dependency from UART6 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_EVE3_0,WKUPDEP_UART6_EVE3_1" bitfld.long 0x30 7. "WKUPDEP_UART6_EVE2,Wakeup dependency from UART6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_EVE2_0,WKUPDEP_UART6_EVE2_1" newline bitfld.long 0x30 6. "WKUPDEP_UART6_EVE1,Wakeup dependency from UART6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_EVE1_0,WKUPDEP_UART6_EVE1_1" bitfld.long 0x30 5. "WKUPDEP_UART6_DSP2,Wakeup dependency from UART6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_DSP2_0,WKUPDEP_UART6_DSP2_1" newline bitfld.long 0x30 4. "WKUPDEP_UART6_IPU1,Wakeup dependency from UART6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_IPU1_0,WKUPDEP_UART6_IPU1_1" bitfld.long 0x30 3. "WKUPDEP_UART6_SDMA,Wakeup dependency from UART6 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_SDMA_0,WKUPDEP_UART6_SDMA_1" newline bitfld.long 0x30 2. "WKUPDEP_UART6_DSP1,Wakeup dependency from UART6 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_DSP1_0,WKUPDEP_UART6_DSP1_1" bitfld.long 0x30 1. "WKUPDEP_UART6_IPU2,Wakeup dependency from UART6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_IPU2_0,WKUPDEP_UART6_IPU2_1" newline bitfld.long 0x30 0. "WKUPDEP_UART6_MPU,Wakeup dependency from UART6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_MPU_0,WKUPDEP_UART6_MPU_1" line.long 0x34 "RM_IPU_UART6_CONTEXT,This register contains dedicated UART6 context statuses" hexmask.long.tbyte 0x34 9.--31. 1. "RESERVED," bitfld.long 0x34 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x34 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 1. "LOSTCONTEXT_RFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x34 0. "RESERVED," "0,1" width 0x0B tree.end tree "IPU_TARG" base ad:0x44001000 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "IPU_UNICACHE_CFG" base ad:0x55080000 group.long 0x04++0x27 line.long 0x00 "CACHE_CONFIG,Configuration Register" hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4. "LOCK_MAIN,Lock access to maintenance registers" "LOCK_MAIN_0,LOCK_MAIN_1" bitfld.long 0x00 3. "LOCK_PORT,Lock access to interface registers" "LOCK_PORT_0,LOCK_PORT_1" newline bitfld.long 0x00 2. "LOCK_INT,Lock access to interrupt registers" "LOCK_INT_0,LOCK_INT_1" bitfld.long 0x00 1. "BYPASS,Bypass cache" "BYPASS_0,BYPASS_1" bitfld.long 0x00 0. "CACHE_LOCK,Unicache lock" "CACHE_LOCK_0,CACHE_LOCK_1" line.long 0x04 "CACHE_INT,Interrupt Register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 5.--8. "PORT,Slave interface number that has recorded an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4. "READ,Interface read response error" "0,1" newline bitfld.long 0x04 3. "WRITE,Interface write response error" "0,1" bitfld.long 0x04 2. "MAINT,Maintenance is completed" "0,1" bitfld.long 0x04 1. "PAGEFAULT,Unicache MMU page fault" "0,1" newline bitfld.long 0x04 0. "CONFIG,Configuration error" "0,1" line.long 0x08 "CACHE_OCP,Interface Configuration Register" hexmask.long 0x08 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 5. "CLEANBUF,Clean write and prefetch buffers in cache" "CLEANBUF_0,CLEANBUF_1" bitfld.long 0x08 4. "PREFETCH,Always prefetch data" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x08 3. "CACHED,Follow cacheable sideband signals" "CACHED_0,CACHED_1" bitfld.long 0x08 2. "WRALLOCATE,Follow write allocate sideband signals" "WRALLOCATE_0,WRALLOCATE_1" bitfld.long 0x08 1. "WRBUFFER,Write throughs and write back no allocate are buffered" "WRBUFFER_0,WRBUFFER_1" newline bitfld.long 0x08 0. "WRAP,OCP wrap mode (critical word first)" "WRAP_0,WRAP_1" line.long 0x0C "CACHE_MAINT,Maintenance Configuration Register" hexmask.long 0x0C 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 5. "INTERRUPT,Generate interrupt when maintenance operation is complete" "INTERRUPT_0,INTERRUPT_1" bitfld.long 0x0C 4. "INVALIDATE,Invalidate lines in region defined by maintenance start/end addresses" "INVALIDATE_0,INVALIDATE_1" newline bitfld.long 0x0C 3. "CLEAN,Evict dirty lines in region defined by maintenance start/end addresses" "CLEAN_0,CLEAN_1" bitfld.long 0x0C 2. "UNLOCK,Unlock region defined by maintenance start/end addresses" "UNLOCK_0,UNLOCK_1" bitfld.long 0x0C 1. "LOCK,Lock region defined by maintenance start/end addresses" "LOCK_0,LOCK_1" newline bitfld.long 0x0C 0. "PRELOAD,Preload region defined by maintenance start/end addresses" "PRELOAD_0,PRELOAD_1" line.long 0x10 "CACHE_MTSTART,Maintenance Start Configuration Register" line.long 0x14 "CACHE_MTEND,Maintenance End Configuration Register" line.long 0x18 "CACHE_CTADDR,Cache Test Address Register" line.long 0x1C "CACHE_CTDATA,Cache Test Data Register" line.long 0x20 "ECC_CFG,ECC configuration register" hexmask.long.tbyte 0x20 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 14. "L2RAM_SEC_AUTO_EN,Enables auto-correction of data in case of SEC error in L2 RAM" "0,1" bitfld.long 0x20 13. "L2RAM_SRESP_EN,Enables error response to master in case of DED error in L2 RAM" "0,1" newline bitfld.long 0x20 12. "L2RAM_DATA_MASK,L2 RAM ECC Code Mask register" "0,1" bitfld.long 0x20 11. "L2RAM_CODE_MASK,L2 RAM ECC Code Mask register" "0,1" bitfld.long 0x20 10. "L2RAM_ECC_EN,L2 RAM ECC enable" "0,1" newline bitfld.long 0x20 9. "L1TAG_SEC_AUTO_EN,Enables auto-correction of data in case of SEC error in L1 Tag" "0,1" bitfld.long 0x20 8. "RESERVED,Reserved" "0,1" bitfld.long 0x20 7. "L1TAG_DATA_MASK,L1 Tag ECC Code Mask register" "0,1" newline bitfld.long 0x20 6. "L1TAG_CODE_MASK,L1 Tag ECC Code Mask register" "0,1" bitfld.long 0x20 5. "L1TAG_ECC_EN,L1 Tag ECC enable" "0,1" bitfld.long 0x20 4. "L1DATA_SEC_AUTO_EN,Enables auto-correction of data in case of SEC error in L1 Data" "0,1" newline bitfld.long 0x20 3. "L1DATA_SRESP_EN,Enables error response to master in case of DED error in L1 Data" "0,1" bitfld.long 0x20 2. "L1DATA_DATA_MASK,L1 Data ECC Code Mask register" "0,1" bitfld.long 0x20 1. "L1DATA_CODE_MASK,L1 Data ECC Code Mask register" "0,1" newline bitfld.long 0x20 0. "L1DATA_ECC_EN,L1 Data ECC enable" "0,1" line.long 0x24 "L1DATA_ERR_INFO,L1 Data ECC information register" hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 3. "ACCESS_TYPE,Indicates what access type resulted in ECC error in L1 Data" "indicates access other..,eviction" bitfld.long 0x24 2. "DED,Indicates DED error in L1 Data" "0,1" newline bitfld.long 0x24 1. "CODE_ERR,Indicates SEC error in ECC code area of memory in L1 Data" "0,1" bitfld.long 0x24 0. "SEC,Indicates SEC error in L1 Data" "0,1" rgroup.long 0x30++0x07 line.long 0x00 "L1DATA_ERR_ADDR_LOC,Indicates address location of error occurence in L1 Data" line.long 0x04 "L1TAG_ERR_INFO,L1 Tag ECC information register" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 3. "ACCESS_TYPE,Indicates what access type resulted in ECC error in L1 Tag" "indicates access other..,eviction" bitfld.long 0x04 2. "DED,Indicates DED error in L1 Tag" "0,1" newline bitfld.long 0x04 1. "CODE_ERR,Indicates SEC error in ECC code area of memory in L1 Tag" "0,1" bitfld.long 0x04 0. "SEC,Indicates SEC error in L1 Tag" "0,1" rgroup.long 0x3C++0x07 line.long 0x00 "L1TAG_ERR_ADDR_LOC,Indicates address location of error occurence in L1 Data" line.long 0x04 "L2RAM_ERR_INFO,L2 RAM ECC information register" hexmask.long 0x04 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 5. "ACCESS_TYPE_MPORT,This bit is set whenever an access is made to L2RAM via the slave configuration interface" "0,1" bitfld.long 0x04 4. "ACCESS_TYPE_CACHE1,This bit is set whenever an access is made to L2RAM via the Unicache interface" "0,1" newline bitfld.long 0x04 3. "ACCESS_TYPE_CACHE2,This bit is reserved since L2 cache is not implemented in IPU subsystem" "0,1" bitfld.long 0x04 2. "DED,Indicates DED error in L2 RAM" "0,1" bitfld.long 0x04 1. "CODE_ERR,Indicates SEC error in ECC code area of memory in L2 RAM" "0,1" newline bitfld.long 0x04 0. "SEC,Indicates SEC error in L2 RAM" "0,1" rgroup.long 0x48++0x03 line.long 0x00 "L2RAM_ERR_ADDR_LOC,Indicates address location of error occurence in L2 RAM" width 0x0B tree.end tree "IPU_UNICACHE_MMU" base ad:0x55080800 group.long 0x00++0x0F line.long 0x00 "CACHE_MMU_LARGE_ADDR_i_0,Large page address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source address" hexmask.long 0x00 0.--24. 1. "RESERVED,Reserved" line.long 0x04 "CACHE_MMU_LARGE_ADDR_i_1,Large page address" hexmask.long.byte 0x04 25.--31. 1. "ADDRESS,Logical source address" hexmask.long 0x04 0.--24. 1. "RESERVED,Reserved" line.long 0x08 "CACHE_MMU_LARGE_ADDR_i_2,Large page address" hexmask.long.byte 0x08 25.--31. 1. "ADDRESS,Logical source address" hexmask.long 0x08 0.--24. 1. "RESERVED,Reserved" line.long 0x0C "CACHE_MMU_LARGE_ADDR_i_3,Large page address" hexmask.long.byte 0x0C 25.--31. 1. "ADDRESS,Logical source address" hexmask.long 0x0C 0.--24. 1. "RESERVED,Reserved" group.long 0x20++0x0F line.long 0x00 "CACHE_MMU_LARGE_XLTE_i_0,Large page translated address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.tbyte 0x00 1.--24. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" line.long 0x04 "CACHE_MMU_LARGE_XLTE_i_1,Large page translated address" hexmask.long.byte 0x04 25.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.tbyte 0x04 1.--24. 1. "RESERVED,Reserved" bitfld.long 0x04 0. "IGNORE,Do not use translated address" "0,1" line.long 0x08 "CACHE_MMU_LARGE_XLTE_i_2,Large page translated address" hexmask.long.byte 0x08 25.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.tbyte 0x08 1.--24. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "IGNORE,Do not use translated address" "0,1" line.long 0x0C "CACHE_MMU_LARGE_XLTE_i_3,Large page translated address" hexmask.long.byte 0x0C 25.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.tbyte 0x0C 1.--24. 1. "RESERVED,Reserved" bitfld.long 0x0C 0. "IGNORE,Do not use translated address" "0,1" group.long 0x40++0x0F line.long 0x00 "CACHE_MMU_LARGE_POLICY_i_0,Large page policy" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x00 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" newline bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" rbitfld.long 0x00 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x04 "CACHE_MMU_LARGE_POLICY_i_1,Large page policy" hexmask.long.word 0x04 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x04 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x04 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x04 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x04 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x04 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x04 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" newline bitfld.long 0x04 5. "READ,Read only" "0,1" bitfld.long 0x04 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x04 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" rbitfld.long 0x04 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x04 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x08 "CACHE_MMU_LARGE_POLICY_i_2,Large page policy" hexmask.long.word 0x08 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x08 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x08 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x08 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x08 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x08 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" newline bitfld.long 0x08 5. "READ,Read only" "0,1" bitfld.long 0x08 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x08 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" rbitfld.long 0x08 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x08 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x0C "CACHE_MMU_LARGE_POLICY_i_3,Large page policy" hexmask.long.word 0x0C 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x0C 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x0C 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x0C 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x0C 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x0C 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" newline bitfld.long 0x0C 5. "READ,Read only" "0,1" bitfld.long 0x0C 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x0C 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" rbitfld.long 0x0C 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x0C 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x60++0x07 line.long 0x00 "CACHE_MMU_MED_ADDR_j_0,Medium page address" hexmask.long.word 0x00 17.--31. 1. "ADDRESS,Logical source address" hexmask.long.tbyte 0x00 0.--16. 1. "RESERVED,Reserved" line.long 0x04 "CACHE_MMU_MED_ADDR_j_1,Medium page address" hexmask.long.word 0x04 17.--31. 1. "ADDRESS,Logical source address" hexmask.long.tbyte 0x04 0.--16. 1. "RESERVED,Reserved" group.long 0xA0++0x07 line.long 0x00 "CACHE_MMU_MED_XLTE_j_0,Medium page translated address" hexmask.long.word 0x00 17.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x00 1.--16. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" line.long 0x04 "CACHE_MMU_MED_XLTE_j_1,Medium page translated address" hexmask.long.word 0x04 17.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x04 1.--16. 1. "RESERVED,Reserved" bitfld.long 0x04 0. "IGNORE,Do not use translated address" "0,1" group.long 0xE0++0x07 line.long 0x00 "CACHE_MMU_MED_POLICY_j_0,Medium page policy" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x00 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" newline bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x04 "CACHE_MMU_MED_POLICY_j_1,Medium page policy" hexmask.long.word 0x04 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x04 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x04 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x04 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x04 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x04 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x04 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" newline bitfld.long 0x04 5. "READ,Read only" "0,1" bitfld.long 0x04 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x04 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x04 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x04 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x120++0x27 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_0,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reserved" line.long 0x04 "CACHE_MMU_SMALL_ADDR_k_1,Small page address" hexmask.long.tbyte 0x04 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x04 0.--11. 1. "RESERVED,Reserved" line.long 0x08 "CACHE_MMU_SMALL_ADDR_k_2,Small page address" hexmask.long.tbyte 0x08 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x08 0.--11. 1. "RESERVED,Reserved" line.long 0x0C "CACHE_MMU_SMALL_ADDR_k_3,Small page address" hexmask.long.tbyte 0x0C 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x0C 0.--11. 1. "RESERVED,Reserved" line.long 0x10 "CACHE_MMU_SMALL_ADDR_k_4,Small page address" hexmask.long.tbyte 0x10 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x10 0.--11. 1. "RESERVED,Reserved" line.long 0x14 "CACHE_MMU_SMALL_ADDR_k_5,Small page address" hexmask.long.tbyte 0x14 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x14 0.--11. 1. "RESERVED,Reserved" line.long 0x18 "CACHE_MMU_SMALL_ADDR_k_6,Small page address" hexmask.long.tbyte 0x18 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x18 0.--11. 1. "RESERVED,Reserved" line.long 0x1C "CACHE_MMU_SMALL_ADDR_k_7,Small page address" hexmask.long.tbyte 0x1C 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x1C 0.--11. 1. "RESERVED,Reserved" line.long 0x20 "CACHE_MMU_SMALL_ADDR_k_8,Small page address" hexmask.long.tbyte 0x20 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x20 0.--11. 1. "RESERVED,Reserved" line.long 0x24 "CACHE_MMU_SMALL_ADDR_k_9,Small page address" hexmask.long.tbyte 0x24 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x24 0.--11. 1. "RESERVED,Reserved" group.long 0x1A0++0x27 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_0,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" line.long 0x04 "CACHE_MMU_SMALL_XLTE_k_1,Small page translated address" hexmask.long.tbyte 0x04 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x04 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x04 0. "IGNORE,Do not use translated address" "0,1" line.long 0x08 "CACHE_MMU_SMALL_XLTE_k_2,Small page translated address" hexmask.long.tbyte 0x08 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x08 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "IGNORE,Do not use translated address" "0,1" line.long 0x0C "CACHE_MMU_SMALL_XLTE_k_3,Small page translated address" hexmask.long.tbyte 0x0C 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x0C 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x0C 0. "IGNORE,Do not use translated address" "0,1" line.long 0x10 "CACHE_MMU_SMALL_XLTE_k_4,Small page translated address" hexmask.long.tbyte 0x10 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x10 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x10 0. "IGNORE,Do not use translated address" "0,1" line.long 0x14 "CACHE_MMU_SMALL_XLTE_k_5,Small page translated address" hexmask.long.tbyte 0x14 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x14 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x14 0. "IGNORE,Do not use translated address" "0,1" line.long 0x18 "CACHE_MMU_SMALL_XLTE_k_6,Small page translated address" hexmask.long.tbyte 0x18 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x18 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x18 0. "IGNORE,Do not use translated address" "0,1" line.long 0x1C "CACHE_MMU_SMALL_XLTE_k_7,Small page translated address" hexmask.long.tbyte 0x1C 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x1C 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x1C 0. "IGNORE,Do not use translated address" "0,1" line.long 0x20 "CACHE_MMU_SMALL_XLTE_k_8,Small page translated address" hexmask.long.tbyte 0x20 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x20 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x20 0. "IGNORE,Do not use translated address" "0,1" line.long 0x24 "CACHE_MMU_SMALL_XLTE_k_9,Small page translated address" hexmask.long.tbyte 0x24 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x24 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x24 0. "IGNORE,Do not use translated address" "0,1" group.long 0x220++0x27 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_0,Small page policy" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x00 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x00 2. "RESERVED,Reserved" "0,1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x04 "CACHE_MMU_SMALL_POLICY_k_1,Small page policy" hexmask.long.word 0x04 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x04 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x04 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x04 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x04 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x04 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x04 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x04 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x04 5. "READ,Read only" "0,1" bitfld.long 0x04 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x04 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x04 2. "RESERVED,Reserved" "0,1" bitfld.long 0x04 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x04 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x08 "CACHE_MMU_SMALL_POLICY_k_2,Small page policy" hexmask.long.word 0x08 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x08 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x08 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x08 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x08 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x08 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x08 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x08 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x08 5. "READ,Read only" "0,1" bitfld.long 0x08 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x08 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x08 2. "RESERVED,Reserved" "0,1" bitfld.long 0x08 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x08 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x0C "CACHE_MMU_SMALL_POLICY_k_3,Small page policy" hexmask.long.word 0x0C 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x0C 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x0C 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x0C 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x0C 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x0C 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x0C 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x0C 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x0C 5. "READ,Read only" "0,1" bitfld.long 0x0C 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x0C 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x0C 2. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x0C 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x10 "CACHE_MMU_SMALL_POLICY_k_4,Small page policy" hexmask.long.word 0x10 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x10 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x10 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x10 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x10 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x10 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x10 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x10 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x10 5. "READ,Read only" "0,1" bitfld.long 0x10 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x10 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x10 2. "RESERVED,Reserved" "0,1" bitfld.long 0x10 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x10 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x14 "CACHE_MMU_SMALL_POLICY_k_5,Small page policy" hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x14 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x14 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x14 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x14 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x14 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x14 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x14 5. "READ,Read only" "0,1" bitfld.long 0x14 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x14 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x14 2. "RESERVED,Reserved" "0,1" bitfld.long 0x14 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x14 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x18 "CACHE_MMU_SMALL_POLICY_k_6,Small page policy" hexmask.long.word 0x18 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x18 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x18 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x18 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x18 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x18 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x18 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x18 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x18 5. "READ,Read only" "0,1" bitfld.long 0x18 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x18 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x18 2. "RESERVED,Reserved" "0,1" bitfld.long 0x18 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x18 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x1C "CACHE_MMU_SMALL_POLICY_k_7,Small page policy" hexmask.long.word 0x1C 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x1C 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x1C 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x1C 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x1C 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x1C 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x1C 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x1C 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x1C 5. "READ,Read only" "0,1" bitfld.long 0x1C 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x1C 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x1C 2. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x1C 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x20 "CACHE_MMU_SMALL_POLICY_k_8,Small page policy" hexmask.long.word 0x20 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x20 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x20 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x20 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x20 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x20 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x20 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x20 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x20 5. "READ,Read only" "0,1" bitfld.long 0x20 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x20 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x20 2. "RESERVED,Reserved" "0,1" bitfld.long 0x20 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x20 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x24 "CACHE_MMU_SMALL_POLICY_k_9,Small page policy" hexmask.long.word 0x24 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x24 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x24 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x24 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x24 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x24 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x24 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x24 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x24 5. "READ,Read only" "0,1" bitfld.long 0x24 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x24 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x24 2. "RESERVED,Reserved" "0,1" bitfld.long 0x24 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x24 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x2A0++0x27 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_0,Small page maintenance configuration" hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x00 1. "LOCK,Lock page" "0,1" bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" line.long 0x04 "CACHE_MMU_SMALL_MAINT_k_1,Small page maintenance configuration" hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x04 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x04 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x04 1. "LOCK,Lock page" "0,1" bitfld.long 0x04 0. "PRELOAD,Preload page" "0,1" line.long 0x08 "CACHE_MMU_SMALL_MAINT_k_2,Small page maintenance configuration" hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x08 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x08 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x08 1. "LOCK,Lock page" "0,1" bitfld.long 0x08 0. "PRELOAD,Preload page" "0,1" line.long 0x0C "CACHE_MMU_SMALL_MAINT_k_3,Small page maintenance configuration" hexmask.long 0x0C 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x0C 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x0C 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x0C 1. "LOCK,Lock page" "0,1" bitfld.long 0x0C 0. "PRELOAD,Preload page" "0,1" line.long 0x10 "CACHE_MMU_SMALL_MAINT_k_4,Small page maintenance configuration" hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x10 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x10 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x10 1. "LOCK,Lock page" "0,1" bitfld.long 0x10 0. "PRELOAD,Preload page" "0,1" line.long 0x14 "CACHE_MMU_SMALL_MAINT_k_5,Small page maintenance configuration" hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x14 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x14 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x14 1. "LOCK,Lock page" "0,1" bitfld.long 0x14 0. "PRELOAD,Preload page" "0,1" line.long 0x18 "CACHE_MMU_SMALL_MAINT_k_6,Small page maintenance configuration" hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x18 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x18 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x18 1. "LOCK,Lock page" "0,1" bitfld.long 0x18 0. "PRELOAD,Preload page" "0,1" line.long 0x1C "CACHE_MMU_SMALL_MAINT_k_7,Small page maintenance configuration" hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x1C 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x1C 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x1C 1. "LOCK,Lock page" "0,1" bitfld.long 0x1C 0. "PRELOAD,Preload page" "0,1" line.long 0x20 "CACHE_MMU_SMALL_MAINT_k_8,Small page maintenance configuration" hexmask.long 0x20 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x20 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x20 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x20 1. "LOCK,Lock page" "0,1" bitfld.long 0x20 0. "PRELOAD,Preload page" "0,1" line.long 0x24 "CACHE_MMU_SMALL_MAINT_k_9,Small page maintenance configuration" hexmask.long 0x24 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x24 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x24 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x24 1. "LOCK,Lock page" "0,1" bitfld.long 0x24 0. "PRELOAD,Preload page" "0,1" group.long 0x4A8++0x13 line.long 0x00 "CACHE_MMU_MAINT,Maintenance configuration register" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 10. "G_FLUSH,Global flush bit" "G_FLUSH_0,G_FLUSH_1" bitfld.long 0x00 8.--9. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x00 7. "L1_CACHE1,Do maintenance operation in L1 cache" "L1_CACHE1_0,L1_CACHE1_1" newline bitfld.long 0x00 6. "CPU_INTERRUPT,Generate interrupt to cpu when maintenance operation initiated by CPU is complete" "CPU_INTERRUPT_0,CPU_INTERRUPT_1" bitfld.long 0x00 5. "HOST_INTERRUPT,Generate interrupt when maintenance operation is complete" "HOST_INTERRUPT_0,HOST_INTERRUPT_1" bitfld.long 0x00 4. "INVALIDATE,Invalidate lines in region defined by maintenance start/end addresses" "INVALIDATE_0,INVALIDATE_1" bitfld.long 0x00 3. "CLEAN,Evict dirty lines in region defined by maintenance start/end addresses" "CLEAN_0,CLEAN_1" newline bitfld.long 0x00 2. "UNLOCK,Unlock region defined by maintenance start/end addresses" "UNLOCK_0,UNLOCK_1" bitfld.long 0x00 1. "LOCK,Lock region defined by maintenance start/end addresses" "LOCK_0,LOCK_1" bitfld.long 0x00 0. "PRELOAD,Preload region defined by maintenance start/end addresses" "PRELOAD_0,PRELOAD_1" line.long 0x04 "CACHE_MMU_MTSTART,Maintenance start configuratoin register" line.long 0x08 "CACHE_MMU_MTEND,Maintenance end configuration register" line.long 0x0C "CACHE_MMU_MAINTST,Maintenance status register" hexmask.long 0x0C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 0. "STATUS,Status bit" "STATUS_0_r,STATUS_1_r" line.long 0x10 "CACHE_MMU_MMUCONFIG,MMU configuration register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "PRIVILEGE,Privilege bit" "PRIVILEGE_0,PRIVILEGE_1" bitfld.long 0x10 0. "MMU_LOCK,MMU lock" "MMU_LOCK_0,MMU_LOCK_1" width 0x0B tree.end tree "IPU_UNICACHE_SCTM" base ad:0x55080400 group.long 0x00++0x03 line.long 0x00 "CACHE_SCTM_CTCNTL," rbitfld.long 0x00 26.--31. "NUMSTM,Number of timers that can export via STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 18.--25. 1. "NUMINPT,Number of event input signals" rbitfld.long 0x00 13.--17. "NUMTIMR,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 7.--12. "NUMCNTR,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 3.--6. "REVISION,Revision ID of SCTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. "IDLEMODE,Idle mode control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 0. "ENBL,SCTM global enable" "ENBL_0,ENBL_1" group.long 0x40++0x07 line.long 0x00 "CACHE_SCTM_TINTVLR_i_0,These registers contain the interval match value for the corresponding timers in the SCTM" line.long 0x04 "CACHE_SCTM_TINTVLR_i_1,These registers contain the interval match value for the corresponding timers in the SCTM" rgroup.long 0x7C++0x03 line.long 0x00 "CACHE_SCTM_CTDBGNUM,Counter Timer Number Debug Event Register" hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0.--2. "NUMEVT,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" group.long 0xF0++0x03 line.long 0x00 "CACHE_SCTM_CTGNBL,These registers provide for simultaneous enable/disable of 32 counters" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x00 0.--7. 1. "ENABLE,The counter enable bit field" group.long 0xF8++0x03 line.long 0x00 "CACHE_SCTM_CTGRST,These registers provide for simultaneous reset of 32 counters" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x00 0.--7. 1. "RESET,The counter reset bit field" group.long 0x100++0x1F line.long 0x00 "CACHE_SCTM_CTCR_WT_i_0,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection1-31: Index of event input signal selected" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 11.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "RESTART_0,RESTART_1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "DBG_0,DBG_1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "INT_0,INT_1" newline rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "OVRFLW_0,OVRFLW_1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" newline bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" line.long 0x04 "CACHE_SCTM_CTCR_WT_i_1,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x04 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 16.--20. "INPSEL,Counter Timer input selection1-31: Index of event input signal selected" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 11.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 10. "RESTART,Restart the timer after an interval match" "RESTART_0,RESTART_1" bitfld.long 0x04 9. "DBG,Signal debug logic on interval match" "DBG_0,DBG_1" bitfld.long 0x04 8. "INT,Generate interrupt on interval match" "INT_0,INT_1" newline rbitfld.long 0x04 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x04 6. "OVRFLW,Counter has wrapped since it was last" "OVRFLW_0,OVRFLW_1" bitfld.long 0x04 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x04 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x04 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x04 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" newline bitfld.long 0x04 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x04 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" line.long 0x08 "CACHE_SCTM_CTCR_WOT_j_0,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x08 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 16.--20. "INPSEL,Counter input selection1-31: Index of event input signal selected" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" hexmask.long.byte 0x08 8.--15. 1. "RESERVED,Reserved" rbitfld.long 0x08 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x08 6. "OVRFLW,Counter has wrapped since it was last" "OVRFLW_0,OVRFLW_1" bitfld.long 0x08 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" newline bitfld.long 0x08 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x08 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x08 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x08 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x08 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" line.long 0x0C "CACHE_SCTM_CTCR_WOT_j_1,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x0C 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 16.--20. "INPSEL,Counter input selection1-31: Index of event input signal selected" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" hexmask.long.byte 0x0C 8.--15. 1. "RESERVED,Reserved" rbitfld.long 0x0C 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x0C 6. "OVRFLW,Counter has wrapped since it was last" "OVRFLW_0,OVRFLW_1" bitfld.long 0x0C 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" newline bitfld.long 0x0C 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x0C 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x0C 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x0C 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x0C 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" line.long 0x10 "CACHE_SCTM_CTCR_WOT_j_2,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x10 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 16.--20. "INPSEL,Counter input selection1-31: Index of event input signal selected" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" hexmask.long.byte 0x10 8.--15. 1. "RESERVED,Reserved" rbitfld.long 0x10 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x10 6. "OVRFLW,Counter has wrapped since it was last" "OVRFLW_0,OVRFLW_1" bitfld.long 0x10 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" newline bitfld.long 0x10 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x10 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x10 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x10 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x10 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" line.long 0x14 "CACHE_SCTM_CTCR_WOT_j_3,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x14 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 16.--20. "INPSEL,Counter input selection1-31: Index of event input signal selected" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" hexmask.long.byte 0x14 8.--15. 1. "RESERVED,Reserved" rbitfld.long 0x14 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x14 6. "OVRFLW,Counter has wrapped since it was last" "OVRFLW_0,OVRFLW_1" bitfld.long 0x14 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" newline bitfld.long 0x14 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x14 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x14 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x14 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x14 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" line.long 0x18 "CACHE_SCTM_CTCR_WOT_j_4,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x18 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 16.--20. "INPSEL,Counter input selection1-31: Index of event input signal selected" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" hexmask.long.byte 0x18 8.--15. 1. "RESERVED,Reserved" rbitfld.long 0x18 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x18 6. "OVRFLW,Counter has wrapped since it was last" "OVRFLW_0,OVRFLW_1" bitfld.long 0x18 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" newline bitfld.long 0x18 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x18 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x18 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x18 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x18 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" line.long 0x1C "CACHE_SCTM_CTCR_WOT_j_5,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x1C 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 16.--20. "INPSEL,Counter input selection1-31: Index of event input signal selected" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" hexmask.long.byte 0x1C 8.--15. 1. "RESERVED,Reserved" rbitfld.long 0x1C 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x1C 6. "OVRFLW,Counter has wrapped since it was last" "OVRFLW_0,OVRFLW_1" bitfld.long 0x1C 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" newline bitfld.long 0x1C 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x1C 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x1C 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x1C 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x1C 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" rgroup.long 0x180++0x1F line.long 0x00 "CACHE_SCTM_CTCNTR_k_0,These registers contain the value of an individual counter in the module" line.long 0x04 "CACHE_SCTM_CTCNTR_k_1,These registers contain the value of an individual counter in the module" line.long 0x08 "CACHE_SCTM_CTCNTR_k_2,These registers contain the value of an individual counter in the module" line.long 0x0C "CACHE_SCTM_CTCNTR_k_3,These registers contain the value of an individual counter in the module" line.long 0x10 "CACHE_SCTM_CTCNTR_k_4,These registers contain the value of an individual counter in the module" line.long 0x14 "CACHE_SCTM_CTCNTR_k_5,These registers contain the value of an individual counter in the module" line.long 0x18 "CACHE_SCTM_CTCNTR_k_6,These registers contain the value of an individual counter in the module" line.long 0x1C "CACHE_SCTM_CTCNTR_k_7,These registers contain the value of an individual counter in the module" width 0x0B tree.end tree "IPU_WUGEN" base ad:0x55081000 group.long 0x00++0x13 line.long 0x00 "CORTEXM4_CTRL_REG,The register is used by one CPU to interrupt the other. thus used as a handshake between the two CPUs" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "INT_CORTEX_2,Interrupt to IPU_C1" "0,1" hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "INT_CORTEX_1,Interrupt to IPU_C0" "0,1" line.long 0x04 "STANDBY_CORE_SYSCONFIG,Standby protocol" hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 0.--1. "STANDBYMODE," "?,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" line.long 0x08 "IDLE_CORE_SYSCONFIG,Idle protocol" hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0.--1. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" line.long 0x0C "WUGEN_MEVT0,This register contains the interrupt mask (LSB) wake-up enable bit per interrupt request" bitfld.long 0x0C 31. "MIRQ31,Interrupt Mask bit 31" "0,1" bitfld.long 0x0C 30. "MIRQ30,Interrupt Mask bit 30" "0,1" bitfld.long 0x0C 29. "MIRQ29,Interrupt Mask bit 29" "0,1" bitfld.long 0x0C 28. "MIRQ28,Interrupt Mask bit 28" "0,1" bitfld.long 0x0C 27. "MIRQ27,Interrupt Mask bit 27" "0,1" bitfld.long 0x0C 26. "MIRQ26,Interrupt Mask bit 26" "0,1" newline bitfld.long 0x0C 25. "MIRQ25,Interrupt Mask bit 25" "0,1" bitfld.long 0x0C 24. "MIRQ24,Interrupt Mask bit 24" "0,1" bitfld.long 0x0C 23. "MIRQ23,Interrupt Mask bit 23" "0,1" bitfld.long 0x0C 22. "MIRQ22,Interrupt Mask bit 22" "0,1" bitfld.long 0x0C 21. "MIRQ21,Interrupt Mask bit 21" "0,1" bitfld.long 0x0C 20. "MIRQ20,Interrupt Mask bit 20" "0,1" newline bitfld.long 0x0C 19. "MIRQ19,Interrupt Mask bit 19" "0,1" bitfld.long 0x0C 18. "MIRQ18,Interrupt Mask bit 18" "0,1" bitfld.long 0x0C 17. "MIRQ17,Interrupt Mask bit 17" "0,1" bitfld.long 0x0C 16. "MIRQ16,Interrupt Mask bit 16" "0,1" bitfld.long 0x0C 15. "MIRQ15,Interrupt Mask bit 15" "0,1" bitfld.long 0x0C 14. "MIRQ14,Interrupt Mask bit 14" "0,1" newline bitfld.long 0x0C 13. "MIRQ13,Interrupt Mask bit 13" "0,1" bitfld.long 0x0C 12. "MIRQ12,Interrupt Mask bit 12" "0,1" bitfld.long 0x0C 11. "MIRQ11,Interrupt Mask bit 11" "0,1" bitfld.long 0x0C 10. "MIRQ10,Interrupt Mask bit 10" "0,1" bitfld.long 0x0C 9. "MIRQ9,Interrupt Mask bit 9" "0,1" bitfld.long 0x0C 8. "MIRQ8,Interrupt Mask bit 8" "0,1" newline bitfld.long 0x0C 7. "MIRQ7,Interrupt Mask bit 7" "0,1" bitfld.long 0x0C 6. "MIRQ6,Interrupt Mask bit 6" "0,1" bitfld.long 0x0C 5. "MIRQ5,Interrupt Mask bit 5" "0,1" bitfld.long 0x0C 4. "MIRQ4,Interrupt Mask bit 4" "0,1" bitfld.long 0x0C 3. "MIRQ3,Interrupt Mask bit 3" "0,1" bitfld.long 0x0C 2. "MIRQ2,Interrupt Mask bit 2" "0,1" newline bitfld.long 0x0C 1. "MIRQ1,Interrupt Mask bit 1" "0,1" bitfld.long 0x0C 0. "MIRQ0,Interrupt Mask bit 0" "0,1" line.long 0x10 "WUGEN_MEVT1,This register contains the interrupt mask (MSB) wake-up enable bit per interrupt request" bitfld.long 0x10 31. "MIRQ63,Interrupt Mask bit 63" "0,1" bitfld.long 0x10 30. "MIRQ62,Interrupt Mask bit 62" "0,1" bitfld.long 0x10 29. "MIRQ61,Interrupt Mask bit 61" "0,1" bitfld.long 0x10 28. "MIRQ60,Interrupt Mask bit 60" "0,1" bitfld.long 0x10 27. "MIRQ59,Interrupt Mask bit 59" "0,1" bitfld.long 0x10 26. "MIRQ58,Interrupt Mask bit 58" "0,1" newline bitfld.long 0x10 25. "MIRQ57,Interrupt Mask bit 57" "0,1" bitfld.long 0x10 24. "MIRQ56,Interrupt Mask bit 56" "0,1" bitfld.long 0x10 23. "MIRQ55,Interrupt Mask bit 55" "0,1" bitfld.long 0x10 22. "MIRQ54,Interrupt Mask bit 54" "0,1" bitfld.long 0x10 21. "MIRQ53,Interrupt Mask bit 53" "0,1" bitfld.long 0x10 20. "MIRQ52,Interrupt Mask bit 52" "0,1" newline bitfld.long 0x10 19. "MIRQ51,Interrupt Mask bit 51" "0,1" bitfld.long 0x10 18. "MIRQ50,Interrupt Mask bit 50" "0,1" bitfld.long 0x10 17. "MIRQ49,Interrupt Mask bit 49" "0,1" bitfld.long 0x10 16. "MIRQ48,Interrupt Mask bit 48" "0,1" bitfld.long 0x10 15. "MIRQ47,Interrupt Mask bit 47" "0,1" bitfld.long 0x10 14. "MIRQ46,Interrupt Mask bit 46" "0,1" newline bitfld.long 0x10 13. "MIRQ45,Interrupt Mask bit 45" "0,1" bitfld.long 0x10 12. "MIRQ44,Interrupt Mask bit 44" "0,1" bitfld.long 0x10 11. "MIRQ43,Interrupt Mask bit 43" "0,1" bitfld.long 0x10 10. "MIRQ42,Interrupt Mask bit 42" "0,1" bitfld.long 0x10 9. "MIRQ41,Interrupt Mask bit 41" "0,1" bitfld.long 0x10 8. "MIRQ40,Interrupt Mask bit 40" "0,1" newline bitfld.long 0x10 7. "MIRQ39,Interrupt Mask bit 39" "0,1" bitfld.long 0x10 6. "MIRQ38,Interrupt Mask bit 38" "0,1" bitfld.long 0x10 5. "MIRQ37,Interrupt Mask bit 37" "0,1" bitfld.long 0x10 4. "MIRQ36,Interrupt Mask bit 36" "0,1" bitfld.long 0x10 3. "MIRQ35,Interrupt Mask bit 35" "0,1" bitfld.long 0x10 2. "MIRQ34,Interrupt Mask bit 34" "0,1" newline bitfld.long 0x10 1. "MIRQ33,Interrupt Mask bit 33" "0,1" bitfld.long 0x10 0. "MIRQ32,Interrupt Mask bit 32" "0,1" width 0x0B tree.end tree "ISP6P5_CNF1" base ad:0x52050C10 group.long 0x00++0x03 line.long 0x00 "NSF3V_SYSCONFIG,OCP interface" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "SOFTRESET,Software reset" "No action Write,Reset (software or other) ongoing" group.long 0x08++0xE7 line.long 0x00 "NSF3V_CTRL,Control" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "EN,Enable NSF3V operation for either single frame or video depending onNSF3V_CFG.ONESHOT" "0,1" line.long 0x04 "NSF3V_CFG,Configuration" hexmask.long.word 0x04 18.--31. 1. "RESERVED," bitfld.long 0x04 17. "FORCE_CLKON,Force clock to be on disabling clock autogating" "0,1" bitfld.long 0x04 16. "SUPPRS_ALL,Suppress all subband signals (debug mode)" "0,1" newline bitfld.long 0x04 15. "BYPASS_W_DELAY,Bypass all processing so that output = input but maintain the same latency" "0,1" bitfld.long 0x04 14. "BBORDER_REP,Replicate top border to not lose 7 lines per color on the bottom" "0,1" bitfld.long 0x04 13. "TBORDER_REP,Replicate top border to not lose 7 lines per color on the top" "0,1" newline bitfld.long 0x04 12. "RBORDER_REP,Replicate right border to not lose 8 data points per color on the right" "0,1" bitfld.long 0x04 11. "LBORDER_REP,Replicate left border to not lose 8 data points per color on the left" "0,1" bitfld.long 0x04 10. "DESAT_EN,enable chroma desaturation" "0,1" newline bitfld.long 0x04 9. "SHD_EN,enable shading gain" "0,1" bitfld.long 0x04 8. "EE_EN,enable edge enhancement" "0,1" bitfld.long 0x04 7. "ONESHOT,Video (continuous operation) or one shot (single-frame)" "video,one-shot" newline bitfld.long 0x04 6. "HARD_THR_EN_422UV,Hard thresholding enable applicable to YUV422 (normal and interleaved) UV path" "0,1" rbitfld.long 0x04 4.--5. "RESERVED," "0,1,2,3" bitfld.long 0x04 0.--3. "MODE,Mode of operation" "Bayer,Bayer interleaved 2x2,Bayer interleaved 3x3,YUV422,YUV420 Y plane,YuV420 UV plane,YUV422 interleaved,YUV420 Y interleaved,YUV420 UV interleaved 9 ~,?,?,?,?,?,?,reserved" line.long 0x08 "NSF3V_DIM,Image block dimension" rbitfld.long 0x08 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x08 16.--29. 1. "IH,Image height in lines" rbitfld.long 0x08 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x08 0.--13. 1. "IW,Image width in pixels" line.long 0x0C "NSF3V_VPOUT_CTRL,Video port output control" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," hexmask.long.word 0x0C 0.--15. 1. "PCLK,Video port output data rate indicate that VPOUT EN signal should be sent functional clock * PCLK / 65536" line.long 0x10 "NSF3V_SHD_ST,Shading gain starting coordinate" rbitfld.long 0x10 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x10 16.--29. 1. "Y,shading gain starting Y coordinate" rbitfld.long 0x10 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x10 0.--13. 1. "X,shading gain starting X coordinate" line.long 0x14 "NSF3V_SHD_HA,Shading gain HA1/HA2" rbitfld.long 0x14 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 16.--28. 1. "HA2,shading gain HA2 coefficient" rbitfld.long 0x14 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 0.--12. 1. "HA1,shading gain HA1 coefficient" line.long 0x18 "NSF3V_SHD_VA,Shading gain VA1/VA2" rbitfld.long 0x18 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x18 16.--28. 1. "VA2,shading gain VA2 coefficient" rbitfld.long 0x18 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x18 0.--12. 1. "VA1,shading gain VA1 coefficient" line.long 0x1C "NSF3V_SHD_HSVS,Shading gain shift counts" rbitfld.long 0x1C 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x1C 28.--29. "VCS,Vshading gain VCS shift count only 1 or 2 allowed" "0,1,2,3" bitfld.long 0x1C 24.--27. "VS2,shading gain VS2 shift count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 20.--23. "VS1,shading gain VS1 bit count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x1C 14.--19. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 12.--13. "HCS,shading gain HCS shift count only 1 or 2 allowed" "0,1,2,3" newline bitfld.long 0x1C 8.--11. "HS2,shading gain HS2 bit count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 4.--7. "HS1,shading gain HS1 shift count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. "S0,shading gain S0 shift count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "NSF3V_SHD_ADJ,Shading gain adjustment" rbitfld.long 0x20 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x20 16.--28. 1. "OADJ,shading gain offset adjustment" hexmask.long.byte 0x20 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x20 0.--7. 1. "GADJ,shading gain gain adjustment unsigned" line.long 0x24 "NSF3V_SHD_MAXG,Max shading gain" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED," hexmask.long.word 0x24 0.--8. 1. "MAXG,Max shading gain" line.long 0x28 "NSF3V_TN_C00,Color 0 noise threshold" rbitfld.long 0x28 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x28 16.--26. 1. "S0_Y,segment 0 Y coordinate U11" rbitfld.long 0x28 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x28 0.--11. 1. "S0_X,segment 0 X coordinate U12 fixed to 0 (read-only)" line.long 0x2C "NSF3V_TN_C01,Color 0 noise threshold" rbitfld.long 0x2C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x2C 16.--27. 1. "S1_X,segment 1 X coordinate U12" rbitfld.long 0x2C 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x2C 0.--13. 1. "S0_S,segment 0 slope S3.11" line.long 0x30 "NSF3V_TN_C02,Color 0 noise threshold" rbitfld.long 0x30 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x30 16.--29. 1. "S1_S,segment 1 slope S3.11" rbitfld.long 0x30 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x30 0.--10. 1. "S1_Y,segment 1 Y coordinate U11" line.long 0x34 "NSF3V_TN_C03,Color 0 noise threshold" rbitfld.long 0x34 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x34 16.--26. 1. "S2_Y,segment 2 Y coordinate U11" rbitfld.long 0x34 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x34 0.--11. 1. "S2_X,segment 2 X coordinate U12" line.long 0x38 "NSF3V_TN_C04,Color 0 noise threshold" rbitfld.long 0x38 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x38 16.--27. 1. "S3_X,segment 3 X coordinate U12" rbitfld.long 0x38 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x38 0.--13. 1. "S2_S,segment 2 slope S3.11" line.long 0x3C "NSF3V_TN_C05,Color 0 noise threshold" rbitfld.long 0x3C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x3C 16.--29. 1. "S3_S,segment 3 slope S3.11" rbitfld.long 0x3C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x3C 0.--10. 1. "S3_Y,segment 3 Y coordinate U11" line.long 0x40 "NSF3V_TN_C10,Color 1 noise threshold" rbitfld.long 0x40 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x40 16.--26. 1. "S0_Y,segment 0 Y coordinate U11" rbitfld.long 0x40 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x40 0.--11. 1. "S0_X,segment 0 X coordinate U12 fixed to 0 (read-only)" line.long 0x44 "NSF3V_TN_C11,Color 1 noise threshold" rbitfld.long 0x44 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x44 16.--27. 1. "S1_X,segment 1 X coordinate U12" rbitfld.long 0x44 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x44 0.--13. 1. "S0_S,segment 0 slope S3.11" line.long 0x48 "NSF3V_TN_C12,Color 1 noise threshold" rbitfld.long 0x48 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x48 16.--29. 1. "S1_S,segment 1 slope S3.11" rbitfld.long 0x48 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 0.--10. 1. "S1_Y,segment 1 Y coordinate U11" line.long 0x4C "NSF3V_TN_C13,Color 1 noise threshold" rbitfld.long 0x4C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x4C 16.--26. 1. "S2_Y,segment 2 Y coordinate U11" rbitfld.long 0x4C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x4C 0.--11. 1. "S2_X,segment 2 X coordinate U12" line.long 0x50 "NSF3V_TN_C14,Color 1 noise threshold" rbitfld.long 0x50 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x50 16.--27. 1. "S3_X,segment 3 X coordinate U12" rbitfld.long 0x50 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x50 0.--13. 1. "S2_S,segment 2 slope S3.11" line.long 0x54 "NSF3V_TN_C15,Color 1 noise threshold" rbitfld.long 0x54 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x54 16.--29. 1. "S3_S,segment 3 slope S3.11" rbitfld.long 0x54 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x54 0.--10. 1. "S3_Y,segment 3 Y coordinate U11" line.long 0x58 "NSF3V_TN_C20,Color 2 noise threshold" rbitfld.long 0x58 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x58 16.--26. 1. "S0_Y,segment 0 Y coordinate U11" rbitfld.long 0x58 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x58 0.--11. 1. "S0_X,segment 0 X coordinate U12 fixed to 0 (read-only)" line.long 0x5C "NSF3V_TN_C21,Color 2 noise threshold" rbitfld.long 0x5C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x5C 16.--27. 1. "S1_X,segment 1 X coordinate U12" rbitfld.long 0x5C 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x5C 0.--13. 1. "S0_S,segment 0 slope S3.11" line.long 0x60 "NSF3V_TN_C22,Color 2 noise threshold" rbitfld.long 0x60 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x60 16.--29. 1. "S1_S,segment 1 slope S3.11" rbitfld.long 0x60 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x60 0.--10. 1. "S1_Y,segment 1 Y coordinate U11" line.long 0x64 "NSF3V_TN_C23,Color 2 noise threshold" rbitfld.long 0x64 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x64 16.--26. 1. "S2_Y,segment 2 Y coordinate U11" rbitfld.long 0x64 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x64 0.--11. 1. "S2_X,segment 2 X coordinate U12" line.long 0x68 "NSF3V_TN_C24,Color 2 noise threshold" rbitfld.long 0x68 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x68 16.--27. 1. "S3_X,segment 3 X coordinate U12" rbitfld.long 0x68 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x68 0.--13. 1. "S2_S,segment 2 slope S3.11" line.long 0x6C "NSF3V_TN_C25,Color 2 noise threshold" rbitfld.long 0x6C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x6C 16.--29. 1. "S3_S,segment 3 slope S3.11" rbitfld.long 0x6C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x6C 0.--10. 1. "S3_Y,segment 3 Y coordinate U11" line.long 0x70 "NSF3V_TN_C30,Color 3 noise threshold" rbitfld.long 0x70 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x70 16.--26. 1. "S0_Y,segment 0 Y coordinate U11" rbitfld.long 0x70 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x70 0.--11. 1. "S0_X,segment 0 X coordinate U12 fixed to 0 (read-only)" line.long 0x74 "NSF3V_TN_C31,Color 3 noise threshold" rbitfld.long 0x74 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x74 16.--27. 1. "S1_X,segment 1 X coordinate U12" rbitfld.long 0x74 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x74 0.--13. 1. "S0_S,segment 0 slope S3.11" line.long 0x78 "NSF3V_TN_C32,Color 3 noise threshold" rbitfld.long 0x78 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x78 16.--29. 1. "S1_S,segment 1 slope S3.11" rbitfld.long 0x78 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x78 0.--10. 1. "S1_Y,segment 1 Y coordinate U11" line.long 0x7C "NSF3V_TN_C33,Color 3 noise threshold" rbitfld.long 0x7C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x7C 16.--26. 1. "S2_Y,segment 2 Y coordinate U11" rbitfld.long 0x7C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x7C 0.--11. 1. "S2_X,segment 2 X coordinate U12" line.long 0x80 "NSF3V_TN_C34,Color 3 noise threshold" rbitfld.long 0x80 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x80 16.--27. 1. "S3_X,segment 3 X coordinate U12" rbitfld.long 0x80 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x80 0.--13. 1. "S2_S,segment 2 slope S3.11" line.long 0x84 "NSF3V_TN_C35,Color 3 noise threshold" rbitfld.long 0x84 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x84 16.--29. 1. "S3_S,segment 3 slope S3.11" rbitfld.long 0x84 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x84 0.--10. 1. "S3_Y,segment 3 Y coordinate U11" line.long 0x88 "NSF3V_TN_SCALE," hexmask.long.byte 0x88 24.--31. 1. "RESERVED," hexmask.long.byte 0x88 16.--23. 1. "TN3_TO_TN2,Scaling factor to get TN3 noise threshold for level 3 subbands U3.5" hexmask.long.byte 0x88 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x88 0.--7. 1. "TN1_TO_TN2,Scaling factor to get TN1 noise threshold for level 1 subbands U3.5" line.long 0x8C "NSF3V_THR_KNEE,Thresholding knee points" hexmask.long.byte 0x8C 24.--31. 1. "RESERVED," hexmask.long.byte 0x8C 16.--23. 1. "U3,Knee point u3 above which ee = ee_max" hexmask.long.byte 0x8C 8.--15. 1. "U2,Knee point u2 below which ee = 0" newline hexmask.long.byte 0x8C 0.--7. 1. "U1,Knee point u1 below which suppression = suppression_max" line.long 0x90 "NSF3V_SUP_C00,Color 0 suppression max" hexmask.long.byte 0x90 24.--31. 1. "L2_HH,Level 2 HH subband suppression_max U1.7" hexmask.long.byte 0x90 16.--23. 1. "L2_LH,Level 2 LH and HL subband suppression_max U1.7" hexmask.long.byte 0x90 8.--15. 1. "L1_HH,Level 1 HH subband suppression_max U1.7" newline hexmask.long.byte 0x90 0.--7. 1. "L1_LH,Level 1 LH and HL subband suppression_max U1.7" line.long 0x94 "NSF3V_SUP_C01,Color 0 suppression max" hexmask.long.word 0x94 16.--31. 1. "RESERVED," hexmask.long.byte 0x94 8.--15. 1. "L3_HH,Level 3 HH subband suppression_max U1.7" hexmask.long.byte 0x94 0.--7. 1. "L3_LH,Level 3 LH and HL subband suppression_max U1.7" line.long 0x98 "NSF3V_SUP_C10,Color 1 suppression max" hexmask.long.byte 0x98 24.--31. 1. "L2_HH,Level 2 HH subband suppression_max U1.7" hexmask.long.byte 0x98 16.--23. 1. "L2_LH,Level 2 LH and HL subband suppression_max U1.7" hexmask.long.byte 0x98 8.--15. 1. "L1_HH,Level 1 HH subband suppression_max U1.7" newline hexmask.long.byte 0x98 0.--7. 1. "L1_LH,Level 1 LH and HL subband suppression_max U1.7" line.long 0x9C "NSF3V_SUP_C11,Color 1 suppression max" hexmask.long.word 0x9C 16.--31. 1. "RESERVED," hexmask.long.byte 0x9C 8.--15. 1. "L3_HH,Level 3 HH subband suppression_max U1.7" hexmask.long.byte 0x9C 0.--7. 1. "L3_LH,Level 3 LH and HL subband suppression_max U1.7" line.long 0xA0 "NSF3V_SUP_C20,Color 2 suppression max" hexmask.long.byte 0xA0 24.--31. 1. "L2_HH,Level 2 HH subband suppression_max U1.7" hexmask.long.byte 0xA0 16.--23. 1. "L2_LH,Level 2 LH and HL subband suppression_max U1.7" hexmask.long.byte 0xA0 8.--15. 1. "L1_HH,Level 1 HH subband suppression_max U1.7" newline hexmask.long.byte 0xA0 0.--7. 1. "L1_LH,Level 1 LH and HL subband suppression_max U1.7" line.long 0xA4 "NSF3V_SUP_C21,Color 2 suppression max" hexmask.long.word 0xA4 16.--31. 1. "RESERVED," hexmask.long.byte 0xA4 8.--15. 1. "L3_HH,Level 3 HH subband suppression_max U1.7" hexmask.long.byte 0xA4 0.--7. 1. "L3_LH,Level 3 LH and HL subband suppression_max U1.7" line.long 0xA8 "NSF3V_SUP_C30,Color 3 suppression max" hexmask.long.byte 0xA8 24.--31. 1. "L2_HH,Level 2 HH subband suppression_max U1.7" hexmask.long.byte 0xA8 16.--23. 1. "L2_LH,Level 2 LH and HL subband suppression_max U1.7" hexmask.long.byte 0xA8 8.--15. 1. "L1_HH,Level 1 HH subband suppression_max U1.7" newline hexmask.long.byte 0xA8 0.--7. 1. "L1_LH,Level 1 LH and HL subband suppression_max U1.7" line.long 0xAC "NSF3V_SUP_C31,Color 3 suppression max" hexmask.long.word 0xAC 16.--31. 1. "RESERVED," hexmask.long.byte 0xAC 8.--15. 1. "L3_HH,Level 3 HH subband suppression_max U1.7" hexmask.long.byte 0xAC 0.--7. 1. "L3_LH,Level 3 LH and HL subband suppression_max U1.7" line.long 0xB0 "NSF3V_EE_C00,Color 0 edge enhancement max" rbitfld.long 0xB0 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xB0 16.--27. 1. "L1_HH,Level 1 HH suband ee_max U10.2" rbitfld.long 0xB0 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xB0 0.--11. 1. "L1_LH,Level 1 LH and HL subband ee_max U10.2" line.long 0xB4 "NSF3V_EE_C01,Color 0 edge enhancement max" rbitfld.long 0xB4 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xB4 16.--27. 1. "L2_HH,Level 2 HH suband ee_max U10.2" rbitfld.long 0xB4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xB4 0.--11. 1. "L2_LH,Level 2 LH and HL subband ee_max U10.2" line.long 0xB8 "NSF3V_EE_C02,Color 0 edge enhancement max" rbitfld.long 0xB8 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xB8 16.--27. 1. "L3_HH,Level 3 HH suband ee_max U10.2" rbitfld.long 0xB8 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xB8 0.--11. 1. "L3_LH,Level 3 LH and HL subband ee_max U10.2" line.long 0xBC "NSF3V_EE_C10,Color 1 edge enhancement max" rbitfld.long 0xBC 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xBC 16.--27. 1. "L1_HH,Level 1 HH suband ee_max U10.2" rbitfld.long 0xBC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xBC 0.--11. 1. "L1_LH,Level 1 LH and HL subband ee_max U10.2" line.long 0xC0 "NSF3V_EE_C11,Color 1 edge enhancement max" rbitfld.long 0xC0 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC0 16.--27. 1. "L2_HH,Level 2 HH suband ee_max U10.2" rbitfld.long 0xC0 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC0 0.--11. 1. "L2_LH,Level 2 LH and HL subband ee_max U10.2" line.long 0xC4 "NSF3V_EE_C12,Color 1 edge enhancement max" rbitfld.long 0xC4 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC4 16.--27. 1. "L3_HH,Level 3 HH suband ee_max U10.2" rbitfld.long 0xC4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC4 0.--11. 1. "L3_LH,Level 3 LH and HL subband ee_max U10.2" line.long 0xC8 "NSF3V_EE_C20,Color 2 edge enhancement max" rbitfld.long 0xC8 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC8 16.--27. 1. "L1_HH,Level 1 HH suband ee_max U10.2" rbitfld.long 0xC8 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC8 0.--11. 1. "L1_LH,Level 1 LH and HL subband ee_max U10.2" line.long 0xCC "NSF3V_EE_C21,Color 2 edge enhancement max" rbitfld.long 0xCC 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xCC 16.--27. 1. "L2_HH,Level 2 HH suband ee_max U10.2" rbitfld.long 0xCC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xCC 0.--11. 1. "L2_LH,Level 2 LH and HL subband ee_max U10.2" line.long 0xD0 "NSF3V_EE_C22,Color 2 edge enhancement max" rbitfld.long 0xD0 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xD0 16.--27. 1. "L3_HH,Level 3 HH suband ee_max U10.2" rbitfld.long 0xD0 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD0 0.--11. 1. "L3_LH,Level 3 LH and HL subband ee_max U10.2" line.long 0xD4 "NSF3V_EE_C30,Color 3 edge enhancement max" rbitfld.long 0xD4 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xD4 16.--27. 1. "L1_HH,Level 1 HH suband ee_max U10.2" rbitfld.long 0xD4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD4 0.--11. 1. "L1_LH,Level 1 LH and HL subband ee_max U10.2" line.long 0xD8 "NSF3V_EE_C31,Color 3 edge enhancement max" rbitfld.long 0xD8 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xD8 16.--27. 1. "L2_HH,Level 2 HH suband ee_max U10.2" rbitfld.long 0xD8 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD8 0.--11. 1. "L2_LH,Level 2 LH and HL subband ee_max U10.2" line.long 0xDC "NSF3V_EE_C32,Color 3 edge enhancement max" rbitfld.long 0xDC 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xDC 16.--27. 1. "L3_HH,Level 3 HH suband ee_max U10.2" rbitfld.long 0xDC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xDC 0.--11. 1. "L3_LH,Level 3 LH and HL subband ee_max U10.2" line.long 0xE0 "NSF3V_DS_THR,Desaturation thresholds" hexmask.long.word 0xE0 22.--31. 1. "RESERVED," bitfld.long 0xE0 16.--21. "THR2,desaturation threshold 2 U6.0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0xE0 6.--15. 1. "RESERVED," newline bitfld.long 0xE0 0.--5. "THR1,desaturation threhsold 1 U6.0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0xE4 "NSF3V_DS_SLOPE,Desaturation slopes" rbitfld.long 0xE4 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0xE4 16.--25. 1. "SLOPE2,desaturation slope 2 U0.10" rbitfld.long 0xE4 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xE4 0.--9. 1. "SLOPE1,desaturation slope 1 U0.10" width 0x0B tree.end tree "ISP6P5_GLBCE" base ad:0x52051000 group.long 0x00++0x6DB line.long 0x00 "GLBCE_CFG,GLBCE Configuration Registers" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "SWRST,This bit initiate software reset process" "SWRST_0,SWRST_1" line.long 0x04 "GLBCE_MODE," hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "OST,One shot mode or continuous mode" "OST_0,OST_1" line.long 0x08 "GLBCE_CONTROL0,GLBCE Configuration Port GLBCE Control Register 0 (control_0)" hexmask.long.word 0x08 16.--31. 1. "RESERVED," hexmask.long.word 0x08 5.--15. 1. "RESERVED," newline bitfld.long 0x08 4. "CCTL,Color Control (CCTL) - Enabling this processing will result in more accurate colors processing" "Disable color correction,Enable color correction" bitfld.long 0x08 3. "MB,Max Bayer Type- Use this bit to select the algorithm used for calculating intensity" "Algorithm 1,Algorithm 2 (Recommended)" newline rbitfld.long 0x08 1.--2. "RESERVED,These bits are read only" "0,1,2,3" bitfld.long 0x08 0. "ONOFF,GLBCE On/Off - This bit turns GLBCE processing ON and OFF" "Disable GLBCE processing,Enable GLBCE processing" line.long 0x0C "GLBCE_CONTROL1,GLBCE Configuration Port Reserved for future connection to CONTROL1 port Not used in OMAP6 as the port is not connected" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED," hexmask.long.byte 0x0C 0.--7. 1. "RESERVED," line.long 0x10 "GLBCE_BLACK_LEVEL,GLBCE Configuration Port Black Level Register (black_level)" hexmask.long.word 0x10 16.--31. 1. "RESERVED," hexmask.long.word 0x10 0.--15. 1. "VAL,The value stored in Black Level Port will be used as zero level for GLBCE processing in all unsigned data channels" line.long 0x14 "GLBCE_WHITE_LEVEL,GLBCE Configuration Port White Level Register (white_level)" hexmask.long.word 0x14 16.--31. 1. "RESERVED," hexmask.long.word 0x14 0.--15. 1. "VAL,The value stored in White Level Port will be used as white level for GLBCE processing in all unsigned data channels" line.long 0x18 "GLBCE_VARIANCE,GLBCE Configuration Port Affects the sensitivity of the transform to different areas of the image. and can be increased in order to emphasize small regions (e.g. faces)" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," bitfld.long 0x18 4.--7. "VARIANCEINTENSITY,Variance Intensity - Sets the degree of sensitivity in the luminance domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 0.--3. "VARIANCESPACE,Variance Space - Sets the degree of spatial sensitivity of the algorithm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "GLBCE_LIMIT_AMPL,GLBCE Configuration Port The parameters ? dark amplification limit ? bright amplification limit are used to restrict the luminance space in which GLBCE can adaptively generate tone curves for each pixel" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," bitfld.long 0x1C 4.--7. "BRIGHTAMPLIFICATIONLIMIT,Bright amplification limit - The resultant tone curve cannot be lower than bright amplification limit line controlled by the bright amplification limit parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 0.--3. "DARKAMPLIFICATIONLIMIT,Dark amplification limit - The resultant tone curve cannot be higher than dark amplification limit line controlled by the dark amplification limit parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "GLBCE_DITHER,GLBCE Configuration Port Dithering Register (dither)" hexmask.long 0x20 7.--31. 1. "RESERVED," rbitfld.long 0x20 3.--6. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x20 0.--2. "DITHER," "?,One least significant bit of the output signal..,Two bits are dithered,Three bits are dithered,Four bits are dithered All other values,?..." line.long 0x24 "GLBCE_SLOPE_MAX,GLBCE Configuration Port Slope Max Limit Register (slope_max)" hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED," hexmask.long.byte 0x24 0.--7. 1. "SLOPEMAXLIMIT,Slope Max Limit - Slope Max Limit is used to restrict the slope of the tone-curve generated by GLBCE" line.long 0x28 "GLBCE_SLOPE_MIN,GLBCE Configuration Port Slope Min Limit Register (slope_min)" hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED," hexmask.long.byte 0x28 0.--7. 1. "SLOPEMINLIMIT,Slope Min Limit - Slope Min Limit is used to restrict the slope of the tone-curve generated by GLBCE" line.long 0x2C "GLBCE_LUT_FI_00,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x2C 16.--31. 1. "RESERVED," hexmask.long.word 0x2C 0.--15. 1. "VAL," line.long 0x30 "GLBCE_LUT_FI_01,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x30 16.--31. 1. "RESERVED," hexmask.long.word 0x30 0.--15. 1. "VAL," line.long 0x34 "GLBCE_LUT_FI_02,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x34 16.--31. 1. "RESERVED," hexmask.long.word 0x34 0.--15. 1. "VAL," line.long 0x38 "GLBCE_LUT_FI_03,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x38 16.--31. 1. "RESERVED," hexmask.long.word 0x38 0.--15. 1. "VAL," line.long 0x3C "GLBCE_LUT_FI_04,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x3C 16.--31. 1. "RESERVED," hexmask.long.word 0x3C 0.--15. 1. "VAL," line.long 0x40 "GLBCE_LUT_FI_05,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x40 16.--31. 1. "RESERVED," hexmask.long.word 0x40 0.--15. 1. "VAL," line.long 0x44 "GLBCE_LUT_FI_06,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x44 16.--31. 1. "RESERVED," hexmask.long.word 0x44 0.--15. 1. "VAL," line.long 0x48 "GLBCE_LUT_FI_07,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x48 16.--31. 1. "RESERVED," hexmask.long.word 0x48 0.--15. 1. "VAL," line.long 0x4C "GLBCE_LUT_FI_08,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x4C 16.--31. 1. "RESERVED," hexmask.long.word 0x4C 0.--15. 1. "VAL," line.long 0x50 "GLBCE_LUT_FI_09,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x50 16.--31. 1. "RESERVED," hexmask.long.word 0x50 0.--15. 1. "VAL," line.long 0x54 "GLBCE_LUT_FI_10,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x54 16.--31. 1. "RESERVED," hexmask.long.word 0x54 0.--15. 1. "VAL," line.long 0x58 "GLBCE_LUT_FI_11,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x58 16.--31. 1. "RESERVED," hexmask.long.word 0x58 0.--15. 1. "VAL," line.long 0x5C "GLBCE_LUT_FI_12,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x5C 16.--31. 1. "RESERVED," hexmask.long.word 0x5C 0.--15. 1. "VAL," line.long 0x60 "GLBCE_LUT_FI_13,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x60 16.--31. 1. "RESERVED," hexmask.long.word 0x60 0.--15. 1. "VAL," line.long 0x64 "GLBCE_LUT_FI_14,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x64 16.--31. 1. "RESERVED," hexmask.long.word 0x64 0.--15. 1. "VAL," line.long 0x68 "GLBCE_LUT_FI_15,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x68 16.--31. 1. "RESERVED," hexmask.long.word 0x68 0.--15. 1. "VAL," line.long 0x6C "GLBCE_LUT_FI_16,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x6C 16.--31. 1. "RESERVED," hexmask.long.word 0x6C 0.--15. 1. "VAL," line.long 0x70 "GLBCE_LUT_FI_17,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x70 16.--31. 1. "RESERVED," hexmask.long.word 0x70 0.--15. 1. "VAL," line.long 0x74 "GLBCE_LUT_FI_18,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x74 16.--31. 1. "RESERVED," hexmask.long.word 0x74 0.--15. 1. "VAL," line.long 0x78 "GLBCE_LUT_FI_19,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x78 16.--31. 1. "RESERVED," hexmask.long.word 0x78 0.--15. 1. "VAL," line.long 0x7C "GLBCE_LUT_FI_20,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x7C 16.--31. 1. "RESERVED," hexmask.long.word 0x7C 0.--15. 1. "VAL," line.long 0x80 "GLBCE_LUT_FI_21,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x80 16.--31. 1. "RESERVED," hexmask.long.word 0x80 0.--15. 1. "VAL," line.long 0x84 "GLBCE_LUT_FI_22,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x84 16.--31. 1. "RESERVED," hexmask.long.word 0x84 0.--15. 1. "VAL," line.long 0x88 "GLBCE_LUT_FI_23,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x88 16.--31. 1. "RESERVED," hexmask.long.word 0x88 0.--15. 1. "VAL," line.long 0x8C "GLBCE_LUT_FI_24,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x8C 16.--31. 1. "RESERVED," hexmask.long.word 0x8C 0.--15. 1. "VAL," line.long 0x90 "GLBCE_LUT_FI_25,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x90 16.--31. 1. "RESERVED," hexmask.long.word 0x90 0.--15. 1. "VAL," line.long 0x94 "GLBCE_LUT_FI_26,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x94 16.--31. 1. "RESERVED," hexmask.long.word 0x94 0.--15. 1. "VAL," line.long 0x98 "GLBCE_LUT_FI_27,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x98 16.--31. 1. "RESERVED," hexmask.long.word 0x98 0.--15. 1. "VAL," line.long 0x9C "GLBCE_LUT_FI_28,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x9C 16.--31. 1. "RESERVED," hexmask.long.word 0x9C 0.--15. 1. "VAL," line.long 0xA0 "GLBCE_LUT_FI_29,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0xA0 16.--31. 1. "RESERVED," hexmask.long.word 0xA0 0.--15. 1. "VAL," line.long 0xA4 "GLBCE_LUT_FI_30,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0xA4 16.--31. 1. "RESERVED," hexmask.long.word 0xA4 0.--15. 1. "VAL," line.long 0xA8 "GLBCE_LUT_FI_31,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0xA8 16.--31. 1. "RESERVED," hexmask.long.word 0xA8 0.--15. 1. "VAL," line.long 0xAC "GLBCE_LUT_FI_32,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0xAC 16.--31. 1. "RESERVED," hexmask.long.word 0xAC 0.--15. 1. "VAL," line.long 0xB0 "GLBCE_FORMAT_CONTROL_REG0,GLBCE Configuration Port The Data format port specifies the input data format so that the GLBCE core can process the different input data formats This register is reserved for ISS6" hexmask.long.tbyte 0xB0 8.--31. 1. "RESERVED," bitfld.long 0xB0 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0xB0 0.--1. "DATAFORMAT,This value is reserved" "0,1,2,3" line.long 0xB4 "GLBCE_FORMAT_CONTROL_REG1,GLBCE Configuration Port Control Reg1" hexmask.long.tbyte 0xB4 8.--31. 1. "RESERVED," bitfld.long 0xB4 7. "AUTOSIZE,This value is read only" "AUTOSIZE_0,AUTOSIZE_1" newline bitfld.long 0xB4 6. "AUTOPOS,This value is read only" "AUTOPOS_0,AUTOPOS_1" bitfld.long 0xB4 4.--5. "FCMODE,Field Correction Mode" "FCMODE_0,FCMODE_1,FCMODE_2,?" newline bitfld.long 0xB4 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0xB4 1. "VSPOL,Vertical Sync Polarity This value is read only" "VSPOL_0,VSPOL_1" newline bitfld.long 0xB4 0. "HSPOL,Horizontal Sync Polarity This value is read only" "HSPOL_0,HSPOL_1" line.long 0xB8 "GLBCE_FRAME_WIDTH,GLBCE Configuration Port Frame Width is the number of pixels in an active line" hexmask.long.word 0xB8 16.--31. 1. "RESERVED," hexmask.long.word 0xB8 0.--15. 1. "VAL," line.long 0xBC "GLBCE_FRAME_HEIGHT,GLBCE Configuration Port Frame Height is the number of active lines in one field" hexmask.long.word 0xBC 16.--31. 1. "RESERVED," hexmask.long.word 0xBC 0.--15. 1. "VAL," line.long 0xC0 "GLBCE_STRENGTH_IR,GLBCE Configuration Port Strength (Strength of GLBCE) - This Port sets processing Strength" hexmask.long.tbyte 0xC0 8.--31. 1. "RESERVED," hexmask.long.byte 0xC0 0.--7. 1. "VAL," line.long 0xC4 "GLBCE_PERCEPT_EN," hexmask.long 0xC4 2.--31. 1. "RESERVED," bitfld.long 0xC4 1. "FWD_EN," "FWD_EN_0,FWD_EN_1" newline bitfld.long 0xC4 0. "REV_EN,Reverse Perceptual LUT enable[" "REV_EN_0,REV_EN_1" line.long 0xC8 "GLBCE_REV_PERCEPT_LUT_00,Reverse Perceptual LUT" hexmask.long.word 0xC8 16.--31. 1. "RESERVED," hexmask.long.word 0xC8 0.--15. 1. "VAL," line.long 0xCC "GLBCE_REV_PERCEPT_LUT_01,Reverse Perceptual LUT" hexmask.long.word 0xCC 16.--31. 1. "RESERVED," hexmask.long.word 0xCC 0.--15. 1. "VAL," line.long 0xD0 "GLBCE_REV_PERCEPT_LUT_02,Reverse Perceptual LUT" hexmask.long.word 0xD0 16.--31. 1. "RESERVED," hexmask.long.word 0xD0 0.--15. 1. "VAL," line.long 0xD4 "GLBCE_REV_PERCEPT_LUT_03,Reverse Perceptual LUT" hexmask.long.word 0xD4 16.--31. 1. "RESERVED," hexmask.long.word 0xD4 0.--15. 1. "VAL," line.long 0xD8 "GLBCE_REV_PERCEPT_LUT_04,Reverse Perceptual LUT" hexmask.long.word 0xD8 16.--31. 1. "RESERVED," hexmask.long.word 0xD8 0.--15. 1. "VAL," line.long 0xDC "GLBCE_REV_PERCEPT_LUT_05,Reverse Perceptual LUT" hexmask.long.word 0xDC 16.--31. 1. "RESERVED," hexmask.long.word 0xDC 0.--15. 1. "VAL," line.long 0xE0 "GLBCE_REV_PERCEPT_LUT_06,Reverse Perceptual LUT" hexmask.long.word 0xE0 16.--31. 1. "RESERVED," hexmask.long.word 0xE0 0.--15. 1. "VAL," line.long 0xE4 "GLBCE_REV_PERCEPT_LUT_07,Reverse Perceptual LUT" hexmask.long.word 0xE4 16.--31. 1. "RESERVED," hexmask.long.word 0xE4 0.--15. 1. "VAL," line.long 0xE8 "GLBCE_REV_PERCEPT_LUT_08,Reverse Perceptual LUT" hexmask.long.word 0xE8 16.--31. 1. "RESERVED," hexmask.long.word 0xE8 0.--15. 1. "VAL," line.long 0xEC "GLBCE_REV_PERCEPT_LUT_09,Reverse Perceptual LUT" hexmask.long.word 0xEC 16.--31. 1. "RESERVED," hexmask.long.word 0xEC 0.--15. 1. "VAL," line.long 0xF0 "GLBCE_REV_PERCEPT_LUT_10,Reverse Perceptual LUT" hexmask.long.word 0xF0 16.--31. 1. "RESERVED," hexmask.long.word 0xF0 0.--15. 1. "VAL," line.long 0xF4 "GLBCE_REV_PERCEPT_LUT_11,Reverse Perceptual LUT" hexmask.long.word 0xF4 16.--31. 1. "RESERVED," hexmask.long.word 0xF4 0.--15. 1. "VAL," line.long 0xF8 "GLBCE_REV_PERCEPT_LUT_12,Reverse Perceptual LUT" hexmask.long.word 0xF8 16.--31. 1. "RESERVED," hexmask.long.word 0xF8 0.--15. 1. "VAL," line.long 0xFC "GLBCE_REV_PERCEPT_LUT_13,Reverse Perceptual LUT" hexmask.long.word 0xFC 16.--31. 1. "RESERVED," hexmask.long.word 0xFC 0.--15. 1. "VAL," line.long 0x100 "GLBCE_REV_PERCEPT_LUT_14,Reverse Perceptual LUT" hexmask.long.word 0x100 16.--31. 1. "RESERVED," hexmask.long.word 0x100 0.--15. 1. "VAL," line.long 0x104 "GLBCE_REV_PERCEPT_LUT_15,Reverse Perceptual LUT" hexmask.long.word 0x104 16.--31. 1. "RESERVED," hexmask.long.word 0x104 0.--15. 1. "VAL," line.long 0x108 "GLBCE_REV_PERCEPT_LUT_16,Reverse Perceptual LUT" hexmask.long.word 0x108 16.--31. 1. "RESERVED," hexmask.long.word 0x108 0.--15. 1. "VAL," line.long 0x10C "GLBCE_REV_PERCEPT_LUT_17,Reverse Perceptual LUT" hexmask.long.word 0x10C 16.--31. 1. "RESERVED," hexmask.long.word 0x10C 0.--15. 1. "VAL," line.long 0x110 "GLBCE_REV_PERCEPT_LUT_18,Reverse Perceptual LUT" hexmask.long.word 0x110 16.--31. 1. "RESERVED," hexmask.long.word 0x110 0.--15. 1. "VAL," line.long 0x114 "GLBCE_REV_PERCEPT_LUT_19,Reverse Perceptual LUT" hexmask.long.word 0x114 16.--31. 1. "RESERVED," hexmask.long.word 0x114 0.--15. 1. "VAL," line.long 0x118 "GLBCE_REV_PERCEPT_LUT_20,Reverse Perceptual LUT" hexmask.long.word 0x118 16.--31. 1. "RESERVED," hexmask.long.word 0x118 0.--15. 1. "VAL," line.long 0x11C "GLBCE_REV_PERCEPT_LUT_21,Reverse Perceptual LUT" hexmask.long.word 0x11C 16.--31. 1. "RESERVED," hexmask.long.word 0x11C 0.--15. 1. "VAL," line.long 0x120 "GLBCE_REV_PERCEPT_LUT_22,Reverse Perceptual LUT" hexmask.long.word 0x120 16.--31. 1. "RESERVED," hexmask.long.word 0x120 0.--15. 1. "VAL," line.long 0x124 "GLBCE_REV_PERCEPT_LUT_23,Reverse Perceptual LUT" hexmask.long.word 0x124 16.--31. 1. "RESERVED," hexmask.long.word 0x124 0.--15. 1. "VAL," line.long 0x128 "GLBCE_REV_PERCEPT_LUT_24,Reverse Perceptual LUT" hexmask.long.word 0x128 16.--31. 1. "RESERVED," hexmask.long.word 0x128 0.--15. 1. "VAL," line.long 0x12C "GLBCE_REV_PERCEPT_LUT_25,Reverse Perceptual LUT" hexmask.long.word 0x12C 16.--31. 1. "RESERVED," hexmask.long.word 0x12C 0.--15. 1. "VAL," line.long 0x130 "GLBCE_REV_PERCEPT_LUT_26,Reverse Perceptual LUT" hexmask.long.word 0x130 16.--31. 1. "RESERVED," hexmask.long.word 0x130 0.--15. 1. "VAL," line.long 0x134 "GLBCE_REV_PERCEPT_LUT_27,Reverse Perceptual LUT" hexmask.long.word 0x134 16.--31. 1. "RESERVED," hexmask.long.word 0x134 0.--15. 1. "VAL," line.long 0x138 "GLBCE_REV_PERCEPT_LUT_28,Reverse Perceptual LUT" hexmask.long.word 0x138 16.--31. 1. "RESERVED," hexmask.long.word 0x138 0.--15. 1. "VAL," line.long 0x13C "GLBCE_REV_PERCEPT_LUT_29,Reverse Perceptual LUT" hexmask.long.word 0x13C 16.--31. 1. "RESERVED," hexmask.long.word 0x13C 0.--15. 1. "VAL," line.long 0x140 "GLBCE_REV_PERCEPT_LUT_30,Reverse Perceptual LUT" hexmask.long.word 0x140 16.--31. 1. "RESERVED," hexmask.long.word 0x140 0.--15. 1. "VAL," line.long 0x144 "GLBCE_REV_PERCEPT_LUT_31,Reverse Perceptual LUT" hexmask.long.word 0x144 16.--31. 1. "RESERVED," hexmask.long.word 0x144 0.--15. 1. "VAL," line.long 0x148 "GLBCE_REV_PERCEPT_LUT_32,Reverse Perceptual LUT" hexmask.long.word 0x148 16.--31. 1. "RESERVED," hexmask.long.word 0x148 0.--15. 1. "VAL," line.long 0x14C "GLBCE_REV_PERCEPT_LUT_33,Reverse Perceptual LUT" hexmask.long.word 0x14C 16.--31. 1. "RESERVED," hexmask.long.word 0x14C 0.--15. 1. "VAL," line.long 0x150 "GLBCE_REV_PERCEPT_LUT_34,Reverse Perceptual LUT" hexmask.long.word 0x150 16.--31. 1. "RESERVED," hexmask.long.word 0x150 0.--15. 1. "VAL," line.long 0x154 "GLBCE_REV_PERCEPT_LUT_35,Reverse Perceptual LUT" hexmask.long.word 0x154 16.--31. 1. "RESERVED," hexmask.long.word 0x154 0.--15. 1. "VAL," line.long 0x158 "GLBCE_REV_PERCEPT_LUT_36,Reverse Perceptual LUT" hexmask.long.word 0x158 16.--31. 1. "RESERVED," hexmask.long.word 0x158 0.--15. 1. "VAL," line.long 0x15C "GLBCE_REV_PERCEPT_LUT_37,Reverse Perceptual LUT" hexmask.long.word 0x15C 16.--31. 1. "RESERVED," hexmask.long.word 0x15C 0.--15. 1. "VAL," line.long 0x160 "GLBCE_REV_PERCEPT_LUT_38,Reverse Perceptual LUT" hexmask.long.word 0x160 16.--31. 1. "RESERVED," hexmask.long.word 0x160 0.--15. 1. "VAL," line.long 0x164 "GLBCE_REV_PERCEPT_LUT_39,Reverse Perceptual LUT" hexmask.long.word 0x164 16.--31. 1. "RESERVED," hexmask.long.word 0x164 0.--15. 1. "VAL," line.long 0x168 "GLBCE_REV_PERCEPT_LUT_40,Reverse Perceptual LUT" hexmask.long.word 0x168 16.--31. 1. "RESERVED," hexmask.long.word 0x168 0.--15. 1. "VAL," line.long 0x16C "GLBCE_REV_PERCEPT_LUT_41,Reverse Perceptual LUT" hexmask.long.word 0x16C 16.--31. 1. "RESERVED," hexmask.long.word 0x16C 0.--15. 1. "VAL," line.long 0x170 "GLBCE_REV_PERCEPT_LUT_42,Reverse Perceptual LUT" hexmask.long.word 0x170 16.--31. 1. "RESERVED," hexmask.long.word 0x170 0.--15. 1. "VAL," line.long 0x174 "GLBCE_REV_PERCEPT_LUT_43,Reverse Perceptual LUT" hexmask.long.word 0x174 16.--31. 1. "RESERVED," hexmask.long.word 0x174 0.--15. 1. "VAL," line.long 0x178 "GLBCE_REV_PERCEPT_LUT_44,Reverse Perceptual LUT" hexmask.long.word 0x178 16.--31. 1. "RESERVED," hexmask.long.word 0x178 0.--15. 1. "VAL," line.long 0x17C "GLBCE_REV_PERCEPT_LUT_45,Reverse Perceptual LUT" hexmask.long.word 0x17C 16.--31. 1. "RESERVED," hexmask.long.word 0x17C 0.--15. 1. "VAL," line.long 0x180 "GLBCE_REV_PERCEPT_LUT_46,Reverse Perceptual LUT" hexmask.long.word 0x180 16.--31. 1. "RESERVED," hexmask.long.word 0x180 0.--15. 1. "VAL," line.long 0x184 "GLBCE_REV_PERCEPT_LUT_47,Reverse Perceptual LUT" hexmask.long.word 0x184 16.--31. 1. "RESERVED," hexmask.long.word 0x184 0.--15. 1. "VAL," line.long 0x188 "GLBCE_REV_PERCEPT_LUT_48,Reverse Perceptual LUT" hexmask.long.word 0x188 16.--31. 1. "RESERVED," hexmask.long.word 0x188 0.--15. 1. "VAL," line.long 0x18C "GLBCE_REV_PERCEPT_LUT_49,Reverse Perceptual LUT" hexmask.long.word 0x18C 16.--31. 1. "RESERVED," hexmask.long.word 0x18C 0.--15. 1. "VAL," line.long 0x190 "GLBCE_REV_PERCEPT_LUT_50,Reverse Perceptual LUT" hexmask.long.word 0x190 16.--31. 1. "RESERVED," hexmask.long.word 0x190 0.--15. 1. "VAL," line.long 0x194 "GLBCE_REV_PERCEPT_LUT_51,Reverse Perceptual LUT" hexmask.long.word 0x194 16.--31. 1. "RESERVED," hexmask.long.word 0x194 0.--15. 1. "VAL," line.long 0x198 "GLBCE_REV_PERCEPT_LUT_52,Reverse Perceptual LUT" hexmask.long.word 0x198 16.--31. 1. "RESERVED," hexmask.long.word 0x198 0.--15. 1. "VAL," line.long 0x19C "GLBCE_REV_PERCEPT_LUT_53,Reverse Perceptual LUT" hexmask.long.word 0x19C 16.--31. 1. "RESERVED," hexmask.long.word 0x19C 0.--15. 1. "VAL," line.long 0x1A0 "GLBCE_REV_PERCEPT_LUT_54,Reverse Perceptual LUT" hexmask.long.word 0x1A0 16.--31. 1. "RESERVED," hexmask.long.word 0x1A0 0.--15. 1. "VAL," line.long 0x1A4 "GLBCE_REV_PERCEPT_LUT_55,Reverse Perceptual LUT" hexmask.long.word 0x1A4 16.--31. 1. "RESERVED," hexmask.long.word 0x1A4 0.--15. 1. "VAL," line.long 0x1A8 "GLBCE_REV_PERCEPT_LUT_56,Reverse Perceptual LUT" hexmask.long.word 0x1A8 16.--31. 1. "RESERVED," hexmask.long.word 0x1A8 0.--15. 1. "VAL," line.long 0x1AC "GLBCE_REV_PERCEPT_LUT_57,Reverse Perceptual LUT" hexmask.long.word 0x1AC 16.--31. 1. "RESERVED," hexmask.long.word 0x1AC 0.--15. 1. "VAL," line.long 0x1B0 "GLBCE_REV_PERCEPT_LUT_58,Reverse Perceptual LUT" hexmask.long.word 0x1B0 16.--31. 1. "RESERVED," hexmask.long.word 0x1B0 0.--15. 1. "VAL," line.long 0x1B4 "GLBCE_REV_PERCEPT_LUT_59,Reverse Perceptual LUT" hexmask.long.word 0x1B4 16.--31. 1. "RESERVED," hexmask.long.word 0x1B4 0.--15. 1. "VAL," line.long 0x1B8 "GLBCE_REV_PERCEPT_LUT_60,Reverse Perceptual LUT" hexmask.long.word 0x1B8 16.--31. 1. "RESERVED," hexmask.long.word 0x1B8 0.--15. 1. "VAL," line.long 0x1BC "GLBCE_REV_PERCEPT_LUT_61,Reverse Perceptual LUT" hexmask.long.word 0x1BC 16.--31. 1. "RESERVED," hexmask.long.word 0x1BC 0.--15. 1. "VAL," line.long 0x1C0 "GLBCE_REV_PERCEPT_LUT_62,Reverse Perceptual LUT" hexmask.long.word 0x1C0 16.--31. 1. "RESERVED," hexmask.long.word 0x1C0 0.--15. 1. "VAL," line.long 0x1C4 "GLBCE_REV_PERCEPT_LUT_63,Reverse Perceptual LUT" hexmask.long.word 0x1C4 16.--31. 1. "RESERVED," hexmask.long.word 0x1C4 0.--15. 1. "VAL," line.long 0x1C8 "GLBCE_REV_PERCEPT_LUT_64,Reverse Perceptual LUT" hexmask.long.word 0x1C8 16.--31. 1. "RESERVED," hexmask.long.word 0x1C8 0.--15. 1. "VAL," line.long 0x1CC "GLBCE_FWD_PERCEPT_LUT_00," hexmask.long.word 0x1CC 16.--31. 1. "RESERVED," hexmask.long.word 0x1CC 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1D0 "GLBCE_FWD_PERCEPT_LUT_01," hexmask.long.word 0x1D0 16.--31. 1. "RESERVED," hexmask.long.word 0x1D0 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1D4 "GLBCE_FWD_PERCEPT_LUT_02," hexmask.long.word 0x1D4 16.--31. 1. "RESERVED," hexmask.long.word 0x1D4 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1D8 "GLBCE_FWD_PERCEPT_LUT_03," hexmask.long.word 0x1D8 16.--31. 1. "RESERVED," hexmask.long.word 0x1D8 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1DC "GLBCE_FWD_PERCEPT_LUT_04," hexmask.long.word 0x1DC 16.--31. 1. "RESERVED," hexmask.long.word 0x1DC 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1E0 "GLBCE_FWD_PERCEPT_LUT_05," hexmask.long.word 0x1E0 16.--31. 1. "RESERVED," hexmask.long.word 0x1E0 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1E4 "GLBCE_FWD_PERCEPT_LUT_06," hexmask.long.word 0x1E4 16.--31. 1. "RESERVED," hexmask.long.word 0x1E4 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1E8 "GLBCE_FWD_PERCEPT_LUT_07," hexmask.long.word 0x1E8 16.--31. 1. "RESERVED," hexmask.long.word 0x1E8 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1EC "GLBCE_FWD_PERCEPT_LUT_08," hexmask.long.word 0x1EC 16.--31. 1. "RESERVED," hexmask.long.word 0x1EC 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1F0 "GLBCE_FWD_PERCEPT_LUT_09," hexmask.long.word 0x1F0 16.--31. 1. "RESERVED," hexmask.long.word 0x1F0 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1F4 "GLBCE_FWD_PERCEPT_LUT_10," hexmask.long.word 0x1F4 16.--31. 1. "RESERVED," hexmask.long.word 0x1F4 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1F8 "GLBCE_FWD_PERCEPT_LUT_11," hexmask.long.word 0x1F8 16.--31. 1. "RESERVED," hexmask.long.word 0x1F8 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1FC "GLBCE_FWD_PERCEPT_LUT_12," hexmask.long.word 0x1FC 16.--31. 1. "RESERVED," hexmask.long.word 0x1FC 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x200 "GLBCE_FWD_PERCEPT_LUT_13," hexmask.long.word 0x200 16.--31. 1. "RESERVED," hexmask.long.word 0x200 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x204 "GLBCE_FWD_PERCEPT_LUT_14," hexmask.long.word 0x204 16.--31. 1. "RESERVED," hexmask.long.word 0x204 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x208 "GLBCE_FWD_PERCEPT_LUT_15," hexmask.long.word 0x208 16.--31. 1. "RESERVED," hexmask.long.word 0x208 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x20C "GLBCE_FWD_PERCEPT_LUT_16," hexmask.long.word 0x20C 16.--31. 1. "RESERVED," hexmask.long.word 0x20C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x210 "GLBCE_FWD_PERCEPT_LUT_17," hexmask.long.word 0x210 16.--31. 1. "RESERVED," hexmask.long.word 0x210 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x214 "GLBCE_FWD_PERCEPT_LUT_18," hexmask.long.word 0x214 16.--31. 1. "RESERVED," hexmask.long.word 0x214 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x218 "GLBCE_FWD_PERCEPT_LUT_19," hexmask.long.word 0x218 16.--31. 1. "RESERVED," hexmask.long.word 0x218 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x21C "GLBCE_FWD_PERCEPT_LUT_20," hexmask.long.word 0x21C 16.--31. 1. "RESERVED," hexmask.long.word 0x21C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x220 "GLBCE_FWD_PERCEPT_LUT_21," hexmask.long.word 0x220 16.--31. 1. "RESERVED," hexmask.long.word 0x220 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x224 "GLBCE_FWD_PERCEPT_LUT_22," hexmask.long.word 0x224 16.--31. 1. "RESERVED," hexmask.long.word 0x224 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x228 "GLBCE_FWD_PERCEPT_LUT_23," hexmask.long.word 0x228 16.--31. 1. "RESERVED," hexmask.long.word 0x228 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x22C "GLBCE_FWD_PERCEPT_LUT_24," hexmask.long.word 0x22C 16.--31. 1. "RESERVED," hexmask.long.word 0x22C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x230 "GLBCE_FWD_PERCEPT_LUT_25," hexmask.long.word 0x230 16.--31. 1. "RESERVED," hexmask.long.word 0x230 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x234 "GLBCE_FWD_PERCEPT_LUT_26," hexmask.long.word 0x234 16.--31. 1. "RESERVED," hexmask.long.word 0x234 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x238 "GLBCE_FWD_PERCEPT_LUT_27," hexmask.long.word 0x238 16.--31. 1. "RESERVED," hexmask.long.word 0x238 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x23C "GLBCE_FWD_PERCEPT_LUT_28," hexmask.long.word 0x23C 16.--31. 1. "RESERVED," hexmask.long.word 0x23C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x240 "GLBCE_FWD_PERCEPT_LUT_29," hexmask.long.word 0x240 16.--31. 1. "RESERVED," hexmask.long.word 0x240 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x244 "GLBCE_FWD_PERCEPT_LUT_30," hexmask.long.word 0x244 16.--31. 1. "RESERVED," hexmask.long.word 0x244 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x248 "GLBCE_FWD_PERCEPT_LUT_31," hexmask.long.word 0x248 16.--31. 1. "RESERVED," hexmask.long.word 0x248 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x24C "GLBCE_FWD_PERCEPT_LUT_32," hexmask.long.word 0x24C 16.--31. 1. "RESERVED," hexmask.long.word 0x24C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x250 "GLBCE_FWD_PERCEPT_LUT_33," hexmask.long.word 0x250 16.--31. 1. "RESERVED," hexmask.long.word 0x250 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x254 "GLBCE_FWD_PERCEPT_LUT_34," hexmask.long.word 0x254 16.--31. 1. "RESERVED," hexmask.long.word 0x254 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x258 "GLBCE_FWD_PERCEPT_LUT_35," hexmask.long.word 0x258 16.--31. 1. "RESERVED," hexmask.long.word 0x258 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x25C "GLBCE_FWD_PERCEPT_LUT_36," hexmask.long.word 0x25C 16.--31. 1. "RESERVED," hexmask.long.word 0x25C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x260 "GLBCE_FWD_PERCEPT_LUT_37," hexmask.long.word 0x260 16.--31. 1. "RESERVED," hexmask.long.word 0x260 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x264 "GLBCE_FWD_PERCEPT_LUT_38," hexmask.long.word 0x264 16.--31. 1. "RESERVED," hexmask.long.word 0x264 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x268 "GLBCE_FWD_PERCEPT_LUT_39," hexmask.long.word 0x268 16.--31. 1. "RESERVED," hexmask.long.word 0x268 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x26C "GLBCE_FWD_PERCEPT_LUT_40," hexmask.long.word 0x26C 16.--31. 1. "RESERVED," hexmask.long.word 0x26C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x270 "GLBCE_FWD_PERCEPT_LUT_41," hexmask.long.word 0x270 16.--31. 1. "RESERVED," hexmask.long.word 0x270 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x274 "GLBCE_FWD_PERCEPT_LUT_42," hexmask.long.word 0x274 16.--31. 1. "RESERVED," hexmask.long.word 0x274 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x278 "GLBCE_FWD_PERCEPT_LUT_43," hexmask.long.word 0x278 16.--31. 1. "RESERVED," hexmask.long.word 0x278 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x27C "GLBCE_FWD_PERCEPT_LUT_44," hexmask.long.word 0x27C 16.--31. 1. "RESERVED," hexmask.long.word 0x27C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x280 "GLBCE_FWD_PERCEPT_LUT_45," hexmask.long.word 0x280 16.--31. 1. "RESERVED," hexmask.long.word 0x280 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x284 "GLBCE_FWD_PERCEPT_LUT_46," hexmask.long.word 0x284 16.--31. 1. "RESERVED," hexmask.long.word 0x284 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x288 "GLBCE_FWD_PERCEPT_LUT_47," hexmask.long.word 0x288 16.--31. 1. "RESERVED," hexmask.long.word 0x288 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x28C "GLBCE_FWD_PERCEPT_LUT_48," hexmask.long.word 0x28C 16.--31. 1. "RESERVED," hexmask.long.word 0x28C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x290 "GLBCE_FWD_PERCEPT_LUT_49," hexmask.long.word 0x290 16.--31. 1. "RESERVED," hexmask.long.word 0x290 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x294 "GLBCE_FWD_PERCEPT_LUT_50," hexmask.long.word 0x294 16.--31. 1. "RESERVED," hexmask.long.word 0x294 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x298 "GLBCE_FWD_PERCEPT_LUT_51," hexmask.long.word 0x298 16.--31. 1. "RESERVED," hexmask.long.word 0x298 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x29C "GLBCE_FWD_PERCEPT_LUT_52," hexmask.long.word 0x29C 16.--31. 1. "RESERVED," hexmask.long.word 0x29C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2A0 "GLBCE_FWD_PERCEPT_LUT_53," hexmask.long.word 0x2A0 16.--31. 1. "RESERVED," hexmask.long.word 0x2A0 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2A4 "GLBCE_FWD_PERCEPT_LUT_54," hexmask.long.word 0x2A4 16.--31. 1. "RESERVED," hexmask.long.word 0x2A4 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2A8 "GLBCE_FWD_PERCEPT_LUT_55," hexmask.long.word 0x2A8 16.--31. 1. "RESERVED," hexmask.long.word 0x2A8 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2AC "GLBCE_FWD_PERCEPT_LUT_56," hexmask.long.word 0x2AC 16.--31. 1. "RESERVED," hexmask.long.word 0x2AC 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2B0 "GLBCE_FWD_PERCEPT_LUT_57," hexmask.long.word 0x2B0 16.--31. 1. "RESERVED," hexmask.long.word 0x2B0 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2B4 "GLBCE_FWD_PERCEPT_LUT_58," hexmask.long.word 0x2B4 16.--31. 1. "RESERVED," hexmask.long.word 0x2B4 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2B8 "GLBCE_FWD_PERCEPT_LUT_59," hexmask.long.word 0x2B8 16.--31. 1. "RESERVED," hexmask.long.word 0x2B8 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2BC "GLBCE_FWD_PERCEPT_LUT_60," hexmask.long.word 0x2BC 16.--31. 1. "RESERVED," hexmask.long.word 0x2BC 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2C0 "GLBCE_FWD_PERCEPT_LUT_61," hexmask.long.word 0x2C0 16.--31. 1. "RESERVED," hexmask.long.word 0x2C0 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2C4 "GLBCE_FWD_PERCEPT_LUT_62," hexmask.long.word 0x2C4 16.--31. 1. "RESERVED," hexmask.long.word 0x2C4 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2C8 "GLBCE_FWD_PERCEPT_LUT_63," hexmask.long.word 0x2C8 16.--31. 1. "RESERVED," hexmask.long.word 0x2C8 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2CC "GLBCE_FWD_PERCEPT_LUT_64," hexmask.long.word 0x2CC 16.--31. 1. "RESERVED," hexmask.long.word 0x2CC 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2D0 "GLBCE_WDR_GAMMA_EN," hexmask.long 0x2D0 1.--31. 1. "RESERVED," bitfld.long 0x2D0 0. "EN,Frontend WDR LUT enable" "EN_0,EN_1" line.long 0x2D4 "GLBCE_WDR_GAMMA_LUT_00,Frontend WDR LUT" hexmask.long.word 0x2D4 16.--31. 1. "RESERVED," hexmask.long.word 0x2D4 0.--15. 1. "VAL," line.long 0x2D8 "GLBCE_WDR_GAMMA_LUT_01,Frontend WDR LUT" hexmask.long.word 0x2D8 16.--31. 1. "RESERVED," hexmask.long.word 0x2D8 0.--15. 1. "VAL," line.long 0x2DC "GLBCE_WDR_GAMMA_LUT_02,Frontend WDR LUT" hexmask.long.word 0x2DC 16.--31. 1. "RESERVED," hexmask.long.word 0x2DC 0.--15. 1. "VAL," line.long 0x2E0 "GLBCE_WDR_GAMMA_LUT_03,Frontend WDR LUT" hexmask.long.word 0x2E0 16.--31. 1. "RESERVED," hexmask.long.word 0x2E0 0.--15. 1. "VAL," line.long 0x2E4 "GLBCE_WDR_GAMMA_LUT_04,Frontend WDR LUT" hexmask.long.word 0x2E4 16.--31. 1. "RESERVED," hexmask.long.word 0x2E4 0.--15. 1. "VAL," line.long 0x2E8 "GLBCE_WDR_GAMMA_LUT_05,Frontend WDR LUT" hexmask.long.word 0x2E8 16.--31. 1. "RESERVED," hexmask.long.word 0x2E8 0.--15. 1. "VAL," line.long 0x2EC "GLBCE_WDR_GAMMA_LUT_06,Frontend WDR LUT" hexmask.long.word 0x2EC 16.--31. 1. "RESERVED," hexmask.long.word 0x2EC 0.--15. 1. "VAL," line.long 0x2F0 "GLBCE_WDR_GAMMA_LUT_07,Frontend WDR LUT" hexmask.long.word 0x2F0 16.--31. 1. "RESERVED," hexmask.long.word 0x2F0 0.--15. 1. "VAL," line.long 0x2F4 "GLBCE_WDR_GAMMA_LUT_08,Frontend WDR LUT" hexmask.long.word 0x2F4 16.--31. 1. "RESERVED," hexmask.long.word 0x2F4 0.--15. 1. "VAL," line.long 0x2F8 "GLBCE_WDR_GAMMA_LUT_09,Frontend WDR LUT" hexmask.long.word 0x2F8 16.--31. 1. "RESERVED," hexmask.long.word 0x2F8 0.--15. 1. "VAL," line.long 0x2FC "GLBCE_WDR_GAMMA_LUT_10,Frontend WDR LUT" hexmask.long.word 0x2FC 16.--31. 1. "RESERVED," hexmask.long.word 0x2FC 0.--15. 1. "VAL," line.long 0x300 "GLBCE_WDR_GAMMA_LUT_11,Frontend WDR LUT" hexmask.long.word 0x300 16.--31. 1. "RESERVED," hexmask.long.word 0x300 0.--15. 1. "VAL," line.long 0x304 "GLBCE_WDR_GAMMA_LUT_12,Frontend WDR LUT" hexmask.long.word 0x304 16.--31. 1. "RESERVED," hexmask.long.word 0x304 0.--15. 1. "VAL," line.long 0x308 "GLBCE_WDR_GAMMA_LUT_13,Frontend WDR LUT" hexmask.long.word 0x308 16.--31. 1. "RESERVED," hexmask.long.word 0x308 0.--15. 1. "VAL," line.long 0x30C "GLBCE_WDR_GAMMA_LUT_14,Frontend WDR LUT" hexmask.long.word 0x30C 16.--31. 1. "RESERVED," hexmask.long.word 0x30C 0.--15. 1. "VAL," line.long 0x310 "GLBCE_WDR_GAMMA_LUT_15,Frontend WDR LUT" hexmask.long.word 0x310 16.--31. 1. "RESERVED," hexmask.long.word 0x310 0.--15. 1. "VAL," line.long 0x314 "GLBCE_WDR_GAMMA_LUT_16,Frontend WDR LUT" hexmask.long.word 0x314 16.--31. 1. "RESERVED," hexmask.long.word 0x314 0.--15. 1. "VAL," line.long 0x318 "GLBCE_WDR_GAMMA_LUT_17,Frontend WDR LUT" hexmask.long.word 0x318 16.--31. 1. "RESERVED," hexmask.long.word 0x318 0.--15. 1. "VAL," line.long 0x31C "GLBCE_WDR_GAMMA_LUT_18,Frontend WDR LUT" hexmask.long.word 0x31C 16.--31. 1. "RESERVED," hexmask.long.word 0x31C 0.--15. 1. "VAL," line.long 0x320 "GLBCE_WDR_GAMMA_LUT_19,Frontend WDR LUT" hexmask.long.word 0x320 16.--31. 1. "RESERVED," hexmask.long.word 0x320 0.--15. 1. "VAL," line.long 0x324 "GLBCE_WDR_GAMMA_LUT_20,Frontend WDR LUT" hexmask.long.word 0x324 16.--31. 1. "RESERVED," hexmask.long.word 0x324 0.--15. 1. "VAL," line.long 0x328 "GLBCE_WDR_GAMMA_LUT_21,Frontend WDR LUT" hexmask.long.word 0x328 16.--31. 1. "RESERVED," hexmask.long.word 0x328 0.--15. 1. "VAL," line.long 0x32C "GLBCE_WDR_GAMMA_LUT_22,Frontend WDR LUT" hexmask.long.word 0x32C 16.--31. 1. "RESERVED," hexmask.long.word 0x32C 0.--15. 1. "VAL," line.long 0x330 "GLBCE_WDR_GAMMA_LUT_23,Frontend WDR LUT" hexmask.long.word 0x330 16.--31. 1. "RESERVED," hexmask.long.word 0x330 0.--15. 1. "VAL," line.long 0x334 "GLBCE_WDR_GAMMA_LUT_24,Frontend WDR LUT" hexmask.long.word 0x334 16.--31. 1. "RESERVED," hexmask.long.word 0x334 0.--15. 1. "VAL," line.long 0x338 "GLBCE_WDR_GAMMA_LUT_25,Frontend WDR LUT" hexmask.long.word 0x338 16.--31. 1. "RESERVED," hexmask.long.word 0x338 0.--15. 1. "VAL," line.long 0x33C "GLBCE_WDR_GAMMA_LUT_26,Frontend WDR LUT" hexmask.long.word 0x33C 16.--31. 1. "RESERVED," hexmask.long.word 0x33C 0.--15. 1. "VAL," line.long 0x340 "GLBCE_WDR_GAMMA_LUT_27,Frontend WDR LUT" hexmask.long.word 0x340 16.--31. 1. "RESERVED," hexmask.long.word 0x340 0.--15. 1. "VAL," line.long 0x344 "GLBCE_WDR_GAMMA_LUT_28,Frontend WDR LUT" hexmask.long.word 0x344 16.--31. 1. "RESERVED," hexmask.long.word 0x344 0.--15. 1. "VAL," line.long 0x348 "GLBCE_WDR_GAMMA_LUT_29,Frontend WDR LUT" hexmask.long.word 0x348 16.--31. 1. "RESERVED," hexmask.long.word 0x348 0.--15. 1. "VAL," line.long 0x34C "GLBCE_WDR_GAMMA_LUT_30,Frontend WDR LUT" hexmask.long.word 0x34C 16.--31. 1. "RESERVED," hexmask.long.word 0x34C 0.--15. 1. "VAL," line.long 0x350 "GLBCE_WDR_GAMMA_LUT_31,Frontend WDR LUT" hexmask.long.word 0x350 16.--31. 1. "RESERVED," hexmask.long.word 0x350 0.--15. 1. "VAL," line.long 0x354 "GLBCE_WDR_GAMMA_LUT_32,Frontend WDR LUT" hexmask.long.word 0x354 16.--31. 1. "RESERVED," hexmask.long.word 0x354 0.--15. 1. "VAL," line.long 0x358 "GLBCE_WDR_GAMMA_LUT_33,Frontend WDR LUT" hexmask.long.word 0x358 16.--31. 1. "RESERVED," hexmask.long.word 0x358 0.--15. 1. "VAL," line.long 0x35C "GLBCE_WDR_GAMMA_LUT_34,Frontend WDR LUT" hexmask.long.word 0x35C 16.--31. 1. "RESERVED," hexmask.long.word 0x35C 0.--15. 1. "VAL," line.long 0x360 "GLBCE_WDR_GAMMA_LUT_35,Frontend WDR LUT" hexmask.long.word 0x360 16.--31. 1. "RESERVED," hexmask.long.word 0x360 0.--15. 1. "VAL," line.long 0x364 "GLBCE_WDR_GAMMA_LUT_36,Frontend WDR LUT" hexmask.long.word 0x364 16.--31. 1. "RESERVED," hexmask.long.word 0x364 0.--15. 1. "VAL," line.long 0x368 "GLBCE_WDR_GAMMA_LUT_37,Frontend WDR LUT" hexmask.long.word 0x368 16.--31. 1. "RESERVED," hexmask.long.word 0x368 0.--15. 1. "VAL," line.long 0x36C "GLBCE_WDR_GAMMA_LUT_38,Frontend WDR LUT" hexmask.long.word 0x36C 16.--31. 1. "RESERVED," hexmask.long.word 0x36C 0.--15. 1. "VAL," line.long 0x370 "GLBCE_WDR_GAMMA_LUT_39,Frontend WDR LUT" hexmask.long.word 0x370 16.--31. 1. "RESERVED," hexmask.long.word 0x370 0.--15. 1. "VAL," line.long 0x374 "GLBCE_WDR_GAMMA_LUT_40,Frontend WDR LUT" hexmask.long.word 0x374 16.--31. 1. "RESERVED," hexmask.long.word 0x374 0.--15. 1. "VAL," line.long 0x378 "GLBCE_WDR_GAMMA_LUT_41,Frontend WDR LUT" hexmask.long.word 0x378 16.--31. 1. "RESERVED," hexmask.long.word 0x378 0.--15. 1. "VAL," line.long 0x37C "GLBCE_WDR_GAMMA_LUT_42,Frontend WDR LUT" hexmask.long.word 0x37C 16.--31. 1. "RESERVED," hexmask.long.word 0x37C 0.--15. 1. "VAL," line.long 0x380 "GLBCE_WDR_GAMMA_LUT_43,Frontend WDR LUT" hexmask.long.word 0x380 16.--31. 1. "RESERVED," hexmask.long.word 0x380 0.--15. 1. "VAL," line.long 0x384 "GLBCE_WDR_GAMMA_LUT_44,Frontend WDR LUT" hexmask.long.word 0x384 16.--31. 1. "RESERVED," hexmask.long.word 0x384 0.--15. 1. "VAL," line.long 0x388 "GLBCE_WDR_GAMMA_LUT_45,Frontend WDR LUT" hexmask.long.word 0x388 16.--31. 1. "RESERVED," hexmask.long.word 0x388 0.--15. 1. "VAL," line.long 0x38C "GLBCE_WDR_GAMMA_LUT_46,Frontend WDR LUT" hexmask.long.word 0x38C 16.--31. 1. "RESERVED," hexmask.long.word 0x38C 0.--15. 1. "VAL," line.long 0x390 "GLBCE_WDR_GAMMA_LUT_47,Frontend WDR LUT" hexmask.long.word 0x390 16.--31. 1. "RESERVED," hexmask.long.word 0x390 0.--15. 1. "VAL," line.long 0x394 "GLBCE_WDR_GAMMA_LUT_48,Frontend WDR LUT" hexmask.long.word 0x394 16.--31. 1. "RESERVED," hexmask.long.word 0x394 0.--15. 1. "VAL," line.long 0x398 "GLBCE_WDR_GAMMA_LUT_49,Frontend WDR LUT" hexmask.long.word 0x398 16.--31. 1. "RESERVED," hexmask.long.word 0x398 0.--15. 1. "VAL," line.long 0x39C "GLBCE_WDR_GAMMA_LUT_50,Frontend WDR LUT" hexmask.long.word 0x39C 16.--31. 1. "RESERVED," hexmask.long.word 0x39C 0.--15. 1. "VAL," line.long 0x3A0 "GLBCE_WDR_GAMMA_LUT_51,Frontend WDR LUT" hexmask.long.word 0x3A0 16.--31. 1. "RESERVED," hexmask.long.word 0x3A0 0.--15. 1. "VAL," line.long 0x3A4 "GLBCE_WDR_GAMMA_LUT_52,Frontend WDR LUT" hexmask.long.word 0x3A4 16.--31. 1. "RESERVED," hexmask.long.word 0x3A4 0.--15. 1. "VAL," line.long 0x3A8 "GLBCE_WDR_GAMMA_LUT_53,Frontend WDR LUT" hexmask.long.word 0x3A8 16.--31. 1. "RESERVED," hexmask.long.word 0x3A8 0.--15. 1. "VAL," line.long 0x3AC "GLBCE_WDR_GAMMA_LUT_54,Frontend WDR LUT" hexmask.long.word 0x3AC 16.--31. 1. "RESERVED," hexmask.long.word 0x3AC 0.--15. 1. "VAL," line.long 0x3B0 "GLBCE_WDR_GAMMA_LUT_55,Frontend WDR LUT" hexmask.long.word 0x3B0 16.--31. 1. "RESERVED," hexmask.long.word 0x3B0 0.--15. 1. "VAL," line.long 0x3B4 "GLBCE_WDR_GAMMA_LUT_56,Frontend WDR LUT" hexmask.long.word 0x3B4 16.--31. 1. "RESERVED," hexmask.long.word 0x3B4 0.--15. 1. "VAL," line.long 0x3B8 "GLBCE_WDR_GAMMA_LUT_57,Frontend WDR LUT" hexmask.long.word 0x3B8 16.--31. 1. "RESERVED," hexmask.long.word 0x3B8 0.--15. 1. "VAL," line.long 0x3BC "GLBCE_WDR_GAMMA_LUT_58,Frontend WDR LUT" hexmask.long.word 0x3BC 16.--31. 1. "RESERVED," hexmask.long.word 0x3BC 0.--15. 1. "VAL," line.long 0x3C0 "GLBCE_WDR_GAMMA_LUT_59,Frontend WDR LUT" hexmask.long.word 0x3C0 16.--31. 1. "RESERVED," hexmask.long.word 0x3C0 0.--15. 1. "VAL," line.long 0x3C4 "GLBCE_WDR_GAMMA_LUT_60,Frontend WDR LUT" hexmask.long.word 0x3C4 16.--31. 1. "RESERVED," hexmask.long.word 0x3C4 0.--15. 1. "VAL," line.long 0x3C8 "GLBCE_WDR_GAMMA_LUT_61,Frontend WDR LUT" hexmask.long.word 0x3C8 16.--31. 1. "RESERVED," hexmask.long.word 0x3C8 0.--15. 1. "VAL," line.long 0x3CC "GLBCE_WDR_GAMMA_LUT_62,Frontend WDR LUT" hexmask.long.word 0x3CC 16.--31. 1. "RESERVED," hexmask.long.word 0x3CC 0.--15. 1. "VAL," line.long 0x3D0 "GLBCE_WDR_GAMMA_LUT_63,Frontend WDR LUT" hexmask.long.word 0x3D0 16.--31. 1. "RESERVED," hexmask.long.word 0x3D0 0.--15. 1. "VAL," line.long 0x3D4 "GLBCE_WDR_GAMMA_LUT_64,Frontend WDR LUT" hexmask.long.word 0x3D4 16.--31. 1. "RESERVED," hexmask.long.word 0x3D4 0.--15. 1. "VAL," line.long 0x3D8 "GLBCE_WDR_GAMMA_LUT_65,Frontend WDR LUT" hexmask.long.word 0x3D8 16.--31. 1. "RESERVED," hexmask.long.word 0x3D8 0.--15. 1. "VAL," line.long 0x3DC "GLBCE_WDR_GAMMA_LUT_66,Frontend WDR LUT" hexmask.long.word 0x3DC 16.--31. 1. "RESERVED," hexmask.long.word 0x3DC 0.--15. 1. "VAL," line.long 0x3E0 "GLBCE_WDR_GAMMA_LUT_67,Frontend WDR LUT" hexmask.long.word 0x3E0 16.--31. 1. "RESERVED," hexmask.long.word 0x3E0 0.--15. 1. "VAL," line.long 0x3E4 "GLBCE_WDR_GAMMA_LUT_68,Frontend WDR LUT" hexmask.long.word 0x3E4 16.--31. 1. "RESERVED," hexmask.long.word 0x3E4 0.--15. 1. "VAL," line.long 0x3E8 "GLBCE_WDR_GAMMA_LUT_69,Frontend WDR LUT" hexmask.long.word 0x3E8 16.--31. 1. "RESERVED," hexmask.long.word 0x3E8 0.--15. 1. "VAL," line.long 0x3EC "GLBCE_WDR_GAMMA_LUT_70,Frontend WDR LUT" hexmask.long.word 0x3EC 16.--31. 1. "RESERVED," hexmask.long.word 0x3EC 0.--15. 1. "VAL," line.long 0x3F0 "GLBCE_WDR_GAMMA_LUT_71,Frontend WDR LUT" hexmask.long.word 0x3F0 16.--31. 1. "RESERVED," hexmask.long.word 0x3F0 0.--15. 1. "VAL," line.long 0x3F4 "GLBCE_WDR_GAMMA_LUT_72,Frontend WDR LUT" hexmask.long.word 0x3F4 16.--31. 1. "RESERVED," hexmask.long.word 0x3F4 0.--15. 1. "VAL," line.long 0x3F8 "GLBCE_WDR_GAMMA_LUT_73,Frontend WDR LUT" hexmask.long.word 0x3F8 16.--31. 1. "RESERVED," hexmask.long.word 0x3F8 0.--15. 1. "VAL," line.long 0x3FC "GLBCE_WDR_GAMMA_LUT_74,Frontend WDR LUT" hexmask.long.word 0x3FC 16.--31. 1. "RESERVED," hexmask.long.word 0x3FC 0.--15. 1. "VAL," line.long 0x400 "GLBCE_WDR_GAMMA_LUT_75,Frontend WDR LUT" hexmask.long.word 0x400 16.--31. 1. "RESERVED," hexmask.long.word 0x400 0.--15. 1. "VAL," line.long 0x404 "GLBCE_WDR_GAMMA_LUT_76,Frontend WDR LUT" hexmask.long.word 0x404 16.--31. 1. "RESERVED," hexmask.long.word 0x404 0.--15. 1. "VAL," line.long 0x408 "GLBCE_WDR_GAMMA_LUT_77,Frontend WDR LUT" hexmask.long.word 0x408 16.--31. 1. "RESERVED," hexmask.long.word 0x408 0.--15. 1. "VAL," line.long 0x40C "GLBCE_WDR_GAMMA_LUT_78,Frontend WDR LUT" hexmask.long.word 0x40C 16.--31. 1. "RESERVED," hexmask.long.word 0x40C 0.--15. 1. "VAL," line.long 0x410 "GLBCE_WDR_GAMMA_LUT_79,Frontend WDR LUT" hexmask.long.word 0x410 16.--31. 1. "RESERVED," hexmask.long.word 0x410 0.--15. 1. "VAL," line.long 0x414 "GLBCE_WDR_GAMMA_LUT_80,Frontend WDR LUT" hexmask.long.word 0x414 16.--31. 1. "RESERVED," hexmask.long.word 0x414 0.--15. 1. "VAL," line.long 0x418 "GLBCE_WDR_GAMMA_LUT_81,Frontend WDR LUT" hexmask.long.word 0x418 16.--31. 1. "RESERVED," hexmask.long.word 0x418 0.--15. 1. "VAL," line.long 0x41C "GLBCE_WDR_GAMMA_LUT_82,Frontend WDR LUT" hexmask.long.word 0x41C 16.--31. 1. "RESERVED," hexmask.long.word 0x41C 0.--15. 1. "VAL," line.long 0x420 "GLBCE_WDR_GAMMA_LUT_83,Frontend WDR LUT" hexmask.long.word 0x420 16.--31. 1. "RESERVED," hexmask.long.word 0x420 0.--15. 1. "VAL," line.long 0x424 "GLBCE_WDR_GAMMA_LUT_84,Frontend WDR LUT" hexmask.long.word 0x424 16.--31. 1. "RESERVED," hexmask.long.word 0x424 0.--15. 1. "VAL," line.long 0x428 "GLBCE_WDR_GAMMA_LUT_85,Frontend WDR LUT" hexmask.long.word 0x428 16.--31. 1. "RESERVED," hexmask.long.word 0x428 0.--15. 1. "VAL," line.long 0x42C "GLBCE_WDR_GAMMA_LUT_86,Frontend WDR LUT" hexmask.long.word 0x42C 16.--31. 1. "RESERVED," hexmask.long.word 0x42C 0.--15. 1. "VAL," line.long 0x430 "GLBCE_WDR_GAMMA_LUT_87,Frontend WDR LUT" hexmask.long.word 0x430 16.--31. 1. "RESERVED," hexmask.long.word 0x430 0.--15. 1. "VAL," line.long 0x434 "GLBCE_WDR_GAMMA_LUT_88,Frontend WDR LUT" hexmask.long.word 0x434 16.--31. 1. "RESERVED," hexmask.long.word 0x434 0.--15. 1. "VAL," line.long 0x438 "GLBCE_WDR_GAMMA_LUT_89,Frontend WDR LUT" hexmask.long.word 0x438 16.--31. 1. "RESERVED," hexmask.long.word 0x438 0.--15. 1. "VAL," line.long 0x43C "GLBCE_WDR_GAMMA_LUT_90,Frontend WDR LUT" hexmask.long.word 0x43C 16.--31. 1. "RESERVED," hexmask.long.word 0x43C 0.--15. 1. "VAL," line.long 0x440 "GLBCE_WDR_GAMMA_LUT_91,Frontend WDR LUT" hexmask.long.word 0x440 16.--31. 1. "RESERVED," hexmask.long.word 0x440 0.--15. 1. "VAL," line.long 0x444 "GLBCE_WDR_GAMMA_LUT_92,Frontend WDR LUT" hexmask.long.word 0x444 16.--31. 1. "RESERVED," hexmask.long.word 0x444 0.--15. 1. "VAL," line.long 0x448 "GLBCE_WDR_GAMMA_LUT_93,Frontend WDR LUT" hexmask.long.word 0x448 16.--31. 1. "RESERVED," hexmask.long.word 0x448 0.--15. 1. "VAL," line.long 0x44C "GLBCE_WDR_GAMMA_LUT_94,Frontend WDR LUT" hexmask.long.word 0x44C 16.--31. 1. "RESERVED," hexmask.long.word 0x44C 0.--15. 1. "VAL," line.long 0x450 "GLBCE_WDR_GAMMA_LUT_95,Frontend WDR LUT" hexmask.long.word 0x450 16.--31. 1. "RESERVED," hexmask.long.word 0x450 0.--15. 1. "VAL," line.long 0x454 "GLBCE_WDR_GAMMA_LUT_96,Frontend WDR LUT" hexmask.long.word 0x454 16.--31. 1. "RESERVED," hexmask.long.word 0x454 0.--15. 1. "VAL," line.long 0x458 "GLBCE_WDR_GAMMA_LUT_97,Frontend WDR LUT" hexmask.long.word 0x458 16.--31. 1. "RESERVED," hexmask.long.word 0x458 0.--15. 1. "VAL," line.long 0x45C "GLBCE_WDR_GAMMA_LUT_98,Frontend WDR LUT" hexmask.long.word 0x45C 16.--31. 1. "RESERVED," hexmask.long.word 0x45C 0.--15. 1. "VAL," line.long 0x460 "GLBCE_WDR_GAMMA_LUT_99,Frontend WDR LUT" hexmask.long.word 0x460 16.--31. 1. "RESERVED," hexmask.long.word 0x460 0.--15. 1. "VAL," line.long 0x464 "GLBCE_WDR_GAMMA_LUT_100,Frontend WDR LUT" hexmask.long.word 0x464 16.--31. 1. "RESERVED," hexmask.long.word 0x464 0.--15. 1. "VAL," line.long 0x468 "GLBCE_WDR_GAMMA_LUT_101,Frontend WDR LUT" hexmask.long.word 0x468 16.--31. 1. "RESERVED," hexmask.long.word 0x468 0.--15. 1. "VAL," line.long 0x46C "GLBCE_WDR_GAMMA_LUT_102,Frontend WDR LUT" hexmask.long.word 0x46C 16.--31. 1. "RESERVED," hexmask.long.word 0x46C 0.--15. 1. "VAL," line.long 0x470 "GLBCE_WDR_GAMMA_LUT_103,Frontend WDR LUT" hexmask.long.word 0x470 16.--31. 1. "RESERVED," hexmask.long.word 0x470 0.--15. 1. "VAL," line.long 0x474 "GLBCE_WDR_GAMMA_LUT_104,Frontend WDR LUT" hexmask.long.word 0x474 16.--31. 1. "RESERVED," hexmask.long.word 0x474 0.--15. 1. "VAL," line.long 0x478 "GLBCE_WDR_GAMMA_LUT_105,Frontend WDR LUT" hexmask.long.word 0x478 16.--31. 1. "RESERVED," hexmask.long.word 0x478 0.--15. 1. "VAL," line.long 0x47C "GLBCE_WDR_GAMMA_LUT_106,Frontend WDR LUT" hexmask.long.word 0x47C 16.--31. 1. "RESERVED," hexmask.long.word 0x47C 0.--15. 1. "VAL," line.long 0x480 "GLBCE_WDR_GAMMA_LUT_107,Frontend WDR LUT" hexmask.long.word 0x480 16.--31. 1. "RESERVED," hexmask.long.word 0x480 0.--15. 1. "VAL," line.long 0x484 "GLBCE_WDR_GAMMA_LUT_108,Frontend WDR LUT" hexmask.long.word 0x484 16.--31. 1. "RESERVED," hexmask.long.word 0x484 0.--15. 1. "VAL," line.long 0x488 "GLBCE_WDR_GAMMA_LUT_109,Frontend WDR LUT" hexmask.long.word 0x488 16.--31. 1. "RESERVED," hexmask.long.word 0x488 0.--15. 1. "VAL," line.long 0x48C "GLBCE_WDR_GAMMA_LUT_110,Frontend WDR LUT" hexmask.long.word 0x48C 16.--31. 1. "RESERVED," hexmask.long.word 0x48C 0.--15. 1. "VAL," line.long 0x490 "GLBCE_WDR_GAMMA_LUT_111,Frontend WDR LUT" hexmask.long.word 0x490 16.--31. 1. "RESERVED," hexmask.long.word 0x490 0.--15. 1. "VAL," line.long 0x494 "GLBCE_WDR_GAMMA_LUT_112,Frontend WDR LUT" hexmask.long.word 0x494 16.--31. 1. "RESERVED," hexmask.long.word 0x494 0.--15. 1. "VAL," line.long 0x498 "GLBCE_WDR_GAMMA_LUT_113,Frontend WDR LUT" hexmask.long.word 0x498 16.--31. 1. "RESERVED," hexmask.long.word 0x498 0.--15. 1. "VAL," line.long 0x49C "GLBCE_WDR_GAMMA_LUT_114,Frontend WDR LUT" hexmask.long.word 0x49C 16.--31. 1. "RESERVED," hexmask.long.word 0x49C 0.--15. 1. "VAL," line.long 0x4A0 "GLBCE_WDR_GAMMA_LUT_115,Frontend WDR LUT" hexmask.long.word 0x4A0 16.--31. 1. "RESERVED," hexmask.long.word 0x4A0 0.--15. 1. "VAL," line.long 0x4A4 "GLBCE_WDR_GAMMA_LUT_116,Frontend WDR LUT" hexmask.long.word 0x4A4 16.--31. 1. "RESERVED," hexmask.long.word 0x4A4 0.--15. 1. "VAL," line.long 0x4A8 "GLBCE_WDR_GAMMA_LUT_117,Frontend WDR LUT" hexmask.long.word 0x4A8 16.--31. 1. "RESERVED," hexmask.long.word 0x4A8 0.--15. 1. "VAL," line.long 0x4AC "GLBCE_WDR_GAMMA_LUT_118,Frontend WDR LUT" hexmask.long.word 0x4AC 16.--31. 1. "RESERVED," hexmask.long.word 0x4AC 0.--15. 1. "VAL," line.long 0x4B0 "GLBCE_WDR_GAMMA_LUT_119,Frontend WDR LUT" hexmask.long.word 0x4B0 16.--31. 1. "RESERVED," hexmask.long.word 0x4B0 0.--15. 1. "VAL," line.long 0x4B4 "GLBCE_WDR_GAMMA_LUT_120,Frontend WDR LUT" hexmask.long.word 0x4B4 16.--31. 1. "RESERVED," hexmask.long.word 0x4B4 0.--15. 1. "VAL," line.long 0x4B8 "GLBCE_WDR_GAMMA_LUT_121,Frontend WDR LUT" hexmask.long.word 0x4B8 16.--31. 1. "RESERVED," hexmask.long.word 0x4B8 0.--15. 1. "VAL," line.long 0x4BC "GLBCE_WDR_GAMMA_LUT_122,Frontend WDR LUT" hexmask.long.word 0x4BC 16.--31. 1. "RESERVED," hexmask.long.word 0x4BC 0.--15. 1. "VAL," line.long 0x4C0 "GLBCE_WDR_GAMMA_LUT_123,Frontend WDR LUT" hexmask.long.word 0x4C0 16.--31. 1. "RESERVED," hexmask.long.word 0x4C0 0.--15. 1. "VAL," line.long 0x4C4 "GLBCE_WDR_GAMMA_LUT_124,Frontend WDR LUT" hexmask.long.word 0x4C4 16.--31. 1. "RESERVED," hexmask.long.word 0x4C4 0.--15. 1. "VAL," line.long 0x4C8 "GLBCE_WDR_GAMMA_LUT_125,Frontend WDR LUT" hexmask.long.word 0x4C8 16.--31. 1. "RESERVED," hexmask.long.word 0x4C8 0.--15. 1. "VAL," line.long 0x4CC "GLBCE_WDR_GAMMA_LUT_126,Frontend WDR LUT" hexmask.long.word 0x4CC 16.--31. 1. "RESERVED," hexmask.long.word 0x4CC 0.--15. 1. "VAL," line.long 0x4D0 "GLBCE_WDR_GAMMA_LUT_127,Frontend WDR LUT" hexmask.long.word 0x4D0 16.--31. 1. "RESERVED," hexmask.long.word 0x4D0 0.--15. 1. "VAL," line.long 0x4D4 "GLBCE_WDR_GAMMA_LUT_128,Frontend WDR LUT" hexmask.long.word 0x4D4 16.--31. 1. "RESERVED," hexmask.long.word 0x4D4 0.--15. 1. "VAL," line.long 0x4D8 "GLBCE_WDR_GAMMA_LUT_129,Frontend WDR LUT" hexmask.long.word 0x4D8 16.--31. 1. "RESERVED," hexmask.long.word 0x4D8 0.--15. 1. "VAL," line.long 0x4DC "GLBCE_WDR_GAMMA_LUT_130,Frontend WDR LUT" hexmask.long.word 0x4DC 16.--31. 1. "RESERVED," hexmask.long.word 0x4DC 0.--15. 1. "VAL," line.long 0x4E0 "GLBCE_WDR_GAMMA_LUT_131,Frontend WDR LUT" hexmask.long.word 0x4E0 16.--31. 1. "RESERVED," hexmask.long.word 0x4E0 0.--15. 1. "VAL," line.long 0x4E4 "GLBCE_WDR_GAMMA_LUT_132,Frontend WDR LUT" hexmask.long.word 0x4E4 16.--31. 1. "RESERVED," hexmask.long.word 0x4E4 0.--15. 1. "VAL," line.long 0x4E8 "GLBCE_WDR_GAMMA_LUT_133,Frontend WDR LUT" hexmask.long.word 0x4E8 16.--31. 1. "RESERVED," hexmask.long.word 0x4E8 0.--15. 1. "VAL," line.long 0x4EC "GLBCE_WDR_GAMMA_LUT_134,Frontend WDR LUT" hexmask.long.word 0x4EC 16.--31. 1. "RESERVED," hexmask.long.word 0x4EC 0.--15. 1. "VAL," line.long 0x4F0 "GLBCE_WDR_GAMMA_LUT_135,Frontend WDR LUT" hexmask.long.word 0x4F0 16.--31. 1. "RESERVED," hexmask.long.word 0x4F0 0.--15. 1. "VAL," line.long 0x4F4 "GLBCE_WDR_GAMMA_LUT_136,Frontend WDR LUT" hexmask.long.word 0x4F4 16.--31. 1. "RESERVED," hexmask.long.word 0x4F4 0.--15. 1. "VAL," line.long 0x4F8 "GLBCE_WDR_GAMMA_LUT_137,Frontend WDR LUT" hexmask.long.word 0x4F8 16.--31. 1. "RESERVED," hexmask.long.word 0x4F8 0.--15. 1. "VAL," line.long 0x4FC "GLBCE_WDR_GAMMA_LUT_138,Frontend WDR LUT" hexmask.long.word 0x4FC 16.--31. 1. "RESERVED," hexmask.long.word 0x4FC 0.--15. 1. "VAL," line.long 0x500 "GLBCE_WDR_GAMMA_LUT_139,Frontend WDR LUT" hexmask.long.word 0x500 16.--31. 1. "RESERVED," hexmask.long.word 0x500 0.--15. 1. "VAL," line.long 0x504 "GLBCE_WDR_GAMMA_LUT_140,Frontend WDR LUT" hexmask.long.word 0x504 16.--31. 1. "RESERVED," hexmask.long.word 0x504 0.--15. 1. "VAL," line.long 0x508 "GLBCE_WDR_GAMMA_LUT_141,Frontend WDR LUT" hexmask.long.word 0x508 16.--31. 1. "RESERVED," hexmask.long.word 0x508 0.--15. 1. "VAL," line.long 0x50C "GLBCE_WDR_GAMMA_LUT_142,Frontend WDR LUT" hexmask.long.word 0x50C 16.--31. 1. "RESERVED," hexmask.long.word 0x50C 0.--15. 1. "VAL," line.long 0x510 "GLBCE_WDR_GAMMA_LUT_143,Frontend WDR LUT" hexmask.long.word 0x510 16.--31. 1. "RESERVED," hexmask.long.word 0x510 0.--15. 1. "VAL," line.long 0x514 "GLBCE_WDR_GAMMA_LUT_144,Frontend WDR LUT" hexmask.long.word 0x514 16.--31. 1. "RESERVED," hexmask.long.word 0x514 0.--15. 1. "VAL," line.long 0x518 "GLBCE_WDR_GAMMA_LUT_145,Frontend WDR LUT" hexmask.long.word 0x518 16.--31. 1. "RESERVED," hexmask.long.word 0x518 0.--15. 1. "VAL," line.long 0x51C "GLBCE_WDR_GAMMA_LUT_146,Frontend WDR LUT" hexmask.long.word 0x51C 16.--31. 1. "RESERVED," hexmask.long.word 0x51C 0.--15. 1. "VAL," line.long 0x520 "GLBCE_WDR_GAMMA_LUT_147,Frontend WDR LUT" hexmask.long.word 0x520 16.--31. 1. "RESERVED," hexmask.long.word 0x520 0.--15. 1. "VAL," line.long 0x524 "GLBCE_WDR_GAMMA_LUT_148,Frontend WDR LUT" hexmask.long.word 0x524 16.--31. 1. "RESERVED," hexmask.long.word 0x524 0.--15. 1. "VAL," line.long 0x528 "GLBCE_WDR_GAMMA_LUT_149,Frontend WDR LUT" hexmask.long.word 0x528 16.--31. 1. "RESERVED," hexmask.long.word 0x528 0.--15. 1. "VAL," line.long 0x52C "GLBCE_WDR_GAMMA_LUT_150,Frontend WDR LUT" hexmask.long.word 0x52C 16.--31. 1. "RESERVED," hexmask.long.word 0x52C 0.--15. 1. "VAL," line.long 0x530 "GLBCE_WDR_GAMMA_LUT_151,Frontend WDR LUT" hexmask.long.word 0x530 16.--31. 1. "RESERVED," hexmask.long.word 0x530 0.--15. 1. "VAL," line.long 0x534 "GLBCE_WDR_GAMMA_LUT_152,Frontend WDR LUT" hexmask.long.word 0x534 16.--31. 1. "RESERVED," hexmask.long.word 0x534 0.--15. 1. "VAL," line.long 0x538 "GLBCE_WDR_GAMMA_LUT_153,Frontend WDR LUT" hexmask.long.word 0x538 16.--31. 1. "RESERVED," hexmask.long.word 0x538 0.--15. 1. "VAL," line.long 0x53C "GLBCE_WDR_GAMMA_LUT_154,Frontend WDR LUT" hexmask.long.word 0x53C 16.--31. 1. "RESERVED," hexmask.long.word 0x53C 0.--15. 1. "VAL," line.long 0x540 "GLBCE_WDR_GAMMA_LUT_155,Frontend WDR LUT" hexmask.long.word 0x540 16.--31. 1. "RESERVED," hexmask.long.word 0x540 0.--15. 1. "VAL," line.long 0x544 "GLBCE_WDR_GAMMA_LUT_156,Frontend WDR LUT" hexmask.long.word 0x544 16.--31. 1. "RESERVED," hexmask.long.word 0x544 0.--15. 1. "VAL," line.long 0x548 "GLBCE_WDR_GAMMA_LUT_157,Frontend WDR LUT" hexmask.long.word 0x548 16.--31. 1. "RESERVED," hexmask.long.word 0x548 0.--15. 1. "VAL," line.long 0x54C "GLBCE_WDR_GAMMA_LUT_158,Frontend WDR LUT" hexmask.long.word 0x54C 16.--31. 1. "RESERVED," hexmask.long.word 0x54C 0.--15. 1. "VAL," line.long 0x550 "GLBCE_WDR_GAMMA_LUT_159,Frontend WDR LUT" hexmask.long.word 0x550 16.--31. 1. "RESERVED," hexmask.long.word 0x550 0.--15. 1. "VAL," line.long 0x554 "GLBCE_WDR_GAMMA_LUT_160,Frontend WDR LUT" hexmask.long.word 0x554 16.--31. 1. "RESERVED," hexmask.long.word 0x554 0.--15. 1. "VAL," line.long 0x558 "GLBCE_WDR_GAMMA_LUT_161,Frontend WDR LUT" hexmask.long.word 0x558 16.--31. 1. "RESERVED," hexmask.long.word 0x558 0.--15. 1. "VAL," line.long 0x55C "GLBCE_WDR_GAMMA_LUT_162,Frontend WDR LUT" hexmask.long.word 0x55C 16.--31. 1. "RESERVED," hexmask.long.word 0x55C 0.--15. 1. "VAL," line.long 0x560 "GLBCE_WDR_GAMMA_LUT_163,Frontend WDR LUT" hexmask.long.word 0x560 16.--31. 1. "RESERVED," hexmask.long.word 0x560 0.--15. 1. "VAL," line.long 0x564 "GLBCE_WDR_GAMMA_LUT_164,Frontend WDR LUT" hexmask.long.word 0x564 16.--31. 1. "RESERVED," hexmask.long.word 0x564 0.--15. 1. "VAL," line.long 0x568 "GLBCE_WDR_GAMMA_LUT_165,Frontend WDR LUT" hexmask.long.word 0x568 16.--31. 1. "RESERVED," hexmask.long.word 0x568 0.--15. 1. "VAL," line.long 0x56C "GLBCE_WDR_GAMMA_LUT_166,Frontend WDR LUT" hexmask.long.word 0x56C 16.--31. 1. "RESERVED," hexmask.long.word 0x56C 0.--15. 1. "VAL," line.long 0x570 "GLBCE_WDR_GAMMA_LUT_167,Frontend WDR LUT" hexmask.long.word 0x570 16.--31. 1. "RESERVED," hexmask.long.word 0x570 0.--15. 1. "VAL," line.long 0x574 "GLBCE_WDR_GAMMA_LUT_168,Frontend WDR LUT" hexmask.long.word 0x574 16.--31. 1. "RESERVED," hexmask.long.word 0x574 0.--15. 1. "VAL," line.long 0x578 "GLBCE_WDR_GAMMA_LUT_169,Frontend WDR LUT" hexmask.long.word 0x578 16.--31. 1. "RESERVED," hexmask.long.word 0x578 0.--15. 1. "VAL," line.long 0x57C "GLBCE_WDR_GAMMA_LUT_170,Frontend WDR LUT" hexmask.long.word 0x57C 16.--31. 1. "RESERVED," hexmask.long.word 0x57C 0.--15. 1. "VAL," line.long 0x580 "GLBCE_WDR_GAMMA_LUT_171,Frontend WDR LUT" hexmask.long.word 0x580 16.--31. 1. "RESERVED," hexmask.long.word 0x580 0.--15. 1. "VAL," line.long 0x584 "GLBCE_WDR_GAMMA_LUT_172,Frontend WDR LUT" hexmask.long.word 0x584 16.--31. 1. "RESERVED," hexmask.long.word 0x584 0.--15. 1. "VAL," line.long 0x588 "GLBCE_WDR_GAMMA_LUT_173,Frontend WDR LUT" hexmask.long.word 0x588 16.--31. 1. "RESERVED," hexmask.long.word 0x588 0.--15. 1. "VAL," line.long 0x58C "GLBCE_WDR_GAMMA_LUT_174,Frontend WDR LUT" hexmask.long.word 0x58C 16.--31. 1. "RESERVED," hexmask.long.word 0x58C 0.--15. 1. "VAL," line.long 0x590 "GLBCE_WDR_GAMMA_LUT_175,Frontend WDR LUT" hexmask.long.word 0x590 16.--31. 1. "RESERVED," hexmask.long.word 0x590 0.--15. 1. "VAL," line.long 0x594 "GLBCE_WDR_GAMMA_LUT_176,Frontend WDR LUT" hexmask.long.word 0x594 16.--31. 1. "RESERVED," hexmask.long.word 0x594 0.--15. 1. "VAL," line.long 0x598 "GLBCE_WDR_GAMMA_LUT_177,Frontend WDR LUT" hexmask.long.word 0x598 16.--31. 1. "RESERVED," hexmask.long.word 0x598 0.--15. 1. "VAL," line.long 0x59C "GLBCE_WDR_GAMMA_LUT_178,Frontend WDR LUT" hexmask.long.word 0x59C 16.--31. 1. "RESERVED," hexmask.long.word 0x59C 0.--15. 1. "VAL," line.long 0x5A0 "GLBCE_WDR_GAMMA_LUT_179,Frontend WDR LUT" hexmask.long.word 0x5A0 16.--31. 1. "RESERVED," hexmask.long.word 0x5A0 0.--15. 1. "VAL," line.long 0x5A4 "GLBCE_WDR_GAMMA_LUT_180,Frontend WDR LUT" hexmask.long.word 0x5A4 16.--31. 1. "RESERVED," hexmask.long.word 0x5A4 0.--15. 1. "VAL," line.long 0x5A8 "GLBCE_WDR_GAMMA_LUT_181,Frontend WDR LUT" hexmask.long.word 0x5A8 16.--31. 1. "RESERVED," hexmask.long.word 0x5A8 0.--15. 1. "VAL," line.long 0x5AC "GLBCE_WDR_GAMMA_LUT_182,Frontend WDR LUT" hexmask.long.word 0x5AC 16.--31. 1. "RESERVED," hexmask.long.word 0x5AC 0.--15. 1. "VAL," line.long 0x5B0 "GLBCE_WDR_GAMMA_LUT_183,Frontend WDR LUT" hexmask.long.word 0x5B0 16.--31. 1. "RESERVED," hexmask.long.word 0x5B0 0.--15. 1. "VAL," line.long 0x5B4 "GLBCE_WDR_GAMMA_LUT_184,Frontend WDR LUT" hexmask.long.word 0x5B4 16.--31. 1. "RESERVED," hexmask.long.word 0x5B4 0.--15. 1. "VAL," line.long 0x5B8 "GLBCE_WDR_GAMMA_LUT_185,Frontend WDR LUT" hexmask.long.word 0x5B8 16.--31. 1. "RESERVED," hexmask.long.word 0x5B8 0.--15. 1. "VAL," line.long 0x5BC "GLBCE_WDR_GAMMA_LUT_186,Frontend WDR LUT" hexmask.long.word 0x5BC 16.--31. 1. "RESERVED," hexmask.long.word 0x5BC 0.--15. 1. "VAL," line.long 0x5C0 "GLBCE_WDR_GAMMA_LUT_187,Frontend WDR LUT" hexmask.long.word 0x5C0 16.--31. 1. "RESERVED," hexmask.long.word 0x5C0 0.--15. 1. "VAL," line.long 0x5C4 "GLBCE_WDR_GAMMA_LUT_188,Frontend WDR LUT" hexmask.long.word 0x5C4 16.--31. 1. "RESERVED," hexmask.long.word 0x5C4 0.--15. 1. "VAL," line.long 0x5C8 "GLBCE_WDR_GAMMA_LUT_189,Frontend WDR LUT" hexmask.long.word 0x5C8 16.--31. 1. "RESERVED," hexmask.long.word 0x5C8 0.--15. 1. "VAL," line.long 0x5CC "GLBCE_WDR_GAMMA_LUT_190,Frontend WDR LUT" hexmask.long.word 0x5CC 16.--31. 1. "RESERVED," hexmask.long.word 0x5CC 0.--15. 1. "VAL," line.long 0x5D0 "GLBCE_WDR_GAMMA_LUT_191,Frontend WDR LUT" hexmask.long.word 0x5D0 16.--31. 1. "RESERVED," hexmask.long.word 0x5D0 0.--15. 1. "VAL," line.long 0x5D4 "GLBCE_WDR_GAMMA_LUT_192,Frontend WDR LUT" hexmask.long.word 0x5D4 16.--31. 1. "RESERVED," hexmask.long.word 0x5D4 0.--15. 1. "VAL," line.long 0x5D8 "GLBCE_WDR_GAMMA_LUT_193,Frontend WDR LUT" hexmask.long.word 0x5D8 16.--31. 1. "RESERVED," hexmask.long.word 0x5D8 0.--15. 1. "VAL," line.long 0x5DC "GLBCE_WDR_GAMMA_LUT_194,Frontend WDR LUT" hexmask.long.word 0x5DC 16.--31. 1. "RESERVED," hexmask.long.word 0x5DC 0.--15. 1. "VAL," line.long 0x5E0 "GLBCE_WDR_GAMMA_LUT_195,Frontend WDR LUT" hexmask.long.word 0x5E0 16.--31. 1. "RESERVED," hexmask.long.word 0x5E0 0.--15. 1. "VAL," line.long 0x5E4 "GLBCE_WDR_GAMMA_LUT_196,Frontend WDR LUT" hexmask.long.word 0x5E4 16.--31. 1. "RESERVED," hexmask.long.word 0x5E4 0.--15. 1. "VAL," line.long 0x5E8 "GLBCE_WDR_GAMMA_LUT_197,Frontend WDR LUT" hexmask.long.word 0x5E8 16.--31. 1. "RESERVED," hexmask.long.word 0x5E8 0.--15. 1. "VAL," line.long 0x5EC "GLBCE_WDR_GAMMA_LUT_198,Frontend WDR LUT" hexmask.long.word 0x5EC 16.--31. 1. "RESERVED," hexmask.long.word 0x5EC 0.--15. 1. "VAL," line.long 0x5F0 "GLBCE_WDR_GAMMA_LUT_199,Frontend WDR LUT" hexmask.long.word 0x5F0 16.--31. 1. "RESERVED," hexmask.long.word 0x5F0 0.--15. 1. "VAL," line.long 0x5F4 "GLBCE_WDR_GAMMA_LUT_200,Frontend WDR LUT" hexmask.long.word 0x5F4 16.--31. 1. "RESERVED," hexmask.long.word 0x5F4 0.--15. 1. "VAL," line.long 0x5F8 "GLBCE_WDR_GAMMA_LUT_201,Frontend WDR LUT" hexmask.long.word 0x5F8 16.--31. 1. "RESERVED," hexmask.long.word 0x5F8 0.--15. 1. "VAL," line.long 0x5FC "GLBCE_WDR_GAMMA_LUT_202,Frontend WDR LUT" hexmask.long.word 0x5FC 16.--31. 1. "RESERVED," hexmask.long.word 0x5FC 0.--15. 1. "VAL," line.long 0x600 "GLBCE_WDR_GAMMA_LUT_203,Frontend WDR LUT" hexmask.long.word 0x600 16.--31. 1. "RESERVED," hexmask.long.word 0x600 0.--15. 1. "VAL," line.long 0x604 "GLBCE_WDR_GAMMA_LUT_204,Frontend WDR LUT" hexmask.long.word 0x604 16.--31. 1. "RESERVED," hexmask.long.word 0x604 0.--15. 1. "VAL," line.long 0x608 "GLBCE_WDR_GAMMA_LUT_205,Frontend WDR LUT" hexmask.long.word 0x608 16.--31. 1. "RESERVED," hexmask.long.word 0x608 0.--15. 1. "VAL," line.long 0x60C "GLBCE_WDR_GAMMA_LUT_206,Frontend WDR LUT" hexmask.long.word 0x60C 16.--31. 1. "RESERVED," hexmask.long.word 0x60C 0.--15. 1. "VAL," line.long 0x610 "GLBCE_WDR_GAMMA_LUT_207,Frontend WDR LUT" hexmask.long.word 0x610 16.--31. 1. "RESERVED," hexmask.long.word 0x610 0.--15. 1. "VAL," line.long 0x614 "GLBCE_WDR_GAMMA_LUT_208,Frontend WDR LUT" hexmask.long.word 0x614 16.--31. 1. "RESERVED," hexmask.long.word 0x614 0.--15. 1. "VAL," line.long 0x618 "GLBCE_WDR_GAMMA_LUT_209,Frontend WDR LUT" hexmask.long.word 0x618 16.--31. 1. "RESERVED," hexmask.long.word 0x618 0.--15. 1. "VAL," line.long 0x61C "GLBCE_WDR_GAMMA_LUT_210,Frontend WDR LUT" hexmask.long.word 0x61C 16.--31. 1. "RESERVED," hexmask.long.word 0x61C 0.--15. 1. "VAL," line.long 0x620 "GLBCE_WDR_GAMMA_LUT_211,Frontend WDR LUT" hexmask.long.word 0x620 16.--31. 1. "RESERVED," hexmask.long.word 0x620 0.--15. 1. "VAL," line.long 0x624 "GLBCE_WDR_GAMMA_LUT_212,Frontend WDR LUT" hexmask.long.word 0x624 16.--31. 1. "RESERVED," hexmask.long.word 0x624 0.--15. 1. "VAL," line.long 0x628 "GLBCE_WDR_GAMMA_LUT_213,Frontend WDR LUT" hexmask.long.word 0x628 16.--31. 1. "RESERVED," hexmask.long.word 0x628 0.--15. 1. "VAL," line.long 0x62C "GLBCE_WDR_GAMMA_LUT_214,Frontend WDR LUT" hexmask.long.word 0x62C 16.--31. 1. "RESERVED," hexmask.long.word 0x62C 0.--15. 1. "VAL," line.long 0x630 "GLBCE_WDR_GAMMA_LUT_215,Frontend WDR LUT" hexmask.long.word 0x630 16.--31. 1. "RESERVED," hexmask.long.word 0x630 0.--15. 1. "VAL," line.long 0x634 "GLBCE_WDR_GAMMA_LUT_216,Frontend WDR LUT" hexmask.long.word 0x634 16.--31. 1. "RESERVED," hexmask.long.word 0x634 0.--15. 1. "VAL," line.long 0x638 "GLBCE_WDR_GAMMA_LUT_217,Frontend WDR LUT" hexmask.long.word 0x638 16.--31. 1. "RESERVED," hexmask.long.word 0x638 0.--15. 1. "VAL," line.long 0x63C "GLBCE_WDR_GAMMA_LUT_218,Frontend WDR LUT" hexmask.long.word 0x63C 16.--31. 1. "RESERVED," hexmask.long.word 0x63C 0.--15. 1. "VAL," line.long 0x640 "GLBCE_WDR_GAMMA_LUT_219,Frontend WDR LUT" hexmask.long.word 0x640 16.--31. 1. "RESERVED," hexmask.long.word 0x640 0.--15. 1. "VAL," line.long 0x644 "GLBCE_WDR_GAMMA_LUT_220,Frontend WDR LUT" hexmask.long.word 0x644 16.--31. 1. "RESERVED," hexmask.long.word 0x644 0.--15. 1. "VAL," line.long 0x648 "GLBCE_WDR_GAMMA_LUT_221,Frontend WDR LUT" hexmask.long.word 0x648 16.--31. 1. "RESERVED," hexmask.long.word 0x648 0.--15. 1. "VAL," line.long 0x64C "GLBCE_WDR_GAMMA_LUT_222,Frontend WDR LUT" hexmask.long.word 0x64C 16.--31. 1. "RESERVED," hexmask.long.word 0x64C 0.--15. 1. "VAL," line.long 0x650 "GLBCE_WDR_GAMMA_LUT_223,Frontend WDR LUT" hexmask.long.word 0x650 16.--31. 1. "RESERVED," hexmask.long.word 0x650 0.--15. 1. "VAL," line.long 0x654 "GLBCE_WDR_GAMMA_LUT_224,Frontend WDR LUT" hexmask.long.word 0x654 16.--31. 1. "RESERVED," hexmask.long.word 0x654 0.--15. 1. "VAL," line.long 0x658 "GLBCE_WDR_GAMMA_LUT_225,Frontend WDR LUT" hexmask.long.word 0x658 16.--31. 1. "RESERVED," hexmask.long.word 0x658 0.--15. 1. "VAL," line.long 0x65C "GLBCE_WDR_GAMMA_LUT_226,Frontend WDR LUT" hexmask.long.word 0x65C 16.--31. 1. "RESERVED," hexmask.long.word 0x65C 0.--15. 1. "VAL," line.long 0x660 "GLBCE_WDR_GAMMA_LUT_227,Frontend WDR LUT" hexmask.long.word 0x660 16.--31. 1. "RESERVED," hexmask.long.word 0x660 0.--15. 1. "VAL," line.long 0x664 "GLBCE_WDR_GAMMA_LUT_228,Frontend WDR LUT" hexmask.long.word 0x664 16.--31. 1. "RESERVED," hexmask.long.word 0x664 0.--15. 1. "VAL," line.long 0x668 "GLBCE_WDR_GAMMA_LUT_229,Frontend WDR LUT" hexmask.long.word 0x668 16.--31. 1. "RESERVED," hexmask.long.word 0x668 0.--15. 1. "VAL," line.long 0x66C "GLBCE_WDR_GAMMA_LUT_230,Frontend WDR LUT" hexmask.long.word 0x66C 16.--31. 1. "RESERVED," hexmask.long.word 0x66C 0.--15. 1. "VAL," line.long 0x670 "GLBCE_WDR_GAMMA_LUT_231,Frontend WDR LUT" hexmask.long.word 0x670 16.--31. 1. "RESERVED," hexmask.long.word 0x670 0.--15. 1. "VAL," line.long 0x674 "GLBCE_WDR_GAMMA_LUT_232,Frontend WDR LUT" hexmask.long.word 0x674 16.--31. 1. "RESERVED," hexmask.long.word 0x674 0.--15. 1. "VAL," line.long 0x678 "GLBCE_WDR_GAMMA_LUT_233,Frontend WDR LUT" hexmask.long.word 0x678 16.--31. 1. "RESERVED," hexmask.long.word 0x678 0.--15. 1. "VAL," line.long 0x67C "GLBCE_WDR_GAMMA_LUT_234,Frontend WDR LUT" hexmask.long.word 0x67C 16.--31. 1. "RESERVED," hexmask.long.word 0x67C 0.--15. 1. "VAL," line.long 0x680 "GLBCE_WDR_GAMMA_LUT_235,Frontend WDR LUT" hexmask.long.word 0x680 16.--31. 1. "RESERVED," hexmask.long.word 0x680 0.--15. 1. "VAL," line.long 0x684 "GLBCE_WDR_GAMMA_LUT_236,Frontend WDR LUT" hexmask.long.word 0x684 16.--31. 1. "RESERVED," hexmask.long.word 0x684 0.--15. 1. "VAL," line.long 0x688 "GLBCE_WDR_GAMMA_LUT_237,Frontend WDR LUT" hexmask.long.word 0x688 16.--31. 1. "RESERVED," hexmask.long.word 0x688 0.--15. 1. "VAL," line.long 0x68C "GLBCE_WDR_GAMMA_LUT_238,Frontend WDR LUT" hexmask.long.word 0x68C 16.--31. 1. "RESERVED," hexmask.long.word 0x68C 0.--15. 1. "VAL," line.long 0x690 "GLBCE_WDR_GAMMA_LUT_239,Frontend WDR LUT" hexmask.long.word 0x690 16.--31. 1. "RESERVED," hexmask.long.word 0x690 0.--15. 1. "VAL," line.long 0x694 "GLBCE_WDR_GAMMA_LUT_240,Frontend WDR LUT" hexmask.long.word 0x694 16.--31. 1. "RESERVED," hexmask.long.word 0x694 0.--15. 1. "VAL," line.long 0x698 "GLBCE_WDR_GAMMA_LUT_241,Frontend WDR LUT" hexmask.long.word 0x698 16.--31. 1. "RESERVED," hexmask.long.word 0x698 0.--15. 1. "VAL," line.long 0x69C "GLBCE_WDR_GAMMA_LUT_242,Frontend WDR LUT" hexmask.long.word 0x69C 16.--31. 1. "RESERVED," hexmask.long.word 0x69C 0.--15. 1. "VAL," line.long 0x6A0 "GLBCE_WDR_GAMMA_LUT_243,Frontend WDR LUT" hexmask.long.word 0x6A0 16.--31. 1. "RESERVED," hexmask.long.word 0x6A0 0.--15. 1. "VAL," line.long 0x6A4 "GLBCE_WDR_GAMMA_LUT_244,Frontend WDR LUT" hexmask.long.word 0x6A4 16.--31. 1. "RESERVED," hexmask.long.word 0x6A4 0.--15. 1. "VAL," line.long 0x6A8 "GLBCE_WDR_GAMMA_LUT_245,Frontend WDR LUT" hexmask.long.word 0x6A8 16.--31. 1. "RESERVED," hexmask.long.word 0x6A8 0.--15. 1. "VAL," line.long 0x6AC "GLBCE_WDR_GAMMA_LUT_246,Frontend WDR LUT" hexmask.long.word 0x6AC 16.--31. 1. "RESERVED," hexmask.long.word 0x6AC 0.--15. 1. "VAL," line.long 0x6B0 "GLBCE_WDR_GAMMA_LUT_247,Frontend WDR LUT" hexmask.long.word 0x6B0 16.--31. 1. "RESERVED," hexmask.long.word 0x6B0 0.--15. 1. "VAL," line.long 0x6B4 "GLBCE_WDR_GAMMA_LUT_248,Frontend WDR LUT" hexmask.long.word 0x6B4 16.--31. 1. "RESERVED," hexmask.long.word 0x6B4 0.--15. 1. "VAL," line.long 0x6B8 "GLBCE_WDR_GAMMA_LUT_249,Frontend WDR LUT" hexmask.long.word 0x6B8 16.--31. 1. "RESERVED," hexmask.long.word 0x6B8 0.--15. 1. "VAL," line.long 0x6BC "GLBCE_WDR_GAMMA_LUT_250,Frontend WDR LUT" hexmask.long.word 0x6BC 16.--31. 1. "RESERVED," hexmask.long.word 0x6BC 0.--15. 1. "VAL," line.long 0x6C0 "GLBCE_WDR_GAMMA_LUT_251,Frontend WDR LUT" hexmask.long.word 0x6C0 16.--31. 1. "RESERVED," hexmask.long.word 0x6C0 0.--15. 1. "VAL," line.long 0x6C4 "GLBCE_WDR_GAMMA_LUT_252,Frontend WDR LUT" hexmask.long.word 0x6C4 16.--31. 1. "RESERVED," hexmask.long.word 0x6C4 0.--15. 1. "VAL," line.long 0x6C8 "GLBCE_WDR_GAMMA_LUT_253,Frontend WDR LUT" hexmask.long.word 0x6C8 16.--31. 1. "RESERVED," hexmask.long.word 0x6C8 0.--15. 1. "VAL," line.long 0x6CC "GLBCE_WDR_GAMMA_LUT_254,Frontend WDR LUT" hexmask.long.word 0x6CC 16.--31. 1. "RESERVED," hexmask.long.word 0x6CC 0.--15. 1. "VAL," line.long 0x6D0 "GLBCE_WDR_GAMMA_LUT_255,Frontend WDR LUT" hexmask.long.word 0x6D0 16.--31. 1. "RESERVED," hexmask.long.word 0x6D0 0.--15. 1. "VAL," line.long 0x6D4 "GLBCE_WDR_GAMMA_LUT_256,Frontend WDR LUT" hexmask.long.word 0x6D4 16.--31. 1. "RESERVED," hexmask.long.word 0x6D4 0.--15. 1. "VAL," line.long 0x6D8 "GLBCE_TILE_OUT_POS,Tile processing signals [TBD]" hexmask.long.word 0x6D8 16.--31. 1. "TOP," hexmask.long.word 0x6D8 0.--15. 1. "LEFT," group.long 0x6E0++0x03 line.long 0x00 "GLBCE_TILE_OUT_SIZE,Tile processing signals [TBD]" hexmask.long.word 0x00 16.--31. 1. "HEIGHT," hexmask.long.word 0x00 0.--15. 1. "WIDTH," group.long 0x6E8++0x07 line.long 0x00 "GLBCE_TILE_CONTROL,TBD" hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED," hexmask.long.word 0x00 5.--14. 1. "RESERVED," newline bitfld.long 0x00 4. "LAST,Last time" "0,1" bitfld.long 0x00 3. "COLLECTION_DISABLE,Statistics collection disable" "0,1" newline bitfld.long 0x00 2. "UPDATE_DSABLE,Statistics update disable" "0,1" rbitfld.long 0x00 1. "RESERVED," "0,1" newline bitfld.long 0x00 0. "ENABLE,Tile processing Enable" "0,1" line.long 0x04 "GLBCE_OUTPUT_FLAGS,TBD" hexmask.long.word 0x04 16.--31. 1. "RESERVED," hexmask.long.word 0x04 0.--15. 1. "TILE_STATUS,Tile Status" width 0x0B tree.end tree "ISP6P5_H3A" base ad:0x52041400 rgroup.long 0x00++0x7F line.long 0x00 "H3A_PID,Peripheral Revision and Class Information" line.long 0x04 "H3A_PCR,Peripheral Control Register" hexmask.long.word 0x04 22.--31. 1. "AVE2LMT,AE/AWB Saturation Limit This is the value that all sub sampled pixels in the AE/AWB engine are compared to" bitfld.long 0x04 21. "OVF,H3A module overflow status bit" "OVF_0,OVF_1" bitfld.long 0x04 20. "AF_VF_EN,AF Vertical Focus Enable" "AF_VF_EN_0,AF_VF_EN_1" bitfld.long 0x04 19. "AEW_MED_EN,AE/AWB Median filter Enable If the median filter is enabled then the 1st 2 and last 2 pixels in the frame are not filtered" "AEW_MED_EN_0,AEW_MED_EN_1" newline rbitfld.long 0x04 18. "BUSYAEAWB,Busy bit for AE/AWB" "0,1" bitfld.long 0x04 17. "AEW_ALAW_EN,AE/AWB A-law Enable" "AEW_ALAW_EN_0,AEW_ALAW_EN_1" bitfld.long 0x04 16. "AEW_EN,AE/AWB enable" "AEW_EN_0,AEW_EN_1" rbitfld.long 0x04 15. "BUSYAF,Busy bit for AF" "0,1" newline bitfld.long 0x04 14. "FVMODE,Focus Value Accumulation Mode" "FVMODE_0,FVMODE_1" bitfld.long 0x04 11.--13. "RGBPOS,Red Green and blue pixel location in the AF windows RGBPOS(0): GR and GB as Bayer pattern RGBPOS(1): RG and GB as Bayer pattern RGBPOS(2): GR and BG as Bayer pattern RGBPOS(3): RG and BG as Bayer pattern RGBPOS(4): GG and RB as custom pattern.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 3.--10. 1. "MED_TH,Median filter threshold" bitfld.long 0x04 2. "AF_MED_EN,Auto Focus Median filter Enable If the median filter is enabled then the 1st 2 and last 2 pixels in the frame are not in the valid region" "AF_MED_EN_0,AF_MED_EN_1" newline bitfld.long 0x04 1. "AF_ALAW_EN,AF A-law table enable" "AF_ALAW_EN_0,AF_ALAW_EN_1" bitfld.long 0x04 0. "AF_EN,AF enable" "AF_EN_0,AF_EN_1" line.long 0x08 "H3A_AFPAX1,Setup for the AF Engine Paxel Configuration" hexmask.long.byte 0x08 24.--31. 1. "RESERVED," hexmask.long.byte 0x08 16.--23. 1. "PAXW,AF Engine Paxel Width The width of the paxel is the value of this register plus 1 multiplied by 2" hexmask.long.byte 0x08 8.--15. 1. "RESERVED," hexmask.long.byte 0x08 0.--7. 1. "PAXH,AF Engine Paxel Height The height of the paxel is the value of this register plus 1 multiplied by 2 with a final value of 2-256 (even) * This value is shadowed and latched on the rising edge of VSYNC" line.long 0x0C "H3A_AFPAX2,Setup for the AF Engine Paxel Configuration" hexmask.long.word 0x0C 21.--31. 1. "RESERVED," bitfld.long 0x0C 17.--20. "AFINCH,AF Engine Column Increments Number of columns to increment in a paxel plus 1 multiplied by 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 13.--16. "AFINCV,AF Engine Line Increments Number of lines to increment in a Paxel plus 1 multiplied by 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0C 6.--12. 1. "PAXVC,AF Engine Vertical Paxel Count The number of paxels in the vertical direction plus 1" newline bitfld.long 0x0C 0.--5. "PAXHC,AF Engine Horizontal Paxel Count The number of paxels in the horizontal direction plus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "H3A_AFPAXSTART,Start Position for AF Engine Paxels" rbitfld.long 0x10 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x10 16.--27. 1. "PAXSH,AF Engine Paxel Horizontal start position Range: 2-4094 PAXSH must be equal to or greater than (IIRSH + 2) This value must be even if Vertical mode is not enabled" rbitfld.long 0x10 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x10 0.--11. 1. "PAXSV,AF Engine Paxel Vertical start position Range: 0-4095 Sets the vertical line for the first paxel" line.long 0x14 "H3A_AFIIRSH,Start Position for IIRSH" hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED," hexmask.long.word 0x14 0.--11. 1. "IIRSH,AF Engine IIR Horizontal Start Position Range from 0-4094" line.long 0x18 "H3A_AFBUFST,SDRAM destination address for AF engine statistics" hexmask.long 0x18 5.--31. 1. "AFBUFST,SDRAM destination address for AF engine statistics The SDRAM destination address for the AF statistics" rbitfld.long 0x18 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "H3A_AFCOEF010,IIR filter coefficient data for SET 0" rbitfld.long 0x1C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 16.--27. 1. "COEFF1,AF Engine IIR filter Coefficient #1 (Set 0) The range is signed" rbitfld.long 0x1C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 0.--11. 1. "COEFF0,AF Engine IIR filter Coefficient #0 (Set 0) The range is signed" line.long 0x20 "H3A_AFCOEF032,IIR filter coefficient data for SET 0" rbitfld.long 0x20 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x20 16.--27. 1. "COEFF3,AF Engine IIR filter Coefficient #3 (Set 0) The range is signed" rbitfld.long 0x20 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x20 0.--11. 1. "COEFF2,AF Engine IIR filter Coefficient #2 (Set 0) The range is signed" line.long 0x24 "H3A_AFCOEF054,IIR filter coefficient data for SET 0" rbitfld.long 0x24 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x24 16.--27. 1. "COEFF5,AF Engine IIR filter Coefficient #5 (Set 0) The range is signed" rbitfld.long 0x24 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x24 0.--11. 1. "COEFF4,AF Engine IIR filter Coefficient #4 (Set 0) The range is signed" line.long 0x28 "H3A_AFCOEF076,IIR filter coefficient data for SET 0" rbitfld.long 0x28 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x28 16.--27. 1. "COEFF7,AF Engine IIR filter Coefficient #7 (Set 0) The range is signed" rbitfld.long 0x28 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x28 0.--11. 1. "COEFF6,AF Engine IIR filter Coefficient #6 (Set 0) The range is signed" line.long 0x2C "H3A_AFCOEF098,IIR filter coefficient data for SET 0" rbitfld.long 0x2C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x2C 16.--27. 1. "COEFF9,AF Engine IIR filter Coefficient #9 (Set 0) The range is signed" rbitfld.long 0x2C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x2C 0.--11. 1. "COEFF8,AF Engine IIR filter Coefficient #8 (Set 0) The range is signed" line.long 0x30 "H3A_AFCOEF0010,IIR filter coefficient data for SET 0" hexmask.long.tbyte 0x30 12.--31. 1. "RESERVED," hexmask.long.word 0x30 0.--11. 1. "COEFF10,AF Engine IIR filter Coefficient #10 (Set 0) The range is signed" line.long 0x34 "H3A_AFCOEF110,IIR filter coefficient data for SET 1" rbitfld.long 0x34 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x34 16.--27. 1. "COEFF1,AF Engine IIR filter Coefficient #1 (Set 1) The range is signed" rbitfld.long 0x34 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x34 0.--11. 1. "COEFF0,AF Engine IIR filter Coefficient #0 (Set 1) The range is signed" line.long 0x38 "H3A_AFCOEF132,IIR filter coefficient data for SET 1" rbitfld.long 0x38 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x38 16.--27. 1. "COEFF3,AF Engine IIR filter Coefficient #3 (Set 1) The range is signed" rbitfld.long 0x38 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x38 0.--11. 1. "COEFF2,AF Engine IIR filter Coefficient #2 (Set 1) The range is signed" line.long 0x3C "H3A_AFCOEF154,IIR filter coefficient data for SET 1" rbitfld.long 0x3C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x3C 16.--27. 1. "COEFF5,AF Engine IIR filter Coefficient #5 (Set 1) The range is signed" rbitfld.long 0x3C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x3C 0.--11. 1. "COEFF4,AF Engine IIR filter Coefficient #4 (Set 1) The range is signed" line.long 0x40 "H3A_AFCOEF176,IIR filter coefficient data for SET 1" rbitfld.long 0x40 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x40 16.--27. 1. "COEFF7,AF Engine IIR filter Coefficient #7 (Set 1) The range is signed" rbitfld.long 0x40 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x40 0.--11. 1. "COEFF6,AF Engine IIR filter Coefficient #6 (Set 1) The range is signed" line.long 0x44 "H3A_AFCOEF198,IIR filter coefficient data for SET 1" rbitfld.long 0x44 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x44 16.--27. 1. "COEFF9,AF Engine IIR filter Coefficient #9 (Set 1) The range is signed" rbitfld.long 0x44 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x44 0.--11. 1. "COEFF8,AF Engine IIR filter Coefficient #8 (Set 1) The range is signed" line.long 0x48 "H3A_AFCOEF1010,IIR filter coefficient data for SET 1" hexmask.long.tbyte 0x48 12.--31. 1. "RESERVED," hexmask.long.word 0x48 0.--11. 1. "COEFF10,AF Engine IIR filter Coefficient #10 (Set 1) The range is signed" line.long 0x4C "H3A_AEWWIN1,Configuration for AE/AWB Windows" hexmask.long.byte 0x4C 24.--31. 1. "WINH,AE/AWB Engine Window Height This specifies the window height in an even number of pixels the window height is the value plus 1 multiplied by 2" rbitfld.long 0x4C 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4C 13.--20. 1. "WINW,AE/AWB Engine Window Width This specifies the window width in an even number of pixels the window width is the value plus 1 multiplied by 2" hexmask.long.byte 0x4C 6.--12. 1. "WINVC,AE/AWB Engine Vertical Window Count The number of windows in the vertical direction plus 1" newline bitfld.long 0x4C 0.--5. "WINHC,AE/AWB Engine Horizontal Window Count The number of horizontal windows plus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x50 "H3A_AEWINSTART,Start position for AE/AWB Windows" rbitfld.long 0x50 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x50 16.--27. 1. "WINSV,AE/AWB Engine Vertical Window Start Position Sets the first line for the first window" rbitfld.long 0x50 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x50 0.--11. 1. "WINSH,AE/AWB Engine Horizontal Window Start Position Sets the horizontal position for the first window on each line" line.long 0x54 "H3A_AEWINBLK,Start position and height for black line of AE/AWB Windows" rbitfld.long 0x54 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x54 16.--27. 1. "WINSV,AE/AWB Engine Vertical Window Start Position for single black line of windows Sets the first line for the single black line of windows" hexmask.long.word 0x54 7.--15. 1. "RESERVED," hexmask.long.byte 0x54 0.--6. 1. "WINH,AE/AWB Engine Window Height for the single black line of windows This specifies the window height in an even number of pixels the window height is the value plus 1 multiplied by 2" line.long 0x58 "H3A_AEWSUBWIN,Configuration for subsample data in AE/AWB window" hexmask.long.tbyte 0x58 12.--31. 1. "RESERVED," bitfld.long 0x58 8.--11. "AEWINCV,AE/AWB Engine Vertical Sampling Point Increment Sets vertical distance between sub-samples within a window plus 1 multiplied by 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x58 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x58 0.--3. "AEWINCH,AE/AWB Engine Horizontal Sampling Point Increment Sets horizontal distance between sub-samples within a window plus 1 multiplied by 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x5C "H3A_AEWBUFST,SDRAM destination address for AE/AWB engine statistics" hexmask.long 0x5C 5.--31. 1. "AEWBUFST,SDRAM destination address for AE/AWB engine statistics The start location in SDRAM for the AE/AWB statistics" rbitfld.long 0x5C 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x60 "H3A_AEWCFG,Configuration for AE/AWB" hexmask.long.tbyte 0x60 10.--31. 1. "RESERVED," bitfld.long 0x60 8.--9. "AEFMT,AE/AWB output format" "sum of squares,min/max,sum only; no sum of squares..,?..." rbitfld.long 0x60 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x60 0.--3. "SUMSHFT,AE/AWB engine shift value for the accumulation of pixel values This bitfield sets the right shift value which is applied on the result of the pixel accumulation before it is stored in the packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x64 "H3A_LINE_START,Line Framing Logic Register In certain cases the number of clock cycles between HD pulses will be greater than the line buffer included in the H3A module" hexmask.long.word 0x64 16.--31. 1. "SLV,Start Line Vertical Specifies how many lines after the VD rising edge the real frame starts" hexmask.long.word 0x64 0.--15. 1. "LINE_START,Line Start The framing module uses the LINE_START bitfield to find the position of the first pixel to place into the line buffer" line.long 0x68 "H3A_VFV_CFG1,Vertical focus value configuration 1" hexmask.long.byte 0x68 24.--31. 1. "VCOEF1_3,Vertical FV FIR 1 coefficient 3" hexmask.long.byte 0x68 16.--23. 1. "VCOEF1_2,Vertical FV FIR 1 coefficient 2" hexmask.long.byte 0x68 8.--15. 1. "VCOEF1_1,Vertical FV FIR 1 coefficient 1" hexmask.long.byte 0x68 0.--7. 1. "VCOEF1_0,Vertical FV FIR 1 coefficient 0" line.long 0x6C "H3A_VFV_CFG2,Vertical focus value configuration 2" hexmask.long.word 0x6C 16.--31. 1. "VTHR1,Threshold for vertical FV FIR 1" hexmask.long.byte 0x6C 8.--15. 1. "RESERVED," hexmask.long.byte 0x6C 0.--7. 1. "VCOEF1_4,Vertical FV FIR 1 coefficient 4" line.long 0x70 "H3A_VFV_CFG3,Vertical focus value configuration 4" hexmask.long.byte 0x70 24.--31. 1. "VCOEF2_3,Vertical FV FIR 2 coefficient 3" hexmask.long.byte 0x70 16.--23. 1. "VCOEF2_2,Vertical FV FIR 2 coefficient 2" hexmask.long.byte 0x70 8.--15. 1. "VCOEF2_1,Vertical FV FIR 2 coefficient 1" hexmask.long.byte 0x70 0.--7. 1. "VCOEF2_0,Vertical FV FIR 2 coefficient 0" line.long 0x74 "H3A_VFV_CFG4,Vertical focus value configuration 4" hexmask.long.word 0x74 16.--31. 1. "VTHR2,Threshold for vertical FV FIR 2" hexmask.long.byte 0x74 8.--15. 1. "RESERVED," hexmask.long.byte 0x74 0.--7. 1. "VCOEF2_4,Vertical FV FIR 2 coefficient 4" line.long 0x78 "H3A_HVF_THR,Horizontal Focus Value Threshold" hexmask.long.word 0x78 16.--31. 1. "HTHR2,Threshold for horizontal FV IIR 2" hexmask.long.word 0x78 0.--15. 1. "HTHR1,Threshold for horizontal FV IIR 1" line.long 0x7C "H3A_ADVANCED," hexmask.long.word 0x7C 16.--31. 1. "ID,Below information should not be in TRM" hexmask.long.word 0x7C 5.--15. 1. "RESERVED," bitfld.long 0x7C 4. "AEW_MODE,This bit should not be included in TRM" "AEW_MODE_0,AEW_MODE_1" rbitfld.long 0x7C 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x7C 0. "AF_MODE,AF engine mode" "AF_MODE_0,AF_MODE_1" width 0x0B tree.end tree "ISP6P5_IPIPE" base ad:0x52040800 group.long 0x00++0x2F line.long 0x00 "IPIPE_SRC_EN,This register is not shadowed" hexmask.long.word 0x00 16.--31. 1. "RESERVED," hexmask.long.word 0x00 1.--15. 1. "RESERVED," bitfld.long 0x00 0. "EN,The start flag of the IPIPE module" "EN_0,EN_1" line.long 0x04 "IPIPE_SRC_MODE," hexmask.long.word 0x04 16.--31. 1. "RESERVED," hexmask.long.word 0x04 2.--15. 1. "RESERVED," bitfld.long 0x04 1. "WRT,The mode selection of the ipipeif_wrt which is an input port of the IPIPE module" "WRT_0,WRT_1" bitfld.long 0x04 0. "OST,The processing mode selection of the IPIPE module" "OST_0,OST_1" line.long 0x08 "IPIPE_SRC_FMT," hexmask.long 0x08 5.--31. 1. "RESERVED," bitfld.long 0x08 4. "FMT3,Chroma sumpling postion in YUV422 to 444 This field is only valide if FMT=3 and FT2=2" "FMT3_0,FMT3_1" bitfld.long 0x08 2.--3. "FMT2,YUV processing mode This field is valid only when FMT=3 (YUV input YUV output)" "FMT2_0,FMT2_1,FMT2_2,FMT2_3" bitfld.long 0x08 0.--1. "FMT,IPIPE module datapath selection" "FMT_0,FMT_1,FMT_2,FMT_3" line.long 0x0C "IPIPE_SRC_COL," hexmask.long.word 0x0C 16.--31. 1. "RESERVED," hexmask.long.byte 0x0C 8.--15. 1. "RESERVED," bitfld.long 0x0C 6.--7. "OO,The color pattern of the odd line and odd pixel" "OO_0,OO_1,OO_2,OO_3" bitfld.long 0x0C 4.--5. "OE,The color pattern of the odd line and even pixel" "OE_0,OE_1,OE_2,OE_3" newline bitfld.long 0x0C 2.--3. "EO,The color pattern of the even line and odd pixel" "EO_0,EO_1,EO_2,EO_3" bitfld.long 0x0C 0.--1. "EE,The color pattern of the even line and even pixel" "EE_0,EE_1,EE_2,EE_3" line.long 0x10 "IPIPE_SRC_VPS," hexmask.long.word 0x10 16.--31. 1. "RESERVED," hexmask.long.word 0x10 0.--15. 1. "VAL,The vertical position of the global frame from the rising edge of the VD" line.long 0x14 "IPIPE_SRC_VSZ," hexmask.long.word 0x14 16.--31. 1. "RESERVED," rbitfld.long 0x14 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 0.--12. 1. "VAL,The vertical size of the processing area" line.long 0x18 "IPIPE_SRC_HPS," hexmask.long.word 0x18 16.--31. 1. "RESERVED," hexmask.long.word 0x18 0.--15. 1. "VAL,The horizontal position of the global frame from the rising edge of the HD" line.long 0x1C "IPIPE_SRC_HSZ," hexmask.long.tbyte 0x1C 13.--31. 1. "RESERVED," hexmask.long.word 0x1C 1.--12. 1. "VAL,The horizontal size of the processing area" rbitfld.long 0x1C 0. "VAL_0,This is the LSB of the VAL[12:0]" "0,1" line.long 0x20 "IPIPE_SEL_SBU," hexmask.long.word 0x20 16.--31. 1. "RESERVED," hexmask.long.word 0x20 1.--15. 1. "RESERVED," bitfld.long 0x20 0. "EDOF,EDOF port selection" "EDOF_0,EDOF_1" line.long 0x24 "IPIPE_SRC_STA,IPIPE STATUS REGISTER" hexmask.long.word 0x24 16.--31. 1. "RESERVED," hexmask.long.word 0x24 5.--15. 1. "RESERVED," bitfld.long 0x24 4. "VAL4,Status of Histogram Process (busy status)" "0,1" bitfld.long 0x24 3. "VAL3,Status of Histogram bank select" "0,1" newline bitfld.long 0x24 2. "VAL2,Status of BSC process (busy status)" "0,1" bitfld.long 0x24 1. "VAL1,Status of Boxcar process (busy status)" "0,1" bitfld.long 0x24 0. "VAL0,Status of Boxcar process (error status)" "0,1" line.long 0x28 "IPIPE_GCK_MMR," hexmask.long.word 0x28 16.--31. 1. "RESERVED," hexmask.long.word 0x28 1.--15. 1. "RESERVED," bitfld.long 0x28 0. "REG,The on/off selection of the clk_arm_g0 which is used for some ARM register access" "REG_0,REG_1" line.long 0x2C "IPIPE_GCK_PIX,This register is not shadowed" hexmask.long.word 0x2C 16.--31. 1. "RESERVED," hexmask.long.word 0x2C 4.--15. 1. "RESERVED," bitfld.long 0x2C 3. "G3,The on/off selection of the clk_pix_g3 which is use for the IPIPE processes of ?EE? and 'CAR'" "G3_0,G3_1" bitfld.long 0x2C 2. "G2,The on/off selection of the clk_pix_g2 which is use for the IPIPE processes of ?CFA? to '422' 'Histogram(YCbCr input)' and 'Boundary Signal Calculator'" "G2_0,G2_1" newline bitfld.long 0x2C 1. "G1,The on/off selection of the clk_pix_g1 which is used for the IPIPE processes of 'DefectCorrection' to 'WhiteBalance' and 'Histogram(RAW input)'" "G1_0,G1_1" bitfld.long 0x2C 0. "G0,The on/off selection of the clk_pix_g0 which is used for the IPIPE processing of 'Boxcar'" "G0_0,G0_1" group.long 0x34++0x5F line.long 0x00 "IPIPE_DPC_LUT_EN," hexmask.long.word 0x00 16.--31. 1. "RESERVED," hexmask.long.word 0x00 1.--15. 1. "RESERVED," bitfld.long 0x00 0. "EN,Enable of LUT defect pixel correction" "EN_0,EN_1" line.long 0x04 "IPIPE_DPC_LUT_SEL," hexmask.long.word 0x04 16.--31. 1. "RESERVED," hexmask.long.word 0x04 2.--15. 1. "RESERVED," bitfld.long 0x04 1. "TBL,LUT table type selection" "TBL_0,TBL_1" bitfld.long 0x04 0. "DOT,Replace dot selection on processing method 0" "DOT_0,DOT_1" line.long 0x08 "IPIPE_DPC_LUT_ADR," hexmask.long.word 0x08 16.--31. 1. "RESERVED," rbitfld.long 0x08 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x08 0.--9. 1. "ADR,The address of the first valid data in look-up-table" line.long 0x0C "IPIPE_DPC_LUT_SIZ," hexmask.long.word 0x0C 16.--31. 1. "RESERVED," rbitfld.long 0x0C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0C 0.--9. 1. "SIZ,The number of valid data in look-up-table" line.long 0x10 "IPIPE_DPC_OTF_EN,Enable of adaptive defect pixel correction module" hexmask.long.word 0x10 16.--31. 1. "RESERVED," hexmask.long.word 0x10 1.--15. 1. "RESERVED," bitfld.long 0x10 0. "EN," "EN_0,EN_1" line.long 0x14 "IPIPE_DPC_OTF_TYP,To select MinMax Algorithm following values are set ALG: 0 TYP: 0 IPIPE_DPC_OTF_2_D_THR_x: 0 IPIPE_DPC_OTF_2_C_THR_x: maximum value" hexmask.long.word 0x14 16.--31. 1. "RESERVED," hexmask.long.word 0x14 2.--15. 1. "RESERVED," bitfld.long 0x14 1. "TYP," "TYP_0,TYP_1" bitfld.long 0x14 0. "ALG," "ALG_0,ALG_1" line.long 0x18 "IPIPE_DPC_OTF_2_D_THR_R,D_THR for R" hexmask.long.word 0x18 16.--31. 1. "RESERVED," rbitfld.long 0x18 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x18 0.--11. 1. "VAL,Defect detection threshold value for each color (DPC2.0)" line.long 0x1C "IPIPE_DPC_OTF_2_D_THR_GR,D_THR for Gr" hexmask.long.word 0x1C 16.--31. 1. "RESERVED," rbitfld.long 0x1C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 0.--11. 1. "VAL,Defect detection threshold value for each color (DPC2.0)" line.long 0x20 "IPIPE_DPC_OTF_2_D_THR_GB,D_THR for Gb" hexmask.long.word 0x20 16.--31. 1. "RESERVED," rbitfld.long 0x20 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x20 0.--11. 1. "VAL,Defect detection threshold value for each color (DPC2.0)" line.long 0x24 "IPIPE_DPC_OTF_2_D_THR_B,D_THR for B" hexmask.long.word 0x24 16.--31. 1. "RESERVED," rbitfld.long 0x24 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x24 0.--11. 1. "VAL,Defect detection threshold value for each color (DPC2.0)" line.long 0x28 "IPIPE_DPC_OTF_2_C_THR_R,C_THR for R" hexmask.long.word 0x28 16.--31. 1. "RESERVED," rbitfld.long 0x28 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x28 0.--11. 1. "VAL,Defect correction threshold value for each color (DPC2.0)" line.long 0x2C "IPIPE_DPC_OTF_2_C_THR_GR,C_THR for Gr" hexmask.long.word 0x2C 16.--31. 1. "RESERVED," rbitfld.long 0x2C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x2C 0.--11. 1. "VAL,Defect correction threshold value for each color (DPC2.0)" line.long 0x30 "IPIPE_DPC_OTF_2_C_THR_GB,C_THR for Gb" hexmask.long.word 0x30 16.--31. 1. "RESERVED," rbitfld.long 0x30 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x30 0.--11. 1. "VAL,Defect correction threshold value for each color (DPC2.0)" line.long 0x34 "IPIPE_DPC_OTF_2_C_THR_B,C_THR for B" hexmask.long.word 0x34 16.--31. 1. "RESERVED," rbitfld.long 0x34 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x34 0.--11. 1. "VAL,Defect correction threshold value for each color (DPC2.0)" line.long 0x38 "IPIPE_DPC_OTF_3_SHF," hexmask.long.word 0x38 16.--31. 1. "RESERVED," hexmask.long.word 0x38 2.--15. 1. "RESERVED," bitfld.long 0x38 0.--1. "SHF," "0,1,2,3" line.long 0x3C "IPIPE_DPC_OTF_3_D_THR," hexmask.long.word 0x3C 16.--31. 1. "RESERVED," rbitfld.long 0x3C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x3C 6.--11. "VAL,DPC3 Defect detection threshold 12-bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x3C 0.--5. "VAL_RESERVED,DPC3 Defect detection threshold 12-bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "IPIPE_DPC_OTF_3_D_SPL," hexmask.long.word 0x40 16.--31. 1. "RESERVED," hexmask.long.word 0x40 6.--15. 1. "RESERVED," bitfld.long 0x40 0.--5. "VAL,Defect detection threshold slope for DPC3.0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x44 "IPIPE_DPC_OTF_3_D_MIN," hexmask.long.word 0x44 16.--31. 1. "RESERVED," rbitfld.long 0x44 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x44 0.--11. 1. "VAL," line.long 0x48 "IPIPE_DPC_OTF_3_D_MAX," hexmask.long.word 0x48 16.--31. 1. "RESERVED," rbitfld.long 0x48 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x48 0.--11. 1. "VAL,Defect detection threshold MAX for DPC3.0" line.long 0x4C "IPIPE_DPC_OTF_3_C_THR," hexmask.long.word 0x4C 16.--31. 1. "RESERVED," rbitfld.long 0x4C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x4C 6.--11. "VAL,Defect correction threshold for DPC3.0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x4C 0.--5. "VAL_RESERVED,Defect correction threshold for DPC3.0 Bits VAL[5-0] cannot be written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x50 "IPIPE_DPC_OTF_3_C_SLP," hexmask.long.word 0x50 16.--31. 1. "RESERVED," rbitfld.long 0x50 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x50 6.--11. "VAL_RESERVED,Defect correction threshold slope for DPC3.0 VAL[11-6] cannot be written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x50 0.--5. "VAL,Defect correction threshold slope for DPC3.0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x54 "IPIPE_DPC_OTF_3_C_MIN," hexmask.long.word 0x54 16.--31. 1. "RESERVED," rbitfld.long 0x54 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x54 0.--11. 1. "VAL,Defect correction threshold MIN for DPC3.0" line.long 0x58 "IPIPE_DPC_OTF_3_C_MAX," hexmask.long.word 0x58 16.--31. 1. "RESERVED," rbitfld.long 0x58 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x58 0.--11. 1. "VAL,Defect correction threshold MAX for DPC3.0" line.long 0x5C "IPIPE_LSC_VOFT,LSC VOFT" hexmask.long.word 0x5C 16.--31. 1. "RESERVED," rbitfld.long 0x5C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x5C 0.--12. 1. "LSC_VOFT," group.long 0x9C++0x07 line.long 0x00 "IPIPE_LSC_VS," hexmask.long.word 0x00 16.--31. 1. "RESERVED," hexmask.long.byte 0x00 8.--15. 1. "RESERVED," bitfld.long 0x00 4.--7. "VS2,LSC VS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "VS1,LSC VS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "IPIPE_LSC_HOFT," hexmask.long.word 0x04 16.--31. 1. "RESERVED," rbitfld.long 0x04 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 0.--12. 1. "VAL,LSC HOFT" group.long 0xAC++0xA3 line.long 0x00 "IPIPE_LSC_HS," hexmask.long.word 0x00 16.--31. 1. "RESERVED," hexmask.long.byte 0x00 8.--15. 1. "RESERVED," bitfld.long 0x00 4.--7. "HS2,LSC HS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "HS1,LSC HS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "IPIPE_LSC_GAN_R," hexmask.long.word 0x04 16.--31. 1. "RESERVED," hexmask.long.byte 0x04 8.--15. 1. "RESERVED," hexmask.long.byte 0x04 0.--7. 1. "VAL,GAN R" line.long 0x08 "IPIPE_LSC_GAN_GR," hexmask.long.word 0x08 16.--31. 1. "RESERVED," hexmask.long.byte 0x08 8.--15. 1. "RESERVED," hexmask.long.byte 0x08 0.--7. 1. "VAL,GAN GR" line.long 0x0C "IPIPE_LSC_GAN_GB," hexmask.long.word 0x0C 16.--31. 1. "RESERVED," hexmask.long.byte 0x0C 8.--15. 1. "RESERVED," hexmask.long.byte 0x0C 0.--7. 1. "VAL,GAN GB" line.long 0x10 "IPIPE_LSC_GAN_B," hexmask.long.word 0x10 16.--31. 1. "RESERVED," hexmask.long.byte 0x10 8.--15. 1. "RESERVED," hexmask.long.byte 0x10 0.--7. 1. "VAL,GAN B" line.long 0x14 "IPIPE_LSC_OFT_R," hexmask.long.word 0x14 16.--31. 1. "RESERVED," hexmask.long.byte 0x14 8.--15. 1. "RESERVED," hexmask.long.byte 0x14 0.--7. 1. "VAL,LSC OFT R" line.long 0x18 "IPIPE_LSC_OFT_GR," hexmask.long.word 0x18 16.--31. 1. "RESERVED," hexmask.long.byte 0x18 8.--15. 1. "RESERVED," hexmask.long.byte 0x18 0.--7. 1. "VAL,LSC OFT GR" line.long 0x1C "IPIPE_LSC_OFT_GB," hexmask.long.word 0x1C 16.--31. 1. "RESERVED," hexmask.long.byte 0x1C 8.--15. 1. "RESERVED," hexmask.long.byte 0x1C 0.--7. 1. "VAL,LSC OFT GB" line.long 0x20 "IPIPE_LSC_OFT_B," hexmask.long.word 0x20 16.--31. 1. "RESERVED," hexmask.long.byte 0x20 8.--15. 1. "RESERVED," hexmask.long.byte 0x20 0.--7. 1. "VAL,LSC OFT B" line.long 0x24 "IPIPE_LSC_SHF," hexmask.long.word 0x24 16.--31. 1. "RESERVED," hexmask.long.word 0x24 4.--15. 1. "RESERVED," bitfld.long 0x24 0.--3. "VAL,LSC SHV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x28 "IPIPE_LSC_MAX," hexmask.long.word 0x28 16.--31. 1. "RESERVED," hexmask.long.byte 0x28 9.--15. 1. "RESERVED," hexmask.long.word 0x28 0.--8. 1. "VAL,LSC MAX" line.long 0x2C "IPIPE_D2F_1ST_EN,Noise Filter 1 Register" hexmask.long.word 0x2C 16.--31. 1. "RESERVED," hexmask.long.word 0x2C 1.--15. 1. "RESERVED," bitfld.long 0x2C 0. "EN,Enable of noise filter-1 module" "EN_0,EN_1" line.long 0x30 "IPIPE_D2F_1ST_TYP,Noise Filter 1 Register" hexmask.long.word 0x30 16.--31. 1. "RESERVED," rbitfld.long 0x30 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 9. "SEL,Select SPR value source" "SEL_0,SEL_1" bitfld.long 0x30 8. "LSC,Apply LSC gain to threshold values" "LSC_0,LSC_1" newline bitfld.long 0x30 7. "TYP,The sampling method of green pixels" "TYP_0,TYP_1" bitfld.long 0x30 5.--6. "SHF,The d value (down shift value) in look-up-table reference address" "0,1,2,3" bitfld.long 0x30 0.--4. "SPR,The SP value ('spread' value) in noise filter-1 algorithm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "IPIPE_D2F_1ST_THR_00,Noise Filter 1 Register" hexmask.long.word 0x34 16.--31. 1. "RESERVED," rbitfld.long 0x34 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x34 0.--9. 1. "VAL,Threshold values in noise filter-1 algorithm" line.long 0x38 "IPIPE_D2F_1ST_THR_01,Noise Filter 1 Register" hexmask.long.word 0x38 16.--31. 1. "RESERVED," rbitfld.long 0x38 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x38 0.--9. 1. "VAL,Threshold values in noise filter-1 algorithm" line.long 0x3C "IPIPE_D2F_1ST_THR_02,Noise Filter 1 Register" hexmask.long.word 0x3C 16.--31. 1. "RESERVED," rbitfld.long 0x3C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x3C 0.--9. 1. "VAL,Threshold values in noise filter-1 algorithm" line.long 0x40 "IPIPE_D2F_1ST_THR_03,Noise Filter 1 Register" hexmask.long.word 0x40 16.--31. 1. "RESERVED," rbitfld.long 0x40 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x40 0.--9. 1. "VAL,Threshold values in noise filter-1 algorithm" line.long 0x44 "IPIPE_D2F_1ST_THR_04,Noise Filter 1 Register" hexmask.long.word 0x44 16.--31. 1. "RESERVED," rbitfld.long 0x44 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x44 0.--9. 1. "VAL,Threshold values in noise filter-1 algorithm" line.long 0x48 "IPIPE_D2F_1ST_THR_05,Noise Filter 1 Register" hexmask.long.word 0x48 16.--31. 1. "RESERVED," rbitfld.long 0x48 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x48 0.--9. 1. "VAL,Threshold values in noise filter-1 algorithm" line.long 0x4C "IPIPE_D2F_1ST_THR_06,Noise Filter 1 Register" hexmask.long.word 0x4C 16.--31. 1. "RESERVED," rbitfld.long 0x4C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x4C 0.--9. 1. "VAL,Threshold values in noise filter-1 algorithm" line.long 0x50 "IPIPE_D2F_1ST_THR_07,Noise Filter 1 Register" hexmask.long.word 0x50 16.--31. 1. "RESERVED," rbitfld.long 0x50 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x50 0.--9. 1. "VAL,Threshold values in noise filter-1 algorithm" line.long 0x54 "IPIPE_D2F_1ST_STR_00,Noise Filter 1 Register" hexmask.long.word 0x54 16.--31. 1. "RESERVED," hexmask.long.word 0x54 5.--15. 1. "RESERVED," bitfld.long 0x54 0.--4. "VAL,Noise filter-1 intensity values (STR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x58 "IPIPE_D2F_1ST_STR_01,Noise Filter 1 Register" hexmask.long.word 0x58 16.--31. 1. "RESERVED," hexmask.long.word 0x58 5.--15. 1. "RESERVED," bitfld.long 0x58 0.--4. "VAL,Noise filter-1 intensity values (STR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x5C "IPIPE_D2F_1ST_STR_02,Noise Filter 1 Register" hexmask.long.word 0x5C 16.--31. 1. "RESERVED," hexmask.long.word 0x5C 5.--15. 1. "RESERVED," bitfld.long 0x5C 0.--4. "VAL,Noise filter-1 intensity values (STR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x60 "IPIPE_D2F_1ST_STR_03,Noise Filter 1 Register" hexmask.long.word 0x60 16.--31. 1. "RESERVED," hexmask.long.word 0x60 5.--15. 1. "RESERVED," bitfld.long 0x60 0.--4. "VAL,Noise filter-1 intensity values (STR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x64 "IPIPE_D2F_1ST_STR_04,Noise Filter 1 Register" hexmask.long.word 0x64 16.--31. 1. "RESERVED," hexmask.long.word 0x64 5.--15. 1. "RESERVED," bitfld.long 0x64 0.--4. "VAL,Noise filter-1 intensity values (STR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x68 "IPIPE_D2F_1ST_STR_05,Noise Filter 1 Register" hexmask.long.word 0x68 16.--31. 1. "RESERVED," hexmask.long.word 0x68 5.--15. 1. "RESERVED," bitfld.long 0x68 0.--4. "VAL,Noise filter-1 intensity values (STR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x6C "IPIPE_D2F_1ST_STR_06,Noise Filter 1 Register" hexmask.long.word 0x6C 16.--31. 1. "RESERVED," hexmask.long.word 0x6C 5.--15. 1. "RESERVED," bitfld.long 0x6C 0.--4. "VAL,Noise filter-1 intensity values (STR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x70 "IPIPE_D2F_1ST_STR_07,Noise Filter 1 Register" hexmask.long.word 0x70 16.--31. 1. "RESERVED," hexmask.long.word 0x70 5.--15. 1. "RESERVED," bitfld.long 0x70 0.--4. "VAL,Noise filter-1 intensity values (STR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x74 "IPIPE_D2F_1ST_SPR_00,Noise Filter 1 Register" hexmask.long.word 0x74 16.--31. 1. "RESERVED," hexmask.long.word 0x74 5.--15. 1. "RESERVED," bitfld.long 0x74 0.--4. "VAL,Noise filter-1 intensity values (SP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x78 "IPIPE_D2F_1ST_SPR_01,Noise Filter 1 Register" hexmask.long.word 0x78 16.--31. 1. "RESERVED," hexmask.long.word 0x78 5.--15. 1. "RESERVED," bitfld.long 0x78 0.--4. "VAL,Noise filter-1 intensity values (SP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x7C "IPIPE_D2F_1ST_SPR_02,Noise Filter 1 Register" hexmask.long.word 0x7C 16.--31. 1. "RESERVED," hexmask.long.word 0x7C 5.--15. 1. "RESERVED," bitfld.long 0x7C 0.--4. "VAL,Noise filter-1 intensity values (SP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x80 "IPIPE_D2F_1ST_SPR_03,Noise Filter 1 Register" hexmask.long.word 0x80 16.--31. 1. "RESERVED," hexmask.long.word 0x80 5.--15. 1. "RESERVED," bitfld.long 0x80 0.--4. "VAL,Noise filter-1 intensity values (SP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x84 "IPIPE_D2F_1ST_SPR_04,Noise Filter 1 Register" hexmask.long.word 0x84 16.--31. 1. "RESERVED," hexmask.long.word 0x84 5.--15. 1. "RESERVED," bitfld.long 0x84 0.--4. "VAL,Noise filter-1 intensity values (SP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x88 "IPIPE_D2F_1ST_SPR_05,Noise Filter 1 Register" hexmask.long.word 0x88 16.--31. 1. "RESERVED," hexmask.long.word 0x88 5.--15. 1. "RESERVED," bitfld.long 0x88 0.--4. "VAL,Noise filter-1 intensity values (SP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x8C "IPIPE_D2F_1ST_SPR_06,Noise Filter 1 Register" hexmask.long.word 0x8C 16.--31. 1. "RESERVED," hexmask.long.word 0x8C 5.--15. 1. "RESERVED," bitfld.long 0x8C 0.--4. "VAL,Noise filter-1 intensity values (SP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x90 "IPIPE_D2F_1ST_SPR_07,Noise Filter 1 Register" hexmask.long.word 0x90 16.--31. 1. "RESERVED," hexmask.long.word 0x90 5.--15. 1. "RESERVED," bitfld.long 0x90 0.--4. "VAL,Noise filter-1 intensity values (SP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x94 "IPIPE_D2F_1ST_EDG_MIN,Noise Filter 1 Register" hexmask.long.word 0x94 16.--31. 1. "RESERVED," rbitfld.long 0x94 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x94 0.--10. 1. "VAL,Noise filter-1 edge detection MIN" line.long 0x98 "IPIPE_D2F_1ST_EDG_MAX,Noise Filter 1 Register" hexmask.long.word 0x98 16.--31. 1. "RESERVED," rbitfld.long 0x98 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x98 0.--10. 1. "VAL,Noise filter-1 edge detection MAX" line.long 0x9C "IPIPE_D2F_2ND_EN,Noise Filter 2 Register" hexmask.long.word 0x9C 16.--31. 1. "RESERVED," hexmask.long.word 0x9C 1.--15. 1. "RESERVED," bitfld.long 0x9C 0. "EN,Enable of noise filter-2 module" "EN_0,EN_1" line.long 0xA0 "IPIPE_D2F_2ND_TYP,Noise Filter 2 Register" hexmask.long.word 0xA0 16.--31. 1. "RESERVED," rbitfld.long 0xA0 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA0 9. "SEL,Select SPR value source" "SEL_0,SEL_1" bitfld.long 0xA0 8. "LSC,Apply LSC gain to threshold values" "LSC_0,LSC_1" newline bitfld.long 0xA0 7. "TYP,The sampling method of green pixels" "TYP_0,TYP_1" bitfld.long 0xA0 5.--6. "SHF,The d value (down shift value) in look-up-table reference address" "0,1,2,3" bitfld.long 0xA0 0.--4. "SPR,The SP value ('spread' value) in noise filter-2 algorithm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x170++0x227 line.long 0x00 "IPIPE_D2F_2ND_STR_00,Noise Filter 2 Register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," hexmask.long.word 0x00 5.--15. 1. "RESERVED," bitfld.long 0x00 0.--4. "VAL,Noise filter-2 intensity values (STR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IPIPE_D2F_2ND_STR_01,Noise Filter 2 Register" hexmask.long.word 0x04 16.--31. 1. "RESERVED," hexmask.long.word 0x04 5.--15. 1. "RESERVED," bitfld.long 0x04 0.--4. "VAL,Noise filter-2 intensity values (STR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "IPIPE_D2F_2ND_STR_02,Noise Filter 2 Register" hexmask.long.word 0x08 16.--31. 1. "RESERVED," hexmask.long.word 0x08 5.--15. 1. "RESERVED," bitfld.long 0x08 0.--4. "VAL,Noise filter-2 intensity values (STR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "IPIPE_D2F_2ND_STR_03,Noise Filter 2 Register" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," hexmask.long.word 0x0C 5.--15. 1. "RESERVED," bitfld.long 0x0C 0.--4. "VAL,Noise filter-2 intensity values (STR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "IPIPE_D2F_2ND_STR_04,Noise Filter 2 Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED," hexmask.long.word 0x10 5.--15. 1. "RESERVED," bitfld.long 0x10 0.--4. "VAL,Noise filter-2 intensity values (STR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "IPIPE_D2F_2ND_STR_05,Noise Filter 2 Register" hexmask.long.word 0x14 16.--31. 1. "RESERVED," hexmask.long.word 0x14 5.--15. 1. "RESERVED," bitfld.long 0x14 0.--4. "VAL,Noise filter-2 intensity values (STR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "IPIPE_D2F_2ND_STR_06,Noise Filter 2 Register" hexmask.long.word 0x18 16.--31. 1. "RESERVED," hexmask.long.word 0x18 5.--15. 1. "RESERVED," bitfld.long 0x18 0.--4. "VAL,Noise filter-2 intensity values (STR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "IPIPE_D2F_2ND_STR_07,Noise Filter 2 Register" hexmask.long.word 0x1C 16.--31. 1. "RESERVED," hexmask.long.word 0x1C 5.--15. 1. "RESERVED," bitfld.long 0x1C 0.--4. "VAL,Noise filter-2 intensity values (STR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "IPIPE_D2F_2ND_SPR_00,Noise Filter 2 Register" hexmask.long.word 0x20 16.--31. 1. "RESERVED," hexmask.long.word 0x20 5.--15. 1. "RESERVED," bitfld.long 0x20 0.--4. "VAL,Noise filter-2 intensity values (SP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "IPIPE_D2F_2ND_SPR_01,Noise Filter 2 Register" hexmask.long.word 0x24 16.--31. 1. "RESERVED," hexmask.long.word 0x24 5.--15. 1. "RESERVED," bitfld.long 0x24 0.--4. "VAL,Noise filter-2 intensity values (SP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "IPIPE_D2F_2ND_SPR_02,Noise Filter 2 Register" hexmask.long.word 0x28 16.--31. 1. "RESERVED," hexmask.long.word 0x28 5.--15. 1. "RESERVED," bitfld.long 0x28 0.--4. "VAL,Noise filter-2 intensity values (SP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x2C "IPIPE_D2F_2ND_SPR_03,Noise Filter 2 Register" hexmask.long.word 0x2C 16.--31. 1. "RESERVED," hexmask.long.word 0x2C 5.--15. 1. "RESERVED," bitfld.long 0x2C 0.--4. "VAL,Noise filter-2 intensity values (SP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "IPIPE_D2F_2ND_SPR_04,Noise Filter 2 Register" hexmask.long.word 0x30 16.--31. 1. "RESERVED," hexmask.long.word 0x30 5.--15. 1. "RESERVED," bitfld.long 0x30 0.--4. "VAL,Noise filter-2 intensity values (SP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "IPIPE_D2F_2ND_SPR_05,Noise Filter 2 Register" hexmask.long.word 0x34 16.--31. 1. "RESERVED," hexmask.long.word 0x34 5.--15. 1. "RESERVED," bitfld.long 0x34 0.--4. "VAL,Noise filter-2 intensity values (SP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x38 "IPIPE_D2F_2ND_SPR_06,Noise Filter 2 Register" hexmask.long.word 0x38 16.--31. 1. "RESERVED," hexmask.long.word 0x38 5.--15. 1. "RESERVED," bitfld.long 0x38 0.--4. "VAL,Noise filter-2 intensity values (SP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x3C "IPIPE_D2F_2ND_SPR_07,Noise Filter 2 Register" hexmask.long.word 0x3C 16.--31. 1. "RESERVED," hexmask.long.word 0x3C 5.--15. 1. "RESERVED," bitfld.long 0x3C 0.--4. "VAL,Noise filter-2 intensity values (SP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "IPIPE_D2F_2ND_EDG_MIN,Noise Filter 2 Register" hexmask.long.word 0x40 16.--31. 1. "RESERVED," rbitfld.long 0x40 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x40 0.--10. 1. "VAL,Noise filter-2 edge detection MIN" line.long 0x44 "IPIPE_D2F_2ND_EDG_MAX,Noise Filter 2 Register" hexmask.long.word 0x44 16.--31. 1. "RESERVED," rbitfld.long 0x44 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x44 0.--10. 1. "VAL,Noise filter-2 edge detection MAX" line.long 0x48 "IPIPE_GIC_EN,Green Imbalance Correction Register" hexmask.long.word 0x48 16.--31. 1. "RESERVED," hexmask.long.word 0x48 1.--15. 1. "RESERVED," bitfld.long 0x48 0. "EN,Enable signal of PreFilter module" "EN_0,EN_1" line.long 0x4C "IPIPE_GIC_TYP,Green Imbalance Correction Register" hexmask.long.word 0x4C 16.--31. 1. "RESERVED," hexmask.long.word 0x4C 3.--15. 1. "RESERVED," bitfld.long 0x4C 2. "LSC,Applies LSC gain to threshold value" "LSC_0,LSC_1" bitfld.long 0x4C 1. "SEL,Threshold Selection This bit selects the threshold either from the register value (GIC_THR) or threshold table of NF-2" "SEL_0,SEL_1" newline bitfld.long 0x4C 0. "TYP,Algorithm select" "TYP_0,TYP_1" line.long 0x50 "IPIPE_GIC_GAN,Green Imbalance Correction Register" hexmask.long.word 0x50 16.--31. 1. "RESERVED," hexmask.long.byte 0x50 8.--15. 1. "RESERVED," hexmask.long.byte 0x50 0.--7. 1. "VAL,VAL specifies the PreFilter gain" line.long 0x54 "IPIPE_GIC_NFGAIN," hexmask.long.word 0x54 16.--31. 1. "RESERVED," hexmask.long.byte 0x54 8.--15. 1. "RESERVED," hexmask.long.byte 0x54 0.--7. 1. "VAL," line.long 0x58 "IPIPE_GIC_THR,Green Imbalance Correction Register" hexmask.long.word 0x58 16.--31. 1. "RESERVED," rbitfld.long 0x58 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x58 0.--11. 1. "VAL,Threshold-1 in the adaptive GIC algorithm" line.long 0x5C "IPIPE_GIC_SLP,Green Imbalance Correction Register" hexmask.long.word 0x5C 16.--31. 1. "RESERVED," rbitfld.long 0x5C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x5C 0.--11. 1. "VAL,Slope (THR2-THR1) of GIC algorithm" line.long 0x60 "IPIPE_WB2_OFT_R,White Balance Register" hexmask.long.word 0x60 16.--31. 1. "RESERVED," rbitfld.long 0x60 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x60 0.--11. 1. "VAL,Offset before white balance (S12) -2048 to +2047" line.long 0x64 "IPIPE_WB2_OFT_GR,White Balance Register" hexmask.long.word 0x64 16.--31. 1. "RESERVED," rbitfld.long 0x64 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x64 0.--11. 1. "VAL,Offset before white balance (S12) -2048 to +2047" line.long 0x68 "IPIPE_WB2_OFT_GB,White Balance Register" hexmask.long.word 0x68 16.--31. 1. "RESERVED," rbitfld.long 0x68 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x68 0.--11. 1. "VAL,Offset before white balance (S12) -2048 to +2047" line.long 0x6C "IPIPE_WB2_OFT_B,White Balance Register" hexmask.long.word 0x6C 16.--31. 1. "RESERVED," rbitfld.long 0x6C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x6C 0.--11. 1. "VAL,Offset before white balance (S12) -2048 to +2047" line.long 0x70 "IPIPE_WB2_WGN_R,White Balance Register" hexmask.long.word 0x70 16.--31. 1. "RESERVED," rbitfld.long 0x70 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x70 0.--12. 1. "VAL,White balance gain for R in U4.9 format 0 to +15.998" line.long 0x74 "IPIPE_WB2_WGN_GR,White Balance Register" hexmask.long.word 0x74 16.--31. 1. "RESERVED," rbitfld.long 0x74 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x74 0.--12. 1. "VAL,White balance gain for Gr in U4.9 format 0 to +15.998" line.long 0x78 "IPIPE_WB2_WGN_GB,White Balance Register" hexmask.long.word 0x78 16.--31. 1. "RESERVED," rbitfld.long 0x78 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x78 0.--12. 1. "VAL,White balance gain for Gb in U4.9 format 0 to +15.998" line.long 0x7C "IPIPE_WB2_WGN_B,White Balance Register" hexmask.long.word 0x7C 16.--31. 1. "RESERVED," rbitfld.long 0x7C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x7C 0.--12. 1. "VAL,White balance gain for B in U4.9 format 0 to +15.998" line.long 0x80 "IPIPE_CFA_MODE,CFA Register" hexmask.long.word 0x80 16.--31. 1. "RESERVED," hexmask.long.word 0x80 2.--15. 1. "RESERVED," bitfld.long 0x80 0.--1. "MODE,Algorithm selection" "MODE_0,MODE_1,MODE_2,MODE_3" line.long 0x84 "IPIPE_CFA_2DIR_HPF_THR,CFA: HP Value Low Threshold" hexmask.long.word 0x84 16.--31. 1. "RESERVED," rbitfld.long 0x84 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x84 0.--12. 1. "VAL,HPF_THR 2DirCFA HP Value Low Threshold" line.long 0x88 "IPIPE_CFA_2DIR_HPF_SLP,CFA: HP Value Slope" hexmask.long.word 0x88 16.--31. 1. "RESERVED," rbitfld.long 0x88 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x88 0.--9. 1. "VAL,HPF_SLP 2DirCFA HP Value Slope" line.long 0x8C "IPIPE_CFA_2DIR_MIX_THR,CFA: HP Mix Threshold" hexmask.long.word 0x8C 16.--31. 1. "RESERVED," rbitfld.long 0x8C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x8C 0.--12. 1. "VAL,MIX_THR 2DirCFA HP Mix Threshold" line.long 0x90 "IPIPE_CFA_2DIR_MIX_SLP,CFA Register" hexmask.long.word 0x90 16.--31. 1. "RESERVED," rbitfld.long 0x90 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x90 0.--9. 1. "VAL,MIX_SLP 2DirCFA HP Mix Slope" line.long 0x94 "IPIPE_CFA_2DIR_DIR_TRH,CFA: Direction Threshold" hexmask.long.word 0x94 16.--31. 1. "RESERVED," rbitfld.long 0x94 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x94 0.--9. 1. "VAL,DIR_THR 2DirCFA Direction Threshold" line.long 0x98 "IPIPE_CFA_2DIR_DIR_SLP,CFA: Direction Slope" hexmask.long.word 0x98 16.--31. 1. "RESERVED," hexmask.long.word 0x98 7.--15. 1. "RESERVED," hexmask.long.byte 0x98 0.--6. 1. "VAL,DIR_SLP 2DirCFA Direction Slope" line.long 0x9C "IPIPE_CFA_2DIR_NDWT," hexmask.long.word 0x9C 16.--31. 1. "RESERVED," hexmask.long.word 0x9C 6.--15. 1. "RESERVED," bitfld.long 0x9C 0.--5. "VAL,ND Weight 2DirCFA NonDirectional Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0xA0 "IPIPE_CFA_MONO_HUE_FRA,Mono CFA Register" hexmask.long.word 0xA0 16.--31. 1. "RESERVED," hexmask.long.word 0xA0 6.--15. 1. "RESERVED," bitfld.long 0xA0 0.--5. "VAL,HUE_FRA DAA Hue Fraction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0xA4 "IPIPE_CFA_MONO_EDG_THR,monoCFA THR SLP" hexmask.long.word 0xA4 16.--31. 1. "RESERVED," hexmask.long.byte 0xA4 8.--15. 1. "RESERVED," hexmask.long.byte 0xA4 0.--7. 1. "VAL,EDGE_THR DAA Edge Threshold" line.long 0xA8 "IPIPE_CFA_MONO_THR_MIN,Mono CFA Register" hexmask.long.word 0xA8 16.--31. 1. "RESERVED," rbitfld.long 0xA8 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0xA8 0.--9. 1. "VAL,THR_MIN DAA Threshold Minimum" line.long 0xAC "IPIPE_CFA_MONO_THR_SLP,CFA: Threshold Slope" hexmask.long.word 0xAC 16.--31. 1. "RESERVED," rbitfld.long 0xAC 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0xAC 0.--9. 1. "VAL,THR_SLP DAA Threshold Slope" line.long 0xB0 "IPIPE_CFA_MONO_SLP_MIN,CFA: Threshold Minimum" hexmask.long.word 0xB0 16.--31. 1. "RESERVED," rbitfld.long 0xB0 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0xB0 0.--9. 1. "VAL,SLP_MIN DAA Slope Minimum" line.long 0xB4 "IPIPE_CFA_MONO_SLP_SLP,CFA: Threshold Slope" hexmask.long.word 0xB4 16.--31. 1. "RESERVED," rbitfld.long 0xB4 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0xB4 0.--9. 1. "VAL,SLP_SLP DAA Slope Slope" line.long 0xB8 "IPIPE_CFA_MONO_LPWT,CFA: LP Weight" hexmask.long.word 0xB8 16.--31. 1. "RESERVED," hexmask.long.word 0xB8 6.--15. 1. "RESERVED," bitfld.long 0xB8 0.--5. "VAL,LPWT DAA LP Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0xBC "IPIPE_RGB1_MUL_RR,RGB to RGB Conversion Register" hexmask.long.word 0xBC 16.--31. 1. "RESERVED," rbitfld.long 0xBC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" abitfld.long 0xBC 0.--11. "VAL,The matrix coefficient" "0xFFFFFFFFFFFFFFFF=-2048/256 = -8,0x000=0/256 = 0,0x001=1/256,0x0FF=255/256,0x100=256/256 = 1,0x101=257/256 [...],0x7FE=2046/256 [...],0x7FF=2047/256 = 7.99609375" line.long 0xC0 "IPIPE_RGB1_MUL_GR,RGB to RGB Conversion Register" hexmask.long.word 0xC0 16.--31. 1. "RESERVED," rbitfld.long 0xC0 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC0 0.--11. 1. "VAL,The matrix coefficient" line.long 0xC4 "IPIPE_RGB1_MUL_BR,RGB to RGB Conversion Register" hexmask.long.word 0xC4 16.--31. 1. "RESERVED," rbitfld.long 0xC4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC4 0.--11. 1. "VAL,The matrix coefficient" line.long 0xC8 "IPIPE_RGB1_MUL_RG,RGB to RGB Conversion Register" hexmask.long.word 0xC8 16.--31. 1. "RESERVED," rbitfld.long 0xC8 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC8 0.--11. 1. "VAL,The matrix coefficient" line.long 0xCC "IPIPE_RGB1_MUL_GG,RGB to RGB Conversion Register" hexmask.long.word 0xCC 16.--31. 1. "RESERVED," rbitfld.long 0xCC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xCC 0.--11. 1. "VAL,The matrix coefficient" line.long 0xD0 "IPIPE_RGB1_MUL_BG,RGB to RGB Conversion Register" hexmask.long.word 0xD0 16.--31. 1. "RESERVED," rbitfld.long 0xD0 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xD0 0.--11. 1. "VAL,The matrix coefficient" line.long 0xD4 "IPIPE_RGB1_MUL_RB,RGB to RGB Conversion Register" hexmask.long.word 0xD4 16.--31. 1. "RESERVED," rbitfld.long 0xD4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xD4 0.--11. 1. "VAL,The matrix coefficient" line.long 0xD8 "IPIPE_RGB1_MUL_GB,RGB to RGB Conversion Register" hexmask.long.word 0xD8 16.--31. 1. "RESERVED," rbitfld.long 0xD8 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xD8 0.--11. 1. "VAL,The matrix coefficient" line.long 0xDC "IPIPE_RGB1_MUL_BB,RGB to RGB Conversion Register" hexmask.long.word 0xDC 16.--31. 1. "RESERVED," rbitfld.long 0xDC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xDC 0.--11. 1. "VAL,The matrix coefficient" line.long 0xE0 "IPIPE_RGB1_OFT_OR,RGB to RGB Conversion Register" hexmask.long.word 0xE0 16.--31. 1. "RESERVED," rbitfld.long 0xE0 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0xE0 0.--12. 1. "VAL,The output offset value for R" line.long 0xE4 "IPIPE_RGB1_OFT_OG,RGB to RGB Conversion Register" hexmask.long.word 0xE4 16.--31. 1. "RESERVED," rbitfld.long 0xE4 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0xE4 0.--12. 1. "VAL,The output offset value for G" line.long 0xE8 "IPIPE_RGB1_OFT_OB,RGB to RGB Conversion Register" hexmask.long.word 0xE8 16.--31. 1. "RESERVED," rbitfld.long 0xE8 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0xE8 0.--12. 1. "VAL,The output offset value for B" line.long 0xEC "IPIPE_GMM_CFG,RGB to RGB Conversion Register" hexmask.long.word 0xEC 16.--31. 1. "RESERVED," hexmask.long.word 0xEC 7.--15. 1. "RESERVED," bitfld.long 0xEC 5.--6. "SIZ,The size of the gamma table" "SIZ_0,SIZ_1,SIZ_2,SIZ_3" bitfld.long 0xEC 4. "TBL,Selection of Gamma table" "TBL_0,TBL_1" newline bitfld.long 0xEC 3. "RESERVED," "0,1" bitfld.long 0xEC 2. "BYPB,Gamma correction mode for B" "BYPB_0,BYPB_1" bitfld.long 0xEC 1. "BYPG,Gamma correction mode for G" "BYPG_0,BYPG_1" bitfld.long 0xEC 0. "BYPR,Gamma correction mode for R" "BYPR_0,BYPR_1" line.long 0xF0 "IPIPE_RGB2_MUL_RR,RGB to RGB conversion after gamma" hexmask.long.word 0xF0 16.--31. 1. "RESERVED," rbitfld.long 0xF0 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" abitfld.long 0xF0 0.--10. "VAL,The matrix coefficient" "0xFFFFFFFFFFFFFFFF=-2048/256 = -8,0x000=0/256 = 0,0x001=1/256,0x0FF=255/256,0x100=256/256 = 1,0x101=257/256,0x7FE=2046/256,0x7FF=2047/256 = 7.99609375" line.long 0xF4 "IPIPE_RGB2_MUL_GR,RGB to RGB conversion after gamma" hexmask.long.word 0xF4 16.--31. 1. "RESERVED," rbitfld.long 0xF4 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0xF4 0.--10. 1. "VAL,The matrix coefficient" line.long 0xF8 "IPIPE_RGB2_MUL_BR,RGB to RGB conversion after gamma" hexmask.long.word 0xF8 16.--31. 1. "RESERVED," rbitfld.long 0xF8 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0xF8 0.--10. 1. "VAL,The matrix coefficient" line.long 0xFC "IPIPE_RGB2_MUL_RG,RGB to RGB conversion after gamma" hexmask.long.word 0xFC 16.--31. 1. "RESERVED," rbitfld.long 0xFC 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0xFC 0.--10. 1. "VAL,The matrix coefficient" line.long 0x100 "IPIPE_RGB2_MUL_GG,RGB to RGB conversion after gamma" hexmask.long.word 0x100 16.--31. 1. "RESERVED," rbitfld.long 0x100 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x100 0.--10. 1. "VAL,The matrix coefficient" line.long 0x104 "IPIPE_RGB2_MUL_BG,RGB to RGB conversion after gamma" hexmask.long.word 0x104 16.--31. 1. "RESERVED," rbitfld.long 0x104 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x104 0.--10. 1. "VAL,The matrix coefficient" line.long 0x108 "IPIPE_RGB2_MUL_RB,RGB to RGB conversion after gamma" hexmask.long.word 0x108 16.--31. 1. "RESERVED," rbitfld.long 0x108 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x108 0.--10. 1. "VAL,The matrix coefficient" line.long 0x10C "IPIPE_RGB2_MUL_GB,RGB to RGB conversion after gamma" hexmask.long.word 0x10C 16.--31. 1. "RESERVED," rbitfld.long 0x10C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x10C 0.--10. 1. "VAL,The matrix coefficient" line.long 0x110 "IPIPE_RGB2_MUL_BB,RGB to RGB conversion after gamma" hexmask.long.word 0x110 16.--31. 1. "RESERVED," rbitfld.long 0x110 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x110 0.--10. 1. "VAL,The matrix coefficient" line.long 0x114 "IPIPE_RGB2_OFT_OR,RGB to RGB conversion after gamma" hexmask.long.word 0x114 16.--31. 1. "RESERVED," rbitfld.long 0x114 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x114 0.--10. 1. "VAL,The output offset value for R S10 number: -1024 to + 1023" line.long 0x118 "IPIPE_RGB2_OFT_OG,RGB to RGB conversion after gamma" hexmask.long.word 0x118 16.--31. 1. "RESERVED," rbitfld.long 0x118 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x118 0.--10. 1. "VAL,The output offset value for G S10 number: -1024 to + 1023" line.long 0x11C "IPIPE_RGB2_OFT_OB,RGB to RGB conversion after gamma" hexmask.long.word 0x11C 16.--31. 1. "RESERVED," rbitfld.long 0x11C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x11C 0.--10. 1. "VAL,The output offset value for B S10 number: -1024 to + 1023" line.long 0x120 "IPIPE_3DLUT_EN,3D-LUT" hexmask.long.word 0x120 16.--31. 1. "RESERVED," hexmask.long.word 0x120 1.--15. 1. "RESERVED," bitfld.long 0x120 0. "EN,Enables or disable the 3D-LUT function" "EN_0,EN_1" line.long 0x124 "IPIPE_YUV_ADJ,RGB to YUV Conversion Register" hexmask.long.word 0x124 16.--31. 1. "RESERVED," hexmask.long.byte 0x124 8.--15. 1. "BRT,The offset value for brightness control" abitfld.long 0x124 0.--7. "CRT,The multiplier coefficient value for contrast control" "0x00=0/16 = 0,0x01=1/16,0x0F=15/16,0x10=16/16 = 1,0x11=17/16,0xFE=254/16,0xFF=255/16 = 15.9375" line.long 0x128 "IPIPE_YUV_MUL_RY,RGB to YUV Conversion Register" hexmask.long.word 0x128 16.--31. 1. "RESERVED," rbitfld.long 0x128 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x128 0.--11. 1. "VAL,Matrix Coefficient for RY (S4.8 = -8 - +7.996)" line.long 0x12C "IPIPE_YUV_MUL_GY,RGB to YUV Conversion Register" hexmask.long.word 0x12C 16.--31. 1. "RESERVED," rbitfld.long 0x12C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x12C 0.--11. 1. "VAL,Matrix Coefficient for GY (S4.8 = -8 - +7.996)" line.long 0x130 "IPIPE_YUV_MUL_BY,RGB to YUV Conversion Register" hexmask.long.word 0x130 16.--31. 1. "RESERVED," rbitfld.long 0x130 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x130 0.--11. 1. "VAL,Matrix Coefficient for BY (S4.8 = -8 - +7.996)" line.long 0x134 "IPIPE_YUV_MUL_RCB,RGB to YUV Conversion Register" hexmask.long.word 0x134 16.--31. 1. "RESERVED," rbitfld.long 0x134 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x134 0.--11. 1. "VAL,The matrix coefficient" line.long 0x138 "IPIPE_YUV_MUL_GCB,RGB to YUV Conversion Register" hexmask.long.word 0x138 16.--31. 1. "RESERVED," rbitfld.long 0x138 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x138 0.--11. 1. "VAL,The matrix coefficient" line.long 0x13C "IPIPE_YUV_MUL_BCB,RGB to YUV Conversion Register" hexmask.long.word 0x13C 16.--31. 1. "RESERVED," rbitfld.long 0x13C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x13C 0.--11. 1. "VAL,The matrix coefficient" line.long 0x140 "IPIPE_YUV_MUL_RCR,RGB to YUV Conversion Register" hexmask.long.word 0x140 16.--31. 1. "RESERVED," rbitfld.long 0x140 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x140 0.--11. 1. "VAL,The matrix coefficient" line.long 0x144 "IPIPE_YUV_MUL_GCR,RGB to YUV Conversion Register" hexmask.long.word 0x144 16.--31. 1. "RESERVED," rbitfld.long 0x144 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x144 0.--11. 1. "VAL,The matrix coefficient" line.long 0x148 "IPIPE_YUV_MUL_BCR,RGB to YUV Conversion Register" hexmask.long.word 0x148 16.--31. 1. "RESERVED," rbitfld.long 0x148 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x148 0.--11. 1. "VAL,The matrix coefficient" line.long 0x14C "IPIPE_YUV_OFT_Y,RGB to YUV Conversion Register" hexmask.long.word 0x14C 16.--31. 1. "RESERVED," rbitfld.long 0x14C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x14C 0.--10. 1. "VAL,The output offset value for Y" line.long 0x150 "IPIPE_YUV_OFT_CB,RGB to YUV Conversion Register" hexmask.long.word 0x150 16.--31. 1. "RESERVED," rbitfld.long 0x150 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x150 0.--10. 1. "VAL,The output offset value for Cb For Cb/Cr set (0x80 + offset value) here" line.long 0x154 "IPIPE_YUV_OFT_CR,RGB to YUV Conversion Register" hexmask.long.word 0x154 16.--31. 1. "RESERVED," rbitfld.long 0x154 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x154 0.--10. 1. "VAL,The output offset value for Cr For Cb/Cr set (0x80 + offset value) here" line.long 0x158 "IPIPE_YUV_PHS,YUV422 down sampling register" hexmask.long.word 0x158 16.--31. 1. "RESERVED," hexmask.long.word 0x158 2.--15. 1. "RESERVED," bitfld.long 0x158 1. "LPF,121-LPF enable for chrominance samples" "LPF_0,LPF_1" bitfld.long 0x158 0. "POS,This bit sets the output position of the chrominance sample with regards to the luma sample positions" "POS_0,POS_1" line.long 0x15C "IPIPE_GBCE_EN,Global brightness contrast enhancement" hexmask.long.word 0x15C 16.--31. 1. "RESERVED," hexmask.long.word 0x15C 1.--15. 1. "RESERVED," bitfld.long 0x15C 0. "EN,Enable of GBCE module" "EN_0,EN_1" line.long 0x160 "IPIPE_GBCE_TYP,Global brightness contrast enhancement" hexmask.long.word 0x160 16.--31. 1. "RESERVED," hexmask.long.word 0x160 1.--15. 1. "RESERVED," bitfld.long 0x160 0. "TYP,GBCE method selection" "TYP_0,TYP_1" line.long 0x164 "IPIPE_YEE_EN,Edge Enhancer Register" hexmask.long.word 0x164 16.--31. 1. "RESERVED," hexmask.long.word 0x164 1.--15. 1. "RESERVED," bitfld.long 0x164 0. "EN,The on/off selection of the ?Edge enhancer?" "EN_0,EN_1" line.long 0x168 "IPIPE_YEE_TYP,Edge Enhancer Register" hexmask.long.word 0x168 16.--31. 1. "RESERVED," hexmask.long.word 0x168 2.--15. 1. "RESERVED," bitfld.long 0x168 1. "HAL,Halo reduction in Edge Sharpener module" "0,1" bitfld.long 0x168 0. "SEL,Merging method between Edge Enhancer and Edge Sharpener" "SEL_0,SEL_1" line.long 0x16C "IPIPE_YEE_SHF,Edge Enhancer Register" hexmask.long.word 0x16C 16.--31. 1. "RESERVED," hexmask.long.word 0x16C 4.--15. 1. "RESERVED," bitfld.long 0x16C 0.--3. "SHF,Down shift length of high pass filter (HPF) in edge enhancer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x170 "IPIPE_YEE_MUL_00,Edge Enhancer Register" hexmask.long.word 0x170 16.--31. 1. "RESERVED," rbitfld.long 0x170 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" abitfld.long 0x170 0.--9. "VAL,Multiplier coefficient in HPF" "0x000=0,0x001=1,0x1FE=510,0x1FF=511,0x200=-512,0x201=-511,0x3FF=-1" line.long 0x174 "IPIPE_YEE_MUL_01,Edge Enhancer Register" hexmask.long.word 0x174 16.--31. 1. "RESERVED," rbitfld.long 0x174 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x174 0.--9. 1. "VAL,Multiplier coefficient in HPF" line.long 0x178 "IPIPE_YEE_MUL_02,Edge Enhancer Register" hexmask.long.word 0x178 16.--31. 1. "RESERVED," rbitfld.long 0x178 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x178 0.--9. 1. "VAL,Multiplier coefficient in HPF" line.long 0x17C "IPIPE_YEE_MUL_10,Edge Enhancer Register" hexmask.long.word 0x17C 16.--31. 1. "RESERVED," rbitfld.long 0x17C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x17C 0.--9. 1. "VAL,Multiplier coefficient in HPF" line.long 0x180 "IPIPE_YEE_MUL_11,Edge Enhancer Register" hexmask.long.word 0x180 16.--31. 1. "RESERVED," rbitfld.long 0x180 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x180 0.--9. 1. "VAL,Multiplier coefficient in HPF" line.long 0x184 "IPIPE_YEE_MUL_12,Edge Enhancer Register" hexmask.long.word 0x184 16.--31. 1. "RESERVED," rbitfld.long 0x184 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x184 0.--9. 1. "VAL,Multiplier coefficient in HPF" line.long 0x188 "IPIPE_YEE_MUL_20,Edge Enhancer Register" hexmask.long.word 0x188 16.--31. 1. "RESERVED," rbitfld.long 0x188 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x188 0.--9. 1. "VAL,Multiplier coefficient in HPF" line.long 0x18C "IPIPE_YEE_MUL_21,Edge Enhancer Register" hexmask.long.word 0x18C 16.--31. 1. "RESERVED," rbitfld.long 0x18C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x18C 0.--9. 1. "VAL,Multiplier coefficient in HPF" line.long 0x190 "IPIPE_YEE_MUL_22,Edge Enhancer Register" hexmask.long.word 0x190 16.--31. 1. "RESERVED," rbitfld.long 0x190 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x190 0.--9. 1. "VAL,Multiplier coefficient in HPF" line.long 0x194 "IPIPE_YEE_THR,Edge Enhancer Register" hexmask.long.word 0x194 16.--31. 1. "RESERVED," hexmask.long.word 0x194 6.--15. 1. "RESERVED," bitfld.long 0x194 0.--5. "VAL,Edge Enhancer lower threshold before referring to LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x198 "IPIPE_YEE_E_GAN,Edge Enhancer Register" hexmask.long.word 0x198 16.--31. 1. "RESERVED," rbitfld.long 0x198 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x198 0.--11. 1. "VAL,Edge sharpener gain" line.long 0x19C "IPIPE_YEE_E_THR_1,Edge Enhancer Register" hexmask.long.word 0x19C 16.--31. 1. "RESERVED," rbitfld.long 0x19C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x19C 0.--11. 1. "VAL,Edge sharpener HPF value lower limit" line.long 0x1A0 "IPIPE_YEE_E_THR_2,Edge Enhancer Register" hexmask.long.word 0x1A0 16.--31. 1. "RESERVED," hexmask.long.word 0x1A0 6.--15. 1. "RESERVED," bitfld.long 0x1A0 0.--5. "VAL,Edge sharpener HPF value upper limit (after 6 bit right shift)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1A4 "IPIPE_YEE_G_GAN,Edge Enhancer Register" hexmask.long.word 0x1A4 16.--31. 1. "RESERVED," hexmask.long.byte 0x1A4 8.--15. 1. "RESERVED," hexmask.long.byte 0x1A4 0.--7. 1. "VAL,Edge sharpener gain value on gradient" line.long 0x1A8 "IPIPE_YEE_G_OFT,Edge Enhancer Register" hexmask.long.word 0x1A8 16.--31. 1. "RESERVED," hexmask.long.word 0x1A8 6.--15. 1. "RESERVED," bitfld.long 0x1A8 0.--5. "VAL,Edge sharpener offset value on gradient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1AC "IPIPE_CAR_EN,Chroma Artifact Reduction Register" hexmask.long.word 0x1AC 16.--31. 1. "RESERVED," hexmask.long.word 0x1AC 1.--15. 1. "RESERVED," bitfld.long 0x1AC 0. "EN,The on/off selection of the ?fault color suppression?" "EN_0,EN_1" line.long 0x1B0 "IPIPE_CAR_TYP,Chroma Artifact Reduction Register" hexmask.long.word 0x1B0 16.--31. 1. "RESERVED," hexmask.long.word 0x1B0 2.--15. 1. "RESERVED," bitfld.long 0x1B0 1. "CHR,Note: This bit is added to OMAP5430 release and after" "Normal Cb/Cr order (default),Flipped order (Cr/Cb)" bitfld.long 0x1B0 0. "TYP,The mode selection of the ?fault color suppression?" "TYP_0,TYP_1" line.long 0x1B4 "IPIPE_CAR_SW,Chroma Artifact Reduction Register" hexmask.long.word 0x1B4 16.--31. 1. "RESERVED," hexmask.long.byte 0x1B4 8.--15. 1. "SW1,Threshold-2 for switching function (Select gain control)" hexmask.long.byte 0x1B4 0.--7. 1. "SW0,Threshold-1 for switching function (Select median filter)" line.long 0x1B8 "IPIPE_CAR_HPF_TYP,Chroma Artifact Reduction Register" hexmask.long.word 0x1B8 16.--31. 1. "RESERVED," hexmask.long.word 0x1B8 3.--15. 1. "RESERVED," bitfld.long 0x1B8 0.--2. "TYP," "TYP_0,TYP_1,TYP_2,TYP_3,TYP_4,TYP_5,TYP_6,TYP_7" line.long 0x1BC "IPIPE_CAR_HPF_SHF,Chroma Artifact Reduction Register" hexmask.long.word 0x1BC 16.--31. 1. "RESERVED," hexmask.long.word 0x1BC 2.--15. 1. "RESERVED," bitfld.long 0x1BC 0.--1. "VAL,Down shift value for HPF" "0,1,2,3" line.long 0x1C0 "IPIPE_CAR_HPF_THR,Chroma Artifact Reduction Register" hexmask.long.word 0x1C0 16.--31. 1. "RESERVED," hexmask.long.byte 0x1C0 8.--15. 1. "RESERVED," hexmask.long.byte 0x1C0 0.--7. 1. "VAL,The threshold of the gain function for HPF value" line.long 0x1C4 "IPIPE_CAR_GN1_GAN,Chroma Artifact Reduction Register" hexmask.long.word 0x1C4 16.--31. 1. "RESERVED," hexmask.long.byte 0x1C4 8.--15. 1. "RESERVED," hexmask.long.byte 0x1C4 0.--7. 1. "VAL,The intensity of the gain function for HPF value" line.long 0x1C8 "IPIPE_CAR_GN1_SHF,Chroma Artifact Reduction Register" hexmask.long.word 0x1C8 16.--31. 1. "RESERVED," hexmask.long.word 0x1C8 3.--15. 1. "RESERVED," bitfld.long 0x1C8 0.--2. "VAL,The down shift value of the gain function on HPF value" "0,1,2,3,4,5,6,7" line.long 0x1CC "IPIPE_CAR_GN1_MIN,Chroma Artifact Reduction Register" hexmask.long.word 0x1CC 16.--31. 1. "RESERVED," hexmask.long.byte 0x1CC 9.--15. 1. "RESERVED," hexmask.long.word 0x1CC 0.--8. 1. "VAL,The lower limit of the gain function on HPF value" line.long 0x1D0 "IPIPE_CAR_GN2_GAN,Chroma Artifact Reduction Register" hexmask.long.word 0x1D0 16.--31. 1. "RESERVED," hexmask.long.byte 0x1D0 8.--15. 1. "RESERVED," hexmask.long.byte 0x1D0 0.--7. 1. "VAL,The intensity of the gain function for chroma value" line.long 0x1D4 "IPIPE_CAR_GN2_SHF,Chroma Artifact Reduction Register" hexmask.long 0x1D4 4.--31. 1. "RESERVED," bitfld.long 0x1D4 0.--3. "VAL,The down shift value of the gain function on chroma value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1D8 "IPIPE_CAR_GN2_MIN,Chroma Artifact Reduction Register" hexmask.long.word 0x1D8 16.--31. 1. "RESERVED," hexmask.long.byte 0x1D8 9.--15. 1. "RESERVED," hexmask.long.word 0x1D8 0.--8. 1. "VAL,The lower limit of the gain function on chroma value" line.long 0x1DC "IPIPE_CGS_EN,Chroma Gain Suppression" hexmask.long.word 0x1DC 16.--31. 1. "RESERVED," hexmask.long.word 0x1DC 1.--15. 1. "RESERVED," bitfld.long 0x1DC 0. "EN,Enables or disables chroma gain suppression" "EN_0,EN_1" line.long 0x1E0 "IPIPE_CGS_GN1_L_THR,Chroma Gain Suppression" hexmask.long.word 0x1E0 16.--31. 1. "RESERVED," hexmask.long.byte 0x1E0 8.--15. 1. "RESERVED," hexmask.long.byte 0x1E0 0.--7. 1. "VAL," line.long 0x1E4 "IPIPE_CGS_GN1_L_GAIN,Chroma Gain Suppression" hexmask.long.word 0x1E4 16.--31. 1. "RESERVED," hexmask.long.byte 0x1E4 8.--15. 1. "RESERVED," hexmask.long.byte 0x1E4 0.--7. 1. "VAL," line.long 0x1E8 "IPIPE_CGS_GN1_L_SHF,Chroma Gain Suppression" hexmask.long.word 0x1E8 16.--31. 1. "RESERVED," hexmask.long.word 0x1E8 3.--15. 1. "RESERVED," bitfld.long 0x1E8 0.--2. "VAL," "0,1,2,3,4,5,6,7" line.long 0x1EC "IPIPE_CGS_GN1_L_MIN,Chroma Gain Suppression" hexmask.long.word 0x1EC 16.--31. 1. "RESERVED," hexmask.long.byte 0x1EC 8.--15. 1. "RESERVED," hexmask.long.byte 0x1EC 0.--7. 1. "VAL,The lower limit 1 of the gain function 1" line.long 0x1F0 "IPIPE_CGS_GN1_H_THR,Chroma Gain Suppression" hexmask.long.word 0x1F0 16.--31. 1. "RESERVED," hexmask.long.byte 0x1F0 8.--15. 1. "RESERVED," hexmask.long.byte 0x1F0 0.--7. 1. "VAL,The threshold 2 of the gain function for Y value" line.long 0x1F4 "IPIPE_CGS_GN1_H_GAIN,Chroma Gain Suppression" hexmask.long.word 0x1F4 16.--31. 1. "RESERVED," hexmask.long.byte 0x1F4 8.--15. 1. "RESERVED," hexmask.long.byte 0x1F4 0.--7. 1. "VAL,The slope 2 of the gain function for Y value" line.long 0x1F8 "IPIPE_CGS_GN1_H_SHF,Chroma Gain Suppression" hexmask.long.word 0x1F8 16.--31. 1. "RESERVED," hexmask.long.word 0x1F8 3.--15. 1. "RESERVED," bitfld.long 0x1F8 0.--2. "VAL,The down shift value of the gain function on Y" "0,1,2,3,4,5,6,7" line.long 0x1FC "IPIPE_CGS_GN1_H_MIN,Chroma Gain Suppression" hexmask.long.word 0x1FC 16.--31. 1. "RESERVED," hexmask.long.byte 0x1FC 8.--15. 1. "RESERVED," hexmask.long.byte 0x1FC 0.--7. 1. "VAL,The lower limit 2 of the gain function" line.long 0x200 "IPIPE_CGS_GN2_L_THR,Chroma Gain Suppression" hexmask.long.word 0x200 16.--31. 1. "RESERVED," hexmask.long.byte 0x200 8.--15. 1. "RESERVED," hexmask.long.byte 0x200 0.--7. 1. "VAL,The slope 2 of the gain function for Y value" line.long 0x204 "IPIPE_CGS_GN2_L_GAIN,Chroma Gain Suppression" hexmask.long.word 0x204 16.--31. 1. "RESERVED," hexmask.long.byte 0x204 8.--15. 1. "RESERVED," hexmask.long.byte 0x204 0.--7. 1. "VAL,The down shift value 3 of the gain function on Y" line.long 0x208 "IPIPE_CGS_GN2_L_SHF," hexmask.long.word 0x208 16.--31. 1. "RESERVED," hexmask.long.word 0x208 3.--15. 1. "RESERVED," bitfld.long 0x208 0.--2. "VAL," "0,1,2,3,4,5,6,7" line.long 0x20C "IPIPE_CGS_GN2_L_MIN,Chroma Gain Suppression" hexmask.long.word 0x20C 16.--31. 1. "RESERVED," hexmask.long.byte 0x20C 8.--15. 1. "RESERVED," hexmask.long.byte 0x20C 0.--7. 1. "VAL,The lower limit 3 of the gain function" line.long 0x210 "IPIPE_BOX_EN,Boxcar Register" hexmask.long.word 0x210 16.--31. 1. "RESERVED," hexmask.long.word 0x210 1.--15. 1. "RESERVED," bitfld.long 0x210 0. "EN,This bit enables ordisables the BOXCAR functionality" "EN_0,EN_1" line.long 0x214 "IPIPE_BOX_MODE,Boxcar Register" hexmask.long.word 0x214 16.--31. 1. "RESERVED," hexmask.long.word 0x214 1.--15. 1. "RESERVED," bitfld.long 0x214 0. "OST,The processing mode selection of the Boxcar function" "OST_0,OST_1" line.long 0x218 "IPIPE_BOX_TYP,Boxcar Register" hexmask.long.word 0x218 16.--31. 1. "RESERVED," hexmask.long.word 0x218 1.--15. 1. "RESERVED," bitfld.long 0x218 0. "SEL,Block size in boxcar sampling" "SEL_0,SEL_1" line.long 0x21C "IPIPE_BOX_SHF,Boxcar Register" hexmask.long.word 0x21C 16.--31. 1. "RESERVED," hexmask.long.word 0x21C 3.--15. 1. "RESERVED," bitfld.long 0x21C 0.--2. "VAL,The down shift value applied to the boxcar compuation result" "0,1,2,3,4,5,6,7" line.long 0x220 "IPIPE_BOX_SDR_SAD_H,Boxcar Register" hexmask.long.word 0x220 16.--31. 1. "RESERVED," hexmask.long.word 0x220 0.--15. 1. "VAL,The higher 11 bits of the first address of output in memory" line.long 0x224 "IPIPE_BOX_SDR_SAD_L,Boxcar Register" hexmask.long.word 0x224 16.--31. 1. "RESERVED," hexmask.long.word 0x224 5.--15. 1. "VAL,The lower 16 bits of the first address of output in memory" rbitfld.long 0x224 0.--4. "VAL_RESERVED,Ensures 32-byte alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x39C++0xBB line.long 0x00 "IPIPE_HST_EN,Histogram" hexmask.long.word 0x00 16.--31. 1. "RESERVED," hexmask.long.word 0x00 1.--15. 1. "RESERVED," bitfld.long 0x00 0. "EN,This bit enables or disables the HISTOGRAM functionality" "EN_0,EN_1" line.long 0x04 "IPIPE_HST_MODE,Histogram" hexmask.long.word 0x04 16.--31. 1. "RESERVED," hexmask.long.word 0x04 1.--15. 1. "RESERVED," bitfld.long 0x04 0. "OST,The processing mode selection of the Histogram module" "OST_0,OST_1" line.long 0x08 "IPIPE_HST_SEL,Histogram" hexmask.long.word 0x08 16.--31. 1. "RESERVED," hexmask.long.word 0x08 3.--15. 1. "RESERVED," bitfld.long 0x08 2. "SEL,Input selection" "SEL_0,SEL_1" bitfld.long 0x08 0.--1. "TYP,G selection in Bayer mode (SEL0=0)" "TYP_0,TYP_1,TYP_2,TYP_3" line.long 0x0C "IPIPE_HST_PARA,Histogram COL0. COL1. COL2. and COL3 should be set to ?1?" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," rbitfld.long 0x0C 14.--15. "RESERVED," "0,1,2,3" bitfld.long 0x0C 12.--13. "BIN,The number of the bins" "BIN_0,BIN_1,BIN_2,BIN_3" bitfld.long 0x0C 8.--11. "SHF,The shift length of the input data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 7. "COL3,The on/off selection of the color pattern 3 (Y)" "COL3_0,COL3_1" bitfld.long 0x0C 6. "COL2,The on/off selection of the color pattern 2 (B)" "COL2_0,COL2_1" bitfld.long 0x0C 5. "COL1,The on/off selection of the color pattern 1 (G)" "COL1_0,COL1_1" bitfld.long 0x0C 4. "COL0,The on/off selection of the color pattern 0 (R)" "COL0_0,COL0_1" newline bitfld.long 0x0C 3. "RGN3,The on/off selection of the region 3" "RGN3_0,RGN3_1" bitfld.long 0x0C 2. "RGN2,The on/off selection of the region 2" "RGN2_0,RGN2_1" bitfld.long 0x0C 1. "RGN1,The on/off selection of the region 1" "RGN1_0,RGN1_1" bitfld.long 0x0C 0. "RGN0,The on/off selection of the region 0" "RGN0_0,RGN0_1" line.long 0x10 "IPIPE_HST_0_VPS,Histogram" hexmask.long.word 0x10 16.--31. 1. "RESERVED," rbitfld.long 0x10 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 1.--12. 1. "VAL,The vertical position of the region 0 from theIPIPE_SRC_VPS" rbitfld.long 0x10 0. "VAL_RESERVED,The vertical position of the region 0 from theIPIPE_SRC_VPS" "0,1" line.long 0x14 "IPIPE_HST_0_VSZ,Histogram" hexmask.long.word 0x14 16.--31. 1. "RESERVED," rbitfld.long 0x14 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 1.--12. 1. "VAL,The vertical size of the region 0" rbitfld.long 0x14 0. "VAL_RESERVED,The vertical size of the region 0" "0,1" line.long 0x18 "IPIPE_HST_0_HPS,Histogram" hexmask.long.word 0x18 16.--31. 1. "RESERVED," rbitfld.long 0x18 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x18 1.--12. 1. "VAL,The horizontal position of the region 0 from theIPIPE_SRC_HPS" rbitfld.long 0x18 0. "VAL_RESERVED,The horizontal position of the region 0 from theIPIPE_SRC_HPS" "0,1" line.long 0x1C "IPIPE_HST_0_HSZ,Histogram" hexmask.long.word 0x1C 16.--31. 1. "RESERVED," rbitfld.long 0x1C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x1C 1.--12. 1. "VAL,The horizontal size of the region 0" rbitfld.long 0x1C 0. "VAL_RESERVED,The horizontal size of the region 0" "0,1" line.long 0x20 "IPIPE_HST_1_VPS,Histogram" hexmask.long.word 0x20 16.--31. 1. "RESERVED," rbitfld.long 0x20 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x20 1.--12. 1. "VAL,The vertical position of the region 0 from theIPIPE_SRC_VPS" rbitfld.long 0x20 0. "VAL_RESERVED,The vertical position of the region 0 from theIPIPE_SRC_VPS" "0,1" line.long 0x24 "IPIPE_HST_1_VSZ,Histogram" hexmask.long.word 0x24 16.--31. 1. "RESERVED," rbitfld.long 0x24 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x24 1.--12. 1. "VAL,The vertical size of the region 1" rbitfld.long 0x24 0. "VAL_RESERVED,The vertical size of the region 1" "0,1" line.long 0x28 "IPIPE_HST_1_HPS,Histogram" hexmask.long.word 0x28 16.--31. 1. "RESERVED," rbitfld.long 0x28 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x28 1.--12. 1. "VAL,The horizontal position of the region 0 from theIPIPE_SRC_HPS" rbitfld.long 0x28 0. "VAL_RESERVED,The horizontal position of the region 0 from theIPIPE_SRC_HPS" "0,1" line.long 0x2C "IPIPE_HST_1_HSZ,Histogram" hexmask.long.word 0x2C 16.--31. 1. "RESERVED," rbitfld.long 0x2C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x2C 1.--12. 1. "VAL,The horizontal size of the region 1" rbitfld.long 0x2C 0. "VAL_RESERVED,The horizontal size of the region 1" "0,1" line.long 0x30 "IPIPE_HST_2_VPS,Histogram" hexmask.long.word 0x30 16.--31. 1. "RESERVED," rbitfld.long 0x30 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x30 1.--12. 1. "VAL,The vertical position of the region 0 from theIPIPE_SRC_VPS" rbitfld.long 0x30 0. "VAL_RESERVED,The vertical position of the region 0 from theIPIPE_SRC_VPS" "0,1" line.long 0x34 "IPIPE_HST_2_VSZ,Histogram" hexmask.long.word 0x34 16.--31. 1. "RESERVED," rbitfld.long 0x34 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x34 1.--12. 1. "VAL,The vertical size of the region 2" rbitfld.long 0x34 0. "VAL_RESERVED,The vertical size of the region 2" "0,1" line.long 0x38 "IPIPE_HST_2_HPS,Histogram" hexmask.long.word 0x38 16.--31. 1. "RESERVED," rbitfld.long 0x38 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x38 1.--12. 1. "VAL,The horizontal position of the region 0 from theIPIPE_SRC_HPS" rbitfld.long 0x38 0. "VAL_RESERVED,The horizontal position of the region 0 from theIPIPE_SRC_HPS" "0,1" line.long 0x3C "IPIPE_HST_2_HSZ,Histogram" hexmask.long.word 0x3C 16.--31. 1. "RESERVED," rbitfld.long 0x3C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x3C 1.--12. 1. "VAL,The horizontal size of the region 2" rbitfld.long 0x3C 0. "VAL_RESERVED,The horizontal size of the region 2" "0,1" line.long 0x40 "IPIPE_HST_3_VPS,Histogram" hexmask.long.word 0x40 16.--31. 1. "RESERVED," rbitfld.long 0x40 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x40 1.--12. 1. "VAL,The vertical position of the region 0 from theIPIPE_SRC_VPS" rbitfld.long 0x40 0. "VAL_RESERVED,The vertical position of the region 0 from theIPIPE_SRC_VPS" "0,1" line.long 0x44 "IPIPE_HST_3_VSZ,Histogram" hexmask.long.word 0x44 16.--31. 1. "RESERVED," rbitfld.long 0x44 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x44 1.--12. 1. "VAL,The vertical size of the region 3" rbitfld.long 0x44 0. "VAL_RESERVED,The vertical size of the region 3" "0,1" line.long 0x48 "IPIPE_HST_3_HPS,Histogram" hexmask.long.word 0x48 16.--31. 1. "RESERVED," rbitfld.long 0x48 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x48 1.--12. 1. "VAL,The horizontal position of the region 0 from theIPIPE_SRC_HPS" rbitfld.long 0x48 0. "VAL_RESERVED,The horizontal position of the region 0 from theIPIPE_SRC_HPS" "0,1" line.long 0x4C "IPIPE_HST_3_HSZ,Histogram" hexmask.long.word 0x4C 16.--31. 1. "RESERVED," rbitfld.long 0x4C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x4C 1.--12. 1. "VAL,The horizontal size of the region 3" rbitfld.long 0x4C 0. "VAL_RESERVED,The horizontal size of the region 3" "0,1" line.long 0x50 "IPIPE_HST_TBL,Histogram" hexmask.long.word 0x50 16.--31. 1. "RESERVED," hexmask.long.word 0x50 2.--15. 1. "RESERVED," bitfld.long 0x50 1. "CLR,Histogram memory clear" "CLR_0,CLR_1" bitfld.long 0x50 0. "SEL,This bit shall be used to select which memory is used to store the histogram data" "SEL_0,SEL_1" line.long 0x54 "IPIPE_HST_MUL_R,Histogram" hexmask.long.word 0x54 16.--31. 1. "RESERVED," hexmask.long.byte 0x54 8.--15. 1. "RESERVED," hexmask.long.byte 0x54 0.--7. 1. "GAIN,Gain" line.long 0x58 "IPIPE_HST_MUL_GR,Histogram" hexmask.long.word 0x58 16.--31. 1. "RESERVED," hexmask.long.byte 0x58 8.--15. 1. "RESERVED," hexmask.long.byte 0x58 0.--7. 1. "GAIN,Gain" line.long 0x5C "IPIPE_HST_MUL_GB,Histogram" hexmask.long.word 0x5C 16.--31. 1. "RESERVED," hexmask.long.byte 0x5C 8.--15. 1. "RESERVED," hexmask.long.byte 0x5C 0.--7. 1. "GAIN,Gain" line.long 0x60 "IPIPE_HST_MUL_B,Histogram" hexmask.long.word 0x60 16.--31. 1. "RESERVED," hexmask.long.byte 0x60 8.--15. 1. "RESERVED," hexmask.long.byte 0x60 0.--7. 1. "GAIN,Gain" line.long 0x64 "IPIPE_BSC_EN,Boundary Signal Calculator" hexmask.long.word 0x64 16.--31. 1. "RESERVED," hexmask.long.word 0x64 1.--15. 1. "RESERVED," bitfld.long 0x64 0. "EN,The start flag of the ?Boundary Signal Calculator?" "EN_0,EN_1" line.long 0x68 "IPIPE_BSC_MODE,Boundary Signal Calculator" hexmask.long.word 0x68 16.--31. 1. "RESERVED," hexmask.long.word 0x68 1.--15. 1. "RESERVED," bitfld.long 0x68 0. "OST,The processing mode selection of the BSC module" "OST_0,OST_1" line.long 0x6C "IPIPE_BSC_TYP,Boundary Signal Calculator" hexmask.long.word 0x6C 16.--31. 1. "RESERVED," hexmask.long.word 0x6C 4.--15. 1. "RESERVED," bitfld.long 0x6C 3. "CEN,Enable of column sampling" "CEN_0,CEN_1" bitfld.long 0x6C 2. "REN,Enable of row sampling" "REN_0,REN_1" newline bitfld.long 0x6C 0.--1. "COL,Selects the element to be summed" "COL_0,COL_1,COL_2,COL_3" line.long 0x70 "IPIPE_BSC_ROW_VCT,Boundary Signal Calculator" hexmask.long.word 0x70 16.--31. 1. "RESERVED," hexmask.long.word 0x70 2.--15. 1. "RESERVED," bitfld.long 0x70 0.--1. "VAL,The number of row sum vectors" "0,1,2,3" line.long 0x74 "IPIPE_BSC_ROW_SHF,Boundary Signal Calculator" hexmask.long.word 0x74 16.--31. 1. "RESERVED," hexmask.long.word 0x74 3.--15. 1. "RESERVED," bitfld.long 0x74 0.--2. "VAL,The down shift value for row sum vectors" "0,1,2,3,4,5,6,7" line.long 0x78 "IPIPE_BSC_ROW_VPOS,Boundary Signal Calculator" hexmask.long.word 0x78 16.--31. 1. "RESERVED," rbitfld.long 0x78 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x78 0.--12. 1. "VAL,The vertical position of the first sampling pixel; the first row to be summed" line.long 0x7C "IPIPE_BSC_ROW_VNUM,Boundary Signal Calculator" hexmask.long.tbyte 0x7C 13.--31. 1. "RESERVED," hexmask.long.word 0x7C 1.--12. 1. "VAL,The height of the area covered by a row sum vector" rbitfld.long 0x7C 0. "VAL_0,The LSB must be odd" "0,1" line.long 0x80 "IPIPE_BSC_ROW_VSKIP,Boundary Signal Calculator" hexmask.long.word 0x80 16.--31. 1. "RESERVED," hexmask.long.word 0x80 5.--15. 1. "RESERVED," bitfld.long 0x80 0.--4. "VAL,The interval of the rows" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x84 "IPIPE_BSC_ROW_HPOS,Boundary Signal Calculator" hexmask.long.word 0x84 16.--31. 1. "RESERVED," rbitfld.long 0x84 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x84 0.--12. 1. "VAL,The horizontal position of the first sampling pixel; the first pixel in a row to be summed" line.long 0x88 "IPIPE_BSC_ROW_HNUM,Boundary Signal Calculator" hexmask.long.word 0x88 16.--31. 1. "RESERVED," rbitfld.long 0x88 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x88 0.--12. 1. "VAL,The horizontal number of samples in the area covered by a row sum vector" line.long 0x8C "IPIPE_BSC_ROW_HSKIP,Boundary Signal Calculator" hexmask.long.word 0x8C 16.--31. 1. "RESERVED," hexmask.long.word 0x8C 5.--15. 1. "RESERVED," bitfld.long 0x8C 0.--4. "VAL,The interval of the pixels in a row to be summed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x90 "IPIPE_BSC_COL_VCT,Boundary Signal Calculator" hexmask.long.word 0x90 16.--31. 1. "RESERVED," hexmask.long.word 0x90 2.--15. 1. "RESERVED," bitfld.long 0x90 0.--1. "VAL,The number of column sum vectors" "0,1,2,3" line.long 0x94 "IPIPE_BSC_COL_SHF,Boundary Signal Calculator" hexmask.long.word 0x94 16.--31. 1. "RESERVED," hexmask.long.word 0x94 3.--15. 1. "RESERVED," bitfld.long 0x94 0.--2. "VAL,The down shift value for column sum vectors" "0,1,2,3,4,5,6,7" line.long 0x98 "IPIPE_BSC_COL_VPOS,Boundary Signal Calculator" hexmask.long.word 0x98 16.--31. 1. "RESERVED," rbitfld.long 0x98 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x98 0.--12. 1. "VAL,The vertical position of the first sampling pixel; the first pixel in a column to be summed" line.long 0x9C "IPIPE_BSC_COL_VNUM,Boundary Signal Calculator" hexmask.long.word 0x9C 16.--31. 1. "RESERVED," rbitfld.long 0x9C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x9C 0.--12. 1. "VAL,The vertical number of samples in the area covered by a column sum vector" line.long 0xA0 "IPIPE_BSC_COL_VSKIP,Boundary Signal Calculator" hexmask.long.word 0xA0 16.--31. 1. "RESERVED," hexmask.long.word 0xA0 5.--15. 1. "RESERVED," bitfld.long 0xA0 0.--4. "VAL,The interval of the pixels in a column to be summed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA4 "IPIPE_BSC_COL_HPOS,Boundary Signal Calculator" hexmask.long.word 0xA4 16.--31. 1. "RESERVED," rbitfld.long 0xA4 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0xA4 0.--12. 1. "VAL,The horizontal position of the first sampling pixel; the first column to be summed" line.long 0xA8 "IPIPE_BSC_COL_HNUM,Boundary Signal Calculator" hexmask.long.tbyte 0xA8 13.--31. 1. "RESERVED," hexmask.long.word 0xA8 1.--12. 1. "VAL,The width of the area covered by a column sum vector" rbitfld.long 0xA8 0. "VAL_0,The LSB must be odd" "0,1" line.long 0xAC "IPIPE_BSC_COL_HSKIP,Boundary Signal Calculator" hexmask.long.word 0xAC 16.--31. 1. "RESERVED," hexmask.long.word 0xAC 5.--15. 1. "RESERVED," bitfld.long 0xAC 0.--4. "VAL,The interval of the columns" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB0 "IPIPE_YUV_INP_OFST_Y,Offset value applied to Y input becore YUVtoRGB matrix" hexmask.long.tbyte 0xB0 9.--31. 1. "RESERVED," hexmask.long.word 0xB0 0.--8. 1. "Y_OFST,Y offset value (s9) Usually zero" line.long 0xB4 "IPIPE_YUV_INP_OFST_CB,Offset value applied to CB input becore YUVtoRGB matrix" hexmask.long.tbyte 0xB4 9.--31. 1. "RESERVED," hexmask.long.word 0xB4 0.--8. 1. "CB_OFST,Cb offset value (s9) Usually -128" line.long 0xB8 "IPIPE_YUV_INP_OFST_CR,Offset value applied to CR input becore YUVtoRGB matrix" hexmask.long.tbyte 0xB8 9.--31. 1. "RESERVED," hexmask.long.word 0xB8 0.--8. 1. "CR_OFST,Cr offset value (s9) Usually -128" repeat 8. (list 00. 01. 02. 03. 04. 05. 06. 07. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C ) group.long ($2+0x150)++0x03 line.long 0x00 "IPIPE_D2F_2ND_THR$1,Noise Filter 2 Register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," rbitfld.long 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--9. 1. "VAL,Threshold values in noise filter-2 algorithm" repeat.end repeat 2. (list 2. 1. )(list 0x00 0x04 ) group.long ($2+0xA4)++0x03 line.long 0x00 "IPIPE_LSC_HA$1," hexmask.long.word 0x00 16.--31. 1. "RESERVED," rbitfld.long 0x00 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 0.--12. 1. "VAL,LSC HA2" repeat.end repeat 2. (list 2. 1. )(list 0x00 0x04 ) group.long ($2+0x94)++0x03 line.long 0x00 "IPIPE_LSC_VA$1," hexmask.long.word 0x00 16.--31. 1. "RESERVED," rbitfld.long 0x00 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 0.--12. 1. "VAL,LSC VA2" repeat.end width 0x0B tree.end tree "ISP6P5_IPIPEIF" base ad:0x52041200 group.long 0x00++0xBB line.long 0x00 "IPIPEIF_ENABLE,IPIPEIF Enable" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "SYNCOFF,VD output mask This register masks the VD output to the IPIPE module" "SYNCOFF_0,SYNCOFF_1" bitfld.long 0x00 0. "ENABLE,IPIPE I/F Enable This register is used to start the operation of SDRAM buffer memory read and generates SYNC signals" "ENABLE_0,ENABLE_1" line.long 0x04 "IPIPEIF_CFG1,IPIPEIF Configuration #1" hexmask.long.word 0x04 16.--31. 1. "RESERVED," bitfld.long 0x04 14.--15. "INPSRC1,Selects the source for the mux (VPORT / ISIF / SDRAM) as well as the data format type" "INPSRC1_0,INPSRC1_1,INPSRC1_2,INPSRC1_3" bitfld.long 0x04 11.--13. "DATASFT,SDRAM read data shift This register is available when INPSRC1 or INPSRC2 = 1 or 2 i.e. when data are read from SDRAM" "DATASFT_0,DATASFT_1,DATASFT_2,DATASFT_3,DATASFT_4,DATASFT_5,DATASFT_6,DATASFT_7" bitfld.long 0x04 10. "CLKSEL,IPIPEIF IPIPE module pixel clock selection" "CLKSEL_0,CLKSEL_1" bitfld.long 0x04 8.--9. "UNPACK,8-Bit 12-bit Packed Mode When sensor raw data are stored in 8-bit packed mode or 12-bit packed mode this register should code 1 or 3" "UNPACK_0,UNPACK_1,UNPACK_2,UNPACK_3" newline bitfld.long 0x04 7. "AVGFILT,Averaging Filter It applies (1 2 1) filter for the RGB/YCbCr data" "AVGFILT_0,AVGFILT_1" rbitfld.long 0x04 5.--6. "RESERVED," "0,1,2,3" bitfld.long 0x04 4. "RAW16_SDRAM,RAW16/12 format of SDRAM This affect how DATASFT works" "0,1" bitfld.long 0x04 2.--3. "INPSRC2,Selects the source for the mux (ISIF / SDRAM) as well as the data format type" "INPSRC2_0,INPSRC2_1,INPSRC2_2,INPSRC2_3" bitfld.long 0x04 1. "DECIM,Pixel Decimation The decimation rate defined by RSZ register" "DECIM_0,DECIM_1" newline bitfld.long 0x04 0. "ONESHOT,One Shot Mode This register is available when INPSRC = 1 or 3" "ONESHOT_0,ONESHOT_1" line.long 0x08 "IPIPEIF_PPLN,IPIPEIF Interval of HD / Start pixel in HD" hexmask.long.word 0x08 16.--31. 1. "RESERVED," rbitfld.long 0x08 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--12. 1. "PPLN,Case-1: Interval of Horizontal Sync (HD) Specifies the interval of horizontal sync" line.long 0x0C "IPIPEIF_LPFR,IPIPEIF Interval of VD / Start line in VD" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," rbitfld.long 0x0C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 0.--12. 1. "LPFR,Case-1: Interval of Vertical Sync (VD) Specifies the interval of vertical sync" line.long 0x10 "IPIPEIF_HNUM,IPIPEIF Number of valid pixels per line" hexmask.long.word 0x10 16.--31. 1. "RESERVED," rbitfld.long 0x10 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--12. 1. "HNUM,The Number of Valid Pixels in a Line Specifies the number of valid pixels in a horizontal line" line.long 0x14 "IPIPEIF_VNUM,IPIPEIF Number of valid lines per frame" hexmask.long.tbyte 0x14 13.--31. 1. "RESERVED," hexmask.long.word 0x14 0.--12. 1. "VNUM,The Number of Valid Line in a Vertical Specifies the number of valid line in a vertical" line.long 0x18 "IPIPEIF_ADDRU,IPIPEIF Memory Address (Upper)" hexmask.long.tbyte 0x18 11.--31. 1. "RESERVED," hexmask.long.word 0x18 0.--10. 1. "ADDRU,Memory Address ? Upper Memory address upper 11-bits are specified in units of 32-bytes This register is available when INPSRC = 1 2 or 3" line.long 0x1C "IPIPEIF_ADDRL,IPIPEIF Memory Address (Lower)" hexmask.long.word 0x1C 16.--31. 1. "RESERVED," hexmask.long.word 0x1C 0.--15. 1. "ADDRL,Memory Address - Lower Memory address lower 16-bits are specified in units of 32-bytes" line.long 0x20 "IPIPEIF_ADOFS,IPIPEIF Address offset" hexmask.long.tbyte 0x20 12.--31. 1. "RESERVED," hexmask.long.word 0x20 0.--11. 1. "ADOFS,Specifies the SDRAM stride for each line in units of 32-bytes" line.long 0x24 "IPIPEIF_RSZ,IPIPEIF Horizontal Resizing Parameter on IPIPE datapath" hexmask.long 0x24 7.--31. 1. "RESERVED," hexmask.long.byte 0x24 0.--6. 1. "RSZ,Horizontal Resizing Parameter for IPIPE datapath Specifies the horizontal resizing parameter" line.long 0x28 "IPIPEIF_GAIN,IPIPEIF Gain Parameter" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED," hexmask.long.word 0x28 0.--9. 1. "GAIN,Gain Parameter Specifies the gain applied to RAW data before it is forwarded to the IPIPE module" line.long 0x2C "IPIPEIF_DPCM,IPIPEIF DPCM configuration This register applies only if.UNPACK = 1. i.e.. RAW8 data is read from SDRAM" hexmask.long 0x2C 3.--31. 1. "RESERVED," bitfld.long 0x2C 2. "BITS,DPCM bit mode for SDRAM data This register access is enabled by the Nokia Custom key" "BITS_0,BITS_1" bitfld.long 0x2C 1. "PRED,DPCM prediction mode for SDRAM data This register access is enabled by the Nokia Custom key" "PRED_0,PRED_1" bitfld.long 0x2C 0. "ENA,DPCM decompression enable for SDRAM data" "ENA_0,ENA_1" line.long 0x30 "IPIPEIF_CFG2,IPIPEIF Configuration #2" hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED," bitfld.long 0x30 7. "YUV8P,8-bit YUV data unpacking to 16 bits WhenIPIPEIF_CFG1.INPSRC2 = 0 and IPIPEIF_CFG2.YUV16 = 1 the 8-bit YUV data are transformed into 16-bit YUV data" "YUV8P_0,YUV8P_1" bitfld.long 0x30 6. "YUV8,YUV 8bit mode When ISIF_CFG1.INPSRC2 = 0 and YUV16 = 1 setting this bit to 1 enables the conversion from 8bit YUV input to 16bit YUV" "YUV8_0,YUV8_1" bitfld.long 0x30 5. "DFSDIR,DFS direction Selects the direction of dark frame subtraction" "DFSDIR_0,DFSDIR_1" bitfld.long 0x30 4. "WENE,External WEN signal selection Do not use for OMAP4 and MONICA since there is not parallel interface at chip level" "WENE_0,WENE_1" newline bitfld.long 0x30 3. "YUV16,Data type selection" "YUV16_0,YUV16_1" bitfld.long 0x30 2. "VDPOL,VD Sync Polarity When input VD is active low SYNC pulse this bit needs to be set to ?1?" "VDPOL_0,VDPOL_1" bitfld.long 0x30 1. "HDPOL,HD Sync Polarity When input HD is active low SYNC pulse this bit needs to be set to ?1?" "HDPOL_0,HDPOL_1" bitfld.long 0x30 0. "INTSW,IPIPEIF interrupt source selection" "INTSW_0,INTSW_1" line.long 0x34 "IPIPEIF_INIRSZ,IPIPEIF resize initial position - IPIPE data path" hexmask.long.tbyte 0x34 14.--31. 1. "RESERVED," bitfld.long 0x34 13. "ALNSYNC,Align the HSYNC VSYNC to initial position defined by INIRSZ" "ALNSYNC_0,ALNSYNC_1" hexmask.long.word 0x34 0.--12. 1. "INIRSZ,Offset used to re-initialize the HD/VD position after resizer" line.long 0x38 "IPIPEIF_OCLIP,IPIPEIF output clipping value" hexmask.long.word 0x38 16.--31. 1. "RESERVED," hexmask.long.word 0x38 0.--15. 1. "OCLIP,Output clipping value after gain control on IPIPE data path" line.long 0x3C "IPIPEIF_DTUDF,IPIPEIF data underflow detection" hexmask.long.word 0x3C 16.--31. 1. "RESERVED," hexmask.long.word 0x3C 6.--15. 1. "RESERVED," bitfld.long 0x3C 2.--5. "FIFOWMRKLVL,To guarantee that the FIFO does not overflow the stall request is deasserted only when a certain number of locations in the FIFO are free" "FIFOWMRKLVL_0,FIFOWMRKLVL_1,FIFOWMRKLVL_2,FIFOWMRKLVL_3,FIFOWMRKLVL_4,FIFOWMRKLVL_5,FIFOWMRKLVL_6,FIFOWMRKLVL_7,FIFOWMRKLVL_8,FIFOWMRKLVL_9,FIFOWMRKLVL_10,FIFOWMRKLVL_11,FIFOWMRKLVL_12,FIFOWMRKLVL_13,FIFOWMRKLVL_14,FIFOWMRKLVL_15" bitfld.long 0x3C 1. "ENM2MSTALL,Enable memory-to-memory stall mechanism" "ENM2MSTALL_0,ENM2MSTALL_1" bitfld.long 0x3C 0. "DTUDF,Data under flow error status register" "0,1" line.long 0x40 "IPIPEIF_CLKDIV,IPIPEIF CLOCK DIVIDER" hexmask.long.word 0x40 16.--31. 1. "RESERVED," hexmask.long.word 0x40 0.--15. 1. "CLKDIV,IPIPEIF clock rate configuration IPIPE/IPIPEIF clock frequency = M/N x clk_vpss clock frequency" line.long 0x44 "IPIPEIF_DPC1,IPIPEIF defect pixel correction #1" hexmask.long.word 0x44 16.--31. 1. "RESERVED," rbitfld.long 0x44 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x44 12. "ENA,DPC enable" "ENA_0,ENA_1" hexmask.long.word 0x44 0.--11. 1. "TH,DPC threshold value" line.long 0x48 "IPIPEIF_DPC2,IPIPEIF defect pixel correction #2" hexmask.long.tbyte 0x48 13.--31. 1. "RESERVED," bitfld.long 0x48 12. "ENA,DPC enable" "ENA_0,ENA_1" hexmask.long.word 0x48 0.--11. 1. "TH,DPC threshold value" line.long 0x4C "IPIPEIF_DFSGVL,IPIPEIF DARK FRAME GAIN CONTROL - GAIN VALUE" hexmask.long.tbyte 0x4C 11.--31. 1. "RESERVED," bitfld.long 0x4C 10. "DFSGEN,DFS gain control enable" "0,1" hexmask.long.word 0x4C 0.--9. 1. "DFSGVL,DFS gain value" line.long 0x50 "IPIPEIF_DFSGTH,IPIPEIF DARK FRAME GAIN CONTROL - THRESHOLD VALUE" hexmask.long.tbyte 0x50 12.--31. 1. "RESERVED," hexmask.long.word 0x50 0.--11. 1. "DFSGTH,DFS gain threshold value" line.long 0x54 "IPIPEIF_RSZ3A,IPIPEIF HORIZONTAL RESIZING PARAMETER FOR H3A" hexmask.long.word 0x54 16.--31. 1. "RESERVED," rbitfld.long 0x54 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x54 9. "DECIM,Pixel Decimation Enable The decimation rate defined by the RSZ bitfield" "DECIM_0,DECIM_1" bitfld.long 0x54 8. "AVGFILT,Averaging Filter It applies a (1 2 1) filter for the RGB/YCbCr data" "AVGFILT_0,AVGFILT_1" rbitfld.long 0x54 7. "RESERVED," "0,1" newline hexmask.long.byte 0x54 0.--6. 1. "RSZ,Horizontal Resizing Parameter for H3A datapath Specifies the horizontal resizing parameter" line.long 0x58 "IPIPEIF_INIRSZ3A,IPIPEIF resize initial position - H3A data path" hexmask.long.tbyte 0x58 14.--31. 1. "RESERVED," bitfld.long 0x58 13. "ALNSYNC,Align the HD VD to initial position defined by the INIRSZ bit field" "ALNSYNC_0,ALNSYNC_1" hexmask.long.word 0x58 0.--12. 1. "INIRSZ,Offset used to re-initialize the HD/VD position after resizer" line.long 0x5C "IPIPEIF_CFG3,Parameters for Circular buffering" rbitfld.long 0x5C 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x5C 29. "HSK_EOF,Issue C_DONE at the end of frame" "HSK_EOF_0,HSK_EOF_1" bitfld.long 0x5C 28. "HSK_EN,Handshake with ICM is enabled Note: If ICM handshake is on in DFS/WDR mode (INPSRC1=2 or INPSRC2=2) memory-to-memory stall mechanism must be on (IPIPEIF_DTUDF.ENM2MSTALL=1) *This bit field is latched by VD" "HSK_EN_0,HSK_EN_1" hexmask.long.word 0x5C 16.--27. 1. "CYN,ICM Handshake cycle U12 *This bit field is latched by VD" rbitfld.long 0x5C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x5C 12. "CIR_EN,Enable circular buffering *This bit field is latched by VD" "CIR_EN_0,CIR_EN_1" hexmask.long.word 0x5C 0.--11. 1. "CBN,Circular buffer cycle U12 *This bit field is latched by VD" line.long 0x60 "IPIPEIF_CFG4,IPIPEIF WDR configuration for WDR merging" hexmask.long.word 0x60 21.--31. 1. "RESERVED," bitfld.long 0x60 16.--20. "DST,Down shift value after WDR merge *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x60 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x60 8.--11. "SBIT,Shift up value for short exposure pixel Usually set (16- (bit width of long exposure pixels))" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x60 4.--7. "LBIT,Shift up value for long exposure pixel Usually set (16- (bit width of long exposure pixels))" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x60 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x60 1. "WGT_SEL,Select the source for weight calculation in WDR merge *This bit field is latched by VD" "WGT_SEL_0,WGT_SEL_1" bitfld.long 0x60 0. "WDR_EN,Enable WDR merge (Two frame/single frame) When this function is enabled WDR is used instead of DFS" "WDR_EN_0,WDR_EN_1" line.long 0x64 "IPIPEIF_WDRAF,WDR Merge parameter AF_M" hexmask.long.byte 0x64 25.--31. 1. "RESERVED," bitfld.long 0x64 20.--24. "AFE,WDR Merge parameter AFE Exponential part of a value in weight calculation Unsigned 5bit *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x64 16.--19. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x64 0.--15. 1. "AFM,WDR Merge parameter AF_M Coefficient (mantissa) part of a value in weight calculation Signed 16bit *This bit field is latched by VD" line.long 0x68 "IPIPEIF_WDRBF,WDR Merge parameter BF" hexmask.long.word 0x68 16.--31. 1. "RESERVED," hexmask.long.word 0x68 0.--15. 1. "BF,WDR Merge parameter BF Q0.15) The actual value is BF x 2^-16 x 2^-5 *This bit field is latched by VD" line.long 0x6C "IPIPEIF_WDRGAIN,Gain difference between long exposure and short exposure" hexmask.long.word 0x6C 16.--31. 1. "GSHORT,The gain applied to short exposure pixels" hexmask.long.word 0x6C 0.--15. 1. "GLONG,The gain applied to long exposure pixels" line.long 0x70 "IPIPEIF_WDRTHR,Threshold value in WDR merging" hexmask.long.word 0x70 16.--31. 1. "RESERVED," hexmask.long.word 0x70 0.--15. 1. "THR,T (Threshold value) U16 *This bit field is latched by VD" line.long 0x74 "IPIPEIF_RSVD1,White Balance used in weight calculation" line.long 0x78 "IPIPEIF_RSVD2," line.long 0x7C "IPIPEIF_WDRLBK1,Black level for Long exposure input" rbitfld.long 0x7C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x7C 16.--27. 1. "LBK01,Black level for long exposure pixel at [0 1] (Odd pixel at even line) U12 *This bit field is latched by VD" rbitfld.long 0x7C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x7C 0.--11. 1. "LBK00,Black level for long exposure pixel at [0 0] (Even pixel at even line) U12 *This bit field is latched by VD" line.long 0x80 "IPIPEIF_WDRLBK2,Black level for Long exposure input" rbitfld.long 0x80 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x80 16.--27. 1. "LBK11,Black level for long exposure pixel at [1 1] (Odd pixel at odd line) U12 *This bit field is latched by VD" rbitfld.long 0x80 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x80 0.--11. 1. "LBK10,1lack level for long exposure pixel at [1 0 ] (Even pixel at odd line) U12 *This bit field is latched by VD" line.long 0x84 "IPIPEIF_WDRSBK1,Black level for short exposure input" rbitfld.long 0x84 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x84 16.--27. 1. "SBK01,Black level for short exposure pixel at [0 1] (Odd pixel at even line) U12 *This bit field is latched by VD" rbitfld.long 0x84 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x84 0.--11. 1. "SBK00,Black level for short exposure pixel at [0 0] (Even pixel at even line) U12 *This bit field is latched by VD" line.long 0x88 "IPIPEIF_WDRSBK2,Black level for short exposure input" rbitfld.long 0x88 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x88 16.--27. 1. "SBK11,Black level for short exposure pixel at [1 1] (Odd pixel at odd line) U12 *This bit field is latched by VD" rbitfld.long 0x88 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x88 0.--11. 1. "SBK10,1lack level for short exposure pixel at [1 0 ] (Even pixel at odd line) U12 *This bit field is latched by VD" line.long 0x8C "IPIPEIF_WDRMA,Threshold value in motion adaptive filter" hexmask.long.word 0x8C 16.--31. 1. "MAS,Slope in motion adaptive filter MAS = 32768/(D2-D1) U16 *This bit field is latched by VD" hexmask.long.word 0x8C 0.--15. 1. "MAD,Threshold (D1) in motion adaptive filter U16 To disable MA filtering put the maximum value (65535: default) *This bit field is latched by VD" line.long 0x90 "IPIPEIF_WDRSAT_VP,Saturation parameters for VPORT input" hexmask.long.word 0x90 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x90 0.--19. 1. "VP_SAT,Saturation value for VPORT input used in WDR split function for pseudo-long-exposure image Do disable set maximum value (1048575: default) *This bit field is latched by VD" line.long 0x94 "IPIPEIF_WDRSAT_VP2,Saturation parameters for VPORT input" hexmask.long.word 0x94 16.--31. 1. "RESERVED," hexmask.long.byte 0x94 8.--15. 1. "VP_DCCLMP,DC Clamp addition value for VPORT input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD" bitfld.long 0x94 3.--7. "VP_DSF,Down shift value for VPORT input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x94 1.--2. "RESERVED," "0,1,2,3" bitfld.long 0x94 0. "VP_SATEN,Enable saturation function on VPort *This bit field is latched by VD" "VP_SATEN_0,VP_SATEN_1" line.long 0x98 "IPIPEIF_WDRSAT_ISIF,Saturation parameters for ISIF input" hexmask.long.word 0x98 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x98 0.--19. 1. "ISIF_SAT,Saturation value for ISIF input used in WDR split function for pseudo-long-exposure image Do disable set maximum value (1048575: default) *This bit field is latched by VD" line.long 0x9C "IPIPEIF_WDRSAT_ISIF2,Saturation value for ISIF input" hexmask.long.word 0x9C 16.--31. 1. "RESERVED," hexmask.long.byte 0x9C 8.--15. 1. "ISIF_DCCLMP,DC Clamp addition value for ISIF input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD" bitfld.long 0x9C 3.--7. "ISIF_DSF,Down shift value for ISIF input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x9C 1.--2. "RESERVED," "0,1,2,3" bitfld.long 0x9C 0. "ISIF_SATEN,Enable saturation function on ISIF port *This bit field is latched by VD" "ISIF_SATEN_0,ISIF_SATEN_1" line.long 0xA0 "IPIPEIF_WDRSAT_SD,Saturation parameters for SDRAM input" hexmask.long.word 0xA0 20.--31. 1. "RESERVED," hexmask.long.tbyte 0xA0 0.--19. 1. "SD_SAT,Saturation value for SDRAM input used in WDR split function for pseudo-long-exposure image Do disable set maximum value (1048575: default) *This bit field is latched by VD" line.long 0xA4 "IPIPEIF_WDRSAT_SD2,Saturation params for SDRAM input" hexmask.long.word 0xA4 16.--31. 1. "RESERVED," hexmask.long.byte 0xA4 8.--15. 1. "SD_DCCLMP,DC Clamp addition value for SD Port input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD" bitfld.long 0xA4 3.--7. "SD_DSF,Down shift value for SDRAM input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0xA4 1.--2. "RESERVED," "0,1,2,3" bitfld.long 0xA4 0. "SD_SATEN,Enable saturation function on SDRAM *This bit field is latched by VD" "SD_SATEN_0,SD_SATEN_1" line.long 0xA8 "IPIPEIF_WDRLWB1,White Balance used in weight calculation" rbitfld.long 0xA8 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0xA8 16.--28. 1. "LWB01,White balance for pixels at [0 1] (Odd pixel at even line) U4.9 (for gain=1.0 set 512) *This bit field is latched by VD" rbitfld.long 0xA8 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0xA8 0.--12. 1. "LWB00,White balance for pixels at [0 0] (Even pixel at even line) U4.9 (for gain=1.0 set 512) *This bit field is latched by VD" line.long 0xAC "IPIPEIF_WDRLWB2,White Balance used in weight calculation" rbitfld.long 0xAC 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0xAC 16.--28. 1. "LWB11,White balance for pixels at [0 1] (Odd pixel at odd line) U4.9 (for gain=1.0 set 512) *This bit field is latched by VD" rbitfld.long 0xAC 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0xAC 0.--12. 1. "LWB10,White balance for pixels at [1 0] (Even pixel at odd line) U4.9 (for gain=1.0 set 512) *This bit field is latched by VD" line.long 0xB0 "IPIPEIF_WDRSWB1,White Balance used in weight calculation" rbitfld.long 0xB0 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0xB0 16.--28. 1. "SWB01,White balance for pixels at [0 1] (Odd pixel at even line) U4.9 (for gain=1.0 set 512) *This bit field is latched by VD" rbitfld.long 0xB0 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0xB0 0.--12. 1. "SWB00,White balance for pixels at [0 0] (Even pixel at even line) U4.9 (for gain=1.0 set 512) *This bit field is latched by VD" line.long 0xB4 "IPIPEIF_WDRSWB2,White Balance used in weight calculation" rbitfld.long 0xB4 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0xB4 16.--28. 1. "SWB11,White balance for pixels at [0 1] (Odd pixel at odd line) U4.9 (for gain=1.0 set 512) *This bit field is latched by VD" rbitfld.long 0xB4 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0xB4 0.--12. 1. "SWB10,White balance for pixels at [1 0] (Even pixel at odd line) U4.9 (for gain=1.0 set 512) *This bit field is latched by VD" line.long 0xB8 "IPIPEIF_VPDCMPXTHR1,Threshold value in VP Decomanding" hexmask.long.word 0xB8 16.--31. 1. "RESERVED," hexmask.long.word 0xB8 0.--15. 1. "XTHR1,X_THR_1 (Threshold value) U16 *This bit field is latched by VD" group.long 0xC4++0x23 line.long 0x00 "IPIPEIF_VPDCMPYTHR1,Threshold value in VP Decomanding" hexmask.long.word 0x00 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--19. 1. "YTHR1,Y_THR_1 (Threshold value) U20 *This bit field is latched by VD" line.long 0x04 "IPIPEIF_VPDCMPYTHR2,Threshold value in VP Decomanding" hexmask.long.word 0x04 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x04 0.--19. 1. "YTHR2,Y_THR_2 (Threshold value) U20 *This bit field is latched by VD" line.long 0x08 "IPIPEIF_VPDCMPYTHR3,Threshold value in VP Decomanding" hexmask.long.word 0x08 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x08 0.--19. 1. "YTHR3,Y_THR_3 (Threshold value) U20 *This bit field is latched by VD" line.long 0x0C "IPIPEIF_VPDCMPSLOPE1,Slope value in VP Decomanding" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," hexmask.long.word 0x0C 0.--15. 1. "SLOPE1,SLOPE_1 (Slope value) U16 *This bit field is latched by VD" line.long 0x10 "IPIPEIF_VPDCMPSLOPE2,Slope value in VP Decomanding" hexmask.long.word 0x10 16.--31. 1. "RESERVED," hexmask.long.word 0x10 0.--15. 1. "SLOPE2,SLOPE_2 (Slope value) U16 *This bit field is latched by VD" line.long 0x14 "IPIPEIF_VPDCMPSLOPE3,Slope value in VP Decomanding" hexmask.long.word 0x14 16.--31. 1. "RESERVED," hexmask.long.word 0x14 0.--15. 1. "SLOPE3,SLOPE_3 (Slope value) U16 *This bit field is latched by VD" line.long 0x18 "IPIPEIF_VPDCMPSLOPE4,Slope value in VP Decomanding" hexmask.long.word 0x18 16.--31. 1. "RESERVED," hexmask.long.word 0x18 0.--15. 1. "SLOPE4,SLOPE_4 (Slope value) U16 *This bit field is latched by VD" line.long 0x1C "IPIPEIF_VPDCMPCFG,Configuration register for VP Decomanding" rbitfld.long 0x1C 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--28. "SHIFT,Shift value for PWL U5 *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x1C 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. "LUTBITSEL,LUTBITSEL (For selecting address to LUT) U4 *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 2.--15. 1. "RESERVED," newline bitfld.long 0x1C 1. "LUTSET,Select Bit '0' : Choose PWL '1' : Choose LUT *This bit field is latched by VD" "0,1" bitfld.long 0x1C 0. "ENABLE,Enable for VP Decompanding *This bit field is latched by VD" "0,1" line.long 0x20 "IPIPEIF_SDDCMPXTHR1,Threshold value in SD Decomanding" hexmask.long.word 0x20 16.--31. 1. "RESERVED," hexmask.long.word 0x20 0.--15. 1. "XTHR1,X_THR_1 (Threshold value) U16 *This bit field is latched by VD" group.long 0xF0++0x37 line.long 0x00 "IPIPEIF_SDDCMPYTHR1,Threshold value in SD Decomanding" hexmask.long.word 0x00 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--19. 1. "YTHR1,Y_THR_1 (Threshold value) U20 *This bit field is latched by VD" line.long 0x04 "IPIPEIF_SDDCMPYTHR2,Threshold value in SD Decomanding" hexmask.long.word 0x04 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x04 0.--19. 1. "YTHR2,Y_THR_2 (Threshold value) U20 *This bit field is latched by VD" line.long 0x08 "IPIPEIF_SDDCMPYTHR3,Threshold value in SD Decomanding" hexmask.long.word 0x08 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x08 0.--19. 1. "YTHR3,Y_THR_3 (Threshold value) U20 *This bit field is latched by VD" line.long 0x0C "IPIPEIF_SDDCMPSLOPE1,Slope value in SD Decomanding" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," hexmask.long.word 0x0C 0.--15. 1. "SLOPE1,SLOPE_1 (Slope value) U16 *This bit field is latched by VD" line.long 0x10 "IPIPEIF_SDDCMPSLOPE2,Slope value in SD Decomanding" hexmask.long.word 0x10 16.--31. 1. "RESERVED," hexmask.long.word 0x10 0.--15. 1. "SLOPE2,SLOPE_2 (Slope value) U16 *This bit field is latched by VD" line.long 0x14 "IPIPEIF_SDDCMPSLOPE3,Slope value in SD Decomanding" hexmask.long.word 0x14 16.--31. 1. "RESERVED," hexmask.long.word 0x14 0.--15. 1. "SLOPE3,SLOPE_3 (Slope value) U16 *This bit field is latched by VD" line.long 0x18 "IPIPEIF_SDDCMPSLOPE4,Slope value in SD Decomanding" hexmask.long.word 0x18 16.--31. 1. "RESERVED," hexmask.long.word 0x18 0.--15. 1. "SLOPE4,SLOPE_4 (Slope value) U16 *This bit field is latched by VD" line.long 0x1C "IPIPEIF_SDDCMPCFG,Configuration register for SD Decomanding" rbitfld.long 0x1C 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--28. "SHIFT,Shift value for PWL U5 *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x1C 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. "LUTBITSEL,LUTBITSEL (For selecting address to LUT) U4 *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 2.--15. 1. "RESERVED," newline bitfld.long 0x1C 1. "LUTSET,Select Bit '0' : Choose PWL '1' : Choose LUT *This bit field is latched by VD" "0,1" bitfld.long 0x1C 0. "ENABLE,Enable for VP Decompanding *This bit field is latched by VD" "0,1" line.long 0x20 "IPIPEIF_WDRCMPXTHR1,Threshold value in SD WDR Companding" hexmask.long.word 0x20 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x20 0.--19. 1. "XTHR1,X_THR_1 (Threshold value) U16 *This bit field is latched by VD" line.long 0x24 "IPIPEIF_WDRCMPXTHR2,Threshold value in WDR Companding" hexmask.long.word 0x24 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x24 0.--19. 1. "XTHR2,X_THR_2 (Threshold value) U16 *This bit field is latched by VD" line.long 0x28 "IPIPEIF_WDRCMPXTHR3,Threshold value in WDR Decompanding" hexmask.long.word 0x28 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x28 0.--19. 1. "XTHR3,X_THR_2 (Threshold value) U16 *This bit field is latched by VD" line.long 0x2C "IPIPEIF_WDRCMPYTHR1,Threshold value in WDR Companding" hexmask.long.word 0x2C 16.--31. 1. "RESERVED," hexmask.long.word 0x2C 0.--15. 1. "YTHR1,Y_THR_1 (Threshold value) U20 *This bit field is latched by VD" line.long 0x30 "IPIPEIF_WDRCMPYTHR2,Threshold value in WDR Decompanding" hexmask.long.word 0x30 16.--31. 1. "RESERVED," hexmask.long.word 0x30 0.--15. 1. "YTHR2,Y_THR_2 (Threshold value) U20 *This bit field is latched by VD" line.long 0x34 "IPIPEIF_WDRCMPYTHR3,Threshold value in WDR Companding" hexmask.long.word 0x34 16.--31. 1. "RESERVED," hexmask.long.word 0x34 0.--15. 1. "YTHR3,Y_THR_3 (Threshold value) U20 *This bit field is latched by VD" group.long 0x138++0x07 line.long 0x00 "IPIPEIF_WDRCMPCFG,Configuration register for WDR Decompanding" rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--28. "SHIFT,Shift value for PWL U5 *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "LUTBITSEL,LUTBITSEL (For selecting address to LUT) U4 *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 1. "LUTSET,Select Bit '0' : Choose PWL '1' : Choose LUT *This bit field is latched by VD" "0,1" bitfld.long 0x00 0. "ENABLE,Enable for VP Decompanding *This bit field is latched by VD" "0,1" line.long 0x04 "IPIPEIF_WDRMRGCFG,Configuration register for WDR Merge" rbitfld.long 0x04 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. "MRGWTSFT,Shift value for Weight black U3 *This bit field is latched by VD" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x04 0.--19. 1. "WDRCLIP,Clip value after WDR Merge *This bit field is latched by VD" repeat 4. (list 1. 2. 3. 4. )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x128)++0x03 line.long 0x00 "IPIPEIF_WDRCMPSLOPE$1,Slope value in WDR Decompanding" hexmask.long.word 0x00 16.--31. 1. "RESERVED," hexmask.long.word 0x00 0.--15. 1. "SLOPE1,SLOPE_1 (Slope value) U16 *This bit field is latched by VD" repeat.end repeat 2. (list 2. 3. )(list 0x00 0x04 ) group.long ($2+0xE8)++0x03 line.long 0x00 "IPIPEIF_SDDCMPXTHR$1,Threshold value in SD Decompanding" hexmask.long.word 0x00 16.--31. 1. "RESERVED," hexmask.long.word 0x00 0.--15. 1. "XTHR2,X_THR_2 (Threshold value) U16 *This bit field is latched by VD" repeat.end repeat 2. (list 2. 3. )(list 0x00 0x04 ) group.long ($2+0xBC)++0x03 line.long 0x00 "IPIPEIF_VPDCMPXTHR$1,Threshold value in VP Decompanding" hexmask.long.word 0x00 16.--31. 1. "RESERVED," hexmask.long.word 0x00 0.--15. 1. "XTHR2,X_THR_2 (Threshold value) U16 *This bit field is latched by VD" repeat.end width 0x0B tree.end tree "ISP6P5_ISIF" base ad:0x52041000 group.long 0x00++0x1C7 line.long 0x00 "ISIF_SYNCEN," hexmask.long.word 0x00 16.--31. 1. "RESERVED," hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 1. "DWEN,Controls the storage of image sensor RAW data in memory" "DWEN_0,DWEN_1" bitfld.long 0x00 0. "SYEN,Controls ON/OFF of VD/HD output" "SYEN_0,SYEN_1" line.long 0x04 "ISIF_MODESET," hexmask.long.word 0x04 16.--31. 1. "RESERVED," rbitfld.long 0x04 15. "MDFS,Field Status This bit indicates the status of the current FLD signal when the ISIF module is in interlaced mode" "MDFS_0,MDFS_1" newline bitfld.long 0x04 14. "HLPF,Low pass filter enable" "HLPF_0,HLPF_1" bitfld.long 0x04 12.--13. "INPMOD,Data input mode" "INPMOD_0,INPMOD_1,INPMOD_2,INPMOD_3" newline bitfld.long 0x04 11. "OVF,ISIF module write port overflow status bit If the write port of the ISIF module overflows when writing data to SDRAM this bit will toggle" "OVF_0,OVF_1" bitfld.long 0x04 8.--10. "CCDW,This bit enables to shift right (divide) the up-to-12-bit RAW data value when writing out to SDRAM" "CCDW_0,CCDW_1,CCDW_2,CCDW_3,CCDW_4,CCDW_5,CCDW_6,CCDW_7" newline bitfld.long 0x04 7. "CCDMD,Field mode: This bit selects the type of image sensor: interlaced or progressive" "CCDMD_0,CCDMD_1" bitfld.long 0x04 6. "DPOL,Image sensor input data polarity" "DPOL_0,DPOL_1" newline bitfld.long 0x04 5. "SWEN,External WEN selection In case this bit and SYNCEN.DWEN are set to 1 the external WEN signal is used to store image sensor data to memory" "SWEN_0,SWEN_1" bitfld.long 0x04 4. "FIPOL,FLD Signal Polarity" "FIPOL_0,FIPOL_1" newline bitfld.long 0x04 3. "HDPOL,HD Sync Signal Polarity" "HDPOL_0,HDPOL_1" bitfld.long 0x04 2. "VDPOL,VD Sync Signal Polarity" "VDPOL_0,VDPOL_1" newline bitfld.long 0x04 1. "FIDD,FLD Signal Direction There shall be at least three clock cycles between the time this bit is modified and the HD/VD pulse for start of frame comes" "FIDD_0,FIDD_1" bitfld.long 0x04 0. "HDVDD,VD HD Sync Signal Direction There shall be at least three clock cycles between the time this bit is modified and the HD/VD pulse for start of frame comes" "HDVDD_0,HDVDD_1" line.long 0x08 "ISIF_HDW," hexmask.long.word 0x08 16.--31. 1. "RESERVED," rbitfld.long 0x08 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 0.--11. 1. "HDW,HD width: Sets width of HD" line.long 0x0C "ISIF_VDW," hexmask.long.word 0x0C 16.--31. 1. "RESERVED," rbitfld.long 0x0C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 0.--11. 1. "VDW,VD width : Sets width of VD" line.long 0x10 "ISIF_PPLN," hexmask.long.word 0x10 16.--31. 1. "RESERVED," hexmask.long.word 0x10 0.--15. 1. "PPLN,Pixels per line Number of pixel clock periods in one line HD period = PPLN+1 pixel clocks" line.long 0x14 "ISIF_LPFR,Line per Frame/Field" hexmask.long.word 0x14 16.--31. 1. "RESERVED," hexmask.long.word 0x14 0.--15. 1. "LPFR,Half lines per filed or frame Sets number of half lines per frame or field" line.long 0x18 "ISIF_SPH,Start Pixel Horizontal" hexmask.long.word 0x18 16.--31. 1. "RESERVED," rbitfld.long 0x18 15. "RESERVED," "0,1" newline hexmask.long.word 0x18 0.--14. 1. "SPH,The first pixel in a line to be stored to memory" line.long 0x1C "ISIF_LNH," hexmask.long.word 0x1C 16.--31. 1. "RESERVED," rbitfld.long 0x1C 15. "RESERVED," "0,1" newline hexmask.long.word 0x1C 0.--14. 1. "LNH,Number of pixels in an line to be stored to memory" line.long 0x20 "ISIF_SLV0," hexmask.long.word 0x20 16.--31. 1. "RESERVED," rbitfld.long 0x20 15. "RESERVED," "0,1" newline hexmask.long.word 0x20 0.--14. 1. "SLV0,Start Line Vertical (Field 0) Sets line at which data output to SDRAM will begin measured from the start of VD *This bit field is latched by VD" line.long 0x24 "ISIF_SLV1," hexmask.long.word 0x24 16.--31. 1. "RESERVED," rbitfld.long 0x24 15. "RESERVED," "0,1" newline hexmask.long.word 0x24 0.--14. 1. "SLV1,Start Line Vertical (Field 1) Sets line at which data output to SDRAM will begin measured from the start of VD *This bit field is latched by VD" line.long 0x28 "ISIF_LNV," hexmask.long.word 0x28 16.--31. 1. "RESERVED," rbitfld.long 0x28 15. "RESERVED,The number of lines to be stored to SDRAM" "0,1" newline hexmask.long.word 0x28 0.--14. 1. "LNV,The number of lines to be stored to memory" line.long 0x2C "ISIF_CULH,This register specifies horizontal culling" hexmask.long.word 0x2C 16.--31. 1. "RESERVED," hexmask.long.byte 0x2C 8.--15. 1. "CLHE,Culling Pattern in EVEN Line: Sets culling pattern when data is loaded into memory (even lines)" newline hexmask.long.byte 0x2C 0.--7. 1. "CLHO,Culling Pattern in ODD Line: Sets culling pattern when data is loaded into memory (odd lines)" line.long 0x30 "ISIF_CULV," hexmask.long.word 0x30 16.--31. 1. "RESERVED," hexmask.long.byte 0x30 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x30 0.--7. 1. "CULV,Culling Pattern in Vertical Line Note: CULV[0] must be 1 for proper operation" line.long 0x34 "ISIF_HSIZE,SDRAM OUTPUT CTRL REGISTER" hexmask.long.word 0x34 16.--31. 1. "RESERVED," rbitfld.long 0x34 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 12. "ADCR,SDRAM address decrement" "ADCR_0,ADCR_1" hexmask.long.word 0x34 0.--11. 1. "HSIZE,Memory address offset between the lines" line.long 0x38 "ISIF_SDOFST,SDRAM OUTPUT CTRL REGISTER" hexmask.long.word 0x38 16.--31. 1. "RESERVED," rbitfld.long 0x38 15. "RESERVED," "0,1" newline bitfld.long 0x38 14. "FIINV,FID polarity: This bit inverse a FID polarity" "FIINV_0,FIINV_1" bitfld.long 0x38 12.--13. "FOFST,Field line offset value in odd (FID = 1) field" "FOFST_0,FOFST_1,FOFST_2,FOFST_3" newline bitfld.long 0x38 9.--11. "LOFSTEE,Field line offset value applied after even line even field (This value affects the first address of odd lines)" "LOFSTEE_0,LOFSTEE_1,LOFSTEE_2,LOFSTEE_3,LOFSTEE_4,LOFSTEE_5,LOFSTEE_6,LOFSTEE_7" bitfld.long 0x38 6.--8. "LOFSTOE,Field line offset value applied after odd line even field (This value affects the even lines)" "LOFSTOE_0,LOFSTOE_1,LOFSTOE_2,LOFSTOE_3,LOFSTOE_4,LOFSTOE_5,LOFSTOE_6,LOFSTOE_7" newline bitfld.long 0x38 3.--5. "LOFSTEO,Field line offset value applied after even line odd field (This value affects the first address of off lines)" "LOFSTEO_0,LOFSTEO_1,LOFSTEO_2,LOFSTEO_3,LOFSTEO_4,LOFSTEO_5,LOFSTEO_6,LOFSTEO_7" bitfld.long 0x38 0.--2. "LOFSTOO,Field line offset value applied after odd line odd field (This value affects the first address of even lines)" "LOFSTOO_0,LOFSTOO_1,LOFSTOO_2,LOFSTOO_3,LOFSTOO_4,LOFSTOO_5,LOFSTOO_6,LOFSTOO_7" line.long 0x3C "ISIF_CADU,SDRAM OUTPUT CTRL REGISTER" hexmask.long.word 0x3C 16.--31. 1. "RESERVED," rbitfld.long 0x3C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x3C 0.--10. 1. "CADU,Memory Address (Upper" line.long 0x40 "ISIF_CADL,SDRAM OUTPUT CTRL REGISTER" hexmask.long.word 0x40 16.--31. 1. "RESERVED," hexmask.long.word 0x40 0.--15. 1. "CADL,Memory Address (Lower" line.long 0x44 "ISIF_LINCFG0,INPUT LINEARIZATION CTRL REGISTER" hexmask.long.word 0x44 16.--31. 1. "RESERVED," hexmask.long.word 0x44 7.--15. 1. "RESERVED," newline bitfld.long 0x44 4.--6. "CORRSFT,Shift up value for the correction value (S10)" "CORRSFT_0,CORRSFT_1,CORRSFT_2,CORRSFT_3,CORRSFT_4,CORRSFT_5,CORRSFT_6,CORRSFT_7" rbitfld.long 0x44 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x44 1. "LINMD,Linearization Mode" "LINMD_0,LINMD_1" bitfld.long 0x44 0. "LINEN,Linearization Enable" "LINEN_0,LINEN_1" line.long 0x48 "ISIF_LINCFG1,INPUT LINEARIZATION CTRL REGISTER" hexmask.long.word 0x48 16.--31. 1. "RESERVED," rbitfld.long 0x48 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 0.--10. 1. "LUTSCL,Scale factor (U11Q10) for LUT input" line.long 0x4C "ISIF_CCOLP," hexmask.long.word 0x4C 16.--31. 1. "RESERVED," bitfld.long 0x4C 14.--15. "CP0_F1,Specifies color pattern for pixel position 0 (Field 1) Pixel position 0 corresponds to pixel count=0 at even line in case of CFAP=?0? and to pixel count=0 in case of CFAP=?1?" "CP0_F1_0,CP0_F1_1,CP0_F1_2,CP0_F1_3" newline bitfld.long 0x4C 12.--13. "CP1_F1,Specifies color pattern for pixel position 1 (Field 1) Pixel position 1 corresponds to pixel count=1 at even line in case of CFAP=?0? and to pixel count=1 in case of CFAP=?1?" "CP1_F1_0,CP1_F1_1,CP1_F1_2,CP1_F1_3" bitfld.long 0x4C 10.--11. "CP2_F1,Specifies color pattern for pixel position 2 (Field 1) Pixel position 2 corresponds to pixel count=0 at odd line in case of CFAP=?0? and to pixel count=2 in case of CFAP=?1?" "CP2_F1_0,CP2_F1_1,CP2_F1_2,CP2_F1_3" newline bitfld.long 0x4C 8.--9. "CP3_F1,Specifies color pattern for pixel position 3 (Field 1) Pixel position 3 corresponds to pixel count=1 at odd line in case of CFAP=?0?" "CP3_F1_0,CP3_F1_1,CP3_F1_2,CP3_F1_3" bitfld.long 0x4C 6.--7. "CP0_F0,Specifies color pattern for pixel position 0 (Field 0) Pixel position 0 corresponds to pixel count=0 at even line in case of CFAP=?0? and to pixel count=0 in case of CFAP=?1?" "CP0_F0_0,CP0_F0_1,CP0_F0_2,CP0_F0_3" newline bitfld.long 0x4C 4.--5. "CP1_F0,Specifies color pattern for pixel position 1 (Field 0) Pixel position 1 corresponds to pixel count=1 at even line in case of CFAP=?0? and to pixel count=1 in case of CFAP=?1?" "CP1_F0_0,CP1_F0_1,CP1_F0_2,CP1_F0_3" bitfld.long 0x4C 2.--3. "CP2_F0,Specifies color pattern for pixel position 2 (Field 0) Pixel position 2 corresponds to pixel count=0 at odd line in case of CFAP=?0? and to pixel count=2 in case of CFAP=?1?" "CP2_F0_0,CP2_F0_1,CP2_F0_2,CP2_F0_3" newline bitfld.long 0x4C 0.--1. "CP3_F0,Specifies color pattern for pixel position 3 (Field 0) Pixel position 3 corresponds to pixel count=1 at odd line in case of CFAP=?0?" "CP3_F0_0,CP3_F0_1,CP3_F0_2,CP3_F0_3" line.long 0x50 "ISIF_CRGAIN," hexmask.long.word 0x50 16.--31. 1. "RESERVED," rbitfld.long 0x50 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x50 0.--11. 1. "CGR,R/Ye gain: Performs gain adjustment on image sensor data" line.long 0x54 "ISIF_CGRGAIN," hexmask.long.word 0x54 16.--31. 1. "RESERVED," rbitfld.long 0x54 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x54 0.--11. 1. "CGGR,Gr/Cy gain: Performs gain adjustment on image sensor data" line.long 0x58 "ISIF_CGBGAIN," hexmask.long.word 0x58 16.--31. 1. "RESERVED," rbitfld.long 0x58 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x58 0.--11. 1. "CGGB,Gb/Cy gain: Performs gain adjustment on image sensor data" line.long 0x5C "ISIF_CBGAIN," hexmask.long.word 0x5C 16.--31. 1. "RESERVED," rbitfld.long 0x5C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x5C 0.--11. 1. "CGB,B/Mg gain: Performs gain adjustment on image sensor data" line.long 0x60 "ISIF_COFSTA," hexmask.long.word 0x60 16.--31. 1. "RESERVED," rbitfld.long 0x60 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x60 0.--11. 1. "COFT,Image sensor offset: Performs offset value adjustment on image sensor data (0~4095)" line.long 0x64 "ISIF_FLSHCFG0,Not used in MONICA and OMAP4" hexmask.long.word 0x64 16.--31. 1. "RESERVED," hexmask.long.word 0x64 1.--15. 1. "RESERVED," newline bitfld.long 0x64 0. "FLSHEN,Flash timing signal enable This bit is automatically cleared to '0' at VD timing" "FLSHEN_0,FLSHEN_1" line.long 0x68 "ISIF_FLSHCFG1,Not used in MONICA and OMAP4" hexmask.long.word 0x68 16.--31. 1. "RESERVED," rbitfld.long 0x68 15. "RESERVED," "0,1" newline hexmask.long.word 0x68 0.--14. 1. "SFLSH,Start line to set the FLASH timing signal" line.long 0x6C "ISIF_FLSHCFG2,Not used in MONICA and OMAP4" hexmask.long.word 0x6C 16.--31. 1. "RESERVED," hexmask.long.word 0x6C 0.--15. 1. "VFLSH,Valid width of the FLASH timing signal" line.long 0x70 "ISIF_VDINT0," hexmask.long.word 0x70 16.--31. 1. "RESERVED," rbitfld.long 0x70 15. "RESERVED," "0,1" newline hexmask.long.word 0x70 0.--14. 1. "CVD0,VD0 Interrupt timing in a field (line number)" line.long 0x74 "ISIF_VDINT1," hexmask.long.word 0x74 16.--31. 1. "RESERVED," rbitfld.long 0x74 15. "RESERVED," "0,1" newline hexmask.long.word 0x74 0.--14. 1. "CVD1,VD1 Interrupt timing in a field (line number)" line.long 0x78 "ISIF_VDINT2," hexmask.long.word 0x78 16.--31. 1. "RESERVED," rbitfld.long 0x78 15. "RESERVED," "0,1" newline hexmask.long.word 0x78 0.--14. 1. "CVD2,VD2 Interrupt timing in a field (line number)" line.long 0x7C "ISIF_MISC," hexmask.long.word 0x7C 16.--31. 1. "RESERVED," rbitfld.long 0x7C 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x7C 13. "DPCMPRE,Selects Predictor for DPCM Encoder (12-8)" "DPCMPRE_0,DPCMPRE_1" bitfld.long 0x7C 12. "DPCMEN,Enables DPCM Encoding (12-8)" "DPCMEN_0,DPCMEN_1" newline hexmask.long.word 0x7C 1.--11. 1. "RESERVED," bitfld.long 0x7C 0. "RESERVED," "0,1" line.long 0x80 "ISIF_CGAMMAWD," hexmask.long.word 0x80 16.--31. 1. "RESERVED," rbitfld.long 0x80 15. "RESERVED," "0,1" newline bitfld.long 0x80 14. "WBEN2,White Balance Enable for H3A" "WBEN2_0,WBEN2_1" bitfld.long 0x80 13. "WBEN1,White Balance Enable for IPIPE" "WBEN1_0,WBEN1_1" newline bitfld.long 0x80 12. "WBEN0,White Balance Enable for memory capture" "WBEN0_0,WBEN0_1" rbitfld.long 0x80 11. "RESERVED," "0,1" newline bitfld.long 0x80 10. "OFSTEN2,Offset control Enable for H3A" "OFSTEN2_0,OFSTEN2_1" bitfld.long 0x80 9. "OFSTEN1,Offset control Enable for IPIPE" "OFSTEN1_0,OFSTEN1_1" newline bitfld.long 0x80 8. "OFSTEN0,Offset control Enable for SDRAM capture" "OFSTEN0_0,OFSTEN0_1" rbitfld.long 0x80 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x80 5. "CFAP,Selects CFA pattern" "CFAP_0,CFAP_1" bitfld.long 0x80 1.--4. "GWDI,Selects MSB position of Input Data" "GWDI_0,GWDI_1,GWDI_2,GWDI_3,GWDI_4,GWDI_5,GWDI_6,GWDI_7,GWDI_8,GWDI_9,GWDI_10,GWDI_11,GWDI_12,GWDI_13,GWDI_14,GWDI_15" newline bitfld.long 0x80 0. "CCDTBL,On/Off control of A-law table for SDRAM capture" "CCDTBL_0,CCDTBL_1" line.long 0x84 "ISIF_REC656IF,INPUT CONFIG REGISTER" hexmask.long.word 0x84 16.--31. 1. "RESERVED," hexmask.long.word 0x84 2.--15. 1. "RESERVED," newline bitfld.long 0x84 1. "R656ON,CCIR Rec.656 interface mode" "R656ON_0,R656ON_1" bitfld.long 0x84 0. "ECCFVH,Error correction of FVH code" "ECCFVH_0,ECCFVH_1" line.long 0x88 "ISIF_CCDCFG," hexmask.long.word 0x88 16.--31. 1. "RESERVED," bitfld.long 0x88 15. "VLDC,On/off control of CPU registers re-synchronize function by VSYNC" "VLDC_0,VLDC_1" newline bitfld.long 0x88 14. "RESERVED,Reserved" "0,1" bitfld.long 0x88 13. "MSBINVI,MSB inverse of CIN port when the data are captured to SDRAM" "MSBINVI_0,MSBINVI_1" newline bitfld.long 0x88 12. "BSWD,On/off control of Byte SWAP function when SDRAM capturing" "BSWD_0,BSWD_1" bitfld.long 0x88 11. "Y8POS,Selects Y signal position when in 8bit input mode" "Y8POS_0,Y8POS_1" newline bitfld.long 0x88 10. "EXTRG,Setting ?1? to this register the SDRAM address is initialized at the rising edge of FID input signal or DWEN register" "0,1" bitfld.long 0x88 9. "TRGSEL,Select trigger source signal of SDRAM address initializing in case EXTRG=1" "TRGSEL_0,TRGSEL_1" newline bitfld.long 0x88 8. "WENLOG,Specifies the CCD valid area" "WENLOG_0,WENLOG_1" bitfld.long 0x88 6.--7. "FIDMD,Specifies FID detection mode" "FIDMD_0,FIDMD_1,FIDMD_2,FIDMD_3" newline bitfld.long 0x88 5. "BT656,Selects bit width of CCIR656" "BT656_0,BT656_1" bitfld.long 0x88 4. "YCINSWP,The ISIF module has a 16-bit interface" "YCINSWP_0,YCINSWP_1" newline bitfld.long 0x88 3. "RESERVED,Reserved" "0,1" bitfld.long 0x88 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x88 0.--1. "SDRPACK,This bit field selects how the data are stored to SDRAM" "SDRPACK_0,SDRPACK_1,SDRPACK_2,SDRPACK_3" line.long 0x8C "ISIF_DFCCTL,VERTICAL LINE DEFCT CTRL REGISTER" hexmask.long.word 0x8C 16.--31. 1. "RESERVED," rbitfld.long 0x8C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x8C 8.--10. "VDFLSFT,Vertical line Defect level shift value Defect Level (value to be subtracted from the data) is 8bit width but can be up-shifted up to 6bits by VDFLSFT" "0,1,2,3,4,5,6,7" bitfld.long 0x8C 7. "VDFCUDA,Vertical line Defect Correction upper pixels disable" "VDFCUDA_0,VDFCUDA_1" newline bitfld.long 0x8C 5.--6. "VDFCSL,Vertical line Defect Correction mode select" "VDFCSL_0,VDFCSL_1,VDFCSL_2,VDFCSL_3" bitfld.long 0x8C 4. "VDFCEN,Vertical line Defect Correction enable" "VDFCEN_0,VDFCEN_1" newline rbitfld.long 0x8C 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x90 "ISIF_VDFSATLV,VERTICAL LINE DEFCT CTRL REGISTER" hexmask.long.word 0x90 16.--31. 1. "RESERVED," rbitfld.long 0x90 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x90 0.--11. 1. "VDFSLV,Vertical line Defect Correction saturation level" line.long 0x94 "ISIF_DFCMEMCTL,VERTICAL LINE DEFCT CTRL REGISTER" hexmask.long.word 0x94 16.--31. 1. "RESERVED," hexmask.long.word 0x94 5.--15. 1. "RESERVED," newline bitfld.long 0x94 4. "DFCMCLR,Defect correction" "0,1" rbitfld.long 0x94 3. "RESERVED," "0,1" newline bitfld.long 0x94 2. "DFCMARST,Defect correction" "DFCMARST_0,DFCMARST_1" bitfld.long 0x94 1. "DFCMRD,Defect correction" "0,1" newline bitfld.long 0x94 0. "DFCMWR,Defect correction" "0,1" line.long 0x98 "ISIF_DFCMEM0,Defect correction memory" hexmask.long.word 0x98 16.--31. 1. "RESERVED," rbitfld.long 0x98 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x98 0.--12. 1. "DFCMEM0,Defect correction memory 0 Sets V position of the defects" line.long 0x9C "ISIF_DFCMEM1,Defect correction memory" hexmask.long.word 0x9C 16.--31. 1. "RESERVED," rbitfld.long 0x9C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x9C 0.--12. 1. "DFCMEM1,Defect correction memory 1 Sets H position of the defects" line.long 0xA0 "ISIF_DFCMEM2,Defect correction memory" hexmask.long.word 0xA0 16.--31. 1. "RESERVED," hexmask.long.byte 0xA0 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xA0 0.--7. 1. "DFCMEM2,Defect correction Memory 2 Set SUB1: Defect level of the Vertical line defect position (V = Vdefect)" line.long 0xA4 "ISIF_DFCMEM3,Defect correction memory" hexmask.long.word 0xA4 16.--31. 1. "RESERVED," hexmask.long.byte 0xA4 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xA4 0.--7. 1. "DFCMEM3,Defect correction Memory 3 Set SUB2: Defect level of the pixels upper than the Vertical line defect (V Vdefect)" line.long 0xA8 "ISIF_DFCMEM4,Defect correction memory" hexmask.long.word 0xA8 16.--31. 1. "RESERVED," hexmask.long.byte 0xA8 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xA8 0.--7. 1. "DFCMEM4,Memory 4 Set SUB3: Defect level of the pixels lower than the Vertical line defect (V Vdefect)" line.long 0xAC "ISIF_CLAMPCFG,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xAC 16.--31. 1. "RESERVED," hexmask.long.word 0xAC 5.--15. 1. "RESERVED," newline bitfld.long 0xAC 4. "CLMD,Black clamp mode Clamp value can be calculated regardless of the color or can be calculated separately for each 4 colors" "CLMD_0,CLMD_1" rbitfld.long 0xAC 3. "RESERVED," "0,1" newline bitfld.long 0xAC 1.--2. "CLHMD,Horizontal Clamp mode" "CLHMD_0,CLHMD_1,CLHMD_2,CLHMD_3" bitfld.long 0xAC 0. "CLEN,Black Clamp Enable Enables clamp value to be subtracted from Image data" "CLEN_0,CLEN_1" line.long 0xB0 "ISIF_CLDCOFST,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xB0 16.--31. 1. "RESERVED," rbitfld.long 0xB0 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xB0 0.--12. 1. "CLDC,DC offset for black clamp This value is added to the incoming pixels regardless whether optical black clamp is enabled (ISIF_CLAMPCFG.CLEN)" line.long 0xB4 "ISIF_CLSV,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xB4 16.--31. 1. "RESERVED," rbitfld.long 0xB4 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xB4 0.--12. 1. "CLSV,Black Clamp Start position (V)" line.long 0xB8 "ISIF_CLHWIN0,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xB8 16.--31. 1. "RESERVED," rbitfld.long 0xB8 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0xB8 12.--13. "CLHWN,Horizontal Black clamp - Vertical dimension of a Window (2^N)" "CLHWN_0,CLHWN_1,CLHWN_2,CLHWN_3" rbitfld.long 0xB8 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0xB8 8.--9. "CLHWM,Horizontal Black clamp - Horizontal dimension of a Window (2^M)" "CLHWM_0,CLHWM_1,CLHWM_2,CLHWM_3" rbitfld.long 0xB8 7. "RESERVED," "0,1" newline bitfld.long 0xB8 6. "CLHLMT,Horizontal Black clamp - Pixel value limitation for the Horizontal clamp value calculation" "CLHLMT_0,CLHLMT_1" bitfld.long 0xB8 5. "CLHWBS,Horizontal Black clamp - Base Window select" "CLHWBS_0,CLHWBS_1" newline bitfld.long 0xB8 0.--4. "CLHWC,Horizontal Black clamp - Window count per color Window count = CLHWC+1 Range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xBC "ISIF_CLHWIN1,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xBC 16.--31. 1. "RESERVED," rbitfld.long 0xBC 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xBC 0.--12. 1. "CLHSH,Horizontal black clamp" line.long 0xC0 "ISIF_CLHWIN2,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xC0 16.--31. 1. "RESERVED," rbitfld.long 0xC0 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC0 0.--12. 1. "CLHSV,Horizontal black clamp" line.long 0xC4 "ISIF_CLVRV,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xC4 16.--31. 1. "RESERVED," rbitfld.long 0xC4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC4 0.--11. 1. "CLVRV,Vertical black clamp reset value" line.long 0xC8 "ISIF_CLVWIN0,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xC8 16.--31. 1. "RESERVED," hexmask.long.byte 0xC8 8.--15. 1. "CLVCOEF,Vertical Black clamp - Line average coefficient (k)" newline rbitfld.long 0xC8 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0xC8 4.--5. "CLVRVSL,Vertical Black clamp - reset value selection Select the reset value for the clamp value of the previous line" "CLVRVSL_0,CLVRVSL_1,CLVRVSL_2,CLVRVSL_3" newline rbitfld.long 0xC8 3. "RESERVED," "0,1" bitfld.long 0xC8 0.--2. "CLVOBH,Vertical Black clamp - Optical Black H valid (2^L)" "CLVOBH_0,CLVOBH_1,CLVOBH_2,CLVOBH_3,CLVOBH_4,CLVOBH_5,CLVOBH_6,CLVOBH_7" line.long 0xCC "ISIF_CLVWIN1,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xCC 16.--31. 1. "RESERVED," rbitfld.long 0xCC 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xCC 0.--12. 1. "CLVSH,Vertical black clamp" line.long 0xD0 "ISIF_CLVWIN2,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xD0 16.--31. 1. "RESERVED," rbitfld.long 0xD0 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xD0 0.--12. 1. "CLVSV,Vertical black clamp" line.long 0xD4 "ISIF_CLVWIN3,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xD4 16.--31. 1. "RESERVED," rbitfld.long 0xD4 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xD4 0.--12. 1. "CLVOBV,Vertical black clamp" line.long 0xD8 "ISIF_LSCHOFST,2D Lens Shading Correction Register" hexmask.long.word 0xD8 16.--31. 1. "RESERVED," rbitfld.long 0xD8 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0xD8 0.--13. 1. "HOFST,H direction Data offset for Lens Shading Correction" line.long 0xDC "ISIF_LSCVOFST,2D Lens Shading Correction Register" hexmask.long.word 0xDC 16.--31. 1. "RESERVED," rbitfld.long 0xDC 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0xDC 0.--13. 1. "VOFST,V direction Data offset for Lens Shading Correction" line.long 0xE0 "ISIF_LSCHVAL,2D Lens Shading Correction Register" hexmask.long.word 0xE0 16.--31. 1. "RESERVED," rbitfld.long 0xE0 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0xE0 0.--13. 1. "HVAL,Number of valid pixels in H direction" line.long 0xE4 "ISIF_LSCVVAL,2D Lens Shading Correction Register" hexmask.long.word 0xE4 16.--31. 1. "RESERVED," rbitfld.long 0xE4 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0xE4 0.--13. 1. "VVAL,Number of valid lines in V direction" line.long 0xE8 "ISIF_2DLSCCFG,2D Lens Shading Correction Register" hexmask.long.word 0xE8 16.--31. 1. "RESERVED," rbitfld.long 0xE8 15. "RESERVED," "0,1" newline bitfld.long 0xE8 12.--14. "GAIN_MODE_M,Define the horizontal dimension of a paxel" "GAIN_MODE_M_0,GAIN_MODE_M_1,GAIN_MODE_M_2,GAIN_MODE_M_3,GAIN_MODE_M_4,GAIN_MODE_M_5,GAIN_MODE_M_6,GAIN_MODE_M_7" rbitfld.long 0xE8 11. "RESERVED," "0,1" newline bitfld.long 0xE8 8.--10. "GAIN_MODE_N,Define the vertical dimension of a paxel" "GAIN_MODE_N_0,GAIN_MODE_N_1,GAIN_MODE_N_2,GAIN_MODE_N_3,GAIN_MODE_N_4,GAIN_MODE_N_5,GAIN_MODE_N_6,GAIN_MODE_N_7" rbitfld.long 0xE8 7. "BUSY,Busy bit" "BUSY_0,BUSY_1" newline bitfld.long 0xE8 6. "GAIN_RANGE,Define the range of gain table values" "8-bit gain mode GAIN table represents unsigned..,16-bit gain mode" rbitfld.long 0xE8 5. "RESERVED," "0,1" newline bitfld.long 0xE8 1.--4. "GAIN_FORMAT,Sets gain table format 16-bit mode is only for OMAP5430" "GAIN_FORMAT_0,GAIN_FORMAT_1,GAIN_FORMAT_2,GAIN_FORMAT_3,GAIN_FORMAT_4,GAIN_FORMAT_5,GAIN_FORMAT_6,GAIN_FORMAT_7,GAIN_FORMAT_8,GAIN_FORMAT_9,GAIN_FORMAT_10,GAIN_FORMAT_11,GAIN_FORMAT_12,GAIN_FORMAT_13,GAIN_FORMAT_14,GAIN_FORMAT_15" bitfld.long 0xE8 0. "ENABLE,Enables/disables LSC" "ENABLE_0,ENABLE_1" line.long 0xEC "ISIF_2DLSCOFST,2D Lens Shading Correction Register" hexmask.long.word 0xEC 16.--31. 1. "RESERVED," hexmask.long.byte 0xEC 8.--15. 1. "OFSTSF,Scaling factor for Offsets (U8Q7) Range: 0 to 1+127/128" newline rbitfld.long 0xEC 7. "RESERVED," "0,1" bitfld.long 0xEC 4.--6. "OFSTSFT,Shift up value for Offsets (S8Q0)" "OFSTSFT_0,OFSTSFT_1,OFSTSFT_2,OFSTSFT_3,OFSTSFT_4,OFSTSFT_5,OFSTSFT_6,OFSTSFT_7" newline rbitfld.long 0xEC 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0xEC 0. "OFSTEN,Enables/disables Offset control in LSC This bit is ignored (treated as zero) in 16-bit gain mode (ISIF_2DLSCCFG.GAIN_RANGE=1)" "OFSTEN_0,OFSTEN_1" line.long 0xF0 "ISIF_2DLSCINI,2D Lens Shading Correction Register" hexmask.long.word 0xF0 16.--31. 1. "RESERVED," rbitfld.long 0xF0 15. "RESERVED," "0,1" newline hexmask.long.byte 0xF0 8.--14. 1. "Y,Initial Y Y position in pixels of the first active pixel in reference to the first active paxel" rbitfld.long 0xF0 7. "RESERVED," "0,1" newline hexmask.long.byte 0xF0 0.--6. 1. "X,Initial X X position in pixels of the first active pixel in reference to the first active paxel" line.long 0xF4 "ISIF_2DLSCGRBU,2D Lens Shading Correction Register" hexmask.long.word 0xF4 16.--31. 1. "RESERVED," hexmask.long.word 0xF4 0.--15. 1. "BASE31_16,Gain Table address base (Upper 16-bits) This bit field sets the address of the gain table in memory" line.long 0xF8 "ISIF_2DLSCGRBL,2D Lens Shading Correction Register" hexmask.long.word 0xF8 16.--31. 1. "RESERVED," hexmask.long.word 0xF8 0.--15. 1. "BASE15_0,Gain Table address base (Lower 16-bits) Table address in bytes" line.long 0xFC "ISIF_2DLSCGROF,2D Lens Shading Correction Register" hexmask.long.word 0xFC 16.--31. 1. "RESERVED," hexmask.long.word 0xFC 0.--15. 1. "OFFSET,Gain Table offset Defines the length in bytes of one row of the table" line.long 0x100 "ISIF_2DLSCORBU,2D Lens Shading Correction Register" hexmask.long.word 0x100 16.--31. 1. "RESERVED," hexmask.long.word 0x100 0.--15. 1. "BASE,Offset Table address base (Upper 16-bits) Table address in bytes" line.long 0x104 "ISIF_2DLSCORBL,2D Lens Shading Correction Register" hexmask.long.word 0x104 16.--31. 1. "RESERVED," hexmask.long.word 0x104 0.--15. 1. "BASE,Offset Table address base (Lower 16-bits) Table address in bytes" line.long 0x108 "ISIF_2DLSCOROF,2D Lens Shading Correction Register" hexmask.long.word 0x108 16.--31. 1. "RESERVED," hexmask.long.word 0x108 0.--15. 1. "OFFSET,Offset Table offset Defines the length in bytes of one row of the table" line.long 0x10C "ISIF_2DLSCIRQEN," hexmask.long.word 0x10C 16.--31. 1. "RESERVED," hexmask.long.word 0x10C 4.--15. 1. "RESERVED," newline bitfld.long 0x10C 3. "SOF,Interrupt status for LSC SOF Indicates the start of the LSC valid region" "SOF_0,SOF_1" bitfld.long 0x10C 2. "PREFETCH_COMPLETED,Interrupt enable for Prefetch Complete Indicates current state of the prefetch buffer" "PREFETCH_COMPLETED_0,PREFETCH_COMPLETED_1" newline bitfld.long 0x10C 1. "PREFETCH_ERROR,Interrupt enable for Prefetch Error The prefetch error indicates when the gain table was read to slowly from SDRAM" "PREFETCH_ERROR_0,PREFETCH_ERROR_1" bitfld.long 0x10C 0. "DONE,Interrupt enable for LSC Done The event is triggered when the internal state of LSC toggles from BUSY to IDLE" "DONE_0,DONE_1" line.long 0x110 "ISIF_2DLSCIRQST,2D Lens Shading Correction Register" hexmask.long.word 0x110 16.--31. 1. "RESERVED," hexmask.long.word 0x110 4.--15. 1. "RESERVED," newline bitfld.long 0x110 3. "SOF,Interrupt status for LSC SOF Indicates the start of the LSC valid region" "SOF_0,SOF_1" bitfld.long 0x110 2. "PREFETCH_COMPLETED,Interrupt status for Prefetch Complete Indicates current state of the prefetch buffer" "PREFETCH_COMPLETED_0,PREFETCH_COMPLETED_1" newline bitfld.long 0x110 1. "PREFETCH_ERROR,Interrupt status for Prefetch Error The prefetch error indicates when the gain table was read to slowly from SDRAM" "PREFETCH_ERROR_0,PREFETCH_ERROR_1" bitfld.long 0x110 0. "DONE,Interrupt status for LSC Done The event is triggered when the internal state of LSC toggles from BUSY to IDLE" "DONE_0,DONE_1" line.long 0x114 "ISIF_FMTCFG,Input Data Formatter Register" hexmask.long.tbyte 0x114 12.--31. 1. "RESERVED," bitfld.long 0x114 8.--11. "FMTAINC,Address increment Address increment = (FMTAINC + 1) Range (1-16) *This bit is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x114 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x114 4.--5. "LNUM,Split/Combine number of lines *This bit is latched by VD" "LNUM_0,LNUM_1,LNUM_2,LNUM_3" newline rbitfld.long 0x114 3. "RESERVED," "0,1" bitfld.long 0x114 2. "LNALT,Line alternating *This bit is latched by VD" "LNALT_0,LNALT_1" newline bitfld.long 0x114 1. "FMTCBL,Combine Input lines *This bit is latched by VD" "FMTCBL_0,FMTCBL_1" bitfld.long 0x114 0. "FMTEN,CCD Formatter enable *This bit is latched by VD" "FMTEN_0,FMTEN_1" line.long 0x118 "ISIF_FMTPLEN,Input Data Formatter Register" hexmask.long.tbyte 0x118 15.--31. 1. "RESERVED," bitfld.long 0x118 12.--14. "FMTPLEN3,Number of program entries for SET3 Number of entries = (FMTPLEN3 + 1) Range: 1-8 Valid only if FMTCBL is set *This bit is latched by VD" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x118 11. "RESERVED," "0,1" bitfld.long 0x118 8.--10. "FMTPLEN2,Number of program entries for SET2 Number of entries = (FMTPLEN2 + 1) Range: 1-8 Valid only if FMTCBL is set *This bit is latched by VD" "0,1,2,3,4,5,6,7" newline bitfld.long 0x118 4.--7. "FMTPLEN1,Number of program entries for SET1 Number of entries = (FMTPLEN1 + 1) Range: 1-16 (FMTCBL = 0) 1-8 (FMTCBL = 1) Setting a value greater than 7 to FMTPLEN1 is not allowed if FMTCBL is set *This bit is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x118 0.--3. "FMTPLEN0,Number of program entries for SET0 Number of entries = (PLEN0 + 1) Range: 1-16 (FMTCBL = 0) 1-8 (FMTCBL = 1) Setting a value greater than 7 to FMTPLEN1 is not allowed if FMTCBL is set *This bit is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x11C "ISIF_FMTSPH,Input Data Formatter Register" hexmask.long.tbyte 0x11C 13.--31. 1. "RESERVED," hexmask.long.word 0x11C 0.--12. 1. "FMTSPH,The first pixel in a line fed into the formatter" line.long 0x120 "ISIF_FMTLNH,Input Data Formatter Register" hexmask.long.tbyte 0x120 13.--31. 1. "RESERVED," hexmask.long.word 0x120 0.--12. 1. "FMTLNH,Number of pixels in a line fed to the formatterNumber of pixels = FMTLNH + 1" line.long 0x124 "ISIF_FMTLSV,Input Data Formatter Register" hexmask.long.tbyte 0x124 13.--31. 1. "RESERVED," hexmask.long.word 0x124 0.--12. 1. "FMTSLV,Start line vertical" line.long 0x128 "ISIF_FMTLNV,Input Data Formatter Register" hexmask.long.tbyte 0x128 15.--31. 1. "RESERVED," hexmask.long.word 0x128 0.--14. 1. "FMTLNV,Number of lines in vertical Number of lines = FMTLNV + 1" line.long 0x12C "ISIF_FMTRLEN,Input Data Formatter Register" hexmask.long.tbyte 0x12C 13.--31. 1. "RESERVED," hexmask.long.word 0x12C 0.--12. 1. "FMTRLEN,Number of pixels in an output line Maximum value = 4480" line.long 0x130 "ISIF_FMTHCNT,Input Data Formatter Register" hexmask.long.tbyte 0x130 13.--31. 1. "RESERVED," hexmask.long.word 0x130 0.--12. 1. "FMTHCNT,HD interval for output lines Set all '0' to this register if combining multiple lines into a single line" line.long 0x134 "ISIF_FMTAPTR0,Input Data Formatter Register" hexmask.long.tbyte 0x134 15.--31. 1. "RESERVED," bitfld.long 0x134 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared" "LINE_0,LINE_1,LINE_2,LINE_3" newline hexmask.long.word 0x134 0.--12. 1. "INIT,Initial address value for address pointer 0 This address can not exceed FMTRLEN - 1" line.long 0x138 "ISIF_FMTAPTR1,Input Data Formatter Register" hexmask.long.tbyte 0x138 15.--31. 1. "RESERVED," bitfld.long 0x138 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared" "LINE_0,LINE_1,LINE_2,LINE_3" newline hexmask.long.word 0x138 0.--12. 1. "INIT,Initial address value for address pointer 1 This address can not exceed FMTRLEN - 1" line.long 0x13C "ISIF_FMTAPTR2,Input Data Formatter Register" hexmask.long.tbyte 0x13C 15.--31. 1. "RESERVED," bitfld.long 0x13C 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared" "LINE_0,LINE_1,LINE_2,LINE_3" newline hexmask.long.word 0x13C 0.--12. 1. "INIT,Initial address value for address pointer 2 This address can not exceed FMTRLEN - 1" line.long 0x140 "ISIF_FMTAPTR3,Input Data Formatter Register" hexmask.long.tbyte 0x140 15.--31. 1. "RESERVED," bitfld.long 0x140 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared" "LINE_0,LINE_1,LINE_2,LINE_3" newline hexmask.long.word 0x140 0.--12. 1. "INIT,Initial address value for address pointer 3 This address can not exceed FMTRLEN - 1" line.long 0x144 "ISIF_FMTAPTR4,Input Data Formatter Register" hexmask.long.tbyte 0x144 15.--31. 1. "RESERVED," bitfld.long 0x144 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared" "LINE_0,LINE_1,LINE_2,LINE_3" newline hexmask.long.word 0x144 0.--12. 1. "INIT,Initial address value for address pointer 4 This address can not exceed FMTRLEN - 1" line.long 0x148 "ISIF_FMTAPTR5,Input Data Formatter Register" hexmask.long.tbyte 0x148 15.--31. 1. "RESERVED," bitfld.long 0x148 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared" "LINE_0,LINE_1,LINE_2,LINE_3" newline hexmask.long.word 0x148 0.--12. 1. "INIT,Initial address value for address pointer 5 This address can not exceed FMTRLEN - 1" line.long 0x14C "ISIF_FMTAPTR6,Input Data Formatter Register" hexmask.long.tbyte 0x14C 15.--31. 1. "RESERVED," bitfld.long 0x14C 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared" "LINE_0,LINE_1,LINE_2,LINE_3" newline hexmask.long.word 0x14C 0.--12. 1. "INIT,Initial address value for address pointer 6 This address can not exceed FMTRLEN - 1" line.long 0x150 "ISIF_FMTAPTR7,Input Data Formatter Register" hexmask.long.tbyte 0x150 15.--31. 1. "RESERVED," bitfld.long 0x150 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared" "LINE_0,LINE_1,LINE_2,LINE_3" newline hexmask.long.word 0x150 0.--12. 1. "INIT,Initial address value for address pointer 7 This address can not exceed FMTRLEN - 1" line.long 0x154 "ISIF_FMTAPTR8,Input Data Formatter Register" hexmask.long.tbyte 0x154 15.--31. 1. "RESERVED," bitfld.long 0x154 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared" "LINE_0,LINE_1,LINE_2,LINE_3" newline hexmask.long.word 0x154 0.--12. 1. "INIT,Initial address value for address pointer 8 This address can not exceed FMTRLEN - 1" line.long 0x158 "ISIF_FMTAPTR9,Input Data Formatter Register" hexmask.long.tbyte 0x158 15.--31. 1. "RESERVED," bitfld.long 0x158 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared" "LINE_0,LINE_1,LINE_2,LINE_3" newline hexmask.long.word 0x158 0.--12. 1. "INIT,Initial address value for address pointer 9 This address can not exceed FMTRLEN - 1" line.long 0x15C "ISIF_FMTAPTR10,Input Data Formatter Register" hexmask.long.tbyte 0x15C 15.--31. 1. "RESERVED," bitfld.long 0x15C 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared" "LINE_0,LINE_1,LINE_2,LINE_3" newline hexmask.long.word 0x15C 0.--12. 1. "INIT,Initial address value for address pointer 10 This address can not exceed FMTRLEN - 1" line.long 0x160 "ISIF_FMTAPTR11,Input Data Formatter Register" hexmask.long.tbyte 0x160 15.--31. 1. "RESERVED," bitfld.long 0x160 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared" "LINE_0,LINE_1,LINE_2,LINE_3" newline hexmask.long.word 0x160 0.--12. 1. "INIT,Initial address value for address pointer 11 This address can not exceed FMTRLEN - 1" line.long 0x164 "ISIF_FMTAPTR12,Input Data Formatter Register" hexmask.long.tbyte 0x164 15.--31. 1. "RESERVED," bitfld.long 0x164 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared" "LINE_0,LINE_1,LINE_2,LINE_3" newline hexmask.long.word 0x164 0.--12. 1. "INIT,Initial address value for address pointer 12 This address can not exceed FMTRLEN - 1" line.long 0x168 "ISIF_FMTAPTR13,Input Data Formatter Register" hexmask.long.tbyte 0x168 15.--31. 1. "RESERVED," bitfld.long 0x168 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared" "LINE_0,LINE_1,LINE_2,LINE_3" newline hexmask.long.word 0x168 0.--12. 1. "INIT,Initial address value for address pointer 13 This address can not exceed FMTRLEN - 1" line.long 0x16C "ISIF_FMTAPTR14,Input Data Formatter Register" hexmask.long.tbyte 0x16C 15.--31. 1. "RESERVED," bitfld.long 0x16C 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared" "LINE_0,LINE_1,LINE_2,LINE_3" newline hexmask.long.word 0x16C 0.--12. 1. "INIT,Initial address value for address pointer 14 This address can not exceed FMTRLEN - 1" line.long 0x170 "ISIF_FMTAPTR15,Input Data Formatter Register" hexmask.long.tbyte 0x170 15.--31. 1. "RESERVED," bitfld.long 0x170 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared" "LINE_0,LINE_1,LINE_2,LINE_3" newline hexmask.long.word 0x170 0.--12. 1. "INIT,Initial address value for address pointer 15 This address can not exceed FMTRLEN - 1" line.long 0x174 "ISIF_FMTPGMVF0,Input Data Formatter Register" hexmask.long.word 0x174 16.--31. 1. "RESERVED," bitfld.long 0x174 15. "PGM15EN,Program 15 Valid Flag" "PGM15EN_0,PGM15EN_1" newline bitfld.long 0x174 14. "PGM14EN,Program 14 Valid Flag" "PGM14EN_0,PGM14EN_1" bitfld.long 0x174 13. "PGM13EN,Program 13 Valid Flag" "PGM13EN_0,PGM13EN_1" newline bitfld.long 0x174 12. "PGM12EN,Program 12 Valid Flag" "PGM12EN_0,PGM12EN_1" bitfld.long 0x174 11. "PGM11EN,Program 11 Valid Flag" "PGM11EN_0,PGM11EN_1" newline bitfld.long 0x174 10. "PGM10EN,Program 10 Valid Flag" "PGM10EN_0,PGM10EN_1" bitfld.long 0x174 9. "PGM09EN,Program 9 Valid Flag" "PGM09EN_0,PGM09EN_1" newline bitfld.long 0x174 8. "PGM08EN,Program 8 Valid Flag" "PGM08EN_0,PGM08EN_1" bitfld.long 0x174 7. "PGM07EN,Program 7 Valid Flag" "PGM07EN_0,PGM07EN_1" newline bitfld.long 0x174 6. "PGM06EN,Program 6 Valid Flag" "PGM06EN_0,PGM06EN_1" bitfld.long 0x174 5. "PGM05EN,Program 5 Valid Flag" "PGM05EN_0,PGM05EN_1" newline bitfld.long 0x174 4. "PGM04EN,Program 4 Valid Flag" "PGM04EN_0,PGM04EN_1" bitfld.long 0x174 3. "PGM03EN,Program 3 Valid Flag" "PGM03EN_0,PGM03EN_1" newline bitfld.long 0x174 2. "PGM02EN,Program 2 Valid Flag" "PGM02EN_0,PGM02EN_1" bitfld.long 0x174 1. "PGM01EN,Program 1 Valid Flag" "PGM01EN_0,PGM01EN_1" newline bitfld.long 0x174 0. "PGM00EN,Program 0 Valid Flag" "PGM00EN_0,PGM00EN_1" line.long 0x178 "ISIF_FMTPGMVF1,Input Data Formatter Register" hexmask.long.word 0x178 16.--31. 1. "RESERVED," bitfld.long 0x178 15. "PGM31EN,Program 31 Valid Flag" "PGM31EN_0,PGM31EN_1" newline bitfld.long 0x178 14. "PGM30EN,Program 30 Valid Flag" "PGM30EN_0,PGM30EN_1" bitfld.long 0x178 13. "PGM29EN,Program 29 Valid Flag" "PGM29EN_0,PGM29EN_1" newline bitfld.long 0x178 12. "PGM28EN,Program 28 Valid Flag" "PGM28EN_0,PGM28EN_1" bitfld.long 0x178 11. "PGM27EN,Program 27 Valid Flag" "PGM27EN_0,PGM27EN_1" newline bitfld.long 0x178 10. "PGM26EN,Program 26 Valid Flag" "PGM26EN_0,PGM26EN_1" bitfld.long 0x178 9. "PGM25EN,Program 25 Valid Flag" "PGM25EN_0,PGM25EN_1" newline bitfld.long 0x178 8. "PGM24EN,Program 24 Valid Flag" "PGM24EN_0,PGM24EN_1" bitfld.long 0x178 7. "PGM23EN,Program 23 Valid Flag" "PGM23EN_0,PGM23EN_1" newline bitfld.long 0x178 6. "PGM22EN,Program 22 Valid Flag" "PGM22EN_0,PGM22EN_1" bitfld.long 0x178 5. "PGM21EN,Program 21 Valid Flag" "PGM21EN_0,PGM21EN_1" newline bitfld.long 0x178 4. "PGM20EN,Program 20 Valid Flag" "PGM20EN_0,PGM20EN_1" bitfld.long 0x178 3. "PGM19EN,Program 19 Valid Flag" "PGM19EN_0,PGM19EN_1" newline bitfld.long 0x178 2. "PGM18EN,Program 18 Valid Flag" "PGM18EN_0,PGM18EN_1" bitfld.long 0x178 1. "PGM17EN,Program 17 Valid Flag" "PGM17EN_0,PGM17EN_1" newline bitfld.long 0x178 0. "PGM16EN,Program 16 Valid Flag" "PGM16EN_0,PGM16EN_1" line.long 0x17C "ISIF_FMTPGMAPU0,Input Data Formatter Register" hexmask.long.word 0x17C 16.--31. 1. "RESERVED," bitfld.long 0x17C 15. "PGM15UPDT,Program 15 Address Pointer Update" "PGM15UPDT_0,PGM15UPDT_1" newline bitfld.long 0x17C 14. "PGM14UPDT,Program 14 Address Pointer Update" "PGM14UPDT_0,PGM14UPDT_1" bitfld.long 0x17C 13. "PGM13UPDT,Program 13 Address Pointer Update" "PGM13UPDT_0,PGM13UPDT_1" newline bitfld.long 0x17C 12. "PGM12UPDT,Program 12 Address Pointer Update" "PGM12UPDT_0,PGM12UPDT_1" bitfld.long 0x17C 11. "PGM11UPDT,Program 11 Address Pointer Update" "PGM11UPDT_0,PGM11UPDT_1" newline bitfld.long 0x17C 10. "PGM10UPDT,Program 10 Address Pointer Update" "PGM10UPDT_0,PGM10UPDT_1" bitfld.long 0x17C 9. "PGM9UPDT,Program 9 Address Pointer Update" "PGM9UPDT_0,PGM9UPDT_1" newline bitfld.long 0x17C 8. "PGM8UPDT,Program 8 Address Pointer Update" "PGM8UPDT_0,PGM8UPDT_1" bitfld.long 0x17C 7. "PGM7UPDT,Program 7 Address Pointer Update" "PGM7UPDT_0,PGM7UPDT_1" newline bitfld.long 0x17C 6. "PGM6UPDT,Program 6 Address Pointer Update" "PGM6UPDT_0,PGM6UPDT_1" bitfld.long 0x17C 5. "PGM5UPDT,Program 5 Address Pointer Update" "PGM5UPDT_0,PGM5UPDT_1" newline bitfld.long 0x17C 4. "PGM4UPDT,Program 4 Address Pointer Update" "PGM4UPDT_0,PGM4UPDT_1" bitfld.long 0x17C 3. "PGM3UPDT,Program 3 Address Pointer Update" "PGM3UPDT_0,PGM3UPDT_1" newline bitfld.long 0x17C 2. "PGM2UPDT,Program 2 Address Pointer Update" "PGM2UPDT_0,PGM2UPDT_1" bitfld.long 0x17C 1. "PGM1UPDT,Program 1 Address Pointer Update" "PGM1UPDT_0,PGM1UPDT_1" newline bitfld.long 0x17C 0. "PGM0UPDT,Program 0 Address Pointer Update" "PGM0UPDT_0,PGM0UPDT_1" line.long 0x180 "ISIF_FMTPGMAPU1,Input Data Formatter Register" hexmask.long.word 0x180 16.--31. 1. "RESERVED," bitfld.long 0x180 15. "PGM31UPDT,Program 31 Address Pointer Update" "PGM31UPDT_0,PGM31UPDT_1" newline bitfld.long 0x180 14. "PGM30UPDT,Program 30 Address Pointer Update" "PGM30UPDT_0,PGM30UPDT_1" bitfld.long 0x180 13. "PGM29UPDT,Program 29 Address Pointer Update" "PGM29UPDT_0,PGM29UPDT_1" newline bitfld.long 0x180 12. "PGM28UPDT,Program 28 Address Pointer Update" "PGM28UPDT_0,PGM28UPDT_1" bitfld.long 0x180 11. "PGM27UPDT,Program 27 Address Pointer Update" "PGM27UPDT_0,PGM27UPDT_1" newline bitfld.long 0x180 10. "PGM26UPDT,Program 26 Address Pointer Update" "PGM26UPDT_0,PGM26UPDT_1" bitfld.long 0x180 9. "PGM25UPDT,Program 25 Address Pointer Update" "PGM25UPDT_0,PGM25UPDT_1" newline bitfld.long 0x180 8. "PGM24UPDT,Program 24 Address Pointer Update" "PGM24UPDT_0,PGM24UPDT_1" bitfld.long 0x180 7. "PGM23UPDT,Program 23 Address Pointer Update" "PGM23UPDT_0,PGM23UPDT_1" newline bitfld.long 0x180 6. "PGM22UPDT,Program 22 Address Pointer Update" "PGM22UPDT_0,PGM22UPDT_1" bitfld.long 0x180 5. "PGM21UPDT,Program 21 Address Pointer Update" "PGM21UPDT_0,PGM21UPDT_1" newline bitfld.long 0x180 4. "PGM20UPDT,Program 20 Address Pointer Update" "PGM20UPDT_0,PGM20UPDT_1" bitfld.long 0x180 3. "PGM19UPDT,Program 19 Address Pointer Update" "PGM19UPDT_0,PGM19UPDT_1" newline bitfld.long 0x180 2. "PGM18UPDT,Program 18 Address Pointer Update" "PGM18UPDT_0,PGM18UPDT_1" bitfld.long 0x180 1. "PGM17UPDT,Program 17 Address Pointer Update" "PGM17UPDT_0,PGM17UPDT_1" newline bitfld.long 0x180 0. "PGM16UPDT,Program 16 Address Pointer Update" "PGM16UPDT_0,PGM16UPDT_1" line.long 0x184 "ISIF_FMTPGMAPS0,Input Data Formatter Register" hexmask.long.word 0x184 16.--31. 1. "RESERVED," bitfld.long 0x184 12.--15. "PGM3APTR,Program 3 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x184 8.--11. "PGM2APTR,Program 2 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x184 4.--7. "PGM1APTR,Program 1 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x184 0.--3. "PGM0APTR,Program 0 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x188 "ISIF_FMTPGMAPS1,Input Data Formatter Register" hexmask.long.word 0x188 16.--31. 1. "RESERVED," bitfld.long 0x188 12.--15. "PGM7APTR,Program 7 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x188 8.--11. "PGM6APTR,Program 6 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x188 4.--7. "PGM5APTR,Program 5 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x188 0.--3. "PGM4APTR,Program 0 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18C "ISIF_FMTPGMAPS2,Input Data Formatter Register" hexmask.long.word 0x18C 16.--31. 1. "RESERVED," bitfld.long 0x18C 12.--15. "PGM11APTR,Program 11 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18C 8.--11. "PGM10APTR,Program 10 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18C 4.--7. "PGM9APTR,Program 9 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18C 0.--3. "PGM8APTR,Program 8 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x190 "ISIF_FMTPGMAPS3,Input Data Formatter Register" hexmask.long.word 0x190 16.--31. 1. "RESERVED," bitfld.long 0x190 12.--15. "PGM15APTR,Program 15 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x190 8.--11. "PGM14APTR,Program 14 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x190 4.--7. "PGM13APTR,Program 13 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x190 0.--3. "PGM12APTR,Program 12 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x194 "ISIF_FMTPGMAPS4,Input Data Formatter Register" hexmask.long.word 0x194 16.--31. 1. "RESERVED," bitfld.long 0x194 12.--15. "PGM19APTR,Program 19 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x194 8.--11. "PGM18APTR,Program 18 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x194 4.--7. "PGM17APTR,Program 17 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x194 0.--3. "PGM16APTR,Program 16 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x198 "ISIF_FMTPGMAPS5,Input Data Formatter Register" hexmask.long.word 0x198 16.--31. 1. "RESERVED," bitfld.long 0x198 12.--15. "PGM23APTR,Program 23 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x198 8.--11. "PGM22APTR,Program 22 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x198 4.--7. "PGM21APTR,Program 21 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x198 0.--3. "PGM20APTR,Program 20 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x19C "ISIF_FMTPGMAPS6,Input Data Formatter Register" hexmask.long.word 0x19C 16.--31. 1. "RESERVED," bitfld.long 0x19C 12.--15. "PGM27APTR,Program 27 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x19C 8.--11. "PGM26APTR,Program 26 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x19C 4.--7. "PGM25APTR,Program 25 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x19C 0.--3. "PGM24APTR,Program 24 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1A0 "ISIF_FMTPGMAPS7,Input Data Formatter Register" hexmask.long.word 0x1A0 16.--31. 1. "RESERVED," bitfld.long 0x1A0 12.--15. "PGM31APTR,Program 31 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1A0 8.--11. "PGM30APTR,Program 30 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1A0 4.--7. "PGM29APTR,Program 29 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1A0 0.--3. "PGM28APTR,Program 28 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1A4 "ISIF_CSCCTL,Color Space Converter Register" hexmask.long.word 0x1A4 16.--31. 1. "RESERVED," hexmask.long.word 0x1A4 1.--15. 1. "RESERVED," newline bitfld.long 0x1A4 0. "CSCEN,Controls ON/OFF of Color Space converter" "CSCEN_0,CSCEN_1" line.long 0x1A8 "ISIF_CSCM0,Color Space Converter Register" hexmask.long.word 0x1A8 16.--31. 1. "RESERVED," hexmask.long.byte 0x1A8 8.--15. 1. "CSCM01,Color Space convert coefficient value M01: This value is signed 8-bit with the 5-bits decimal" newline hexmask.long.byte 0x1A8 0.--7. 1. "CSCM00,Color Space convert coefficient value M00: This value is signed 8-bit with the 5-bits decimal" line.long 0x1AC "ISIF_CSCM1,Color Space Converter Register" hexmask.long.word 0x1AC 16.--31. 1. "RESERVED," hexmask.long.byte 0x1AC 8.--15. 1. "CSCM03,Color Space convert coefficient value M03: This value is signed 8-bit with the 5-bits decimal" newline hexmask.long.byte 0x1AC 0.--7. 1. "CSCM02,Color Space convert coefficient value M02: This value is signed 8-bit with the 5-bits decimal" line.long 0x1B0 "ISIF_CSCM2,Color Space Converter Register" hexmask.long.word 0x1B0 16.--31. 1. "RESERVED," hexmask.long.byte 0x1B0 8.--15. 1. "CSCM11,Color Space convert coefficient value M11: This value is signed 8-bit with the 5-bits decimal" newline hexmask.long.byte 0x1B0 0.--7. 1. "CSCM10,Color Space convert coefficient value M10: This value is signed 8-bit with the 5-bits decimal" line.long 0x1B4 "ISIF_CSCM3,Color Space Converter Register" hexmask.long.word 0x1B4 16.--31. 1. "RESERVED," hexmask.long.byte 0x1B4 8.--15. 1. "CSCM13,Color Space convert coefficient value M13: This value is signed 8-bit with the 5-bits decimal" newline hexmask.long.byte 0x1B4 0.--7. 1. "CSCM12,Color Space convert coefficient value M12: This value is signed 8-bit with the 5-bits decimal" line.long 0x1B8 "ISIF_CSCM4,Color Space Converter Register" hexmask.long.word 0x1B8 16.--31. 1. "RESERVED," hexmask.long.byte 0x1B8 8.--15. 1. "CSCM21,Color Space convert coefficient value M21: This value is signed 8-bit with the 5-bits decimal" newline hexmask.long.byte 0x1B8 0.--7. 1. "CSCM20,Color Space convert coefficient value M20: This value is signed 8-bit with the 5-bits decimal" line.long 0x1BC "ISIF_CSCM5,Color Space Converter Register" hexmask.long.word 0x1BC 16.--31. 1. "RESERVED," hexmask.long.byte 0x1BC 8.--15. 1. "CSCM23,Color Space convert coefficient value M23: This value is signed 8-bit with the 5-bits decimal" newline hexmask.long.byte 0x1BC 0.--7. 1. "CSCM22,Color Space convert coefficient value M22: This value is signed 8-bit with the 5-bits decimal" line.long 0x1C0 "ISIF_CSCM6,Color Space Converter Register" hexmask.long.word 0x1C0 16.--31. 1. "RESERVED," hexmask.long.byte 0x1C0 8.--15. 1. "CSCM31,Color Space convert coefficient value M31: This value is signed 8-bit with the 5-bits decimal" newline hexmask.long.byte 0x1C0 0.--7. 1. "CSCM30,Color Space convert coefficient value M30: This value is signed 8-bit with the 5-bits decimal" line.long 0x1C4 "ISIF_CSCM7,Color Space Converter Register" hexmask.long.word 0x1C4 16.--31. 1. "RESERVED," hexmask.long.byte 0x1C4 8.--15. 1. "CSCM33,Color Space convert coefficient value M33: This value is signed 8-bit with the 5-bits decimal" newline hexmask.long.byte 0x1C4 0.--7. 1. "CSCM32,Color Space convert coefficient value M32: This value is signed 8-bit with the 5-bits decimal" group.long 0x1F8++0x07 line.long 0x00 "ISIF_CLKCTL," hexmask.long.word 0x00 16.--31. 1. "RESERVED," hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 1. "CLKEN1,Forces isif_clken1 to be active" "CLKEN1_0,CLKEN1_1" bitfld.long 0x00 0. "CLKEN2,Forces isif_clken2 to be active" "CLKEN2_0,CLKEN2_1" line.long 0x04 "ISIF_CBN,Circular bufferr parameters" rbitfld.long 0x04 31. "RESERVED," "0,1" hexmask.long.word 0x04 16.--30. 1. "CYN,Cicular Buffer Interrupt timing (line number)" newline rbitfld.long 0x04 15. "RESERVED," "0,1" hexmask.long.word 0x04 0.--14. 1. "CBN,Circular buffer size" repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C ) rgroup.long ($2+0x1D8)++0x03 line.long 0x00 "ISIF_OBVAL$1,Reserved" hexmask.long.word 0x00 16.--31. 1. "RESERVED," hexmask.long.word 0x00 0.--15. 1. "RESERVED," repeat.end repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C ) rgroup.long ($2+0x1C8)++0x03 line.long 0x00 "ISIF_OBWIN$1,Reserved" hexmask.long.word 0x00 16.--31. 1. "RESERVED," hexmask.long.word 0x00 0.--15. 1. "RESERVED," repeat.end width 0x0B tree.end tree "ISP6P5_NSF3V" base ad:0x52050810 group.long 0x00++0x03 line.long 0x00 "NSF3V_SYSCONFIG,OCP interface" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "SOFTRESET,Software reset" "No action Write,Reset (software or other) ongoing" group.long 0x08++0xE7 line.long 0x00 "NSF3V_CTRL,Control" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "EN,Enable NSF3V operation for either single frame or video depending onNSF3V_CFG.ONESHOT" "0,1" line.long 0x04 "NSF3V_CFG,Configuration" hexmask.long.word 0x04 18.--31. 1. "RESERVED," bitfld.long 0x04 17. "FORCE_CLKON,Force clock to be on disabling clock autogating" "0,1" bitfld.long 0x04 16. "SUPPRS_ALL,Suppress all subband signals (debug mode)" "0,1" newline bitfld.long 0x04 15. "BYPASS_W_DELAY,Bypass all processing so that output = input but maintain the same latency" "0,1" bitfld.long 0x04 14. "BBORDER_REP,Replicate top border to not lose 7 lines per color on the bottom" "0,1" bitfld.long 0x04 13. "TBORDER_REP,Replicate top border to not lose 7 lines per color on the top" "0,1" newline bitfld.long 0x04 12. "RBORDER_REP,Replicate right border to not lose 8 data points per color on the right" "0,1" bitfld.long 0x04 11. "LBORDER_REP,Replicate left border to not lose 8 data points per color on the left" "0,1" bitfld.long 0x04 10. "DESAT_EN,enable chroma desaturation" "0,1" newline bitfld.long 0x04 9. "SHD_EN,enable shading gain" "0,1" bitfld.long 0x04 8. "EE_EN,enable edge enhancement" "0,1" bitfld.long 0x04 7. "ONESHOT,Video (continuous operation) or one shot (single-frame)" "video,one-shot" newline bitfld.long 0x04 6. "HARD_THR_EN_422UV,Hard thresholding enable applicable to YUV422 (normal and interleaved) UV path" "0,1" rbitfld.long 0x04 4.--5. "RESERVED," "0,1,2,3" bitfld.long 0x04 0.--3. "MODE,Mode of operation" "Bayer,Bayer interleaved 2x2,Bayer interleaved 3x3,YUV422,YUV420 Y plane,YuV420 UV plane,YUV422 interleaved,YUV420 Y interleaved,YUV420 UV interleaved 9 ~,?,?,?,?,?,?,reserved" line.long 0x08 "NSF3V_DIM,Image block dimension" rbitfld.long 0x08 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x08 16.--29. 1. "IH,Image height in lines" rbitfld.long 0x08 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x08 0.--13. 1. "IW,Image width in pixels" line.long 0x0C "NSF3V_VPOUT_CTRL,Video port output control" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," hexmask.long.word 0x0C 0.--15. 1. "PCLK,Video port output data rate indicate that VPOUT EN signal should be sent functional clock * PCLK / 65536" line.long 0x10 "NSF3V_SHD_ST,Shading gain starting coordinate" rbitfld.long 0x10 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x10 16.--29. 1. "Y,shading gain starting Y coordinate" rbitfld.long 0x10 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x10 0.--13. 1. "X,shading gain starting X coordinate" line.long 0x14 "NSF3V_SHD_HA,Shading gain HA1/HA2" rbitfld.long 0x14 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 16.--28. 1. "HA2,shading gain HA2 coefficient" rbitfld.long 0x14 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 0.--12. 1. "HA1,shading gain HA1 coefficient" line.long 0x18 "NSF3V_SHD_VA,Shading gain VA1/VA2" rbitfld.long 0x18 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x18 16.--28. 1. "VA2,shading gain VA2 coefficient" rbitfld.long 0x18 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x18 0.--12. 1. "VA1,shading gain VA1 coefficient" line.long 0x1C "NSF3V_SHD_HSVS,Shading gain shift counts" rbitfld.long 0x1C 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x1C 28.--29. "VCS,Vshading gain VCS shift count only 1 or 2 allowed" "0,1,2,3" bitfld.long 0x1C 24.--27. "VS2,shading gain VS2 shift count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 20.--23. "VS1,shading gain VS1 bit count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x1C 14.--19. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 12.--13. "HCS,shading gain HCS shift count only 1 or 2 allowed" "0,1,2,3" newline bitfld.long 0x1C 8.--11. "HS2,shading gain HS2 bit count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 4.--7. "HS1,shading gain HS1 shift count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. "S0,shading gain S0 shift count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "NSF3V_SHD_ADJ,Shading gain adjustment" rbitfld.long 0x20 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x20 16.--28. 1. "OADJ,shading gain offset adjustment" hexmask.long.byte 0x20 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x20 0.--7. 1. "GADJ,shading gain gain adjustment unsigned" line.long 0x24 "NSF3V_SHD_MAXG,Max shading gain" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED," hexmask.long.word 0x24 0.--8. 1. "MAXG,Max shading gain" line.long 0x28 "NSF3V_TN_C00,Color 0 noise threshold" rbitfld.long 0x28 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x28 16.--26. 1. "S0_Y,segment 0 Y coordinate U11" rbitfld.long 0x28 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x28 0.--11. 1. "S0_X,segment 0 X coordinate U12 fixed to 0 (read-only)" line.long 0x2C "NSF3V_TN_C01,Color 0 noise threshold" rbitfld.long 0x2C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x2C 16.--27. 1. "S1_X,segment 1 X coordinate U12" rbitfld.long 0x2C 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x2C 0.--13. 1. "S0_S,segment 0 slope S3.11" line.long 0x30 "NSF3V_TN_C02,Color 0 noise threshold" rbitfld.long 0x30 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x30 16.--29. 1. "S1_S,segment 1 slope S3.11" rbitfld.long 0x30 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x30 0.--10. 1. "S1_Y,segment 1 Y coordinate U11" line.long 0x34 "NSF3V_TN_C03,Color 0 noise threshold" rbitfld.long 0x34 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x34 16.--26. 1. "S2_Y,segment 2 Y coordinate U11" rbitfld.long 0x34 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x34 0.--11. 1. "S2_X,segment 2 X coordinate U12" line.long 0x38 "NSF3V_TN_C04,Color 0 noise threshold" rbitfld.long 0x38 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x38 16.--27. 1. "S3_X,segment 3 X coordinate U12" rbitfld.long 0x38 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x38 0.--13. 1. "S2_S,segment 2 slope S3.11" line.long 0x3C "NSF3V_TN_C05,Color 0 noise threshold" rbitfld.long 0x3C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x3C 16.--29. 1. "S3_S,segment 3 slope S3.11" rbitfld.long 0x3C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x3C 0.--10. 1. "S3_Y,segment 3 Y coordinate U11" line.long 0x40 "NSF3V_TN_C10,Color 1 noise threshold" rbitfld.long 0x40 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x40 16.--26. 1. "S0_Y,segment 0 Y coordinate U11" rbitfld.long 0x40 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x40 0.--11. 1. "S0_X,segment 0 X coordinate U12 fixed to 0 (read-only)" line.long 0x44 "NSF3V_TN_C11,Color 1 noise threshold" rbitfld.long 0x44 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x44 16.--27. 1. "S1_X,segment 1 X coordinate U12" rbitfld.long 0x44 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x44 0.--13. 1. "S0_S,segment 0 slope S3.11" line.long 0x48 "NSF3V_TN_C12,Color 1 noise threshold" rbitfld.long 0x48 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x48 16.--29. 1. "S1_S,segment 1 slope S3.11" rbitfld.long 0x48 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 0.--10. 1. "S1_Y,segment 1 Y coordinate U11" line.long 0x4C "NSF3V_TN_C13,Color 1 noise threshold" rbitfld.long 0x4C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x4C 16.--26. 1. "S2_Y,segment 2 Y coordinate U11" rbitfld.long 0x4C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x4C 0.--11. 1. "S2_X,segment 2 X coordinate U12" line.long 0x50 "NSF3V_TN_C14,Color 1 noise threshold" rbitfld.long 0x50 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x50 16.--27. 1. "S3_X,segment 3 X coordinate U12" rbitfld.long 0x50 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x50 0.--13. 1. "S2_S,segment 2 slope S3.11" line.long 0x54 "NSF3V_TN_C15,Color 1 noise threshold" rbitfld.long 0x54 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x54 16.--29. 1. "S3_S,segment 3 slope S3.11" rbitfld.long 0x54 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x54 0.--10. 1. "S3_Y,segment 3 Y coordinate U11" line.long 0x58 "NSF3V_TN_C20,Color 2 noise threshold" rbitfld.long 0x58 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x58 16.--26. 1. "S0_Y,segment 0 Y coordinate U11" rbitfld.long 0x58 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x58 0.--11. 1. "S0_X,segment 0 X coordinate U12 fixed to 0 (read-only)" line.long 0x5C "NSF3V_TN_C21,Color 2 noise threshold" rbitfld.long 0x5C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x5C 16.--27. 1. "S1_X,segment 1 X coordinate U12" rbitfld.long 0x5C 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x5C 0.--13. 1. "S0_S,segment 0 slope S3.11" line.long 0x60 "NSF3V_TN_C22,Color 2 noise threshold" rbitfld.long 0x60 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x60 16.--29. 1. "S1_S,segment 1 slope S3.11" rbitfld.long 0x60 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x60 0.--10. 1. "S1_Y,segment 1 Y coordinate U11" line.long 0x64 "NSF3V_TN_C23,Color 2 noise threshold" rbitfld.long 0x64 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x64 16.--26. 1. "S2_Y,segment 2 Y coordinate U11" rbitfld.long 0x64 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x64 0.--11. 1. "S2_X,segment 2 X coordinate U12" line.long 0x68 "NSF3V_TN_C24,Color 2 noise threshold" rbitfld.long 0x68 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x68 16.--27. 1. "S3_X,segment 3 X coordinate U12" rbitfld.long 0x68 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x68 0.--13. 1. "S2_S,segment 2 slope S3.11" line.long 0x6C "NSF3V_TN_C25,Color 2 noise threshold" rbitfld.long 0x6C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x6C 16.--29. 1. "S3_S,segment 3 slope S3.11" rbitfld.long 0x6C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x6C 0.--10. 1. "S3_Y,segment 3 Y coordinate U11" line.long 0x70 "NSF3V_TN_C30,Color 3 noise threshold" rbitfld.long 0x70 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x70 16.--26. 1. "S0_Y,segment 0 Y coordinate U11" rbitfld.long 0x70 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x70 0.--11. 1. "S0_X,segment 0 X coordinate U12 fixed to 0 (read-only)" line.long 0x74 "NSF3V_TN_C31,Color 3 noise threshold" rbitfld.long 0x74 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x74 16.--27. 1. "S1_X,segment 1 X coordinate U12" rbitfld.long 0x74 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x74 0.--13. 1. "S0_S,segment 0 slope S3.11" line.long 0x78 "NSF3V_TN_C32,Color 3 noise threshold" rbitfld.long 0x78 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x78 16.--29. 1. "S1_S,segment 1 slope S3.11" rbitfld.long 0x78 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x78 0.--10. 1. "S1_Y,segment 1 Y coordinate U11" line.long 0x7C "NSF3V_TN_C33,Color 3 noise threshold" rbitfld.long 0x7C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x7C 16.--26. 1. "S2_Y,segment 2 Y coordinate U11" rbitfld.long 0x7C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x7C 0.--11. 1. "S2_X,segment 2 X coordinate U12" line.long 0x80 "NSF3V_TN_C34,Color 3 noise threshold" rbitfld.long 0x80 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x80 16.--27. 1. "S3_X,segment 3 X coordinate U12" rbitfld.long 0x80 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x80 0.--13. 1. "S2_S,segment 2 slope S3.11" line.long 0x84 "NSF3V_TN_C35,Color 3 noise threshold" rbitfld.long 0x84 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x84 16.--29. 1. "S3_S,segment 3 slope S3.11" rbitfld.long 0x84 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x84 0.--10. 1. "S3_Y,segment 3 Y coordinate U11" line.long 0x88 "NSF3V_TN_SCALE," hexmask.long.byte 0x88 24.--31. 1. "RESERVED," hexmask.long.byte 0x88 16.--23. 1. "TN3_TO_TN2,Scaling factor to get TN3 noise threshold for level 3 subbands U3.5" hexmask.long.byte 0x88 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x88 0.--7. 1. "TN1_TO_TN2,Scaling factor to get TN1 noise threshold for level 1 subbands U3.5" line.long 0x8C "NSF3V_THR_KNEE,Thresholding knee points" hexmask.long.byte 0x8C 24.--31. 1. "RESERVED," hexmask.long.byte 0x8C 16.--23. 1. "U3,Knee point u3 above which ee = ee_max" hexmask.long.byte 0x8C 8.--15. 1. "U2,Knee point u2 below which ee = 0" newline hexmask.long.byte 0x8C 0.--7. 1. "U1,Knee point u1 below which suppression = suppression_max" line.long 0x90 "NSF3V_SUP_C00,Color 0 suppression max" hexmask.long.byte 0x90 24.--31. 1. "L2_HH,Level 2 HH subband suppression_max U1.7" hexmask.long.byte 0x90 16.--23. 1. "L2_LH,Level 2 LH and HL subband suppression_max U1.7" hexmask.long.byte 0x90 8.--15. 1. "L1_HH,Level 1 HH subband suppression_max U1.7" newline hexmask.long.byte 0x90 0.--7. 1. "L1_LH,Level 1 LH and HL subband suppression_max U1.7" line.long 0x94 "NSF3V_SUP_C01,Color 0 suppression max" hexmask.long.word 0x94 16.--31. 1. "RESERVED," hexmask.long.byte 0x94 8.--15. 1. "L3_HH,Level 3 HH subband suppression_max U1.7" hexmask.long.byte 0x94 0.--7. 1. "L3_LH,Level 3 LH and HL subband suppression_max U1.7" line.long 0x98 "NSF3V_SUP_C10,Color 1 suppression max" hexmask.long.byte 0x98 24.--31. 1. "L2_HH,Level 2 HH subband suppression_max U1.7" hexmask.long.byte 0x98 16.--23. 1. "L2_LH,Level 2 LH and HL subband suppression_max U1.7" hexmask.long.byte 0x98 8.--15. 1. "L1_HH,Level 1 HH subband suppression_max U1.7" newline hexmask.long.byte 0x98 0.--7. 1. "L1_LH,Level 1 LH and HL subband suppression_max U1.7" line.long 0x9C "NSF3V_SUP_C11,Color 1 suppression max" hexmask.long.word 0x9C 16.--31. 1. "RESERVED," hexmask.long.byte 0x9C 8.--15. 1. "L3_HH,Level 3 HH subband suppression_max U1.7" hexmask.long.byte 0x9C 0.--7. 1. "L3_LH,Level 3 LH and HL subband suppression_max U1.7" line.long 0xA0 "NSF3V_SUP_C20,Color 2 suppression max" hexmask.long.byte 0xA0 24.--31. 1. "L2_HH,Level 2 HH subband suppression_max U1.7" hexmask.long.byte 0xA0 16.--23. 1. "L2_LH,Level 2 LH and HL subband suppression_max U1.7" hexmask.long.byte 0xA0 8.--15. 1. "L1_HH,Level 1 HH subband suppression_max U1.7" newline hexmask.long.byte 0xA0 0.--7. 1. "L1_LH,Level 1 LH and HL subband suppression_max U1.7" line.long 0xA4 "NSF3V_SUP_C21,Color 2 suppression max" hexmask.long.word 0xA4 16.--31. 1. "RESERVED," hexmask.long.byte 0xA4 8.--15. 1. "L3_HH,Level 3 HH subband suppression_max U1.7" hexmask.long.byte 0xA4 0.--7. 1. "L3_LH,Level 3 LH and HL subband suppression_max U1.7" line.long 0xA8 "NSF3V_SUP_C30,Color 3 suppression max" hexmask.long.byte 0xA8 24.--31. 1. "L2_HH,Level 2 HH subband suppression_max U1.7" hexmask.long.byte 0xA8 16.--23. 1. "L2_LH,Level 2 LH and HL subband suppression_max U1.7" hexmask.long.byte 0xA8 8.--15. 1. "L1_HH,Level 1 HH subband suppression_max U1.7" newline hexmask.long.byte 0xA8 0.--7. 1. "L1_LH,Level 1 LH and HL subband suppression_max U1.7" line.long 0xAC "NSF3V_SUP_C31,Color 3 suppression max" hexmask.long.word 0xAC 16.--31. 1. "RESERVED," hexmask.long.byte 0xAC 8.--15. 1. "L3_HH,Level 3 HH subband suppression_max U1.7" hexmask.long.byte 0xAC 0.--7. 1. "L3_LH,Level 3 LH and HL subband suppression_max U1.7" line.long 0xB0 "NSF3V_EE_C00,Color 0 edge enhancement max" rbitfld.long 0xB0 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xB0 16.--27. 1. "L1_HH,Level 1 HH suband ee_max U10.2" rbitfld.long 0xB0 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xB0 0.--11. 1. "L1_LH,Level 1 LH and HL subband ee_max U10.2" line.long 0xB4 "NSF3V_EE_C01,Color 0 edge enhancement max" rbitfld.long 0xB4 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xB4 16.--27. 1. "L2_HH,Level 2 HH suband ee_max U10.2" rbitfld.long 0xB4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xB4 0.--11. 1. "L2_LH,Level 2 LH and HL subband ee_max U10.2" line.long 0xB8 "NSF3V_EE_C02,Color 0 edge enhancement max" rbitfld.long 0xB8 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xB8 16.--27. 1. "L3_HH,Level 3 HH suband ee_max U10.2" rbitfld.long 0xB8 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xB8 0.--11. 1. "L3_LH,Level 3 LH and HL subband ee_max U10.2" line.long 0xBC "NSF3V_EE_C10,Color 1 edge enhancement max" rbitfld.long 0xBC 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xBC 16.--27. 1. "L1_HH,Level 1 HH suband ee_max U10.2" rbitfld.long 0xBC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xBC 0.--11. 1. "L1_LH,Level 1 LH and HL subband ee_max U10.2" line.long 0xC0 "NSF3V_EE_C11,Color 1 edge enhancement max" rbitfld.long 0xC0 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC0 16.--27. 1. "L2_HH,Level 2 HH suband ee_max U10.2" rbitfld.long 0xC0 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC0 0.--11. 1. "L2_LH,Level 2 LH and HL subband ee_max U10.2" line.long 0xC4 "NSF3V_EE_C12,Color 1 edge enhancement max" rbitfld.long 0xC4 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC4 16.--27. 1. "L3_HH,Level 3 HH suband ee_max U10.2" rbitfld.long 0xC4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC4 0.--11. 1. "L3_LH,Level 3 LH and HL subband ee_max U10.2" line.long 0xC8 "NSF3V_EE_C20,Color 2 edge enhancement max" rbitfld.long 0xC8 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC8 16.--27. 1. "L1_HH,Level 1 HH suband ee_max U10.2" rbitfld.long 0xC8 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC8 0.--11. 1. "L1_LH,Level 1 LH and HL subband ee_max U10.2" line.long 0xCC "NSF3V_EE_C21,Color 2 edge enhancement max" rbitfld.long 0xCC 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xCC 16.--27. 1. "L2_HH,Level 2 HH suband ee_max U10.2" rbitfld.long 0xCC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xCC 0.--11. 1. "L2_LH,Level 2 LH and HL subband ee_max U10.2" line.long 0xD0 "NSF3V_EE_C22,Color 2 edge enhancement max" rbitfld.long 0xD0 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xD0 16.--27. 1. "L3_HH,Level 3 HH suband ee_max U10.2" rbitfld.long 0xD0 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD0 0.--11. 1. "L3_LH,Level 3 LH and HL subband ee_max U10.2" line.long 0xD4 "NSF3V_EE_C30,Color 3 edge enhancement max" rbitfld.long 0xD4 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xD4 16.--27. 1. "L1_HH,Level 1 HH suband ee_max U10.2" rbitfld.long 0xD4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD4 0.--11. 1. "L1_LH,Level 1 LH and HL subband ee_max U10.2" line.long 0xD8 "NSF3V_EE_C31,Color 3 edge enhancement max" rbitfld.long 0xD8 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xD8 16.--27. 1. "L2_HH,Level 2 HH suband ee_max U10.2" rbitfld.long 0xD8 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD8 0.--11. 1. "L2_LH,Level 2 LH and HL subband ee_max U10.2" line.long 0xDC "NSF3V_EE_C32,Color 3 edge enhancement max" rbitfld.long 0xDC 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xDC 16.--27. 1. "L3_HH,Level 3 HH suband ee_max U10.2" rbitfld.long 0xDC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xDC 0.--11. 1. "L3_LH,Level 3 LH and HL subband ee_max U10.2" line.long 0xE0 "NSF3V_DS_THR,Desaturation thresholds" hexmask.long.word 0xE0 22.--31. 1. "RESERVED," bitfld.long 0xE0 16.--21. "THR2,desaturation threshold 2 U6.0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0xE0 6.--15. 1. "RESERVED," newline bitfld.long 0xE0 0.--5. "THR1,desaturation threhsold 1 U6.0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0xE4 "NSF3V_DS_SLOPE,Desaturation slopes" rbitfld.long 0xE4 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0xE4 16.--25. 1. "SLOPE2,desaturation slope 2 U0.10" rbitfld.long 0xE4 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xE4 0.--9. 1. "SLOPE1,desaturation slope 1 U0.10" width 0x0B tree.end tree "ISP6P5_RESIZER" base ad:0x52040400 rgroup.long 0x00++0x17 line.long 0x00 "RSZ_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "RSZ_SYSCONFIG,SYSTEM CONFIGURATION REGISTER This register is not shadowed" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "RSZB_CLK_EN,Resizer B clock enable This bit enable to enable / disable the RESIZER B clock" "RSZB_CLK_EN_0,RSZB_CLK_EN_1" newline bitfld.long 0x04 8. "RSZA_CLK_EN,Resizer A clock enable This bit enable to enable / disable the RESIZER A clock" "RSZA_CLK_EN_0,RSZA_CLK_EN_1" rbitfld.long 0x04 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x04 1. "RESERVED," "0,1" bitfld.long 0x04 0. "AUTOGATING,Internal Clock Gating Strategy Enables or disables auto clock gating" "AUTOGATING_0,AUTOGATING_1" line.long 0x08 "RSZ_SYSSTATUS,SYSTEM STATUS REGISTER This register is not shadowed" hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "RESERVED," "0,1" line.long 0x0C "RSZ_IN_FIFO_CTRL,INPUT DATA BUFFER CONTROL REGISTER This register is not shadowed" rbitfld.long 0x0C 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 16.--28. 1. "THRLD_LOW,WhenRSZ_IN_FIFO_CTRL.THRLD_HIGH = RSZ_IN_FIFO_CTRL.THRLD_LOW the rsz_stall_input is not asserted" newline rbitfld.long 0x0C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 0.--12. 1. "THRLD_HIGH,High threshold value" line.long 0x10 "RSZ_GNC,GENERIC PARAMETER REGISTER" bitfld.long 0x10 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 16.--28. 1. "RSZB_MEM_LINE_SIZE,Resizer #B memory line size (pixels)" newline bitfld.long 0x10 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--12. 1. "RSZA_MEM_LINE_SIZE,Resizer #A memory line size (pixels)" line.long 0x14 "RSZ_FRACDIV,Fractional clock divider settings" hexmask.long.word 0x14 16.--31. 1. "RESERVED," hexmask.long.word 0x14 0.--15. 1. "RSZ_FRACDIV,Fractional clock divider value" group.long 0x20++0x2F line.long 0x00 "RSZ_SRC_EN,RESIZER ENABLE REGISTER This register is not shadowed" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "EN,Resizer module enable The start flag of the RESIZER module" "EN_0,EN_1" line.long 0x04 "RSZ_SRC_MODE,This register is not shadowed" hexmask.long 0x04 2.--31. 1. "RESERVED," bitfld.long 0x04 1. "WRT,Video port WEN signal selection This bit selects whether the WEN signal which is present on the IPIPE and IPIPEIF video port is used or not to select the input data" "WRT_0,WRT_1" newline bitfld.long 0x04 0. "OST,The processing mode selection of the RESIZER module" "OST_0,OST_1" line.long 0x08 "RSZ_SRC_FMT0,This register is not shadowed" hexmask.long 0x08 2.--31. 1. "RESERVED," bitfld.long 0x08 1. "BYPASS,Pass Through This bit enables or disables the RESIZER module pass through mode" "BYPASS_0,BYPASS_1" newline bitfld.long 0x08 0. "SEL,Input selection This bit selects which of the two video port is selected to push data through the RESIZER module" "SEL_0,SEL_1" line.long 0x0C "RSZ_SRC_FMT1," hexmask.long 0x0C 4.--31. 1. "RESERVED," bitfld.long 0x0C 3. "CHR,Cb/Cr order Note: This is only for OMA5430 This bit indicates if Cb/Cr is flipped" "Normal,Flipped" newline bitfld.long 0x0C 2. "COL,Y/C selection This bit is valid only if the input data is YUV420 (IN420 = '1')" "COL_0,COL_1" bitfld.long 0x0C 1. "IN420,Chroma Format Selection This bit sets the chroma undersampling when YUV data is input to the RESIZER module" "IN420_0,IN420_1" newline bitfld.long 0x0C 0. "RAW,Pass-through mode input data format selection This bit affects the horizontal reversal (flipping) process" "RAW_0,RAW_1" line.long 0x10 "RSZ_SRC_VPS,VERTICAL POSITION REGISTER This register is not shadowed" hexmask.long.word 0x10 16.--31. 1. "RESERVED," hexmask.long.word 0x10 0.--15. 1. "VPS,Vertical Start Position Sets the vertical position of the global frame from the rising edge of the VD" line.long 0x14 "RSZ_SRC_VSZ,VERTICAL SIZER REGISTER" hexmask.long.tbyte 0x14 13.--31. 1. "RESERVED," hexmask.long.word 0x14 0.--12. 1. "VSZ,Vertical Processing Size Sets the vertical size of the processing area" line.long 0x18 "RSZ_SRC_HPS,HORIZONTAL POSITION REGISTER This register is not shadowed" hexmask.long.word 0x18 16.--31. 1. "RESERVED," hexmask.long.word 0x18 0.--15. 1. "HPS,Horizontal Start Position TheRSZ_SRC_HPS register has two functions" line.long 0x1C "RSZ_SRC_HSZ,HORIZONTAL SIZE REGISTER The HSZ value is given by HSZ concatenated with HSZ_LSB" hexmask.long.tbyte 0x1C 13.--31. 1. "RESERVED," hexmask.long.word 0x1C 0.--12. 1. "HSZ,Horizontal size Sets the horizontal size of the processing area" line.long 0x20 "RSZ_DMA_RZA,RESIZER A - MEMORY REQUEST MINIMUM INTERVAL REGISTER" hexmask.long.word 0x20 16.--31. 1. "RESERVED," hexmask.long.word 0x20 0.--15. 1. "RZA,Sets the minimum inteval btw two consecutive memory request for resizer #A" line.long 0x24 "RSZ_DMA_RZB,RESIZER B - MEMORY REQUEST MINIMUM INTERVAL REGISTER" hexmask.long.word 0x24 16.--31. 1. "RESERVED," hexmask.long.word 0x24 0.--15. 1. "RZB,Sets the minimum inteval btw two consecutive memory request for resizer #B" line.long 0x28 "RSZ_DMA_STA,RESIZER STATUS REGISTER" hexmask.long 0x28 1.--31. 1. "RESERVED," bitfld.long 0x28 0. "STATUS,Resizer process status This bit is set in the time window from rsz_int_reg to rsz_int_dma" "STATUS_0,STATUS_1" line.long 0x2C "RSZ_GCK_MMR,MMR CLOCK CONTROL REGISTER This register is not shadowed" hexmask.long 0x2C 1.--31. 1. "RESERVED," bitfld.long 0x2C 0. "MMR,The on/off selection of the MMR interface clock which is used for MMR register access" "MMR_0,MMR_1" group.long 0x54++0x143 line.long 0x00 "RSZ_GCK_SDR,CORE CLOCK CONTROL REGISTER This register is not shadowed" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "CORE,RSZ Core Clock Enable" "CORE_0,CORE_1" line.long 0x04 "RSZ_IRQ_RZA,RESIZER A - CIRCULAR BUFFER INTERRUPT INTERVAL REGISTER" hexmask.long.byte 0x04 25.--31. 1. "RESERVED," bitfld.long 0x04 24. "ICMA_CTRL_COL,Choose luma done (P_DONE_A) or chroma done (P_DONE_AC) to control" "ICMA_CTRL_COL_0,ICMA_CTRL_COL_1" newline rbitfld.long 0x04 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x04 21. "ICMA_CHR_EOF,Enable the generation of P_DONE_AC pulse at the end of each frame if the height is not a multiple of RZA" "ICMA_CHR_EOF_0,ICMA_CHR_EOF_1" newline bitfld.long 0x04 20. "ICMA_CHR_EN,Enable hand-shaking with ICM (RSZ-A) in Chroma Channel This is only valid in YUV-420 mode with chroma output" "ICMA_CHR_EN_0,ICMA_CHR_EN_1" rbitfld.long 0x04 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 17. "ICMA_EOF,Enable the generation of P_DONE_A pulse at the end of each frame if the height is not a multiple of RZA" "ICMA_EOF_0,ICMA_EOF_1" bitfld.long 0x04 16. "ICMA_EN,Enable hand-shaking with ICM (RSZ-A)" "ICMA_EN_0,ICMA_EN_1" newline rbitfld.long 0x04 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 0.--12. 1. "RZA,Resizer A circular buffer interval" line.long 0x08 "RSZ_IRQ_RZB,RESIZER B - CIRCULAR BUFFER INTERRUPT INTERVAL REGISTER" hexmask.long.byte 0x08 25.--31. 1. "RESERVED," bitfld.long 0x08 24. "ICMB_CTRL_COL,Choose luma done (P_DONE_B) or chroma done (P_DONE_BC) to control" "ICMB_CTRL_COL_0,ICMB_CTRL_COL_1" newline rbitfld.long 0x08 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x08 21. "ICMB_CHR_EOF,Enable the generation of P_DONE_BC pulse at the end of each frame if the height is not a multiple of RZB" "ICMB_CHR_EOF_0,ICMB_CHR_EOF_1" newline bitfld.long 0x08 20. "ICMB_CHR_EN,Enable hand-shaking with ICM (RSZ-B) in Chroma Channel This is only valid in YUV-420 mode with chroma output" "ICMB_CHR_EN_0,ICMB_CHR_EN_1" rbitfld.long 0x08 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 17. "ICMB_EOF,Enable the generation of P_DONE_B pulse at the end of each frame if the height is not a multiple of RZB" "ICMB_EOF_0,ICMB_EOF_1" bitfld.long 0x08 16. "ICMB_EN,Enalbe handshake between RSZB and ICM" "ICMB_EN_0,ICMB_EN_1" newline rbitfld.long 0x08 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--12. 1. "RZB,Resizer B circular buffer interval" line.long 0x0C "RSZ_YUV_Y_MIN,LUMINANCE SATURATION REGISTER" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED," hexmask.long.byte 0x0C 0.--7. 1. "MIN,The minimum value of Luminance (8bits unsigned)" line.long 0x10 "RSZ_YUV_Y_MAX,LUMINANCE SATURATION REGISTER" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED," hexmask.long.byte 0x10 0.--7. 1. "MAX,The maximum value of Luminance (8bits unsigned)" line.long 0x14 "RSZ_YUV_C_MIN,CHROMINANCE SATURATION REGISTER" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," hexmask.long.byte 0x14 0.--7. 1. "MIN,The minimum value of Chrominance (8bits unsigned)" line.long 0x18 "RSZ_YUV_C_MAX,CHROMINANCE SATURATION REGISTER" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," hexmask.long.byte 0x18 0.--7. 1. "MAX,The maximum value of Chrominance (8bits unsigned)" line.long 0x1C "RSZ_YUV_PHS,The phase position of the output of the Chrominance" hexmask.long 0x1C 1.--31. 1. "RESERVED," bitfld.long 0x1C 0. "POS,The phase position of the output of the chrominance" "POS_0,POS_1" line.long 0x20 "RSZ_SEQ," hexmask.long 0x20 5.--31. 1. "RESERVED," bitfld.long 0x20 4. "CRV,Chroma sampling point change" "CRV_0,CRV_1" newline bitfld.long 0x20 3. "VRVB,Resizer B - Vertical reversal of output image" "VRVB_0,VRVB_1" bitfld.long 0x20 2. "HRVB,Resizer B -Horizontal reversal of output image" "HRVB_0,HRVB_1" newline bitfld.long 0x20 1. "VRVA,Resizer A - Vertical reversal of output image" "VRVA_0,VRVA_1" bitfld.long 0x20 0. "HRVA,Resizer A - Horizontal reversal of output image" "HRVA_0,HRVA_1" line.long 0x24 "RZA_EN,RESIZER A - ENABLE REGISTER" hexmask.long 0x24 1.--31. 1. "RESERVED," bitfld.long 0x24 0. "EN,Enable resizer #A This bit is latched on video port VD input" "EN_0,EN_1" line.long 0x28 "RZA_MODE,RESIZER #A MODE REGISTER" hexmask.long 0x28 1.--31. 1. "RESERVED," bitfld.long 0x28 0. "MODE,Select 'Free Run mode' or 'One Shot Mode'" "MODE_0,MODE_1" line.long 0x2C "RZA_420,YEN/CEN" hexmask.long 0x2C 2.--31. 1. "RESERVED," bitfld.long 0x2C 1. "CEN,Output Enable for Chrominance This bit is valid in 422 input mode.When CEN=0 and YEN=0 output is 422" "CEN_0,CEN_1" newline bitfld.long 0x2C 0. "YEN,Output Enable for Luminance This bit is valid in 422 input mode.When CEN=0 and YEN=0 output is 422" "YEN_0,YEN_1" line.long 0x30 "RZA_I_VPS,RESIZER A - INPUT VERTICAL START REGISTER Note: The height of the image after the second crop must be 2 or larger" hexmask.long.tbyte 0x30 13.--31. 1. "RESERVED," hexmask.long.word 0x30 0.--12. 1. "VPS,Input Vertical Position Sets the vertical start position of the input image within the global frame" line.long 0x34 "RZA_I_HPS,RESIZER A - INPUT HORIZONTAL START REGISTER" hexmask.long.tbyte 0x34 13.--31. 1. "RESERVED," hexmask.long.word 0x34 0.--12. 1. "HPS,Input Horizontal Position Sets the horizontal position of the first pixel for each line within the global frame" line.long 0x38 "RZA_O_VSZ,RESIZER A - OUTPUT VERTICAL SIZE REGISTER In 422 to 420 mode. chorma output lines number is 1/2 of this value" hexmask.long.tbyte 0x38 13.--31. 1. "RESERVED," hexmask.long.word 0x38 0.--12. 1. "VSZ,The target output size of the resized image" line.long 0x3C "RZA_O_HSZ,RESIZER A - OUTPUT HORIZONTAL SIZE REGISTER When CNFA is enabled. this value must be - Same as CNFA width. if CDS is off" hexmask.long.tbyte 0x3C 13.--31. 1. "RESERVED," hexmask.long.word 0x3C 1.--12. 1. "HSZ,The horizontal size of output image" newline rbitfld.long 0x3C 0. "HSZ_LSB,The least significant bit of HSZ is forced to 1" "0,1" line.long 0x40 "RZA_V_PHS_Y,RESIZER A - INITIAL LUMINANCE PHASE OF VERTICAL RESIZING PROCESS When YUV422 data are output. the phase values for luma and chroma should typicall be equal. i.e.. RZX_V_PHS_Y= RZX_V_PHS_C" hexmask.long.tbyte 0x40 14.--31. 1. "RESERVED," hexmask.long.word 0x40 0.--13. 1. "Y,The initial value for the luma phase in vertical resizing process" line.long 0x44 "RZA_V_PHS_C,RESIZER A - INITIAL CHROMINANCE PHASE OF VERTICAL RESIZING PROCESS When YUV422 data are output. the phase values for luma and chroma should typicall be equal. i.e.. RZX_V_PHS_Y= RZX_V_PHS_C" hexmask.long.tbyte 0x44 14.--31. 1. "RESERVED," hexmask.long.word 0x44 0.--13. 1. "C,The initial value for the chroma phase in vertical resizing process" line.long 0x48 "RZA_V_DIF,RESIZER A - VERTICAL RESIZER REGISTER" hexmask.long.tbyte 0x48 14.--31. 1. "RESERVED," abitfld.long 0x48 0.--13. "V,The parameter for vertical resize" "0x0010=RZA_V_DIF = 4096,0x0100=RZA_V_DIF = 4096" line.long 0x4C "RZA_V_TYP,RESIZER A - INTERPOLATION METHOD FOR VERTICAL RESIZING" hexmask.long 0x4C 2.--31. 1. "RESERVED," bitfld.long 0x4C 1. "C,Selection of resizing method for" "C_0,C_1" newline bitfld.long 0x4C 0. "Y,Selection of resizing method for luminance: vertical" "Y_0,Y_1" line.long 0x50 "RZA_V_LPF,RESIZER A - VERTICAL LPF INTENSITY REGISTER" hexmask.long.tbyte 0x50 12.--31. 1. "RESERVED," bitfld.long 0x50 6.--11. "C,The intensity parameter for chroma vertical low pass filtering" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x50 0.--5. "Y,The intensity parameter for luma vertical low pass filtering" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x54 "RZA_H_PHS,RESIZER A - INITIAL PHASE OF HORIZONTAL RESIZING PROCESS" hexmask.long.tbyte 0x54 14.--31. 1. "RESERVED," hexmask.long.word 0x54 0.--13. 1. "PHS,Initial value for the phase in horizontal resizing process i.e. the sampling position is shifted" line.long 0x58 "RZA_H_PHS_ADJ,RESIZER A - LUMINANCE HORIZONTAL PHASE ADJUSTMENT The register enables to adjust the horizontal phase for the luma component when averaging is enabled (the horizontal averaging disrupts the relative sampling point between luminance and.." hexmask.long.tbyte 0x58 9.--31. 1. "RESERVED," hexmask.long.word 0x58 0.--8. 1. "ADJ,Horizontal phase adjustment value" line.long 0x5C "RZA_H_DIF,RESIZER A - HORIZONTAL RESIZER REGISTER" hexmask.long.tbyte 0x5C 14.--31. 1. "RESERVED," abitfld.long 0x5C 0.--13. "H,The parameter for horizontal resizing process" "0x0010=RSZ_RZA_H_DIF =4096 In down-scale mode,0x0100=RSZ_RZA_H_DIF =4096" line.long 0x60 "RZA_H_TYP,Resize-A" hexmask.long 0x60 2.--31. 1. "RESERVED," bitfld.long 0x60 1. "C,Selection of resizing method for" "C_0,C_1" newline bitfld.long 0x60 0. "Y,Selection of resizing method for luminance: horizontal" "Y_0,Y_1" line.long 0x64 "RZA_H_LPF,RESIZER A - HORIZONTAL LPF INTENSITY REGISTER" hexmask.long.tbyte 0x64 12.--31. 1. "RESERVED," bitfld.long 0x64 6.--11. "C,Horizontal LPF Intensity for Chrominance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x64 0.--5. "Y,Selection of resizing method for Luminance in horizontal direction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x68 "RZA_DWN_EN,RESIZER #A - DOWNSCALE ENABLE REGISTER" hexmask.long 0x68 1.--31. 1. "RESERVED," bitfld.long 0x68 0. "DWN_EN,Resizer downscale enable" "DWN_EN_0,DWN_EN_1" line.long 0x6C "RZA_DWN_AV,Resize-A" hexmask.long 0x6C 6.--31. 1. "RESERVED," bitfld.long 0x6C 3.--5. "V,Vertical averaging size : 1/2^(VWT+1) The range goes from 1/2 to 1/256 in power of two" "_DIV21/2 down scale,_DIV41/4 down scale,_DIV81/8 down scale,_DIV161/16 down scale,_DIV321/32 down scale,_DIV641/64 down scale,_DIV1281/128 down scale,_DIV2561/256 down scale" newline bitfld.long 0x6C 0.--2. "H,Horizontal averaging size : 1/2^(HWT+1) The range goes from 1/2 to 1/256 in power of two" "_DIV21/2 down scale,_DIV41/4 down scale,_DIV81/8 down scale,_DIV161/16 down scale,_DIV321/32 down scale,_DIV641/64 down scale,_DIV1281/128 down scale,_DIV2561/256 down scale" line.long 0x70 "RZA_RGB_EN,RESIZER #A - RGB OUTPUT ENABLE" hexmask.long 0x70 1.--31. 1. "RESERVED," bitfld.long 0x70 0. "RGB_EN,Enable of RGB output In pass through mode this register must be 0" "RGB_EN_0,RGB_EN_1" line.long 0x74 "RZA_RGB_TYP,RESIZER A - RGB OUTPUT CONTROL REGISTER" hexmask.long 0x74 3.--31. 1. "RESERVED," bitfld.long 0x74 2. "MSK1,Enables masking of the last 2 pixels This bit is used to mask the 2 last pixels at the image boundary which are affected by the YUV422 to YUV444 conversion" "MSK1_0,MSK1_1" newline bitfld.long 0x74 1. "MSK0,Enables masking of the first 2 pixels This bit is used to mask the 2 first pixels at the image boundary which are affected by the YUV422 to YUV444 conversion" "MSK0_0,MSK0_1" bitfld.long 0x74 0. "TYP,16bit/32bit output selection" "TYP_0,TYP_1" line.long 0x78 "RZA_RGB_BLD,RESIZER A - RGB BLEND REGISTER" hexmask.long.tbyte 0x78 8.--31. 1. "RESERVED," hexmask.long.byte 0x78 0.--7. 1. "BLD,The alpha value used in 32-bit RGBA output mode" line.long 0x7C "RZA_SDR_Y_BAD_H,RESIZER A - OUTPUT MEMORY BASE ADDRESS REGISTER (HIGH) This register is used if the output data format is one of the following: RAW. YUV422. YUV420. RGB565. RGBA" hexmask.long.word 0x7C 16.--31. 1. "RESERVED," hexmask.long.word 0x7C 0.--15. 1. "Y_BAD_H,Memory Base Address Sets the 16 upper bits of the 32-bit base address of the circular buffer in memory" line.long 0x80 "RZA_SDR_Y_BAD_L,RESIZER A - OUTPUT MEMORY BASE ADDRESS REGISTER (LOW) This register is used if the output data format is one of the following: RAW. YUV422. YUV420. RGB565. RGBA" hexmask.long.word 0x80 16.--31. 1. "RESERVED," hexmask.long.word 0x80 0.--15. 1. "Y_BAD_L,Memory Base Address Sets the 16 lower bits of the 32-bit base address of the circular buffer in memory" line.long 0x84 "RZA_SDR_Y_SAD_H,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER (HIGH) This register is used if the output data format is one of the following: RAW. YUV422. YUV420. RGB565. RGBA" hexmask.long.word 0x84 16.--31. 1. "RESERVED," hexmask.long.word 0x84 0.--15. 1. "Y_SAD_H,Memory Start Address Sets the 16 upper bits of the 32-bit start address in memory" line.long 0x88 "RZA_SDR_Y_SAD_L,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER (LOW) This register is used if the output data format is one of the following: RAW. YUV422. YUV420. RGB565. RGBA" hexmask.long.word 0x88 16.--31. 1. "RESERVED," hexmask.long.word 0x88 0.--15. 1. "Y_SAD_L,Memory Start Address Sets 16 lower bits of the 32-bit start address in memory" line.long 0x8C "RZA_SDR_Y_OFT,RESIZER A - OUTPUT MEMORY OFFSET REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420 or RGBA" hexmask.long.word 0x8C 17.--31. 1. "RESERVED," hexmask.long.tbyte 0x8C 0.--16. 1. "Y_OFT,Memory Line Offset Sets the size of each line in the circular buffer" line.long 0x90 "RZA_SDR_Y_PTR_S,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420 or RGBA" hexmask.long.tbyte 0x90 13.--31. 1. "RESERVED," hexmask.long.word 0x90 0.--12. 1. "Y_PTR_S,Start Line of Memory Pointer Sets the vertical position of the first output line in the output memory space" line.long 0x94 "RZA_SDR_Y_PTR_E,RESIZER A - OUTPUT MEMORY END ADDRESS REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420 or RGBA" hexmask.long.tbyte 0x94 13.--31. 1. "RESERVED," hexmask.long.word 0x94 0.--12. 1. "Y_PTR_E,End Line of Memory Pointer Sets the maximum number of lines to be stored in the output memory space" line.long 0x98 "RZA_SDR_C_BAD_H,RESIZER A - OUTPUT MEMORY BASE ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0x98 16.--31. 1. "RESERVED," hexmask.long.word 0x98 0.--15. 1. "C_BAD_H,Memory Base Address Sets the 16 higher bits of the 32-bit base address of the circular buffer in memory" line.long 0x9C "RZA_SDR_C_BAD_L,RESIZER A - OUTPUT MEMORY BASE ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0x9C 16.--31. 1. "RESERVED," hexmask.long.word 0x9C 0.--15. 1. "C_BAD_L,Memory Base Address Sets the 16 lower bits of the 32-bit base address of the circular buffer in memory" line.long 0xA0 "RZA_SDR_C_SAD_H,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0xA0 16.--31. 1. "RESERVED," hexmask.long.word 0xA0 0.--15. 1. "C_SAD_H,Memory Base Address Sets the 16 higher bits of the 32-bit start address in memory" line.long 0xA4 "RZA_SDR_C_SAD_L,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0xA4 16.--31. 1. "RESERVED," hexmask.long.word 0xA4 0.--15. 1. "C_SAD_L,Memory Base Address Sets the 16 lower bits of the 32-bit start address in memory" line.long 0xA8 "RZA_SDR_C_OFT,RESIZER A - OUTPUT MEMORY OFFSET REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0xA8 17.--31. 1. "RESERVED," hexmask.long.tbyte 0xA8 0.--16. 1. "C_OFT,Memory Line Offset Sets the size of each line in the circular buffer" line.long 0xAC "RZA_SDR_C_PTR_S,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.tbyte 0xAC 13.--31. 1. "RESERVED," hexmask.long.word 0xAC 0.--12. 1. "C_PTR_S,Start Line of Memory Pointer Sets the vertical position of the first output line in the output memory space" line.long 0xB0 "RZA_SDR_C_PTR_E,RESIZER A - OUTPUT MEMORY END ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.tbyte 0xB0 13.--31. 1. "RESERVED," hexmask.long.word 0xB0 0.--12. 1. "C_PTR_E,End Line of Memory Pointer Sets the maximum number of lines to be stored in the output memory space" line.long 0xB4 "RZB_EN,RESIZER B - ENABLE REGISTER" hexmask.long 0xB4 1.--31. 1. "RESERVED," bitfld.long 0xB4 0. "EN,Enable resizer #A This bit is latched on the video port VD input signal" "EN_0,EN_1" line.long 0xB8 "RZB_MODE,RESIZER B MODE REGISTER" hexmask.long 0xB8 1.--31. 1. "RESERVED," bitfld.long 0xB8 0. "MODE,Select 'Free Run mode' or 'One Shot Mode'" "MODE_0,MODE_1" line.long 0xBC "RZB_420,YEN/CEN" hexmask.long 0xBC 2.--31. 1. "RESERVED," bitfld.long 0xBC 1. "CEN,Output Enable for Chrominance This bit is valid in 422 input mode.When CEN=0 and YEN=0 output is 422" "CEN_0,CEN_1" newline bitfld.long 0xBC 0. "YEN,Output Enable for Luminance This bit is valid in 422 input mode.When CEN=0 and YEN=0 output is 422" "YEN_0,YEN_1" line.long 0xC0 "RZB_I_VPS,RESIZER B - INPUT VERTICAL START REGISTER Note: The height of the image after the second crop must be 2 or larger" hexmask.long.tbyte 0xC0 13.--31. 1. "RESERVED," hexmask.long.word 0xC0 0.--12. 1. "VPS,Input Vertical Position Sets the vertical start position of the input image within the global frame" line.long 0xC4 "RZB_I_HPS,RESIZER B - INPUT HORIZONTAL START REGISTER" hexmask.long.tbyte 0xC4 13.--31. 1. "RESERVED," hexmask.long.word 0xC4 0.--12. 1. "HPS,Input Horizontal Position Sets the horizontal position of the first pixel for each line within the global frame" line.long 0xC8 "RZB_O_VSZ,RESIZER B - OUTPUT VERTICAL SIZER REGISTER In 422 to 420 mode. chorma output lines number is 1/2 of this value" hexmask.long.tbyte 0xC8 13.--31. 1. "RESERVED," hexmask.long.word 0xC8 0.--12. 1. "VSZ,The target output size of the resized image" line.long 0xCC "RZB_O_HSZ,RESIZER B - OUTPUT HORIZONTAL SIZE REGISTER When CNFB is enabled. this value must be - Same as CNFB width. if CDS is off" hexmask.long.tbyte 0xCC 13.--31. 1. "RESERVED," hexmask.long.word 0xCC 1.--12. 1. "HSZ,The horizontal size of output image" newline rbitfld.long 0xCC 0. "HSZ_LSB,The least significant bit of HSZ is forced to 1" "0,1" line.long 0xD0 "RZB_V_PHS_Y,RESIZER B - INITIAL LUMINANCE PHASE OF VERTICAL RESIZING PROCESS When YUV422 data are output. the phase values for luma and chroma should typicall be equal. i.e.. RZX_V_PHS_Y= RZX_V_PHS_C" hexmask.long.tbyte 0xD0 14.--31. 1. "RESERVED," hexmask.long.word 0xD0 0.--13. 1. "Y,The initial value for the luma phase in vertical resizing process" line.long 0xD4 "RZB_V_PHS_C,RESIZER B - INITIAL CHROMINANCE PHASE OF VERTICAL RESIZING PROCESS When YUV422 data are output. the phase values for luma and chroma should typicall be equal. i.e.. RZX_V_PHS_Y= RZX_V_PHS_C" hexmask.long.tbyte 0xD4 14.--31. 1. "RESERVED," hexmask.long.word 0xD4 0.--13. 1. "C,The initial value for the chroma phase in vertical resizing process" line.long 0xD8 "RZB_V_DIF,RESIZER B - VERTICAL RESIZER REGISTERR" hexmask.long.tbyte 0xD8 14.--31. 1. "RESERVED," abitfld.long 0xD8 0.--13. "V,The parameter for vertical resize" "0x0010=RZB_V_DIF = 4096,0x0100=RZB_V_DIF = 4096" line.long 0xDC "RZB_V_TYP,RESIZER B - INTERPOLATION METHOD FOR VERTICAL RESIZING" hexmask.long 0xDC 2.--31. 1. "RESERVED," bitfld.long 0xDC 1. "C,Selection of resizing method for" "C_0,C_1" newline bitfld.long 0xDC 0. "Y,Selection of resizing method for luminance: vertical" "Y_0,Y_1" line.long 0xE0 "RZB_V_LPF,RESIZER B - VERTICAL LPF INTENSITY REGISTER" hexmask.long.tbyte 0xE0 12.--31. 1. "RESERVED," bitfld.long 0xE0 6.--11. "C,The intensity parameter for chroma vertical low pass filtering" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0xE0 0.--5. "Y,The intensity parameter for luma vertical low pass filtering" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0xE4 "RZB_H_PHS,RESIZER B - INITIAL PHASE OF HORIZONTAL RESIZING PROCESS" hexmask.long.tbyte 0xE4 14.--31. 1. "RESERVED," hexmask.long.word 0xE4 0.--13. 1. "PHS,Initial value for the phase in horizontal resizing process i.e. the sampling position is shifted" line.long 0xE8 "RZB_H_PHS_ADJ,RESIZER B - LUMINANCE HORIZONTAL PHASE ADJUSTMENT The register enables to adjust the horizontal phase for the luma component when averaging is enabled (the horizontal averaging disrupts the relative sampling point between luminance and.." hexmask.long.tbyte 0xE8 9.--31. 1. "RESERVED," hexmask.long.word 0xE8 0.--8. 1. "ADJ,Horizontal phase adjustment value" line.long 0xEC "RZB_H_DIF,RESIZER B - HORIZONTAL RESIZER REGISTER" hexmask.long.tbyte 0xEC 14.--31. 1. "RESERVED," abitfld.long 0xEC 0.--13. "H,The parameter for horizontal resizing process" "0x0010=RSZ_RZA_H_DIF =4096 In down-scale mode,0x0100=RSZ_RZA_H_DIF =4096" line.long 0xF0 "RZB_H_TYP,RESIZER B" hexmask.long 0xF0 2.--31. 1. "RESERVED," bitfld.long 0xF0 1. "C,Selection of resizing method for" "C_0,C_1" newline bitfld.long 0xF0 0. "Y,Selection of resizing method for luminance: horizontal" "Y_0,Y_1" line.long 0xF4 "RZB_H_LPF,RESIZER B - HORIZONTAL LPF INTENSITY REGISTER" hexmask.long.tbyte 0xF4 12.--31. 1. "RESERVED," bitfld.long 0xF4 6.--11. "C,Horizontal LPF Intensity for Chrominance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0xF4 0.--5. "Y,Selection of resizing method for Luminance in horizontal direction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0xF8 "RZB_DWN_EN,RESIZER B - DOWNSCALE ENABLE REGISTER" hexmask.long 0xF8 1.--31. 1. "RESERVED," bitfld.long 0xF8 0. "DWN_EN,Resizer downscale enable" "DWN_EN_0,DWN_EN_1" line.long 0xFC "RZB_DWN_AV,RESIZER B" hexmask.long 0xFC 6.--31. 1. "RESERVED," bitfld.long 0xFC 3.--5. "V,Vertical averaging size : 1/2^(VWT+1) The range goes from 1/2 to 1/256 in power of two" "_DIV21/2 down scale,_DIV41/4 down scale,_DIV81/8 down scale,_DIV161/16 down scale,_DIV321/32 down scale,_DIV641/64 down scale,_DIV1281/128 down scale,_DIV2561/256 down scale" newline bitfld.long 0xFC 0.--2. "H,Horizontal averaging size : 1/2^(HWT+1) The range goes from 1/2 to 1/256 in power of two" "_DIV21/2 down scale,_DIV41/4 down scale,_DIV81/8 down scale,_DIV161/16 down scale,_DIV321/32 down scale,_DIV641/64 down scale,_DIV1281/128 down scale,_DIV2561/256 down scale" line.long 0x100 "RZB_RGB_EN,RESIZER B - RGB OUTPUT ENABLE" hexmask.long 0x100 1.--31. 1. "RESERVED," bitfld.long 0x100 0. "RGB_EN,Enable of RGB output In pass through mode this register must be 0" "RGB_EN_0,RGB_EN_1" line.long 0x104 "RZB_RGB_TYP,RESIZER B - RGB OUTPUT CONTROL REGISTER" hexmask.long 0x104 3.--31. 1. "RESERVED," bitfld.long 0x104 2. "MSK1,Enables masking of the last 2 pixels This bit is used to mask the 2 last pixels at the image boundary which are affected by the YUV422 to YUV444 conversion" "MSK1_0,MSK1_1" newline bitfld.long 0x104 1. "MSK0,Enables masking of the first 2 pixels This bit is used to mask the 2 first pixels at the image boundary which are affected by the YUV422 to YUV444 conversion" "MSK0_0,MSK0_1" bitfld.long 0x104 0. "TYP,16bit/32bit output selection" "TYP_0,TYP_1" line.long 0x108 "RZB_RGB_BLD,RESIZER B - RGB BLEND REGISTER" hexmask.long.tbyte 0x108 8.--31. 1. "RESERVED," hexmask.long.byte 0x108 0.--7. 1. "BLD,The alpha value used in 32-bit RGBA output mode" line.long 0x10C "RZB_SDR_Y_BAD_H,RESIZER B - OUTPUT MEMORY BASE ADDRESS REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420. RGB565. RGBA" hexmask.long.word 0x10C 16.--31. 1. "RESERVED," hexmask.long.word 0x10C 0.--15. 1. "Y_BAD_H,Memory Base Address Sets 16 upper bits of the 32-bit base address of the circular buffer in memory" line.long 0x110 "RZB_SDR_Y_BAD_L,RESIZER B - OUTPUT MEMORY BASE ADDRESS REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420. RGB565. RGBA" hexmask.long.word 0x110 16.--31. 1. "RESERVED," hexmask.long.word 0x110 0.--15. 1. "Y_BAD_L,Memory Base Address Sets the 16 lower bits of the 32-bit base address of the circular buffer in memory" line.long 0x114 "RZB_SDR_Y_SAD_H,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420. RGB565. RGBA" hexmask.long.word 0x114 16.--31. 1. "RESERVED," hexmask.long.word 0x114 0.--15. 1. "Y_SAD_H,Memory Start Address Sets 16 upper bits of the 32-bit start address in memory" line.long 0x118 "RZB_SDR_Y_SAD_L,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420. RGB565. RGBA" hexmask.long.word 0x118 16.--31. 1. "RESERVED," hexmask.long.word 0x118 0.--15. 1. "Y_SAD_L,Memory Start Address Sets the 16 lower bits of the 32-bit start address in memory" line.long 0x11C "RZB_SDR_Y_OFT,RESIZER B - OUTPUT MEMORY OFFSET REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420 or RGBA" hexmask.long.word 0x11C 17.--31. 1. "RESERVED," hexmask.long.tbyte 0x11C 0.--16. 1. "Y_OFT,Memory Line Offset Sets the size of each line in the circular buffer" line.long 0x120 "RZB_SDR_Y_PTR_S,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420 or RGBA" hexmask.long.tbyte 0x120 13.--31. 1. "RESERVED," hexmask.long.word 0x120 0.--12. 1. "Y_PTR_S,Start Line of Memory Pointer Sets the vertical position of the first output line in the output memory space" line.long 0x124 "RZB_SDR_Y_PTR_E,RESIZER B - OUTPUT MEMORY END ADDRESS REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420 or RGBA" hexmask.long.tbyte 0x124 13.--31. 1. "RESERVED," hexmask.long.word 0x124 0.--12. 1. "Y_PTR_E,End Line of Memory Pointer Sets the maximum number of lines to be stored in the output memory space" line.long 0x128 "RZB_SDR_C_BAD_H,RESIZER B - OUTPUT MEMORY BASE ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0x128 16.--31. 1. "RESERVED," hexmask.long.word 0x128 0.--15. 1. "C_BAD_H,Memory Base Address Sets the 16 upper bits of the 32-bit base address of the circular buffer in memory" line.long 0x12C "RZB_SDR_C_BAD_L,RESIZER B - OUTPUT MEMORY BASE ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0x12C 16.--31. 1. "RESERVED," hexmask.long.word 0x12C 0.--15. 1. "C_BAD_L,Memory Base Address Sets the 16 lower bits of the 32-bit base address of the circular buffer in memory" line.long 0x130 "RZB_SDR_C_SAD_H,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0x130 16.--31. 1. "RESERVED," hexmask.long.word 0x130 0.--15. 1. "C_SAD_H,Memory Base Address Sets the 16 upper bits of the 32-bit start address in memory" line.long 0x134 "RZB_SDR_C_SAD_L,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0x134 16.--31. 1. "RESERVED," hexmask.long.word 0x134 0.--15. 1. "C_SAD_L,Memory Base Address Sets the 16 lower bits of the 32-bit start address in memory" line.long 0x138 "RZB_SDR_C_OFT,RESIZER B - OUTPUT MEMORY OFFSET REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0x138 17.--31. 1. "RESERVED," hexmask.long.tbyte 0x138 0.--16. 1. "C_OFT,Memory Line Offset Sets the size of each line in the circular buffer" line.long 0x13C "RZB_SDR_C_PTR_S,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.tbyte 0x13C 13.--31. 1. "RESERVED," hexmask.long.word 0x13C 0.--12. 1. "C_PTR_S,Start Line of Memory Pointer Sets the vertical position of the first output line in the output memory space" line.long 0x140 "RZB_SDR_C_PTR_E,RESIZER B - OUTPUT MEMORY END ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.tbyte 0x140 13.--31. 1. "RESERVED," hexmask.long.word 0x140 0.--12. 1. "C_PTR_E,End Line of Memory Pointer Sets the maximum number of lines to be stored in the output memory space" width 0x0B tree.end tree "ISP6P5_SYS1" base ad:0x52040000 rgroup.long 0x00++0x0B line.long 0x00 "ISP5_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "ISP5_HWINFO1,GENERIC PARAMETER REGISTER Information about the IP module's hardware configuration" bitfld.long 0x04 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 16.--28. 1. "ISIF_RFM_LINE_SIZE,Memory line size for the data reformatter in the ISIF module" bitfld.long 0x04 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x04 0.--12. 1. "IPIPE_LINE_SIZE,Memory line size for the IPIPE module" line.long 0x08 "ISP5_HWINFO2,GENERIC PARAMETER REGISTER Information about the IP module's hardware configuration" hexmask.long.tbyte 0x08 13.--31. 1. "RESERVED," hexmask.long.word 0x08 0.--12. 1. "H3A_LINE_SIZE,Memory line size for the H3A module" group.long 0x10++0x03 line.long 0x00 "ISP5_SYSCONFIG,Clock management configuration" hexmask.long 0x00 6.--31. 1. "RESERVED," bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" rbitfld.long 0x00 0. "AUTO_IDLE,Auto clock gating" "0,1" group.long 0x20++0x6B line.long 0x00 "ISP5_IRQ_EOI,End Of Interrupt number specification" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 0.--1. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1,LINE_NUMBER_2,LINE_NUMBER_3" line.long 0x04 "ISP5_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x04 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x04 30. "RESERVED," "0,1" bitfld.long 0x04 29. "IPIPE_INT_DPC_RNEW1," "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" newline bitfld.long 0x04 28. "IPIPE_INT_DPC_RNEW0," "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x04 27. "IPIPE_INT_DPC_INI," "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" rbitfld.long 0x04 26. "RESERVED," "0,1" newline bitfld.long 0x04 25. "IPIPE_INT_EOF," "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x04 24. "H3A_INT_EOF," "H3A_INT_EOF_0,H3A_INT_EOF_1" bitfld.long 0x04 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" newline bitfld.long 0x04 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" rbitfld.long 0x04 20.--21. "RESERVED," "0,1,2,3" bitfld.long 0x04 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x04 18. "RSZ_FIFO_OVF,Resizer module overflow This event is set when overflow happens in the RESIZER module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x04 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x04 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x04 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x04 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x04 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x04 12. "H3A_INT," "H3A_INT_0,H3A_INT_1" bitfld.long 0x04 11. "AF_INT," "AF_INT_0,AF_INT_1" bitfld.long 0x04 10. "AEW_INT," "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x04 9. "IPIPEIF_IRQ,IPIPEIF module interrupt" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x04 8. "IPIPE_INT_HST," "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x04 7. "IPIPE_INT_BSC," "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x04 6. "IPIPE_INT_DMA," "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x04 5. "IPIPE_INT_LAST_PIX," "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x04 4. "IPIPE_INT_REG," "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x04 3. "ISIF_INT_3," "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x04 2. "ISIF_INT_2," "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x04 1. "ISIF_INT_1," "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x04 0. "ISIF_INT_0," "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x08 "ISP5_IRQSTATUS,Per-event 'enabled' interrupt status vector" bitfld.long 0x08 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x08 30. "RESERVED," "0,1" bitfld.long 0x08 29. "IPIPE_INT_DPC_RNEW1," "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" newline bitfld.long 0x08 28. "IPIPE_INT_DPC_RNEW0," "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x08 27. "IPIPE_INT_DPC_INI," "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" rbitfld.long 0x08 26. "RESERVED," "0,1" newline bitfld.long 0x08 25. "IPIPE_INT_EOF," "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x08 24. "H3A_INT_EOF," "H3A_INT_EOF_0,H3A_INT_EOF_1" bitfld.long 0x08 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" newline bitfld.long 0x08 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" rbitfld.long 0x08 20.--21. "RESERVED," "0,1,2,3" bitfld.long 0x08 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x08 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x08 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x08 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x08 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x08 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x08 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x08 12. "H3A_INT," "H3A_INT_0,H3A_INT_1" bitfld.long 0x08 11. "AF_INT," "AF_INT_0,AF_INT_1" bitfld.long 0x08 10. "AEW_INT," "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x08 9. "IPIPEIF_IRQ,IPIPEIF module interrupt" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x08 8. "IPIPE_INT_HST," "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x08 7. "IPIPE_INT_BSC," "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x08 6. "IPIPE_INT_DMA," "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x08 5. "IPIPE_INT_LAST_PIX," "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x08 4. "IPIPE_INT_REG," "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x08 3. "ISIF_INT_3," "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x08 2. "ISIF_INT_2," "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x08 1. "ISIF_INT_1," "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x08 0. "ISIF_INT_0," "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x0C "ISP5_IRQENABLE_SET,Per-event interrupt enable bit vector" bitfld.long 0x0C 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x0C 30. "RESERVED," "0,1" bitfld.long 0x0C 29. "IPIPE_INT_DPC_RNEW1," "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" newline bitfld.long 0x0C 28. "IPIPE_INT_DPC_RNEW0," "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x0C 27. "IPIPE_INT_DPC_INI," "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" rbitfld.long 0x0C 26. "RESERVED," "0,1" newline bitfld.long 0x0C 25. "IPIPE_INT_EOF," "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x0C 24. "H3A_INT_EOF," "H3A_INT_EOF_0,H3A_INT_EOF_1" bitfld.long 0x0C 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" newline bitfld.long 0x0C 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" rbitfld.long 0x0C 20.--21. "RESERVED," "0,1,2,3" bitfld.long 0x0C 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x0C 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x0C 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x0C 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x0C 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x0C 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x0C 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x0C 12. "H3A_INT," "H3A_INT_0,H3A_INT_1" bitfld.long 0x0C 11. "AF_INT," "AF_INT_0,AF_INT_1" bitfld.long 0x0C 10. "AEW_INT," "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x0C 9. "IPIPEIF_IRQ,IPIPEIF module interrupt" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x0C 8. "IPIPE_INT_HST," "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x0C 7. "IPIPE_INT_BSC," "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x0C 6. "IPIPE_INT_DMA," "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x0C 5. "IPIPE_INT_LAST_PIX," "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x0C 4. "IPIPE_INT_REG," "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x0C 3. "ISIF_INT_3," "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x0C 2. "ISIF_INT_2," "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x0C 1. "ISIF_INT_1," "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x0C 0. "ISIF_INT_0," "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x10 "ISP5_IRQENABLE_CLR,Per-event interrupt enable bit vector" bitfld.long 0x10 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x10 30. "RESERVED," "0,1" bitfld.long 0x10 29. "IPIPE_INT_DPC_RNEW1," "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" newline bitfld.long 0x10 28. "IPIPE_INT_DPC_RNEW0," "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x10 27. "IPIPE_INT_DPC_INI," "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" rbitfld.long 0x10 26. "RESERVED," "0,1" newline bitfld.long 0x10 25. "IPIPE_INT_EOF," "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x10 24. "H3A_INT_EOF," "H3A_INT_EOF_0,H3A_INT_EOF_1" bitfld.long 0x10 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" newline bitfld.long 0x10 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" rbitfld.long 0x10 20.--21. "RESERVED," "0,1,2,3" bitfld.long 0x10 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x10 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x10 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x10 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x10 15. "RSZ_INT_DMA,RESIZER module event: This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x10 14. "RSZ_INT_LAST_PIX,RESIZER module event: This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x10 13. "RSZ_INT_REG,RESIZER module event: This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x10 12. "H3A_INT," "H3A_INT_0,H3A_INT_1" bitfld.long 0x10 11. "AF_INT," "AF_INT_0,AF_INT_1" bitfld.long 0x10 10. "AEW_INT," "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x10 9. "IPIPEIF_IRQ,IPIPEIF module interrupt" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x10 8. "IPIPE_INT_HST," "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x10 7. "IPIPE_INT_BSC," "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x10 6. "IPIPE_INT_DMA," "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x10 5. "IPIPE_INT_LAST_PIX," "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x10 4. "IPIPE_INT_REG," "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x10 3. "ISIF_INT_3," "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x10 2. "ISIF_INT_2," "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x10 1. "ISIF_INT_1," "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x10 0. "ISIF_INT_0," "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x14 "ISP5_IRQSTATUS_RAW_1,Per-event raw interrupt status vector" bitfld.long 0x14 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x14 30. "RESERVED," "0,1" bitfld.long 0x14 29. "IPIPE_INT_DPC_RNEW1," "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" newline bitfld.long 0x14 28. "IPIPE_INT_DPC_RNEW0," "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x14 27. "IPIPE_INT_DPC_INI," "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" rbitfld.long 0x14 26. "RESERVED," "0,1" newline bitfld.long 0x14 25. "IPIPE_INT_EOF," "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x14 24. "H3A_INT_EOF," "H3A_INT_EOF_0,H3A_INT_EOF_1" bitfld.long 0x14 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" newline bitfld.long 0x14 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" rbitfld.long 0x14 20.--21. "RESERVED," "0,1,2,3" bitfld.long 0x14 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x14 18. "RSZ_FIFO_OVF,Resizer module overflow This event is set when overflow happens in the RESIZER module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x14 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x14 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x14 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x14 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x14 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x14 12. "H3A_INT," "H3A_INT_0,H3A_INT_1" bitfld.long 0x14 11. "AF_INT," "AF_INT_0,AF_INT_1" bitfld.long 0x14 10. "AEW_INT," "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x14 9. "IPIPEIF_IRQ,IPIPEIF module interrupt" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x14 8. "IPIPE_INT_HST," "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x14 7. "IPIPE_INT_BSC," "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x14 6. "IPIPE_INT_DMA," "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x14 5. "IPIPE_INT_LAST_PIX," "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x14 4. "IPIPE_INT_REG," "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x14 3. "ISIF_INT_3," "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x14 2. "ISIF_INT_2," "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x14 1. "ISIF_INT_1," "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x14 0. "ISIF_INT_0," "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x18 "ISP5_IRQSTATUS_1,Per-event 'enabled' interrupt status vector" bitfld.long 0x18 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x18 30. "RESERVED," "0,1" bitfld.long 0x18 29. "IPIPE_INT_DPC_RNEW1," "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" newline bitfld.long 0x18 28. "IPIPE_INT_DPC_RNEW0," "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x18 27. "IPIPE_INT_DPC_INI," "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" rbitfld.long 0x18 26. "RESERVED," "0,1" newline bitfld.long 0x18 25. "IPIPE_INT_EOF," "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x18 24. "H3A_INT_EOF," "H3A_INT_EOF_0,H3A_INT_EOF_1" bitfld.long 0x18 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" newline bitfld.long 0x18 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" rbitfld.long 0x18 20.--21. "RESERVED," "0,1,2,3" bitfld.long 0x18 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x18 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x18 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x18 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x18 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x18 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x18 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x18 12. "H3A_INT," "H3A_INT_0,H3A_INT_1" bitfld.long 0x18 11. "AF_INT," "AF_INT_0,AF_INT_1" bitfld.long 0x18 10. "AEW_INT," "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x18 9. "IPIPEIF_IRQ,IPIPEIF module interrupt" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x18 8. "IPIPE_INT_HST," "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x18 7. "IPIPE_INT_BSC," "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x18 6. "IPIPE_INT_DMA," "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x18 5. "IPIPE_INT_LAST_PIX," "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x18 4. "IPIPE_INT_REG," "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x18 3. "ISIF_INT_3," "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x18 2. "ISIF_INT_2," "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x18 1. "ISIF_INT_1," "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x18 0. "ISIF_INT_0," "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x1C "ISP5_IRQENABLE_SET_1,Per-event interrupt enable bit vector" bitfld.long 0x1C 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x1C 30. "RESERVED," "0,1" bitfld.long 0x1C 29. "IPIPE_INT_DPC_RNEW1," "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" newline bitfld.long 0x1C 28. "IPIPE_INT_DPC_RNEW0," "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x1C 27. "IPIPE_INT_DPC_INI," "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" rbitfld.long 0x1C 26. "RESERVED," "0,1" newline bitfld.long 0x1C 25. "IPIPE_INT_EOF," "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x1C 24. "H3A_INT_EOF," "H3A_INT_EOF_0,H3A_INT_EOF_1" bitfld.long 0x1C 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" newline bitfld.long 0x1C 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" rbitfld.long 0x1C 20.--21. "RESERVED," "0,1,2,3" bitfld.long 0x1C 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x1C 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x1C 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x1C 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x1C 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x1C 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x1C 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x1C 12. "H3A_INT," "H3A_INT_0,H3A_INT_1" bitfld.long 0x1C 11. "AF_INT," "AF_INT_0,AF_INT_1" bitfld.long 0x1C 10. "AEW_INT," "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x1C 9. "IPIPEIF_IRQ,IPIPEIF module interrupt" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x1C 8. "IPIPE_INT_HST," "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x1C 7. "IPIPE_INT_BSC," "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x1C 6. "IPIPE_INT_DMA," "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x1C 5. "IPIPE_INT_LAST_PIX," "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x1C 4. "IPIPE_INT_REG," "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x1C 3. "ISIF_INT_3," "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x1C 2. "ISIF_INT_2," "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x1C 1. "ISIF_INT_1," "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x1C 0. "ISIF_INT_0," "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x20 "ISP5_IRQENABLE_CLR_1,Per-event interrupt enable bit vector" bitfld.long 0x20 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x20 30. "RESERVED," "0,1" bitfld.long 0x20 29. "IPIPE_INT_DPC_RNEW1," "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" newline bitfld.long 0x20 28. "IPIPE_INT_DPC_RNEW0," "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x20 27. "IPIPE_INT_DPC_INI," "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" rbitfld.long 0x20 26. "RESERVED," "0,1" newline bitfld.long 0x20 25. "IPIPE_INT_EOF," "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x20 24. "H3A_INT_EOF," "H3A_INT_EOF_0,H3A_INT_EOF_1" bitfld.long 0x20 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" newline bitfld.long 0x20 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" rbitfld.long 0x20 20.--21. "RESERVED," "0,1,2,3" bitfld.long 0x20 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x20 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x20 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x20 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x20 15. "RSZ_INT_DMA,RESIZER module event: This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x20 14. "RSZ_INT_LAST_PIX,RESIZER module event: This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x20 13. "RSZ_INT_REG,RESIZER module event: This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x20 12. "H3A_INT," "H3A_INT_0,H3A_INT_1" bitfld.long 0x20 11. "AF_INT," "AF_INT_0,AF_INT_1" bitfld.long 0x20 10. "AEW_INT," "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x20 9. "IPIPEIF_IRQ,IPIPEIF module interrupt" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x20 8. "IPIPE_INT_HST," "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x20 7. "IPIPE_INT_BSC," "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x20 6. "IPIPE_INT_DMA," "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x20 5. "IPIPE_INT_LAST_PIX," "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x20 4. "IPIPE_INT_REG," "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x20 3. "ISIF_INT_3," "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x20 2. "ISIF_INT_2," "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x20 1. "ISIF_INT_1," "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x20 0. "ISIF_INT_0," "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x24 "ISP5_IRQSTATUS_RAW_2,Per-event raw interrupt status vector" bitfld.long 0x24 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x24 30. "RESERVED," "0,1" bitfld.long 0x24 29. "IPIPE_INT_DPC_RNEW1," "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" newline bitfld.long 0x24 28. "IPIPE_INT_DPC_RNEW0," "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x24 27. "IPIPE_INT_DPC_INI," "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" rbitfld.long 0x24 26. "RESERVED," "0,1" newline bitfld.long 0x24 25. "IPIPE_INT_EOF," "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x24 24. "H3A_INT_EOF," "H3A_INT_EOF_0,H3A_INT_EOF_1" bitfld.long 0x24 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" newline bitfld.long 0x24 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" rbitfld.long 0x24 20.--21. "RESERVED," "0,1,2,3" bitfld.long 0x24 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x24 18. "RSZ_FIFO_OVF,Resizer module overflow This event is set when overflow happens in the RESIZER module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x24 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x24 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x24 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x24 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x24 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x24 12. "H3A_INT," "H3A_INT_0,H3A_INT_1" bitfld.long 0x24 11. "AF_INT," "AF_INT_0,AF_INT_1" bitfld.long 0x24 10. "AEW_INT," "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x24 9. "IPIPEIF_IRQ,IPIPEIF module interrupt" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x24 8. "IPIPE_INT_HST," "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x24 7. "IPIPE_INT_BSC," "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x24 6. "IPIPE_INT_DMA," "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x24 5. "IPIPE_INT_LAST_PIX," "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x24 4. "IPIPE_INT_REG," "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x24 3. "ISIF_INT_3," "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x24 2. "ISIF_INT_2," "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x24 1. "ISIF_INT_1," "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x24 0. "ISIF_INT_0," "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x28 "ISP5_IRQSTATUS_2,Per-event 'enabled' interrupt status vector" bitfld.long 0x28 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x28 30. "RESERVED," "0,1" bitfld.long 0x28 29. "IPIPE_INT_DPC_RNEW1," "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" newline bitfld.long 0x28 28. "IPIPE_INT_DPC_RNEW0," "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x28 27. "IPIPE_INT_DPC_INI," "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" rbitfld.long 0x28 26. "RESERVED," "0,1" newline bitfld.long 0x28 25. "IPIPE_INT_EOF," "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x28 24. "H3A_INT_EOF," "H3A_INT_EOF_0,H3A_INT_EOF_1" bitfld.long 0x28 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" newline bitfld.long 0x28 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" rbitfld.long 0x28 20.--21. "RESERVED," "0,1,2,3" bitfld.long 0x28 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x28 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x28 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x28 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x28 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x28 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x28 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x28 12. "H3A_INT," "H3A_INT_0,H3A_INT_1" bitfld.long 0x28 11. "AF_INT," "AF_INT_0,AF_INT_1" bitfld.long 0x28 10. "AEW_INT," "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x28 9. "IPIPEIF_IRQ,IPIPEIF module interrupt" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x28 8. "IPIPE_INT_HST," "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x28 7. "IPIPE_INT_BSC," "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x28 6. "IPIPE_INT_DMA," "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x28 5. "IPIPE_INT_LAST_PIX," "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x28 4. "IPIPE_INT_REG," "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x28 3. "ISIF_INT_3," "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x28 2. "ISIF_INT_2," "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x28 1. "ISIF_INT_1," "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x28 0. "ISIF_INT_0," "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x2C "ISP5_IRQENABLE_SET_2,Per-event interrupt enable bit vector" bitfld.long 0x2C 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x2C 30. "RESERVED," "0,1" bitfld.long 0x2C 29. "IPIPE_INT_DPC_RNEW1," "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" newline bitfld.long 0x2C 28. "IPIPE_INT_DPC_RNEW0," "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x2C 27. "IPIPE_INT_DPC_INI," "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" rbitfld.long 0x2C 26. "RESERVED," "0,1" newline bitfld.long 0x2C 25. "IPIPE_INT_EOF," "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x2C 24. "H3A_INT_EOF," "H3A_INT_EOF_0,H3A_INT_EOF_1" bitfld.long 0x2C 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" newline bitfld.long 0x2C 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" rbitfld.long 0x2C 20.--21. "RESERVED," "0,1,2,3" bitfld.long 0x2C 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x2C 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x2C 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x2C 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x2C 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x2C 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x2C 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x2C 12. "H3A_INT," "H3A_INT_0,H3A_INT_1" bitfld.long 0x2C 11. "AF_INT," "AF_INT_0,AF_INT_1" bitfld.long 0x2C 10. "AEW_INT," "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x2C 9. "IPIPEIF_IRQ,IPIPEIF module interrupt" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x2C 8. "IPIPE_INT_HST," "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x2C 7. "IPIPE_INT_BSC," "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x2C 6. "IPIPE_INT_DMA," "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x2C 5. "IPIPE_INT_LAST_PIX," "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x2C 4. "IPIPE_INT_REG," "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x2C 3. "ISIF_INT_3," "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x2C 2. "ISIF_INT_2," "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x2C 1. "ISIF_INT_1," "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x2C 0. "ISIF_INT_0," "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x30 "ISP5_IRQENABLE_CLR_2,Per-event interrupt enable bit vector" bitfld.long 0x30 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x30 30. "RESERVED," "0,1" bitfld.long 0x30 29. "IPIPE_INT_DPC_RNEW1," "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" newline bitfld.long 0x30 28. "IPIPE_INT_DPC_RNEW0," "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x30 27. "IPIPE_INT_DPC_INI," "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" rbitfld.long 0x30 26. "RESERVED," "0,1" newline bitfld.long 0x30 25. "IPIPE_INT_EOF," "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x30 24. "H3A_INT_EOF," "H3A_INT_EOF_0,H3A_INT_EOF_1" bitfld.long 0x30 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" newline bitfld.long 0x30 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" rbitfld.long 0x30 20.--21. "RESERVED," "0,1,2,3" bitfld.long 0x30 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x30 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x30 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x30 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x30 15. "RSZ_INT_DMA,RESIZER module event: This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x30 14. "RSZ_INT_LAST_PIX,RESIZER module event: This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x30 13. "RSZ_INT_REG,RESIZER module event: This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x30 12. "H3A_INT," "H3A_INT_0,H3A_INT_1" bitfld.long 0x30 11. "AF_INT," "AF_INT_0,AF_INT_1" bitfld.long 0x30 10. "AEW_INT," "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x30 9. "IPIPEIF_IRQ,IPIPEIF module interrupt" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x30 8. "IPIPE_INT_HST," "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x30 7. "IPIPE_INT_BSC," "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x30 6. "IPIPE_INT_DMA," "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x30 5. "IPIPE_INT_LAST_PIX," "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x30 4. "IPIPE_INT_REG," "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x30 3. "ISIF_INT_3," "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x30 2. "ISIF_INT_2," "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x30 1. "ISIF_INT_1," "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x30 0. "ISIF_INT_0," "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x34 "ISP5_IRQSTATUS_RAW_3,Per-event raw interrupt status vector" bitfld.long 0x34 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x34 30. "RESERVED," "0,1" bitfld.long 0x34 29. "IPIPE_INT_DPC_RNEW1," "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" newline bitfld.long 0x34 28. "IPIPE_INT_DPC_RNEW0," "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x34 27. "IPIPE_INT_DPC_INI," "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" rbitfld.long 0x34 26. "RESERVED," "0,1" newline bitfld.long 0x34 25. "IPIPE_INT_EOF," "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x34 24. "H3A_INT_EOF," "H3A_INT_EOF_0,H3A_INT_EOF_1" bitfld.long 0x34 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" newline bitfld.long 0x34 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" rbitfld.long 0x34 20.--21. "RESERVED," "0,1,2,3" bitfld.long 0x34 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x34 18. "RSZ_FIFO_OVF,Resizer module overflow This event is set when overflow happens in the RESIZER module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x34 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x34 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x34 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x34 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x34 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x34 12. "H3A_INT," "H3A_INT_0,H3A_INT_1" bitfld.long 0x34 11. "AF_INT," "AF_INT_0,AF_INT_1" bitfld.long 0x34 10. "AEW_INT," "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x34 9. "IPIPEIF_IRQ,IPIPEIF module interrupt" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x34 8. "IPIPE_INT_HST," "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x34 7. "IPIPE_INT_BSC," "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x34 6. "IPIPE_INT_DMA," "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x34 5. "IPIPE_INT_LAST_PIX," "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x34 4. "IPIPE_INT_REG," "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x34 3. "ISIF_INT_3," "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x34 2. "ISIF_INT_2," "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x34 1. "ISIF_INT_1," "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x34 0. "ISIF_INT_0," "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x38 "ISP5_IRQSTATUS_3,Per-event 'enabled' interrupt status vector" bitfld.long 0x38 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x38 30. "RESERVED," "0,1" bitfld.long 0x38 29. "IPIPE_INT_DPC_RNEW1," "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" newline bitfld.long 0x38 28. "IPIPE_INT_DPC_RNEW0," "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x38 27. "IPIPE_INT_DPC_INI," "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" rbitfld.long 0x38 26. "RESERVED," "0,1" newline bitfld.long 0x38 25. "IPIPE_INT_EOF," "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x38 24. "H3A_INT_EOF," "H3A_INT_EOF_0,H3A_INT_EOF_1" bitfld.long 0x38 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" newline bitfld.long 0x38 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" rbitfld.long 0x38 20.--21. "RESERVED," "0,1,2,3" bitfld.long 0x38 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x38 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x38 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x38 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x38 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x38 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x38 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x38 12. "H3A_INT," "H3A_INT_0,H3A_INT_1" bitfld.long 0x38 11. "AF_INT," "AF_INT_0,AF_INT_1" bitfld.long 0x38 10. "AEW_INT," "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x38 9. "IPIPEIF_IRQ,IPIPEIF module interrupt" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x38 8. "IPIPE_INT_HST," "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x38 7. "IPIPE_INT_BSC," "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x38 6. "IPIPE_INT_DMA," "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x38 5. "IPIPE_INT_LAST_PIX," "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x38 4. "IPIPE_INT_REG," "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x38 3. "ISIF_INT_3," "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x38 2. "ISIF_INT_2," "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x38 1. "ISIF_INT_1," "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x38 0. "ISIF_INT_0," "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x3C "ISP5_IRQENABLE_SET_3,Per-event interrupt enable bit vector" bitfld.long 0x3C 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x3C 30. "RESERVED," "0,1" bitfld.long 0x3C 29. "IPIPE_INT_DPC_RNEW1," "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" newline bitfld.long 0x3C 28. "IPIPE_INT_DPC_RNEW0," "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x3C 27. "IPIPE_INT_DPC_INI," "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" rbitfld.long 0x3C 26. "RESERVED," "0,1" newline bitfld.long 0x3C 25. "IPIPE_INT_EOF," "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x3C 24. "H3A_INT_EOF," "H3A_INT_EOF_0,H3A_INT_EOF_1" bitfld.long 0x3C 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" newline bitfld.long 0x3C 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" rbitfld.long 0x3C 20.--21. "RESERVED," "0,1,2,3" bitfld.long 0x3C 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x3C 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x3C 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x3C 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x3C 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x3C 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x3C 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x3C 12. "H3A_INT," "H3A_INT_0,H3A_INT_1" bitfld.long 0x3C 11. "AF_INT," "AF_INT_0,AF_INT_1" bitfld.long 0x3C 10. "AEW_INT," "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x3C 9. "IPIPEIF_IRQ,IPIPEIF module interrupt" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x3C 8. "IPIPE_INT_HST," "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x3C 7. "IPIPE_INT_BSC," "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x3C 6. "IPIPE_INT_DMA," "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x3C 5. "IPIPE_INT_LAST_PIX," "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x3C 4. "IPIPE_INT_REG," "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x3C 3. "ISIF_INT_3," "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x3C 2. "ISIF_INT_2," "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x3C 1. "ISIF_INT_1," "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x3C 0. "ISIF_INT_0," "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x40 "ISP5_IRQENABLE_CLR_3,Per-event interrupt enable bit vector" bitfld.long 0x40 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x40 30. "RESERVED," "0,1" bitfld.long 0x40 29. "IPIPE_INT_DPC_RNEW1," "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" newline bitfld.long 0x40 28. "IPIPE_INT_DPC_RNEW0," "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x40 27. "IPIPE_INT_DPC_INI," "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" rbitfld.long 0x40 26. "RESERVED," "0,1" newline bitfld.long 0x40 25. "IPIPE_INT_EOF," "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x40 24. "H3A_INT_EOF," "H3A_INT_EOF_0,H3A_INT_EOF_1" bitfld.long 0x40 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" newline bitfld.long 0x40 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" rbitfld.long 0x40 20.--21. "RESERVED," "0,1,2,3" bitfld.long 0x40 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x40 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x40 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x40 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x40 15. "RSZ_INT_DMA,RESIZER module event: This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x40 14. "RSZ_INT_LAST_PIX,RESIZER module event: This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x40 13. "RSZ_INT_REG,RESIZER module event: This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x40 12. "H3A_INT," "H3A_INT_0,H3A_INT_1" bitfld.long 0x40 11. "AF_INT," "AF_INT_0,AF_INT_1" bitfld.long 0x40 10. "AEW_INT," "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x40 9. "IPIPEIF_IRQ,IPIPEIF module interrupt" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x40 8. "IPIPE_INT_HST," "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x40 7. "IPIPE_INT_BSC," "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x40 6. "IPIPE_INT_DMA," "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x40 5. "IPIPE_INT_LAST_PIX," "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x40 4. "IPIPE_INT_REG," "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x40 3. "ISIF_INT_3," "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x40 2. "ISIF_INT_2," "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x40 1. "ISIF_INT_1," "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x40 0. "ISIF_INT_0," "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x44 "ISP5_DMAENABLE_SET,Per-line DMA enable bit vector Write 1 to set (enable DMA request generation)" hexmask.long 0x44 5.--31. 1. "RESERVED," bitfld.long 0x44 4. "IPIPE_INT_DPC_RNEW1,Enable for ISP5 DMA request generation on line #2 This DMA request shall be set to transfer the DPC data from memory to the IPIPE internal RAM" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x44 3. "IPIPE_INT_LAST_PIX,Enable for ISP5 DMA request generation on line #3 This DMA request shall be set to transfer the GAMMA data from memory to the IPIPE internal RAM or to initialize the DPC table" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" newline bitfld.long 0x44 2. "IPIPE_INT_DPC_RNEW0,Enable for ISP5 DMA request generation on line #2 This DMA request shall be set to transfer the DPC data from memory to the IPIPE internal RAM" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x44 1. "IPIPE_INT_HST,Enable for ISP5 DMA request generation on line #1 This DMA request shall be set to transfer the HIST data from the IPIPE internal RAM to memory" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x44 0. "IPIPE_INT_BSC,Enable for ISP5 DMA request generation on line #0 This DMA request shall be set to transfer the BSC data from the IPIPE internal RAM to memory" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" line.long 0x48 "ISP5_DMAENABLE_CLR,Per-line DMA clear bit vector Write 1 to clear (disable DMA request generation)" hexmask.long 0x48 5.--31. 1. "RESERVED," bitfld.long 0x48 4. "IPIPE_INT_DPC_RNEW1,Clear for ISP5 DMA request generation on line ISP5_DMA_REQ[2]" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x48 3. "IPIPE_INT_LAST_PIX,Clear for ISP5 DMA request generation on ISP5_DMA_REQ[3]" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" newline bitfld.long 0x48 2. "IPIPE_INT_DPC_RNEW0,Clear for ISP5 DMA request generation on ISP5_DMA_REQ[2]" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" bitfld.long 0x48 1. "IPIPE_INT_HST,Clear for ISP5 DMA request generation on ISP5_DMA_REQ[1]" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x48 0. "IPIPE_INT_BSC,Clear for ISP5 DMA request generation on ISP5_DMA_REQ[0]" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" line.long 0x4C "ISP5_CTRL,ISP5 CONTROL REGISTER" bitfld.long 0x4C 30.--31. "DMA3_CFG,This bitfield selects the DMA transfer configuration which is used with the ISP5_DMA_REQ[3] DMA request signal" "DMA3_CFG_0,DMA3_CFG_1,DMA3_CFG_2,DMA3_CFG_3" rbitfld.long 0x4C 28.--29. "RESERVED," "0,1,2,3" bitfld.long 0x4C 27. "BSC_RD_CHK,When the BSC computation is enabled and the BSC DMA request not used to read out the data this register enables to ensure that the data were read fast enough else an interrupt IPIPE_BSC_ERR is triggered" "BSC_RD_CHK_0,BSC_RD_CHK_1" newline bitfld.long 0x4C 26. "HST_RD_CHK,When the HISTOGRAM computation is enabled and the HST DMA request not used to read out the data this register enables to ensure that the data were read fast enough else an interrupt IPIPE_HST_ERR is triggered" "HST_RD_CHK_0,HST_RD_CHK_1" bitfld.long 0x4C 25. "DPC_EVT_INI,Select the IPIPE module event to be used to generate the DMA requests for the DPC submodule" "DPC_EVT_INI_0,DPC_EVT_INI_1" bitfld.long 0x4C 24. "MSTANDBY,MStandby signal assertion and de-assertion control for power management transitions" "MSTANDBY_0,MSTANDBY_1" newline bitfld.long 0x4C 23. "VD_PULSE_EXT,VD pulse extension enable This bit enables or disables the VD extension bridge" "VD_PULSE_EXT_0,VD_PULSE_EXT_1" bitfld.long 0x4C 22. "PCLK_INV,Pixel clock inversion This bit enables or disables pixel clock inversion" "PCLK_INV_0,PCLK_INV_1" bitfld.long 0x4C 21. "MFLAG,MFlag signal generation control This bit controls how the OCP MFlag signal is generated on the ISS NOC" "MFLAG_0,MFLAG_1" newline rbitfld.long 0x4C 20. "MSTANDDBY_WAIT,MStandby / Wait power management status bit" "MSTANDDBY_WAIT_0,MSTANDDBY_WAIT_1" bitfld.long 0x4C 19. "GLBCE_CLK_ENABLE,GLBCE clock enable" "GLBCE_CLK_ENABLE_0,GLBCE_CLK_ENABLE_1" bitfld.long 0x4C 18. "NSF3V_CLK_ENABLE,NSF3V clock enable" "NSF3V_CLK_ENABLE_0,NSF3V_CLK_ENABLE_1" newline bitfld.long 0x4C 17. "CNFB_CLK_ENABLE,CNFB clock enable" "CNFB_CLK_ENABLE_0,CNFB_CLK_ENABLE_1" bitfld.long 0x4C 16. "CNFA_CLK_ENABLE,CNFA clock enable" "CNFA_CLK_ENABLE_0,CNFA_CLK_ENABLE_1" bitfld.long 0x4C 15. "BL_CLK_ENABLE,BL clock enable" "BL_CLK_ENABLE_0,BL_CLK_ENABLE_1" newline bitfld.long 0x4C 14. "ISIF_CLK_ENABLE,ISIF clock enable The ISP5 will return OCP_ERROR if one tries to program the module MMR or memory when the clock is disabled" "ISIF_CLK_ENABLE_0,ISIF_CLK_ENABLE_1" bitfld.long 0x4C 13. "H3A_CLK_ENABLE,H3A clock enable The ISP5 will return OCP_ERROR if one tries to program the module MMR or memory when the clock is disabled" "H3A_CLK_ENABLE_0,H3A_CLK_ENABLE_1" bitfld.long 0x4C 12. "RSZ_CLK_ENABLE,RESIZER clock enable The ISP5 will return OCP_ERROR if one tries to program the module MMR or memory when the clock is disabled" "RSZ_CLK_ENABLE_0,RSZ_CLK_ENABLE_1" newline bitfld.long 0x4C 11. "IPIPE_CLK_ENABLE,IPIPE clock enable The ISP5 will return OCP_ERROR if one tries to program the module MMR or memory when the clock is disabled" "IPIPE_CLK_ENABLE_0,IPIPE_CLK_ENABLE_1" bitfld.long 0x4C 10. "IPIPEIF_CLK_ENABLE,IPIPEIF clock enable The ISP5 will return OCP_ERROR if one tries to program the module MMR or memory when the clock is disabled" "IPIPEIF_CLK_ENABLE_0,IPIPEIF_CLK_ENABLE_1" bitfld.long 0x4C 9. "SYNC_ENABLE,PCLK Sync module enable" "SYNC_ENABLE_0,SYNC_ENABLE_1" newline bitfld.long 0x4C 8. "PSYNC_CLK_SEL,PCLK Sync clock select" "PSYNC_CLK_SEL_0,PSYNC_CLK_SEL_1" bitfld.long 0x4C 4.--7. "VBUSM_CIDS,BL MAX VBUSM CIDs The BL module supports up to 16 CIDs/tags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x4C 1.--3. "VBUSM_CPRIORITY,BL VBUSM priority setting" "VBUSM_CPRIORITY_0,VBUSM_CPRIORITY_1,VBUSM_CPRIORITY_2,VBUSM_CPRIORITY_3,VBUSM_CPRIORITY_4,VBUSM_CPRIORITY_5,VBUSM_CPRIORITY_6,VBUSM_CPRIORITY_7" newline bitfld.long 0x4C 0. "OCP_WRNP,ISP5 OCP master port non-posted write control" "OCP_WRNP_0,OCP_WRNP_1" line.long 0x50 "ISP5_PG,PATTERN GENERATOR REGISTER" hexmask.long 0x50 6.--31. 1. "RESERVED," bitfld.long 0x50 4.--5. "SRC_SEL,Input mux selection" "SRC_SEL_0,SRC_SEL_1,SRC_SEL_2,SRC_SEL_3" bitfld.long 0x50 3. "EN," "EN_0,EN_1" newline bitfld.long 0x50 2. "WEN," "WEN_0,WEN_1" bitfld.long 0x50 1. "HDPOL," "HDPOL_0,HDPOL_1" bitfld.long 0x50 0. "VDPOL," "VDPOL_0,VDPOL_1" line.long 0x54 "ISP5_PG_PULSE_CTRL,PATTERN GENERATOR REGISTER" rbitfld.long 0x54 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x54 16.--27. 1. "VDW,Pattern generator VD width Width = VDW+1" rbitfld.long 0x54 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x54 0.--12. 1. "HDW,Pattern generator HD width Width = HDW+1" line.long 0x58 "ISP5_PG_FRAME_SIZE,PATTERN GENERATOR REGISTER" hexmask.long.word 0x58 16.--31. 1. "PPLN,Pattern Generator: pixels per line PPLN+1" hexmask.long.word 0x58 0.--15. 1. "HLPFR,Pattern Generator: half lines per frame HLPFR+1" line.long 0x5C "ISP5_MPSR,ISP5 memory access register" bitfld.long 0x5C 31. "IPIPEIF_CMP_LUT2,IPIPEIF Companding LUT memory access priority" "IPIPEIF_CMP_LUT2_0,IPIPEIF_CMP_LUT2_1" bitfld.long 0x5C 30. "IPIPEIF_DECMP_LUT1,IPIPEIF Memory Read path Decompanding LUT memory access priority" "IPIPEIF_DECMP_LUT1_0,IPIPEIF_DECMP_LUT1_1" bitfld.long 0x5C 29. "IPIPEIF_DECMP_LUT0,IPIPEIF VPORT Decompanding LUT memory access priority" "IPIPEIF_DECMP_LUT0_0,IPIPEIF_DECMP_LUT0_1" newline bitfld.long 0x5C 28. "ISP_GLBCE_TB,ISP GLBCE TB memory access priority This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "ISP_GLBCE_TB_0,ISP_GLBCE_TB_1" rbitfld.long 0x5C 25.--27. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x5C 24. "IPIPE_GAMMA_RGB_COPY,GAMMA table RGB Copy This bit shall be enable when one wants to use the same Gamma table for the R G and B color components" "IPIPE_GAMMA_RGB_COPY_0,IPIPE_GAMMA_RGB_COPY_1" newline rbitfld.long 0x5C 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x5C 20. "IPIPE_BSC_TB1,IPIPE BSC TB1 memory access priority This memory is expected to be read by the CPU or the DMA to get BSC information during vertical blanking period" "IPIPE_BSC_TB1_0,IPIPE_BSC_TB1_1" bitfld.long 0x5C 19. "IPIPE_BSC_TB0,IPIPE BSC TB0 memory access priority This memory is expected to be read by the CPU or the DMA to get BSC information during vertical blanking period" "IPIPE_BSC_TB0_0,IPIPE_BSC_TB0_1" newline bitfld.long 0x5C 18. "IPIPE_HST_TB3,IPIPE histogram memory #3 access priority This memory is expected to be read by the CPU or the DMA to get HST information during vertical blanking period" "IPIPE_HST_TB3_0,IPIPE_HST_TB3_1" bitfld.long 0x5C 17. "IPIPE_HST_TB2,IPIPE histogram memory #2 access priority This memory is expected to be read by the CPU or the DMA to get HST information during vertical blanking period" "IPIPE_HST_TB2_0,IPIPE_HST_TB2_1" bitfld.long 0x5C 16. "IPIPE_HST_TB1,IPIPE histogram memory #1 access priority This memory is expected to be read by the CPU or the DMA to get HST information during vertical blanking period" "IPIPE_HST_TB1_0,IPIPE_HST_TB1_1" newline bitfld.long 0x5C 15. "IPIPE_HST_TB0,IPIPE histogram memory #0 access priority This memory is expected to be read by the CPU or the DMA to get HST information during vertical blanking period" "IPIPE_HST_TB0_0,IPIPE_HST_TB0_1" bitfld.long 0x5C 14. "IPIPE_D3L_TB3,D3L TB3 memory access priority This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_D3L_TB3_0,IPIPE_D3L_TB3_1" bitfld.long 0x5C 13. "IPIPE_D3L_TB2,D3L TB2 memory access priority This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_D3L_TB2_0,IPIPE_D3L_TB2_1" newline bitfld.long 0x5C 12. "IPIPE_D3L_TB1,D3L TB1 memory access priority This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_D3L_TB1_0,IPIPE_D3L_TB1_1" bitfld.long 0x5C 11. "IPIPE_D3L_TB0,D3L TB0 memory access priority This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_D3L_TB0_0,IPIPE_D3L_TB0_1" bitfld.long 0x5C 10. "IPIPE_GBC_TB,IPIPE GBC TB memory access priority This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_GBC_TB_0,IPIPE_GBC_TB_1" newline bitfld.long 0x5C 9. "IPIPE_YEE_TB,YEE TB memory access priority This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_YEE_TB_0,IPIPE_YEE_TB_1" bitfld.long 0x5C 8. "IPIPE_GMM_TBR,IPIPE Gamma LUT R memory arbitration This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_GMM_TBR_0,IPIPE_GMM_TBR_1" bitfld.long 0x5C 7. "IPIPE_GMM_TBG,IPIPE Gamma LUT G memory arbitration This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_GMM_TBG_0,IPIPE_GMM_TBG_1" newline bitfld.long 0x5C 6. "IPIPE_GMM_TBB,IPIPE Gamma LUT B memory arbitration This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_GMM_TBB_0,IPIPE_GMM_TBB_1" bitfld.long 0x5C 5. "IPIPE_DPC_TB,IPIPE defect pixel memory arbitration This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_DPC_TB_0,IPIPE_DPC_TB_1" bitfld.long 0x5C 4. "ISIF_DCLAMP,ISIF DC accumulation memory arbitration This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "ISIF_DCLAMP_0,ISIF_DCLAMP_1" newline bitfld.long 0x5C 3. "ISIF_LSC_TB1,ISIF LSC memory 1 access This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "ISIF_LSC_TB1_0,ISIF_LSC_TB1_1" bitfld.long 0x5C 2. "ISIF_LSC_TB0,ISIF LSC memory 0 access This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "ISIF_LSC_TB0_0,ISIF_LSC_TB0_1" bitfld.long 0x5C 1. "ISIF_LIN_TB,ISIF linearity compensation memory arbitration This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "ISIF_LIN_TB_0,ISIF_LIN_TB_1" newline rbitfld.long 0x5C 0. "RESERVED," "0,1" line.long 0x60 "ISP5_BL_MTC_1,MEMORY REQUEST MINIMUM INTERVAL REGISTER" hexmask.long.word 0x60 16.--31. 1. "ISIF_R,Sets the minimum interval btw two consecutive memory requests for the ISIF-Read port" hexmask.long.word 0x60 0.--15. 1. "IPIPEIF_R,Sets the minimum interval btw two consecutive memory requests for the IPIPEIF-Read port" line.long 0x64 "ISP5_BL_MTC_2,MEMORY REQUEST MINIMUM INTERVAL REGISTER" hexmask.long.word 0x64 16.--31. 1. "H3A_W,Sets the minimum interval btw two consecutive memory requests for the H3A-Write port" hexmask.long.word 0x64 0.--15. 1. "RESERVED," line.long 0x68 "ISP5_BL_VBUSM,BL VBUSM TUNING REGISTER The settings in the register are static and not expected to be modified dynamically" hexmask.long 0x68 6.--31. 1. "RESERVED," bitfld.long 0x68 5. "MFLAG_THRES,MFLAG Threshold value The value of this bit field is a threshold which is compared to the MFlag output of the ISP5" "MFLAG_THRES_0,MFLAG_THRES_1" bitfld.long 0x68 0.--4. "LASTCMD_DLY,The value of this bitfield represents a delay expressed in cycles (L3 clock)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "ISP6P5_SYS2" base ad:0x520400A0 rgroup.long 0x00++0x17 line.long 0x00 "ISP5_KEY_EN1,IPIPE eFuse enable" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "KEY1_EN,EFUSE enable Equals 1 when ISP5_EFUSE3_EN = 1 or 0 otherwise" "KEY1_EN_0,KEY1_EN_1" line.long 0x04 "ISP5_KEY_EN2,ISIF eFuse enable" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "KEY1_EN,EFUSE enable Equals 1 when ISP5_EFUSE1_EN = 1 or 0 otherwise" "KEY1_EN_0,KEY1_EN_1" line.long 0x08 "ISP5_KEY_EN3,ISIF eFuse enable" hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "KEY_EN,EFUSE enable Equals 1 when ISP5_EFUSE3_EN = 1 or 0 otherwise" "KEY_EN_0,KEY_EN_1" line.long 0x0C "ISP5_KEY_EN4,IPIPEIF eFuse enable" hexmask.long 0x0C 2.--31. 1. "RESERVED," bitfld.long 0x0C 1. "KEY2_EN,EFUSE enable Equals 1 when ISP5_EFUSE4_EN = 1 or 0 otherwise" "KEY2_EN_0,KEY2_EN_1" bitfld.long 0x0C 0. "KEY1_EN,EFUSE enable Equals 1 when ISP5_EFUSE1_EN = 1 or 0 otherwise" "KEY1_EN_0,KEY1_EN_1" line.long 0x10 "ISP5_KEY_EN5,H3A eFuse enable" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "KEY_EN,EFUSE enable Equals 1 when ISP5_EFUSE2_EN = 1 or 0 otherwise" "KEY_EN_0,KEY_EN_1" line.long 0x14 "ISP5_KEY_EN6,H3A eFuse enable" hexmask.long 0x14 1.--31. 1. "RESERVED," bitfld.long 0x14 0. "KEY_EN,EFUSE enable Equals 1 when ISP5_EFUSE3_EN = 1 or 0 otherwise" "KEY_EN_0,KEY_EN_1" width 0x0B tree.end tree "ISP6P5_SYS3" base ad:0x52050000 rgroup.long 0x00++0x07 line.long 0x00 "ISP_KEY_EN7,GLBCE eFuse enable" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "KEY2_EN,EFUSE enable Equals 1 when ISP5_EFUSE6_EN = 1" "KEY2_EN_0,KEY2_EN_1" bitfld.long 0x00 0. "KEY1_EN,EFUSE Enable" "KEY1_EN_0,KEY1_EN_1" line.long 0x04 "ISP_SWT_SEL,Controls the Switch block in ISP-Top" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 8.--9. "GLBCE_SEL,Select GLBCE Module processing order" "GLBCE_SEL_0,GLBCE_SEL_1,GLBCE_SEL_2,GLBCE_SEL_3" rbitfld.long 0x04 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 4. "DPC_SEL," "DPC_SEL_0,DPC_SEL_1" rbitfld.long 0x04 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 0.--1. "NSF3V_SEL,Select NSF3V Module processing order" "NSF3V_SEL_0,NSF3V_SEL_1,NSF3V_SEL_2,NSF3V_SEL_3" group.long 0x0C++0x1F line.long 0x00 "ISP_NSF3V_MODESET,Note: This entry is not shadowed" hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED," bitfld.long 0x00 12.--13. "INPMOD,Data input mode for NSF3V (VP-1 and CAL-1) For CAL this value must be either 0 (RAW) or 1 (8bit) This bit can be changed only when NSF3V is in idle" "INPMOD_0,INPMOD_1,INPMOD_2,INPMOD_3" rbitfld.long 0x00 7.--11. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. "DPOL,Image sensor input data polarity (only for VP-1)" "DPOL_0,DPOL_1" rbitfld.long 0x00 4.--5. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 3. "HDPOL,HD Sync Signal Polarity of input signal (only for VP-1) Switch will convert HD polarity to high active regardless of the input polarity" "HDPOL_0,HDPOL_1" bitfld.long 0x00 2. "VDPOL,VD Sync Signal Polarity of input signal (Only for VP-1) Switch will convert VD polarity to high active regardless of the input polarity" "VDPOL_0,VDPOL_1" rbitfld.long 0x00 0.--1. "RESERVED," "0,1,2,3" line.long 0x04 "ISP_VP1_SPH,Start Pixel Horizontal" hexmask.long.tbyte 0x04 15.--31. 1. "RESERVED," hexmask.long.word 0x04 0.--14. 1. "SPH,The location of the first active pixel in a line" line.long 0x08 "ISP_VP1_LNH,This register is latched at VD or at corresponding SYNCEN rising edge" hexmask.long.tbyte 0x08 15.--31. 1. "RESERVED," hexmask.long.word 0x08 0.--14. 1. "LNH,Number of active pixels in an line Number of pixels = LNH + 1" line.long 0x0C "ISP_VP1_SLV,Start Line. Vertical" hexmask.long.tbyte 0x0C 15.--31. 1. "RESERVED," hexmask.long.word 0x0C 0.--14. 1. "SLV,Start Line Vertical Sets line at which active data will begin measured from the start of VD This register is latched at VD or at corresponding SYNCEN rising edge" line.long 0x10 "ISP_VP1_LNV," hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED," hexmask.long.word 0x10 0.--14. 1. "LNV,The number of active lines Number of lines = LNV + 1 This register is latched at VD or at corresponding SYNCEN rising edge" line.long 0x14 "ISP_NSF3V_CGAMMAWD," hexmask.long 0x14 5.--31. 1. "RESERVED," bitfld.long 0x14 1.--4. "GWDI,Selects MSB position of Input Data for NSF3V (VP-1 and CAL) For input of IN[15..0] corresponding output is given to DPC and/or NSF3V" "GWDI_0,GWDI_1,GWDI_2,GWDI_3,GWDI_4,GWDI_5,GWDI_6,GWDI_7,GWDI_8,GWDI_9,?,?,?,?,?,?" rbitfld.long 0x14 0. "RESERVED," "0,1" line.long 0x18 "ISP_VP1_CCDCFG," hexmask.long.byte 0x18 24.--31. 1. "RESERVED," bitfld.long 0x18 22.--23. "OO,The color pattern of the odd line and odd pixel used in DPC This parameter is valid when NSF3V_SEL=1 or 2 and DPC_SEL=1" "OO_0,OO_1,OO_2,OO_3" bitfld.long 0x18 20.--21. "OE,The color pattern of the odd line and even pixel used in DPC This parameter is valid when NSF3V_SEL=1 or 2 and DPC_SEL=1" "OE_0,OE_1,OE_2,OE_3" bitfld.long 0x18 18.--19. "EO,The color pattern of the even line and odd pixel used in DPC This parameter is valid when NSF3V_SEL=1 or 2 and DPC_SEL=1" "EO_0,EO_1,EO_2,EO_3" bitfld.long 0x18 16.--17. "EE,The color pattern of the even line and even pixel used in DPC This parameter is valid when NSF3V_SEL=1 or 2 and DPC_SEL=1" "EE_0,EE_1,EE_2,EE_3" newline rbitfld.long 0x18 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 11. "Y8POS,Selects Y signal position when in 8bit input mode" "Y8POS_0,Y8POS_1" rbitfld.long 0x18 5.--10. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 4. "YCINSWP,The ISIF module has a 16-bit interface" "YCINSWP_0,YCINSWP_1" rbitfld.long 0x18 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "ISP_VP1_DLAY,Horizontal/Vertical Delay of VP1 port" rbitfld.long 0x1C 31. "RESERVED," "0,1" bitfld.long 0x1C 30. "DELAY_SWT,This bit changes the delay between NSF3V input VD/HD and output VD/HD Usually this bit is '0'" "DELAY_SWT_0,DELAY_SWT_1" rbitfld.long 0x1C 24.--29. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x1C 16.--23. 1. "DLV,Vertical Delay of VP1 port from VS_IN to VD_OUT" hexmask.long.byte 0x1C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x1C 0.--7. 1. "DLH,This field is only used if DELAY_SWT=='1' and ignored if DELAY_SWT=='0' VP1 port horizontal delay from HS_IN (derived from HD_IN) to HD_OUT which affect the cycles between HD_OUT and first valid pixel" group.long 0x30++0x0B line.long 0x00 "ISP_VP2_SPH,Start Pixel Horizontal" hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED," hexmask.long.word 0x00 0.--14. 1. "SPH,The location of the first active pixel in a line" line.long 0x04 "RSERVED2,Reserved" line.long 0x08 "ISP_VP2_SLV,Start Line. Vertical" hexmask.long.tbyte 0x08 15.--31. 1. "RESERVED," hexmask.long.word 0x08 0.--14. 1. "SLV,Start Line Vertical Sets line at which active data will begin measured from the start of VD This register is latched at VD or at corresponding SYNCEN rising edge" group.long 0x40++0x07 line.long 0x00 "ISP_GLBCE_CGAMMAWD," hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED," bitfld.long 0x00 8.--11. "GWDO,Selects MSB position of output data from GLBCE (VP2/CAL2) This value is only used at GLBCE output and does not affect if GLBCE is skipped (IPIPEIF to IPIPE case)" "GWDO_0,GWDO_1,GWDO_2,GWDO_3,GWDO_4,GWDO_5,GWDO_6,GWDO_7,GWDO_8,GWDO_9,?,?,?,?,?,?" rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--4. "GWDI,Selects MSB position of Input Data for GLBCE (VP2/CAL2) This value is only used at GLBCE input and does not affect if GLBCE is skipped (IPIPEIF to IPIPE case)" "GWDI_0,GWDI_1,GWDI_2,GWDI_3,GWDI_4,GWDI_5,GWDI_6,GWDI_7,GWDI_8,GWDI_9,?,?,?,?,?,?" rbitfld.long 0x00 0. "RESERVED," "0,1" line.long 0x04 "ISP_VP2_DLAY,Horizontal/Vertical Delay of VP2 port" hexmask.long.byte 0x04 24.--31. 1. "RESERVED," hexmask.long.byte 0x04 16.--23. 1. "DLV,Vertical Delay of VP1 port from VS_IN to VD_IN" hexmask.long.byte 0x04 8.--15. 1. "RESERVED," hexmask.long.byte 0x04 0.--7. 1. "DLH,VP1 port horizontal delay from HS_IN (derived from HD_IN) to HD_OUT" group.long 0x50++0x0B line.long 0x00 "ISP_CNF_EN," hexmask.long 0x00 6.--31. 1. "RESERVED," bitfld.long 0x00 5. "CNFB_CDSEN,Note: This is don't care in ISP6.5 since CNF-B is removed" "CNFB_CDSEN_0,CNFB_CDSEN_1" bitfld.long 0x00 4. "CNFB_EN,?WARNING This shouldn't be enabled in ISP6.5 (ADAS-LOW Program) since CNF-B is removed" "CNFB_EN_0,CNFB_EN_1" rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 1. "CNFA_CDSEN,CDS (Chroma down sample) is enabled in CNF process on RZA path" "CNFA_CDSEN_0,CNFA_CDSEN_1" newline bitfld.long 0x00 0. "CNFA_EN,Enable CNF (Chroma noise filter) on RZA path This is only valid if the output is 420 and UV pass is active" "CNFA_EN_0,CNFA_EN_1" line.long 0x04 "ISP_CNFA_SIZ," rbitfld.long 0x04 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x04 16.--29. 1. "HEIGHT,The height of CNFA output" rbitfld.long 0x04 14.--15. "RESERVED," "0,1,2,3" hexmask.long.word 0x04 0.--13. 1. "WIDTH,The width of CNFA output" line.long 0x08 "ISP_CNFB_SIZ," rbitfld.long 0x08 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x08 16.--29. 1. "HEIGHT,Note: This is don't care in ISP6.5 since CNF-B is removed" rbitfld.long 0x08 14.--15. "RESERVED," "0,1,2,3" hexmask.long.word 0x08 0.--13. 1. "WIDTH,Note: This is don't care in ISP6.5 since CNF-B is removed" width 0x0B tree.end tree "ISS_CM_CORE_AON" base ad:0x4A005760 group.long 0x00++0x0B line.long 0x00 "CM_ISS_CLKSTCTRL,This register enables the ISS domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_ISS_GCLK,This field indicates the state of the ISS_GCLK clock in the domain" "CLKACTIVITY_ISS_GCLK_0,CLKACTIVITY_ISS_GCLK_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_ISS_ISS_CLKCTRL,This register manages the ISS clocks" hexmask.long.word 0x04 19.--31. 1. "RESERVED," rbitfld.long 0x04 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x04 2.--15. 1. "RESERVED," bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x08 "CM_ISS_STATICDEP,This register controls the static domain depedencies from ISS domain towards 'target' domains" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" hexmask.long.tbyte 0x08 6.--26. 1. "RESERVED," newline rbitfld.long 0x08 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" bitfld.long 0x08 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x08 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "ISS_CTSET" base ad:0x52010000 rgroup.long 0x00++0x03 line.long 0x00 "CTSETIDEN,CTSET identification register" group.long 0x10++0x07 line.long 0x00 "CTSETSYSCFG,CTSET system configuration register" hexmask.long 0x00 4.--31. 1. "RESERVED," bitfld.long 0x00 2.--3. "IDLEMODE," "0,1,2,3" rbitfld.long 0x00 1. "RESERVED," "0,1" bitfld.long 0x00 0. "SOFTRESET," "0,1" line.long 0x04 "SETSTR,SET status register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "HWFIFOEMPTY," "0,1" hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "RESETDONE," "0,1" group.long 0x24++0x07 line.long 0x00 "CTSETCFG,CTSET configuration register" bitfld.long 0x00 28.--31. "OWNERSHIP,Claim control and status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x00 8.--27. 1. "RESERVED," bitfld.long 0x00 7. "CAPENABLE,When high the system event capture is enabled" "0,1" rbitfld.long 0x00 5.--6. "RESERVED," "0,1,2,3" bitfld.long 0x00 4. "EVENTEDGE,High or Low level event detection" "0,1" bitfld.long 0x00 3. "DETECTMODE,Message generated based on event detection or sampling window" "0,1" bitfld.long 0x00 2. "STOPCAPONTRIG,Stop capturing system events from external trigger detection" "0,1" newline bitfld.long 0x00 1. "STARTCAPONTRIG,Start capturing systetm events from external trigger detection" "0,1" rbitfld.long 0x00 0. "RESERVED," "0,1" line.long 0x04 "SETSPLREG,System event sampling window register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," hexmask.long.byte 0x04 0.--7. 1. "WINDOWSIZE," group.long 0x30++0x23 line.long 0x00 "SETEVTENBL1,System event detection enable register 1" line.long 0x04 "SETEVTENBL2,System event detection enable register 2" line.long 0x08 "SETEVTENBL3," line.long 0x0C "SETEVTENBL4," line.long 0x10 "SETEVTENBL5," line.long 0x14 "SETEVTENBL6," line.long 0x18 "SETEVTENBL7," line.long 0x1C "SETEVTENBL8," rbitfld.long 0x1C 31. "RESERVED," "0,1" hexmask.long 0x1C 0.--30. 1. "EVTENABLE,Event 225 to 255 detection enable bits" line.long 0x20 "SETMSTID,System Event Master ID" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED," hexmask.long.byte 0x20 0.--7. 1. "MASTID,HW Master ID for SET" group.long 0x800++0x03 line.long 0x00 "CTCNTL,Counter Timer Control" rbitfld.long 0x00 26.--31. "NUMSTM," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 18.--25. 1. "NUMINPT," rbitfld.long 0x00 13.--17. "NUMTIMR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 7.--12. "NUMCNTR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 3.--6. "REVID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1.--2. "RESERVED," "0,1,2,3" bitfld.long 0x00 0. "ENBL," "0,1" group.long 0x820++0x0B line.long 0x00 "CTSTMCNTL,Counter Timer STM Control" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED," bitfld.long 0x00 6.--11. "NUMXPORT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 5. "XPORTACT," "0,1" bitfld.long 0x00 4. "CCMXPORT," "0,1" rbitfld.long 0x00 3. "CCMAVAIL," "0,1" bitfld.long 0x00 2. "CSMXPORT," "0,1" bitfld.long 0x00 1. "SENDOVR," "0,1" newline bitfld.long 0x00 0. "ENBL," "0,1" line.long 0x04 "CTSTMMSTID,CTM STM Master ID register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," hexmask.long.byte 0x04 0.--7. 1. "MASTID," line.long 0x08 "CTSTMINTVL,CTM STM interval register" hexmask.long.word 0x08 16.--31. 1. "RESERVED," hexmask.long.word 0x08 0.--15. 1. "INTERVAL," rgroup.long 0x8C0++0x03 line.long 0x00 "CTNUMDBG,CTM Debug Event Register" hexmask.long 0x00 4.--31. 1. "RESERVED," bitfld.long 0x00 0.--3. "NUMEVNT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC00++0x13 line.long 0x00 "CTEOI,Counter Timer EOI Register" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "EOI," "0,1" line.long 0x04 "CTIRQSTAT_RAW,Counter Timer IRQ raw status register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," hexmask.long.byte 0x04 0.--7. 1. "TIM_INT_IRQ," line.long 0x08 "CTIRQSTAT,Counter Timer IRQ Status Register" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED," hexmask.long.byte 0x08 0.--7. 1. "TIM_INT," line.long 0x0C "CTIRQENABLE_SET,Counter Timer IRQ eable set register" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED," hexmask.long.byte 0x0C 0.--7. 1. "TIM_INT_IES," line.long 0x10 "CTIRQENABLE_CLR,Counter Timer IRQ enable clear register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED," hexmask.long.byte 0x10 0.--7. 1. "TIM_INT_IEC," repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0xB40)++0x03 line.long 0x00 "CTCNTR$1,Counter Timer Counter Register" repeat.end repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0xB00)++0x03 line.long 0x00 "CTCNTR$1,Counter Timer Counter Register" repeat.end repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xA40)++0x03 line.long 0x00 "CTCR$1,Counter Timer Control Register" hexmask.long.byte 0x00 24.--31. 1. "WDRESET," hexmask.long.byte 0x00 16.--23. 1. "INPSEL," newline rbitfld.long 0x00 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 12. "DBG_TRIG_STAT," "0,1" newline bitfld.long 0x00 11. "WDMODE," "0,1" bitfld.long 0x00 10. "RESTART," "0,1" newline bitfld.long 0x00 9. "DBG," "0,1" bitfld.long 0x00 8. "INT," "0,1" newline rbitfld.long 0x00 7. "CHNSDW," "0,1" rbitfld.long 0x00 6. "OVRFLW," "0,1" newline bitfld.long 0x00 5. "IDLE," "0,1" bitfld.long 0x00 4. "FREE," "0,1" newline bitfld.long 0x00 3. "DURMODE," "0,1" bitfld.long 0x00 2. "CHAIN," "0,1" newline bitfld.long 0x00 1. "RESET," "0,1" bitfld.long 0x00 0. "ENBL," "0,1" repeat.end repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xA00)++0x03 line.long 0x00 "CTCR$1,Counter Timer Control Register" hexmask.long.byte 0x00 24.--31. 1. "WDRESET," hexmask.long.byte 0x00 16.--23. 1. "INPSEL," newline rbitfld.long 0x00 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 12. "DBG_TRIG_STAT," "0,1" newline bitfld.long 0x00 11. "WDMODE," "0,1" bitfld.long 0x00 10. "RESTART," "0,1" newline bitfld.long 0x00 9. "DBG," "0,1" bitfld.long 0x00 8. "INT," "0,1" newline rbitfld.long 0x00 7. "CHNSDW," "0,1" rbitfld.long 0x00 6. "OVRFLW," "0,1" newline bitfld.long 0x00 5. "IDLE," "0,1" bitfld.long 0x00 4. "FREE," "0,1" newline bitfld.long 0x00 3. "DURMODE," "0,1" bitfld.long 0x00 2. "CHAIN," "0,1" newline bitfld.long 0x00 1. "RESET," "0,1" bitfld.long 0x00 0. "ENBL," "0,1" repeat.end repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x9F8)++0x03 line.long 0x00 "CTGRST$1,CTM Global Reset Register 0" repeat.end repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x9F0)++0x03 line.long 0x00 "CTGNBL$1,CTM Global Enable Register 0" repeat.end repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C ) group.long ($2+0x8C4)++0x03 line.long 0x00 "CTDBGSGL$1,CTM Debug Event Register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," hexmask.long.byte 0x00 0.--7. 1. "INPSEL," repeat.end repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x840)++0x03 line.long 0x00 "TINTVLR$1,Timer Interval Register 0" repeat.end repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x82C)++0x03 line.long 0x00 "CTSTMSEL$1,CTM STM counter select register" repeat.end width 0x0B tree.end tree "ISS_FW" base ad:0x4A23E000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" newline rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "ISS_FW_CFG_TARG" base ad:0x4A23F000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "ISS_PRM" base ad:0x4AE07C80 group.long 0x00++0x07 line.long 0x00 "PM_ISS_PWRSTCTRL,This register controls the ISS power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "ISS_BANK_ONSTATE,ISS_BANK state when domain is ON" "?,?,?,ISS_BANK_ONSTATE_3" hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "ISS_BANK_RETSTATE,ISS_BANK state when domain is RETENTION" "ISS_BANK_RETSTATE_0,ISS_BANK_RETSTATE_1" rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION" "LOGICRETSTATE_0,LOGICRETSTATE_1" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_ISS_PWRSTST,This register provides a status on the ISS domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "ISS_BANK_STATEST,ISS_BANK memory state status" "ISS_BANK_STATEST_0,ISS_BANK_STATEST_1,ISS_BANK_STATEST_2,ISS_BANK_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x20++0x07 line.long 0x00 "PM_ISS_ISS_WKDEP,This register controls wakeup dependency based on ISS service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_ISS_EVE4,Wakeup dependency from ISS module (Swakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_EVE4_0,WKUPDEP_ISS_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_ISS_EVE3,Wakeup dependency from ISS module (Swakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_EVE3_0,WKUPDEP_ISS_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_ISS_EVE2,Wakeup dependency from ISS module (Swakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_EVE2_0,WKUPDEP_ISS_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_ISS_EVE1,Wakeup dependency from ISS module ( Swakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_EVE1_0,WKUPDEP_ISS_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_ISS_DSP2,Wakeup dependency from ISS module (Swakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_DSP2_0,WKUPDEP_ISS_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_ISS_IPU1,Wakeup dependency from ISS module (Swakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_IPU1_0,WKUPDEP_ISS_IPU1_1" rbitfld.long 0x00 3. "RESERVED," "0,1" bitfld.long 0x00 2. "WKUPDEP_ISS_DSP1,Wakeup dependency from ISS module (Swakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_DSP1_0,WKUPDEP_ISS_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_ISS_IPU2,Wakeup dependency from ISS module ( Swakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_IPU2_0,WKUPDEP_ISS_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_ISS_MPU,Wakeup dependency from ISS module (Swakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_MPU_0,WKUPDEP_ISS_MPU_1" line.long 0x04 "RM_ISS_ISS_CONTEXT,This register contains dedicated ISS context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_ISS_BANK,Specify if memory-based context in ISS memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_ISS_BANK_0,LOSTMEM_ISS_BANK_1" hexmask.long.byte 0x04 1.--7. 1. "RESERVED," newline bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "ISS_TARG" base ad:0x44000800 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "ISS_TCTRL" base ad:0x520000C0 rgroup.long 0x00++0x0B line.long 0x00 "TCTRL_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "TCTRL_SYSCONFIG,OCP-SOCKET SYSTEM CONFIGURATION REGISTER" hexmask.long 0x04 2.--31. 1. "RESERVED," bitfld.long 0x04 1. "SOFT_RESET,Software reset" "SOFT_RESET_0,SOFT_RESET_1" bitfld.long 0x04 0. "AUTO_IDLE,Internal OCP and functional clock gating strategy" "AUTO_IDLE_0,AUTO_IDLE_1" line.long 0x08 "TCTRL_SYSSTATUS,OCP-SOCKET SYSTEM STATUS REGISTER" hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "RESET_DONE,Internal reset monitoring" "RESET_DONE_0_r,RESET_DONE_1_r" group.long 0x10++0x1B line.long 0x00 "TCTRL_STRB_LENGTH,TIMING CONTROL - STROBE LENGTH REGISTER This register is used by the TIMING CTRL module to generate the STROBE signal" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--23. 1. "LENGTH,Sets the length of the CAM_STROBE signal assertion in cycles of the CNTCLK clock" line.long 0x04 "TCTRL_PSTRB_LENGTH,TIMING CONTROL - PRESTROBE LENGTH REGISTER This register is used by the TIMING CTRL module to generate the PRESTROBE signal" hexmask.long.byte 0x04 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x04 0.--23. 1. "LENGTH,Sets the length of the CAM_PRESTROBE signal assertion in cycles of the CNTCLK clock" line.long 0x08 "TCTRL_SHUT_LENGTH,TIMING CONTROL - SHUTTER LENGTH REGISTER This register is used by the TIMING CTRL module to generate the CAM_SHUTTER signal" hexmask.long.byte 0x08 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x08 0.--23. 1. "LENGTH,Sets the length of the CAM_SHUTTER signal assertion in cycles of the CNTCLK clock" line.long 0x0C "TCTRL_GRESET_LENGTH,TIMING CONTROL - GLOBAL SHUTTER LENGTH REGISTER This register is used by the TIMING CTRL module to generate the CAM_GLOBALRESET signal" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x0C 0.--23. 1. "LENGTH,Sets the length of the CAM_GLOBALRESET signal assertion in cycles of the CNTCLK clock" line.long 0x10 "TCTRL_STRB_DELAY,TIMING CONTROL - STROBE DELAY REGISTER This register is used by the TIMING CTRL module to generate the STROBE signal" hexmask.long.byte 0x10 25.--31. 1. "RESERVED," hexmask.long 0x10 0.--24. 1. "DELAY,Sets the delay for the CAM_STROBE signal assertion in cycles of the CNTCLK clock" line.long 0x14 "TCTRL_PSTRB_DELAY,TIMING CONTROL - PRE STROBE DELAY REGISTER This register is used by the TIMING CTRL module to generate the PRESTROBE signal" hexmask.long.byte 0x14 25.--31. 1. "RESERVED," hexmask.long 0x14 0.--24. 1. "DELAY,Sets the delay for the PRESTROBE signal assertion in cycles of the CNTCLK clock" line.long 0x18 "TCTRL_SHUT_DELAY,TIMING CONTROL - SHUTTER DELAY REGISTER This register is used by the TIMING CTRL module to generate the CAM_SHUTTER signal" hexmask.long.byte 0x18 25.--31. 1. "RESERVED," hexmask.long 0x18 0.--24. 1. "DELAY,Sets the delay for the CAM_SHUTTER signal assertion in cycles of the CNTCLK clock" group.long 0x30++0x0B line.long 0x00 "TCTRL_CTRL,TIMING CONTROL - CONTROL REGISTER" bitfld.long 0x00 31. "GRESETDIR,Sets the direction of the CAM_GLOBAL_RESET signal" "INPUT - CAM_GLOBALRESET is an input to the..,OUTPUT - CAM_GLOBALRESET is an output of the.." bitfld.long 0x00 30. "GRESETPOL,Sets the polarity of the global reset signal: CAM_GLOBALRESET" "active high,active low" bitfld.long 0x00 29. "GRESETEN,Triggers the generation of the CAM_GLOBALRESET signal" "0,1" newline bitfld.long 0x00 27.--28. "INSEL,Sets the mode that will trigger the SHUTTER PRESTROBE and STROBE signals" "INSEL_0,INSEL_1,INSEL_2,INSEL_3" bitfld.long 0x00 26. "STRBPSTRBPOL,Sets the polarity of the strobe and prestrobe signals" "STRBPSTRBPOL_0,STRBPSTRBPOL_1" rbitfld.long 0x00 25. "RESERVED," "0,1" newline bitfld.long 0x00 24. "SHUTPOL,Sets the polarity of the mechanical shutter signal: CAM_SHUTTER" "SHUTPOL_0,SHUTPOL_1" bitfld.long 0x00 23. "STRBEN,Flash strobe signal enable" "0,1" bitfld.long 0x00 22. "PSTRBEN,Flash prestrobe signal enable" "0,1" newline bitfld.long 0x00 21. "SHUTEN,Mechanical shutter signal enable" "0,1" bitfld.long 0x00 19.--20. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x00 10.--18. 1. "DIVC,Sets the clock divisor value for the CNTCLK clock generation based on the CLK input clock" newline hexmask.long.word 0x00 0.--9. 1. "RESERVED," line.long 0x04 "TCTRL_PSTRB_REPLAY,TIMING CONTROL - PRESTROBE REPLAY REGISTER This register is used by the TIMING CTRL module to generate the prestrobe signal" hexmask.long.byte 0x04 25.--31. 1. "COUNTER,Sets the number of PRESTROBE pulses after the original pulse" hexmask.long 0x04 0.--24. 1. "DELAY,Sets the delay for the PRESTROBE signal reassertion in cycles of the CNTCLK clock" line.long 0x08 "TCTRL_FRAME,TIMING CONTROL - FRAME REGISTER This register is used by the TIMING CTRL module to generate the SHUTTER. PRESTROBE. and STROBE signals" hexmask.long.word 0x08 18.--31. 1. "RESERVED," bitfld.long 0x08 12.--17. "STRB,Frame counter for the STROBE signal generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 6.--11. "PSTRB,Frame counter for the PRESTROBE signal generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 0.--5. "SHUT,Frame counter for the SHUTTER signal generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end tree "ISS_TOP" base ad:0x52000000 rgroup.long 0x00++0x07 line.long 0x00 "ISS_HL_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "ISS_HL_HWINFO,This register is reserved and users should write the reset value to this register location" hexmask.long 0x04 3.--31. 1. "RESERVED," bitfld.long 0x04 0.--2. "BRIDGE_BUFF,Size of the re-ordering buffer in the CCP2 read bridge" "BRIDGE_BUFF_0,BRIDGE_BUFF_1,BRIDGE_BUFF_2,BRIDGE_BUFF_3,BRIDGE_BUFF_4,?,?,?" group.long 0x10++0x03 line.long 0x00 "ISS_HL_SYSCONFIG,Clock management configuration" hexmask.long 0x00 6.--31. 1. "RESERVED," bitfld.long 0x00 4.--5. "STANDBYMODE,Master interface power management standby/Wait control" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x00 2.--3. "IDLEMODE,IDLE protocol configuration" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline rbitfld.long 0x00 1. "RESERVED," "0,1" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x1C++0x0B line.long 0x00 "ISS_HL_IRQ_EOI,End Of Interrupt number specification" hexmask.long 0x00 3.--31. 1. "RESERVED," bitfld.long 0x00 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1,LINE_NUMBER_2,LINE_NUMBER_3,LINE_NUMBER_4,LINE_NUMBER_5,?,?" line.long 0x04 "ISS_HL_IRQSTATUS_RAW_i,Per-event raw interrupt status vector. line #0" rbitfld.long 0x04 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" rbitfld.long 0x04 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x04 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x04 27. "LVDSRX1_IRQ," "0,1" rbitfld.long 0x04 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x04 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x04 23. "CAL_B_IRQ,Event generated by the CAL #B" "No event pending,Event pending" rbitfld.long 0x04 22. "CAL_A_IRQ,Event generated by the CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x04 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x04 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x04 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x04 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" rbitfld.long 0x04 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" rbitfld.long 0x04 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline rbitfld.long 0x04 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x04 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" rbitfld.long 0x04 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline rbitfld.long 0x04 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" rbitfld.long 0x04 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" rbitfld.long 0x04 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" line.long 0x08 "ISS_HL_IRQSTATUS_i_0,Per-event 'enabled' interrupt status vector. line #0" rbitfld.long 0x08 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" rbitfld.long 0x08 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x08 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x08 27. "LVDSRX1_IRQ," "0,1" rbitfld.long 0x08 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x08 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x08 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 23. "CAL_B_IRQ,Event generated by CAL #B" "No (enabled) event pending,Event pending" rbitfld.long 0x08 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x08 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x08 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x08 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x08 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x08 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x08 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" rbitfld.long 0x08 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" rbitfld.long 0x08 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline rbitfld.long 0x08 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x08 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x08 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x08 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x08 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x08 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x08 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x08 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" rbitfld.long 0x08 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline rbitfld.long 0x08 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" rbitfld.long 0x08 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" rbitfld.long 0x08 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x34++0x03 line.long 0x00 "ISS_HL_IRQSTATUS_i_1,Per-event 'enabled' interrupt status vector. line #0" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" rbitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" rbitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No (enabled) event pending,Event pending" rbitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" rbitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" rbitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline rbitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" rbitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline rbitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" rbitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" rbitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x44++0x03 line.long 0x00 "ISS_HL_IRQSTATUS_i_2,Per-event 'enabled' interrupt status vector. line #0" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" rbitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" rbitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No (enabled) event pending,Event pending" rbitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" rbitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" rbitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline rbitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" rbitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline rbitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" rbitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" rbitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x54++0x03 line.long 0x00 "ISS_HL_IRQSTATUS_i_3,Per-event 'enabled' interrupt status vector. line #0" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" rbitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" rbitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No (enabled) event pending,Event pending" rbitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" rbitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" rbitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline rbitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" rbitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline rbitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" rbitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" rbitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x64++0x03 line.long 0x00 "ISS_HL_IRQSTATUS_i_4,Per-event 'enabled' interrupt status vector. line #0" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" rbitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" rbitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No (enabled) event pending,Event pending" rbitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" rbitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" rbitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline rbitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" rbitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline rbitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" rbitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" rbitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x74++0x03 line.long 0x00 "ISS_HL_IRQSTATUS_i_5,Per-event 'enabled' interrupt status vector. line #0" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" rbitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" rbitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No (enabled) event pending,Event pending" rbitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" rbitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" rbitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline rbitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" rbitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline rbitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" rbitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" rbitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x28++0x03 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_0,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Enable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x38++0x03 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_1,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Enable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x48++0x03 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_2,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Enable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x58++0x03 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_3,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Enable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x68++0x03 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_4,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Enable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x78++0x03 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_5,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Enable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x2C++0x03 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_0,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Disable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x3C++0x03 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_1,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Disable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x4C++0x03 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_2,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Disable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x5C++0x03 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_3,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Disable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x6C++0x03 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_4,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Disable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x7C++0x43 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_5,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" rbitfld.long 0x00 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" newline rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Disable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 21. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX" "VMUX_IRQ_0,VMUX_IRQ_1" newline rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4.--5. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" line.long 0x04 "ISS_CTRL,ISS control register" hexmask.long.byte 0x04 24.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x04 20.--23. "CCP2W_TAG_CNT,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. "CCP2R_TAG_CNT,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x04 8.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x04 6.--7. "INPUT_SEL2,This bit field is reserved and users should write the reset value to this bit location" "INPUT_SEL2_0,INPUT_SEL2_1,INPUT_SEL2_2,INPUT_SEL2_3" bitfld.long 0x04 4.--5. "ISS_CLK_DIV,ISS functional clock division CLK refers to the input clock provided to the ISS FCLK is the functional clock provided to ISS top level and sub modules CFGCLK is the clock used for the configuration network" "ISS_CLK_DIV_0,ISS_CLK_DIV_1,ISS_CLK_DIV_2,ISS_CLK_DIV_3" newline bitfld.long 0x04 2.--3. "INPUT_SEL,This bit field is reserved and users should write the reset value to this bit location" "INPUT_SEL_0,?,INPUT_SEL_2,INPUT_SEL_3" bitfld.long 0x04 0.--1. "SYNC_DETECT,Chooses among rising and falling edge for the HS_VS_IRQ synchronization event" "SYNC_DETECT_0,SYNC_DETECT_1,SYNC_DETECT_2,SYNC_DETECT_3" line.long 0x08 "ISS_CLKCTRL,ISS clock control register" rbitfld.long 0x08 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x08 29. "LVDSRX_OUT3_PCLK,Enables the pixel clock at VMUX input level" "LVDSRX_OUT3_PCLK_0,LVDSRX_OUT3_PCLK_1" bitfld.long 0x08 28. "LVDSRX_OUT2_PCLK,This bit field is reserved and users should write the reset value to this bit location" "LVDSRX_OUT2_PCLK_0,LVDSRX_OUT2_PCLK_1" newline bitfld.long 0x08 27. "LVDSRX_OUT1_PCLK,This bit field is reserved and users should write the reset value to this bit location" "LVDSRX_OUT1_PCLK_0,LVDSRX_OUT1_PCLK_1" bitfld.long 0x08 26. "LVDSRX_OUT0_PCLK,Enables the pixel clock at VMUX input level" "LVDSRX_OUT0_PCLK_0,LVDSRX_OUT0_PCLK_1" bitfld.long 0x08 25. "GLBCE_OUT_PCLK,Enables the pixel clock at VMUX input level" "GLBCE_OUT_PCLK_0,GLBCE_OUT_PCLK_1" newline bitfld.long 0x08 24. "NSF3V_OUT_PCLK,Enables the pixel clock at VMUX input level" "NSF3V_OUT_PCLK_0,NSF3V_OUT_PCLK_1" bitfld.long 0x08 23. "BYS_B_OUT_PCLK,This bit field is reserved and users should write the reset value to this bit location" "BYS_B_OUT_PCLK_0,BYS_B_OUT_PCLK_1" bitfld.long 0x08 22. "BYS_A_OUT_PCLK,This bit field is reserved and users should write the reset value to this bit location" "BYS_A_OUT_PCLK_0,BYS_A_OUT_PCLK_1" newline bitfld.long 0x08 21. "PARALLEL_A_PCLK,Enables the pixel clock at VMUX input level" "PARALLEL_A_PCLK_0,PARALLEL_A_PCLK_1" bitfld.long 0x08 20. "CAL_B_OUT_PCLK,Enables the pixel clock at VMUX input level" "CAL_B_OUT_PCLK_0,CAL_B_OUT_PCLK_1" bitfld.long 0x08 19. "CAL_B_BYS_OUT_PCLK,Enables the pixel clock at VMUX input level" "CAL_B_BYS_OUT_PCLK_0,CAL_B_BYS_OUT_PCLK_1" newline bitfld.long 0x08 18. "CAL_A_OUT_PCLK,Enables the pixel clock at VMUX input level" "CAL_A_OUT_PCLK_0,CAL_A_OUT_PCLK_1" bitfld.long 0x08 17. "CAL_A_BYS_OUT_PCLK,Enables the pixel clock at VMUX input level" "CAL_A_BYS_OUT_PCLK_0,CAL_A_BYS_OUT_PCLK_1" bitfld.long 0x08 16. "CCP2_PCLK,This bit field is reserved and users should write the reset value to this bit location" "CCP2_PCLK_0,CCP2_PCLK_1" newline rbitfld.long 0x08 15. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 14. "CTSET,CTSET" "CTSET_0,CTSET_1" bitfld.long 0x08 13. "LVDSRX,LVDSRX" "LVDSRX_0,LVDSRX_1" newline bitfld.long 0x08 12. "ICM_A,This bit field is reserved and users should write the reset value to this bit location" "ICM_A_0,ICM_A_1" bitfld.long 0x08 11. "ICM_B,This bit field is reserved and users should write the reset value to this bit location" "ICM_B_0,ICM_B_1" bitfld.long 0x08 10. "CAL_B,CAL #B" "CAL_B_0,CAL_B_1" newline bitfld.long 0x08 9. "CAL_A,CAL #A" "CAL_A_0,CAL_A_1" rbitfld.long 0x08 8. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 7. "BYS_B,This bit field is reserved and users should write the reset value to this bit location" "BYS_B_0,BYS_B_1" newline rbitfld.long 0x08 6. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 5. "BYS_A,This bit field is reserved and users should write the reset value to this bit location" "BYS_A_0,BYS_A_1" bitfld.long 0x08 4. "CCP2,This bit field is reserved and users should write the reset value to this bit location" "CCP2_0,CCP2_1" newline rbitfld.long 0x08 2.--3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x08 1. "ISP,ISP" "ISP_0,ISP_1" bitfld.long 0x08 0. "SIMCOP,SIMCOP" "SIMCOP_0,SIMCOP_1" line.long 0x0C "ISS_CLKSTAT,ISS clock status register" bitfld.long 0x0C 30.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x0C 29. "LVDSRX_OUT3_PCLK,Status of the pixel clock" "LVDSRX_OUT3_PCLK_0,LVDSRX_OUT3_PCLK_1" bitfld.long 0x0C 28. "LVDSRX_OUT2_PCLK,This bit field is reserved and users should write the reset value to this bit location" "LVDSRX_OUT2_PCLK_0,LVDSRX_OUT2_PCLK_1" newline bitfld.long 0x0C 27. "LVDSRX_OUT1_PCLK,This bit field is reserved and users should write the reset value to this bit location" "LVDSRX_OUT1_PCLK_0,LVDSRX_OUT1_PCLK_1" bitfld.long 0x0C 26. "LVDSRX_OUT0_PCLK,Status of the pixel clock" "LVDSRX_OUT0_PCLK_0,LVDSRX_OUT0_PCLK_1" bitfld.long 0x0C 25. "GLBCE_OUT_PCLK,Status of the pixel clock" "GLBCE_OUT_PCLK_0,GLBCE_OUT_PCLK_1" newline bitfld.long 0x0C 24. "NSF3V_OUT_PCLK,Status of the pixel clock" "NSF3V_OUT_PCLK_0,NSF3V_OUT_PCLK_1" bitfld.long 0x0C 23. "BYS_B_OUT_PCLK,This bit field is reserved and users should write the reset value to this bit location" "BYS_B_OUT_PCLK_0,BYS_B_OUT_PCLK_1" bitfld.long 0x0C 22. "BYS_A_OUT_PCLK,This bit field is reserved and users should write the reset value to this bit location" "BYS_A_OUT_PCLK_0,BYS_A_OUT_PCLK_1" newline bitfld.long 0x0C 21. "PARALLEL_A_PCLK,Status of the pixel clock" "PARALLEL_A_PCLK_0,PARALLEL_A_PCLK_1" bitfld.long 0x0C 20. "CAL_B_OUT_PCLK,Status of the pixel clock" "CAL_B_OUT_PCLK_0,CAL_B_OUT_PCLK_1" bitfld.long 0x0C 19. "CAL_B_BYS_OUT_PCLK,Status of the pixel clock" "CAL_B_BYS_OUT_PCLK_0,CAL_B_BYS_OUT_PCLK_1" newline bitfld.long 0x0C 18. "CAL_A_OUT_PCLK,Status of the pixel clock" "CAL_A_OUT_PCLK_0,CAL_A_OUT_PCLK_1" bitfld.long 0x0C 17. "CAL_A_BYS_OUT_PCLK,Status of the pixel clock" "CAL_A_BYS_OUT_PCLK_0,CAL_A_BYS_OUT_PCLK_1" bitfld.long 0x0C 16. "CCP2_PCLK,This bit field is reserved and users should write the reset value to this bit location" "CCP2_PCLK_0,CCP2_PCLK_1" newline bitfld.long 0x0C 15. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x0C 14. "CTSET,CTSET" "CTSET_0,CTSET_1" bitfld.long 0x0C 13. "LVDSRX,LVDSRX" "LVDSRX_0,LVDSRX_1" newline bitfld.long 0x0C 12. "ICM_A,This bit field is reserved and users should write the reset value to this bit location" "ICM_A_0,ICM_A_1" bitfld.long 0x0C 11. "ICM_B,This bit field is reserved and users should write the reset value to this bit location" "ICM_B_0,ICM_B_1" bitfld.long 0x0C 10. "CAL_B,CAL #B" "CAL_B_0,CAL_B_1" newline bitfld.long 0x0C 9. "CAL_A,CAL #A" "CAL_A_0,CAL_A_1" bitfld.long 0x0C 8. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x0C 7. "BYS_B,This bit field is reserved and users should write the reset value to this bit location" "BYS_B_0,BYS_B_1" newline bitfld.long 0x0C 6. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x0C 5. "BYS_A,This bit field is reserved and users should write the reset value to this bit location" "BYS_A_0,BYS_A_1" bitfld.long 0x0C 4. "CCP2,This bit field is reserved and users should write the reset value to this bit location" "CCP2_0,CCP2_1" newline bitfld.long 0x0C 2.--3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x0C 1. "ISP,ISP" "ISP_0,ISP_1" bitfld.long 0x0C 0. "SIMCOP,SIMCOP" "SIMCOP_0,SIMCOP_1" line.long 0x10 "ISS_PM_STATUS,ISS power manager status register" bitfld.long 0x10 28.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 26.--27. "CTSET,Power status of the CTSET module" "CTSET_0,CTSET_1,CTSET_2,?" bitfld.long 0x10 24.--25. "ICM_A,This bit field is reserved and users should write the reset value to this bit location" "ICM_A_0,ICM_A_1,ICM_A_2,?" newline bitfld.long 0x10 22.--23. "ICM_B,This bit field is reserved and users should write the reset value to this bit location" "ICM_B_0,ICM_B_1,ICM_B_2,?" bitfld.long 0x10 20.--21. "CAL_B,Power status of the CAL #B module" "CAL_B_0,CAL_B_1,CAL_B_2,?" bitfld.long 0x10 18.--19. "CAL_A,Power status of the CAL #A module" "CAL_A_0,CAL_A_1,CAL_A_2,?" newline bitfld.long 0x10 14.--17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 12.--13. "CBUFF_PM,This bit field is reserved and users should write the reset value to this bit location" "CBUFF_PM_0,CBUFF_PM_1,CBUFF_PM_2,?" bitfld.long 0x10 10.--11. "BTE_PM,This bit field is reserved and users should write the reset value to this bit location" "BTE_PM_0,BTE_PM_1,BTE_PM_2,?" newline bitfld.long 0x10 8.--9. "SIMCOP_PM,Power status of the SIMCOP module" "SIMCOP_PM_0,SIMCOP_PM_1,SIMCOP_PM_2,?" bitfld.long 0x10 6.--7. "ISP_PM,Power status of the ISP module" "ISP_PM_0,ISP_PM_1,ISP_PM_2,?" bitfld.long 0x10 4.--5. "CCP2_PM,This bit field is reserved and users should write the reset value to this bit location" "CCP2_PM_0,CCP2_PM_1,CCP2_PM_2,?" newline bitfld.long 0x10 0.--3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "ISS_BYS,This register is reserved and users should write the reset value to this register location" hexmask.long.tbyte 0x14 15.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x14 14. "CSI3A_IN,This bit field is reserved and users should write the reset value to this bit location" "CSI3A_IN_0,CSI3A_IN_1" hexmask.long.byte 0x14 7.--13. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline bitfld.long 0x14 4.--6. "BYSB_IN,This bit field is reserved and users should write the reset value to this bit location" "BYSB_IN_0,BYSB_IN_1,?,?,BYSB_IN_4,BYSB_IN_5,?,?" rbitfld.long 0x14 3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x14 0.--2. "BYSA_IN,This bit field is reserved and users should write the reset value to this bit location" "BYSA_IN_0,BYSA_IN_1,?,?,BYSA_IN_4,BYSA_IN_5,?,?" line.long 0x18 "ISS_CTRL1,ISS control register" hexmask.long.word 0x18 17.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x18 16. "PPI_MODE,Controls PPI interface - CAL mux at ISS level" "PPI_MODE_0,PPI_MODE_1" bitfld.long 0x18 13.--15. "STALL_MODE,Refer to the functional specification for details" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 7.--12. "SENSOR_HUB_SYNC,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 5.--6. "BTE_WMEM,This bit field is reserved and users should write the reset value to this bit location" "BTE_WMEM_0,BTE_WMEM_1,?,?" bitfld.long 0x18 4. "ENABLE_VMUX,Enables the video mux instead of legacy mode for ISP #A input and BYS connections" "ENABLE_VMUX_0,ENABLE_VMUX_1" newline rbitfld.long 0x18 2.--3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x18 0.--1. "CTSET_EVT,CTSET event selection" "0,1,2,3" line.long 0x1C "ISS_VMUX,ISS video mux control" rbitfld.long 0x1C 31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x1C 28.--30. "BYS_B_IN,This bit field is reserved and users should write the reset value to this bit location" "BYS_B_IN_0,BYS_B_IN_1,BYS_B_IN_2,BYS_B_IN_3,BYS_B_IN_4,BYS_B_IN_5,?,?" rbitfld.long 0x1C 27. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x1C 24.--26. "BYS_A_IN,This bit field is reserved and users should write the reset value to this bit location" "BYS_A_IN_0,BYS_A_IN_1,BYS_A_IN_2,BYS_A_IN_3,BYS_A_IN_4,BYS_A_IN_5,?,?" bitfld.long 0x1C 20.--23. "CAL_B_BYS_IN,This bit field is reserved and users should write the reset value to this bit location" "CAL_B_BYS_IN_0,CAL_B_BYS_IN_1,CAL_B_BYS_IN_2,CAL_B_BYS_IN_3,CAL_B_BYS_IN_4,CAL_B_BYS_IN_5,CAL_B_BYS_IN_6,?,CAL_B_BYS_IN_8,CAL_B_BYS_IN_9,?,?,?,?,?,?" bitfld.long 0x1C 16.--19. "CAL_A_BYS_IN,Data source connected to the BYSin port of CAL #A" "CAL_A_BYS_IN_0,CAL_A_BYS_IN_1,CAL_A_BYS_IN_2,CAL_A_BYS_IN_3,CAL_A_BYS_IN_4,CAL_A_BYS_IN_5,CAL_A_BYS_IN_6,CAL_A_BYS_IN_7,CAL_A_BYS_IN_8,CAL_A_BYS_IN_9,?,?,?,?,?,?" newline rbitfld.long 0x1C 12.--15. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 8.--11. "GLBCE_IN,Data source connected to GLBCE" "GLBCE_IN_0,GLBCE_IN_1,GLBCE_IN_2,GLBCE_IN_3,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x1C 4.--7. "NSF3V_IN,Data source connected to NSF3V" "NSF3V_IN_0,NSF3V_IN_1,NSF3V_IN_2,NSF3V_IN_3,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x1C 0.--3. "ISP_IN,Data source connected to ISP" "ISP_IN_0,ISP_IN_1,ISP_IN_2,ISP_IN_3,ISP_IN_4,ISP_IN_5,ISP_IN_6,ISP_IN_7,ISP_IN_8,?,?,?,?,?,?,?" line.long 0x20 "ISS_ROUTE1,Controls traffic routing inside ISS" hexmask.long.word 0x20 16.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x20 14.--15. "CALA_7,CPort #7" "CALA_7_0,CALA_7_1,CALA_7_2,CALA_7_3" bitfld.long 0x20 12.--13. "CALA_6,CPort #6" "CALA_6_0,CALA_6_1,CALA_6_2,CALA_6_3" newline bitfld.long 0x20 10.--11. "CALA_5,CPort #5" "CALA_5_0,CALA_5_1,CALA_5_2,CALA_5_3" bitfld.long 0x20 8.--9. "CALA_4,CPort #4" "CALA_4_0,CALA_4_1,CALA_4_2,CALA_4_3" bitfld.long 0x20 6.--7. "CALA_3,CPort #3" "CALA_3_0,CALA_3_1,CALA_3_2,CALA_3_3" newline bitfld.long 0x20 4.--5. "CALA_2,CPort #2" "CALA_2_0,CALA_2_1,CALA_2_2,CALA_2_3" bitfld.long 0x20 2.--3. "CALA_1,CPort #1" "CALA_1_0,CALA_1_1,CALA_1_2,CALA_1_3" bitfld.long 0x20 0.--1. "CALA_0,CPort #0" "CALA_0_0,CALA_0_1,CALA_0_2,CALA_0_3" line.long 0x24 "ISS_ROUTE2,This register is reserved and users should write the reset value to this register location.Controls traffic routing inside ISS" hexmask.long.word 0x24 16.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x24 14.--15. "CALB_7,CPort #7" "CALB_7_0,CALB_7_1,CALB_7_2,CALB_7_3" bitfld.long 0x24 12.--13. "CALB_6,CPort #6" "CALB_6_0,CALB_6_1,CALB_6_2,CALB_6_3" newline bitfld.long 0x24 10.--11. "CALB_5,CPort #5" "CALB_5_0,CALB_5_1,CALB_5_2,CALB_5_3" bitfld.long 0x24 8.--9. "CALB_4,CPort #4" "CALB_4_0,CALB_4_1,CALB_4_2,CALB_4_3" bitfld.long 0x24 6.--7. "CALB_3,CPort #3" "CALB_3_0,CALB_3_1,CALB_3_2,CALB_3_3" newline bitfld.long 0x24 4.--5. "CALB_2,CPort #2" "CALB_2_0,CALB_2_1,CALB_2_2,CALB_2_3" bitfld.long 0x24 2.--3. "CALB_1,CPort #1" "CALB_1_0,CALB_1_1,CALB_1_2,CALB_1_3" bitfld.long 0x24 0.--1. "CALB_0,CPort #0" "CALB_0_0,CALB_0_1,CALB_0_2,CALB_0_3" line.long 0x28 "ISS_ROUTE3,Controls traffic routing inside ISS" rbitfld.long 0x28 28.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x28 26.--27. "CCP2_WR,This bit field is reserved and users should write the reset value to this bit location" "CCP2_WR_0,CCP2_WR_1,CCP2_WR_2,CCP2_WR_3" bitfld.long 0x28 24.--25. "CCP2_RD,This bit field is reserved and users should write the reset value to this bit location" "CCP2_RD_0,CCP2_RD_1,CCP2_RD_2,CCP2_RD_3" newline bitfld.long 0x28 22.--23. "LDC,SIMCOP LDC" "LDC_0,LDC_1,LDC_2,LDC_3" bitfld.long 0x28 20.--21. "SDMA,SIMCOP - DMA" "SDMA_0,SDMA_1,SDMA_2,SDMA_3" bitfld.long 0x28 18.--19. "ICMB,This bit field is reserved and users should write the reset value to this bit location" "ICMB_0,ICMB_1,ICMB_2,ICMB_3" newline bitfld.long 0x28 16.--17. "ICMA,This bit field is reserved and users should write the reset value to this bit location" "ICMA_0,ICMA_1,ICMA_2,ICMA_3" rbitfld.long 0x28 14.--15. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3" bitfld.long 0x28 12.--13. "ISP_RSZB,ISP RSZ B" "ISP_RSZB_0,ISP_RSZB_1,ISP_RSZB_2,ISP_RSZB_3" newline bitfld.long 0x28 10.--11. "ISP_RSZA,ISP RSZ A" "ISP_RSZA_0,ISP_RSZA_1,ISP_RSZA_2,ISP_RSZA_3" bitfld.long 0x28 8.--9. "ISP_H3A,ISP H3A" "ISP_H3A_0,ISP_H3A_1,ISP_H3A_2,ISP_H3A_3" bitfld.long 0x28 6.--7. "ISP_BOXCAR,ISP_BOXCAR" "ISP_BOXCAR_0,ISP_BOXCAR_1,ISP_BOXCAR_2,ISP_BOXCAR_3" newline bitfld.long 0x28 4.--5. "ISP_RAW,ISP_RAW" "ISP_RAW_0,ISP_RAW_1,ISP_RAW_2,ISP_RAW_3" bitfld.long 0x28 2.--3. "ISP_LSC,ISP LSC" "ISP_LSC_0,ISP_LSC_1,ISP_LSC_2,ISP_LSC_3" bitfld.long 0x28 0.--1. "ISP_IPIPEIF,IPIPEIF" "ISP_IPIPEIF_0,ISP_IPIPEIF_1,ISP_IPIPEIF_2,ISP_IPIPEIF_3" line.long 0x2C "ISS_EMU_OUT,Select exported ISS level events" rbitfld.long 0x2C 26.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 24.--25. "EMU3_H," "0,1,2,3" hexmask.long.byte 0x2C 16.--23. 1. "EMU3_L," newline rbitfld.long 0x2C 10.--15. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 8.--9. "EMU2_H," "0,1,2,3" hexmask.long.byte 0x2C 0.--7. 1. "EMU2_L," line.long 0x30 "ISS_VMUX_RESET,For debug purposes only" hexmask.long.tbyte 0x30 14.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x30 13. "F304_426_F_OVR_IRQ," "F304_426_F_OVR_IRQ_0,F304_426_F_OVR_IRQ_1" bitfld.long 0x30 12. "F304_426_E_OVR_IRQ," "F304_426_E_OVR_IRQ_0,F304_426_E_OVR_IRQ_1" newline bitfld.long 0x30 11. "F304_426_D_OVR_IRQ," "F304_426_D_OVR_IRQ_0,F304_426_D_OVR_IRQ_1" bitfld.long 0x30 10. "F304_426_C_OVR_IRQ," "F304_426_C_OVR_IRQ_0,F304_426_C_OVR_IRQ_1" bitfld.long 0x30 9. "F304_426_B_OVR_IRQ," "F304_426_B_OVR_IRQ_0,F304_426_B_OVR_IRQ_1" newline bitfld.long 0x30 8. "F304_426_A_OVR_IRQ," "F304_426_A_OVR_IRQ_0,F304_426_A_OVR_IRQ_1" bitfld.long 0x30 7. "F426_304_B_OVR_IRQ," "F426_304_B_OVR_IRQ_0,F426_304_B_OVR_IRQ_1" bitfld.long 0x30 6. "F426_304_A_OVR_IRQ," "F426_304_A_OVR_IRQ_0,F426_304_A_OVR_IRQ_1" newline bitfld.long 0x30 5. "W64_32_A_OVR_IRQ," "W64_32_A_OVR_IRQ_0,W64_32_A_OVR_IRQ_1" bitfld.long 0x30 4. "W32_16_A_OVR_IRQ," "W32_16_A_OVR_IRQ_0,W32_16_A_OVR_IRQ_1" bitfld.long 0x30 3. "W64_16_B_OVR_IRQ," "W64_16_B_OVR_IRQ_0,W64_16_B_OVR_IRQ_1" newline bitfld.long 0x30 2. "W64_16_A_OVR_IRQ," "W64_16_A_OVR_IRQ_0,W64_16_A_OVR_IRQ_1" bitfld.long 0x30 1. "W16_64_B_OVR_IRQ," "W16_64_B_OVR_IRQ_0,W16_64_B_OVR_IRQ_1" bitfld.long 0x30 0. "W16_64_A_OVR_IRQ," "W16_64_A_OVR_IRQ_0,W16_64_A_OVR_IRQ_1" line.long 0x34 "ISS_VMUX_IRQSTATUS_RAW,Per-event raw interrupt status vector" hexmask.long.tbyte 0x34 14.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" rbitfld.long 0x34 13. "F304_426_F_OVR_IRQ," "0,1" rbitfld.long 0x34 12. "F304_426_E_OVR_IRQ," "0,1" newline rbitfld.long 0x34 11. "F304_426_D_OVR_IRQ," "0,1" rbitfld.long 0x34 10. "F304_426_C_OVR_IRQ," "0,1" rbitfld.long 0x34 9. "F304_426_B_OVR_IRQ," "0,1" newline rbitfld.long 0x34 8. "F304_426_A_OVR_IRQ," "0,1" rbitfld.long 0x34 7. "F426_304_B_OVR_IRQ," "0,1" rbitfld.long 0x34 6. "F426_304_A_OVR_IRQ," "0,1" newline bitfld.long 0x34 5. "W64_32_A_OVR_IRQ," "W64_32_A_OVR_IRQ_0,W64_32_A_OVR_IRQ_1" bitfld.long 0x34 4. "W32_16_A_OVR_IRQ," "W32_16_A_OVR_IRQ_0,W32_16_A_OVR_IRQ_1" bitfld.long 0x34 3. "W64_16_B_OVR_IRQ," "W64_16_B_OVR_IRQ_0,W64_16_B_OVR_IRQ_1" newline bitfld.long 0x34 2. "W64_16_A_OVR_IRQ," "W64_16_A_OVR_IRQ_0,W64_16_A_OVR_IRQ_1" bitfld.long 0x34 1. "W16_64_B_OVR_IRQ," "W16_64_B_OVR_IRQ_0,W16_64_B_OVR_IRQ_1" bitfld.long 0x34 0. "W16_64_A_OVR_IRQ," "W16_64_A_OVR_IRQ_0,W16_64_A_OVR_IRQ_1" line.long 0x38 "ISS_VMUX_IRQSTATUS,Per-event 'enabled' interrupt status vector" hexmask.long.tbyte 0x38 14.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" rbitfld.long 0x38 13. "F304_426_F_OVR_IRQ," "0,1" rbitfld.long 0x38 12. "F304_426_E_OVR_IRQ," "0,1" newline rbitfld.long 0x38 11. "F304_426_D_OVR_IRQ," "0,1" rbitfld.long 0x38 10. "F304_426_C_OVR_IRQ," "0,1" rbitfld.long 0x38 9. "F304_426_B_OVR_IRQ," "0,1" newline rbitfld.long 0x38 8. "F304_426_A_OVR_IRQ," "0,1" rbitfld.long 0x38 7. "F426_304_B_OVR_IRQ," "0,1" rbitfld.long 0x38 6. "F426_304_A_OVR_IRQ," "0,1" newline bitfld.long 0x38 5. "W64_32_A_OVR_IRQ," "W64_32_A_OVR_IRQ_0,W64_32_A_OVR_IRQ_1" bitfld.long 0x38 4. "W32_16_A_OVR_IRQ," "W32_16_A_OVR_IRQ_0,W32_16_A_OVR_IRQ_1" bitfld.long 0x38 3. "W64_16_B_OVR_IRQ," "W64_16_B_OVR_IRQ_0,W64_16_B_OVR_IRQ_1" newline bitfld.long 0x38 2. "W64_16_A_OVR_IRQ," "W64_16_A_OVR_IRQ_0,W64_16_A_OVR_IRQ_1" bitfld.long 0x38 1. "W16_64_B_OVR_IRQ," "W16_64_B_OVR_IRQ_0,W16_64_B_OVR_IRQ_1" bitfld.long 0x38 0. "W16_64_A_OVR_IRQ," "W16_64_A_OVR_IRQ_0,W16_64_A_OVR_IRQ_1" line.long 0x3C "ISS_VMUX_IRQENABLE_SET,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" hexmask.long.tbyte 0x3C 14.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" rbitfld.long 0x3C 13. "F304_426_F_OVR_IRQ," "0,1" rbitfld.long 0x3C 12. "F304_426_E_OVR_IRQ," "0,1" newline rbitfld.long 0x3C 11. "F304_426_D_OVR_IRQ," "0,1" rbitfld.long 0x3C 10. "F304_426_C_OVR_IRQ," "0,1" rbitfld.long 0x3C 9. "F304_426_B_OVR_IRQ," "0,1" newline rbitfld.long 0x3C 8. "F304_426_A_OVR_IRQ," "0,1" rbitfld.long 0x3C 7. "F426_304_B_OVR_IRQ," "0,1" rbitfld.long 0x3C 6. "F426_304_A_OVR_IRQ," "0,1" newline bitfld.long 0x3C 5. "W64_32_A_OVR_IRQ," "W64_32_A_OVR_IRQ_0,W64_32_A_OVR_IRQ_1" bitfld.long 0x3C 4. "W32_16_A_OVR_IRQ," "W32_16_A_OVR_IRQ_0,W32_16_A_OVR_IRQ_1" bitfld.long 0x3C 3. "W64_16_B_OVR_IRQ," "W64_16_B_OVR_IRQ_0,W64_16_B_OVR_IRQ_1" newline bitfld.long 0x3C 2. "W64_16_A_OVR_IRQ," "W64_16_A_OVR_IRQ_0,W64_16_A_OVR_IRQ_1" bitfld.long 0x3C 1. "W16_64_B_OVR_IRQ," "W16_64_B_OVR_IRQ_0,W16_64_B_OVR_IRQ_1" bitfld.long 0x3C 0. "W16_64_A_OVR_IRQ," "W16_64_A_OVR_IRQ_0,W16_64_A_OVR_IRQ_1" line.long 0x40 "ISS_VMUX_IRQENABLE_CLR,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" hexmask.long.tbyte 0x40 14.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" rbitfld.long 0x40 13. "F304_426_F_OVR_IRQ," "0,1" rbitfld.long 0x40 12. "F304_426_E_OVR_IRQ," "0,1" newline rbitfld.long 0x40 11. "F304_426_D_OVR_IRQ," "0,1" rbitfld.long 0x40 10. "F304_426_C_OVR_IRQ," "0,1" rbitfld.long 0x40 9. "F304_426_B_OVR_IRQ," "0,1" newline rbitfld.long 0x40 8. "F304_426_A_OVR_IRQ," "0,1" rbitfld.long 0x40 7. "F426_304_B_OVR_IRQ," "0,1" rbitfld.long 0x40 6. "F426_304_A_OVR_IRQ," "0,1" newline bitfld.long 0x40 5. "W64_32_A_OVR_IRQ," "W64_32_A_OVR_IRQ_0,W64_32_A_OVR_IRQ_1" bitfld.long 0x40 4. "W32_16_A_OVR_IRQ," "W32_16_A_OVR_IRQ_0,W32_16_A_OVR_IRQ_1" bitfld.long 0x40 3. "W64_16_B_OVR_IRQ," "W64_16_B_OVR_IRQ_0,W64_16_B_OVR_IRQ_1" newline bitfld.long 0x40 2. "W64_16_A_OVR_IRQ," "W64_16_A_OVR_IRQ_0,W64_16_A_OVR_IRQ_1" bitfld.long 0x40 1. "W16_64_B_OVR_IRQ," "W16_64_B_OVR_IRQ_0,W16_64_B_OVR_IRQ_1" bitfld.long 0x40 0. "W16_64_A_OVR_IRQ," "W16_64_A_OVR_IRQ_0,W16_64_A_OVR_IRQ_1" group.long 0x100++0x03 line.long 0x00 "ISS_ICM_A_TC_k_0,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x110++0x03 line.long 0x00 "ISS_ICM_A_TC_k_1,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x120++0x03 line.long 0x00 "ISS_ICM_A_TC_k_2,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x130++0x03 line.long 0x00 "ISS_ICM_A_TC_k_3,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x140++0x03 line.long 0x00 "ISS_ICM_A_TC_k_4,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x150++0x03 line.long 0x00 "ISS_ICM_A_TC_k_5,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x160++0x03 line.long 0x00 "ISS_ICM_A_TC_k_6,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x170++0x03 line.long 0x00 "ISS_ICM_A_TC_k_7,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x180++0x03 line.long 0x00 "ISS_ICM_A_CME_k_0,This register is reserved and users should write the reset value to this register location" hexmask.long.word 0x00 22.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 16.--21. "PRODUCER,P_START / P_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 6.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline bitfld.long 0x00 0.--5. "CONSUMER,C_START / C_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x190++0x03 line.long 0x00 "ISS_ICM_A_CME_k_1,This register is reserved and users should write the reset value to this register location" hexmask.long.word 0x00 22.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 16.--21. "PRODUCER,P_START / P_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 6.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline bitfld.long 0x00 0.--5. "CONSUMER,C_START / C_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1A0++0x03 line.long 0x00 "ISS_ICM_A_CME_k_2,This register is reserved and users should write the reset value to this register location" hexmask.long.word 0x00 22.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 16.--21. "PRODUCER,P_START / P_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 6.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline bitfld.long 0x00 0.--5. "CONSUMER,C_START / C_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1B0++0x03 line.long 0x00 "ISS_ICM_A_CME_k_3,This register is reserved and users should write the reset value to this register location" hexmask.long.word 0x00 22.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 16.--21. "PRODUCER,P_START / P_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 6.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline bitfld.long 0x00 0.--5. "CONSUMER,C_START / C_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C0++0x03 line.long 0x00 "ISS_ICM_A_CME_k_4,This register is reserved and users should write the reset value to this register location" hexmask.long.word 0x00 22.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 16.--21. "PRODUCER,P_START / P_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 6.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline bitfld.long 0x00 0.--5. "CONSUMER,C_START / C_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1D0++0x03 line.long 0x00 "ISS_ICM_A_CME_k_5,This register is reserved and users should write the reset value to this register location" hexmask.long.word 0x00 22.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 16.--21. "PRODUCER,P_START / P_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 6.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline bitfld.long 0x00 0.--5. "CONSUMER,C_START / C_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E0++0x03 line.long 0x00 "ISS_ICM_A_CME_k_6,This register is reserved and users should write the reset value to this register location" hexmask.long.word 0x00 22.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 16.--21. "PRODUCER,P_START / P_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 6.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline bitfld.long 0x00 0.--5. "CONSUMER,C_START / C_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1F0++0x03 line.long 0x00 "ISS_ICM_A_CME_k_7,This register is reserved and users should write the reset value to this register location" hexmask.long.word 0x00 22.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 16.--21. "PRODUCER,P_START / P_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 6.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline bitfld.long 0x00 0.--5. "CONSUMER,C_START / C_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "ISS_ICM_B_TC_k_0,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 8.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x210++0x03 line.long 0x00 "ISS_ICM_B_TC_k_1,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 8.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x220++0x03 line.long 0x00 "ISS_ICM_B_TC_k_2,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 8.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x230++0x03 line.long 0x00 "ISS_ICM_B_TC_k_3,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 8.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x240++0x03 line.long 0x00 "ISS_ICM_B_TC_k_4,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 8.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x250++0x03 line.long 0x00 "ISS_ICM_B_TC_k_5,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 8.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x260++0x03 line.long 0x00 "ISS_ICM_B_TC_k_6,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 8.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x270++0x03 line.long 0x00 "ISS_ICM_B_TC_k_7,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 8.--15. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" newline hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x300++0x0F line.long 0x00 "ISS_REQINFO_MAP0_7,MReqInfo remapping table" rbitfld.long 0x00 31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 28.--30. "REQINFO_7,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 24.--26. "REQINFO_6,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 20.--22. "REQINFO_5,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 16.--18. "REQINFO_4,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 15. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 12.--14. "REQINFO_3,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 11. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 8.--10. "REQINFO_2,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 4.--6. "REQINFO_1,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 0.--2. "REQINFO_0,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" line.long 0x04 "ISS_REQINFO_MAP8_15,MReqInfo remapping table" rbitfld.long 0x04 31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x04 28.--30. "REQINFO_15,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x04 24.--26. "REQINFO_14,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 23. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x04 20.--22. "REQINFO_13,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x04 16.--18. "REQINFO_12,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 15. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x04 12.--14. "REQINFO_11,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 11. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x04 8.--10. "REQINFO_10,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x04 4.--6. "REQINFO_9,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x04 0.--2. "REQINFO_8,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" line.long 0x08 "ISS_REQINFO_MAP16_23,MReqInfo remapping table" rbitfld.long 0x08 31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 28.--30. "REQINFO_23,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 27. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x08 24.--26. "REQINFO_22,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 23. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 20.--22. "REQINFO_21,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 16.--18. "REQINFO_20,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 15. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x08 12.--14. "REQINFO_19,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 11. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 8.--10. "REQINFO_18,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 4.--6. "REQINFO_17,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x08 0.--2. "REQINFO_16,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" line.long 0x0C "ISS_REQINFO_MAP24_31,MReqInfo remapping table" rbitfld.long 0x0C 31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x0C 28.--30. "REQINFO_31,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 27. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x0C 24.--26. "REQINFO_30,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 23. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x0C 20.--22. "REQINFO_29,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x0C 16.--18. "REQINFO_28,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 15. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x0C 12.--14. "REQINFO_27,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 11. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x0C 8.--10. "REQINFO_26,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x0C 4.--6. "REQINFO_25,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 3. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x0C 0.--2. "REQINFO_24,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" width 0x0B tree.end tree "IVA_CM_CORE" base ad:0x4A008F00 group.long 0x00++0x0B line.long 0x00 "CM_IVA_CLKSTCTRL,This register enables the IVA domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_IVA_GCLK,This field indicates the state of the IVA_ROOT_CLK clock input of the domain" "CLKACTIVITY_IVA_GCLK_0,CLKACTIVITY_IVA_GCLK_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the IVA clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_IVA_STATICDEP,This register controls the static domain depedencies from IVA domain towards 'target' domains" hexmask.long 0x04 6.--31. 1. "RESERVED," rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "CM_IVA_DYNAMICDEP,This register controls the dynamic domain depedencies from IVA domain towards 'target' domains" hexmask.long 0x08 6.--31. 1. "RESERVED," bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "L3MAIN1_DYNDEP_0,?" bitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20++0x03 line.long 0x00 "CM_IVA_IVA_CLKCTRL,This register manages the IVA clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x28++0x03 line.long 0x00 "CM_IVA_SL2_CLKCTRL,This register manages the SL2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "IVA_PRM" base ad:0x4AE06F00 group.long 0x00++0x07 line.long 0x00 "PM_IVA_PWRSTCTRL,This register controls the IVA power state to reach upon a domain sleep transition" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," rbitfld.long 0x00 22.--23. "TCM2_MEM_ONSTATE,TCM_CORE memory state when domain is ON" "?,?,?,TCM2_MEM_ONSTATE_3" newline rbitfld.long 0x00 20.--21. "TCM1_MEM_ONSTATE,TCM1 memory state when domain is ON" "?,?,?,TCM1_MEM_ONSTATE_3" rbitfld.long 0x00 18.--19. "SL2_MEM_ONSTATE,SL2 memory state when domain is ON" "?,?,?,SL2_MEM_ONSTATE_3" newline rbitfld.long 0x00 16.--17. "HWA_MEM_ONSTATE,HWA memory state when domain is ON" "?,?,?,HWA_MEM_ONSTATE_3" rbitfld.long 0x00 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 11. "TCM2_MEM_RETSTATE,TCM2 memory state when domain is RETENTION" "TCM2_MEM_RETSTATE_0,TCM2_MEM_RETSTATE_1" bitfld.long 0x00 10. "TCM1_MEM_RETSTATE,TCM1 memory state when domain is RETENTION" "TCM1_MEM_RETSTATE_0,TCM1_MEM_RETSTATE_1" newline bitfld.long 0x00 9. "SL2_MEM_RETSTATE,SL2 memory state when domain is RETENTION" "SL2_MEM_RETSTATE_0,SL2_MEM_RETSTATE_1" rbitfld.long 0x00 8. "HWA_MEM_RETSTATE,HWA memory state when domain is RETENTION" "HWA_MEM_RETSTATE_0,?" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" rbitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION" "LOGICRETSTATE_0,?" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_IVA_PWRSTST,This register provides a status on the current IVA power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.byte 0x04 12.--19. 1. "RESERVED," rbitfld.long 0x04 10.--11. "TCM2_MEM_STATEST,TCM2 memory state status" "TCM2_MEM_STATEST_0,TCM2_MEM_STATEST_1,TCM2_MEM_STATEST_2,TCM2_MEM_STATEST_3" newline rbitfld.long 0x04 8.--9. "TCM1_MEM_STATEST,TCM1 memory state status" "TCM1_MEM_STATEST_0,TCM1_MEM_STATEST_1,TCM1_MEM_STATEST_2,TCM1_MEM_STATEST_3" rbitfld.long 0x04 6.--7. "SL2_MEM_STATEST,SL2 memory state status" "SL2_MEM_STATEST_0,SL2_MEM_STATEST_1,SL2_MEM_STATEST_2,SL2_MEM_STATEST_3" newline rbitfld.long 0x04 4.--5. "HWA_MEM_STATEST,HWA memory state status" "HWA_MEM_STATEST_0,HWA_MEM_STATEST_1,HWA_MEM_STATEST_2,HWA_MEM_STATEST_3" rbitfld.long 0x04 3. "RESERVED," "0,1" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_IVA_RSTCTRL,This register controls the release of the IVA sub-system resets" hexmask.long 0x00 3.--31. 1. "RESERVED," bitfld.long 0x00 2. "RST_LOGIC,IVA logic and SL2 reset control" "RST_LOGIC_0,RST_LOGIC_1" newline bitfld.long 0x00 1. "RST_SEQ2,IVA Sequencer2 reset control" "RST_SEQ2_0,RST_SEQ2_1" bitfld.long 0x00 0. "RST_SEQ1,IVA sequencer1 reset control" "RST_SEQ1_0,RST_SEQ1_1" line.long 0x04 "RM_IVA_RSTST,This register logs the different reset sources of the IVA domain" hexmask.long 0x04 7.--31. 1. "RESERVED," bitfld.long 0x04 6. "RST_ICECRUSHER_SEQ2,Sequencer2 CPU has been reset due to IVA ICECRUSHER2 reset event" "RST_ICECRUSHER_SEQ2_0,RST_ICECRUSHER_SEQ2_1" newline bitfld.long 0x04 5. "RST_ICECRUSHER_SEQ1,Sequencer1 CPU has been reset due to IVA ICECRUSHER1 reset event" "RST_ICECRUSHER_SEQ1_0,RST_ICECRUSHER_SEQ1_1" bitfld.long 0x04 4. "RST_EMULATION_SEQ2,Sequencer2 CPU has been reset due to emulation reset source e.g" "RST_EMULATION_SEQ2_0,RST_EMULATION_SEQ2_1" newline bitfld.long 0x04 3. "RST_EMULATION_SEQ1,Sequencer1 CPU has been reset due to emulation reset source e.g" "RST_EMULATION_SEQ1_0,RST_EMULATION_SEQ1_1" bitfld.long 0x04 2. "RST_LOGIC,IVA logic and SL2 SW reset" "RST_LOGIC_0,RST_LOGIC_1" newline bitfld.long 0x04 1. "RST_SEQ2,IVA Sequencer2 CPU SW reset" "RST_SEQ2_0,RST_SEQ2_1" bitfld.long 0x04 0. "RST_SEQ1,IVA Sequencer1 CPU SW reset" "RST_SEQ1_0,RST_SEQ1_1" group.long 0x24++0x03 line.long 0x00 "RM_IVA_IVA_CONTEXT,This register contains dedicated IVA context statuses" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," bitfld.long 0x00 10. "LOSTMEM_HWA_MEM,Specify if memory-based context in HWA_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_HWA_MEM_0,LOSTMEM_HWA_MEM_1" newline bitfld.long 0x00 9. "LOSTMEM_TCM2_MEM,Specify if memory-based context in TCM2_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_TCM2_MEM_0,LOSTMEM_TCM2_MEM_1" bitfld.long 0x00 8. "LOSTMEM_TCM1_MEM,Specify if memory-based context in TCM1_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_TCM1_MEM_0,LOSTMEM_TCM1_MEM_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x2C++0x03 line.long 0x00 "RM_IVA_SL2_CONTEXT,This register contains dedicated SL2 context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_SL2_MEM,Specify if memory-based context in SL2_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_SL2_MEM_0,LOSTMEM_SL2_MEM_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "L3_INSTR" base ad:0x45000100 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L3_INSTR_FW" base ad:0x4A226000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "L3_INSTR_FW_CFG_TARG" base ad:0x4A227000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "L3INIT_CM_CORE" base ad:0x4A009300 group.long 0x00++0x0B line.long 0x00 "CM_L3INIT_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," newline rbitfld.long 0x00 24. "CLKACTIVITY_SATA_REF_GFCLK,This field indicates the state of the SATA_REF_GFCLK clock in the domain" "CLKACTIVITY_SATA_REF_GFCLK_0,CLKACTIVITY_SATA_REF_GFCLK_1" newline rbitfld.long 0x00 23. "CLKACTIVITY_L3INIT_32K_GFCLK,This field indicates the state of the L3INIT_32K_FCLK clock in the domain" "CLKACTIVITY_L3INIT_32K_GFCLK_0,CLKACTIVITY_L3INIT_32K_GFCLK_1" newline rbitfld.long 0x00 22. "CLKACTIVITY_L3INIT_960M_GFCLK,This field indicates the state of the L3INIT_960M_GFCLK clock in the domain" "CLKACTIVITY_L3INIT_960M_GFCLK_0,CLKACTIVITY_L3INIT_960M_GFCLK_1" newline rbitfld.long 0x00 21. "CLKACTIVITY_L3INIT_480M_GFCLK,This field indicates the state of the L3INIT_480M_GFCLK clock in the domain" "CLKACTIVITY_L3INIT_480M_GFCLK_0,CLKACTIVITY_L3INIT_480M_GFCLK_1" newline rbitfld.long 0x00 20. "CLKACTIVITY_USB_OTG_SS_REF_CLK,This field indicates the state of the USB_OTG_SS_REF_CLK clock in the domain" "CLKACTIVITY_USB_OTG_SS_REF_CLK_0,CLKACTIVITY_USB_OTG_SS_REF_CLK_1" newline rbitfld.long 0x00 19. "CLKACTIVITY_MLB_SYS_L3_GFCLK,This field indicates the state of the MLB_SYS_L3_GFCLK clock in the domain" "CLKACTIVITY_MLB_SYS_L3_GFCLK_0,CLKACTIVITY_MLB_SYS_L3_GFCLK_1" newline rbitfld.long 0x00 18. "CLKACTIVITY_MLB_SPB_L4_GICLK,This field indicates the state of the MLB_SPB_L4_GICLK clock in the domain" "CLKACTIVITY_MLB_SPB_L4_GICLK_0,CLKACTIVITY_MLB_SPB_L4_GICLK_1" newline rbitfld.long 0x00 17. "CLKACTIVITY_MLB_SHB_L3_GICLK,This field indicates the state of the MLB_SHB_L3_GICLK clock in the domain" "CLKACTIVITY_MLB_SHB_L3_GICLK_0,CLKACTIVITY_MLB_SHB_L3_GICLK_1" newline rbitfld.long 0x00 16. "CLKACTIVITY_MMC2_GFCLK,This field indicates the state of the MMC2 clock in the domain" "CLKACTIVITY_MMC2_GFCLK_0,CLKACTIVITY_MMC2_GFCLK_1" newline rbitfld.long 0x00 15. "CLKACTIVITY_MMC1_GFCLK,This field indicates the state of the MMC1_GFCLK clock in the domain" "CLKACTIVITY_MMC1_GFCLK_0,CLKACTIVITY_MMC1_GFCLK_1" newline rbitfld.long 0x00 14. "CLKACTIVITY_HSI_GFCLK,This field indicates the state of the HSI_GFCLK clock in the domain" "CLKACTIVITY_HSI_GFCLK_0,CLKACTIVITY_HSI_GFCLK_1" newline rbitfld.long 0x00 13. "CLKACTIVITY_USB_DPLL_HS_CLK,This field indicates the state of the USB_DPLL_HS_CLK clock in the domain" "CLKACTIVITY_USB_DPLL_HS_CLK_0,CLKACTIVITY_USB_DPLL_HS_CLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_USB_DPLL_CLK,This field indicates the state of the USB_DPLL_CLK clock in the domain" "CLKACTIVITY_USB_DPLL_CLK_0,CLKACTIVITY_USB_DPLL_CLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_L3INIT_48M_GFCLK,This field indicates the state of the INIT_48M_GFCLK clock in the domain" "CLKACTIVITY_L3INIT_48M_GFCLK_0,CLKACTIVITY_L3INIT_48M_GFCLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK,This field indicates the state of the L3INIT_USB_LFPS_TX_GFCLK clock in the domain" "CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK_0,CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_L3INIT_L4_GICLK,This field indicates the state of the L3INIT_L4_GICLK clock in the domain" "CLKACTIVITY_L3INIT_L4_GICLK_0,CLKACTIVITY_L3INIT_L4_GICLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_L3INIT_L3_GICLK,This field indicates the state of the L3INIT_L3_GICLK clock in the domain" "CLKACTIVITY_L3INIT_L3_GICLK_0,CLKACTIVITY_L3INIT_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L3INIT clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_L3INIT_STATICDEP,This register controls the static domain depedencies from L3INIT domain towards 'target' domains" rbitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline hexmask.long.word 0x04 16.--26. 1. "RESERVED," newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 6.--11. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" line.long 0x08 "CM_L3INIT_DYNAMICDEP,This register controls the dynamic domain depedencies from L3INIT domain towards 'target' domains" hexmask.long 0x08 6.--31. 1. "RESERVED," newline bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "L3MAIN1_DYNDEP_0,?" newline bitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x28++0x03 line.long 0x00 "CM_L3INIT_MMC1_CLKCTRL,This register manages the MMC1 clocks" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 25.--26. "CLKSEL_DIV,MMC1 clock divide ratio" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" newline bitfld.long 0x00 24. "CLKSEL_SOURCE,Selects the source of the functional clock" "CLKSEL_SOURCE_0,CLKSEL_SOURCE_1" newline rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,MMC optional clock control: 32K CLK" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x30++0x03 line.long 0x00 "CM_L3INIT_MMC2_CLKCTRL,This register manages the MMC2 clocks" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 25.--26. "CLKSEL_DIV,MMC2 clock divide ratio" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" newline bitfld.long 0x00 24. "CLKSEL_SOURCE,Selects the source of the functional clock" "CLKSEL_SOURCE_0,CLKSEL_SOURCE_1" newline rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,MMC optional clock control: 32K CLK" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_L3INIT_USB_OTG_SS2_CLKCTRL,This register manages the USB_OTG_SS2 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_REFCLK960M,USB_OTG_SS optional clock control: REFCLK960M (960MHz clock)" "OPTFCLKEN_REFCLK960M_0,OPTFCLKEN_REFCLK960M_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x48++0x03 line.long 0x00 "CM_L3INIT_USB_OTG_SS3_CLKCTRL,This register manages the USB_OTG_SS3 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x50++0x03 line.long 0x00 "CM_L3INIT_USB_OTG_SS4_CLKCTRL,This register manages the USB_OTG_SS4 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x58++0x03 line.long 0x00 "CM_L3INIT_MLB_SS_CLKCTRL,This register manages the MLBSS clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x78++0x03 line.long 0x00 "CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,This register manages the IEE1500_2_OCP clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x88++0x03 line.long 0x00 "CM_L3INIT_SATA_CLKCTRL,This register manages the SATA clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_REF_CLK,SATA optional clock control: REF_CLK (from SYS_CLK clock)" "OPTFCLKEN_REF_CLK_0,OPTFCLKEN_REF_CLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xA0++0x07 line.long 0x00 "CM_PCIE_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED," newline rbitfld.long 0x00 13. "CLKACTIVITY_PCIE_32K_GFCLK,This field indicates the state of the PCIE_32K_GFCLK clock in the domain" "CLKACTIVITY_PCIE_32K_GFCLK_0,CLKACTIVITY_PCIE_32K_GFCLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_PCIE_SYS_GFCLK,This field indicates the state of the PCIE_SYS_GFCLK clock in the domain" "CLKACTIVITY_PCIE_SYS_GFCLK_0,CLKACTIVITY_PCIE_SYS_GFCLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_PCIE_REF_GFCLK,This field indicates the state of the PCIE_REF_GFCLK clock in the domain" "CLKACTIVITY_PCIE_REF_GFCLK_0,CLKACTIVITY_PCIE_REF_GFCLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_PCIE_PHY_DIV_GCLK,This field indicates the state of the PCIE_PHY_DIV_GCLK clock in the domain" "CLKACTIVITY_PCIE_PHY_DIV_GCLK_0,CLKACTIVITY_PCIE_PHY_DIV_GCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_PCIE_PHY_GCLK,This field indicates the state of the PCIE_PHY_GCLK clock in the domain" "CLKACTIVITY_PCIE_PHY_GCLK_0,CLKACTIVITY_PCIE_PHY_GCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_PCIE_L3_GICLK,This field indicates the state of the PCIE_L3_GICLK clock in the domain" "CLKACTIVITY_PCIE_L3_GICLK_0,CLKACTIVITY_PCIE_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L3INIT clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_PCIE_STATICDEP,This register controls the static domain depedencies from PCIE domain towards 'target' domains" rbitfld.long 0x04 31. "RESERVED," "0,1" newline bitfld.long 0x04 30. "CRC_STATDEP,Static dependency towards CRC clock domain" "CRC_STATDEP_0,CRC_STATDEP_1" newline rbitfld.long 0x04 29. "RESERVED," "0,1" newline bitfld.long 0x04 28. "ISS_STATDEP,Static dependency towards ISS clock domain" "ISS_STATDEP_0,ISS_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain" "GMAC_STATDEP_0,GMAC_STATDEP_1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" newline bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain" "EVE1_STATDEP_0,EVE1_STATDEP_1" newline bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain" "CUSTEFUSE_STATDEP_0,?" newline rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain" "COREAON_STATDEP_0,?" newline rbitfld.long 0x04 15. "RESERVED," "0,1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 11. "SDMA_STATDEP,Static dependency towards SDMA clock domain" "SDMA_STATDEP_0,?" newline bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU clock domain" "GPU_STATDEP_0,GPU_STATDEP_1" newline bitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain" "CAM_STATDEP_0,CAM_STATDEP_1" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline rbitfld.long 0x04 5.--6. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP1 clock domain" "DSP1_STATDEP_0,DSP1_STATDEP_1" newline rbitfld.long 0x04 0. "RESERVED," "0,1" group.long 0xB0++0x03 line.long 0x00 "CM_PCIE_PCIESS1_CLKCTRL,This register manages the PCESS1 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10. "OPTFCLKEN_PCIEPHY_CLK_DIV,PCIE PHY optional clock control" "OPTFCLKEN_PCIEPHY_CLK_DIV_0,OPTFCLKEN_PCIEPHY_CLK_DIV_1" newline bitfld.long 0x00 9. "OPTFCLKEN_PCIEPHY_CLK,PCIE PHY optional clock control" "OPTFCLKEN_PCIEPHY_CLK_0,OPTFCLKEN_PCIEPHY_CLK_1" newline bitfld.long 0x00 8. "OPTFCLKEN_32KHZ,PCIE PHY optional clock control" "OPTFCLKEN_32KHZ_0,OPTFCLKEN_32KHZ_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xB8++0x03 line.long 0x00 "CM_PCIE_PCIESS2_CLKCTRL,This register manages the PCESS2 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10. "OPTFCLKEN_PCIEPHY_CLK_DIV,PCIE PHY optional clock control" "OPTFCLKEN_PCIEPHY_CLK_DIV_0,OPTFCLKEN_PCIEPHY_CLK_DIV_1" newline bitfld.long 0x00 9. "OPTFCLKEN_PCIEPHY_CLK,PCIE PHY optional clock control" "OPTFCLKEN_PCIEPHY_CLK_0,OPTFCLKEN_PCIEPHY_CLK_1" newline bitfld.long 0x00 8. "OPTFCLKEN_32KHZ,PCIE PHY optional clock control" "OPTFCLKEN_32KHZ_0,OPTFCLKEN_32KHZ_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xC0++0x0B line.long 0x00 "CM_GMAC_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED," newline rbitfld.long 0x00 12. "CLKACTIVITY_GMAC_MAIN_CLK,This field indicates the state of the GMAC_MAIN_CLK clock in the domain" "CLKACTIVITY_GMAC_MAIN_CLK_0,CLKACTIVITY_GMAC_MAIN_CLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_GMAC_RFT_CLK,This field indicates the state of the GMAC_RFT_CLK clock in the domain" "CLKACTIVITY_GMAC_RFT_CLK_0,CLKACTIVITY_GMAC_RFT_CLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_RMII_50MHZ_CLK,This field indicates the state of the RMII_50MHZ_CLK clock in the domain" "CLKACTIVITY_RMII_50MHZ_CLK_0,CLKACTIVITY_RMII_50MHZ_CLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_RGMII_5MHZ_CLK,This field indicates the state of the RGMII_5MHZ_CLK clock in the domain" "CLKACTIVITY_RGMII_5MHZ_CLK_0,CLKACTIVITY_RGMII_5MHZ_CLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_GMII_250MHZ_CLK,This field indicates the state of the GMII_250MHZ_CLK clock in the domain" "CLKACTIVITY_GMII_250MHZ_CLK_0,CLKACTIVITY_GMII_250MHZ_CLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,This bit field must not be programmed for SW_SLEEP or HW_AUTO when in EEE mode" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_GMAC_STATICDEP,This register controls the static domain depedencies from GMAC domain towards 'target' domains" rbitfld.long 0x04 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline hexmask.long.tbyte 0x04 6.--25. 1. "RESERVED," newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "CM_GMAC_DYNAMICDEP,This register controls the dynamic domain depedencies from GMAC domain towards 'target' domains" hexmask.long 0x08 6.--31. 1. "RESERVED," newline bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "L3MAIN1_DYNDEP_0,?" newline bitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xD0++0x03 line.long 0x00 "CM_GMAC_GMAC_CLKCTRL,This register manages the GMAC clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 25.--27. "CLKSEL_RFT,Selects the source of the GMAC_RFT_CLK" "CLKSEL_RFT_0,CLKSEL_RFT_1,CLKSEL_RFT_2,CLKSEL_RFT_3,CLKSEL_RFT_4,CLKSEL_RFT_5,CLKSEL_RFT_6,CLKSEL_RFT_7" newline bitfld.long 0x00 24. "CLKSEL_REF,Selects the source of the RMII_50MHZ_CLK functional clock" "CLKSEL_REF_0,CLKSEL_REF_1" newline rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xE0++0x03 line.long 0x00 "CM_L3INIT_OCP2SCP1_CLKCTRL,This register manages the OCP2SCP1 clocks and the optional clock of USB PHY" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xE8++0x03 line.long 0x00 "CM_L3INIT_OCP2SCP3_CLKCTRL,This register manages the OCP2SCP3 clocks and the optional clock of USB PHY" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xF0++0x03 line.long 0x00 "CM_L3INIT_USB_OTG_SS1_CLKCTRL,This register manages the USB_OTG_SS1 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_REFCLK960M,USB_OTG_SS optional clock control: REFCLK960M (960MHz clock)" "OPTFCLKEN_REFCLK960M_0,OPTFCLKEN_REFCLK960M_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "L3INIT_PRM" base ad:0x4AE07300 group.long 0x00++0x07 line.long 0x00 "PM_L3INIT_PWRSTCTRL,This register controls the L3INIT power state to reach upon a domain sleep transition" hexmask.long.word 0x00 20.--31. 1. "RESERVED," rbitfld.long 0x00 18.--19. "GMAC_BANK_ONSTATE,GMAC BANK state when domain is ON" "?,?,?,GMAC_BANK_ONSTATE_3" newline rbitfld.long 0x00 16.--17. "L3INIT_BANK2_ONSTATE,L3INIT BANK2 state when domain is ON" "?,?,?,L3INIT_BANK2_ONSTATE_3" rbitfld.long 0x00 14.--15. "L3INIT_BANK1_ONSTATE,L3INIT BANK1 state when domain is ON" "?,?,?,L3INIT_BANK1_ONSTATE_3" newline rbitfld.long 0x00 11.--13. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x00 10. "GMAC_BANK_RETSTATE,GMAC BANK state when domain is RETENTION" "?,GMAC_BANK_RETSTATE_1" newline rbitfld.long 0x00 9. "L3INIT_BANK2_RETSTATE,L3INIT BANK2 state when domain is RETENTION" "?,L3INIT_BANK2_RETSTATE_1" rbitfld.long 0x00 8. "L3INIT_BANK1_RETSTATE,L3INIT BANK1 state when domain is RETENTION" "L3INIT_BANK1_RETSTATE_0,?" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION" "LOGICRETSTATE_0,LOGICRETSTATE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_L3INIT_PWRSTST,This register provides a status on the current L3INIT power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 10.--19. 1. "RESERVED," rbitfld.long 0x04 8.--9. "L3INIT_GMAC_STATEST,L3INIT GMAC state status" "L3INIT_GMAC_STATEST_0,L3INIT_GMAC_STATEST_1,L3INIT_GMAC_STATEST_2,L3INIT_GMAC_STATEST_3" newline rbitfld.long 0x04 6.--7. "L3INIT_BANK2_STATEST,L3INIT BANK2 state status" "L3INIT_BANK2_STATEST_0,L3INIT_BANK2_STATEST_1,L3INIT_BANK2_STATEST_2,L3INIT_BANK2_STATEST_3" rbitfld.long 0x04 4.--5. "L3INIT_BANK1_STATEST,L3INIT BANK1 state status" "L3INIT_BANK1_STATEST_0,L3INIT_BANK1_STATEST_1,L3INIT_BANK1_STATEST_2,L3INIT_BANK1_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_PCIESS_RSTCTRL,This register controls the release of the PCIESS local reset" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "RST_LOCAL_PCIE2,PCIESS2 local reset control" "RST_LOCAL_PCIE2_0,RST_LOCAL_PCIE2_1" newline bitfld.long 0x00 0. "RST_LOCAL_PCIE1,PCIESS1 local reset control" "RST_LOCAL_PCIE1_0,RST_LOCAL_PCIE1_1" line.long 0x04 "RM_PCIESS_RSTST,This register logs the different reset sources of the PCIESS domain" hexmask.long 0x04 2.--31. 1. "RESERVED," bitfld.long 0x04 1. "RST_LOCAL_PCIE2,PCIESS2 local SW reset" "RST_LOCAL_PCIE2_0,RST_LOCAL_PCIE2_1" newline bitfld.long 0x04 0. "RST_LOCAL_PCIE1,PCIESS1 local SW reset" "RST_LOCAL_PCIE1_0,RST_LOCAL_PCIE1_1" group.long 0x28++0x0F line.long 0x00 "PM_L3INIT_MMC1_WKDEP,This register controls wakeup dependency based on MMC1 service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_MMC1_EVE4,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_EVE4_0,WKUPDEP_MMC1_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_MMC1_EVE3,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_EVE3_0,WKUPDEP_MMC1_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_MMC1_EVE2,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_EVE2_0,WKUPDEP_MMC1_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_MMC1_EVE1,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_EVE1_0,WKUPDEP_MMC1_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_MMC1_DSP2,Wakeup dependency from MMC1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_DSP2_0,WKUPDEP_MMC1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_MMC1_IPU1,Wakeup dependency from MMC1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_IPU1_0,WKUPDEP_MMC1_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_MMC1_SDMA,Wakeup dependency from MMC1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_SDMA_0,WKUPDEP_MMC1_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_MMC1_DSP1,Wakeup dependency from MMC1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_DSP1_0,WKUPDEP_MMC1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_MMC1_IPU2,Wakeup dependency from MMC1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_IPU2_0,WKUPDEP_MMC1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_MMC1_MPU,Wakeup dependency from MMC1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_MPU_0,WKUPDEP_MMC1_MPU_1" line.long 0x04 "RM_L3INIT_MMC1_CONTEXT,This register contains dedicated MMC1 context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline rbitfld.long 0x04 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x04 0. "RESERVED," "0,1" line.long 0x08 "PM_L3INIT_MMC2_WKDEP,This register controls wakeup dependency based on MMC2 service requests" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "WKUPDEP_MMC2_EVE4,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_EVE4_0,WKUPDEP_MMC2_EVE4_1" newline bitfld.long 0x08 8. "WKUPDEP_MMC2_EVE3,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_EVE3_0,WKUPDEP_MMC2_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_MMC2_EVE2,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_EVE2_0,WKUPDEP_MMC2_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_MMC2_EVE1,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_EVE1_0,WKUPDEP_MMC2_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_MMC2_DSP2,Wakeup dependency from MMC2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_DSP2_0,WKUPDEP_MMC2_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_MMC2_IPU1,Wakeup dependency from MMC2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_IPU1_0,WKUPDEP_MMC2_IPU1_1" bitfld.long 0x08 3. "WKUPDEP_MMC2_SDMA,Wakeup dependency from MMC2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_SDMA_0,WKUPDEP_MMC2_SDMA_1" newline bitfld.long 0x08 2. "WKUPDEP_MMC2_DSP1,Wakeup dependency from MMC2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_DSP1_0,WKUPDEP_MMC2_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_MMC2_IPU2,Wakeup dependency from MMC2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_IPU2_0,WKUPDEP_MMC2_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_MMC2_MPU,Wakeup dependency from MMC2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_MPU_0,WKUPDEP_MMC2_MPU_1" line.long 0x0C "RM_L3INIT_MMC2_CONTEXT,This register contains dedicated MMC2 context statuses" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED," bitfld.long 0x0C 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline rbitfld.long 0x0C 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x0C 0. "RESERVED," "0,1" group.long 0x40++0x17 line.long 0x00 "PM_L3INIT_USB_OTG_SS2_WKDEP,This register controls wakeup dependency based on USB_OTG_SS2 service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_USB_OTG_SS2_EVE4,Wakeup dependency from USB2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_EVE4_0,WKUPDEP_USB_OTG_SS2_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_USB_OTG_SS2_EVE3,Wakeup dependency from USB2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_EVE3_0,WKUPDEP_USB_OTG_SS2_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_USB_OTG_SS2_EVE2,Wakeup dependency from USB2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_EVE2_0,WKUPDEP_USB_OTG_SS2_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_USB_OTG_SS2_EVE1,Wakeup dependency from USB2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_EVE1_0,WKUPDEP_USB_OTG_SS2_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_USB_OTG_SS2_DSP2,Wakeup dependency from USB2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_DSP2_0,WKUPDEP_USB_OTG_SS2_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_USB_OTG_SS2_IPU1,Wakeup dependency from USB2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_IPU1_0,WKUPDEP_USB_OTG_SS2_IPU1_1" rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_USB_OTG_SS2_DSP1,Wakeup dependency from USB2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_DSP1_0,WKUPDEP_USB_OTG_SS2_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_USB_OTG_SS2_IPU2,Wakeup dependency from USB2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_IPU2_0,WKUPDEP_USB_OTG_SS2_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_USB_OTG_SS2_MPU,Wakeup dependency from USB2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_MPU_0,WKUPDEP_USB_OTG_SS2_MPU_1" line.long 0x04 "RM_L3INIT_USB_OTG_SS2_CONTEXT,This register contains dedicated USB_OTG_SS2 context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline rbitfld.long 0x04 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x04 0. "RESERVED," "0,1" line.long 0x08 "PM_L3INIT_USB_OTG_SS3_WKDEP,This register controls wakeup dependency based on USB_OTG_SS3 service requests" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "WKUPDEP_USB_OTG_SS3_EVE4,Wakeup dependency from USB3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_EVE4_0,WKUPDEP_USB_OTG_SS3_EVE4_1" newline bitfld.long 0x08 8. "WKUPDEP_USB_OTG_SS3_EVE3,Wakeup dependency from USB3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_EVE3_0,WKUPDEP_USB_OTG_SS3_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_USB_OTG_SS3_EVE2,Wakeup dependency from USB3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_EVE2_0,WKUPDEP_USB_OTG_SS3_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_USB_OTG_SS3_EVE1,Wakeup dependency from USB3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_EVE1_0,WKUPDEP_USB_OTG_SS3_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_USB_OTG_SS3_DSP2,Wakeup dependency from USB3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_DSP2_0,WKUPDEP_USB_OTG_SS3_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_USB_OTG_SS3_IPU1,Wakeup dependency from USB3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_IPU1_0,WKUPDEP_USB_OTG_SS3_IPU1_1" rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 2. "WKUPDEP_USB_OTG_SS3_DSP1,Wakeup dependency from USB3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_DSP1_0,WKUPDEP_USB_OTG_SS3_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_USB_OTG_SS3_IPU2,Wakeup dependency from USB3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_IPU2_0,WKUPDEP_USB_OTG_SS3_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_USB_OTG_SS3_MPU,Wakeup dependency from USB3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_MPU_0,WKUPDEP_USB_OTG_SS3_MPU_1" line.long 0x0C "RM_L3INIT_USB_OTG_SS3_CONTEXT,This register contains dedicated USB_OTG_SS3 context statuses" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED," bitfld.long 0x0C 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline rbitfld.long 0x0C 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x0C 0. "RESERVED," "0,1" line.long 0x10 "PM_L3INIT_USB_OTG_SS4_WKDEP,This register controls wakeup dependency based on USB_OTG_SS4 service requests" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED," bitfld.long 0x10 9. "WKUPDEP_USB_OTG_SS4_EVE4,Wakeup dependency from USB4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_EVE4_0,WKUPDEP_USB_OTG_SS4_EVE4_1" newline bitfld.long 0x10 8. "WKUPDEP_USB_OTG_SS4_EVE3,Wakeup dependency from USB4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_EVE3_0,WKUPDEP_USB_OTG_SS4_EVE3_1" bitfld.long 0x10 7. "WKUPDEP_USB_OTG_SS4_EVE2,Wakeup dependency from USB4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_EVE2_0,WKUPDEP_USB_OTG_SS4_EVE2_1" newline bitfld.long 0x10 6. "WKUPDEP_USB_OTG_SS4_EVE1,Wakeup dependency from USB4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_EVE1_0,WKUPDEP_USB_OTG_SS4_EVE1_1" bitfld.long 0x10 5. "WKUPDEP_USB_OTG_SS4_DSP2,Wakeup dependency from USB4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_DSP2_0,WKUPDEP_USB_OTG_SS4_DSP2_1" newline bitfld.long 0x10 4. "WKUPDEP_USB_OTG_SS4_IPU1,Wakeup dependency from USB4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_IPU1_0,WKUPDEP_USB_OTG_SS4_IPU1_1" rbitfld.long 0x10 3. "RESERVED," "0,1" newline bitfld.long 0x10 2. "WKUPDEP_USB_OTG_SS4_DSP1,Wakeup dependency from USB4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_DSP1_0,WKUPDEP_USB_OTG_SS4_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_USB_OTG_SS4_IPU2,Wakeup dependency from USB4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_IPU2_0,WKUPDEP_USB_OTG_SS4_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_USB_OTG_SS4_MPU,Wakeup dependency from USB4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_MPU_0,WKUPDEP_USB_OTG_SS4_MPU_1" line.long 0x14 "RM_L3INIT_USB_OTG_SS4_CONTEXT,This register contains dedicated USB_OTG_SS4 context statuses" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED," bitfld.long 0x14 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline rbitfld.long 0x14 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x14 0. "RESERVED," "0,1" group.long 0x5C++0x03 line.long 0x00 "RM_L3INIT_MLB_SS_CONTEXT,This register contains dedicated MLBSS context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_MLB_BANK,Specify if memory-based context in MLB_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_MLB_BANK_0,LOSTMEM_MLB_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x7C++0x03 line.long 0x00 "RM_L3INIT_IEEE1500_2_OCP_CONTEXT,This register contains dedicated IEEE1500_2_OCP context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x88++0x07 line.long 0x00 "PM_L3INIT_SATA_WKDEP,This register controls wakeup dependency based on SATA service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_SATA_EVE4,Wakeup dependency from SATA module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SATA_EVE4_0,WKUPDEP_SATA_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_SATA_EVE3,Wakeup dependency from SATA module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SATA_EVE3_0,WKUPDEP_SATA_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_SATA_EVE2,Wakeup dependency from SATA module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SATA_EVE2_0,WKUPDEP_SATA_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SATA_EVE1,Wakeup dependency from SATA module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SATA_EVE1_0,WKUPDEP_SATA_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_SATA_DSP2,Wakeup dependency from SATA module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SATA_DSP2_0,WKUPDEP_SATA_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SATA_IPU1,Wakeup dependency from SATA module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SATA_IPU1_0,WKUPDEP_SATA_IPU1_1" rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_SATA_DSP1,Wakeup dependency from SATA module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SATA_DSP1_0,WKUPDEP_SATA_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_SATA_IPU2,Wakeup dependency from SATA module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SATA_IPU2_0,WKUPDEP_SATA_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SATA_MPU,Wakeup dependency from SATA module (SWakeup signal) towards MPU + L3MAIN1 + L4CFG domains" "WKUPDEP_SATA_MPU_0,WKUPDEP_SATA_MPU_1" line.long 0x04 "RM_L3INIT_SATA_CONTEXT,This register contains dedicated SATA context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xB0++0x0F line.long 0x00 "PM_PCIE_PCIESS1_WKDEP,This register controls wakeup dependency based on PCIESS1 service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_PCIESS1_EVE4,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_EVE4_0,WKUPDEP_PCIESS1_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_PCIESS1_EVE3,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_EVE3_0,WKUPDEP_PCIESS1_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_PCIESS1_EVE2,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_EVE2_0,WKUPDEP_PCIESS1_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_PCIESS1_EVE1,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_EVE1_0,WKUPDEP_PCIESS1_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_PCIESS1_DSP2,Wakeup dependency from PCIESS1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_DSP2_0,WKUPDEP_PCIESS1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_PCIESS1_IPU1,Wakeup dependency from PCIESS1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_IPU1_0,WKUPDEP_PCIESS1_IPU1_1" rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_PCIESS1_DSP1,Wakeup dependency from PCIESS1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_DSP1_0,WKUPDEP_PCIESS1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_PCIESS1_IPU2,Wakeup dependency from PCIESS1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_IPU2_0,WKUPDEP_PCIESS1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_PCIESS1_MPU,Wakeup dependency from PCIESS1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_MPU_0,WKUPDEP_PCIESS1_MPU_1" line.long 0x04 "RM_PCIE_PCIESS1_CONTEXT,This register contains dedicated PCIESS1 context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in PCIESS1_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_PCIE_PCIESS2_WKDEP,This register controls wakeup dependency based on PCIESS2 service requests" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "WKUPDEP_PCIESS2_EVE4,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_EVE4_0,WKUPDEP_PCIESS2_EVE4_1" newline bitfld.long 0x08 8. "WKUPDEP_PCIESS2_EVE3,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_EVE3_0,WKUPDEP_PCIESS2_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_PCIESS2_EVE2,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_EVE2_0,WKUPDEP_PCIESS2_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_PCIESS2_EVE1,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_EVE1_0,WKUPDEP_PCIESS2_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_PCIESS2_DSP2,Wakeup dependency from PCIESS2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_DSP2_0,WKUPDEP_PCIESS2_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_PCIESS2_IPU1,Wakeup dependency from PCIESS2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_IPU1_0,WKUPDEP_PCIESS2_IPU1_1" rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 2. "WKUPDEP_PCIESS2_DSP1,Wakeup dependency from PCIESS2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_DSP1_0,WKUPDEP_PCIESS2_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_PCIESS2_IPU2,Wakeup dependency from PCIESS2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_IPU2_0,WKUPDEP_PCIESS2_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_PCIESS2_MPU,Wakeup dependency from PCIESS2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_MPU_0,WKUPDEP_PCIESS2_MPU_1" line.long 0x0C "RM_PCIE_PCIESS2_CONTEXT,This register contains dedicated PCIESS2 context statuses" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED," bitfld.long 0x0C 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in PCIESS1_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline hexmask.long.byte 0x0C 1.--7. 1. "RESERVED," bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xD4++0x03 line.long 0x00 "RM_GMAC_GMAC_CONTEXT,This register contains dedicated GMAC context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_GMAC_BANK,Specify if memory-based context in GMAC_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_GMAC_BANK_0,LOSTMEM_GMAC_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xE4++0x03 line.long 0x00 "RM_L3INIT_OCP2SCP1_CONTEXT,This register contains dedicated OCP2SCP1 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xEC++0x0B line.long 0x00 "RM_L3INIT_OCP2SCP3_CONTEXT,This register contains dedicated OCP2SCP3 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_L3INIT_USB_OTG_SS1_WKDEP,This register controls wakeup dependency based on USB_OTG_SS1 service requests" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "WKUPDEP_USB_OTG_SS1_EVE4,Wakeup dependency from USB1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_EVE4_0,WKUPDEP_USB_OTG_SS1_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_USB_OTG_SS1_EVE3,Wakeup dependency from USB1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_EVE3_0,WKUPDEP_USB_OTG_SS1_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_USB_OTG_SS1_EVE2,Wakeup dependency from USB1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_EVE2_0,WKUPDEP_USB_OTG_SS1_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_USB_OTG_SS1_EVE1,Wakeup dependency from USB1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_EVE1_0,WKUPDEP_USB_OTG_SS1_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_USB_OTG_SS1_DSP2,Wakeup dependency from USB1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_DSP2_0,WKUPDEP_USB_OTG_SS1_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_USB_OTG_SS1_IPU1,Wakeup dependency from USB1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_IPU1_0,WKUPDEP_USB_OTG_SS1_IPU1_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "WKUPDEP_USB_OTG_SS1_DSP1,Wakeup dependency from USB1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_DSP1_0,WKUPDEP_USB_OTG_SS1_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_USB_OTG_SS1_IPU2,Wakeup dependency from USB1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_IPU2_0,WKUPDEP_USB_OTG_SS1_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_USB_OTG_SS1_MPU,Wakeup dependency from USB1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_MPU_0,WKUPDEP_USB_OTG_SS1_MPU_1" line.long 0x08 "RM_L3INIT_USB_OTG_SS1_CONTEXT,This register contains dedicated USB_OTG_SS1 context statuses" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," bitfld.long 0x08 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline rbitfld.long 0x08 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x08 0. "RESERVED," "0,1" width 0x0B tree.end tree "L4_CFG_AP" base ad:0x4A000000 rgroup.long 0x00++0x07 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x100++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_0,Defines the base address of each segment" rgroup.long 0x108++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_1,Defines the base address of each segment" rgroup.long 0x110++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_2,Defines the base address of each segment" rgroup.long 0x104++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_0,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x10C++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_1,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x114++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_2,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x208++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x210++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x218++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x220++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x228++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x230++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x238++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x280++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x288++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x290++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x298++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Reserved" rgroup.long 0x28C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Reserved" rgroup.long 0x294++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Reserved" rgroup.long 0x29C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Reserved" rgroup.long 0x2A4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Reserved" rgroup.long 0x2AC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Reserved" rgroup.long 0x2B4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Reserved" rgroup.long 0x2BC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Reserved" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x308++0x03 line.long 0x00 "L4_AP_REGION_l_L_1,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x310++0x03 line.long 0x00 "L4_AP_REGION_l_L_2,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x318++0x03 line.long 0x00 "L4_AP_REGION_l_L_3,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x320++0x03 line.long 0x00 "L4_AP_REGION_l_L_4,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x328++0x03 line.long 0x00 "L4_AP_REGION_l_L_5,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x330++0x03 line.long 0x00 "L4_AP_REGION_l_L_6,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x338++0x03 line.long 0x00 "L4_AP_REGION_l_L_7,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x340++0x03 line.long 0x00 "L4_AP_REGION_l_L_8,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x348++0x03 line.long 0x00 "L4_AP_REGION_l_L_9,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x358++0x03 line.long 0x00 "L4_AP_REGION_l_L_11,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x360++0x03 line.long 0x00 "L4_AP_REGION_l_L_12,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x368++0x03 line.long 0x00 "L4_AP_REGION_l_L_13,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x370++0x03 line.long 0x00 "L4_AP_REGION_l_L_14,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x378++0x03 line.long 0x00 "L4_AP_REGION_l_L_15,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x380++0x03 line.long 0x00 "L4_AP_REGION_l_L_16,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x388++0x03 line.long 0x00 "L4_AP_REGION_l_L_17,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x390++0x03 line.long 0x00 "L4_AP_REGION_l_L_18,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x398++0x03 line.long 0x00 "L4_AP_REGION_l_L_19,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_20,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_21,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_22,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_23,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_25,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_26,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_27,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_28,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_29,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_30,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_31,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x400++0x03 line.long 0x00 "L4_AP_REGION_l_L_32,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x408++0x03 line.long 0x00 "L4_AP_REGION_l_L_33,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x410++0x03 line.long 0x00 "L4_AP_REGION_l_L_34,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x418++0x03 line.long 0x00 "L4_AP_REGION_l_L_35,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x420++0x03 line.long 0x00 "L4_AP_REGION_l_L_36,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x428++0x03 line.long 0x00 "L4_AP_REGION_l_L_37,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x430++0x03 line.long 0x00 "L4_AP_REGION_l_L_38,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x438++0x03 line.long 0x00 "L4_AP_REGION_l_L_39,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x448++0x03 line.long 0x00 "L4_AP_REGION_l_L_41,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x450++0x03 line.long 0x00 "L4_AP_REGION_l_L_42,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x458++0x03 line.long 0x00 "L4_AP_REGION_l_L_43,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x460++0x03 line.long 0x00 "L4_AP_REGION_l_L_44,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x468++0x03 line.long 0x00 "L4_AP_REGION_l_L_45,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x470++0x03 line.long 0x00 "L4_AP_REGION_l_L_46,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x478++0x03 line.long 0x00 "L4_AP_REGION_l_L_47,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x480++0x03 line.long 0x00 "L4_AP_REGION_l_L_48,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x488++0x03 line.long 0x00 "L4_AP_REGION_l_L_49,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x490++0x03 line.long 0x00 "L4_AP_REGION_l_L_50,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x498++0x03 line.long 0x00 "L4_AP_REGION_l_L_51,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_52,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_53,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_54,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_55,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_56,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_57,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_58,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_59,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_60,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_61,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_62,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_63,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x500++0x03 line.long 0x00 "L4_AP_REGION_l_L_64,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x508++0x03 line.long 0x00 "L4_AP_REGION_l_L_65,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x510++0x03 line.long 0x00 "L4_AP_REGION_l_L_66,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x518++0x03 line.long 0x00 "L4_AP_REGION_l_L_67,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x520++0x03 line.long 0x00 "L4_AP_REGION_l_L_68,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x528++0x03 line.long 0x00 "L4_AP_REGION_l_L_69,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x530++0x03 line.long 0x00 "L4_AP_REGION_l_L_70,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x538++0x03 line.long 0x00 "L4_AP_REGION_l_L_71,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x540++0x03 line.long 0x00 "L4_AP_REGION_l_L_72,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x548++0x03 line.long 0x00 "L4_AP_REGION_l_L_73,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x550++0x03 line.long 0x00 "L4_AP_REGION_l_L_74,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x558++0x03 line.long 0x00 "L4_AP_REGION_l_L_75,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x560++0x03 line.long 0x00 "L4_AP_REGION_l_L_76,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x568++0x03 line.long 0x00 "L4_AP_REGION_l_L_77,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x570++0x03 line.long 0x00 "L4_AP_REGION_l_L_78,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x578++0x03 line.long 0x00 "L4_AP_REGION_l_L_79,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x580++0x03 line.long 0x00 "L4_AP_REGION_l_L_80,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x588++0x03 line.long 0x00 "L4_AP_REGION_l_L_81,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x590++0x03 line.long 0x00 "L4_AP_REGION_l_L_82,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x598++0x03 line.long 0x00 "L4_AP_REGION_l_L_83,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_84,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_85,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_86,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_87,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_88,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_89,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_90,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_91,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_92,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_93,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_94,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_95,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x600++0x03 line.long 0x00 "L4_AP_REGION_l_L_96,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x608++0x03 line.long 0x00 "L4_AP_REGION_l_L_97,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x610++0x03 line.long 0x00 "L4_AP_REGION_l_L_98,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x618++0x03 line.long 0x00 "L4_AP_REGION_l_L_99,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x620++0x03 line.long 0x00 "L4_AP_REGION_l_L_100,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x628++0x03 line.long 0x00 "L4_AP_REGION_l_L_101,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x630++0x03 line.long 0x00 "L4_AP_REGION_l_L_102,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x638++0x03 line.long 0x00 "L4_AP_REGION_l_L_103,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x640++0x03 line.long 0x00 "L4_AP_REGION_l_L_104,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x648++0x03 line.long 0x00 "L4_AP_REGION_l_L_105,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x650++0x03 line.long 0x00 "L4_AP_REGION_l_L_106,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x658++0x03 line.long 0x00 "L4_AP_REGION_l_L_107,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x660++0x03 line.long 0x00 "L4_AP_REGION_l_L_108,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x668++0x03 line.long 0x00 "L4_AP_REGION_l_L_109,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x670++0x03 line.long 0x00 "L4_AP_REGION_l_L_110,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x30C++0x03 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x314++0x03 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x31C++0x03 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x324++0x03 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x32C++0x03 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x334++0x03 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x33C++0x03 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x344++0x03 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x34C++0x03 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x35C++0x03 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x364++0x03 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x36C++0x03 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x374++0x03 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x37C++0x03 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x384++0x03 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x38C++0x03 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x394++0x03 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x39C++0x03 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x404++0x03 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x40C++0x03 line.long 0x00 "L4_AP_REGION_l_H_33,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x414++0x03 line.long 0x00 "L4_AP_REGION_l_H_34,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x41C++0x03 line.long 0x00 "L4_AP_REGION_l_H_35,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x424++0x03 line.long 0x00 "L4_AP_REGION_l_H_36,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x42C++0x03 line.long 0x00 "L4_AP_REGION_l_H_37,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x434++0x03 line.long 0x00 "L4_AP_REGION_l_H_38,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x43C++0x03 line.long 0x00 "L4_AP_REGION_l_H_39,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x44C++0x03 line.long 0x00 "L4_AP_REGION_l_H_41,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x454++0x03 line.long 0x00 "L4_AP_REGION_l_H_42,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x45C++0x03 line.long 0x00 "L4_AP_REGION_l_H_43,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x464++0x03 line.long 0x00 "L4_AP_REGION_l_H_44,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x46C++0x03 line.long 0x00 "L4_AP_REGION_l_H_45,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x474++0x03 line.long 0x00 "L4_AP_REGION_l_H_46,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x47C++0x03 line.long 0x00 "L4_AP_REGION_l_H_47,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x484++0x03 line.long 0x00 "L4_AP_REGION_l_H_48,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x48C++0x03 line.long 0x00 "L4_AP_REGION_l_H_49,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x494++0x03 line.long 0x00 "L4_AP_REGION_l_H_50,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x49C++0x03 line.long 0x00 "L4_AP_REGION_l_H_51,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_52,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_53,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_54,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_55,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_56,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_57,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_58,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_59,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_60,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_61,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_62,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_63,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x504++0x03 line.long 0x00 "L4_AP_REGION_l_H_64,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x50C++0x03 line.long 0x00 "L4_AP_REGION_l_H_65,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x514++0x03 line.long 0x00 "L4_AP_REGION_l_H_66,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x51C++0x03 line.long 0x00 "L4_AP_REGION_l_H_67,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x524++0x03 line.long 0x00 "L4_AP_REGION_l_H_68,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x52C++0x03 line.long 0x00 "L4_AP_REGION_l_H_69,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x534++0x03 line.long 0x00 "L4_AP_REGION_l_H_70,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x53C++0x03 line.long 0x00 "L4_AP_REGION_l_H_71,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x544++0x03 line.long 0x00 "L4_AP_REGION_l_H_72,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x54C++0x03 line.long 0x00 "L4_AP_REGION_l_H_73,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x554++0x03 line.long 0x00 "L4_AP_REGION_l_H_74,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x55C++0x03 line.long 0x00 "L4_AP_REGION_l_H_75,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x564++0x03 line.long 0x00 "L4_AP_REGION_l_H_76,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x56C++0x03 line.long 0x00 "L4_AP_REGION_l_H_77,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x574++0x03 line.long 0x00 "L4_AP_REGION_l_H_78,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x57C++0x03 line.long 0x00 "L4_AP_REGION_l_H_79,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x584++0x03 line.long 0x00 "L4_AP_REGION_l_H_80,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x58C++0x03 line.long 0x00 "L4_AP_REGION_l_H_81,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x594++0x03 line.long 0x00 "L4_AP_REGION_l_H_82,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x59C++0x03 line.long 0x00 "L4_AP_REGION_l_H_83,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_84,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_85,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_86,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_87,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_88,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_89,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_90,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_91,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_92,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_93,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_94,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_95,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x604++0x03 line.long 0x00 "L4_AP_REGION_l_H_96,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x60C++0x03 line.long 0x00 "L4_AP_REGION_l_H_97,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x614++0x03 line.long 0x00 "L4_AP_REGION_l_H_98,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x61C++0x03 line.long 0x00 "L4_AP_REGION_l_H_99,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x624++0x03 line.long 0x00 "L4_AP_REGION_l_H_100,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x62C++0x03 line.long 0x00 "L4_AP_REGION_l_H_101,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x634++0x03 line.long 0x00 "L4_AP_REGION_l_H_102,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x63C++0x03 line.long 0x00 "L4_AP_REGION_l_H_103,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x644++0x03 line.long 0x00 "L4_AP_REGION_l_H_104,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x64C++0x03 line.long 0x00 "L4_AP_REGION_l_H_105,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x654++0x03 line.long 0x00 "L4_AP_REGION_l_H_106,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x65C++0x03 line.long 0x00 "L4_AP_REGION_l_H_107,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x664++0x03 line.long 0x00 "L4_AP_REGION_l_H_108,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x66C++0x03 line.long 0x00 "L4_AP_REGION_l_H_109,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x674++0x03 line.long 0x00 "L4_AP_REGION_l_H_110,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" width 0x0B tree.end tree "L4_CFG_IA_IP0" base ad:0x4A001000 rgroup.long 0x00++0x07 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x17 line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" rbitfld.long 0x08 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" newline hexmask.long.tbyte 0x08 0.--23. 1. "RESERVED," line.long 0x0C "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" line.long 0x10 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x10 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x10 30. "PROT_ERROR_PRIMARY," "0,1" rbitfld.long 0x10 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x10 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x10 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x10 24. "MERROR,Value of the OCP MError signal" "0,1" newline hexmask.long.tbyte 0x10 0.--23. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0F line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" rbitfld.long 0x00 26.--29. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "No errors,Unsupported command,Address hole,Protection violation" hexmask.long.word 0x00 14.--23. 1. "RESERVED,Read returns 0" rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 3.--7. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--2. "CMD,Command that has caused an error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that has caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" line.long 0x0C "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" width 0x0B tree.end tree "L4_CFG_LA" base ad:0x4A000800 rgroup.long 0x00++0x07 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" newline hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x10++0x17 line.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" line.long 0x04 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x08 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x08 28.--31. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "PROT_GROUPS,Number of protection groups in the current L4" "No protection group,1 protection group,2 protection groups,?,?,?,?,?,8 protection groups 0x9 to,?,?,?,?,?,?,Reserved" newline abitfld.long 0x08 16.--23. "NUMBER_REGIONS,Number of regions in the current L4" "0x00=Reserved,0x01=1 region,0x02=2 regions,0xFF=Reserved 'Max regions' is listed in on row.." newline hexmask.long.word 0x08 4.--15. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 0.--3. "SEGMENTS,Number of segments in the current L4" "Reserved,1 segment,2 segments,?,?,?,?,?,8 segments,?..." line.long 0x0C "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" hexmask.long.word 0x0C 19.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x0C 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 15. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 11. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "?,16-bit data width is specified,32-bit data width is specified,?..." newline bitfld.long 0x0C 6.--7. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" hexmask.long.tbyte 0x10 11.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "Time-out disabled,L4 interconnect clock cycles divided by 64,L4 interconnect clock cycles divided by 256,L4 interconnect clock cycles divided by 1024,L4 interconnect clock cycles divided by 4096,?..." newline hexmask.long.byte 0x10 0.--7. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x14 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" newline rbitfld.long 0x14 21.--23. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 20. "THREAD0_PRI,Sets thread priority" "0,1" newline hexmask.long.word 0x14 9.--19. 1. "RESERVED,Read returns 0" newline rbitfld.long 0x14 8. "EXT_CLOCK,Global external clock control" "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "RESERVED,Read returns 0" width 0x0B tree.end tree "L4_CFG_TARG" base ad:0x44000500 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER1_AP" base ad:0x48000000 rgroup.long 0x00++0x07 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x100++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_0,Defines the base address of each segment" rgroup.long 0x108++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_1,Defines the base address of each segment" rgroup.long 0x104++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_0,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x10C++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_1,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x208++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x210++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x218++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x220++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x228++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x230++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x238++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x280++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x288++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x290++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x298++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Reserved" rgroup.long 0x28C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Reserved" rgroup.long 0x294++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Reserved" rgroup.long 0x29C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Reserved" rgroup.long 0x2A4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Reserved" rgroup.long 0x2AC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Reserved" rgroup.long 0x2B4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Reserved" rgroup.long 0x2BC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Reserved" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x308++0x03 line.long 0x00 "L4_AP_REGION_l_L_1,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x310++0x03 line.long 0x00 "L4_AP_REGION_l_L_2,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x318++0x03 line.long 0x00 "L4_AP_REGION_l_L_3,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x320++0x03 line.long 0x00 "L4_AP_REGION_l_L_4,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x328++0x03 line.long 0x00 "L4_AP_REGION_l_L_5,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x330++0x03 line.long 0x00 "L4_AP_REGION_l_L_6,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x338++0x03 line.long 0x00 "L4_AP_REGION_l_L_7,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x340++0x03 line.long 0x00 "L4_AP_REGION_l_L_8,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x348++0x03 line.long 0x00 "L4_AP_REGION_l_L_9,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x358++0x03 line.long 0x00 "L4_AP_REGION_l_L_11,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x360++0x03 line.long 0x00 "L4_AP_REGION_l_L_12,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x368++0x03 line.long 0x00 "L4_AP_REGION_l_L_13,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x370++0x03 line.long 0x00 "L4_AP_REGION_l_L_14,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x378++0x03 line.long 0x00 "L4_AP_REGION_l_L_15,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x380++0x03 line.long 0x00 "L4_AP_REGION_l_L_16,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x388++0x03 line.long 0x00 "L4_AP_REGION_l_L_17,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x390++0x03 line.long 0x00 "L4_AP_REGION_l_L_18,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x398++0x03 line.long 0x00 "L4_AP_REGION_l_L_19,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_20,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_21,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_22,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_23,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_25,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_26,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_27,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_28,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_29,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_30,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_31,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x400++0x03 line.long 0x00 "L4_AP_REGION_l_L_32,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x408++0x03 line.long 0x00 "L4_AP_REGION_l_L_33,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x410++0x03 line.long 0x00 "L4_AP_REGION_l_L_34,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x418++0x03 line.long 0x00 "L4_AP_REGION_l_L_35,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x420++0x03 line.long 0x00 "L4_AP_REGION_l_L_36,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x428++0x03 line.long 0x00 "L4_AP_REGION_l_L_37,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x430++0x03 line.long 0x00 "L4_AP_REGION_l_L_38,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x438++0x03 line.long 0x00 "L4_AP_REGION_l_L_39,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x448++0x03 line.long 0x00 "L4_AP_REGION_l_L_41,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x450++0x03 line.long 0x00 "L4_AP_REGION_l_L_42,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x458++0x03 line.long 0x00 "L4_AP_REGION_l_L_43,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x460++0x03 line.long 0x00 "L4_AP_REGION_l_L_44,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x468++0x03 line.long 0x00 "L4_AP_REGION_l_L_45,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x470++0x03 line.long 0x00 "L4_AP_REGION_l_L_46,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x478++0x03 line.long 0x00 "L4_AP_REGION_l_L_47,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x480++0x03 line.long 0x00 "L4_AP_REGION_l_L_48,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x488++0x03 line.long 0x00 "L4_AP_REGION_l_L_49,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x490++0x03 line.long 0x00 "L4_AP_REGION_l_L_50,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x498++0x03 line.long 0x00 "L4_AP_REGION_l_L_51,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_52,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_53,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_54,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_55,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_56,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_57,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_58,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_59,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_60,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_61,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_62,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_63,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x500++0x03 line.long 0x00 "L4_AP_REGION_l_L_64,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x508++0x03 line.long 0x00 "L4_AP_REGION_l_L_65,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x510++0x03 line.long 0x00 "L4_AP_REGION_l_L_66,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x518++0x03 line.long 0x00 "L4_AP_REGION_l_L_67,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x520++0x03 line.long 0x00 "L4_AP_REGION_l_L_68,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x528++0x03 line.long 0x00 "L4_AP_REGION_l_L_69,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x530++0x03 line.long 0x00 "L4_AP_REGION_l_L_70,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x538++0x03 line.long 0x00 "L4_AP_REGION_l_L_71,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x540++0x03 line.long 0x00 "L4_AP_REGION_l_L_72,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x548++0x03 line.long 0x00 "L4_AP_REGION_l_L_73,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x550++0x03 line.long 0x00 "L4_AP_REGION_l_L_74,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x558++0x03 line.long 0x00 "L4_AP_REGION_l_L_75,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x560++0x03 line.long 0x00 "L4_AP_REGION_l_L_76,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x568++0x03 line.long 0x00 "L4_AP_REGION_l_L_77,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x30C++0x03 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x314++0x03 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x31C++0x03 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x324++0x03 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x32C++0x03 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x334++0x03 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x33C++0x03 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x344++0x03 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x34C++0x03 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x35C++0x03 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x364++0x03 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x36C++0x03 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x374++0x03 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x37C++0x03 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x384++0x03 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x38C++0x03 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x394++0x03 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x39C++0x03 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x404++0x03 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x40C++0x03 line.long 0x00 "L4_AP_REGION_l_H_33,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x414++0x03 line.long 0x00 "L4_AP_REGION_l_H_34,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x41C++0x03 line.long 0x00 "L4_AP_REGION_l_H_35,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x424++0x03 line.long 0x00 "L4_AP_REGION_l_H_36,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x42C++0x03 line.long 0x00 "L4_AP_REGION_l_H_37,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x434++0x03 line.long 0x00 "L4_AP_REGION_l_H_38,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x43C++0x03 line.long 0x00 "L4_AP_REGION_l_H_39,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x44C++0x03 line.long 0x00 "L4_AP_REGION_l_H_41,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x454++0x03 line.long 0x00 "L4_AP_REGION_l_H_42,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x45C++0x03 line.long 0x00 "L4_AP_REGION_l_H_43,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x464++0x03 line.long 0x00 "L4_AP_REGION_l_H_44,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x46C++0x03 line.long 0x00 "L4_AP_REGION_l_H_45,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x474++0x03 line.long 0x00 "L4_AP_REGION_l_H_46,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x47C++0x03 line.long 0x00 "L4_AP_REGION_l_H_47,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x484++0x03 line.long 0x00 "L4_AP_REGION_l_H_48,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x48C++0x03 line.long 0x00 "L4_AP_REGION_l_H_49,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x494++0x03 line.long 0x00 "L4_AP_REGION_l_H_50,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x49C++0x03 line.long 0x00 "L4_AP_REGION_l_H_51,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_52,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_53,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_54,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_55,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_56,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_57,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_58,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_59,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_60,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_61,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_62,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_63,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x504++0x03 line.long 0x00 "L4_AP_REGION_l_H_64,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x50C++0x03 line.long 0x00 "L4_AP_REGION_l_H_65,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x514++0x03 line.long 0x00 "L4_AP_REGION_l_H_66,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x51C++0x03 line.long 0x00 "L4_AP_REGION_l_H_67,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x524++0x03 line.long 0x00 "L4_AP_REGION_l_H_68,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x52C++0x03 line.long 0x00 "L4_AP_REGION_l_H_69,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x534++0x03 line.long 0x00 "L4_AP_REGION_l_H_70,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x53C++0x03 line.long 0x00 "L4_AP_REGION_l_H_71,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x544++0x03 line.long 0x00 "L4_AP_REGION_l_H_72,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x54C++0x03 line.long 0x00 "L4_AP_REGION_l_H_73,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x554++0x03 line.long 0x00 "L4_AP_REGION_l_H_74,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x55C++0x03 line.long 0x00 "L4_AP_REGION_l_H_75,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x564++0x03 line.long 0x00 "L4_AP_REGION_l_H_76,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x56C++0x03 line.long 0x00 "L4_AP_REGION_l_H_77,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x48001000 ad:0x48001400 ) tree "L4_PER1_IA_IP$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x17 line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" rbitfld.long 0x08 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" newline hexmask.long.tbyte 0x08 0.--23. 1. "RESERVED," line.long 0x0C "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" line.long 0x10 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x10 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x10 30. "PROT_ERROR_PRIMARY," "0,1" rbitfld.long 0x10 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x10 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x10 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x10 24. "MERROR,Value of the OCP MError signal" "0,1" newline hexmask.long.tbyte 0x10 0.--23. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0F line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" rbitfld.long 0x00 26.--29. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "No errors,Unsupported command,Address hole,Protection violation" hexmask.long.word 0x00 14.--23. 1. "RESERVED,Read returns 0" rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 3.--7. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--2. "CMD,Command that has caused an error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that has caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" line.long 0x0C "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" width 0x0B tree.end repeat.end tree "L4_PER1_LA" base ad:0x48000800 rgroup.long 0x00++0x07 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" newline hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x10++0x17 line.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" line.long 0x04 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x08 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x08 28.--31. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "PROT_GROUPS,Number of protection groups in the current L4" "No protection group,1 protection group,2 protection groups,?,?,?,?,?,8 protection groups 0x9 to,?,?,?,?,?,?,Reserved" newline abitfld.long 0x08 16.--23. "NUMBER_REGIONS,Number of regions in the current L4" "0x00=Reserved,0x01=1 region,0x02=2 regions,0xFF=Reserved 'Max regions' is listed in on row.." newline hexmask.long.word 0x08 4.--15. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 0.--3. "SEGMENTS,Number of segments in the current L4" "Reserved,1 segment,2 segments,?,?,?,?,?,8 segments,?..." line.long 0x0C "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" hexmask.long.word 0x0C 19.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x0C 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 15. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 11. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "?,16-bit data width is specified,32-bit data width is specified,?..." newline bitfld.long 0x0C 6.--7. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" hexmask.long.tbyte 0x10 11.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "Time-out disabled,L4 interconnect clock cycles divided by 64,L4 interconnect clock cycles divided by 256,L4 interconnect clock cycles divided by 1024,L4 interconnect clock cycles divided by 4096,?..." newline hexmask.long.byte 0x10 0.--7. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x14 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" newline rbitfld.long 0x14 21.--23. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 20. "THREAD0_PRI,Sets thread priority" "0,1" newline hexmask.long.word 0x14 9.--19. 1. "RESERVED,Read returns 0" newline rbitfld.long 0x14 8. "EXT_CLOCK,Global external clock control" "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "RESERVED,Read returns 0" group.long 0x100++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_0,Mask of composite sideband flag(0)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x120++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_1,Mask of composite sideband flag(0)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x104++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_H_0,Status of composite sideband flag(0)" rgroup.long 0x124++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_H_1,Status of composite sideband flag(0)" group.long 0x110++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_0,Mask of composite sideband flag(1)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_1,Mask of composite sideband flag(1)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x114++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_H_0,Status of composite sideband flag(1)" rgroup.long 0x134++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_H_1,Status of composite sideband flag(1)" width 0x0B tree.end tree "L4_PER1_P1_TARG" base ad:0x44001C00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER1_P2_TARG" base ad:0x44001F00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER2_AP" base ad:0x48400000 rgroup.long 0x00++0x07 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x100++0x07 line.long 0x00 "L4_AP_SEGMENT_i_L,Defines the base address of each segment" line.long 0x04 "L4_AP_SEGMENT_i_H,Defines the size of each segment" hexmask.long 0x04 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x04 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x208++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x210++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x218++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x220++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x228++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x230++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x238++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x280++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x288++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x290++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x298++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Reserved" rgroup.long 0x28C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Reserved" rgroup.long 0x294++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Reserved" rgroup.long 0x29C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Reserved" rgroup.long 0x2A4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Reserved" rgroup.long 0x2AC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Reserved" rgroup.long 0x2B4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Reserved" rgroup.long 0x2BC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Reserved" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x308++0x03 line.long 0x00 "L4_AP_REGION_l_L_1,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x310++0x03 line.long 0x00 "L4_AP_REGION_l_L_2,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x318++0x03 line.long 0x00 "L4_AP_REGION_l_L_3,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x320++0x03 line.long 0x00 "L4_AP_REGION_l_L_4,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x328++0x03 line.long 0x00 "L4_AP_REGION_l_L_5,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x330++0x03 line.long 0x00 "L4_AP_REGION_l_L_6,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x338++0x03 line.long 0x00 "L4_AP_REGION_l_L_7,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x340++0x03 line.long 0x00 "L4_AP_REGION_l_L_8,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x348++0x03 line.long 0x00 "L4_AP_REGION_l_L_9,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x358++0x03 line.long 0x00 "L4_AP_REGION_l_L_11,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x360++0x03 line.long 0x00 "L4_AP_REGION_l_L_12,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x368++0x03 line.long 0x00 "L4_AP_REGION_l_L_13,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x370++0x03 line.long 0x00 "L4_AP_REGION_l_L_14,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x378++0x03 line.long 0x00 "L4_AP_REGION_l_L_15,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x380++0x03 line.long 0x00 "L4_AP_REGION_l_L_16,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x388++0x03 line.long 0x00 "L4_AP_REGION_l_L_17,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x390++0x03 line.long 0x00 "L4_AP_REGION_l_L_18,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x398++0x03 line.long 0x00 "L4_AP_REGION_l_L_19,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_20,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_21,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_22,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_23,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_25,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_26,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_27,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_28,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_29,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_30,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_31,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x400++0x03 line.long 0x00 "L4_AP_REGION_l_L_32,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x30C++0x03 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x314++0x03 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x31C++0x03 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x324++0x03 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x32C++0x03 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x334++0x03 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x33C++0x03 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x344++0x03 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x34C++0x03 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x35C++0x03 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x364++0x03 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x36C++0x03 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x374++0x03 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x37C++0x03 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x384++0x03 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x38C++0x03 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x394++0x03 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x39C++0x03 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x404++0x03 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" width 0x0B tree.end tree "L4_PER2_IA_IP0" base ad:0x48401000 rgroup.long 0x00++0x07 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x17 line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" rbitfld.long 0x08 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" newline hexmask.long.tbyte 0x08 0.--23. 1. "RESERVED," line.long 0x0C "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" line.long 0x10 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x10 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x10 30. "PROT_ERROR_PRIMARY," "0,1" rbitfld.long 0x10 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x10 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x10 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x10 24. "MERROR,Value of the OCP MError signal" "0,1" newline hexmask.long.tbyte 0x10 0.--23. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0F line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" rbitfld.long 0x00 26.--29. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "No errors,Unsupported command,Address hole,Protection violation" hexmask.long.word 0x00 14.--23. 1. "RESERVED,Read returns 0" rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 3.--7. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--2. "CMD,Command that has caused an error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that has caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" line.long 0x0C "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" width 0x0B tree.end tree "L4_PER2_LA" base ad:0x48400800 rgroup.long 0x00++0x07 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" newline hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x10++0x17 line.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" line.long 0x04 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x08 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x08 28.--31. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "PROT_GROUPS,Number of protection groups in the current L4" "No protection group,1 protection group,2 protection groups,?,?,?,?,?,8 protection groups 0x9 to,?,?,?,?,?,?,Reserved" newline abitfld.long 0x08 16.--23. "NUMBER_REGIONS,Number of regions in the current L4" "0x00=Reserved,0x01=1 region,0x02=2 regions,0xFF=Reserved 'Max regions' is listed in on row.." newline hexmask.long.word 0x08 4.--15. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 0.--3. "SEGMENTS,Number of segments in the current L4" "Reserved,1 segment,2 segments,?,?,?,?,?,8 segments,?..." line.long 0x0C "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" hexmask.long.word 0x0C 19.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x0C 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 15. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 11. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "?,16-bit data width is specified,32-bit data width is specified,?..." newline bitfld.long 0x0C 6.--7. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" hexmask.long.tbyte 0x10 11.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "Time-out disabled,L4 interconnect clock cycles divided by 64,L4 interconnect clock cycles divided by 256,L4 interconnect clock cycles divided by 1024,L4 interconnect clock cycles divided by 4096,?..." newline hexmask.long.byte 0x10 0.--7. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x14 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" newline rbitfld.long 0x14 21.--23. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 20. "THREAD0_PRI,Sets thread priority" "0,1" newline hexmask.long.word 0x14 9.--19. 1. "RESERVED,Read returns 0" newline rbitfld.long 0x14 8. "EXT_CLOCK,Global external clock control" "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "RESERVED,Read returns 0" group.long 0x100++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_0,Mask of composite sideband flag(0)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x120++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_1,Mask of composite sideband flag(0)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x104++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_H_0,Status of composite sideband flag(0)" rgroup.long 0x124++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_H_1,Status of composite sideband flag(0)" group.long 0x110++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_0,Mask of composite sideband flag(1)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_1,Mask of composite sideband flag(1)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x114++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_H_0,Status of composite sideband flag(1)" rgroup.long 0x134++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_H_1,Status of composite sideband flag(1)" width 0x0B tree.end tree "L4_PER2_P1_TARG" base ad:0x44002300 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER3_AP" base ad:0x48800000 rgroup.long 0x00++0x07 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x100++0x07 line.long 0x00 "L4_AP_SEGMENT_i_L,Defines the base address of each segment" line.long 0x04 "L4_AP_SEGMENT_i_H,Defines the size of each segment" hexmask.long 0x04 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x04 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x208++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x210++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x218++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x220++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x228++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x230++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x238++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x280++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x288++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x290++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x298++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Reserved" rgroup.long 0x28C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Reserved" rgroup.long 0x294++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Reserved" rgroup.long 0x29C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Reserved" rgroup.long 0x2A4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Reserved" rgroup.long 0x2AC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Reserved" rgroup.long 0x2B4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Reserved" rgroup.long 0x2BC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Reserved" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x308++0x03 line.long 0x00 "L4_AP_REGION_l_L_1,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x310++0x03 line.long 0x00 "L4_AP_REGION_l_L_2,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x318++0x03 line.long 0x00 "L4_AP_REGION_l_L_3,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x320++0x03 line.long 0x00 "L4_AP_REGION_l_L_4,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x328++0x03 line.long 0x00 "L4_AP_REGION_l_L_5,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x330++0x03 line.long 0x00 "L4_AP_REGION_l_L_6,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x338++0x03 line.long 0x00 "L4_AP_REGION_l_L_7,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x340++0x03 line.long 0x00 "L4_AP_REGION_l_L_8,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x348++0x03 line.long 0x00 "L4_AP_REGION_l_L_9,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x358++0x03 line.long 0x00 "L4_AP_REGION_l_L_11,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x360++0x03 line.long 0x00 "L4_AP_REGION_l_L_12,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x368++0x03 line.long 0x00 "L4_AP_REGION_l_L_13,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x370++0x03 line.long 0x00 "L4_AP_REGION_l_L_14,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x378++0x03 line.long 0x00 "L4_AP_REGION_l_L_15,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x380++0x03 line.long 0x00 "L4_AP_REGION_l_L_16,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x388++0x03 line.long 0x00 "L4_AP_REGION_l_L_17,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x390++0x03 line.long 0x00 "L4_AP_REGION_l_L_18,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x398++0x03 line.long 0x00 "L4_AP_REGION_l_L_19,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_20,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_21,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_22,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_23,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_25,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_26,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_27,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_28,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_29,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_30,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_31,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x400++0x03 line.long 0x00 "L4_AP_REGION_l_L_32,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x408++0x03 line.long 0x00 "L4_AP_REGION_l_L_33,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x410++0x03 line.long 0x00 "L4_AP_REGION_l_L_34,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x418++0x03 line.long 0x00 "L4_AP_REGION_l_L_35,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x420++0x03 line.long 0x00 "L4_AP_REGION_l_L_36,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x428++0x03 line.long 0x00 "L4_AP_REGION_l_L_37,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x430++0x03 line.long 0x00 "L4_AP_REGION_l_L_38,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x438++0x03 line.long 0x00 "L4_AP_REGION_l_L_39,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x448++0x03 line.long 0x00 "L4_AP_REGION_l_L_41,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x450++0x03 line.long 0x00 "L4_AP_REGION_l_L_42,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x458++0x03 line.long 0x00 "L4_AP_REGION_l_L_43,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x460++0x03 line.long 0x00 "L4_AP_REGION_l_L_44,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x468++0x03 line.long 0x00 "L4_AP_REGION_l_L_45,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x470++0x03 line.long 0x00 "L4_AP_REGION_l_L_46,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x478++0x03 line.long 0x00 "L4_AP_REGION_l_L_47,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x480++0x03 line.long 0x00 "L4_AP_REGION_l_L_48,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x488++0x03 line.long 0x00 "L4_AP_REGION_l_L_49,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x490++0x03 line.long 0x00 "L4_AP_REGION_l_L_50,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x498++0x03 line.long 0x00 "L4_AP_REGION_l_L_51,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_52,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_53,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_54,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_55,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_56,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_57,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_58,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_59,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_60,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_61,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_62,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_63,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x500++0x03 line.long 0x00 "L4_AP_REGION_l_L_64,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x508++0x03 line.long 0x00 "L4_AP_REGION_l_L_65,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x510++0x03 line.long 0x00 "L4_AP_REGION_l_L_66,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x518++0x03 line.long 0x00 "L4_AP_REGION_l_L_67,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x520++0x03 line.long 0x00 "L4_AP_REGION_l_L_68,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x528++0x03 line.long 0x00 "L4_AP_REGION_l_L_69,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x530++0x03 line.long 0x00 "L4_AP_REGION_l_L_70,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x538++0x03 line.long 0x00 "L4_AP_REGION_l_L_71,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x540++0x03 line.long 0x00 "L4_AP_REGION_l_L_72,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x548++0x03 line.long 0x00 "L4_AP_REGION_l_L_73,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x550++0x03 line.long 0x00 "L4_AP_REGION_l_L_74,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x558++0x03 line.long 0x00 "L4_AP_REGION_l_L_75,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x560++0x03 line.long 0x00 "L4_AP_REGION_l_L_76,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x568++0x03 line.long 0x00 "L4_AP_REGION_l_L_77,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x570++0x03 line.long 0x00 "L4_AP_REGION_l_L_78,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x578++0x03 line.long 0x00 "L4_AP_REGION_l_L_79,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x580++0x03 line.long 0x00 "L4_AP_REGION_l_L_80,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x588++0x03 line.long 0x00 "L4_AP_REGION_l_L_81,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x590++0x03 line.long 0x00 "L4_AP_REGION_l_L_82,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x598++0x03 line.long 0x00 "L4_AP_REGION_l_L_83,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_84,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_85,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_86,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_87,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_88,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_89,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_90,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_91,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_92,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_93,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x30C++0x03 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x314++0x03 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x31C++0x03 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x324++0x03 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x32C++0x03 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x334++0x03 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x33C++0x03 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x344++0x03 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x34C++0x03 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x35C++0x03 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x364++0x03 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x36C++0x03 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x374++0x03 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x37C++0x03 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x384++0x03 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x38C++0x03 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x394++0x03 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x39C++0x03 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x404++0x03 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x40C++0x03 line.long 0x00 "L4_AP_REGION_l_H_33,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x414++0x03 line.long 0x00 "L4_AP_REGION_l_H_34,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x41C++0x03 line.long 0x00 "L4_AP_REGION_l_H_35,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x424++0x03 line.long 0x00 "L4_AP_REGION_l_H_36,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x42C++0x03 line.long 0x00 "L4_AP_REGION_l_H_37,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x434++0x03 line.long 0x00 "L4_AP_REGION_l_H_38,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x43C++0x03 line.long 0x00 "L4_AP_REGION_l_H_39,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x44C++0x03 line.long 0x00 "L4_AP_REGION_l_H_41,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x454++0x03 line.long 0x00 "L4_AP_REGION_l_H_42,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x45C++0x03 line.long 0x00 "L4_AP_REGION_l_H_43,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x464++0x03 line.long 0x00 "L4_AP_REGION_l_H_44,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x46C++0x03 line.long 0x00 "L4_AP_REGION_l_H_45,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x474++0x03 line.long 0x00 "L4_AP_REGION_l_H_46,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x47C++0x03 line.long 0x00 "L4_AP_REGION_l_H_47,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x484++0x03 line.long 0x00 "L4_AP_REGION_l_H_48,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x48C++0x03 line.long 0x00 "L4_AP_REGION_l_H_49,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x494++0x03 line.long 0x00 "L4_AP_REGION_l_H_50,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x49C++0x03 line.long 0x00 "L4_AP_REGION_l_H_51,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_52,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_53,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_54,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_55,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_56,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_57,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_58,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_59,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_60,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_61,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_62,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_63,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x504++0x03 line.long 0x00 "L4_AP_REGION_l_H_64,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x50C++0x03 line.long 0x00 "L4_AP_REGION_l_H_65,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x514++0x03 line.long 0x00 "L4_AP_REGION_l_H_66,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x51C++0x03 line.long 0x00 "L4_AP_REGION_l_H_67,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x524++0x03 line.long 0x00 "L4_AP_REGION_l_H_68,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x52C++0x03 line.long 0x00 "L4_AP_REGION_l_H_69,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x534++0x03 line.long 0x00 "L4_AP_REGION_l_H_70,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x53C++0x03 line.long 0x00 "L4_AP_REGION_l_H_71,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x544++0x03 line.long 0x00 "L4_AP_REGION_l_H_72,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x54C++0x03 line.long 0x00 "L4_AP_REGION_l_H_73,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x554++0x03 line.long 0x00 "L4_AP_REGION_l_H_74,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x55C++0x03 line.long 0x00 "L4_AP_REGION_l_H_75,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x564++0x03 line.long 0x00 "L4_AP_REGION_l_H_76,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x56C++0x03 line.long 0x00 "L4_AP_REGION_l_H_77,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x574++0x03 line.long 0x00 "L4_AP_REGION_l_H_78,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x57C++0x03 line.long 0x00 "L4_AP_REGION_l_H_79,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x584++0x03 line.long 0x00 "L4_AP_REGION_l_H_80,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x58C++0x03 line.long 0x00 "L4_AP_REGION_l_H_81,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x594++0x03 line.long 0x00 "L4_AP_REGION_l_H_82,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x59C++0x03 line.long 0x00 "L4_AP_REGION_l_H_83,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_84,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_85,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_86,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_87,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_88,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_89,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_90,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_91,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_92,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_93,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" width 0x0B tree.end repeat 2. (list 1. 2. )(list ad:0x48801400 ad:0x48801800 ) tree "L4_PER3_IA_IP$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x17 line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" rbitfld.long 0x08 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" newline hexmask.long.tbyte 0x08 0.--23. 1. "RESERVED," line.long 0x0C "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" line.long 0x10 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x10 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x10 30. "PROT_ERROR_PRIMARY," "0,1" rbitfld.long 0x10 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x10 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x10 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x10 24. "MERROR,Value of the OCP MError signal" "0,1" newline hexmask.long.tbyte 0x10 0.--23. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0F line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" rbitfld.long 0x00 26.--29. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "No errors,Unsupported command,Address hole,Protection violation" hexmask.long.word 0x00 14.--23. 1. "RESERVED,Read returns 0" rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 3.--7. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--2. "CMD,Command that has caused an error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that has caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" line.long 0x0C "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" width 0x0B tree.end repeat.end tree "L4_PER3_LA" base ad:0x48800800 rgroup.long 0x00++0x07 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" newline hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x10++0x17 line.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" line.long 0x04 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x08 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x08 28.--31. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "PROT_GROUPS,Number of protection groups in the current L4" "No protection group,1 protection group,2 protection groups,?,?,?,?,?,8 protection groups 0x9 to,?,?,?,?,?,?,Reserved" newline abitfld.long 0x08 16.--23. "NUMBER_REGIONS,Number of regions in the current L4" "0x00=Reserved,0x01=1 region,0x02=2 regions,0xFF=Reserved 'Max regions' is listed in on row.." newline hexmask.long.word 0x08 4.--15. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 0.--3. "SEGMENTS,Number of segments in the current L4" "Reserved,1 segment,2 segments,?,?,?,?,?,8 segments,?..." line.long 0x0C "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" hexmask.long.word 0x0C 19.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x0C 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 15. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 11. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "?,16-bit data width is specified,32-bit data width is specified,?..." newline bitfld.long 0x0C 6.--7. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" hexmask.long.tbyte 0x10 11.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "Time-out disabled,L4 interconnect clock cycles divided by 64,L4 interconnect clock cycles divided by 256,L4 interconnect clock cycles divided by 1024,L4 interconnect clock cycles divided by 4096,?..." newline hexmask.long.byte 0x10 0.--7. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x14 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" newline rbitfld.long 0x14 21.--23. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 20. "THREAD0_PRI,Sets thread priority" "0,1" newline hexmask.long.word 0x14 9.--19. 1. "RESERVED,Read returns 0" newline rbitfld.long 0x14 8. "EXT_CLOCK,Global external clock control" "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "RESERVED,Read returns 0" group.long 0x100++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_0,Mask of composite sideband flag(0)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x120++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_1,Mask of composite sideband flag(0)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x104++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_H_0,Status of composite sideband flag(0)" rgroup.long 0x124++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_H_1,Status of composite sideband flag(0)" group.long 0x110++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_0,Mask of composite sideband flag(1)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_1,Mask of composite sideband flag(1)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x114++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_H_0,Status of composite sideband flag(1)" rgroup.long 0x134++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_H_1,Status of composite sideband flag(1)" width 0x0B tree.end tree "L4_PER3_P1_TARG" base ad:0x44002600 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER3_P2_TARG" base ad:0x44002700 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_WKUP_AP" base ad:0x4AE00000 rgroup.long 0x00++0x07 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x100++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_0,Defines the base address of each segment" rgroup.long 0x108++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_1,Defines the base address of each segment" rgroup.long 0x110++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_2,Defines the base address of each segment" rgroup.long 0x118++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_3,Defines the base address of each segment" rgroup.long 0x104++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_0,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x10C++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_1,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x114++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_2,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x11C++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_3,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x208++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x210++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x218++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x220++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x228++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x230++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x238++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x280++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x288++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x290++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x298++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Reserved" rgroup.long 0x28C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Reserved" rgroup.long 0x294++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Reserved" rgroup.long 0x29C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Reserved" rgroup.long 0x2A4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Reserved" rgroup.long 0x2AC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Reserved" rgroup.long 0x2B4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Reserved" rgroup.long 0x2BC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Reserved" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x308++0x03 line.long 0x00 "L4_AP_REGION_l_L_1,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x310++0x03 line.long 0x00 "L4_AP_REGION_l_L_2,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x318++0x03 line.long 0x00 "L4_AP_REGION_l_L_3,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x320++0x03 line.long 0x00 "L4_AP_REGION_l_L_4,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x328++0x03 line.long 0x00 "L4_AP_REGION_l_L_5,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x330++0x03 line.long 0x00 "L4_AP_REGION_l_L_6,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x338++0x03 line.long 0x00 "L4_AP_REGION_l_L_7,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x340++0x03 line.long 0x00 "L4_AP_REGION_l_L_8,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x348++0x03 line.long 0x00 "L4_AP_REGION_l_L_9,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x358++0x03 line.long 0x00 "L4_AP_REGION_l_L_11,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x360++0x03 line.long 0x00 "L4_AP_REGION_l_L_12,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x368++0x03 line.long 0x00 "L4_AP_REGION_l_L_13,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x370++0x03 line.long 0x00 "L4_AP_REGION_l_L_14,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x378++0x03 line.long 0x00 "L4_AP_REGION_l_L_15,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x380++0x03 line.long 0x00 "L4_AP_REGION_l_L_16,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x388++0x03 line.long 0x00 "L4_AP_REGION_l_L_17,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x390++0x03 line.long 0x00 "L4_AP_REGION_l_L_18,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x398++0x03 line.long 0x00 "L4_AP_REGION_l_L_19,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_20,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_21,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_22,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_23,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_25,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_26,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_27,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_28,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_29,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_30,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_31,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x400++0x03 line.long 0x00 "L4_AP_REGION_l_L_32,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x408++0x03 line.long 0x00 "L4_AP_REGION_l_L_33,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x410++0x03 line.long 0x00 "L4_AP_REGION_l_L_34,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x418++0x03 line.long 0x00 "L4_AP_REGION_l_L_35,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x420++0x03 line.long 0x00 "L4_AP_REGION_l_L_36,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x428++0x03 line.long 0x00 "L4_AP_REGION_l_L_37,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x430++0x03 line.long 0x00 "L4_AP_REGION_l_L_38,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x438++0x03 line.long 0x00 "L4_AP_REGION_l_L_39,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x448++0x03 line.long 0x00 "L4_AP_REGION_l_L_41,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x450++0x03 line.long 0x00 "L4_AP_REGION_l_L_42,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x458++0x03 line.long 0x00 "L4_AP_REGION_l_L_43,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x30C++0x03 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x314++0x03 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x31C++0x03 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x324++0x03 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x32C++0x03 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x334++0x03 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x33C++0x03 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x344++0x03 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x34C++0x03 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x35C++0x03 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x364++0x03 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x36C++0x03 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x374++0x03 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x37C++0x03 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x384++0x03 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x38C++0x03 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x394++0x03 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x39C++0x03 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x404++0x03 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x40C++0x03 line.long 0x00 "L4_AP_REGION_l_H_33,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x414++0x03 line.long 0x00 "L4_AP_REGION_l_H_34,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x41C++0x03 line.long 0x00 "L4_AP_REGION_l_H_35,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x424++0x03 line.long 0x00 "L4_AP_REGION_l_H_36,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x42C++0x03 line.long 0x00 "L4_AP_REGION_l_H_37,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x434++0x03 line.long 0x00 "L4_AP_REGION_l_H_38,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x43C++0x03 line.long 0x00 "L4_AP_REGION_l_H_39,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x44C++0x03 line.long 0x00 "L4_AP_REGION_l_H_41,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x454++0x03 line.long 0x00 "L4_AP_REGION_l_H_42,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x45C++0x03 line.long 0x00 "L4_AP_REGION_l_H_43,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" width 0x0B tree.end tree "L4_WKUP_COUNTER_32K" base ad:0x4AE04000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION,This register contains the sync counter IP revision code" group.long 0x10++0x03 line.long 0x00 "SYSCONFIG,This register is used for idle modes only" hexmask.long 0x00 5.--31. 1. "Reserved,Reads return 0" bitfld.long 0x00 3.--4. "IDLEMODE,Power management REQ/ACK control" "0,1,2,3" rbitfld.long 0x00 1.--2. "Reserved,Reads return 0" "0,1,2,3" bitfld.long 0x00 0. "SYNCMODE,Synchronization scheme0x0 Gray synchronization scheme" "0,1" rgroup.long 0x30++0x03 line.long 0x00 "CR,This register contains the 32-kHz sync counter value" width 0x0B tree.end tree "L4_WKUP_IA_IP0" base ad:0x4AE01000 rgroup.long 0x00++0x07 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x17 line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" rbitfld.long 0x08 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" newline hexmask.long.tbyte 0x08 0.--23. 1. "RESERVED," line.long 0x0C "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" line.long 0x10 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x10 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x10 30. "PROT_ERROR_PRIMARY," "0,1" rbitfld.long 0x10 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x10 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x10 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x10 24. "MERROR,Value of the OCP MError signal" "0,1" newline hexmask.long.tbyte 0x10 0.--23. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0F line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" rbitfld.long 0x00 26.--29. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "No errors,Unsupported command,Address hole,Protection violation" hexmask.long.word 0x00 14.--23. 1. "RESERVED,Read returns 0" rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 3.--7. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--2. "CMD,Command that has caused an error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that has caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" line.long 0x0C "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" width 0x0B tree.end tree "L4_WKUP_LA" base ad:0x4AE00800 rgroup.long 0x00++0x07 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" newline hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x10++0x17 line.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" line.long 0x04 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x08 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x08 28.--31. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "PROT_GROUPS,Number of protection groups in the current L4" "No protection group,1 protection group,2 protection groups,?,?,?,?,?,8 protection groups 0x9 to,?,?,?,?,?,?,Reserved" newline abitfld.long 0x08 16.--23. "NUMBER_REGIONS,Number of regions in the current L4" "0x00=Reserved,0x01=1 region,0x02=2 regions,0xFF=Reserved 'Max regions' is listed in on row.." newline hexmask.long.word 0x08 4.--15. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 0.--3. "SEGMENTS,Number of segments in the current L4" "Reserved,1 segment,2 segments,?,?,?,?,?,8 segments,?..." line.long 0x0C "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" hexmask.long.word 0x0C 19.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x0C 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 15. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 11. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "?,16-bit data width is specified,32-bit data width is specified,?..." newline bitfld.long 0x0C 6.--7. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" hexmask.long.tbyte 0x10 11.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "Time-out disabled,L4 interconnect clock cycles divided by 64,L4 interconnect clock cycles divided by 256,L4 interconnect clock cycles divided by 1024,L4 interconnect clock cycles divided by 4096,?..." newline hexmask.long.byte 0x10 0.--7. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x14 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" newline rbitfld.long 0x14 21.--23. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 20. "THREAD0_PRI,Sets thread priority" "0,1" newline hexmask.long.word 0x14 9.--19. 1. "RESERVED,Read returns 0" newline rbitfld.long 0x14 8. "EXT_CLOCK,Global external clock control" "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "RESERVED,Read returns 0" width 0x0B tree.end tree "L4_WKUP_TARG" base ad:0x44001D00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4PER_CM_CORE" base ad:0x4A009700 group.long 0x00++0x03 line.long 0x00 "CM_L4PER_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "CLKACTIVITY_L4PER_32K_GFCLK,This field indicates the state of the L4PER_32K_FCLK clock in the domain" "CLKACTIVITY_L4PER_32K_GFCLK_0,CLKACTIVITY_L4PER_32K_GFCLK_1" newline rbitfld.long 0x00 26. "CLKACTIVITY_UART5_GFCLK,This field indicates the state of the UART5_GFCLK clock in the domain" "CLKACTIVITY_UART5_GFCLK_0,CLKACTIVITY_UART5_GFCLK_1" rbitfld.long 0x00 25. "CLKACTIVITY_PER_192M_GFCLK,This field indicates the state of the PER_192M_GFCLK clock in the domain" "CLKACTIVITY_PER_192M_GFCLK_0,CLKACTIVITY_PER_192M_GFCLK_1" newline rbitfld.long 0x00 24. "CLKACTIVITY_GPIO_GFCLK,This field indicates the state of the GPIO_GFCLK clock in the domain" "CLKACTIVITY_GPIO_GFCLK_0,CLKACTIVITY_GPIO_GFCLK_1" rbitfld.long 0x00 23. "CLKACTIVITY_MMC4_GFCLK,This field indicates the state of the MMC4_GFCLK clock in the domain" "CLKACTIVITY_MMC4_GFCLK_0,CLKACTIVITY_MMC4_GFCLK_1" newline rbitfld.long 0x00 22. "CLKACTIVITY_MMC3_GFCLK,This field indicates the state of the MMC3_GFCLK clock in the domain" "CLKACTIVITY_MMC3_GFCLK_0,CLKACTIVITY_MMC3_GFCLK_1" rbitfld.long 0x00 21. "CLKACTIVITY_PER_96M_GFCLK,This field indicates the state of the PER_96M_GFCLK clock in the domain" "CLKACTIVITY_PER_96M_GFCLK_0,CLKACTIVITY_PER_96M_GFCLK_1" newline rbitfld.long 0x00 20. "CLKACTIVITY_PER_48M_GFCLK,This field indicates the state of the PER_48M_GFCLK clock in the domain" "CLKACTIVITY_PER_48M_GFCLK_0,CLKACTIVITY_PER_48M_GFCLK_1" rbitfld.long 0x00 19. "CLKACTIVITY_PER_12M_GFCLK,This field indicates the state of the PER_12M_GFCLK clock in the domain" "CLKACTIVITY_PER_12M_GFCLK_0,CLKACTIVITY_PER_12M_GFCLK_1" newline rbitfld.long 0x00 18. "CLKACTIVITY_UART4_GFCLK,This field indicates the state of the UART4_GFCLK clock in the domain" "CLKACTIVITY_UART4_GFCLK_0,CLKACTIVITY_UART4_GFCLK_1" rbitfld.long 0x00 17. "CLKACTIVITY_UART3_GFCLK,This field indicates the state of the UART3_GFCLK clock in the domain" "CLKACTIVITY_UART3_GFCLK_0,CLKACTIVITY_UART3_GFCLK_1" newline rbitfld.long 0x00 16. "CLKACTIVITY_UART2_GFCLK,This field indicates the state of the UART2_GFCLK clock in the domain" "CLKACTIVITY_UART2_GFCLK_0,CLKACTIVITY_UART2_GFCLK_1" rbitfld.long 0x00 15. "CLKACTIVITY_UART1_GFCLK,This field indicates the state of the UART1_GFCLK clock in the domain" "CLKACTIVITY_UART1_GFCLK_0,CLKACTIVITY_UART1_GFCLK_1" newline rbitfld.long 0x00 14. "CLKACTIVITY_DCC5_GFCLK,This field indicates the state of the DMT9_GFCLK clock in the domain" "CLKACTIVITY_DCC5_GFCLK_0,CLKACTIVITY_DCC5_GFCLK_1" rbitfld.long 0x00 13. "CLKACTIVITY_TIMER4_GFCLK,This field indicates the state of the DMT4_GFCLK clock in the domain" "CLKACTIVITY_TIMER4_GFCLK_0,CLKACTIVITY_TIMER4_GFCLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_TIMER3_GFCLK,This field indicates the state of the DMT3_GFCLK clock in the domain" "CLKACTIVITY_TIMER3_GFCLK_0,CLKACTIVITY_TIMER3_GFCLK_1" rbitfld.long 0x00 11. "CLKACTIVITY_TIMER2_GFCLK,This field indicates the state of the DMT2_GFCLK clock in the domain" "CLKACTIVITY_TIMER2_GFCLK_0,CLKACTIVITY_TIMER2_GFCLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_DCC7_GFCLK,This field indicates the state of the DMT11_GFCLK clock in the domain" "CLKACTIVITY_DCC7_GFCLK_0,CLKACTIVITY_DCC7_GFCLK_1" rbitfld.long 0x00 9. "CLKACTIVITY_DCC6_GFCLK,This field indicates the state of the DMT10_GFCLK clock in the domain" "CLKACTIVITY_DCC6_GFCLK_0,CLKACTIVITY_DCC6_GFCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_L4PER_L3_GICLK,This field indicates the state of the L4PER_L3_GICLK clock in the domain" "CLKACTIVITY_L4PER_L3_GICLK_0,CLKACTIVITY_L4PER_L3_GICLK_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4PER clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x08++0x07 line.long 0x00 "CM_L4PER_DYNAMICDEP,This register controls the dynamic domain depedencies from L4PER domain towards 'target' domains" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 15.--23. 1. "RESERVED," rbitfld.long 0x00 14. "L4SEC_DYNDEP,Dynamic dependency towards L4SEC clock domain" "?,L4SEC_DYNDEP_1" newline rbitfld.long 0x00 9.--13. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 8. "DSS_DYNDEP,Dynamic dependency towards DSS clock domain" "?,DSS_DYNDEP_1" newline rbitfld.long 0x00 7. "L3INIT_DYNDEP,Dynamic dependency towards L3INIT clock domain" "?,L3INIT_DYNDEP_1" rbitfld.long 0x00 4.--6. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "IPU_DYNDEP,Dynamic dependency towards IPU clock domain" "?,IPU_DYNDEP_1" rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x04 "CM_L4PER2_L4_PER2_CLKCTRL,This register manages the L4_PER2 clocks" hexmask.long.word 0x04 18.--31. 1. "RESERVED," bitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x04 2.--15. 1. "RESERVED," bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x14++0x07 line.long 0x00 "CM_L4PER3_L4_PER3_CLKCTRL,This register manages the L4_PER3 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" line.long 0x04 "CM_L4PER2_PRUSS1_CLKCTRL,This register manages the PRUSS clocks" hexmask.long.word 0x04 19.--31. 1. "RESERVED," rbitfld.long 0x04 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x04 2.--15. 1. "RESERVED," newline bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x20++0x03 line.long 0x00 "CM_L4PER2_PRUSS2_CLKCTRL,This register manages the PRUSS clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x28++0x03 line.long 0x00 "CM_L4PER_DCC6_CLKCTRL,This register manages the DCC6 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x30++0x03 line.long 0x00 "CM_L4PER_DCC7_CLKCTRL,This register manages the DCC7 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x38++0x03 line.long 0x00 "CM_L4PER_TIMER2_CLKCTRL,This register manages the TIMER2 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_L4PER_TIMER3_CLKCTRL,This register manages the TIMER3 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x48++0x03 line.long 0x00 "CM_L4PER_TIMER4_CLKCTRL,This register manages the TIMER4 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x50++0x03 line.long 0x00 "CM_L4PER_DCC5_CLKCTRL,This register manages the DCC5 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x58++0x03 line.long 0x00 "CM_L4PER_ELM_CLKCTRL,This register manages the ELM clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x60++0x03 line.long 0x00 "CM_L4PER_GPIO2_CLKCTRL,This register manages the GPIO2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x68++0x03 line.long 0x00 "CM_L4PER_GPIO3_CLKCTRL,This register manages the GPIO3 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x70++0x03 line.long 0x00 "CM_L4PER_GPIO4_CLKCTRL,This register manages the GPIO4 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x78++0x03 line.long 0x00 "CM_L4PER_GPIO5_CLKCTRL,This register manages the GPIO5 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x80++0x03 line.long 0x00 "CM_L4PER_GPIO6_CLKCTRL,This register manages the GPIO6 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x88++0x03 line.long 0x00 "CM_L4PER_ESM_CLKCTRL,This register manages the ESM clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x90++0x03 line.long 0x00 "CM_L4PER2_PWMSS2_CLKCTRL,This register manages the PWMSS1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x98++0x03 line.long 0x00 "CM_L4PER2_PWMSS3_CLKCTRL,This register manages the PWMSS2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xA0++0x03 line.long 0x00 "CM_L4PER_I2C1_CLKCTRL,This register manages the I2C1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xA8++0x03 line.long 0x00 "CM_L4PER_I2C2_CLKCTRL,This register manages the I2C2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xB0++0x03 line.long 0x00 "CM_L4PER_I2C3_CLKCTRL,This register manages the I2C3 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xB8++0x03 line.long 0x00 "CM_L4PER_I2C4_CLKCTRL,This register manages the I2C4 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0xC0++0x0B line.long 0x00 "CM_L4PER_L4_PER1_CLKCTRL,This register manages the L4_PER1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" line.long 0x04 "CM_L4PER2_PWMSS1_CLKCTRL,This register manages the PWMSS1 clocks" hexmask.long.word 0x04 18.--31. 1. "RESERVED," rbitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x04 2.--15. 1. "RESERVED," bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x08 "CM_L4PER3_DCC1_CLKCTRL,This register manages the DCC1 clocks" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. "CLKSEL,Select the source of the functional clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" newline rbitfld.long 0x08 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x08 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x08 2.--15. 1. "RESERVED," bitfld.long 0x08 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xD0++0x03 line.long 0x00 "CM_L4PER3_DCC2_CLKCTRL,This register manages the DCC2 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xD8++0x03 line.long 0x00 "CM_L4PER3_DCC3_CLKCTRL,This register manages the DCC3 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xF0++0x03 line.long 0x00 "CM_L4PER_MCSPI1_CLKCTRL,This register manages the MCSPI1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xF8++0x03 line.long 0x00 "CM_L4PER_MCSPI2_CLKCTRL,This register manages the MCSPI2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x100++0x03 line.long 0x00 "CM_L4PER_MCSPI3_CLKCTRL,This register manages the MCSPI3 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x108++0x03 line.long 0x00 "CM_L4PER_MCSPI4_CLKCTRL,This register manages the MCSPI4 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x110++0x03 line.long 0x00 "CM_L4PER_GPIO7_CLKCTRL,This register manages the GPIO7 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x118++0x03 line.long 0x00 "CM_L4PER_GPIO8_CLKCTRL,This register manages the GPIO8 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x120++0x03 line.long 0x00 "CM_L4PER_MMC3_CLKCTRL,This register manages the MMC3 clocks" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 25.--26. "CLKSEL_DIV,Selects the divider value" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" newline bitfld.long 0x00 24. "CLKSEL_MUX,Select the clock for the MMC from DPLL_PER" "CLKSEL_MUX_0,CLKSEL_MUX_1" rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,MMC optional clock control: 32K CLK" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x128++0x03 line.long 0x00 "CM_L4PER_MMC4_CLKCTRL,This register manages the MMC4 clocks" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 25.--26. "CLKSEL_DIV,Selects the divider value" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" newline bitfld.long 0x00 24. "CLKSEL_MUX,Select the clock for the MMC from DPLL_PER" "CLKSEL_MUX_0,CLKSEL_MUX_1" rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,MMC optional clock control: 32K CLK" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x130++0x03 line.long 0x00 "CM_L4PER3_DCC4_CLKCTRL,This register manages the DCC4 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x138++0x03 line.long 0x00 "CM_L4PER2_QSPI_CLKCTRL,This register manages the QSPI clocks" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 25.--26. "CLKSEL_DIV,QSPI clock divide ratio" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" newline bitfld.long 0x00 24. "CLKSEL_SOURCE,Selects the source of the functional clock" "CLKSEL_SOURCE_0,CLKSEL_SOURCE_1" rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x140++0x03 line.long 0x00 "CM_L4PER_UART1_CLKCTRL,This register manages the UART1 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNC_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x148++0x03 line.long 0x00 "CM_L4PER_UART2_CLKCTRL,This register manages the UART2 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNC_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x150++0x03 line.long 0x00 "CM_L4PER_UART3_CLKCTRL,This register manages the UART3 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNC_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x158++0x03 line.long 0x00 "CM_L4PER_UART4_CLKCTRL,This register manages the UART4 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x160++0x03 line.long 0x00 "CM_L4PER2_ADC_CLKCTRL,This register manages the ADC clocks" bitfld.long 0x00 28.--31. "CLKSEL_AHCLKR,Selects reference clock for AHCLKR" "CLKSEL_AHCLKR_0,CLKSEL_AHCLKR_1,CLKSEL_AHCLKR_2,CLKSEL_AHCLKR_3,CLKSEL_AHCLKR_4,CLKSEL_AHCLKR_5,CLKSEL_AHCLKR_6,CLKSEL_AHCLKR_7,CLKSEL_AHCLKR_8,CLKSEL_AHCLKR_9,CLKSEL_AHCLKR_10,CLKSEL_AHCLKR_11,CLKSEL_AHCLKR_12,CLKSEL_AHCLKR_13,CLKSEL_AHCLKR_14,CLKSEL_AHCLKR_15" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" newline bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x00 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x168++0x03 line.long 0x00 "CM_L4PER2_ATL_CLKCTRL,This register manages the ATL module mode (SR2.0)" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" newline bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x00 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x170++0x03 line.long 0x00 "CM_L4PER_UART5_CLKCTRL,This register manages the UART5 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x178++0x03 line.long 0x00 "CM_L4PER2_MCASP5_CLKCTRL,This register manages the MCASP3 clocks (SR2.0)" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" newline bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x00 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x180++0x0B line.long 0x00 "CM_L4SEC_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_L4SEC_L3_GICLK,This field indicates the state of the L3_SECURE_GICLK clock in the domain" "CLKACTIVITY_L4SEC_L3_GICLK_0,CLKACTIVITY_L4SEC_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4PER clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_L4SEC_STATICDEP,This register controls the static domain depedencies from L4SEC domain towards 'target' domains" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED," bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline hexmask.long.byte 0x04 6.--12. 1. "RESERVED," rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "CM_L4SEC_DYNAMICDEP,This register controls the dynamic domain depedencies from L4SEC domain towards 'target' domains" hexmask.long 0x08 6.--31. 1. "RESERVED," bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "L3MAIN1_DYNDEP_0,?" newline bitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "CM_L4PER2_MCASP8_CLKCTRL,This register manages the MCASP8 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" newline bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x00 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x198++0x03 line.long 0x00 "CM_L4PER2_MCASP4_CLKCTRL,This register manages the MCASP2 clocks (SR2.0)" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" newline bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x00 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1A0++0x03 line.long 0x00 "CM_L4SEC_AES1_CLKCTRL,This register manages the AES1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1A8++0x03 line.long 0x00 "CM_L4SEC_AES2_CLKCTRL,This register manages the AES2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1B0++0x03 line.long 0x00 "CM_L4SEC_DES3DES_CLKCTRL,This register manages the DES3DES clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1B8++0x03 line.long 0x00 "CM_L4SEC_FPKA_CLKCTRL,This register manages the FPKA clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1C0++0x03 line.long 0x00 "CM_L4SEC_RNG_CLKCTRL,This register manages the RNG clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1C8++0x03 line.long 0x00 "CM_L4SEC_SHA2MD51_CLKCTRL,This register manages the SHA2MD51 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1D0++0x03 line.long 0x00 "CM_L4PER2_UART7_CLKCTRL,This register manages the UART7 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x1D8++0x03 line.long 0x00 "CM_L4SEC_DMA_CRYPTO_CLKCTRL,This register manages the DMA_CRYPTO clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x1E0++0x03 line.long 0x00 "CM_L4PER2_UART8_CLKCTRL,This register manages the UART8 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1E8++0x03 line.long 0x00 "CM_L4PER2_UART9_CLKCTRL,This register manages the UART9 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1F0++0x03 line.long 0x00 "CM_L4PER2_DCAN2_CLKCTRL,This register manages the MCAN clocks (SR2.0) or DCAN2 clocks (SR1.0)" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1F8++0x1F line.long 0x00 "CM_L4SEC_SHA2MD52_CLKCTRL,This register manages the SHA2MD52 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x04 "CM_L4PER2_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x04 31. "CLKACTIVITY_MCASP8_AUX_GFCLK,This field indicates the state of the MCASP8_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP8_AUX_GFCLK_0,CLKACTIVITY_MCASP8_AUX_GFCLK_1" rbitfld.long 0x04 30. "CLKACTIVITY_MCASP8_AHCLKX,This field indicates the state of the MCASP8_AHCLKX clock in the domain" "CLKACTIVITY_MCASP8_AHCLKX_0,CLKACTIVITY_MCASP8_AHCLKX_1" newline rbitfld.long 0x04 29. "CLKACTIVITY_MCASP7_AUX_GFCLK,This field indicates the state of the MCASP7_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP7_AUX_GFCLK_0,CLKACTIVITY_MCASP7_AUX_GFCLK_1" rbitfld.long 0x04 28. "CLKACTIVITY_MCASP7_AHCLK,This field indicates the state of the MCASP7_AHCLKX clock in the domain" "CLKACTIVITY_MCASP7_AHCLK_0,CLKACTIVITY_MCASP7_AHCLK_1" newline rbitfld.long 0x04 27. "CLKACTIVITY_MCASP6_AUX_GFCLK,This field indicates the state of the MCASP6_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP6_AUX_GFCLK_0,CLKACTIVITY_MCASP6_AUX_GFCLK_1" rbitfld.long 0x04 26. "CLKACTIVITY_MCASP6_AHCLKX,This field indicates the state of the MCASP6_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP6_AHCLKX_0,CLKACTIVITY_MCASP6_AHCLKX_1" newline rbitfld.long 0x04 25. "CLKACTIVITY_MCASP5_AHCLKX,This field indicates the state of the MCASP5_AHCLKX clock in the domain" "CLKACTIVITY_MCASP5_AHCLKX_0,CLKACTIVITY_MCASP5_AHCLKX_1" rbitfld.long 0x04 24. "CLKACTIVITY_MCASP5_AUX_GFCLK,This field indicates the state of the MCASP5_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP5_AUX_GFCLK_0,CLKACTIVITY_MCASP5_AUX_GFCLK_1" newline rbitfld.long 0x04 23. "CLKACTIVITY_MCASP4_AUX_GFCLK,This field indicates the state of the MCASP4_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP4_AUX_GFCLK_0,CLKACTIVITY_MCASP4_AUX_GFCLK_1" rbitfld.long 0x04 22. "CLKACTIVITY_MCASP4_AHCLKX,This field indicates the state of the MCASP4_AHCLKX clock in the domain" "CLKACTIVITY_MCASP4_AHCLKX_0,CLKACTIVITY_MCASP4_AHCLKX_1" newline rbitfld.long 0x04 21. "CLKACTIVITY_MCASP3_AUX_GFCLK,This field indicates the state of the MCASP3_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP3_AUX_GFCLK_0,CLKACTIVITY_MCASP3_AUX_GFCLK_1" rbitfld.long 0x04 20. "CLKACTIVITY_MCASP3_AHCLKX,This field indicates the state of the MCASP3_AHCLKX clock in the domain" "CLKACTIVITY_MCASP3_AHCLKX_0,CLKACTIVITY_MCASP3_AHCLKX_1" newline rbitfld.long 0x04 19. "CLKACTIVITY_MCASP2_AUX_GFCLK,This field indicates the state of the ADC_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP2_AUX_GFCLK_0,CLKACTIVITY_MCASP2_AUX_GFCLK_1" rbitfld.long 0x04 18. "CLKACTIVITY_MCASP2_AHCLKR,This field indicates the state of the ADC_AHCLKR clock in the domain" "CLKACTIVITY_MCASP2_AHCLKR_0,CLKACTIVITY_MCASP2_AHCLKR_1" newline rbitfld.long 0x04 17. "CLKACTIVITY_MCASP2_AHCLKX,This field indicates the state of the ADC_AHCLKX clock in the domain" "CLKACTIVITY_MCASP2_AHCLKX_0,CLKACTIVITY_MCASP2_AHCLKX_1" rbitfld.long 0x04 16. "CLKACTIVITY_L4PER2_L3_GICLK,This field indicates the state of the L4PER2_L3_GICLK clock in the domain" "CLKACTIVITY_L4PER2_L3_GICLK_0,CLKACTIVITY_L4PER2_L3_GICLK_1" newline rbitfld.long 0x04 15. "CLKACTIVITY_DCAN2_SYS_CLK,This field indicates the state of the MCAN_CLK clock in the domain" "CLKACTIVITY_DCAN2_SYS_CLK_0,CLKACTIVITY_DCAN2_SYS_CLK_1" rbitfld.long 0x04 14. "CLKACTIVITY_ICSS_IEP_CLK,This field indicates the state of the ICSS_IEP_CLK clock in the domain" "CLKACTIVITY_ICSS_IEP_CLK_0,CLKACTIVITY_ICSS_IEP_CLK_1" newline rbitfld.long 0x04 13. "CLKACTIVITY_PER_192M_GFCLK,This field indicates the state of the PER_192M_GFCLK clock in the domain" "CLKACTIVITY_PER_192M_GFCLK_0,CLKACTIVITY_PER_192M_GFCLK_1" rbitfld.long 0x04 12. "CLKACTIVITY_QSPI_GFCLK,This field indicates the state of the QSPI_GFCLK clock in the domain" "CLKACTIVITY_QSPI_GFCLK_0,CLKACTIVITY_QSPI_GFCLK_1" newline rbitfld.long 0x04 11. "CLKACTIVITY_UART9_GFCLK,This field indicates the state of the UART9_GFCLK clock in the domain" "CLKACTIVITY_UART9_GFCLK_0,CLKACTIVITY_UART9_GFCLK_1" rbitfld.long 0x04 10. "CLKACTIVITY_UART8_GFCLK,This field indicates the state of the UART8_GFCLK clock in the domain" "CLKACTIVITY_UART8_GFCLK_0,CLKACTIVITY_UART8_GFCLK_1" newline rbitfld.long 0x04 9. "CLKACTIVITY_UART7_GFCLK,This field indicates the state of the UART7_GFCLK clock in the domain" "CLKACTIVITY_UART7_GFCLK_0,CLKACTIVITY_UART7_GFCLK_1" rbitfld.long 0x04 8. "CLKACTIVITY_ICSS_CLK,This field indicates the state of the ICSS_CLK clock in the domain" "CLKACTIVITY_ICSS_CLK_0,CLKACTIVITY_ICSS_CLK_1" newline rbitfld.long 0x04 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4PER clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x08 "CM_L4PER2_DYNAMICDEP,This register controls the dynamic domain depedencies from L4PER2 domain towards 'target' domains" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x08 23. "RESERVED," "0,1" rbitfld.long 0x08 22. "GMAC_DYNDEP,Dynamic dependency towards GMAC clock domain" "?,GMAC_DYNDEP_1" newline hexmask.long.word 0x08 13.--21. 1. "RESERVED," rbitfld.long 0x08 12. "L4CFG_DYNDEP,Dynamic dependency towards L4CFG clock domain" "?,L4CFG_DYNDEP_1" newline rbitfld.long 0x08 8.--11. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x08 7. "L3INIT_DYNDEP,Dynamic dependency towards L3INIT clock domain" "?,L3INIT_DYNDEP_1" newline rbitfld.long 0x08 6. "CRC_DYNDEP,Dynamic dependency towards CRC clock domain" "?,CRC_DYNDEP_1" rbitfld.long 0x08 4.--5. "RESERVED," "0,1,2,3" newline rbitfld.long 0x08 3. "IPU_DYNDEP,Dynamic dependency towards IPU clock domain" "?,IPU_DYNDEP_1" rbitfld.long 0x08 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x0C "CM_L4PER2_MCASP6_CLKCTRL,This register manages the MCASP2 clocks (SR2.0)" rbitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 24.--27. "CLKSEL_AHCLKR,Selects reference clock for AHCLKR (SR2.0)" "CLKSEL_AHCLKR_0,CLKSEL_AHCLKR_1,CLKSEL_AHCLKR_2,CLKSEL_AHCLKR_3,CLKSEL_AHCLKR_4,CLKSEL_AHCLKR_5,CLKSEL_AHCLKR_6,CLKSEL_AHCLKR_7,CLKSEL_AHCLKR_8,CLKSEL_AHCLKR_9,CLKSEL_AHCLKR_10,CLKSEL_AHCLKR_11,CLKSEL_AHCLKR_12,CLKSEL_AHCLKR_13,CLKSEL_AHCLKR_14,CLKSEL_AHCLKR_15" newline bitfld.long 0x0C 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x0C 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x0C 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x0C 2.--15. 1. "RESERVED," newline rbitfld.long 0x0C 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x10 "CM_L4PER2_MCASP7_CLKCTRL,This register manages the MCASP3 clocks (SR2.0)" rbitfld.long 0x10 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. "CLKSEL_AHCLKR,Selects reference clock for AHCLKR (SR2.0)" "CLKSEL_AHCLKR_0,CLKSEL_AHCLKR_1,CLKSEL_AHCLKR_2,CLKSEL_AHCLKR_3,CLKSEL_AHCLKR_4,CLKSEL_AHCLKR_5,CLKSEL_AHCLKR_6,CLKSEL_AHCLKR_7,CLKSEL_AHCLKR_8,CLKSEL_AHCLKR_9,CLKSEL_AHCLKR_10,CLKSEL_AHCLKR_11,CLKSEL_AHCLKR_12,CLKSEL_AHCLKR_13,CLKSEL_AHCLKR_14,CLKSEL_AHCLKR_15" newline bitfld.long 0x10 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x10 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x10 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x10 2.--15. 1. "RESERVED," newline rbitfld.long 0x10 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x14 "CM_L4PER2_STATICDEP,This register controls the static domain depedencies from L4PER2 domain towards 'target' domains" hexmask.long.byte 0x14 24.--31. 1. "RESERVED," bitfld.long 0x14 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline rbitfld.long 0x14 19.--22. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline hexmask.long.word 0x14 6.--17. 1. "RESERVED," rbitfld.long 0x14 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline rbitfld.long 0x14 2.--4. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x14 1. "DSP1_STATDEP,Static dependency towards DSP1 clock domain" "DSP1_STATDEP_0,DSP1_STATDEP_1" newline bitfld.long 0x14 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x18 "CM_L4PER3_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x18 13.--31. 1. "RESERVED," rbitfld.long 0x18 12. "CLKACTIVITY_TIMER16_GFCLK,This field indicates the state of the DMT16_GFCLK clock in the domain" "CLKACTIVITY_TIMER16_GFCLK_0,CLKACTIVITY_TIMER16_GFCLK_1" newline rbitfld.long 0x18 11. "CLKACTIVITY_TIMER15_GFCLK,This field indicates the state of the DMT15_GFCLK clock in the domain" "CLKACTIVITY_TIMER15_GFCLK_0,CLKACTIVITY_TIMER15_GFCLK_1" rbitfld.long 0x18 10. "CLKACTIVITY_TIMER14_GFCLK,This field indicates the state of the DMT14_GFCLK clock in the domain" "CLKACTIVITY_TIMER14_GFCLK_0,CLKACTIVITY_TIMER14_GFCLK_1" newline rbitfld.long 0x18 9. "CLKACTIVITY_TIMER13_GFCLK,This field indicates the state of the DMT13_GFCLK clock in the domain" "CLKACTIVITY_TIMER13_GFCLK_0,CLKACTIVITY_TIMER13_GFCLK_1" rbitfld.long 0x18 8. "CLKACTIVITY_L4PER3_L3_GICLK,This field indicates the state of the L4PER2_L3_GICLK clock in the domain" "CLKACTIVITY_L4PER3_L3_GICLK_0,CLKACTIVITY_L4PER3_L3_GICLK_1" newline rbitfld.long 0x18 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4PER clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x1C "CM_L4PER3_DYNAMICDEP,This register controls the dynamic domain depedencies from L4PER3 domain towards 'target' domains" rbitfld.long 0x1C 31. "ISS_DYNDEP,Dynamic dependency towards ISS clock domain" "?,ISS_DYNDEP_1" rbitfld.long 0x1C 28.--30. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x1C 23. "RTC_DYNDEP,Dynamic dependency towards RTC clock domain" "?,RTC_DYNDEP_1" newline hexmask.long.word 0x1C 13.--22. 1. "RESERVED," rbitfld.long 0x1C 12. "L4CFG_DYNDEP,Dynamic dependency towards L4CFG clock domain" "?,L4CFG_DYNDEP_1" newline rbitfld.long 0x1C 10.--11. "RESERVED," "0,1,2,3" rbitfld.long 0x1C 9. "CAM_DYNDEP,Dynamic dependency towards CAM clock domain" "?,CAM_DYNDEP_1" newline rbitfld.long 0x1C 8. "RESERVED," "0,1" rbitfld.long 0x1C 7. "L3INIT_DYNDEP,Dynamic dependency towards L3INIT clock domain" "?,L3INIT_DYNDEP_1" newline rbitfld.long 0x1C 6. "RESERVED," "0,1" rbitfld.long 0x1C 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x1C 4. "RESERVED," "0,1" rbitfld.long 0x1C 3. "IPU_DYNDEP,Dynamic dependency towards IPU clock domain" "?,IPU_DYNDEP_1" newline rbitfld.long 0x1C 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" width 0x0B tree.end tree "L4PER_PRM" base ad:0x4AE07400 group.long 0x00++0x07 line.long 0x00 "PM_L4PER_PWRSTCTRL,This register controls the L4PER power state to reach upon a domain sleep transition" hexmask.long.word 0x00 20.--31. 1. "RESERVED," rbitfld.long 0x00 18.--19. "NONRETAINED_BANK_ONSTATE,NONRETAINED_BANK state when domain is ON" "?,?,?,NONRETAINED_BANK_ONSTATE_3" newline rbitfld.long 0x00 16.--17. "RETAINED_BANK_ONSTATE,RETAINED_BANK state when domain is ON" "?,?,?,RETAINED_BANK_ONSTATE_3" rbitfld.long 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 9. "NONRETAINED_BANK_RETSTATE,NONRETAINED_BANK state when domain is RETENTION" "NONRETAINED_BANK_RETSTATE_0,?" rbitfld.long 0x00 8. "RETAINED_BANK_RETSTATE,RETAINED_BANK state when domain is RETENTION" "?,RETAINED_BANK_RETSTATE_1" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION" "LOGICRETSTATE_0,LOGICRETSTATE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_L4PER_PWRSTST,This register provides a status on the current L4PER power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 8.--19. 1. "RESERVED," rbitfld.long 0x04 6.--7. "NONRETAINED_BANK_STATEST,NONRETAINED_BANK state status" "NONRETAINED_BANK_STATEST_0,NONRETAINED_BANK_STATEST_1,NONRETAINED_BANK_STATEST_2,NONRETAINED_BANK_STATEST_3" newline rbitfld.long 0x04 4.--5. "RETAINED_BANK_STATEST,RETAINED_BANK state status" "RETAINED_BANK_STATEST_0,RETAINED_BANK_STATEST_1,RETAINED_BANK_STATEST_2,RETAINED_BANK_STATEST_3" rbitfld.long 0x04 3. "RESERVED," "0,1" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x0C++0x03 line.long 0x00 "RM_L4PER2_L4PER2_CONTEXT,This register contains dedicated L4_PER2 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x14++0x03 line.long 0x00 "RM_L4PER3_L4PER3_CONTEXT,This register contains dedicated L4_PER3 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x1C++0x03 line.long 0x00 "RM_L4PER2_PRUSS1_CONTEXT,This register contains dedicated PRUSS0 context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_PRUSS1_BANK,Specify if memory-based context in pruss memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_PRUSS1_BANK_0,LOSTMEM_PRUSS1_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x24++0x33 line.long 0x00 "RM_L4PER2_PRUSS2_CONTEXT,This register contains dedicated PRUSS1 context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_PRUSS2_BANK,Specify if memory-based context in pruss memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_PRUSS2_BANK_0,LOSTMEM_PRUSS2_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_L4PER_DCC6_WKDEP,This register controls wakeup dependency based on DCC6 service requests" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "WKUPDEP_DCC6_EVE4,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_EVE4_0,WKUPDEP_DCC6_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_DCC6_EVE3,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_EVE3_0,WKUPDEP_DCC6_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_DCC6_EVE2,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_EVE2_0,WKUPDEP_DCC6_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_DCC6_EVE1,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_EVE1_0,WKUPDEP_DCC6_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_DCC6_DSP2,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_DSP2_0,WKUPDEP_DCC6_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_DCC6_IPU1,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_IPU1_0,WKUPDEP_DCC6_IPU1_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "WKUPDEP_DCC6_DSP1,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_DSP1_0,WKUPDEP_DCC6_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_DCC6_IPU2,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_IPU2_0,WKUPDEP_DCC6_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_DCC6_MPU,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_MPU_0,WKUPDEP_DCC6_MPU_1" line.long 0x08 "RM_L4PER_DCC6_CONTEXT,This register contains dedicated DCC6 context statuses" hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x0C "PM_L4PER_DCC7_WKDEP,This register controls wakeup dependency based on DCC7 service requests" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED," bitfld.long 0x0C 9. "WKUPDEP_DCC7_EVE4,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_EVE4_0,WKUPDEP_DCC7_EVE4_1" newline bitfld.long 0x0C 8. "WKUPDEP_DCC7_EVE3,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_EVE3_0,WKUPDEP_DCC7_EVE3_1" bitfld.long 0x0C 7. "WKUPDEP_DCC7_EVE2,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_EVE2_0,WKUPDEP_DCC7_EVE2_1" newline bitfld.long 0x0C 6. "WKUPDEP_DCC7_EVE1,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_EVE1_0,WKUPDEP_DCC7_EVE1_1" bitfld.long 0x0C 5. "WKUPDEP_DCC7_DSP2,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_DSP2_0,WKUPDEP_DCC7_DSP2_1" newline bitfld.long 0x0C 4. "WKUPDEP_DCC7_IPU1,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_IPU1_0,WKUPDEP_DCC7_IPU1_1" rbitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "WKUPDEP_DCC7_DSP1,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_DSP1_0,WKUPDEP_DCC7_DSP1_1" bitfld.long 0x0C 1. "WKUPDEP_DCC7_IPU2,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_IPU2_0,WKUPDEP_DCC7_IPU2_1" newline bitfld.long 0x0C 0. "WKUPDEP_DCC7_MPU,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_MPU_0,WKUPDEP_DCC7_MPU_1" line.long 0x10 "RM_L4PER_DCC7_CONTEXT,This register contains dedicated DCC7 context statuses" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x14 "PM_L4PER_TIMER2_WKDEP,This register controls wakeup dependency based on TIMER2 service requests" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," bitfld.long 0x14 9. "WKUPDEP_TIMER2_EVE4,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_EVE4_0,WKUPDEP_TIMER2_EVE4_1" newline bitfld.long 0x14 8. "WKUPDEP_TIMER2_EVE3,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_EVE3_0,WKUPDEP_TIMER2_EVE3_1" bitfld.long 0x14 7. "WKUPDEP_TIMER2_EVE2,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_EVE2_0,WKUPDEP_TIMER2_EVE2_1" newline bitfld.long 0x14 6. "WKUPDEP_TIMER2_EVE1,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_EVE1_0,WKUPDEP_TIMER2_EVE1_1" bitfld.long 0x14 5. "WKUPDEP_TIMER2_DSP2,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_DSP2_0,WKUPDEP_TIMER2_DSP2_1" newline bitfld.long 0x14 4. "WKUPDEP_TIMER2_IPU1,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_IPU1_0,WKUPDEP_TIMER2_IPU1_1" rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 2. "WKUPDEP_TIMER2_DSP1,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_DSP1_0,WKUPDEP_TIMER2_DSP1_1" bitfld.long 0x14 1. "WKUPDEP_TIMER2_IPU2,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_IPU2_0,WKUPDEP_TIMER2_IPU2_1" newline bitfld.long 0x14 0. "WKUPDEP_TIMER2_MPU,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_MPU_0,WKUPDEP_TIMER2_MPU_1" line.long 0x18 "RM_L4PER_TIMER2_CONTEXT,This register contains dedicated TIMER2 context statuses" hexmask.long 0x18 1.--31. 1. "RESERVED," bitfld.long 0x18 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x1C "PM_L4PER_TIMER3_WKDEP,This register controls wakeup dependency based on TIMER3 service requests" hexmask.long.tbyte 0x1C 10.--31. 1. "RESERVED," bitfld.long 0x1C 9. "WKUPDEP_TIMER3_EVE4,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_EVE4_0,WKUPDEP_TIMER3_EVE4_1" newline bitfld.long 0x1C 8. "WKUPDEP_TIMER3_EVE3,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_EVE3_0,WKUPDEP_TIMER3_EVE3_1" bitfld.long 0x1C 7. "WKUPDEP_TIMER3_EVE2,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_EVE2_0,WKUPDEP_TIMER3_EVE2_1" newline bitfld.long 0x1C 6. "WKUPDEP_TIMER3_EVE1,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_EVE1_0,WKUPDEP_TIMER3_EVE1_1" bitfld.long 0x1C 5. "WKUPDEP_TIMER3_DSP2,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_DSP2_0,WKUPDEP_TIMER3_DSP2_1" newline bitfld.long 0x1C 4. "WKUPDEP_TIMER3_IPU1,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_IPU1_0,WKUPDEP_TIMER3_IPU1_1" rbitfld.long 0x1C 3. "RESERVED," "0,1" newline bitfld.long 0x1C 2. "WKUPDEP_TIMER3_DSP1,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_DSP1_0,WKUPDEP_TIMER3_DSP1_1" bitfld.long 0x1C 1. "WKUPDEP_TIMER3_IPU2,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_IPU2_0,WKUPDEP_TIMER3_IPU2_1" newline bitfld.long 0x1C 0. "WKUPDEP_TIMER3_MPU,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_MPU_0,WKUPDEP_TIMER3_MPU_1" line.long 0x20 "RM_L4PER_TIMER3_CONTEXT,This register contains dedicated TIMER3 context statuses" hexmask.long 0x20 1.--31. 1. "RESERVED," bitfld.long 0x20 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x24 "PM_L4PER_TIMER4_WKDEP,This register controls wakeup dependency based on TIMER4 service requests" hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED," bitfld.long 0x24 9. "WKUPDEP_TIMER4_EVE4,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_EVE4_0,WKUPDEP_TIMER4_EVE4_1" newline bitfld.long 0x24 8. "WKUPDEP_TIMER4_EVE3,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_EVE3_0,WKUPDEP_TIMER4_EVE3_1" bitfld.long 0x24 7. "WKUPDEP_TIMER4_EVE2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_EVE2_0,WKUPDEP_TIMER4_EVE2_1" newline bitfld.long 0x24 6. "WKUPDEP_TIMER4_EVE1,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_EVE1_0,WKUPDEP_TIMER4_EVE1_1" bitfld.long 0x24 5. "WKUPDEP_TIMER4_DSP2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_DSP2_0,WKUPDEP_TIMER4_DSP2_1" newline bitfld.long 0x24 4. "WKUPDEP_TIMER4_IPU1,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_IPU1_0,WKUPDEP_TIMER4_IPU1_1" rbitfld.long 0x24 3. "RESERVED," "0,1" newline bitfld.long 0x24 2. "WKUPDEP_TIMER4_DSP1,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_DSP1_0,WKUPDEP_TIMER4_DSP1_1" bitfld.long 0x24 1. "WKUPDEP_TIMER4_IPU2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_IPU2_0,WKUPDEP_TIMER4_IPU2_1" newline bitfld.long 0x24 0. "WKUPDEP_TIMER4_MPU,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_MPU_0,WKUPDEP_TIMER4_MPU_1" line.long 0x28 "RM_L4PER_TIMER4_CONTEXT,This register contains dedicated TIMER4 context statuses" hexmask.long 0x28 1.--31. 1. "RESERVED," bitfld.long 0x28 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x2C "PM_L4PER_DCC5_WKDEP,This register controls wakeup dependency based on DCC5 service requests" hexmask.long.tbyte 0x2C 10.--31. 1. "RESERVED," bitfld.long 0x2C 9. "WKUPDEP_DCC5_EVE4,Wakeup dependency from DCC5 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_EVE4_0,WKUPDEP_DCC5_EVE4_1" newline bitfld.long 0x2C 8. "WKUPDEP_DCC5_EVE3,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_EVE3_0,WKUPDEP_DCC5_EVE3_1" bitfld.long 0x2C 7. "WKUPDEP_DCC5_EVE2,Wakeup dependency from DCC5 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_EVE2_0,WKUPDEP_DCC5_EVE2_1" newline bitfld.long 0x2C 6. "WKUPDEP_DCC5_EVE1,Wakeup dependency from DCC5 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_EVE1_0,WKUPDEP_DCC5_EVE1_1" bitfld.long 0x2C 5. "WKUPDEP_DCC5_DSP2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_DSP2_0,WKUPDEP_DCC5_DSP2_1" newline bitfld.long 0x2C 4. "WKUPDEP_DCC5_IPU1,Wakeup dependency from DCC5 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_IPU1_0,WKUPDEP_DCC5_IPU1_1" rbitfld.long 0x2C 3. "RESERVED," "0,1" newline bitfld.long 0x2C 2. "WKUPDEP_DCC5_DSP1,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_DSP1_0,WKUPDEP_DCC5_DSP1_1" bitfld.long 0x2C 1. "WKUPDEP_DCC5_IPU2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_IPU2_0,WKUPDEP_DCC5_IPU2_1" newline bitfld.long 0x2C 0. "WKUPDEP_DCC5_MPU,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_MPU_0,WKUPDEP_DCC5_MPU_1" line.long 0x30 "RM_L4PER_DCC5_CONTEXT,This register contains dedicated DCC5 context statuses" hexmask.long 0x30 1.--31. 1. "RESERVED," bitfld.long 0x30 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x5C++0x2B line.long 0x00 "RM_L4PER_ELM_CONTEXT,This register contains dedicated ELM context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_L4PER_GPIO2_WKDEP,This register controls wakeup dependency based on GPIO2 service requests" hexmask.long.word 0x04 20.--31. 1. "RESERVED," bitfld.long 0x04 19. "WKUPDEP_GPIO2_IRQ2_EVE4,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_EVE4_0,WKUPDEP_GPIO2_IRQ2_EVE4_1" newline bitfld.long 0x04 18. "WKUPDEP_GPIO2_IRQ2_EVE3,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_EVE3_0,WKUPDEP_GPIO2_IRQ2_EVE3_1" bitfld.long 0x04 17. "WKUPDEP_GPIO2_IRQ2_EVE2,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_EVE2_0,WKUPDEP_GPIO2_IRQ2_EVE2_1" newline bitfld.long 0x04 16. "WKUPDEP_GPIO2_IRQ2_EVE1,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_EVE1_0,WKUPDEP_GPIO2_IRQ2_EVE1_1" bitfld.long 0x04 15. "WKUPDEP_GPIO2_IRQ2_DSP2,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_DSP2_0,WKUPDEP_GPIO2_IRQ2_DSP2_1" newline bitfld.long 0x04 14. "WKUPDEP_GPIO2_IRQ2_IPU1,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_IPU1_0,WKUPDEP_GPIO2_IRQ2_IPU1_1" rbitfld.long 0x04 13. "RESERVED," "0,1" newline bitfld.long 0x04 12. "WKUPDEP_GPIO2_IRQ2_DSP1,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_DSP1_0,WKUPDEP_GPIO2_IRQ2_DSP1_1" bitfld.long 0x04 11. "WKUPDEP_GPIO2_IRQ2_IPU2,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_IPU2_0,WKUPDEP_GPIO2_IRQ2_IPU2_1" newline bitfld.long 0x04 10. "WKUPDEP_GPIO2_IRQ2_MPU,Wakeup dependency from GPIO2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_MPU_0,WKUPDEP_GPIO2_IRQ2_MPU_1" bitfld.long 0x04 9. "WKUPDEP_GPIO2_IRQ1_EVE4,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_EVE4_0,WKUPDEP_GPIO2_IRQ1_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_GPIO2_IRQ1_EVE3,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_EVE3_0,WKUPDEP_GPIO2_IRQ1_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_GPIO2_IRQ1_EVE2,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_EVE2_0,WKUPDEP_GPIO2_IRQ1_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_GPIO2_IRQ1_EVE1,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_EVE1_0,WKUPDEP_GPIO2_IRQ1_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_GPIO2_IRQ1_DSP2,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_DSP2_0,WKUPDEP_GPIO2_IRQ1_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_GPIO2_IRQ1_IPU1,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_IPU1_0,WKUPDEP_GPIO2_IRQ1_IPU1_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "WKUPDEP_GPIO2_IRQ1_DSP1,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_DSP1_0,WKUPDEP_GPIO2_IRQ1_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_GPIO2_IRQ1_IPU2,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_IPU2_0,WKUPDEP_GPIO2_IRQ1_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_GPIO2_IRQ1_MPU,Wakeup dependency from GPIO2 module (SWakeup signal for POROCPSINTERRUPT1 ) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_MPU_0,WKUPDEP_GPIO2_IRQ1_MPU_1" line.long 0x08 "RM_L4PER_GPIO2_CONTEXT,This register contains dedicated GPIO2 context statuses" hexmask.long 0x08 2.--31. 1. "RESERVED," bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x08 0. "RESERVED," "0,1" line.long 0x0C "PM_L4PER_GPIO3_WKDEP,This register controls wakeup dependency based on GPIO3 service requests" hexmask.long.word 0x0C 20.--31. 1. "RESERVED," bitfld.long 0x0C 19. "WKUPDEP_GPIO3_IRQ2_EVE4,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_EVE4_0,WKUPDEP_GPIO3_IRQ2_EVE4_1" newline bitfld.long 0x0C 18. "WKUPDEP_GPIO3_IRQ2_EVE3,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_EVE3_0,WKUPDEP_GPIO3_IRQ2_EVE3_1" bitfld.long 0x0C 17. "WKUPDEP_GPIO3_IRQ2_EVE2,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_EVE2_0,WKUPDEP_GPIO3_IRQ2_EVE2_1" newline bitfld.long 0x0C 16. "WKUPDEP_GPIO3_IRQ2_EVE1,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_EVE1_0,WKUPDEP_GPIO3_IRQ2_EVE1_1" bitfld.long 0x0C 15. "WKUPDEP_GPIO3_IRQ2_DSP2,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_DSP2_0,WKUPDEP_GPIO3_IRQ2_DSP2_1" newline bitfld.long 0x0C 14. "WKUPDEP_GPIO3_IRQ2_IPU1,Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_IPU1_0,WKUPDEP_GPIO3_IRQ2_IPU1_1" rbitfld.long 0x0C 13. "RESERVED," "0,1" newline bitfld.long 0x0C 12. "WKUPDEP_GPIO3_IRQ2_DSP1,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_DSP1_0,WKUPDEP_GPIO3_IRQ2_DSP1_1" bitfld.long 0x0C 11. "WKUPDEP_GPIO3_IRQ2_IPU2,Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_IPU2_0,WKUPDEP_GPIO3_IRQ2_IPU2_1" newline bitfld.long 0x0C 10. "WKUPDEP_GPIO3_IRQ2_MPU,Wakeup dependency from GPIO3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_MPU_0,WKUPDEP_GPIO3_IRQ2_MPU_1" bitfld.long 0x0C 9. "WKUPDEP_GPIO3_IRQ1_EVE4,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_EVE4_0,WKUPDEP_GPIO3_IRQ1_EVE4_1" newline bitfld.long 0x0C 8. "WKUPDEP_GPIO3_IRQ1_EVE3,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_EVE3_0,WKUPDEP_GPIO3_IRQ1_EVE3_1" bitfld.long 0x0C 7. "WKUPDEP_GPIO3_IRQ1_EVE2,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_EVE2_0,WKUPDEP_GPIO3_IRQ1_EVE2_1" newline bitfld.long 0x0C 6. "WKUPDEP_GPIO3_IRQ1_EVE1,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_EVE1_0,WKUPDEP_GPIO3_IRQ1_EVE1_1" bitfld.long 0x0C 5. "WKUPDEP_GPIO3_IRQ1_DSP2,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_DSP2_0,WKUPDEP_GPIO3_IRQ1_DSP2_1" newline bitfld.long 0x0C 4. "WKUPDEP_GPIO3_IRQ1_IPU1,Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_IPU1_0,WKUPDEP_GPIO3_IRQ1_IPU1_1" rbitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "WKUPDEP_GPIO3_IRQ1_DSP1,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_DSP1_0,WKUPDEP_GPIO3_IRQ1_DSP1_1" bitfld.long 0x0C 1. "WKUPDEP_GPIO3_IRQ1_IPU2,3Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_IPU2_0,WKUPDEP_GPIO3_IRQ1_IPU2_1" newline bitfld.long 0x0C 0. "WKUPDEP_GPIO3_IRQ1_MPU,Wakeup dependency from GPIO3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_MPU_0,WKUPDEP_GPIO3_IRQ1_MPU_1" line.long 0x10 "RM_L4PER_GPIO3_CONTEXT,This register contains dedicated GPIO3 context statuses" hexmask.long 0x10 2.--31. 1. "RESERVED," bitfld.long 0x10 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x10 0. "RESERVED," "0,1" line.long 0x14 "PM_L4PER_GPIO4_WKDEP,This register controls wakeup dependency based on GPIO4 service requests" hexmask.long.word 0x14 20.--31. 1. "RESERVED," bitfld.long 0x14 19. "WKUPDEP_GPIO4_IRQ2_EVE4,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_EVE4_0,WKUPDEP_GPIO4_IRQ2_EVE4_1" newline bitfld.long 0x14 18. "WKUPDEP_GPIO4_IRQ2_EVE3,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_EVE3_0,WKUPDEP_GPIO4_IRQ2_EVE3_1" bitfld.long 0x14 17. "WKUPDEP_GPIO4_IRQ2_EVE2,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_EVE2_0,WKUPDEP_GPIO4_IRQ2_EVE2_1" newline bitfld.long 0x14 16. "WKUPDEP_GPIO4_IRQ2_EVE1,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_EVE1_0,WKUPDEP_GPIO4_IRQ2_EVE1_1" bitfld.long 0x14 15. "WKUPDEP_GPIO4_IRQ2_DSP2,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_DSP2_0,WKUPDEP_GPIO4_IRQ2_DSP2_1" newline bitfld.long 0x14 14. "WKUPDEP_GPIO4_IRQ2_IPU1,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_IPU1_0,WKUPDEP_GPIO4_IRQ2_IPU1_1" rbitfld.long 0x14 13. "RESERVED," "0,1" newline bitfld.long 0x14 12. "WKUPDEP_GPIO4_IRQ2_DSP1,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_DSP1_0,WKUPDEP_GPIO4_IRQ2_DSP1_1" bitfld.long 0x14 11. "WKUPDEP_GPIO4_IRQ2_IPU2,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_IPU2_0,WKUPDEP_GPIO4_IRQ2_IPU2_1" newline bitfld.long 0x14 10. "WKUPDEP_GPIO4_IRQ2_MPU,Wakeup dependency from GPIO4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_MPU_0,WKUPDEP_GPIO4_IRQ2_MPU_1" bitfld.long 0x14 9. "WKUPDEP_GPIO4_IRQ1_EVE4,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_EVE4_0,WKUPDEP_GPIO4_IRQ1_EVE4_1" newline bitfld.long 0x14 8. "WKUPDEP_GPIO4_IRQ1_EVE3,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_EVE3_0,WKUPDEP_GPIO4_IRQ1_EVE3_1" bitfld.long 0x14 7. "WKUPDEP_GPIO4_IRQ1_EVE2,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_EVE2_0,WKUPDEP_GPIO4_IRQ1_EVE2_1" newline bitfld.long 0x14 6. "WKUPDEP_GPIO4_IRQ1_EVE1,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_EVE1_0,WKUPDEP_GPIO4_IRQ1_EVE1_1" bitfld.long 0x14 5. "WKUPDEP_GPIO4_IRQ1_DSP2,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_DSP2_0,WKUPDEP_GPIO4_IRQ1_DSP2_1" newline bitfld.long 0x14 4. "WKUPDEP_GPIO4_IRQ1_IPU1,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_IPU1_0,WKUPDEP_GPIO4_IRQ1_IPU1_1" rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 2. "WKUPDEP_GPIO4_IRQ1_DSP1,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_DSP1_0,WKUPDEP_GPIO4_IRQ1_DSP1_1" bitfld.long 0x14 1. "WKUPDEP_GPIO4_IRQ1_IPU2,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_IPU2_0,WKUPDEP_GPIO4_IRQ1_IPU2_1" newline bitfld.long 0x14 0. "WKUPDEP_GPIO4_IRQ1_MPU,Wakeup dependency from GPIO4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_MPU_0,WKUPDEP_GPIO4_IRQ1_MPU_1" line.long 0x18 "RM_L4PER_GPIO4_CONTEXT,This register contains dedicated GPIO4 context statuses" hexmask.long 0x18 2.--31. 1. "RESERVED," bitfld.long 0x18 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x18 0. "RESERVED," "0,1" line.long 0x1C "PM_L4PER_GPIO5_WKDEP,This register controls wakeup dependency based on GPIO5 service requests" hexmask.long.word 0x1C 20.--31. 1. "RESERVED," bitfld.long 0x1C 19. "WKUPDEP_GPIO5_IRQ2_EVE4,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_EVE4_0,WKUPDEP_GPIO5_IRQ2_EVE4_1" newline bitfld.long 0x1C 18. "WKUPDEP_GPIO5_IRQ2_EVE3,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_EVE3_0,WKUPDEP_GPIO5_IRQ2_EVE3_1" bitfld.long 0x1C 17. "WKUPDEP_GPIO5_IRQ2_EVE2,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_EVE2_0,WKUPDEP_GPIO5_IRQ2_EVE2_1" newline bitfld.long 0x1C 16. "WKUPDEP_GPIO5_IRQ2_EVE1,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_EVE1_0,WKUPDEP_GPIO5_IRQ2_EVE1_1" bitfld.long 0x1C 15. "WKUPDEP_GPIO5_IRQ2_DSP2,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_DSP2_0,WKUPDEP_GPIO5_IRQ2_DSP2_1" newline bitfld.long 0x1C 14. "WKUPDEP_GPIO5_IRQ2_IPU1,Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_IPU1_0,WKUPDEP_GPIO5_IRQ2_IPU1_1" rbitfld.long 0x1C 13. "RESERVED," "0,1" newline bitfld.long 0x1C 12. "WKUPDEP_GPIO5_IRQ2_DSP1,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_DSP1_0,WKUPDEP_GPIO5_IRQ2_DSP1_1" bitfld.long 0x1C 11. "WKUPDEP_GPIO5_IRQ2_IPU2,Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_IPU2_0,WKUPDEP_GPIO5_IRQ2_IPU2_1" newline bitfld.long 0x1C 10. "WKUPDEP_GPIO5_IRQ2_MPU,Wakeup dependency from GPIO5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_MPU_0,WKUPDEP_GPIO5_IRQ2_MPU_1" bitfld.long 0x1C 9. "WKUPDEP_GPIO5_IRQ1_EVE4,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_EVE4_0,WKUPDEP_GPIO5_IRQ1_EVE4_1" newline bitfld.long 0x1C 8. "WKUPDEP_GPIO5_IRQ1_EVE3,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_EVE3_0,WKUPDEP_GPIO5_IRQ1_EVE3_1" bitfld.long 0x1C 7. "WKUPDEP_GPIO5_IRQ1_EVE2,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_EVE2_0,WKUPDEP_GPIO5_IRQ1_EVE2_1" newline bitfld.long 0x1C 6. "WKUPDEP_GPIO5_IRQ1_EVE1,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_EVE1_0,WKUPDEP_GPIO5_IRQ1_EVE1_1" bitfld.long 0x1C 5. "WKUPDEP_GPIO5_IRQ1_DSP2,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_DSP2_0,WKUPDEP_GPIO5_IRQ1_DSP2_1" newline bitfld.long 0x1C 4. "WKUPDEP_GPIO5_IRQ1_IPU1,Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_IPU1_0,WKUPDEP_GPIO5_IRQ1_IPU1_1" rbitfld.long 0x1C 3. "RESERVED," "0,1" newline bitfld.long 0x1C 2. "WKUPDEP_GPIO5_IRQ1_DSP1,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_DSP1_0,WKUPDEP_GPIO5_IRQ1_DSP1_1" bitfld.long 0x1C 1. "WKUPDEP_GPIO5_IRQ1_IPU2,5Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_IPU2_0,WKUPDEP_GPIO5_IRQ1_IPU2_1" newline bitfld.long 0x1C 0. "WKUPDEP_GPIO5_IRQ1_MPU,Wakeup dependency from GPIO5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_MPU_0,WKUPDEP_GPIO5_IRQ1_MPU_1" line.long 0x20 "RM_L4PER_GPIO5_CONTEXT,This register contains dedicated GPIO5 context statuses" hexmask.long 0x20 2.--31. 1. "RESERVED," bitfld.long 0x20 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x20 0. "RESERVED," "0,1" line.long 0x24 "PM_L4PER_GPIO6_WKDEP,This register controls wakeup dependency based on GPIO6 service requests" hexmask.long.word 0x24 20.--31. 1. "RESERVED," bitfld.long 0x24 19. "WKUPDEP_GPIO6_IRQ2_EVE4,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_EVE4_0,WKUPDEP_GPIO6_IRQ2_EVE4_1" newline bitfld.long 0x24 18. "WKUPDEP_GPIO6_IRQ2_EVE3,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_EVE3_0,WKUPDEP_GPIO6_IRQ2_EVE3_1" bitfld.long 0x24 17. "WKUPDEP_GPIO6_IRQ2_EVE2,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_EVE2_0,WKUPDEP_GPIO6_IRQ2_EVE2_1" newline bitfld.long 0x24 16. "WKUPDEP_GPIO6_IRQ2_EVE1,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_EVE1_0,WKUPDEP_GPIO6_IRQ2_EVE1_1" bitfld.long 0x24 15. "WKUPDEP_GPIO6_IRQ2_DSP2,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_DSP2_0,WKUPDEP_GPIO6_IRQ2_DSP2_1" newline bitfld.long 0x24 14. "WKUPDEP_GPIO6_IRQ2_IPU1,Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_IPU1_0,WKUPDEP_GPIO6_IRQ2_IPU1_1" rbitfld.long 0x24 13. "RESERVED," "0,1" newline bitfld.long 0x24 12. "WKUPDEP_GPIO6_IRQ2_DSP1,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_DSP1_0,WKUPDEP_GPIO6_IRQ2_DSP1_1" bitfld.long 0x24 11. "WKUPDEP_GPIO6_IRQ2_IPU2,Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_IPU2_0,WKUPDEP_GPIO6_IRQ2_IPU2_1" newline bitfld.long 0x24 10. "WKUPDEP_GPIO6_IRQ2_MPU,Wakeup dependency from GPIO6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_MPU_0,WKUPDEP_GPIO6_IRQ2_MPU_1" bitfld.long 0x24 9. "WKUPDEP_GPIO6_IRQ1_EVE4,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_EVE4_0,WKUPDEP_GPIO6_IRQ1_EVE4_1" newline bitfld.long 0x24 8. "WKUPDEP_GPIO6_IRQ1_EVE3,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_EVE3_0,WKUPDEP_GPIO6_IRQ1_EVE3_1" bitfld.long 0x24 7. "WKUPDEP_GPIO6_IRQ1_EVE2,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_EVE2_0,WKUPDEP_GPIO6_IRQ1_EVE2_1" newline bitfld.long 0x24 6. "WKUPDEP_GPIO6_IRQ1_EVE1,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_EVE1_0,WKUPDEP_GPIO6_IRQ1_EVE1_1" bitfld.long 0x24 5. "WKUPDEP_GPIO6_IRQ1_DSP2,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_DSP2_0,WKUPDEP_GPIO6_IRQ1_DSP2_1" newline bitfld.long 0x24 4. "WKUPDEP_GPIO6_IRQ1_IPU1,Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_IPU1_0,WKUPDEP_GPIO6_IRQ1_IPU1_1" rbitfld.long 0x24 3. "RESERVED," "0,1" newline bitfld.long 0x24 2. "WKUPDEP_GPIO6_IRQ1_DSP1,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_DSP1_0,WKUPDEP_GPIO6_IRQ1_DSP1_1" bitfld.long 0x24 1. "WKUPDEP_GPIO6_IRQ1_IPU2,5Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_IPU2_0,WKUPDEP_GPIO6_IRQ1_IPU2_1" newline bitfld.long 0x24 0. "WKUPDEP_GPIO6_IRQ1_MPU,Wakeup dependency from GPIO6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_MPU_0,WKUPDEP_GPIO6_IRQ1_MPU_1" line.long 0x28 "RM_L4PER_GPIO6_CONTEXT,This register contains dedicated GPIO6 context statuses" hexmask.long 0x28 2.--31. 1. "RESERVED," bitfld.long 0x28 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x28 0. "RESERVED," "0,1" group.long 0x8C++0x03 line.long 0x00 "RM_L4PER_ESM_CONTEXT,This register contains dedicated ESM context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x94++0x03 line.long 0x00 "RM_L4PER2_PWMSS2_CONTEXT,This register contains dedicated PWMSS2 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x9C++0x43 line.long 0x00 "RM_L4PER2_PWMSS3_CONTEXT,This register contains dedicated PWMSS3 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_L4PER_I2C1_WKDEP,This register controls wakeup dependency based on I2C1 service requests" hexmask.long.word 0x04 16.--31. 1. "RESERVED," bitfld.long 0x04 15. "WKUPDEP_I2C1_DMA_DSP2,Wakeup dependency from I2C1 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_DMA_DSP2_0,WKUPDEP_I2C1_DMA_DSP2_1" newline rbitfld.long 0x04 14. "RESERVED," "0,1" bitfld.long 0x04 13. "WKUPDEP_I2C1_DMA_SDMA,Wakeup dependency from I2C1 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_DMA_SDMA_0,WKUPDEP_I2C1_DMA_SDMA_1" newline bitfld.long 0x04 12. "WKUPDEP_I2C1_DMA_DSP1,Wakeup dependency from I2C1 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_DMA_DSP1_0,WKUPDEP_I2C1_DMA_DSP1_1" rbitfld.long 0x04 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 9. "WKUPDEP_I2C1_IRQ_EVE4,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_EVE4_0,WKUPDEP_I2C1_IRQ_EVE4_1" bitfld.long 0x04 8. "WKUPDEP_I2C1_IRQ_EVE3,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_EVE3_0,WKUPDEP_I2C1_IRQ_EVE3_1" newline bitfld.long 0x04 7. "WKUPDEP_I2C1_IRQ_EVE2,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_EVE2_0,WKUPDEP_I2C1_IRQ_EVE2_1" bitfld.long 0x04 6. "WKUPDEP_I2C1_IRQ_EVE1,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_EVE1_0,WKUPDEP_I2C1_IRQ_EVE1_1" newline bitfld.long 0x04 5. "WKUPDEP_I2C1_IRQ_DSP2,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_DSP2_0,WKUPDEP_I2C1_IRQ_DSP2_1" bitfld.long 0x04 4. "WKUPDEP_I2C1_IRQ_IPU1,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_IPU1_0,WKUPDEP_I2C1_IRQ_IPU1_1" newline rbitfld.long 0x04 3. "RESERVED," "0,1" bitfld.long 0x04 2. "WKUPDEP_I2C1_IRQ_DSP1,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_DSP1_0,WKUPDEP_I2C1_IRQ_DSP1_1" newline bitfld.long 0x04 1. "WKUPDEP_I2C1_IRQ_IPU2,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_IPU2_0,WKUPDEP_I2C1_IRQ_IPU2_1" bitfld.long 0x04 0. "WKUPDEP_I2C1_IRQ_MPU,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_MPU_0,WKUPDEP_I2C1_IRQ_MPU_1" line.long 0x08 "RM_L4PER_I2C1_CONTEXT,This register contains dedicated I2C1 context statuses" hexmask.long 0x08 2.--31. 1. "RESERVED," bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x08 0. "RESERVED," "0,1" line.long 0x0C "PM_L4PER_I2C2_WKDEP,This register controls wakeup dependency based on I2C2 service requests" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," bitfld.long 0x0C 15. "WKUPDEP_I2C2_DMA_DSP2,Wakeup dependency from I2C2 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_DMA_DSP2_0,WKUPDEP_I2C2_DMA_DSP2_1" newline rbitfld.long 0x0C 14. "RESERVED," "0,1" bitfld.long 0x0C 13. "WKUPDEP_I2C2_DMA_SDMA,Wakeup dependency from I2C2 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_DMA_SDMA_0,WKUPDEP_I2C2_DMA_SDMA_1" newline bitfld.long 0x0C 12. "WKUPDEP_I2C2_DMA_DSP1,Wakeup dependency from I2C2 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_DMA_DSP1_0,WKUPDEP_I2C2_DMA_DSP1_1" rbitfld.long 0x0C 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 9. "WKUPDEP_I2C2_IRQ_EVE4,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_EVE4_0,WKUPDEP_I2C2_IRQ_EVE4_1" bitfld.long 0x0C 8. "WKUPDEP_I2C2_IRQ_EVE3,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_EVE3_0,WKUPDEP_I2C2_IRQ_EVE3_1" newline bitfld.long 0x0C 7. "WKUPDEP_I2C2_IRQ_EVE2,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_EVE2_0,WKUPDEP_I2C2_IRQ_EVE2_1" bitfld.long 0x0C 6. "WKUPDEP_I2C2_IRQ_EVE1,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_EVE1_0,WKUPDEP_I2C2_IRQ_EVE1_1" newline bitfld.long 0x0C 5. "WKUPDEP_I2C2_IRQ_DSP2,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_DSP2_0,WKUPDEP_I2C2_IRQ_DSP2_1" bitfld.long 0x0C 4. "WKUPDEP_I2C2_IRQ_IPU1,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_IPU1_0,WKUPDEP_I2C2_IRQ_IPU1_1" newline rbitfld.long 0x0C 3. "RESERVED," "0,1" bitfld.long 0x0C 2. "WKUPDEP_I2C2_IRQ_DSP1,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_DSP1_0,WKUPDEP_I2C2_IRQ_DSP1_1" newline bitfld.long 0x0C 1. "WKUPDEP_I2C2_IRQ_IPU2,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_IPU2_0,WKUPDEP_I2C2_IRQ_IPU2_1" bitfld.long 0x0C 0. "WKUPDEP_I2C2_IRQ_MPU,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_MPU_0,WKUPDEP_I2C2_IRQ_MPU_1" line.long 0x10 "RM_L4PER_I2C2_CONTEXT,This register contains dedicated I2C2 context statuses" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x14 "PM_L4PER_I2C3_WKDEP,This register controls wakeup dependency based on I2C3 service requests" hexmask.long.word 0x14 16.--31. 1. "RESERVED," bitfld.long 0x14 15. "WKUPDEP_I2C3_DMA_DSP2,Wakeup dependency from I2C3 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_DMA_DSP2_0,WKUPDEP_I2C3_DMA_DSP2_1" newline rbitfld.long 0x14 14. "RESERVED," "0,1" bitfld.long 0x14 13. "WKUPDEP_I2C3_DMA_SDMA,Wakeup dependency from I2C3 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_DMA_SDMA_0,WKUPDEP_I2C3_DMA_SDMA_1" newline bitfld.long 0x14 12. "WKUPDEP_I2C3_DMA_DSP1,Wakeup dependency from I2C3 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_DMA_DSP1_0,WKUPDEP_I2C3_DMA_DSP1_1" rbitfld.long 0x14 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 9. "WKUPDEP_I2C3_IRQ_EVE4,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_EVE4_0,WKUPDEP_I2C3_IRQ_EVE4_1" bitfld.long 0x14 8. "WKUPDEP_I2C3_IRQ_EVE3,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_EVE3_0,WKUPDEP_I2C3_IRQ_EVE3_1" newline bitfld.long 0x14 7. "WKUPDEP_I2C3_IRQ_EVE2,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_EVE2_0,WKUPDEP_I2C3_IRQ_EVE2_1" bitfld.long 0x14 6. "WKUPDEP_I2C3_IRQ_EVE1,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_EVE1_0,WKUPDEP_I2C3_IRQ_EVE1_1" newline bitfld.long 0x14 5. "WKUPDEP_I2C3_IRQ_DSP2,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_DSP2_0,WKUPDEP_I2C3_IRQ_DSP2_1" bitfld.long 0x14 4. "WKUPDEP_I2C3_IRQ_IPU1,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_IPU1_0,WKUPDEP_I2C3_IRQ_IPU1_1" newline rbitfld.long 0x14 3. "RESERVED," "0,1" bitfld.long 0x14 2. "WKUPDEP_I2C3_IRQ_DSP1,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_DSP1_0,WKUPDEP_I2C3_IRQ_DSP1_1" newline bitfld.long 0x14 1. "WKUPDEP_I2C3_IRQ_IPU2,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_IPU2_0,WKUPDEP_I2C3_IRQ_IPU2_1" bitfld.long 0x14 0. "WKUPDEP_I2C3_IRQ_MPU,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_MPU_0,WKUPDEP_I2C3_IRQ_MPU_1" line.long 0x18 "RM_L4PER_I2C3_CONTEXT,This register contains dedicated I2C3 context statuses" hexmask.long 0x18 1.--31. 1. "RESERVED," bitfld.long 0x18 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x1C "PM_L4PER_I2C4_WKDEP,This register controls wakeup dependency based on I2C4 service requests" hexmask.long.word 0x1C 16.--31. 1. "RESERVED," bitfld.long 0x1C 15. "WKUPDEP_I2C4_DMA_DSP2,Wakeup dependency from I2C4 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_DMA_DSP2_0,WKUPDEP_I2C4_DMA_DSP2_1" newline rbitfld.long 0x1C 14. "RESERVED," "0,1" bitfld.long 0x1C 13. "WKUPDEP_I2C4_DMA_SDMA,Wakeup dependency from I2C4 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_DMA_SDMA_0,WKUPDEP_I2C4_DMA_SDMA_1" newline bitfld.long 0x1C 12. "WKUPDEP_I2C4_DMA_DSP1,Wakeup dependency from I2C4 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_DMA_DSP1_0,WKUPDEP_I2C4_DMA_DSP1_1" rbitfld.long 0x1C 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x1C 9. "WKUPDEP_I2C4_IRQ_EVE4,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_EVE4_0,WKUPDEP_I2C4_IRQ_EVE4_1" bitfld.long 0x1C 8. "WKUPDEP_I2C4_IRQ_EVE3,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_EVE3_0,WKUPDEP_I2C4_IRQ_EVE3_1" newline bitfld.long 0x1C 7. "WKUPDEP_I2C4_IRQ_EVE2,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_EVE2_0,WKUPDEP_I2C4_IRQ_EVE2_1" bitfld.long 0x1C 6. "WKUPDEP_I2C4_IRQ_EVE1,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_EVE1_0,WKUPDEP_I2C4_IRQ_EVE1_1" newline bitfld.long 0x1C 5. "WKUPDEP_I2C4_IRQ_DSP2,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_DSP2_0,WKUPDEP_I2C4_IRQ_DSP2_1" bitfld.long 0x1C 4. "WKUPDEP_I2C4_IRQ_IPU1,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_IPU1_0,WKUPDEP_I2C4_IRQ_IPU1_1" newline rbitfld.long 0x1C 3. "RESERVED," "0,1" bitfld.long 0x1C 2. "WKUPDEP_I2C4_IRQ_DSP1,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_DSP1_0,WKUPDEP_I2C4_IRQ_DSP1_1" newline bitfld.long 0x1C 1. "WKUPDEP_I2C4_IRQ_IPU2,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_IPU2_0,WKUPDEP_I2C4_IRQ_IPU2_1" bitfld.long 0x1C 0. "WKUPDEP_I2C4_IRQ_MPU,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_MPU_0,WKUPDEP_I2C4_IRQ_MPU_1" line.long 0x20 "RM_L4PER_I2C4_CONTEXT,This register contains dedicated I2C4 context statuses" hexmask.long 0x20 1.--31. 1. "RESERVED," bitfld.long 0x20 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x24 "RM_L4PER_L4PER1_CONTEXT,This register contains dedicated L4_PER1 context statuses" hexmask.long 0x24 2.--31. 1. "RESERVED," bitfld.long 0x24 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x24 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x28 "RM_L4PER2_PWMSS1_CONTEXT,This register contains dedicated PWMSS1 context statuses" hexmask.long 0x28 1.--31. 1. "RESERVED," bitfld.long 0x28 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x2C "PM_L4PER_DCC1_WKDEP,This register controls wakeup dependency based on DCC1 service requests" hexmask.long.tbyte 0x2C 10.--31. 1. "RESERVED," bitfld.long 0x2C 9. "WKUPDEP_DCC1_EVE4,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_EVE4_0,WKUPDEP_DCC1_EVE4_1" newline bitfld.long 0x2C 8. "WKUPDEP_DCC1_EVE3,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_EVE3_0,WKUPDEP_DCC1_EVE3_1" bitfld.long 0x2C 7. "WKUPDEP_DCC1_EVE2,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_EVE2_0,WKUPDEP_DCC1_EVE2_1" newline bitfld.long 0x2C 6. "WKUPDEP_DCC1_EVE1,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_EVE1_0,WKUPDEP_DCC1_EVE1_1" bitfld.long 0x2C 5. "WKUPDEP_DCC1_DSP2,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_DSP2_0,WKUPDEP_DCC1_DSP2_1" newline bitfld.long 0x2C 4. "WKUPDEP_DCC1_IPU1,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_IPU1_0,WKUPDEP_DCC1_IPU1_1" rbitfld.long 0x2C 3. "RESERVED," "0,1" newline bitfld.long 0x2C 2. "WKUPDEP_DCC1_DSP1,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_DSP1_0,WKUPDEP_DCC1_DSP1_1" bitfld.long 0x2C 1. "WKUPDEP_DCC1_IPU2,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_IPU2_0,WKUPDEP_DCC1_IPU2_1" newline bitfld.long 0x2C 0. "WKUPDEP_DCC1_MPU,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_MPU_0,WKUPDEP_DCC1_MPU_1" line.long 0x30 "RM_L4PER3_DCC1_CONTEXT,This register contains dedicated DCC1 context statuses" hexmask.long 0x30 1.--31. 1. "RESERVED," bitfld.long 0x30 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x34 "PM_L4PER_DCC2_WKDEP,This register controls wakeup dependency based on DCC2 service requests" hexmask.long.tbyte 0x34 10.--31. 1. "RESERVED," bitfld.long 0x34 9. "WKUPDEP_DCC2_EVE4,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_EVE4_0,WKUPDEP_DCC2_EVE4_1" newline bitfld.long 0x34 8. "WKUPDEP_DCC2_EVE3,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_EVE3_0,WKUPDEP_DCC2_EVE3_1" bitfld.long 0x34 7. "WKUPDEP_DCC2_EVE2,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_EVE2_0,WKUPDEP_DCC2_EVE2_1" newline bitfld.long 0x34 6. "WKUPDEP_DCC2_EVE1,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_EVE1_0,WKUPDEP_DCC2_EVE1_1" bitfld.long 0x34 5. "WKUPDEP_DCC2_DSP2,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_DSP2_0,WKUPDEP_DCC2_DSP2_1" newline bitfld.long 0x34 4. "WKUPDEP_DCC2_IPU1,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_IPU1_0,WKUPDEP_DCC2_IPU1_1" rbitfld.long 0x34 3. "RESERVED," "0,1" newline bitfld.long 0x34 2. "WKUPDEP_DCC2_DSP1,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_DSP1_0,WKUPDEP_DCC2_DSP1_1" bitfld.long 0x34 1. "WKUPDEP_DCC2_IPU2,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_IPU2_0,WKUPDEP_DCC2_IPU2_1" newline bitfld.long 0x34 0. "WKUPDEP_DCC2_MPU,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_MPU_0,WKUPDEP_DCC2_MPU_1" line.long 0x38 "RM_L4PER3_DCC2_CONTEXT,This register contains dedicated DCC2 context statuses" hexmask.long 0x38 1.--31. 1. "RESERVED," bitfld.long 0x38 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x3C "PM_L4PER_DCC3_WKDEP,This register controls wakeup dependency based on DCC3 service requests" hexmask.long.tbyte 0x3C 10.--31. 1. "RESERVED," bitfld.long 0x3C 9. "WKUPDEP_DCC3_EVE4,5Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_EVE4_0,WKUPDEP_DCC3_EVE4_1" newline bitfld.long 0x3C 8. "WKUPDEP_DCC3_EVE3,Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_EVE3_0,WKUPDEP_DCC3_EVE3_1" bitfld.long 0x3C 7. "WKUPDEP_DCC3_EVE2,Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_EVE2_0,WKUPDEP_DCC3_EVE2_1" newline bitfld.long 0x3C 6. "WKUPDEP_DCC3_EVE1,Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_EVE1_0,WKUPDEP_DCC3_EVE1_1" bitfld.long 0x3C 5. "WKUPDEP_DCC3_DSP2,Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_DSP2_0,WKUPDEP_DCC3_DSP2_1" newline bitfld.long 0x3C 4. "WKUPDEP_DCC3_IPU1,Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_IPU1_0,WKUPDEP_DCC3_IPU1_1" rbitfld.long 0x3C 3. "RESERVED," "0,1" newline bitfld.long 0x3C 2. "WKUPDEP_DCC3_DSP1,Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_DSP1_0,WKUPDEP_DCC3_DSP1_1" bitfld.long 0x3C 1. "WKUPDEP_DCC3_IPU2,Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_IPU2_0,WKUPDEP_DCC3_IPU2_1" newline bitfld.long 0x3C 0. "WKUPDEP_DCC3_MPU,Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_MPU_0,WKUPDEP_DCC3_MPU_1" line.long 0x40 "RM_L4PER3_DCC3_CONTEXT,This register contains dedicated DCC3 context statuses" hexmask.long 0x40 1.--31. 1. "RESERVED," bitfld.long 0x40 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xF0++0xAF line.long 0x00 "PM_L4PER_MCSPI1_WKDEP,This register controls wakeup dependency based on MCSPI1 service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_MCSPI1_EVE4,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_EVE4_0,WKUPDEP_MCSPI1_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_MCSPI1_EVE3,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_EVE3_0,WKUPDEP_MCSPI1_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_MCSPI1_EVE2,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_EVE2_0,WKUPDEP_MCSPI1_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_MCSPI1_EVE1,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_EVE1_0,WKUPDEP_MCSPI1_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_MCSPI1_DSP2,Wakeup dependency from MCSPI1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_DSP2_0,WKUPDEP_MCSPI1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_MCSPI1_IPU1,Wakeup dependency from MCSPI1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_IPU1_0,WKUPDEP_MCSPI1_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_MCSPI1_SDMA,Wakeup dependency from MCSPI1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_SDMA_0,WKUPDEP_MCSPI1_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_MCSPI1_DSP1,Wakeup dependency from MCSPI1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_DSP1_0,WKUPDEP_MCSPI1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_MCSPI1_IPU2,Wakeup dependency from MCSPI1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_IPU2_0,WKUPDEP_MCSPI1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_MCSPI1_MPU,Wakeup dependency from MCSPI1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_MPU_0,WKUPDEP_MCSPI1_MPU_1" line.long 0x04 "RM_L4PER_MCSPI1_CONTEXT,This register contains dedicated MCSPI1 context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_L4PER_MCSPI2_WKDEP,This register controls wakeup dependency based on MCSPI2 service requests" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "WKUPDEP_MCSPI2_EVE4,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_EVE4_0,WKUPDEP_MCSPI2_EVE4_1" newline bitfld.long 0x08 8. "WKUPDEP_MCSPI2_EVE3,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_EVE3_0,WKUPDEP_MCSPI2_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_MCSPI2_EVE2,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_EVE2_0,WKUPDEP_MCSPI2_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_MCSPI2_EVE1,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_EVE1_0,WKUPDEP_MCSPI2_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_MCSPI2_DSP2,Wakeup dependency from MCSPI2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_DSP2_0,WKUPDEP_MCSPI2_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_MCSPI2_IPU1,Wakeup dependency from MCSPI2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_IPU1_0,WKUPDEP_MCSPI2_IPU1_1" bitfld.long 0x08 3. "WKUPDEP_MCSPI2_SDMA,Wakeup dependency from MCSPI2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_SDMA_0,WKUPDEP_MCSPI2_SDMA_1" newline bitfld.long 0x08 2. "WKUPDEP_MCSPI2_DSP1,Wakeup dependency from MCSPI2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_DSP1_0,WKUPDEP_MCSPI2_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_MCSPI2_IPU2,Wakeup dependency from MCSPI2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_IPU2_0,WKUPDEP_MCSPI2_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_MCSPI2_MPU,Wakeup dependency from MCSPI2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_MPU_0,WKUPDEP_MCSPI2_MPU_1" line.long 0x0C "RM_L4PER_MCSPI2_CONTEXT,This register contains dedicated MCSPI2 context statuses" hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_L4PER_MCSPI3_WKDEP,This register controls wakeup dependency based on MCSPI3 service requests" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED," bitfld.long 0x10 9. "WKUPDEP_MCSPI3_EVE4,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_EVE4_0,WKUPDEP_MCSPI3_EVE4_1" newline bitfld.long 0x10 8. "WKUPDEP_MCSPI3_EVE3,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_EVE3_0,WKUPDEP_MCSPI3_EVE3_1" bitfld.long 0x10 7. "WKUPDEP_MCSPI3_EVE2,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_EVE2_0,WKUPDEP_MCSPI3_EVE2_1" newline bitfld.long 0x10 6. "WKUPDEP_MCSPI3_EVE1,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_EVE1_0,WKUPDEP_MCSPI3_EVE1_1" bitfld.long 0x10 5. "WKUPDEP_MCSPI3_DSP2,Wakeup dependency from MCSPI3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_DSP2_0,WKUPDEP_MCSPI3_DSP2_1" newline bitfld.long 0x10 4. "WKUPDEP_MCSPI3_IPU1,Wakeup dependency from MCSPI3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_IPU1_0,WKUPDEP_MCSPI3_IPU1_1" bitfld.long 0x10 3. "WKUPDEP_MCSPI3_SDMA,Wakeup dependency from MCSPI3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_SDMA_0,WKUPDEP_MCSPI3_SDMA_1" newline bitfld.long 0x10 2. "WKUPDEP_MCSPI3_DSP1,Wakeup dependency from MCSPI3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_DSP1_0,WKUPDEP_MCSPI3_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_MCSPI3_IPU2,Wakeup dependency from MCSPI3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_IPU2_0,WKUPDEP_MCSPI3_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_MCSPI3_MPU,Wakeup dependency from MCSPI3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_MPU_0,WKUPDEP_MCSPI3_MPU_1" line.long 0x14 "RM_L4PER_MCSPI3_CONTEXT,This register contains dedicated MCSPI3 context statuses" hexmask.long 0x14 1.--31. 1. "RESERVED," bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x18 "PM_L4PER_MCSPI4_WKDEP,This register controls wakeup dependency based on MCSPI4 service requests" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," bitfld.long 0x18 9. "WKUPDEP_MCSPI4_EVE4,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_EVE4_0,WKUPDEP_MCSPI4_EVE4_1" newline bitfld.long 0x18 8. "WKUPDEP_MCSPI4_EVE3,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_EVE3_0,WKUPDEP_MCSPI4_EVE3_1" bitfld.long 0x18 7. "WKUPDEP_MCSPI4_EVE2,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_EVE2_0,WKUPDEP_MCSPI4_EVE2_1" newline bitfld.long 0x18 6. "WKUPDEP_MCSPI4_EVE1,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_EVE1_0,WKUPDEP_MCSPI4_EVE1_1" bitfld.long 0x18 5. "WKUPDEP_MCSPI4_DSP2,Wakeup dependency from MCSPI4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_DSP2_0,WKUPDEP_MCSPI4_DSP2_1" newline bitfld.long 0x18 4. "WKUPDEP_MCSPI4_IPU1,Wakeup dependency from MCSPI4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_IPU1_0,WKUPDEP_MCSPI4_IPU1_1" bitfld.long 0x18 3. "WKUPDEP_MCSPI4_SDMA,Wakeup dependency from MCSPI4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_SDMA_0,WKUPDEP_MCSPI4_SDMA_1" newline bitfld.long 0x18 2. "WKUPDEP_MCSPI4_DSP1,Wakeup dependency from MCSPI4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_DSP1_0,WKUPDEP_MCSPI4_DSP1_1" bitfld.long 0x18 1. "WKUPDEP_MCSPI4_IPU2,Wakeup dependency from MCSPI4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_IPU2_0,WKUPDEP_MCSPI4_IPU2_1" newline bitfld.long 0x18 0. "WKUPDEP_MCSPI4_MPU,Wakeup dependency from MCSPI4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_MPU_0,WKUPDEP_MCSPI4_MPU_1" line.long 0x1C "RM_L4PER_MCSPI4_CONTEXT,This register contains dedicated MCSPI4 context statuses" hexmask.long 0x1C 1.--31. 1. "RESERVED," bitfld.long 0x1C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x20 "PM_L4PER_GPIO7_WKDEP,This register controls wakeup dependency based on GPIO7 service requests" hexmask.long.word 0x20 20.--31. 1. "RESERVED," bitfld.long 0x20 19. "WKUPDEP_GPIO7_IRQ2_EVE4,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_EVE4_0,WKUPDEP_GPIO7_IRQ2_EVE4_1" newline bitfld.long 0x20 18. "WKUPDEP_GPIO7_IRQ2_EVE3,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_EVE3_0,WKUPDEP_GPIO7_IRQ2_EVE3_1" bitfld.long 0x20 17. "WKUPDEP_GPIO7_IRQ2_EVE2,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_EVE2_0,WKUPDEP_GPIO7_IRQ2_EVE2_1" newline bitfld.long 0x20 16. "WKUPDEP_GPIO7_IRQ2_EVE1,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_EVE1_0,WKUPDEP_GPIO7_IRQ2_EVE1_1" bitfld.long 0x20 15. "WKUPDEP_GPIO7_IRQ2_DSP2,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_DSP2_0,WKUPDEP_GPIO7_IRQ2_DSP2_1" newline bitfld.long 0x20 14. "WKUPDEP_GPIO7_IRQ2_IPU1,Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_IPU1_0,WKUPDEP_GPIO7_IRQ2_IPU1_1" rbitfld.long 0x20 13. "RESERVED," "0,1" newline bitfld.long 0x20 12. "WKUPDEP_GPIO7_IRQ2_DSP1,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_DSP1_0,WKUPDEP_GPIO7_IRQ2_DSP1_1" bitfld.long 0x20 11. "WKUPDEP_GPIO7_IRQ2_IPU2,Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_IPU2_0,WKUPDEP_GPIO7_IRQ2_IPU2_1" newline bitfld.long 0x20 10. "WKUPDEP_GPIO7_IRQ2_MPU,Wakeup dependency from GPIO7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_MPU_0,WKUPDEP_GPIO7_IRQ2_MPU_1" bitfld.long 0x20 9. "WKUPDEP_GPIO7_IRQ1_EVE4,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_EVE4_0,WKUPDEP_GPIO7_IRQ1_EVE4_1" newline bitfld.long 0x20 8. "WKUPDEP_GPIO7_IRQ1_EVE3,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_EVE3_0,WKUPDEP_GPIO7_IRQ1_EVE3_1" bitfld.long 0x20 7. "WKUPDEP_GPIO7_IRQ1_EVE2,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_EVE2_0,WKUPDEP_GPIO7_IRQ1_EVE2_1" newline bitfld.long 0x20 6. "WKUPDEP_GPIO7_IRQ1_EVE1,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_EVE1_0,WKUPDEP_GPIO7_IRQ1_EVE1_1" bitfld.long 0x20 5. "WKUPDEP_GPIO7_IRQ1_DSP2,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_DSP2_0,WKUPDEP_GPIO7_IRQ1_DSP2_1" newline bitfld.long 0x20 4. "WKUPDEP_GPIO7_IRQ1_IPU1,Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_IPU1_0,WKUPDEP_GPIO7_IRQ1_IPU1_1" rbitfld.long 0x20 3. "RESERVED," "0,1" newline bitfld.long 0x20 2. "WKUPDEP_GPIO7_IRQ1_DSP1,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_DSP1_0,WKUPDEP_GPIO7_IRQ1_DSP1_1" bitfld.long 0x20 1. "WKUPDEP_GPIO7_IRQ1_IPU2,5Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_IPU2_0,WKUPDEP_GPIO7_IRQ1_IPU2_1" newline bitfld.long 0x20 0. "WKUPDEP_GPIO7_IRQ1_MPU,Wakeup dependency from GPIO7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_MPU_0,WKUPDEP_GPIO7_IRQ1_MPU_1" line.long 0x24 "RM_L4PER_GPIO7_CONTEXT,This register contains dedicated GPIO7 context statuses" hexmask.long 0x24 2.--31. 1. "RESERVED," bitfld.long 0x24 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x24 0. "RESERVED," "0,1" line.long 0x28 "PM_L4PER_GPIO8_WKDEP,This register controls wakeup dependency based on GPIO8 service requests" hexmask.long.word 0x28 20.--31. 1. "RESERVED," bitfld.long 0x28 19. "WKUPDEP_GPIO8_IRQ2_EVE4,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_EVE4_0,WKUPDEP_GPIO8_IRQ2_EVE4_1" newline bitfld.long 0x28 18. "WKUPDEP_GPIO8_IRQ2_EVE3,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_EVE3_0,WKUPDEP_GPIO8_IRQ2_EVE3_1" bitfld.long 0x28 17. "WKUPDEP_GPIO8_IRQ2_EVE2,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_EVE2_0,WKUPDEP_GPIO8_IRQ2_EVE2_1" newline bitfld.long 0x28 16. "WKUPDEP_GPIO8_IRQ2_EVE1,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_EVE1_0,WKUPDEP_GPIO8_IRQ2_EVE1_1" bitfld.long 0x28 15. "WKUPDEP_GPIO8_IRQ2_DSP2,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_DSP2_0,WKUPDEP_GPIO8_IRQ2_DSP2_1" newline bitfld.long 0x28 14. "WKUPDEP_GPIO8_IRQ2_IPU1,Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_IPU1_0,WKUPDEP_GPIO8_IRQ2_IPU1_1" rbitfld.long 0x28 13. "RESERVED," "0,1" newline bitfld.long 0x28 12. "WKUPDEP_GPIO8_IRQ2_DSP1,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_DSP1_0,WKUPDEP_GPIO8_IRQ2_DSP1_1" bitfld.long 0x28 11. "WKUPDEP_GPIO8_IRQ2_IPU2,Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_IPU2_0,WKUPDEP_GPIO8_IRQ2_IPU2_1" newline bitfld.long 0x28 10. "WKUPDEP_GPIO8_IRQ2_MPU,Wakeup dependency from GPIO8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_MPU_0,WKUPDEP_GPIO8_IRQ2_MPU_1" bitfld.long 0x28 9. "WKUPDEP_GPIO8_IRQ1_EVE4,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_EVE4_0,WKUPDEP_GPIO8_IRQ1_EVE4_1" newline bitfld.long 0x28 8. "WKUPDEP_GPIO8_IRQ1_EVE3,Wakeup dependency from GPIO8 (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_EVE3_0,WKUPDEP_GPIO8_IRQ1_EVE3_1" bitfld.long 0x28 7. "WKUPDEP_GPIO8_IRQ1_EVE2,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_EVE2_0,WKUPDEP_GPIO8_IRQ1_EVE2_1" newline bitfld.long 0x28 6. "WKUPDEP_GPIO8_IRQ1_EVE1,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_EVE1_0,WKUPDEP_GPIO8_IRQ1_EVE1_1" bitfld.long 0x28 5. "WKUPDEP_GPIO8_IRQ1_DSP2,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_DSP2_0,WKUPDEP_GPIO8_IRQ1_DSP2_1" newline bitfld.long 0x28 4. "WKUPDEP_GPIO8_IRQ1_IPU1,Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_IPU1_0,WKUPDEP_GPIO8_IRQ1_IPU1_1" rbitfld.long 0x28 3. "RESERVED," "0,1" newline bitfld.long 0x28 2. "WKUPDEP_GPIO8_IRQ1_DSP1,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_DSP1_0,WKUPDEP_GPIO8_IRQ1_DSP1_1" bitfld.long 0x28 1. "WKUPDEP_GPIO8_IRQ1_IPU2,5Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_IPU2_0,WKUPDEP_GPIO8_IRQ1_IPU2_1" newline bitfld.long 0x28 0. "WKUPDEP_GPIO8_IRQ1_MPU,Wakeup dependency from GPIO8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_MPU_0,WKUPDEP_GPIO8_IRQ1_MPU_1" line.long 0x2C "RM_L4PER_GPIO8_CONTEXT,This register contains dedicated GPIO8 context statuses" hexmask.long 0x2C 2.--31. 1. "RESERVED," bitfld.long 0x2C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x2C 0. "RESERVED," "0,1" line.long 0x30 "PM_L4PER_MMC3_WKDEP,This register controls wakeup dependency based on MMC3 service requests" hexmask.long.tbyte 0x30 10.--31. 1. "RESERVED," bitfld.long 0x30 9. "WKUPDEP_MMC3_EVE4,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_EVE4_0,WKUPDEP_MMC3_EVE4_1" newline bitfld.long 0x30 8. "WKUPDEP_MMC3_EVE3,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_EVE3_0,WKUPDEP_MMC3_EVE3_1" bitfld.long 0x30 7. "WKUPDEP_MMC3_EVE2,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_EVE2_0,WKUPDEP_MMC3_EVE2_1" newline bitfld.long 0x30 6. "WKUPDEP_MMC3_EVE1,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_EVE1_0,WKUPDEP_MMC3_EVE1_1" bitfld.long 0x30 5. "WKUPDEP_MMC3_DSP2,Wakeup dependency from MMC3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_DSP2_0,WKUPDEP_MMC3_DSP2_1" newline bitfld.long 0x30 4. "WKUPDEP_MMC3_IPU1,Wakeup dependency from MMC3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_IPU1_0,WKUPDEP_MMC3_IPU1_1" bitfld.long 0x30 3. "WKUPDEP_MMC3_SDMA,Wakeup dependency from MMC3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_SDMA_0,WKUPDEP_MMC3_SDMA_1" newline bitfld.long 0x30 2. "WKUPDEP_MMC3_DSP1,Wakeup dependency from MMC3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_DSP1_0,WKUPDEP_MMC3_DSP1_1" bitfld.long 0x30 1. "WKUPDEP_MMC3_IPU2,Wakeup dependency from MMC3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_IPU2_0,WKUPDEP_MMC3_IPU2_1" newline bitfld.long 0x30 0. "WKUPDEP_MMC3_MPU,Wakeup dependency from MMC3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_MPU_0,WKUPDEP_MMC3_MPU_1" line.long 0x34 "RM_L4PER_MMC3_CONTEXT,This register contains dedicated MMC3 context statuses" hexmask.long.tbyte 0x34 9.--31. 1. "RESERVED," bitfld.long 0x34 8. "LOSTMEM_NONRETAINED_BANK,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_NONRETAINED_BANK_0,LOSTMEM_NONRETAINED_BANK_1" newline hexmask.long.byte 0x34 1.--7. 1. "RESERVED," bitfld.long 0x34 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x38 "PM_L4PER_MMC4_WKDEP,This register controls wakeup dependency based on MMC4 service requests" hexmask.long.tbyte 0x38 10.--31. 1. "RESERVED," bitfld.long 0x38 9. "WKUPDEP_MMC4_EVE4,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_EVE4_0,WKUPDEP_MMC4_EVE4_1" newline bitfld.long 0x38 8. "WKUPDEP_MMC4_EVE3,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_EVE3_0,WKUPDEP_MMC4_EVE3_1" bitfld.long 0x38 7. "WKUPDEP_MMC4_EVE2,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_EVE2_0,WKUPDEP_MMC4_EVE2_1" newline bitfld.long 0x38 6. "WKUPDEP_MMC4_EVE1,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_EVE1_0,WKUPDEP_MMC4_EVE1_1" bitfld.long 0x38 5. "WKUPDEP_MMC4_DSP2,Wakeup dependency from MMC4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_DSP2_0,WKUPDEP_MMC4_DSP2_1" newline bitfld.long 0x38 4. "WKUPDEP_MMC4_IPU1,Wakeup dependency from MMC4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_IPU1_0,WKUPDEP_MMC4_IPU1_1" bitfld.long 0x38 3. "WKUPDEP_MMC4_SDMA,Wakeup dependency from MMC4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_SDMA_0,WKUPDEP_MMC4_SDMA_1" newline bitfld.long 0x38 2. "WKUPDEP_MMC4_DSP1,Wakeup dependency from MMC4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_DSP1_0,WKUPDEP_MMC4_DSP1_1" bitfld.long 0x38 1. "WKUPDEP_MMC4_IPU2,Wakeup dependency from MMC4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_IPU2_0,WKUPDEP_MMC4_IPU2_1" newline bitfld.long 0x38 0. "WKUPDEP_MMC4_MPU,Wakeup dependency from MMC4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_MPU_0,WKUPDEP_MMC4_MPU_1" line.long 0x3C "RM_L4PER_MMC4_CONTEXT,This register contains dedicated MMC4 context statuses" hexmask.long.tbyte 0x3C 9.--31. 1. "RESERVED," bitfld.long 0x3C 8. "LOSTMEM_NONRETAINED_BANK,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_NONRETAINED_BANK_0,LOSTMEM_NONRETAINED_BANK_1" newline hexmask.long.byte 0x3C 1.--7. 1. "RESERVED," bitfld.long 0x3C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x40 "PM_L4PER_DCC4_WKDEP,This register controls wakeup dependency based on DCC4 service requests" hexmask.long.tbyte 0x40 10.--31. 1. "RESERVED," bitfld.long 0x40 9. "WKUPDEP_DCC4_EVE4,Wakeup dependency from DCC4 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_EVE4_0,WKUPDEP_DCC4_EVE4_1" newline bitfld.long 0x40 8. "WKUPDEP_DCC4_EVE3,Wakeup dependency from DCC4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_EVE3_0,WKUPDEP_DCC4_EVE3_1" bitfld.long 0x40 7. "WKUPDEP_DCC4_EVE2,Wakeup dependency from DCC4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_EVE2_0,WKUPDEP_DCC4_EVE2_1" newline bitfld.long 0x40 6. "WKUPDEP_DCC4_EVE1,Wakeup dependency from DCC4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_EVE1_0,WKUPDEP_DCC4_EVE1_1" bitfld.long 0x40 5. "WKUPDEP_DCC4_DSP2,Wakeup dependency from DCC4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_DSP2_0,WKUPDEP_DCC4_DSP2_1" newline bitfld.long 0x40 4. "WKUPDEP_DCC4_IPU1,Wakeup dependency from DCC4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_IPU1_0,WKUPDEP_DCC4_IPU1_1" rbitfld.long 0x40 3. "RESERVED," "0,1" newline bitfld.long 0x40 2. "WKUPDEP_DCC4_DSP1,Wakeup dependency from DCC4 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_DSP1_0,WKUPDEP_DCC4_DSP1_1" bitfld.long 0x40 1. "WKUPDEP_DCC4_IPU2,Wakeup dependency from DCC4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_IPU2_0,WKUPDEP_DCC4_IPU2_1" newline bitfld.long 0x40 0. "WKUPDEP_DCC4_MPU,6Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_MPU_0,WKUPDEP_DCC4_MPU_1" line.long 0x44 "RM_L4PER3_DCC4_CONTEXT,This register contains dedicated DCC4 context statuses" hexmask.long 0x44 1.--31. 1. "RESERVED," bitfld.long 0x44 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x48 "PM_L4PER2_QSPI_WKDEP,This register controls wakeup dependency based on QSPI service requests" hexmask.long.tbyte 0x48 10.--31. 1. "RESERVED," bitfld.long 0x48 9. "WKUPDEP_QSPI_EVE4,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_EVE4_0,WKUPDEP_QSPI_EVE4_1" newline bitfld.long 0x48 8. "WKUPDEP_QSPI_EVE3,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_EVE3_0,WKUPDEP_QSPI_EVE3_1" bitfld.long 0x48 7. "WKUPDEP_QSPI_EVE2,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_EVE2_0,WKUPDEP_QSPI_EVE2_1" newline bitfld.long 0x48 6. "WKUPDEP_QSPI_EVE1,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_EVE1_0,WKUPDEP_QSPI_EVE1_1" bitfld.long 0x48 5. "WKUPDEP_QSPI_DSP2,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_DSP2_0,WKUPDEP_QSPI_DSP2_1" newline bitfld.long 0x48 4. "WKUPDEP_QSPI_IPU1,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_IPU1_0,WKUPDEP_QSPI_IPU1_1" rbitfld.long 0x48 3. "RESERVED," "0,1" newline bitfld.long 0x48 2. "WKUPDEP_QSPI_DSP1,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_DSP1_0,WKUPDEP_QSPI_DSP1_1" bitfld.long 0x48 1. "WKUPDEP_QSPI_IPU2,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_IPU2_0,WKUPDEP_QSPI_IPU2_1" newline bitfld.long 0x48 0. "WKUPDEP_QSPI_MPU,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_MPU_0,WKUPDEP_QSPI_MPU_1" line.long 0x4C "RM_L4PER2_QSPI_CONTEXT,This register contains dedicated QSPI context statuses" hexmask.long 0x4C 1.--31. 1. "RESERVED," bitfld.long 0x4C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x50 "PM_L4PER_UART1_WKDEP,This register controls wakeup dependency based on UART1 service requests" hexmask.long.tbyte 0x50 10.--31. 1. "RESERVED," bitfld.long 0x50 9. "WKUPDEP_UART1_EVE4,Wakeup dependency from UART1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_EVE4_0,WKUPDEP_UART1_EVE4_1" newline bitfld.long 0x50 8. "WKUPDEP_UART1_EVE3,Wakeup dependency from UART1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_EVE3_0,WKUPDEP_UART1_EVE3_1" bitfld.long 0x50 7. "WKUPDEP_UART1_EVE2,Wakeup dependency from UART1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_EVE2_0,WKUPDEP_UART1_EVE2_1" newline bitfld.long 0x50 6. "WKUPDEP_UART1_EVE1,Wakeup dependency from UART1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_EVE1_0,WKUPDEP_UART1_EVE1_1" bitfld.long 0x50 5. "WKUPDEP_UART1_DSP2,Wakeup dependency from UART1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_DSP2_0,WKUPDEP_UART1_DSP2_1" newline bitfld.long 0x50 4. "WKUPDEP_UART1_IPU1,Wakeup dependency from UART1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_IPU1_0,WKUPDEP_UART1_IPU1_1" bitfld.long 0x50 3. "WKUPDEP_UART1_SDMA,Wakeup dependency from UART1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_SDMA_0,WKUPDEP_UART1_SDMA_1" newline bitfld.long 0x50 2. "WKUPDEP_UART1_DSP1,Wakeup dependency from UART1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_DSP1_0,WKUPDEP_UART1_DSP1_1" bitfld.long 0x50 1. "WKUPDEP_UART1_IPU2,Wakeup dependency from UART1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_IPU2_0,WKUPDEP_UART1_IPU2_1" newline bitfld.long 0x50 0. "WKUPDEP_UART1_MPU,Wakeup dependency from UART1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_MPU_0,WKUPDEP_UART1_MPU_1" line.long 0x54 "RM_L4PER_UART1_CONTEXT,This register contains dedicated UART1 context statuses" hexmask.long.tbyte 0x54 9.--31. 1. "RESERVED," bitfld.long 0x54 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x54 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x54 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x54 0. "RESERVED," "0,1" line.long 0x58 "PM_L4PER_UART2_WKDEP,This register controls wakeup dependency based on UART2 service requests" hexmask.long.tbyte 0x58 10.--31. 1. "RESERVED," bitfld.long 0x58 9. "WKUPDEP_UART2_EVE4,Wakeup dependency from UART2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_EVE4_0,WKUPDEP_UART2_EVE4_1" newline bitfld.long 0x58 8. "WKUPDEP_UART2_EVE3,Wakeup dependency from UART2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_EVE3_0,WKUPDEP_UART2_EVE3_1" bitfld.long 0x58 7. "WKUPDEP_UART2_EVE2,Wakeup dependency from UART2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_EVE2_0,WKUPDEP_UART2_EVE2_1" newline bitfld.long 0x58 6. "WKUPDEP_UART2_EVE1,Wakeup dependency from UART2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_EVE1_0,WKUPDEP_UART2_EVE1_1" bitfld.long 0x58 5. "WKUPDEP_UART2_DSP2,Wakeup dependency from UART2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_DSP2_0,WKUPDEP_UART2_DSP2_1" newline bitfld.long 0x58 4. "WKUPDEP_UART2_IPU1,Wakeup dependency from UART2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_IPU1_0,WKUPDEP_UART2_IPU1_1" bitfld.long 0x58 3. "WKUPDEP_UART2_SDMA,2Wakeup dependency from UART1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_SDMA_0,WKUPDEP_UART2_SDMA_1" newline bitfld.long 0x58 2. "WKUPDEP_UART2_DSP1,Wakeup dependency from UART2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_DSP1_0,WKUPDEP_UART2_DSP1_1" bitfld.long 0x58 1. "WKUPDEP_UART2_IPU2,Wakeup dependency from UART2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_IPU2_0,WKUPDEP_UART2_IPU2_1" newline bitfld.long 0x58 0. "WKUPDEP_UART2_MPU,Wakeup dependency from UART2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_MPU_0,WKUPDEP_UART2_MPU_1" line.long 0x5C "RM_L4PER_UART2_CONTEXT,This register contains dedicated UART2 context statuses" hexmask.long.tbyte 0x5C 9.--31. 1. "RESERVED," bitfld.long 0x5C 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x5C 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x5C 0. "RESERVED," "0,1" line.long 0x60 "PM_L4PER_UART3_WKDEP,This register controls wakeup dependency based on UART3 service requests" hexmask.long.tbyte 0x60 10.--31. 1. "RESERVED," bitfld.long 0x60 9. "WKUPDEP_UART3_EVE4,Wakeup dependency from UART3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_EVE4_0,WKUPDEP_UART3_EVE4_1" newline bitfld.long 0x60 8. "WKUPDEP_UART3_EVE3,Wakeup dependency from UART3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_EVE3_0,WKUPDEP_UART3_EVE3_1" bitfld.long 0x60 7. "WKUPDEP_UART3_EVE2,Wakeup dependency from UART3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_EVE2_0,WKUPDEP_UART3_EVE2_1" newline bitfld.long 0x60 6. "WKUPDEP_UART3_EVE1,Wakeup dependency from UART3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_EVE1_0,WKUPDEP_UART3_EVE1_1" bitfld.long 0x60 5. "WKUPDEP_UART3_DSP2,Wakeup dependency from UART3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_DSP2_0,WKUPDEP_UART3_DSP2_1" newline bitfld.long 0x60 4. "WKUPDEP_UART3_IPU1,Wakeup dependency from UART3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_IPU1_0,WKUPDEP_UART3_IPU1_1" bitfld.long 0x60 3. "WKUPDEP_UART3_SDMA,Wakeup dependency from UART3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_SDMA_0,WKUPDEP_UART3_SDMA_1" newline bitfld.long 0x60 2. "WKUPDEP_UART3_DSP1,Wakeup dependency from UART3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_DSP1_0,WKUPDEP_UART3_DSP1_1" bitfld.long 0x60 1. "WKUPDEP_UART3_IPU2,Wakeup dependency from UART3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_IPU2_0,WKUPDEP_UART3_IPU2_1" newline bitfld.long 0x60 0. "WKUPDEP_UART3_MPU,Wakeup dependency from UART3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_MPU_0,WKUPDEP_UART3_MPU_1" line.long 0x64 "RM_L4PER_UART3_CONTEXT,This register contains dedicated UART3 context statuses" hexmask.long.tbyte 0x64 9.--31. 1. "RESERVED," bitfld.long 0x64 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x64 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x64 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x64 0. "RESERVED," "0,1" line.long 0x68 "PM_L4PER_UART4_WKDEP,This register controls wakeup dependency based on UART4 service requests" hexmask.long.tbyte 0x68 10.--31. 1. "RESERVED," bitfld.long 0x68 9. "WKUPDEP_UART4_EVE4,Wakeup dependency from UART4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_EVE4_0,WKUPDEP_UART4_EVE4_1" newline bitfld.long 0x68 8. "WKUPDEP_UART4_EVE3,Wakeup dependency from UART4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_EVE3_0,WKUPDEP_UART4_EVE3_1" bitfld.long 0x68 7. "WKUPDEP_UART4_EVE2,Wakeup dependency from UART4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_EVE2_0,WKUPDEP_UART4_EVE2_1" newline bitfld.long 0x68 6. "WKUPDEP_UART4_EVE1,Wakeup dependency from UART4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_EVE1_0,WKUPDEP_UART4_EVE1_1" bitfld.long 0x68 5. "WKUPDEP_UART4_DSP2,Wakeup dependency from UART4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_DSP2_0,WKUPDEP_UART4_DSP2_1" newline bitfld.long 0x68 4. "WKUPDEP_UART4_IPU1,Wakeup dependency from UART4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_IPU1_0,WKUPDEP_UART4_IPU1_1" bitfld.long 0x68 3. "WKUPDEP_UART4_SDMA,Wakeup dependency from UART4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_SDMA_0,WKUPDEP_UART4_SDMA_1" newline bitfld.long 0x68 2. "WKUPDEP_UART4_DSP1,Wakeup dependency from UART4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_DSP1_0,WKUPDEP_UART4_DSP1_1" bitfld.long 0x68 1. "WKUPDEP_UART4_IPU2,Wakeup dependency from UART4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_IPU2_0,WKUPDEP_UART4_IPU2_1" newline bitfld.long 0x68 0. "WKUPDEP_UART4_MPU,Wakeup dependency from UART4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_MPU_0,WKUPDEP_UART4_MPU_1" line.long 0x6C "RM_L4PER_UART4_CONTEXT,This register contains dedicated UART4 context statuses" hexmask.long.tbyte 0x6C 9.--31. 1. "RESERVED," bitfld.long 0x6C 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x6C 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x6C 0. "RESERVED," "0,1" line.long 0x70 "PM_L4PER2_ADC_WKDEP,This register controls wakeup dependency based on ADC service requests" hexmask.long.word 0x70 16.--31. 1. "RESERVED," bitfld.long 0x70 15. "WKUPDEP_ADC_DMA_DSP2,Wakeup dependency from ADC module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_DMA_DSP2_0,WKUPDEP_ADC_DMA_DSP2_1" newline rbitfld.long 0x70 14. "RESERVED," "0,1" bitfld.long 0x70 13. "WKUPDEP_ADC_DMA_SDMA,Wakeup dependency from ADC module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_DMA_SDMA_0,WKUPDEP_ADC_DMA_SDMA_1" newline bitfld.long 0x70 12. "WKUPDEP_ADC_DMA_DSP1,Wakeup dependency from ADC module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_DMA_DSP1_0,WKUPDEP_ADC_DMA_DSP1_1" rbitfld.long 0x70 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x70 9. "WKUPDEP_ADC_IRQ_EVE4,Wakeup dependency from ADC module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_EVE4_0,WKUPDEP_ADC_IRQ_EVE4_1" bitfld.long 0x70 8. "WKUPDEP_ADC_IRQ_EVE3,Wakeup dependency from ADC module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_EVE3_0,WKUPDEP_ADC_IRQ_EVE3_1" newline bitfld.long 0x70 7. "WKUPDEP_ADC_IRQ_EVE2,Wakeup dependency from ADC module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_EVE2_0,WKUPDEP_ADC_IRQ_EVE2_1" bitfld.long 0x70 6. "WKUPDEP_ADC_IRQ_EVE1,Wakeup dependency from ADC module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_EVE1_0,WKUPDEP_ADC_IRQ_EVE1_1" newline bitfld.long 0x70 5. "WKUPDEP_ADC_IRQ_DSP2,Wakeup dependency from ADC module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_DSP2_0,WKUPDEP_ADC_IRQ_DSP2_1" bitfld.long 0x70 4. "WKUPDEP_ADC_IRQ_IPU1,Wakeup dependency from ADC module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_IPU1_0,WKUPDEP_ADC_IRQ_IPU1_1" newline rbitfld.long 0x70 3. "RESERVED," "0,1" bitfld.long 0x70 2. "WKUPDEP_ADC_IRQ_DSP1,Wakeup dependency from ADC module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_DSP1_0,WKUPDEP_ADC_IRQ_DSP1_1" newline bitfld.long 0x70 1. "WKUPDEP_ADC_IRQ_IPU2,Wakeup dependency from ADC module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_IPU2_0,WKUPDEP_ADC_IRQ_IPU2_1" bitfld.long 0x70 0. "WKUPDEP_ADC_IRQ_MPU,Wakeup dependency from ADC module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_MPU_0,WKUPDEP_ADC_IRQ_MPU_1" line.long 0x74 "RM_L4PER2_ADC_CONTEXT,This register contains dedicated ADC context statuses" hexmask.long 0x74 1.--31. 1. "RESERVED," bitfld.long 0x74 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x78 "PM_L4PER2_MCASP3_WKDEP,This register controls wakeup dependency based on MCASP3 service requests" hexmask.long.word 0x78 16.--31. 1. "RESERVED," bitfld.long 0x78 15. "WKUPDEP_MCASP3_DMA_DSP2,Wakeup dependency from MCASP3 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_DMA_DSP2_0,WKUPDEP_MCASP3_DMA_DSP2_1" newline rbitfld.long 0x78 14. "RESERVED," "0,1" bitfld.long 0x78 13. "WKUPDEP_MCASP3_DMA_SDMA,Wakeup dependency from MCASP3 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_DMA_SDMA_0,WKUPDEP_MCASP3_DMA_SDMA_1" newline bitfld.long 0x78 12. "WKUPDEP_MCASP3_DMA_DSP1,3Wakeup dependency from ADC module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_DMA_DSP1_0,WKUPDEP_MCASP3_DMA_DSP1_1" rbitfld.long 0x78 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x78 9. "WKUPDEP_MCASP3_IRQ_EVE4,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_EVE4_0,WKUPDEP_MCASP3_IRQ_EVE4_1" bitfld.long 0x78 8. "WKUPDEP_MCASP3_IRQ_EVE3,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_EVE3_0,WKUPDEP_MCASP3_IRQ_EVE3_1" newline bitfld.long 0x78 7. "WKUPDEP_MCASP3_IRQ_EVE2,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_EVE2_0,WKUPDEP_MCASP3_IRQ_EVE2_1" bitfld.long 0x78 6. "WKUPDEP_MCASP3_IRQ_EVE1,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_EVE1_0,WKUPDEP_MCASP3_IRQ_EVE1_1" newline bitfld.long 0x78 5. "WKUPDEP_MCASP3_IRQ_DSP2,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_DSP2_0,WKUPDEP_MCASP3_IRQ_DSP2_1" bitfld.long 0x78 4. "WKUPDEP_MCASP3_IRQ_IPU1,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_IPU1_0,WKUPDEP_MCASP3_IRQ_IPU1_1" newline rbitfld.long 0x78 3. "RESERVED," "0,1" bitfld.long 0x78 2. "WKUPDEP_MCASP3_IRQ_DSP1,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_DSP1_0,WKUPDEP_MCASP3_IRQ_DSP1_1" newline bitfld.long 0x78 1. "WKUPDEP_MCASP3_IRQ_IPU2,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_IPU2_0,WKUPDEP_MCASP3_IRQ_IPU2_1" bitfld.long 0x78 0. "WKUPDEP_MCASP3_IRQ_MPU,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_MPU_0,WKUPDEP_MCASP3_IRQ_MPU_1" line.long 0x7C "RM_L4PER2_MCASP3_CONTEXT,This register contains dedicated MCASP3 context statuses" hexmask.long 0x7C 1.--31. 1. "RESERVED," bitfld.long 0x7C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x80 "PM_L4PER_UART5_WKDEP,This register controls wakeup dependency based on UART5 service requests" hexmask.long.tbyte 0x80 10.--31. 1. "RESERVED," bitfld.long 0x80 9. "WKUPDEP_UART5_EVE4,Wakeup dependency from UART5 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_EVE4_0,WKUPDEP_UART5_EVE4_1" newline bitfld.long 0x80 8. "WKUPDEP_UART5_EVE3,Wakeup dependency from UART5 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_EVE3_0,WKUPDEP_UART5_EVE3_1" bitfld.long 0x80 7. "WKUPDEP_UART5_EVE2,Wakeup dependency from UART5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_EVE2_0,WKUPDEP_UART5_EVE2_1" newline bitfld.long 0x80 6. "WKUPDEP_UART5_EVE1,Wakeup dependency from UART5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_EVE1_0,WKUPDEP_UART5_EVE1_1" bitfld.long 0x80 5. "WKUPDEP_UART5_DSP2,Wakeup dependency from UART5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_DSP2_0,WKUPDEP_UART5_DSP2_1" newline bitfld.long 0x80 4. "WKUPDEP_UART5_IPU1,Wakeup dependency from UART5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_IPU1_0,WKUPDEP_UART5_IPU1_1" bitfld.long 0x80 3. "WKUPDEP_UART5_SDMA,Wakeup dependency from UART5 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_SDMA_0,WKUPDEP_UART5_SDMA_1" newline bitfld.long 0x80 2. "WKUPDEP_UART5_DSP1,Wakeup dependency from UART5 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_DSP1_0,WKUPDEP_UART5_DSP1_1" bitfld.long 0x80 1. "WKUPDEP_UART5_IPU2,Wakeup dependency from UART5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_IPU2_0,WKUPDEP_UART5_IPU2_1" newline bitfld.long 0x80 0. "WKUPDEP_UART5_MPU,Wakeup dependency from UART5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_MPU_0,WKUPDEP_UART5_MPU_1" line.long 0x84 "RM_L4PER_UART5_CONTEXT,This register contains dedicated UART5 context statuses" hexmask.long.tbyte 0x84 9.--31. 1. "RESERVED," bitfld.long 0x84 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x84 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x84 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x84 0. "RESERVED," "0,1" line.long 0x88 "PM_L4PER2_MCASP5_WKDEP,This register controls wakeup dependency based on MCASP5 service requests" hexmask.long.word 0x88 16.--31. 1. "RESERVED," bitfld.long 0x88 15. "WKUPDEP_MCASP5_DMA_DSP2,Wakeup dependency from MCASP5 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_DMA_DSP2_0,WKUPDEP_MCASP5_DMA_DSP2_1" newline rbitfld.long 0x88 14. "RESERVED," "0,1" bitfld.long 0x88 13. "WKUPDEP_MCASP5_DMA_SDMA,Wakeup dependency from MCASP5 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_DMA_SDMA_0,WKUPDEP_MCASP5_DMA_SDMA_1" newline bitfld.long 0x88 12. "WKUPDEP_MCASP5_DMA_DSP1,Wakeup dependency from MCASP5 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_DMA_DSP1_0,WKUPDEP_MCASP5_DMA_DSP1_1" rbitfld.long 0x88 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x88 9. "WKUPDEP_MCASP5_IRQ_EVE4,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_EVE4_0,WKUPDEP_MCASP5_IRQ_EVE4_1" bitfld.long 0x88 8. "WKUPDEP_MCASP5_IRQ_EVE3,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_EVE3_0,WKUPDEP_MCASP5_IRQ_EVE3_1" newline bitfld.long 0x88 7. "WKUPDEP_MCASP5_IRQ_EVE2,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_EVE2_0,WKUPDEP_MCASP5_IRQ_EVE2_1" bitfld.long 0x88 6. "WKUPDEP_MCASP5_IRQ_EVE1,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_EVE1_0,WKUPDEP_MCASP5_IRQ_EVE1_1" newline bitfld.long 0x88 5. "WKUPDEP_MCASP5_IRQ_DSP2,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_DSP2_0,WKUPDEP_MCASP5_IRQ_DSP2_1" bitfld.long 0x88 4. "WKUPDEP_MCASP5_IRQ_IPU1,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_IPU1_0,WKUPDEP_MCASP5_IRQ_IPU1_1" newline rbitfld.long 0x88 3. "RESERVED," "0,1" bitfld.long 0x88 2. "WKUPDEP_MCASP5_IRQ_DSP1,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_DSP1_0,WKUPDEP_MCASP5_IRQ_DSP1_1" newline bitfld.long 0x88 1. "WKUPDEP_MCASP5_IRQ_IPU2,Wakeup dependency from ADC module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_IPU2_0,WKUPDEP_MCASP5_IRQ_IPU2_1" bitfld.long 0x88 0. "WKUPDEP_MCASP5_IRQ_MPU,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_MPU_0,WKUPDEP_MCASP5_IRQ_MPU_1" line.long 0x8C "RM_L4PER2_MCASP5_CONTEXT,This register contains dedicated MCASP5 context statuses" hexmask.long 0x8C 1.--31. 1. "RESERVED," bitfld.long 0x8C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x90 "PM_L4PER2_MCASP6_WKDEP,This register controls wakeup dependency based on MCASP6 service requests" hexmask.long.word 0x90 16.--31. 1. "RESERVED," bitfld.long 0x90 15. "WKUPDEP_MCASP6_DMA_DSP2,Wakeup dependency from MCASP6 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_DMA_DSP2_0,WKUPDEP_MCASP6_DMA_DSP2_1" newline rbitfld.long 0x90 14. "RESERVED," "0,1" bitfld.long 0x90 13. "WKUPDEP_MCASP6_DMA_SDMA,Wakeup dependency from MCASP6 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_DMA_SDMA_0,WKUPDEP_MCASP6_DMA_SDMA_1" newline bitfld.long 0x90 12. "WKUPDEP_MCASP6_DMA_DSP1,Wakeup dependency from MCASP6 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_DMA_DSP1_0,WKUPDEP_MCASP6_DMA_DSP1_1" rbitfld.long 0x90 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x90 9. "WKUPDEP_MCASP6_IRQ_EVE4,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_EVE4_0,WKUPDEP_MCASP6_IRQ_EVE4_1" bitfld.long 0x90 8. "WKUPDEP_MCASP6_IRQ_EVE3,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_EVE3_0,WKUPDEP_MCASP6_IRQ_EVE3_1" newline bitfld.long 0x90 7. "WKUPDEP_MCASP6_IRQ_EVE2,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_EVE2_0,WKUPDEP_MCASP6_IRQ_EVE2_1" bitfld.long 0x90 6. "WKUPDEP_MCASP6_IRQ_EVE1,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_EVE1_0,WKUPDEP_MCASP6_IRQ_EVE1_1" newline bitfld.long 0x90 5. "WKUPDEP_MCASP6_IRQ_DSP2,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_DSP2_0,WKUPDEP_MCASP6_IRQ_DSP2_1" bitfld.long 0x90 4. "WKUPDEP_MCASP6_IRQ_IPU1,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_IPU1_0,WKUPDEP_MCASP6_IRQ_IPU1_1" newline rbitfld.long 0x90 3. "RESERVED," "0,1" bitfld.long 0x90 2. "WKUPDEP_MCASP6_IRQ_DSP1,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_DSP1_0,WKUPDEP_MCASP6_IRQ_DSP1_1" newline bitfld.long 0x90 1. "WKUPDEP_MCASP6_IRQ_IPU2,Wakeup dependency from MCASP6 (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_IPU2_0,WKUPDEP_MCASP6_IRQ_IPU2_1" bitfld.long 0x90 0. "WKUPDEP_MCASP6_IRQ_MPU,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_MPU_0,WKUPDEP_MCASP6_IRQ_MPU_1" line.long 0x94 "RM_L4PER2_MCASP6_CONTEXT,This register contains dedicated MCASP6 context statuses" hexmask.long 0x94 1.--31. 1. "RESERVED," bitfld.long 0x94 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x98 "PM_L4PER2_MCASP7_WKDEP,This register controls wakeup dependency based on MCASP7 service requests" hexmask.long.word 0x98 16.--31. 1. "RESERVED," bitfld.long 0x98 15. "WKUPDEP_MCASP7_DMA_DSP2,Wakeup dependency from MCASP7 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_DMA_DSP2_0,WKUPDEP_MCASP7_DMA_DSP2_1" newline rbitfld.long 0x98 14. "RESERVED," "0,1" bitfld.long 0x98 13. "WKUPDEP_MCASP7_DMA_SDMA,Wakeup dependency from MCASP7 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_DMA_SDMA_0,WKUPDEP_MCASP7_DMA_SDMA_1" newline bitfld.long 0x98 12. "WKUPDEP_MCASP7_DMA_DSP1,Wakeup dependency from MCASP7 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_DMA_DSP1_0,WKUPDEP_MCASP7_DMA_DSP1_1" rbitfld.long 0x98 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x98 9. "WKUPDEP_MCASP7_IRQ_EVE4,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_EVE4_0,WKUPDEP_MCASP7_IRQ_EVE4_1" bitfld.long 0x98 8. "WKUPDEP_MCASP7_IRQ_EVE3,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_EVE3_0,WKUPDEP_MCASP7_IRQ_EVE3_1" newline bitfld.long 0x98 7. "WKUPDEP_MCASP7_IRQ_EVE2,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_EVE2_0,WKUPDEP_MCASP7_IRQ_EVE2_1" bitfld.long 0x98 6. "WKUPDEP_MCASP7_IRQ_EVE1,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_EVE1_0,WKUPDEP_MCASP7_IRQ_EVE1_1" newline bitfld.long 0x98 5. "WKUPDEP_MCASP7_IRQ_DSP2,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_DSP2_0,WKUPDEP_MCASP7_IRQ_DSP2_1" bitfld.long 0x98 4. "WKUPDEP_MCASP7_IRQ_IPU1,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_IPU1_0,WKUPDEP_MCASP7_IRQ_IPU1_1" newline rbitfld.long 0x98 3. "RESERVED," "0,1" bitfld.long 0x98 2. "WKUPDEP_MCASP7_IRQ_DSP1,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_DSP1_0,WKUPDEP_MCASP7_IRQ_DSP1_1" newline bitfld.long 0x98 1. "WKUPDEP_MCASP7_IRQ_IPU2,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_IPU2_0,WKUPDEP_MCASP7_IRQ_IPU2_1" bitfld.long 0x98 0. "WKUPDEP_MCASP7_IRQ_MPU,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_MPU_0,WKUPDEP_MCASP7_IRQ_MPU_1" line.long 0x9C "RM_L4PER2_MCASP7_CONTEXT,This register contains dedicated MCASP7 context statuses" hexmask.long 0x9C 1.--31. 1. "RESERVED," bitfld.long 0x9C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0xA0 "PM_L4PER2_MCASP8_WKDEP,This register controls wakeup dependency based on MCASP8 service requests" hexmask.long.word 0xA0 16.--31. 1. "RESERVED," bitfld.long 0xA0 15. "WKUPDEP_MCASP8_DMA_DSP2,Wakeup dependency from MCASP8 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_DMA_DSP2_0,WKUPDEP_MCASP8_DMA_DSP2_1" newline rbitfld.long 0xA0 14. "RESERVED," "0,1" bitfld.long 0xA0 13. "WKUPDEP_MCASP8_DMA_SDMA,Wakeup dependency from MCASP8 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_DMA_SDMA_0,WKUPDEP_MCASP8_DMA_SDMA_1" newline bitfld.long 0xA0 12. "WKUPDEP_MCASP8_DMA_DSP1,Wakeup dependency from MCASP8 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_DMA_DSP1_0,WKUPDEP_MCASP8_DMA_DSP1_1" rbitfld.long 0xA0 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0xA0 9. "WKUPDEP_MCASP8_IRQ_EVE4,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_EVE4_0,WKUPDEP_MCASP8_IRQ_EVE4_1" bitfld.long 0xA0 8. "WKUPDEP_MCASP8_IRQ_EVE3,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_EVE3_0,WKUPDEP_MCASP8_IRQ_EVE3_1" newline bitfld.long 0xA0 7. "WKUPDEP_MCASP8_IRQ_EVE2,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_EVE2_0,WKUPDEP_MCASP8_IRQ_EVE2_1" bitfld.long 0xA0 6. "WKUPDEP_MCASP8_IRQ_EVE1,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_EVE1_0,WKUPDEP_MCASP8_IRQ_EVE1_1" newline bitfld.long 0xA0 5. "WKUPDEP_MCASP8_IRQ_DSP2,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_DSP2_0,WKUPDEP_MCASP8_IRQ_DSP2_1" bitfld.long 0xA0 4. "WKUPDEP_MCASP8_IRQ_IPU1,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_IPU1_0,WKUPDEP_MCASP8_IRQ_IPU1_1" newline rbitfld.long 0xA0 3. "RESERVED," "0,1" bitfld.long 0xA0 2. "WKUPDEP_MCASP8_IRQ_DSP1,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_DSP1_0,WKUPDEP_MCASP8_IRQ_DSP1_1" newline bitfld.long 0xA0 1. "WKUPDEP_MCASP8_IRQ_IPU2,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_IPU2_0,WKUPDEP_MCASP8_IRQ_IPU2_1" bitfld.long 0xA0 0. "WKUPDEP_MCASP8_IRQ_MPU,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_MPU_0,WKUPDEP_MCASP8_IRQ_MPU_1" line.long 0xA4 "RM_L4PER2_MCASP8_CONTEXT,This register contains dedicated MCASP8 context statuses" hexmask.long 0xA4 1.--31. 1. "RESERVED," bitfld.long 0xA4 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0xA8 "PM_L4PER2_MCASP4_WKDEP,This register controls wakeup dependency based on MCASP4 service requests" hexmask.long.word 0xA8 16.--31. 1. "RESERVED," bitfld.long 0xA8 15. "WKUPDEP_MCASP4_DMA_DSP2,Wakeup dependency from MCASP4 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_DMA_DSP2_0,WKUPDEP_MCASP4_DMA_DSP2_1" newline rbitfld.long 0xA8 14. "RESERVED," "0,1" bitfld.long 0xA8 13. "WKUPDEP_MCASP4_DMA_SDMA,Wakeup dependency from MCASP4 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_DMA_SDMA_0,WKUPDEP_MCASP4_DMA_SDMA_1" newline bitfld.long 0xA8 12. "WKUPDEP_MCASP4_DMA_DSP1,Wakeup dependency from MCASP4 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_DMA_DSP1_0,WKUPDEP_MCASP4_DMA_DSP1_1" rbitfld.long 0xA8 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0xA8 9. "WKUPDEP_MCASP4_IRQ_EVE4,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_EVE4_0,WKUPDEP_MCASP4_IRQ_EVE4_1" bitfld.long 0xA8 8. "WKUPDEP_MCASP4_IRQ_EVE3,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_EVE3_0,WKUPDEP_MCASP4_IRQ_EVE3_1" newline bitfld.long 0xA8 7. "WKUPDEP_MCASP4_IRQ_EVE2,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_EVE2_0,WKUPDEP_MCASP4_IRQ_EVE2_1" bitfld.long 0xA8 6. "WKUPDEP_MCASP4_IRQ_EVE1,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_EVE1_0,WKUPDEP_MCASP4_IRQ_EVE1_1" newline bitfld.long 0xA8 5. "WKUPDEP_MCASP4_IRQ_DSP2,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_DSP2_0,WKUPDEP_MCASP4_IRQ_DSP2_1" bitfld.long 0xA8 4. "WKUPDEP_MCASP4_IRQ_IPU1,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_IPU1_0,WKUPDEP_MCASP4_IRQ_IPU1_1" newline rbitfld.long 0xA8 3. "RESERVED," "0,1" bitfld.long 0xA8 2. "WKUPDEP_MCASP4_IRQ_DSP1,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_DSP1_0,WKUPDEP_MCASP4_IRQ_DSP1_1" newline bitfld.long 0xA8 1. "WKUPDEP_MCASP4_IRQ_IPU2,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_IPU2_0,WKUPDEP_MCASP4_IRQ_IPU2_1" bitfld.long 0xA8 0. "WKUPDEP_MCASP4_IRQ_MPU,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_MPU_0,WKUPDEP_MCASP4_IRQ_MPU_1" line.long 0xAC "RM_L4PER2_MCASP4_CONTEXT,This register contains dedicated MCASP4 context statuses" hexmask.long 0xAC 1.--31. 1. "RESERVED," bitfld.long 0xAC 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x1A4++0x03 line.long 0x00 "RM_L4SEC_AES1_CONTEXT,This register contains dedicated AES1 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x1AC++0x03 line.long 0x00 "RM_L4SEC_AES2_CONTEXT,This register contains dedicated AES2 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x1B4++0x03 line.long 0x00 "RM_L4SEC_DES3DES_CONTEXT,This register contains dedicated DES3DES context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x1BC++0x03 line.long 0x00 "RM_L4SEC_FPKA_CONTEXT,This register contains dedicated FPKA context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_NONRETAINED_BANK,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_NONRETAINED_BANK_0,LOSTMEM_NONRETAINED_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x1C4++0x03 line.long 0x00 "RM_L4SEC_RNG_CONTEXT,This register contains dedicated RNG context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x1CC++0x0B line.long 0x00 "RM_L4SEC_SHA2MD51_CONTEXT,This register contains dedicated SHA2MD51 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" line.long 0x04 "PM_L4PER2_UART7_WKDEP,This register controls wakeup dependency based on UART7 service requests" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "WKUPDEP_UART7_EVE4,Wakeup dependency from UART7 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_EVE4_0,WKUPDEP_UART7_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_UART7_EVE3,Wakeup dependency from UART7 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_EVE3_0,WKUPDEP_UART7_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_UART7_EVE2,Wakeup dependency from UART7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_EVE2_0,WKUPDEP_UART7_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_UART7_EVE1,Wakeup dependency from UART7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_EVE1_0,WKUPDEP_UART7_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_UART7_DSP2,Wakeup dependency from UART7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_DSP2_0,WKUPDEP_UART7_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_UART7_IPU1,Wakeup dependency from UART7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_IPU1_0,WKUPDEP_UART7_IPU1_1" bitfld.long 0x04 3. "WKUPDEP_UART7_SDMA,Wakeup dependency from UART7 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_SDMA_0,WKUPDEP_UART7_SDMA_1" newline bitfld.long 0x04 2. "WKUPDEP_UART7_DSP1,Wakeup dependency from UART7 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_DSP1_0,WKUPDEP_UART7_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_UART7_IPU2,Wakeup dependency from UART7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_IPU2_0,WKUPDEP_UART7_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_UART7_MPU,Wakeup dependency from UART7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_MPU_0,WKUPDEP_UART7_MPU_1" line.long 0x08 "RM_L4PER2_UART7_CONTEXT,This register contains dedicated UART7 context statuses" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," bitfld.long 0x08 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x08 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x08 0. "RESERVED," "0,1" group.long 0x1DC++0x1B line.long 0x00 "RM_L4SEC_DMA_CRYPTO_CONTEXT,This register contains dedicated DMA_CRYPTO context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" line.long 0x04 "PM_L4PER2_UART8_WKDEP,This register controls wakeup dependency based on UART8 service requests" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "WKUPDEP_UART8_EVE4,Wakeup dependency from UART8 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_EVE4_0,WKUPDEP_UART8_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_UART8_EVE3,Wakeup dependency from UART8 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_EVE3_0,WKUPDEP_UART8_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_UART8_EVE2,Wakeup dependency from UART8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_EVE2_0,WKUPDEP_UART8_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_UART8_EVE1,Wakeup dependency from UART8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_EVE1_0,WKUPDEP_UART8_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_UART8_DSP2,Wakeup dependency from UART8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_DSP2_0,WKUPDEP_UART8_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_UART8_IPU1,Wakeup dependency from UART8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_IPU1_0,WKUPDEP_UART8_IPU1_1" bitfld.long 0x04 3. "WKUPDEP_UART8_SDMA,Wakeup dependency from UART8 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_SDMA_0,WKUPDEP_UART8_SDMA_1" newline bitfld.long 0x04 2. "WKUPDEP_UART8_DSP1,Wakeup dependency from UART8 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_DSP1_0,WKUPDEP_UART8_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_UART8_IPU2,Wakeup dependency from UART8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_IPU2_0,WKUPDEP_UART8_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_UART8_MPU,Wakeup dependency from UART8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_MPU_0,WKUPDEP_UART8_MPU_1" line.long 0x08 "RM_L4PER2_UART8_CONTEXT,This register contains dedicated UART8 context statuses" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," bitfld.long 0x08 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x08 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x08 0. "RESERVED," "0,1" line.long 0x0C "PM_L4PER2_UART9_WKDEP,This register controls wakeup dependency based on UART9 service requests" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED," bitfld.long 0x0C 9. "WKUPDEP_UART9_EVE4,Wakeup dependency from UART9 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_EVE4_0,WKUPDEP_UART9_EVE4_1" newline bitfld.long 0x0C 8. "WKUPDEP_UART9_EVE3,Wakeup dependency from UART9 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_EVE3_0,WKUPDEP_UART9_EVE3_1" bitfld.long 0x0C 7. "WKUPDEP_UART9_EVE2,Wakeup dependency from UART9 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_EVE2_0,WKUPDEP_UART9_EVE2_1" newline bitfld.long 0x0C 6. "WKUPDEP_UART9_EVE1,Wakeup dependency from UART9 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_EVE1_0,WKUPDEP_UART9_EVE1_1" bitfld.long 0x0C 5. "WKUPDEP_UART9_DSP2,Wakeup dependency from UART9 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_DSP2_0,WKUPDEP_UART9_DSP2_1" newline bitfld.long 0x0C 4. "WKUPDEP_UART9_IPU1,Wakeup dependency from UART9 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_IPU1_0,WKUPDEP_UART9_IPU1_1" bitfld.long 0x0C 3. "WKUPDEP_UART9_SDMA,Wakeup dependency from UART9 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_SDMA_0,WKUPDEP_UART9_SDMA_1" newline bitfld.long 0x0C 2. "WKUPDEP_UART9_DSP1,Wakeup dependency from UART4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_DSP1_0,WKUPDEP_UART9_DSP1_1" bitfld.long 0x0C 1. "WKUPDEP_UART9_IPU2,Wakeup dependency from UART4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_IPU2_0,WKUPDEP_UART9_IPU2_1" newline bitfld.long 0x0C 0. "WKUPDEP_UART9_MPU,Wakeup dependency from UART9 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_MPU_0,WKUPDEP_UART9_MPU_1" line.long 0x10 "RM_L4PER2_UART9_CONTEXT,This register contains dedicated UART9 context statuses" hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED," bitfld.long 0x10 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x10 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x10 0. "RESERVED," "0,1" line.long 0x14 "PM_L4PER2_DCAN2_WKDEP,This register controls wakeup dependency based on MCAN service requests" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," bitfld.long 0x14 9. "WKUPDEP_DCAN2_EVE4,Wakeup dependency from MCAN module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_EVE4_0,WKUPDEP_DCAN2_EVE4_1" newline bitfld.long 0x14 8. "WKUPDEP_DCAN2_EVE3,Wakeup dependency from MCAN module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_EVE3_0,WKUPDEP_DCAN2_EVE3_1" bitfld.long 0x14 7. "WKUPDEP_DCAN2_EVE2,Wakeup dependency from MCAN module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_EVE2_0,WKUPDEP_DCAN2_EVE2_1" newline bitfld.long 0x14 6. "WKUPDEP_DCAN2_EVE1,Wakeup dependency from MCAN module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_EVE1_0,WKUPDEP_DCAN2_EVE1_1" bitfld.long 0x14 5. "WKUPDEP_DCAN2_DSP2,Wakeup dependency from MCAN module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_DSP2_0,WKUPDEP_DCAN2_DSP2_1" newline bitfld.long 0x14 4. "WKUPDEP_DCAN2_IPU1,Wakeup dependency from MCAN module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_IPU1_0,WKUPDEP_DCAN2_IPU1_1" bitfld.long 0x14 3. "WKUPDEP_DCAN2_SDMA,Wakeup dependency from MCAN module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_SDMA_0,WKUPDEP_DCAN2_SDMA_1" newline bitfld.long 0x14 2. "WKUPDEP_DCAN2_DSP1,Wakeup dependency from MCAN module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_DSP1_0,WKUPDEP_DCAN2_DSP1_1" bitfld.long 0x14 1. "WKUPDEP_DCAN2_IPU2,Wakeup dependency from MCAN module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_IPU2_0,WKUPDEP_DCAN2_IPU2_1" newline bitfld.long 0x14 0. "WKUPDEP_DCAN2_MPU,Wakeup dependency from MCAN module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_MPU_0,WKUPDEP_DCAN2_MPU_1" line.long 0x18 "RM_L4PER2_DCAN2_CONTEXT,This register contains dedicated MCAN context statuses" hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED," bitfld.long 0x18 8. "LOSTMEM_DCAN_BANK,Specify if memory-based context in DCAN memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DCAN_BANK_0,LOSTMEM_DCAN_BANK_1" newline hexmask.long.byte 0x18 1.--7. 1. "RESERVED," bitfld.long 0x18 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x1FC++0x03 line.long 0x00 "RM_L4SEC_SHA2MD52_CONTEXT,This register contains dedicated SHA2MD52 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" width 0x0B tree.end tree "LDC" base ad:0x52020100 rgroup.long 0x00++0x2B line.long 0x00 "LDC_PID,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "LDC_PCR,LDC Peripheral Control" hexmask.long.word 0x04 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 16.--17. "STANDBYMODE,Configuration of the local initiator state management mode" "0,1,2,3" newline rbitfld.long 0x04 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 11. "SCS_SUPPORT,Reports '1' if SCS feature is supported by LDC" "0,1" newline bitfld.long 0x04 10. "AFF_EXPANDEN,Enables expanded format of affine warp coefficients (A B D and E)" "A B D E are treated as S14Q12,A B D E are treated as S16Q12" bitfld.long 0x04 9. "CIRCEN,Enables circular addressing mode" "Disable circular addressing for input data,Enable circular addressing" newline bitfld.long 0x04 8. "SCSEN,Enable/Disable smart codec statistic (SCS) function" "Disable SCS,Enable SCS" bitfld.long 0x04 7. "PWARPEN,Enable perspective warp transform" "0,1" newline bitfld.long 0x04 5.--6. "BMODE,Bayer data format (only applicable when MODE=1)" "Unpacked 12-bit data in/out,Packed 12-bit data in/out,Packed 8-bit data in/out,A-law data in/out" bitfld.long 0x04 3.--4. "MODE," "YCbCr 4:2:2 Lens Distortion,Bayer chromatic aberration mode,?..." newline bitfld.long 0x04 2. "BUSY,Idle/busy status " "Idle,Busy.." bitfld.long 0x04 1. "LDMAPEN,LD Mapping Enable " "Disabled,Enabled" newline bitfld.long 0x04 0. "EN,Write 1 to start the function as specified in MODE" "0,1" line.long 0x08 "LDC_RD_BASE,LDC Read Frame Base" line.long 0x0C "LDC_RD_OFST," rbitfld.long 0x0C 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x0C 16.--29. 1. "MOD,Sets the circular buffer size if circular buffering mode is used" newline hexmask.long.word 0x0C 0.--15. 1. "ROFST,Read frame line offset must be 16-byte aligned so internally [3:0] bits are hard-wired zero" line.long 0x10 "LDC_FRAME_SIZE,LDC Frame Size" rbitfld.long 0x10 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x10 16.--29. 1. "H,Frame number of lines" newline rbitfld.long 0x10 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x10 0.--13. 1. "W,Frame width" line.long 0x14 "LDC_INITXY,LDC Initial XY" rbitfld.long 0x14 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x14 16.--29. 1. "INITY,Output starting Y-coordinate (must be even)" newline rbitfld.long 0x14 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x14 0.--13. 1. "INITX,Output starting X-coordiinate (must be even)" line.long 0x18 "LDC_WR_BASE,LDC Write Frame Base" line.long 0x1C "LDC_WR_OFST,LDC Write Frame Line Offset" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 0.--15. 1. "WOFST,Write frame line offset must be 16-byte aligned so internally [3:0] bits are hard-wired zero" line.long 0x20 "LDC_420C_RD_BASE,LDC Read Frame Base For Cb/Cr in 420 Mode" line.long 0x24 "LDC_420C_WR_BASE,LDC Write Frame Base for Cb/Cr in 420 Mode" line.long 0x28 "LDC_CONFIG,LDC Configuration" hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 7. "CNST_MD,Constant output address mode" "0,1" newline bitfld.long 0x28 6. "YINT_TYP,Interpolation type for Y data " "bicubic,bilinear" bitfld.long 0x28 4.--5. "INITC,Initial color for LD back mapping (Bayer mode only) " "R,Gr,Gb,B" newline rbitfld.long 0x28 0.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x34++0x03 line.long 0x00 "LDC_BLOCK,LDC Block Size" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16.--19. "PIXPAD,Pixel pad (must be greater than 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "OBH,Output block height (must be 0 and even)" hexmask.long.byte 0x00 0.--7. 1. "OBW,Output block width (must be 0 and multiple of 8 in 422 mode or in 420 mode 16 or in Bayer mode 8 16 or 32 depending on Bayer format)" group.long 0x44++0x23 line.long 0x00 "LDC_AB,LDC Affine Transwarp A/B" hexmask.long.word 0x00 16.--31. 1. "B,Affine transwarp B (S16Q12)" hexmask.long.word 0x00 0.--15. 1. "A,Affine transwarp A (S16Q12)" line.long 0x04 "LDC_CD,LDC Affine Transwarp C/D" hexmask.long.word 0x04 16.--31. 1. "D,Affine transwarp D (S16Q12)" hexmask.long.word 0x04 0.--15. 1. "C,Affine transwarp C (S16Q3)" line.long 0x08 "LDC_EF,LDC Affine Transwarp EF" hexmask.long.word 0x08 16.--31. 1. "F,Affine transwarp F (S16Q3)" hexmask.long.word 0x08 0.--15. 1. "E,Affine transwarp E (S16Q12)" line.long 0x0C "LDC_GH,LDC Perspective Transformation Parameters. G and H" hexmask.long.word 0x0C 16.--31. 1. "H,Perspective Transformation H (S16Q23)" hexmask.long.word 0x0C 0.--15. 1. "G,Perspective Transformation G (S16Q23)" line.long 0x10 "LDC_SCS_CTL,Define number of regions and output divider for region based statistics" rbitfld.long 0x10 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x10 16.--29. 1. "SLICE_SIZE,Sets the number of output lines computed by LDC before the computed macroblock row statistics are transferred to system memory" newline hexmask.long.word 0x10 7.--15. 1. "RESERVED,Reserved" bitfld.long 0x10 5.--6. "REGION,Sets the number of regions in both directions for the region based statistics" "0,1,2,3" newline bitfld.long 0x10 0.--4. "ACCSHIFT,Sets the output divider for sum of pixels in a region and sum of squares of pixels in a region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "LDC_INPUT_FRAME_SIZE,Defines the total input frame size" rbitfld.long 0x14 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x14 16.--29. 1. "H,Height of input image" newline rbitfld.long 0x14 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x14 0.--13. 1. "W,Width of input image" line.long 0x18 "LDC_MESHTABLE_BASE,Read address for mesh offset table" line.long 0x1C "LDC_MESHTABLE_OFST,Defines the stride between rows for the offset table (in bytes)" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 0.--15. 1. "OFST,LDC Mesh table line offset must be 16-byte aligned so internally [3:0] bits are hard-wired zero" line.long 0x20 "LDC_MESHTABLE_CONFIG,Defines the downsampling factors used for the mesh offset tables" hexmask.long 0x20 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 0.--2. "M,Mesh table downsampling factor" "?,2 -..,4,8,16,32,64,128" width 0x0B tree.end tree "LVDSRX" base ad:0x52004000 rgroup.long 0x00++0x03 line.long 0x00 "LVDSRX_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" group.long 0x10++0x07 line.long 0x00 "LVDSRX_SYSCONFIG,Reserved" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "RESERVED," "RESERVED_0,RESERVED_1" line.long 0x04 "LVDSRX_CAMCFG,Camera port enable" hexmask.long.word 0x04 20.--31. 1. "RESERVED," bitfld.long 0x04 19. "CAM4TEST,Camera port #4 monitor" "CAM4TEST_0,CAM4TEST_1" newline bitfld.long 0x04 18. "CAM3TEST,Camera port #3 monitor" "CAM3TEST_0,CAM3TEST_1" bitfld.long 0x04 17. "CAM2TEST,Camera port #2 monitor" "CAM2TEST_0,CAM2TEST_1" newline bitfld.long 0x04 16. "CAM1TEST,Camera port #1 monitor" "CAM1TEST_0,CAM1TEST_1" hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 3. "CAM4ENA,Camera port #4 control" "CAM4ENA_0,CAM4ENA_1" bitfld.long 0x04 2. "CAM3ENA,Camera port #3 control" "CAM3ENA_0,CAM3ENA_1" newline bitfld.long 0x04 1. "CAM2ENA,Camera port #2 control" "CAM2ENA_0,CAM2ENA_1" bitfld.long 0x04 0. "CAM1ENA,Camera port #1 control" "CAM1ENA_0,CAM1ENA_1" group.long 0x1C++0xD3 line.long 0x00 "LVDSRX_IRQ_EOI,End Of Interrupt number specification" hexmask.long 0x00 3.--31. 1. "RESERVED," bitfld.long 0x00 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1,LINE_NUMBER_2,LINE_NUMBER_3,LINE_NUMBER_4,?,?,?" line.long 0x04 "LVDSRX_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line #0" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "CAM1_ERR7,sync detected timeout reached" "CAM1_ERR7_0,CAM1_ERR7_1" newline bitfld.long 0x04 8. "CAM1_ERR6,CRC error" "CAM1_ERR6_0,CAM1_ERR6_1" bitfld.long 0x04 7. "CAM1_ERR5,unexpected SOF" "CAM1_ERR5_0,CAM1_ERR5_1" newline bitfld.long 0x04 6. "CAM1_ERR4,unexpected SOL" "CAM1_ERR4_0,CAM1_ERR4_1" bitfld.long 0x04 5. "CAM1_ERR3,unexpected EOF" "CAM1_ERR3_0,CAM1_ERR3_1" newline bitfld.long 0x04 4. "CAM1_ERR2,unexpected EOL" "CAM1_ERR2_0,CAM1_ERR2_1" bitfld.long 0x04 3. "CAM1_ERR1,unexpected SOV" "CAM1_ERR1_0,CAM1_ERR1_1" newline bitfld.long 0x04 2. "CAM1_ERR0,EOX not received" "CAM1_ERR0_0,CAM1_ERR0_1" bitfld.long 0x04 1. "CAM1_EOF,End of frame timing" "CAM1_EOF_0,CAM1_EOF_1" newline bitfld.long 0x04 0. "CAM1_SOF,Start of frame timing" "CAM1_SOF_0,CAM1_SOF_1" line.long 0x08 "LVDSRX_IRQSTATUS_0,Per-event 'enabled' interrupt status vector. line #0" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "CAM1_ERR7,sync detected timeout reached" "CAM1_ERR7_0,CAM1_ERR7_1" newline bitfld.long 0x08 8. "CAM1_ERR6,CRC error" "CAM1_ERR6_0,CAM1_ERR6_1" bitfld.long 0x08 7. "CAM1_ERR5,unexpected SOF" "CAM1_ERR5_0,CAM1_ERR5_1" newline bitfld.long 0x08 6. "CAM1_ERR4,unexpected SOL" "CAM1_ERR4_0,CAM1_ERR4_1" bitfld.long 0x08 5. "CAM1_ERR3,unexpected EOF" "CAM1_ERR3_0,CAM1_ERR3_1" newline bitfld.long 0x08 4. "CAM1_ERR2,unexpected EOL" "CAM1_ERR2_0,CAM1_ERR2_1" bitfld.long 0x08 3. "CAM1_ERR1,unexpected SOV" "CAM1_ERR1_0,CAM1_ERR1_1" newline bitfld.long 0x08 2. "CAM1_ERR0,EOX not received" "CAM1_ERR0_0,CAM1_ERR0_1" bitfld.long 0x08 1. "CAM1_EOF,End of frame timing" "CAM1_EOF_0,CAM1_EOF_1" newline bitfld.long 0x08 0. "CAM1_SOF,Start of frame timing" "CAM1_SOF_0,CAM1_SOF_1" line.long 0x0C "LVDSRX_IRQENABLE_SET_0,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED," bitfld.long 0x0C 9. "CAM1_ERR7,sync detected timeout reached" "CAM1_ERR7_0,CAM1_ERR7_1" newline bitfld.long 0x0C 8. "CAM1_ERR6,CRC error" "CAM1_ERR6_0,CAM1_ERR6_1" bitfld.long 0x0C 7. "CAM1_ERR5,unexpected SOF" "CAM1_ERR5_0,CAM1_ERR5_1" newline bitfld.long 0x0C 6. "CAM1_ERR4,unexpected SOL" "CAM1_ERR4_0,CAM1_ERR4_1" bitfld.long 0x0C 5. "CAM1_ERR3,unexpected EOF" "CAM1_ERR3_0,CAM1_ERR3_1" newline bitfld.long 0x0C 4. "CAM1_ERR2,unexpected EOL" "CAM1_ERR2_0,CAM1_ERR2_1" bitfld.long 0x0C 3. "CAM1_ERR1,unexpected SOV" "CAM1_ERR1_0,CAM1_ERR1_1" newline bitfld.long 0x0C 2. "CAM1_ERR0,EOX not received" "CAM1_ERR0_0,CAM1_ERR0_1" bitfld.long 0x0C 1. "CAM1_EOF,End of frame timing" "CAM1_EOF_0,CAM1_EOF_1" newline bitfld.long 0x0C 0. "CAM1_SOF,Start of frame timing" "CAM1_SOF_0,CAM1_SOF_1" line.long 0x10 "LVDSRX_IRQENABLE_CLR_0,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED," bitfld.long 0x10 9. "CAM1_ERR7,sync detected timeout reached" "CAM1_ERR7_0,CAM1_ERR7_1" newline bitfld.long 0x10 8. "CAM1_ERR6,CRC error" "CAM1_ERR6_0,CAM1_ERR6_1" bitfld.long 0x10 7. "CAM1_ERR5,unexpected SOF" "CAM1_ERR5_0,CAM1_ERR5_1" newline bitfld.long 0x10 6. "CAM1_ERR4,unexpected SOL" "CAM1_ERR4_0,CAM1_ERR4_1" bitfld.long 0x10 5. "CAM1_ERR3,unexpected EOF" "CAM1_ERR3_0,CAM1_ERR3_1" newline bitfld.long 0x10 4. "CAM1_ERR2,unexpected EOL" "CAM1_ERR2_0,CAM1_ERR2_1" bitfld.long 0x10 3. "CAM1_ERR1,unexpected SOV" "CAM1_ERR1_0,CAM1_ERR1_1" newline bitfld.long 0x10 2. "CAM1_ERR0,EOX not received" "CAM1_ERR0_0,CAM1_ERR0_1" bitfld.long 0x10 1. "CAM1_EOF,End of frame timing" "CAM1_EOF_0,CAM1_EOF_1" newline bitfld.long 0x10 0. "CAM1_SOF,Start of frame timing" "CAM1_SOF_0,CAM1_SOF_1" line.long 0x14 "LVDSRX_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. line #1" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," bitfld.long 0x14 9. "CAM2_ERR7,sync detected timeout reached" "CAM2_ERR7_0,CAM2_ERR7_1" newline bitfld.long 0x14 8. "CAM2_ERR6,CRC error" "CAM2_ERR6_0,CAM2_ERR6_1" bitfld.long 0x14 7. "CAM2_ERR5,unexpected SOF" "CAM2_ERR5_0,CAM2_ERR5_1" newline bitfld.long 0x14 6. "CAM2_ERR4,unexpected SOL" "CAM2_ERR4_0,CAM2_ERR4_1" bitfld.long 0x14 5. "CAM2_ERR3,unexpected EOF" "CAM2_ERR3_0,CAM2_ERR3_1" newline bitfld.long 0x14 4. "CAM2_ERR2,unexpected EOL" "CAM2_ERR2_0,CAM2_ERR2_1" bitfld.long 0x14 3. "CAM2_ERR1,unexpected SOV" "CAM2_ERR1_0,CAM2_ERR1_1" newline bitfld.long 0x14 2. "CAM2_ERR0,EOX not received" "CAM2_ERR0_0,CAM2_ERR0_1" bitfld.long 0x14 1. "CAM2_EOF,End of frame timing" "CAM2_EOF_0,CAM2_EOF_1" newline bitfld.long 0x14 0. "CAM2_SOF,Start of frame timing" "CAM2_SOF_0,CAM2_SOF_1" line.long 0x18 "LVDSRX_IRQSTATUS_1,Per-event 'enabled' interrupt status vector. line #1" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," bitfld.long 0x18 9. "CAM2_ERR7,sync detected timeout reached" "CAM2_ERR7_0,CAM2_ERR7_1" newline bitfld.long 0x18 8. "CAM2_ERR6,CRC error" "CAM2_ERR6_0,CAM2_ERR6_1" bitfld.long 0x18 7. "CAM2_ERR5,unexpected SOF" "CAM2_ERR5_0,CAM2_ERR5_1" newline bitfld.long 0x18 6. "CAM2_ERR4,unexpected SOL" "CAM2_ERR4_0,CAM2_ERR4_1" bitfld.long 0x18 5. "CAM2_ERR3,unexpected EOF" "CAM2_ERR3_0,CAM2_ERR3_1" newline bitfld.long 0x18 4. "CAM2_ERR2,unexpected EOL" "CAM2_ERR2_0,CAM2_ERR2_1" bitfld.long 0x18 3. "CAM2_ERR1,unexpected SOV" "CAM2_ERR1_0,CAM2_ERR1_1" newline bitfld.long 0x18 2. "CAM2_ERR0,EOX not received" "CAM2_ERR0_0,CAM2_ERR0_1" bitfld.long 0x18 1. "CAM2_EOF,End of frame timing" "CAM2_EOF_0,CAM2_EOF_1" newline bitfld.long 0x18 0. "CAM2_SOF,Start of frame timing" "CAM2_SOF_0,CAM2_SOF_1" line.long 0x1C "LVDSRX_IRQENABLE_SET_1,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" hexmask.long.tbyte 0x1C 10.--31. 1. "RESERVED," bitfld.long 0x1C 9. "CAM2_ERR7,sync detected timeout reached" "CAM2_ERR7_0,CAM2_ERR7_1" newline bitfld.long 0x1C 8. "CAM2_ERR6,CRC error" "CAM2_ERR6_0,CAM2_ERR6_1" bitfld.long 0x1C 7. "CAM2_ERR5,unexpected SOF" "CAM2_ERR5_0,CAM2_ERR5_1" newline bitfld.long 0x1C 6. "CAM2_ERR4,unexpected SOL" "CAM2_ERR4_0,CAM2_ERR4_1" bitfld.long 0x1C 5. "CAM2_ERR3,unexpected EOF" "CAM2_ERR3_0,CAM2_ERR3_1" newline bitfld.long 0x1C 4. "CAM2_ERR2,unexpected EOL" "CAM2_ERR2_0,CAM2_ERR2_1" bitfld.long 0x1C 3. "CAM2_ERR1,unexpected SOV" "CAM2_ERR1_0,CAM2_ERR1_1" newline bitfld.long 0x1C 2. "CAM2_ERR0,EOX not received" "CAM2_ERR0_0,CAM2_ERR0_1" bitfld.long 0x1C 1. "CAM2_EOF,End of frame timing" "CAM2_EOF_0,CAM2_EOF_1" newline bitfld.long 0x1C 0. "CAM2_SOF,Start of frame timing" "CAM2_SOF_0,CAM2_SOF_1" line.long 0x20 "LVDSRX_IRQENABLE_CLR_1,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" hexmask.long.tbyte 0x20 10.--31. 1. "RESERVED," bitfld.long 0x20 9. "CAM2_ERR7,sync detected timeout reached" "CAM2_ERR7_0,CAM2_ERR7_1" newline bitfld.long 0x20 8. "CAM2_ERR6,CRC error" "CAM2_ERR6_0,CAM2_ERR6_1" bitfld.long 0x20 7. "CAM2_ERR5,unexpected SOF" "CAM2_ERR5_0,CAM2_ERR5_1" newline bitfld.long 0x20 6. "CAM2_ERR4,unexpected SOL" "CAM2_ERR4_0,CAM2_ERR4_1" bitfld.long 0x20 5. "CAM2_ERR3,unexpected EOF" "CAM2_ERR3_0,CAM2_ERR3_1" newline bitfld.long 0x20 4. "CAM2_ERR2,unexpected EOL" "CAM2_ERR2_0,CAM2_ERR2_1" bitfld.long 0x20 3. "CAM2_ERR1,unexpected SOV" "CAM2_ERR1_0,CAM2_ERR1_1" newline bitfld.long 0x20 2. "CAM2_ERR0,EOX not received" "CAM2_ERR0_0,CAM2_ERR0_1" bitfld.long 0x20 1. "CAM2_EOF,End of frame timing" "CAM2_EOF_0,CAM2_EOF_1" newline bitfld.long 0x20 0. "CAM2_SOF,Start of frame timing" "CAM2_SOF_0,CAM2_SOF_1" line.long 0x24 "LVDSRX_IRQSTATUS_RAW2_2,Per-event raw interrupt status vector. line #2" hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED," bitfld.long 0x24 9. "CAM3_ERR7,sync detected timeout reached" "CAM3_ERR7_0,CAM3_ERR7_1" newline bitfld.long 0x24 8. "CAM3_ERR6,CRC error" "CAM3_ERR6_0,CAM3_ERR6_1" bitfld.long 0x24 7. "CAM3_ERR5,unexpected SOF" "CAM3_ERR5_0,CAM3_ERR5_1" newline bitfld.long 0x24 6. "CAM3_ERR4,unexpected SOL" "CAM3_ERR4_0,CAM3_ERR4_1" bitfld.long 0x24 5. "CAM3_ERR3,unexpected EOF" "CAM3_ERR3_0,CAM3_ERR3_1" newline bitfld.long 0x24 4. "CAM3_ERR2,unexpected EOL" "CAM3_ERR2_0,CAM3_ERR2_1" bitfld.long 0x24 3. "CAM3_ERR1,unexpected SOV" "CAM3_ERR1_0,CAM3_ERR1_1" newline bitfld.long 0x24 2. "CAM3_ERR0,EOX not received" "CAM3_ERR0_0,CAM3_ERR0_1" bitfld.long 0x24 1. "CAM3_EOF,End of frame timing" "CAM3_EOF_0,CAM3_EOF_1" newline bitfld.long 0x24 0. "CAM3_SOF,Start of frame timing" "CAM3_SOF_0,CAM3_SOF_1" line.long 0x28 "LVDSRX_IRQSTATUS_2,Per-event 'enabled' interrupt status vector. line #2" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED," bitfld.long 0x28 9. "CAM3_ERR7,sync detected timeout reached" "CAM3_ERR7_0,CAM3_ERR7_1" newline bitfld.long 0x28 8. "CAM3_ERR6,CRC error" "CAM3_ERR6_0,CAM3_ERR6_1" bitfld.long 0x28 7. "CAM3_ERR5,unexpected SOF" "CAM3_ERR5_0,CAM3_ERR5_1" newline bitfld.long 0x28 6. "CAM3_ERR4,unexpected SOL" "CAM3_ERR4_0,CAM3_ERR4_1" bitfld.long 0x28 5. "CAM3_ERR3,unexpected EOF" "CAM3_ERR3_0,CAM3_ERR3_1" newline bitfld.long 0x28 4. "CAM3_ERR2,unexpected EOL" "CAM3_ERR2_0,CAM3_ERR2_1" bitfld.long 0x28 3. "CAM3_ERR1,unexpected SOV" "CAM3_ERR1_0,CAM3_ERR1_1" newline bitfld.long 0x28 2. "CAM3_ERR0,EOX not received" "CAM3_ERR0_0,CAM3_ERR0_1" bitfld.long 0x28 1. "CAM3_EOF,End of frame timing" "CAM3_EOF_0,CAM3_EOF_1" newline bitfld.long 0x28 0. "CAM3_SOF,Start of frame timing" "CAM3_SOF_0,CAM3_SOF_1" line.long 0x2C "LVDSRX_IRQENABLE_SET_2,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" hexmask.long.tbyte 0x2C 10.--31. 1. "RESERVED," bitfld.long 0x2C 9. "CAM3_ERR7,sync detected timeout reached" "CAM3_ERR7_0,CAM3_ERR7_1" newline bitfld.long 0x2C 8. "CAM3_ERR6,CRC error" "CAM3_ERR6_0,CAM3_ERR6_1" bitfld.long 0x2C 7. "CAM3_ERR5,unexpected SOF" "CAM3_ERR5_0,CAM3_ERR5_1" newline bitfld.long 0x2C 6. "CAM3_ERR4,unexpected SOL" "CAM3_ERR4_0,CAM3_ERR4_1" bitfld.long 0x2C 5. "CAM3_ERR3,unexpected EOF" "CAM3_ERR3_0,CAM3_ERR3_1" newline bitfld.long 0x2C 4. "CAM3_ERR2,unexpected EOL" "CAM3_ERR2_0,CAM3_ERR2_1" bitfld.long 0x2C 3. "CAM3_ERR1,unexpected SOV" "CAM3_ERR1_0,CAM3_ERR1_1" newline bitfld.long 0x2C 2. "CAM3_ERR0,EOX not received" "CAM3_ERR0_0,CAM3_ERR0_1" bitfld.long 0x2C 1. "CAM3_EOF,End of frame timing" "CAM3_EOF_0,CAM3_EOF_1" newline bitfld.long 0x2C 0. "CAM3_SOF,Start of frame timing" "CAM3_SOF_0,CAM3_SOF_1" line.long 0x30 "LVDSRX_IRQENABLE_CLR_2,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" hexmask.long.tbyte 0x30 10.--31. 1. "RESERVED," bitfld.long 0x30 9. "CAM3_ERR7,sync detected timeout reached" "CAM3_ERR7_0,CAM3_ERR7_1" newline bitfld.long 0x30 8. "CAM3_ERR6,CRC error" "CAM3_ERR6_0,CAM3_ERR6_1" bitfld.long 0x30 7. "CAM3_ERR5,unexpected SOF" "CAM3_ERR5_0,CAM3_ERR5_1" newline bitfld.long 0x30 6. "CAM3_ERR4,unexpected SOL" "CAM3_ERR4_0,CAM3_ERR4_1" bitfld.long 0x30 5. "CAM3_ERR3,unexpected EOF" "CAM3_ERR3_0,CAM3_ERR3_1" newline bitfld.long 0x30 4. "CAM3_ERR2,unexpected EOL" "CAM3_ERR2_0,CAM3_ERR2_1" bitfld.long 0x30 3. "CAM3_ERR1,unexpected SOV" "CAM3_ERR1_0,CAM3_ERR1_1" newline bitfld.long 0x30 2. "CAM3_ERR0,EOX not received" "CAM3_ERR0_0,CAM3_ERR0_1" bitfld.long 0x30 1. "CAM3_EOF,End of frame timing" "CAM3_EOF_0,CAM3_EOF_1" newline bitfld.long 0x30 0. "CAM3_SOF,Start of frame timing" "CAM3_SOF_0,CAM3_SOF_1" line.long 0x34 "LVDSRX_IRQSTATUS_RAW_3,Per-event raw interrupt status vector. line #3" hexmask.long.tbyte 0x34 10.--31. 1. "RESERVED," bitfld.long 0x34 9. "CAM4_ERR7,sync detected timeout reached" "CAM4_ERR7_0,CAM4_ERR7_1" newline bitfld.long 0x34 8. "CAM4_ERR6,CRC error" "CAM4_ERR6_0,CAM4_ERR6_1" bitfld.long 0x34 7. "CAM4_ERR5,unexpected SOF" "CAM4_ERR5_0,CAM4_ERR5_1" newline bitfld.long 0x34 6. "CAM4_ERR4,unexpected SOL" "CAM4_ERR4_0,CAM4_ERR4_1" bitfld.long 0x34 5. "CAM4_ERR3,unexpected EOF" "CAM4_ERR3_0,CAM4_ERR3_1" newline bitfld.long 0x34 4. "CAM4_ERR2,unexpected EOL" "CAM4_ERR2_0,CAM4_ERR2_1" bitfld.long 0x34 3. "CAM5_ERR1,unexpected SOV" "CAM5_ERR1_0,CAM5_ERR1_1" newline bitfld.long 0x34 2. "CAM4_ERR0,EOX not received" "CAM4_ERR0_0,CAM4_ERR0_1" bitfld.long 0x34 1. "CAM4_EOF,End of frame timing" "CAM4_EOF_0,CAM4_EOF_1" newline bitfld.long 0x34 0. "CAM4_SOF,Start of frame timing" "CAM4_SOF_0,CAM4_SOF_1" line.long 0x38 "LVDSRX_IRQSTATUS_3,Per-event 'enabled' interrupt status vector. line #3" hexmask.long.tbyte 0x38 10.--31. 1. "RESERVED," bitfld.long 0x38 9. "CAM4_ERR7,sync detected timeout reached" "CAM4_ERR7_0,CAM4_ERR7_1" newline bitfld.long 0x38 8. "CAM4_ERR6,CRC error" "CAM4_ERR6_0,CAM4_ERR6_1" bitfld.long 0x38 7. "CAM4_ERR5,unexpected SOF" "CAM4_ERR5_0,CAM4_ERR5_1" newline bitfld.long 0x38 6. "CAM4_ERR4,unexpected SOL" "CAM4_ERR4_0,CAM4_ERR4_1" bitfld.long 0x38 5. "CAM4_ERR3,unexpected EOF" "CAM4_ERR3_0,CAM4_ERR3_1" newline bitfld.long 0x38 4. "CAM4_ERR2,unexpected EOL" "CAM4_ERR2_0,CAM4_ERR2_1" bitfld.long 0x38 3. "CAM4_ERR1,unexpected SOV" "CAM4_ERR1_0,CAM4_ERR1_1" newline bitfld.long 0x38 2. "CAM4_ERR0,EOX not received" "CAM4_ERR0_0,CAM4_ERR0_1" bitfld.long 0x38 1. "CAM4_EOF,End of frame timing" "CAM4_EOF_0,CAM4_EOF_1" newline bitfld.long 0x38 0. "CAM4_SOF,Start of frame timing" "CAM4_SOF_0,CAM4_SOF_1" line.long 0x3C "LVDSRX_IRQENABLE_SET_3,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" hexmask.long.tbyte 0x3C 10.--31. 1. "RESERVED," bitfld.long 0x3C 9. "CAM4_ERR7,sync detected timeout reached" "CAM4_ERR7_0,CAM4_ERR7_1" newline bitfld.long 0x3C 8. "CAM4_ERR6,CRC error" "CAM4_ERR6_0,CAM4_ERR6_1" bitfld.long 0x3C 7. "CAM4_ERR5,unexpected SOF" "CAM4_ERR5_0,CAM4_ERR5_1" newline bitfld.long 0x3C 6. "CAM4_ERR4,unexpected SOL" "CAM4_ERR4_0,CAM4_ERR4_1" bitfld.long 0x3C 5. "CAM4_ERR3,unexpected EOF" "CAM4_ERR3_0,CAM4_ERR3_1" newline bitfld.long 0x3C 4. "CAM4_ERR2,unexpected EOL" "CAM4_ERR2_0,CAM4_ERR2_1" bitfld.long 0x3C 3. "CAM4_ERR1,unexpected SOV" "CAM4_ERR1_0,CAM4_ERR1_1" newline bitfld.long 0x3C 2. "CAM4_ERR0,EOX not received" "CAM4_ERR0_0,CAM4_ERR0_1" bitfld.long 0x3C 1. "CAM4_EOF,End of frame timing" "CAM4_EOF_0,CAM4_EOF_1" newline bitfld.long 0x3C 0. "CAM4_SOF,Start of frame timing" "CAM4_SOF_0,CAM4_SOF_1" line.long 0x40 "LVDSRX_IRQENABLE_CLR_3,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" hexmask.long.tbyte 0x40 10.--31. 1. "RESERVED," bitfld.long 0x40 9. "CAM4_ERR7,sync detected timeout reached" "CAM4_ERR7_0,CAM4_ERR7_1" newline bitfld.long 0x40 8. "CAM4_ERR6,CRC error" "CAM4_ERR6_0,CAM4_ERR6_1" bitfld.long 0x40 7. "CAM4_ERR5,unexpected SOF" "CAM4_ERR5_0,CAM4_ERR5_1" newline bitfld.long 0x40 6. "CAM4_ERR4,unexpected SOL" "CAM4_ERR4_0,CAM4_ERR4_1" bitfld.long 0x40 5. "CAM4_ERR3,unexpected EOF" "CAM4_ERR3_0,CAM4_ERR3_1" newline bitfld.long 0x40 4. "CAM4_ERR2,unexpected EOL" "CAM4_ERR2_0,CAM4_ERR2_1" bitfld.long 0x40 3. "CAM4_ERR1,unexpected SOV" "CAM4_ERR1_0,CAM4_ERR1_1" newline bitfld.long 0x40 2. "CAM4_ERR0,EOX not received" "CAM4_ERR0_0,CAM4_ERR0_1" bitfld.long 0x40 1. "CAM4_EOF,End of frame timing" "CAM4_EOF_0,CAM4_EOF_1" newline bitfld.long 0x40 0. "CAM4_SOF,Start of frame timing" "CAM4_SOF_0,CAM4_SOF_1" line.long 0x44 "LVDSRX_CAM1_CFG,CAM output port #1 configuration This register associate one bit for each context in order to enable/disable each context individually" rbitfld.long 0x44 31. "RESERVED," "0,1" bitfld.long 0x44 28.--30. "NUM_LANE4,Number of lanes of PHY4 when NUM_PHY 3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x44 27. "RESERVED," "0,1" bitfld.long 0x44 24.--26. "NUM_LANE3,Number of lanes of PHY3 when NUM_PHY 2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x44 23. "RESERVED," "0,1" bitfld.long 0x44 20.--22. "NUM_LANE2,Number of lanes of PHY2 when NUM_PHY 1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x44 19. "RESERVED," "0,1" bitfld.long 0x44 16.--18. "NUM_LANE1,Number of lanes of PHY1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x44 15. "ALIGN,MSB LSB alignment for output pixel data" "LSB align,MSB align" bitfld.long 0x44 14. "DENDIAN,Transmit format of none SYNC area" "Little endian,big endian" newline bitfld.long 0x44 13. "FILEN," "0,1" bitfld.long 0x44 12. "CRCEN," "0,1" newline bitfld.long 0x44 11. "SENDIAN,Transmit format of SYNC area" "Little endian,big endian" bitfld.long 0x44 8.--10. "PIX_WIDTH,Word width of recovered parallel data" "8-BITS,10-BITS,12-BITS,14-BITS,16-BITS 5-7:..,?..." newline bitfld.long 0x44 7. "FRSTAT_INIT,Specifies Initial frame state in mode2 mode4 mod5 and mode8" "0,1" bitfld.long 0x44 4.--6. "NUMPHY,Number of PHYs 0 ~ 4 is available" "0,1,2,3,4,5,6,7" newline bitfld.long 0x44 0.--3. "OP_MODE,Protocol selection" "Serial LVDS mode 1,Serial LVDS mode 2,Serial LVDS mode 3,Serial LVDS mode 4,Serial LVDS mode 5,Serial LVDS mode 6,Serial LVDS mode 7,Serial LVDS mode 8,Serial LVDS mode 9 9-15: Reserved,?..." line.long 0x48 "LVDSRX_CAM1_FRMSIZE,CAM port #1 frame X*Y width" hexmask.long.word 0x48 16.--31. 1. "FRWIDTH,Frame size in number of image lines" hexmask.long.word 0x48 0.--15. 1. "LNWIDTH,Image line width in number of data words" line.long 0x4C "LVDSRX_CAM1_MAXWIDTH,CAM port #1 maximum line width" hexmask.long.word 0x4C 16.--31. 1. "RESERVED," hexmask.long.word 0x4C 0.--15. 1. "MAXWIDTH,The maximum line width expected in number of pixels" line.long 0x50 "LVDSRX_CAM1_SYNCSOF,Specifies SYNC pattern" hexmask.long.word 0x50 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x50 0.--15. 1. "SOFPTN,Specifies SOF(Start Of Frame) sync pattern" line.long 0x54 "LVDSRX_CAM1_SYNCEOF,Specifies SYNC pattern" hexmask.long.word 0x54 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x54 0.--15. 1. "SOFPTN,Specifies SOF(End Of Frame) sync pattern" line.long 0x58 "LVDSRX_CAM1_SYNCSOL,Specifies SYNC pattern" hexmask.long.word 0x58 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x58 0.--15. 1. "SOFPTN,Specifies SOF(Start Of Line) sync pattern" line.long 0x5C "LVDSRX_CAM1_SYNCEOL,Specifies SYNC pattern" hexmask.long.word 0x5C 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x5C 0.--15. 1. "SOFPTN,Specifies SOF(End Of Line) sync pattern" line.long 0x60 "LVDSRX_CAM1_SYNCSOV,Specifies SYNC pattern" hexmask.long.word 0x60 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x60 0.--15. 1. "SOFPTN,Specifies SOF(Start Of V-blanking) sync pattern" line.long 0x64 "LVDSRX_CAM2_CFG,CAM output port #2 configuration This register associate one bit for each context in order to enable/disable each context individually" rbitfld.long 0x64 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x64 24.--26. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x64 23. "RESERVED," "0,1" bitfld.long 0x64 20.--22. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x64 19. "RESERVED," "0,1" bitfld.long 0x64 16.--18. "NUM_LANE,Number of lanes of PHY2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x64 15. "ALIGN,MSB LSB alignment for output pixel data" "LSB align,MSB align" bitfld.long 0x64 14. "DENDIAN,Transmit format of none SYNC area" "Little endian,big endian" newline bitfld.long 0x64 13. "FILEN," "0,1" bitfld.long 0x64 12. "CRCEN," "0,1" newline bitfld.long 0x64 11. "SENDIAN,Transmit format of SYNC area" "Little endian,big endian" bitfld.long 0x64 8.--10. "PIX_WIDTH,Word width of recovered parallel data" "8-BITS,10-BITS,12-BITS,14-BITS,16-BITS 5-7:..,?..." newline bitfld.long 0x64 7. "FRSTAT_INIT,Specifies Initial frame state in mode2 mode4 mod5 and mode8" "0,1" rbitfld.long 0x64 6. "RESERVED," "0,1" newline bitfld.long 0x64 4.--5. "NUMPHY,Number of PHYs 0 ~ 1 is available" "0,1,2,3" bitfld.long 0x64 0.--3. "OP_MODE,Protocol selection" "Serial LVDS mode 1,Serial LVDS mode 2,Serial LVDS mode 3,Serial LVDS mode 4,Serial LVDS mode 5,Serial LVDS mode 6,Serial LVDS mode 7,Serial LVDS mode 8,Serial LVDS mode 9 9-15: Reserved,?..." line.long 0x68 "LVDSRX_CAM2_FRMSIZE,CAM port #2 frame X*Y width" hexmask.long.word 0x68 16.--31. 1. "FRWIDTH,Frame size in number of image lines" hexmask.long.word 0x68 0.--15. 1. "LNWIDTH,Image line width in number of data words" line.long 0x6C "LVDSRX_CAM2_MAXWIDTH,CAM port #2 maximum line width" hexmask.long.word 0x6C 16.--31. 1. "RESERVED," hexmask.long.word 0x6C 0.--15. 1. "MAXWIDTH,The maximum line width expected in number of pixels" line.long 0x70 "LVDSRX_CAM2_SYNCSOF,Specifies SYNC pattern" hexmask.long.word 0x70 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x70 0.--15. 1. "SOFPTN,Specifies SOF(Start Of Frame) sync pattern" line.long 0x74 "LVDSRX_CAM2_SYNCEOF,Specifies SYNC pattern" hexmask.long.word 0x74 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x74 0.--15. 1. "SOFPTN,Specifies SOF(End Of Frame) sync pattern" line.long 0x78 "LVDSRX_CAM2_SYNCSOL,Specifies SYNC pattern" hexmask.long.word 0x78 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x78 0.--15. 1. "SOFPTN,Specifies SOF(Start Of Line) sync pattern" line.long 0x7C "LVDSRX_CAM2_SYNCEOL,Specifies SYNC pattern" hexmask.long.word 0x7C 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x7C 0.--15. 1. "SOFPTN,Specifies SOF(End Of Line) sync pattern" line.long 0x80 "LVDSRX_CAM2_SYNCSOV,Specifies SYNC pattern" hexmask.long.word 0x80 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x80 0.--15. 1. "SOFPTN,Specifies SOF(Start Of V-blanking) sync pattern" line.long 0x84 "LVDSRX_CAM3_CFG,CAM output port #3 configuration This register associate one bit for each context in order to enable/disable each context individually" hexmask.long.word 0x84 23.--31. 1. "RESERVED," bitfld.long 0x84 20.--22. "NUM_LANE2,Number of lanes of PHY4 when NUM_PHY 1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x84 19. "RESERVED," "0,1" bitfld.long 0x84 16.--18. "NUM_LANE1,Number of lanes of PHY3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x84 15. "ALIGN,MSB LSB alignment for output pixel data" "LSB align,MSB align" bitfld.long 0x84 14. "DENDIAN,Transmit format of none SYNC area" "Little endian,big endian" newline bitfld.long 0x84 13. "FILEN," "0,1" bitfld.long 0x84 12. "CRCEN," "0,1" newline bitfld.long 0x84 11. "SENDIAN,Transmit format of SYNC area" "Little endian,big endian" bitfld.long 0x84 8.--10. "PIX_WIDTH,Word width of recovered parallel data" "8-BITS,10-BITS,12-BITS,14-BITS,16-BITS 5-7:..,?..." newline bitfld.long 0x84 7. "FRSTAT_INIT,Specifies Initial frame state in mode2 mode4 mod5 and mode8" "0,1" rbitfld.long 0x84 6. "RESERVED," "0,1" newline bitfld.long 0x84 4.--5. "NUMPHY,Number of PHYs 0 1 2 is available" "0,1,2,3" bitfld.long 0x84 0.--3. "OP_MODE,Protocol selection" "Serial LVDS mode 1,Serial LVDS mode 2,Serial LVDS mode 3,Serial LVDS mode 4,Serial LVDS mode 5,Serial LVDS mode 6,Serial LVDS mode 7,Serial LVDS mode 8,Serial LVDS mode 9 9-15: Reserved,?..." line.long 0x88 "LVDSRX_CAM3_FRMSIZE,CAM port #3 frame X*Y width" hexmask.long.word 0x88 16.--31. 1. "FRWIDTH,Frame size in number of image lines" hexmask.long.word 0x88 0.--15. 1. "LNWIDTH,Image line width in number of data words" line.long 0x8C "LVDSRX_CAM3_MAXWIDTH,CAM port #3 maximum line width" hexmask.long.word 0x8C 16.--31. 1. "RESERVED," hexmask.long.word 0x8C 0.--15. 1. "MAXWIDTH,The maximum line width expected in number of pixels" line.long 0x90 "LVDSRX_CAM3_SYNCSOF,Specifies SYNC pattern" hexmask.long.word 0x90 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x90 0.--15. 1. "SOFPTN,Specifies SOF(Start Of Frame) sync pattern" line.long 0x94 "LVDSRX_CAM3_SYNCEOF,Specifies SYNC pattern" hexmask.long.word 0x94 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x94 0.--15. 1. "SOFPTN,Specifies SOF(End Of Frame) sync pattern" line.long 0x98 "LVDSRX_CAM3_SYNCSOL,Specifies SYNC pattern" hexmask.long.word 0x98 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x98 0.--15. 1. "SOFPTN,Specifies SOF(Start Of Line) sync pattern" line.long 0x9C "LVDSRX_CAM3_SYNCEOL,Specifies SYNC pattern" hexmask.long.word 0x9C 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x9C 0.--15. 1. "SOFPTN,Specifies SOF(End Of Line) sync pattern" line.long 0xA0 "LVDSRX_CAM3_SYNCSOV,Specifies SYNC pattern" hexmask.long.word 0xA0 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0xA0 0.--15. 1. "SOFPTN,Specifies SOF(Start Of V-blanking) sync pattern" line.long 0xA4 "LVDSRX_CAM4_CFG,CAM output port #4 configuration This register associate one bit for each context in order to enable/disable each context individually" hexmask.long.word 0xA4 19.--31. 1. "RESERVED," bitfld.long 0xA4 16.--18. "NUM_LANE,Number of lanes of PHY4" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA4 15. "ALIGN,MSB LSB alignment for output pixel data" "LSB align,MSB align" bitfld.long 0xA4 14. "DENDIAN,Transmit format of none SYNC area" "Little endian,big endian" newline bitfld.long 0xA4 13. "FILEN," "0,1" bitfld.long 0xA4 12. "CRCEN," "0,1" newline bitfld.long 0xA4 11. "SENDIAN,Transmit format of SYNC area" "Little endian,big endian" bitfld.long 0xA4 8.--10. "PIX_WIDTH,Word width of recovered parallel data" "8-BITS,10-BITS,12-BITS,14-BITS,16-BITS 5-7:..,?..." newline bitfld.long 0xA4 7. "FRSTAT_INIT,Specifies Initial frame state in mode2 mode4 mod5 and mode8" "0,1" rbitfld.long 0xA4 5.--6. "RESERVED," "0,1,2,3" newline bitfld.long 0xA4 4. "NUMPHY,Number of PHYs 0 1 is available" "0,1" bitfld.long 0xA4 0.--3. "OP_MODE,Protocol selection" "Serial LVDS mode 1,Serial LVDS mode 2,Serial LVDS mode 3,Serial LVDS mode 4,Serial LVDS mode 5,Serial LVDS mode 6,Serial LVDS mode 7,Serial LVDS mode 8,Serial LVDS mode 9 9-13: Reserved,?,?,?,?,?,CMOS parallel IF (CCIR656 embeded sync),CMOS parallel IF (extenal HSYNC/VSYNC) When in.." line.long 0xA8 "LVDSRX_CAM4_FRMSIZE,CAM port #4 frame X*Y width" hexmask.long.word 0xA8 16.--31. 1. "FRWIDTH,Frame size in number of image lines" hexmask.long.word 0xA8 0.--15. 1. "LNWIDTH,Image line width in number of data words" line.long 0xAC "LVDSRX_CAM4_MAXWIDTH,CAM port #4 maximum line width" hexmask.long.word 0xAC 16.--31. 1. "RESERVED," hexmask.long.word 0xAC 0.--15. 1. "MAXWIDTH,The maximum line width expected in number of pixels" line.long 0xB0 "LVDSRX_CAM4_SYNCSOF,Specifies SYNC pattern" hexmask.long.word 0xB0 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0xB0 0.--15. 1. "SOFPTN,Specifies SOF(Start Of Frame) sync pattern" line.long 0xB4 "LVDSRX_CAM4_SYNCEOF,Specifies SYNC pattern" hexmask.long.word 0xB4 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0xB4 0.--15. 1. "SOFPTN,Specifies SOF(End Of Frame) sync pattern" line.long 0xB8 "LVDSRX_CAM4_SYNCSOL,Specifies SYNC pattern" hexmask.long.word 0xB8 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0xB8 0.--15. 1. "SOFPTN,Specifies SOF(Start Of Line) sync pattern" line.long 0xBC "LVDSRX_CAM4_SYNCEOL,Specifies SYNC pattern" hexmask.long.word 0xBC 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0xBC 0.--15. 1. "SOFPTN,Specifies SOF(End Of Line) sync pattern" line.long 0xC0 "LVDSRX_CAM4_SYNCSOV,Specifies SYNC pattern" hexmask.long.word 0xC0 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0xC0 0.--15. 1. "SOFPTN,Specifies SOF(Start Of V-blanking) sync pattern" line.long 0xC4 "LVDSRX_WDRCFG," hexmask.long.tbyte 0xC4 12.--31. 1. "RESERVED," bitfld.long 0xC4 8.--11. "PIX_WIDTH,Word width after de-companded" "12-BITS,13-BITS,14-BITS,15-BITS,16-BITS,17-BITS,18-BITS,19-BITS,20-BITS 9-15:..,?..." newline rbitfld.long 0xC4 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0xC4 4. "WDRMODE,WDR mode select" "de-companding,bit interlaced format Not alloweed to.." newline bitfld.long 0xC4 3. "WDRENA4,WDR mode enable for CAM port #4" "disable,enable WDR function.." bitfld.long 0xC4 2. "WDRENA3,WDR mode enable for CAM port #3" "disable,enable WDR function.." newline bitfld.long 0xC4 1. "WDRENA2,WDR mode enable for CAM port #2" "disable,enable WDR function.." bitfld.long 0xC4 0. "WDRENA1,WDR mode enable for CAM port #1" "disable,enable WDR function.." line.long 0xC8 "LVDSRX_WDRGN,WDR gain configuration" hexmask.long.word 0xC8 22.--31. 1. "RESERVED," bitfld.long 0xC8 16.--21. "WDRNPXY1,Specifies the pixel level for area #1 knee point inX/ Y axis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0xC8 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0xC8 8.--11. "WDRGN4,Specifies the gain for area #4 Gain = 1/2^WDRGN4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xC8 4.--7. "WDRGN3,Specifies the gain for area #3 Gain = 1/2^WDRGN3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0xC8 0.--3. "WDRGN2,Specifies the gain for area #2 Gain = 1/2^WDRGN2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0xCC "LVDSRX_WDRKP1,WDR knee point configuration" rbitfld.long 0xCC 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0xCC 16.--25. 1. "WDRNPY3,Specifies the pixel level for area #3 knee point in Y axis" newline rbitfld.long 0xCC 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0xCC 0.--9. 1. "WDRNPY2,Specifies the pixel level for area #2 knee point in Y axis" line.long 0xD0 "LVDSRX_WDRKP2," rbitfld.long 0xD0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xD0 16.--29. 1. "WDRNPX3,Specifies the pixel level for area #3 knee point in X axis" newline rbitfld.long 0xD0 14.--15. "RESERVED," "0,1,2,3" hexmask.long.word 0xD0 0.--13. 1. "WDRNPX2,Specifies the pixel level for area #2 knee point in X axis" rgroup.long 0x100++0x0F line.long 0x00 "LVDSRX_TEST1,When.CAM1TEST=1. PHY #1 data (8bitx4 lanes) can be monitored by this register" hexmask.long.byte 0x00 24.--31. 1. "LANE4,lane #4 byte data" hexmask.long.byte 0x00 16.--23. 1. "LANE3,lane #3 byte data" newline hexmask.long.byte 0x00 8.--15. 1. "LANE2,lane #2 byte data" hexmask.long.byte 0x00 0.--7. 1. "LANE1,lane #1 byte data" line.long 0x04 "LVDSRX_TEST2,When.CAM2TEST=1. PHY #2 data (8bitx4 lanes) can be monitored by this register" hexmask.long.byte 0x04 24.--31. 1. "LANE4,lane #4 byte data" hexmask.long.byte 0x04 16.--23. 1. "LANE3,lane #3 byte data" newline hexmask.long.byte 0x04 8.--15. 1. "LANE2,lane #2 byte data" hexmask.long.byte 0x04 0.--7. 1. "LANE1,lane #1 byte data" line.long 0x08 "LVDSRX_TEST3,When.CAM3TEST=1. PHY #3 data (8bitx4 lanes) can be monitored by this register" hexmask.long.byte 0x08 24.--31. 1. "LANE4,lane #4 byte data" hexmask.long.byte 0x08 16.--23. 1. "LANE3,lane #3 byte data" newline hexmask.long.byte 0x08 8.--15. 1. "LANE2,lane #2 byte data" hexmask.long.byte 0x08 0.--7. 1. "LANE1,lane #1 byte data" line.long 0x0C "LVDSRX_TEST4,When.CAM4TEST=1. PHY #4 data (8bitx4 lanes) can be monitored by this register" hexmask.long.byte 0x0C 24.--31. 1. "LANE4,lane #4 byte data" hexmask.long.byte 0x0C 16.--23. 1. "LANE3,lane #3 byte data" newline hexmask.long.byte 0x0C 8.--15. 1. "LANE2,lane #2 byte data" hexmask.long.byte 0x0C 0.--7. 1. "LANE1,lane #1 byte data" width 0x0B tree.end tree "MAILBOX1_TARG" base ad:0x4A0F5000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_H,Error reporting" line.long 0x14 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x14 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x14 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x14 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x14 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x14 0. "OCP_RESET,L3 Reset" "0,1" width 0x0B tree.end tree "MAILBOX2_TARG" base ad:0x4883B000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCAN" base ad:0x48480000 rgroup.long 0x1900++0x2B line.long 0x00 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the module" bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID" newline bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3" newline bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCAN module" hexmask.long 0x04 7.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" newline bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x04 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x04 3. "FREE," "0,1" newline bitfld.long 0x04 2. "SOFT,If FREE =" "debug suspend doesn't wait for Idle,debug suspend waits for Idle" newline bitfld.long 0x04 1. "CLKFACK,Clock Fast Ack" "0,1" newline bitfld.long 0x04 0. "RESET,Initiates a Soft Reset" "0,1" line.long 0x08 "MCANSS_STAT,Status Regsiter The Status register provide general status bits for the MCAN module" hexmask.long 0x08 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x08 3.--5. "STATE," "?,In transition to Idle,Idle,In transition to Active,?..." newline bitfld.long 0x08 2. "ENABLE_FDOE,Enable CAN FD configuration" "0,1" newline bitfld.long 0x08 1. "MEM_INIT_DONE," "0,1" newline bitfld.long 0x08 0. "RESET," "0,1" line.long 0x0C "MCANSS_ICS,Interrupt Clear Shadow Register Write to clear interrupt bits" hexmask.long 0x0C 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt status" "0,1" line.long 0x10 "MCANSS_IRS,Interrupt Raw Status Register Read raw interrupt status" hexmask.long 0x10 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt status" "0,1" line.long 0x14 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write to clear interrupt enable bits" hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" line.long 0x18 "MCANSS_IE,Interrupt Enable Register Read interrupt Enable" hexmask.long 0x18 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x18 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" line.long 0x1C "MCANSS_IES,Interrupt Enable Status Read Enabled Interrupts" hexmask.long 0x1C 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" line.long 0x20 "MCANSS_EOI,End Of Interrupt End of Interrupt Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x20 0.--7. 1. "EOI,Write with bit position of targetted interrupt (example: External TS is bit 0)" line.long 0x24 "MCANSS_EXT_TS_PRESCALER,External Timestamp PreScaler 0 External TImeStamp PreScaler" hexmask.long.byte 0x24 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value" line.long 0x28 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp PreScaler 0 Unserviced Interrupts Counter External TImeStamp Unserviced Interrupts Counter" hexmask.long 0x28 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of unserviced rollover interupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1980++0x03 line.long 0x00 "MCANSS_ECC_EOI,ECC EOI End Of Interrupt for ECC interrupt" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 8. "ECC_EOI,ECC EOI" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED,Reserved" rgroup.long 0x1A00++0x07 line.long 0x00 "MCAN_CREL,Core Release Register Release dependent constant (version + date)" bitfld.long 0x00 28.--31. "REL,Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "STEP,Step of Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "SUBSTEP,Sub-step of Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded" newline hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded" line.long 0x04 "MCAN_ENDN,Endian Register Constant 0x8765 4321" group.long 0x1A0C++0x23 line.long 0x00 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 23. "TDC,Transmitter Delay Compensation" "Transmitter Delay Compensation disabled,Transmitter Delay Compensation enabled" newline rbitfld.long 0x00 21.--22. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 16.--20. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0x00-0x1F)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--7. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0x0-0xF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0x0-0xF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "MCAN_TEST,Test Register Test mode selection" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 7. "RX,Receive Pin Monitors the actual value of the mcan_rx pin" "The CAN bus is dominant (mcan_rx = '0'),The CAN bus is recessive (mcan_rx = '1')" newline bitfld.long 0x04 5.--6. "TX,Control of Transmit Pin" "Reset value the mcan_tx pin controlled by the..,Sample Point can be monitored at the mcan_tx pin,Dominant ('0') level at the mcan_tx pin,Recessive ('1') at the mcan_tx pin" newline bitfld.long 0x04 4. "LBCK,Loop Back Mode" "Reset value Loop Back Mode is disabled,Loop Back Mode is enabled" newline rbitfld.long 0x04 0.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM" hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x08 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value" newline hexmask.long.byte 0x08 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter" line.long 0x0C "MCAN_CCCR,CC Control Register Operation mode configuration" hexmask.long.tbyte 0x0C 15.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame" "Transmit pause disabled,Transmit pause enabled" newline bitfld.long 0x0C 13. "EFBI,Edge Filtering during Bus Integration" "Edge filtering disabled,Two consecutive dominant t" newline bitfld.long 0x0C 12. "PXHD,Protocol Exception Handling Disable" "Protocol exception handling enabled,Protocol exception handling disabled" newline rbitfld.long 0x0C 10.--11. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 9. "BRSE,Bit Rate Switch Enable" "Bit rate switching for transmissions disabled,Bit rate switching for transmissions enabled" newline bitfld.long 0x0C 8. "FDOE,FD Operation Enable" "FD operation disabled,FD operation enabled" newline bitfld.long 0x0C 7. "TEST,Test Mode Enable" "Normal operation,Test Mode" newline bitfld.long 0x0C 6. "DAR,Disable Automatic Retransmission" "Automatic retransmission of messages not..,Automatic retransmission disabled" newline bitfld.long 0x0C 5. "MON,Bus Monitoring Mode" "Bus Monitoring Mode is disabled,Bus Monitoring Mode is enabled" newline bitfld.long 0x0C 4. "CSR,Clock Stop Request" "No clock stop is requested,Clock stop requested" newline bitfld.long 0x0C 3. "CSA,Clock Stop Acknowledge" "No clock stop acknowledged,The MCAN module may be set in power down by.." newline bitfld.long 0x0C 2. "ASM,Restricted Operation Mode" "Normal CAN operation,Restricted Operation Mode active" newline bitfld.long 0x0C 1. "CCE,Configuration Change Enable" "The Host CPU has no write access to the..,The Host CPU has write access to the protected.." newline bitfld.long 0x0C 0. "INIT,Initialization" "Normal Operation,Initialization is started" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing" hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0x00-0x7F)" newline hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (0x01-0xFF)" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0x00-0x7F)" line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 16.--19. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0x0-0xF)]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "Timestamp counter value always 0x0000,Timestamp counter value incremented according to,External timestamp counter value used,Same as '00'" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx)" line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter)" newline hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to" "Continuous operation,Timeout controlled by Tx Event FIFO,Timeout controlled by Rx FIFO 0,Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "Timeout Counter disabled,Timeout Counter enabled" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter" hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of" rgroup.long 0x1A40++0x0B line.long 0x00 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented" newline bitfld.long 0x00 15. "RP,Receive Error Passive" "The Receive Error Counter is below the error..,The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127" newline hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255" line.long 0x04 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value" hexmask.long.word 0x04 23.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x04 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the mcan_tx to mcan_rx pins and" newline bitfld.long 0x04 15. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 14. "PXE,Protocol Exception Event" "No protocol exception event occurred since last..,Protocol exception event occurred" newline bitfld.long 0x04 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering" "Since this bit was reset by the Host CPU no CAN..,Message in CAN FD format with FDF flag set has.." newline bitfld.long 0x04 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with" "Last received CAN FD message did not have its..,Last received CAN FD message had its BRS flag set" newline bitfld.long 0x04 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with" "Last received CAN FD message did not have its..,Last received CAN FD message had its ESI flag set" newline bitfld.long 0x04 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 7. "BO,Bus_Off Status" "The MCAN module is not Bus_Off,The MCAN module is in Bus_Off state" newline bitfld.long 0x04 6. "EW,Warning Status" "Both error counters are below the Error_Warning..,At least one of error counter has reached the.." newline bitfld.long 0x04 5. "EP,Error Passive" "The MCAN module is in the Error_Active state,The MCAN module is in the Error_Passive state" newline bitfld.long 0x04 3.--4. "ACT,Activity Monitors the module's CAN communication state" "Synchronizing - node is synchronizing on CAN..,Idle - node is neither receiver nor transmitter,Receiver - node is operating as receiver,Transmitter - node is operating as transmitter" newline bitfld.long 0x04 0.--2. "LEC,Last Error Code" "No Error,Stuff Error,Form Error,AckError,Bit1Error,Bit0Error,CRCError,NoChange" line.long 0x08 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length" hexmask.long.tbyte 0x08 15.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x08 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the mcan_rx and mcan_tx pins and the secondary sample point" newline rbitfld.long 0x08 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x08 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the mcan_rx pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment" group.long 0x1A50++0x0F line.long 0x00 "MCAN_IR,Interrupt RegisterThe flags are set when one of the listed conditions is detected (edge-sensitive)" rbitfld.long 0x00 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 29. "ARA,Access to Reserved Address" "No access to reserved address occurred,Access to reserved address occurred" newline bitfld.long 0x00 28. "PED,Protocol Error in Data Phase" "No protocol error in data phase,Protocol error in data phase detected (" newline bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "No protocol error in arbitration phase,Protocol error in arbitration phase detected (" newline bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "No Message RAM Watchdog event occurred,Message RAM Watchdog event due to missing READY" newline bitfld.long 0x00 25. "BO,Bus_Off Status" "Bus_Off status unchanged,Bus_Off status changed" newline bitfld.long 0x00 24. "EW,Warning Status" "Error_Warning status unchanged,Error_Warning status changed" newline bitfld.long 0x00 23. "EP,Error Passive" "Error_Passive status unchanged,Error_Passive status changed" newline bitfld.long 0x00 22. "ELO,Error Logging Overflow" "CAN Error Logging Counter did not overflow,Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x00 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected" "No bit error detected when reading from Message..,Bit error detected uncorrected (example: parity.." newline bitfld.long 0x00 20. "BEC,Bit Error Corrected Message RAM bit error detected and corrected" "No bit error detected when reading from Message..,Bit error detected and corrected (example: ECC)" newline bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer" "No Rx Buffer updated,At least one received message stored into an Rx.." newline bitfld.long 0x00 18. "TOO,Timeout Occurred" "No timeout,Timeout reached" newline bitfld.long 0x00 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received" "No Message RAM access failure occurred,Message RAM access failure occurred" newline bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "No timestamp counter wrap-around,Timestamp counter wrapped around" newline bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "No Tx Event FIFO element lost,Tx Event FIFO element lost also set after write.." newline bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "Tx Event FIFO not full,Tx Event FIFO full" newline bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "Tx Event FIFO fill level below watermark,Tx Event FIFO fill level reached watermark" newline bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "Tx Event FIFO unchanged,Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "Tx FIFO non-empty,Tx FIFO empty" newline bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "No transmission cancellation finished,Transmission cancellation finished" newline bitfld.long 0x00 9. "TC,Transmission Completed" "No transmission completed,Transmission completed" newline bitfld.long 0x00 8. "HPM,High Priority Message" "No high priority message received,High priority message received" newline bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "No Rx FIFO 1 message lost,Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "Rx FIFO 1 not full,Rx FIFO 1 full" newline bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "Rx FIFO 1 fill level below watermark,Rx FIFO 1 fill level reached watermark" newline bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "No new message written to Rx FIFO 1,New message written to Rx FIFO 1" newline bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "No Rx FIFO 0 message lost,Rx FIFO 0 message lost also set after write.." newline bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "Rx FIFO 0 not full,Rx FIFO 0 full" newline bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "Rx FIFO 0 fill level below watermark,Rx FIFO 0 fill level reached watermark" newline bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "No new message written to Rx FIFO 0,New message written to Rx FIFO 0" line.long 0x04 "MCAN_IE,Interrupt EnableThe settings in the Interrupt Enable register determine which status changes in the Interrupt Register are signalled on an interrupt line" rbitfld.long 0x04 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x04 29. "ARAE,Access to Reserved Address Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 28. "PEDE,Protocol Error in Data Phase Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 27. "PEAE,Protocol Error in Arbitration Phase Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 26. "WDIE,Watchdog Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 25. "BOE,Bus_Off Status Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 24. "EWE,Warning Status Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 23. "EPE,Error Passive Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 22. "ELOE,Error Logging Overflow Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 20. "BECE,Bit Error Corrected Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" newline bitfld.long 0x04 18. "TOOE,Timeout Occurred Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 16. "TSWE,Timestamp Wraparound Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 11. "TFEE,Tx FIFO Empty Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 9. "TCE,Transmission Completed Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 8. "HPME,High Priority Message Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "Interrupt disabled,Interrupt enabled" line.long 0x08 "MCAN_ILS,Interrupt Line SelectThe Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines" rbitfld.long 0x08 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x08 29. "ARAL,Access to Reserved Address Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 28. "PEDL,Protocol Error in Data Phase Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 27. "PEAL,Protocol Error in Arbitration Phase Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 26. "WDIL,Watchdog Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 25. "BOL,Bus_Off Status Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 24. "EWL,Warning Status Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 23. "EPL,Error Passive Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 22. "ELOL,Error Logging Overflow Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 21. "BEUL,Bit Error Uncorrected Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 20. "BECL,Bit Error Corrected Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 18. "TOOL,Timeout Occurred Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 17. "MRAFL,Message RAM Access Failure Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 16. "TSWL,Timestamp Wraparound Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 11. "TFEL,Tx FIFO Empty Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 9. "TCL,Transmission Completed Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 8. "HPML,High Priority Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" line.long 0x0C "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1" hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 1. "EINT1,Enable Interrupt Line 1" "Interrupt line INT1 disabled,Interrupt line INT1 enabled" newline bitfld.long 0x0C 0. "EINT0,Enable Interrupt Line 0" "Interrupt line INT0 disabled,Interrupt line INT0 enabled" group.long 0x1A80++0x0B line.long 0x00 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames" hexmask.long 0x00 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated" "Accept in Rx..,Accept in Rx..,Reject,Reject" newline bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated" "Accept in Rx..,Accept in Rx..,Reject,Reject" newline bitfld.long 0x00 1. "RRFS,Reject Remote Frames Standard" "Filter remote frames with 11-bit standard IDs,Reject all remote frames with 11-bit standard IDs" newline bitfld.long 0x00 0. "RRFE,Reject Remote Frames Extended" "Filter remote frames with 29-bit extended IDs,Reject all remote frames with 29-bit extended IDs" line.long 0x04 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x04 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x04 16.--23. 1. "LSS,List Size Standard" newline hexmask.long.word 0x04 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" newline rbitfld.long 0x04 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x08 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list" hexmask.long.word 0x08 23.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x08 16.--22. 1. "LSE,List Size Extended" newline hexmask.long.word 0x08 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" newline rbitfld.long 0x08 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x1A90++0x57 line.long 0x00 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939" rbitfld.long 0x00 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame" line.long 0x04 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 15. "FLST,Filter List Indicates the filter list of the matching filter element" "Standard Filter List,Extended Filter List" newline hexmask.long.byte 0x04 8.--14. 1. "FIDX,Filter Index Index of matching filter element" newline bitfld.long 0x04 6.--7. "MSI,Message Storage Indicator" "No FIFO selected,FIFO message lost,Message stored in FIFO 0,Message stored in FIFO 1" newline bitfld.long 0x04 0.--5. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x08 31. "ND31,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 30. "ND30,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 29. "ND29,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 28. "ND28,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 27. "ND27,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 26. "ND26,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 25. "ND25,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 24. "ND24,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 23. "ND23,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 22. "ND22,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 21. "ND21,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 20. "ND20,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 19. "ND19,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 18. "ND18,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 17. "ND17,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 16. "ND16,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 15. "ND15,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 14. "ND14,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 13. "ND13,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 12. "ND12,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 11. "ND11,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 10. "ND10,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 9. "ND9,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 8. "ND8,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 7. "ND7,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 6. "ND6,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 5. "ND5,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 4. "ND4,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 3. "ND3,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 2. "ND2,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 1. "ND1,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 0. "ND0,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" line.long 0x0C "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x0C 31. "ND63,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 30. "ND62,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 29. "ND61,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 28. "ND60,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 27. "ND59,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 26. "ND58,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 25. "ND57,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 24. "ND56,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 23. "ND55,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 22. "ND54,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 21. "ND53,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 20. "ND52,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 19. "ND51,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 18. "ND50,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 17. "ND49,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 16. "ND48,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 15. "ND47,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 14. "ND46,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 13. "ND45,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 12. "ND44,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 11. "ND43,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 10. "ND42,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 9. "ND41,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 8. "ND40,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 7. "ND39,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 6. "ND38,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 5. "ND37,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 4. "ND36,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 3. "ND35,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 2. "ND34,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 1. "ND33,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 0. "ND32,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" line.long 0x10 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x10 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0x0: FIFO 0 blocking mode 0x1: FIFO 0 overwrite mode" "FIFO 0 blocking mode,FIFO 0 overwrite mode" newline hexmask.long.byte 0x10 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline rbitfld.long 0x10 23. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x10 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" newline rbitfld.long 0x10 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x14 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x14 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x14 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag" "No Rx FIFO 0 message lost,Rx FIFO 0 message lost also set after write.." newline bitfld.long 0x14 24. "F0F,Rx FIFO 0 Full" "Rx FIFO 0 not full,Rx FIFO 0 full" newline bitfld.long 0x14 22.--23. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x14 16.--21. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x14 14.--15. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x14 8.--13. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x14 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x14 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64" line.long 0x18 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long 0x18 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x18 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x1C 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM Also used to reference debug messages A B C" newline rbitfld.long 0x1C 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x20 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x20 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0x0: FIFO 1 blocking mode 0x1: FIFO 1 overwrite mode" "FIFO 1 blocking mode,FIFO 1 overwrite mode" newline hexmask.long.byte 0x20 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline rbitfld.long 0x20 23. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x20 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" newline rbitfld.long 0x20 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x24 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x24 30.--31. "DMS,Debug Message Status" "Idle state wait for reception of debug messages..,Debug message A received,Debug messages A B received,Debug messages A B C received" newline bitfld.long 0x24 26.--29. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x24 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag" "No Rx FIFO 1 message lost,Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x24 24. "F1F,Rx FIFO 1 Full" "Rx FIFO 1 not full,Rx FIFO 1 full" newline bitfld.long 0x24 22.--23. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x24 16.--21. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x24 14.--15. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x24 8.--13. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x24 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x24 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64" line.long 0x28 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long 0x28 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x28 0.--5. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "MCAN_RXESC,Rx Buffer / FIFO Element Size Configuration Configure data field size for storage of accepted frames" hexmask.long.tbyte 0x2C 11.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 8.--10. "RBDS,Rx Buffer Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field" newline rbitfld.long 0x2C 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field" newline rbitfld.long 0x2C 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field" line.long 0x30 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" rbitfld.long 0x30 31. "RESERVED,Reserved" "0,1" newline bitfld.long 0x30 30. "TFQM,Tx FIFO/Queue Mode" "Tx FIFO operation,Tx Queue operation" newline bitfld.long 0x30 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x30 22.--23. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x30 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x30 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see" newline rbitfld.long 0x30 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x34 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" hexmask.long.word 0x34 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x34 21. "TFQF,Tx FIFO/Queue Full" "Tx FIFO/Queue not full,Tx FIFO/Queue full" newline bitfld.long 0x34 16.--20. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x34 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 8.--12. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x34 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x34 0.--5. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission" hexmask.long 0x38 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x38 0.--2. "TBDS,Tx Buffer Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field" line.long 0x3C "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request" bitfld.long 0x3C 31. "TRP31,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 30. "TRP30,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 29. "TRP29,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 28. "TRP28,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 27. "TRP27,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 26. "TRP26,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 25. "TRP25,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 24. "TRP24,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 23. "TRP23,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 22. "TRP22,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 21. "TRP21,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 20. "TRP20,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 19. "TRP19,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 18. "TRP18,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 17. "TRP17,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 16. "TRP16,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 15. "TRP15,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 14. "TRP14,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 13. "TRP13,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 12. "TRP12,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 11. "TRP11,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 10. "TRP10,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 9. "TRP9,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 8. "TRP8,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 7. "TRP7,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 6. "TRP6,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 5. "TRP5,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 4. "TRP4,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 3. "TRP3,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 2. "TRP2,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 1. "TRP1,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 0. "TRP0,Transmission Request Pending" "No transmission request pending,Transmission request pending" line.long 0x40 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests" bitfld.long 0x40 31. "AR31,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 30. "AR30,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 29. "AR29,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 28. "AR28,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 27. "AR27,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 26. "AR26,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 25. "AR25,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 24. "AR24,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 23. "AR23,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 22. "AR22,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 21. "AR21,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 20. "AR20,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 19. "AR19,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 18. "AR18,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 17. "AR17,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 16. "AR16,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 15. "AR15,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 14. "AR14,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 13. "AR13,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 12. "AR12,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 11. "AR11,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 10. "AR10,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 9. "AR9,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 8. "AR8,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 7. "AR7,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 6. "AR6,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 5. "AR5,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 4. "AR4,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 3. "AR3,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 2. "AR2,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 1. "AR1,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 0. "AR0,Add Request" "No transmission request added,Transmission requested added" line.long 0x44 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions" bitfld.long 0x44 31. "CR31,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 30. "CR30,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 29. "CR29,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 28. "CR28,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 27. "CR27,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 26. "CR26,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 25. "CR25,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 24. "CR24,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 23. "CR23,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 22. "CR22,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 21. "CR21,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 20. "CR20,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 19. "CR19,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 18. "CR18,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 17. "CR17,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 16. "CR16,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 15. "CR15,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 14. "CR14,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 13. "CR13,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 12. "CR12,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 11. "CR11,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 10. "CR10,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 9. "CR9,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 8. "CR8,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 7. "CR7,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 6. "CR6,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 5. "CR5,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 4. "CR4,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 3. "CR3,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 2. "CR2,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 1. "CR1,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 0. "CR0,Cancellation Request" "No cancellation pending,Cancellation pending" line.long 0x48 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared" bitfld.long 0x48 31. "TO31,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 30. "TO30,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 29. "TO29,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 28. "TO28,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 27. "TO27,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 26. "TO26,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 25. "TO25,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 24. "TO24,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 23. "TO23,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 22. "TO22,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 21. "TO21,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 20. "TO20,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 19. "TO19,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 18. "TO18,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 17. "TO17,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 16. "TO16,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 15. "TO15,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 14. "TO14,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 13. "TO13,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 12. "TO12,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 11. "TO11,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 10. "TO10,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 9. "TO9,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 8. "TO8,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 7. "TO7,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 6. "TO6,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 5. "TO5,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 4. "TO4,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 3. "TO3,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 2. "TO2,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 1. "TO1,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 0. "TO0,Transmission Occurred" "No transmission occurred,Transmission occurred" line.long 0x4C "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4C 31. "CF31,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 30. "CF30,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 29. "CF29,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 28. "CF28,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 27. "CF27,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 26. "CF26,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 25. "CF25,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 24. "CF24,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 23. "CF23,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 22. "CF22,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 21. "CF21,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 20. "CF20,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 19. "CF19,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 18. "CF18,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 17. "CF17,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 16. "CF16,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 15. "CF15,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 14. "CF14,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 13. "CF13,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 12. "CF12,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 11. "CF11,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 10. "CF10,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 9. "CF9,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 8. "CF8,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 7. "CF7,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 6. "CF6,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 5. "CF5,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 4. "CF4,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 3. "CF3,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 2. "CF2,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 1. "CF1,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 0. "CF0,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" line.long 0x50 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers" bitfld.long 0x50 31. "TIE31,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 30. "TIE30,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 29. "TIE29,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 28. "TIE28,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 27. "TIE27,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 26. "TIE26,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 25. "TIE25,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 24. "TIE24,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 23. "TIE23,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 22. "TIE22,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 21. "TIE21,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 20. "TIE20,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 19. "TIE19,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 18. "TIE18,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 17. "TIE17,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 16. "TIE16,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 15. "TIE15,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 14. "TIE14,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 13. "TIE13,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 12. "TIE12,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 11. "TIE11,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 10. "TIE10,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 9. "TIE9,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 8. "TIE8,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 7. "TIE7,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 6. "TIE6,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 5. "TIE5,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 4. "TIE4,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 3. "TIE3,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 2. "TIE2,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 1. "TIE1,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 0. "TIE0,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" line.long 0x54 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x54 31. "CFIE31,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 30. "CFIE30,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 29. "CFIE29,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 28. "CFIE28,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 27. "CFIE27,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 26. "CFIE26,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 25. "CFIE25,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 24. "CFIE24,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 23. "CFIE23,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 22. "CFIE22,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 21. "CFIE21,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 20. "CFIE20,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 19. "CFIE19,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 18. "CFIE18,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 17. "CFIE17,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 16. "CFIE16,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 15. "CFIE15,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 14. "CFIE14,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 13. "CFIE13,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 12. "CFIE12,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 11. "CFIE11,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 10. "CFIE10,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 9. "CFIE9,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 8. "CFIE8,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 7. "CFIE7,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 6. "CFIE6,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 5. "CFIE5,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 4. "CFIE4,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 3. "CFIE3,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 2. "CFIE2,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 1. "CFIE1,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 0. "CFIE0,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" group.long 0x1AF0++0x0B line.long 0x00 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address" rbitfld.long 0x00 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 22.--23. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" newline rbitfld.long 0x00 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x04 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x04 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 25. "TEFL,This bit is a copy of interrupt flag" "No Tx Event FIFO element lost,Tx Event FIFO element lost also set after write.." newline bitfld.long 0x04 24. "EFF,Event FIFO Full" "Tx Event FIFO not full,Tx Event FIFO full" newline bitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 16.--20. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 8.--12. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x04 0.--5. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x08 0.--4. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x1C00++0x03 line.long 0x00 "MCANSS_ECC_AGGR_REVISION,Aggregator Revision Register Revision parameters" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID" newline bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C08++0x1F line.long 0x00 "MCANSS_ECC_VECTOR,ECC Vector Register ECC Vector Register" hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read is complete" "0,1" newline hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x00 15. "RD_SVBUS,Write '1' to trigger a" "0,1" newline rbitfld.long 0x00 11.--14. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" line.long 0x04 "MCANSS_ECC_MISC_STATUS,Misc Status Misc Status" hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" line.long 0x08 "MCANSS_ECC_WRAP_REVISION,ECC Wrapper Revision Register Revision parameters" bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x08 28.--29. "BU,Business Unit" "0,1,2,3" newline hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID" newline bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "MCANSS_ECC_CONTROL,ECC Control ECC Control Register" hexmask.long 0x0C 7.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1" newline bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1" newline bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1" newline bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1" newline bitfld.long 0x0C 2. "ENABLE_RMW,Enable RMW" "0,1" newline bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1" newline bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1" line.long 0x10 "MCANSS_ECC_ERR_CTRL1,ECC Error Control1 Register ECC Error Control1 Register" hexmask.long.word 0x10 16.--31. 1. "ECC_BIT1,Data bit that needs to be flipped when FORCE_SEC is set" newline hexmask.long.word 0x10 0.--15. 1. "ECC_ROW,Row address where single or double-bit error needs to be applied" line.long 0x14 "MCANSS_ECC_ERR_CTRL2,ECC Error Control2 Register ECC Error Control2 Register" hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x14 0.--15. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced" line.long 0x18 "MCANSS_ECC_ERR_STAT1,ECC Error Status1 Register ECC Error Status1 Register" hexmask.long.word 0x18 16.--31. 1. "ECC_ROW,Row address where the single or double-bit error has occurred" newline rbitfld.long 0x18 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x18 9. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1" newline bitfld.long 0x18 8. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1" newline rbitfld.long 0x18 2.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x18 1. "ECC_DED,Level Double Bit Error Status" "0,1" newline bitfld.long 0x18 0. "ECC_SEC,Level Single Bit Error Status" "0,1" line.long 0x1C "MCANSS_ECC_ERR_STAT2,ECC Error Status2 Register ECC Error Status2 Register" hexmask.long.word 0x1C 16.--31. 1. "ECC_BIT2,Data bit that corresponds to the double-bit error" newline hexmask.long.word 0x1C 0.--15. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error" group.long 0x1C3C++0x07 line.long 0x00 "MCANSS_ECC_SEC_EOI_REG,EOI Register EOI Register" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1" line.long 0x04 "MCANSS_ECC_SEC_STATUS_REG0,Interrupt Status Register 0 Interrupt Status Register 0" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x1C80++0x03 line.long 0x00 "MCANSS_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0 Interrupt Enable Set Register 0" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for MSGMEM_PEND" "0,1" group.long 0x1CC0++0x03 line.long 0x00 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0 Interrupt Enable Clear Register 0" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for MSGMEM_PEND" "0,1" group.long 0x1D3C++0x07 line.long 0x00 "MCANSS_ECC_DED_EOI_REG,EOI Register EOI Register" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1" line.long 0x04 "MCANSS_ECC_DED_STATUS_REG0,Interrupt Status Register 0 Interrupt Status Register 0" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x1D80++0x03 line.long 0x00 "MCANSS_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0 Interrupt Enable Set Register 0" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for MSGMEM_PEND" "0,1" group.long 0x1DC0++0x03 line.long 0x00 "MCANSS_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0 Interrupt Enable Clear Register 0" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for MSGMEM_PEND" "0,1" width 0x0B tree.end tree "MCAN_TARG" base ad:0x48482000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP1_AFIFO" base ad:0x48461000 group.long 0x00++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" abitfld.long 0x00 8.--15. "WNUMEVT,Write word count (32-bit) to generate TX event to host" "0x40=3 to 64 words currently..,0xFF=Reserved" abitfld.long 0x00 0.--7. "WNUMDMA,Write word count (32-bit words)" "0x10=3 to 16 words,0xFF=Reserved" line.long 0x04 "WFIFOSTS,The Write FIFO status register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently..,0xFF=Reserved" line.long 0x08 "RFIFOCTL,The Read FIFO control register" hexmask.long.word 0x08 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" abitfld.long 0x08 8.--15. "RNUMEVT,Read word count (32-bit) to generate RX event to host" "0x40=3 to 64 words..,0xFF=Reserved" abitfld.long 0x08 0.--7. "RNUMDMA,Read word count (32-bit words)" "0x10=3-16 words,0xFF=Reserved" line.long 0x0C "RFIFOSTS,The Read FIFO status register" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently..,0xFF=Reserved" width 0x0B tree.end tree "MCASP1_CFG" base ad:0x48460000 rgroup.long 0x00++0x07 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x00 28.--29. "RESV,Reserved" "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. "FUNCTION,MCASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "0,1,2,3" newline bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PWRIDLESYSCONFIG,Power idle module configuration register" hexmask.long 0x04 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2.--5. "OTHER,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--1. "IDLE_MODE," "?,No-idle mode,Smart-idle mode - default..,Reserved" group.long 0x10++0x0F line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" newline bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x00 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x04 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x04 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x04 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" newline bitfld.long 0x04 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" newline bitfld.long 0x04 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" newline bitfld.long 0x04 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" newline bitfld.long 0x04 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" bitfld.long 0x04 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" newline bitfld.long 0x04 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" newline bitfld.long 0x04 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x08 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x08 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" newline bitfld.long 0x08 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1" "ACLKR_0,ACLKR_1" bitfld.long 0x08 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" newline bitfld.long 0x08 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" bitfld.long 0x08 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x08 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x08 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" newline bitfld.long 0x08 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" newline bitfld.long 0x08 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" bitfld.long 0x08 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" newline bitfld.long 0x08 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" newline bitfld.long 0x08 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" newline bitfld.long 0x08 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" newline bitfld.long 0x08 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" bitfld.long 0x08 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" newline bitfld.long 0x08 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x0C "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins" bitfld.long 0x0C 31. "AFSR,Logic level on AFSR pin (device level: mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x0C 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 29. "ACLKR,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" bitfld.long 0x0C 28. "AFSX,Logic level on AFSX pin (device level: mcaspi_fsx signal)" "AFSX_0,AFSX_1" newline bitfld.long 0x0C 27. "AHCLKX,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" bitfld.long 0x0C 26. "ACLKX,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x0C 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x0C 15. "AXR15,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" newline bitfld.long 0x0C 14. "AXR14,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x0C 13. "AXR13,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" newline bitfld.long 0x0C 12. "AXR12,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x0C 11. "AXR11,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x0C 10. "AXR10,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x0C 9. "AXR9,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" newline bitfld.long 0x0C 8. "AXR8,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x0C 7. "AXR7,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" newline bitfld.long 0x0C 6. "AXR6,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" bitfld.long 0x0C 5. "AXR5,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" newline bitfld.long 0x0C 4. "AXR4,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x0C 3. "AXR3,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" newline bitfld.long 0x0C 2. "AXR2,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x0C 1. "AXR1,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x0C 0. "AXR0,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x1C++0x07 line.long 0x00 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" newline bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x00 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x04 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x04 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x04 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x04 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x04 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x04 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x04 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x04 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x04 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x04 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x44++0x0F line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit" "XFRST_0,XFRST_1" newline bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bitAXR[n] pin state : If[n] = 0 and [n] = 1 the corresponding serializer [n] drives the AXR[n] pin to the state specified for inactive time slot" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" newline bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" line.long 0x08 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode" hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects between and loopback modes" "IOLBEN_0,IOLBEN_1" newline bitfld.long 0x08 2.--3. "MODE,Loopback generator mode bits.0x2 " "MODE_0,MODE_1,?,?" bitfld.long 0x08 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" newline bitfld.long 0x08 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" line.long 0x0C "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the MCASP" hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" newline bitfld.long 0x0C 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" bitfld.long 0x0C 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 0. "DITEN,DIT mode enable bit" "DITEN_0,DITEN_1" group.long 0x60++0x2F line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED," rbitfld.long 0x00 12. "XFRST,Frame sync generator reset" "XFRST_0,XFRST_1" newline rbitfld.long 0x00 11. "XSMRST,XMT state machine reset" "XSMRST_0,XSMRST_1" rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear" "XSRCLR_0,XSRCLR_1" newline rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "RFRST,Frame sync generator reset" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,RCV state machine reset" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" line.long 0x08 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" hexmask.long.word 0x08 18.--31. 1. "RESERVED," bitfld.long 0x08 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n]" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" newline bitfld.long 0x08 15. "RRVRS,Receive serial bitstream order" "RRVRS_0,RRVRS_1" bitfld.long 0x08 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" newline bitfld.long 0x08 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x08 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" newline bitfld.long 0x08 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" bitfld.long 0x08 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" line.long 0x0C "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," abitfld.long 0x0C 7.--15. "RMOD,Receive frame sync mode select" "0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x1FF=Reserved" newline bitfld.long 0x0C 5.--6. "RESERVED," "0,1,2,3" bitfld.long 0x0C 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" newline bitfld.long 0x0C 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x0C 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" newline bitfld.long 0x0C 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" line.long 0x10 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" hexmask.long.word 0x10 21.--31. 1. "RESERVED," bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" hexmask.long.byte 0x10 8.--15. 1. "RESERVED," newline bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" bitfld.long 0x10 6. "RESERVED," "0,1" newline bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" bitfld.long 0x10 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" hexmask.long.word 0x14 21.--31. 1. "RESERVED," bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" bitfld.long 0x14 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" bitfld.long 0x14 12.--13. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to" line.long 0x18 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" line.long 0x1C "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT)" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit" "RSTAFRM_0,RSTAFRM_1" newline bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "RDATA,Receive data-ready interrupt enable bit" "RDATA_0,RDATA_1" newline bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit" "RLAST_0,RLAST_1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit" "ROVRN_0,ROVRN_1" line.long 0x20 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED," bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" newline bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" newline bitfld.long 0x20 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" bitfld.long 0x20 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" newline bitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" newline bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" line.long 0x24 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED," hexmask.long.word 0x24 0.--8. 1. "RSLOTCNT," line.long 0x28 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "RCNT," hexmask.long.byte 0x28 16.--23. 1. "RMAX," newline hexmask.long.byte 0x28 8.--15. 1. "RMIN," bitfld.long 0x28 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 0.--3. "RPS,Receive clock check prescaler value.0x9" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" line.long 0x2C "MCASP_REVTCTL,Receiver DMA event control register" hexmask.long 0x2C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0xA0++0x33 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED," bitfld.long 0x00 12. "XFRST,Frame sync generator reset" "XFRST_0,XFRST_1" newline bitfld.long 0x00 11. "XSMRST,XMT state machine reset" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,XMT serializer clear" "XSRCLR_0,XSRCLR_1" newline bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x00 4. "RFRST,Frame sync generator reset" "RFRST_0,RFRST_1" newline rbitfld.long 0x00 3. "RSMRST,RCV state machine reset" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear" "RSRCLKR_0,RSRCLKR_1" newline rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" line.long 0x08 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 16.--17. "XDATDLY,Transmit sync bit delay" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" newline bitfld.long 0x08 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" bitfld.long 0x08 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" newline bitfld.long 0x08 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" newline bitfld.long 0x08 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" bitfld.long 0x08 0.--2. "XROT,Right-rotation value for transmit rotate right format unit" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" line.long 0x0C "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,Reserved" abitfld.long 0x0C 7.--15. "XMOD,Transmit frame-sync mode select bits" "0x000=Burst mode,0x001=Reserved,0x002=2-slot TDM mode (),0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x180=384-slot DIT mode All other: Reserved" newline bitfld.long 0x0C 5.--6. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0C 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" newline bitfld.long 0x0C 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0C 1. "FSXM,Transmit frame-sync generation select bit" "FSXM_0,FSXM_1" newline bitfld.long 0x0C 0. "FSXP,Transmit frame-sync polarity select bit" "FSXP_0,FSXP_1" line.long 0x10 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" hexmask.long.word 0x10 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" hexmask.long.byte 0x10 8.--15. 1. "RESERVED," newline bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" bitfld.long 0x10 6. "ASYNC,Transmit operation asynchronous enable bit" "ASYNC_0,ASYNC_1" newline bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit" "CLKXM_0,CLKXM_1" bitfld.long 0x10 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "Divide-by-1,Divide-by-2 0x2 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide-by-3 to divide-by-32" line.long 0x14 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" hexmask.long.word 0x14 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit" "HCLKXM_0,HCLKXM_1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" bitfld.long 0x14 12.--13. "RESERVED,Reserved" "0,1,2,3" newline abitfld.long 0x14 0.--11. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" "0x000=Divide-by-1,0x001=Divide-by-2 0x2 to,0xFFF=Divide-by-3 to divide-by-4096" line.long 0x18 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" line.long 0x1C "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit" "XSTAFRM_0,XSTAFRM_1" newline bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data-ready interrupt enable bit" "XDATA_0,XDATA_1" newline bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit" "XLAST_0,XLAST_1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit" "XUNDRN_0,XUNDRN_1" line.long 0x20 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the MCASP logic has priority and the flag remains set" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" newline bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" newline bitfld.long 0x20 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" newline bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" line.long 0x24 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 0.--8. 1. "XSLOTCNT,Current transmit time slot count" line.long 0x28 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x28 16.--23. 1. "XMAX,0x0 to" newline hexmask.long.byte 0x28 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x28 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 0.--3. "XPS,Transmit clock check prescaler value" "MCASP interface clock divided by 1,MCASP interface clock divided by 2,MCASP interface clock divided by 4,MCASP interface clock divided by 8,MCASP interface clock divided by 16,MCASP interface clock divided by 32,MCASP interface clock divided by 64,MCASP interface clock divided by 128,MCASP interface clock divided by 256 0x9 to,?,?,?,?,?,?,Reserved" line.long 0x2C "MCASP_XEVTCTL,Transmitter DMA event control register" hexmask.long 0x2C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" line.long 0x30 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" hexmask.long 0x30 1.--31. 1. "RESERVED," bitfld.long 0x30 0. "ENABLE,One-shot clock adjust enable" "ENABLE_0,ENABLE_1" group.long 0x100++0x5F line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x04 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x08 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x0C "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x10 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x14 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x18 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x1C "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x20 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x24 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x28 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x2C "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x30 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x34 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x38 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x3C "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x40 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x44 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x48 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x4C "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x50 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x54 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x58 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x5C "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x180++0x3F line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" hexmask.long 0x00 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x04 "MCASP_XRSRCTLn_1,Serializer n control register" hexmask.long 0x04 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x04 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x04 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x04 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x08 "MCASP_XRSRCTLn_2,Serializer n control register" hexmask.long 0x08 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x08 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x08 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x08 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x08 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x0C "MCASP_XRSRCTLn_3,Serializer n control register" hexmask.long 0x0C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0C 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x0C 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x0C 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x0C 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x10 "MCASP_XRSRCTLn_4,Serializer n control register" hexmask.long 0x10 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x14 "MCASP_XRSRCTLn_5,Serializer n control register" hexmask.long 0x14 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x18 "MCASP_XRSRCTLn_6,Serializer n control register" hexmask.long 0x18 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x18 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x18 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x18 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x18 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x1C "MCASP_XRSRCTLn_7,Serializer n control register" hexmask.long 0x1C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x1C 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x1C 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x1C 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x1C 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x20 "MCASP_XRSRCTLn_8,Serializer n control register" hexmask.long 0x20 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x20 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x20 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x20 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x20 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x24 "MCASP_XRSRCTLn_9,Serializer n control register" hexmask.long 0x24 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x24 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x24 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x24 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x24 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x28 "MCASP_XRSRCTLn_10,Serializer n control register" hexmask.long 0x28 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x28 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x28 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x28 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x28 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x2C "MCASP_XRSRCTLn_11,Serializer n control register" hexmask.long 0x2C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x2C 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x2C 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x2C 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x2C 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x30 "MCASP_XRSRCTLn_12,Serializer n control register" hexmask.long 0x30 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x30 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x30 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x30 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x30 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x34 "MCASP_XRSRCTLn_13,Serializer n control register" hexmask.long 0x34 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x34 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x34 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x34 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x34 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x38 "MCASP_XRSRCTLn_14,Serializer n control register" hexmask.long 0x38 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x38 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x38 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x38 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x38 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x3C "MCASP_XRSRCTLn_15,Serializer n control register" hexmask.long 0x3C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x3C 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x3C 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x3C 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x3C 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" group.long 0x200++0x3F line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x04 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x08 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x0C "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x10 "MCASP_TXBUFn_4,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x14 "MCASP_TXBUFn_5,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x18 "MCASP_TXBUFn_6,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x1C "MCASP_TXBUFn_7,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x20 "MCASP_TXBUFn_8,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x24 "MCASP_TXBUFn_9,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x28 "MCASP_TXBUFn_10,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x2C "MCASP_TXBUFn_11,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x30 "MCASP_TXBUFn_12,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x34 "MCASP_TXBUFn_13,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x38 "MCASP_TXBUFn_14,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x3C "MCASP_TXBUFn_15,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x280++0x3F line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x04 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x08 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x0C "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x10 "MCASP_RXBUFn_4,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x14 "MCASP_RXBUFn_5,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x18 "MCASP_RXBUFn_6,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x1C "MCASP_RXBUFn_7,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x20 "MCASP_RXBUFn_8,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x24 "MCASP_RXBUFn_9,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x28 "MCASP_RXBUFn_10,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x2C "MCASP_RXBUFn_11,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x30 "MCASP_RXBUFn_12,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x34 "MCASP_RXBUFn_13,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x38 "MCASP_RXBUFn_14,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x3C "MCASP_RXBUFn_15,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" width 0x0B tree.end tree "MCASP1_DAT" base ad:0x45800000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" width 0x0B tree.end tree "MCASP1_FW" base ad:0x4A167000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "MCASP1_FW_CFG_TARG" base ad:0x4A168000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP1_TARG" base ad:0x44002F00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "MCASP2_AFIFO" base ad:0x4846D000 group.long 0x00++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" abitfld.long 0x00 8.--15. "WNUMEVT,Write word count (32-bit) to generate TX event to host" "0x40=3 to 64 words currently..,0xFF=Reserved" abitfld.long 0x00 0.--7. "WNUMDMA,Write word count (32-bit words)" "0x10=3 to 16 words,0xFF=Reserved" line.long 0x04 "WFIFOSTS,The Write FIFO status register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently..,0xFF=Reserved" line.long 0x08 "RFIFOCTL,The Read FIFO control register" hexmask.long.word 0x08 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" abitfld.long 0x08 8.--15. "RNUMEVT,Read word count (32-bit) to generate RX event to host" "0x40=3 to 64 words..,0xFF=Reserved" abitfld.long 0x08 0.--7. "RNUMDMA,Read word count (32-bit words)" "0x10=3-16 words,0xFF=Reserved" line.long 0x0C "RFIFOSTS,The Read FIFO status register" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently..,0xFF=Reserved" width 0x0B tree.end tree "MCASP2_CFG" base ad:0x4846C000 rgroup.long 0x00++0x07 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x00 28.--29. "RESV,Reserved" "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. "FUNCTION,MCASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "0,1,2,3" newline bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PWRIDLESYSCONFIG,Power idle module configuration register" hexmask.long 0x04 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2.--5. "OTHER,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--1. "IDLE_MODE," "?,No-idle mode,Smart-idle mode - default..,Reserved" group.long 0x10++0x0F line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" newline bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x00 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x04 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x04 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x04 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" newline bitfld.long 0x04 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" newline bitfld.long 0x04 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" newline bitfld.long 0x04 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" newline bitfld.long 0x04 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" bitfld.long 0x04 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" newline bitfld.long 0x04 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" newline bitfld.long 0x04 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x08 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x08 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" newline bitfld.long 0x08 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1" "ACLKR_0,ACLKR_1" bitfld.long 0x08 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" newline bitfld.long 0x08 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" bitfld.long 0x08 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x08 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x08 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" newline bitfld.long 0x08 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" newline bitfld.long 0x08 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" bitfld.long 0x08 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" newline bitfld.long 0x08 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" newline bitfld.long 0x08 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" newline bitfld.long 0x08 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" newline bitfld.long 0x08 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" bitfld.long 0x08 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" newline bitfld.long 0x08 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x0C "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins" bitfld.long 0x0C 31. "AFSR,Logic level on AFSR pin (device level: mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x0C 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 29. "ACLKR,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" bitfld.long 0x0C 28. "AFSX,Logic level on AFSX pin (device level: mcaspi_fsx signal)" "AFSX_0,AFSX_1" newline bitfld.long 0x0C 27. "AHCLKX,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" bitfld.long 0x0C 26. "ACLKX,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x0C 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x0C 15. "AXR15,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" newline bitfld.long 0x0C 14. "AXR14,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x0C 13. "AXR13,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" newline bitfld.long 0x0C 12. "AXR12,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x0C 11. "AXR11,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x0C 10. "AXR10,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x0C 9. "AXR9,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" newline bitfld.long 0x0C 8. "AXR8,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x0C 7. "AXR7,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" newline bitfld.long 0x0C 6. "AXR6,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" bitfld.long 0x0C 5. "AXR5,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" newline bitfld.long 0x0C 4. "AXR4,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x0C 3. "AXR3,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" newline bitfld.long 0x0C 2. "AXR2,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x0C 1. "AXR1,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x0C 0. "AXR0,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x1C++0x07 line.long 0x00 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" newline bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x00 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x04 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x04 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x04 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x04 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x04 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x04 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x04 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x04 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x04 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x04 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x44++0x0F line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit" "XFRST_0,XFRST_1" newline bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bitAXR[n] pin state : If[n] = 0 and [n] = 1 the corresponding serializer [n] drives the AXR[n] pin to the state specified for inactive time slot" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" newline bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" line.long 0x08 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode" hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects between and loopback modes" "IOLBEN_0,IOLBEN_1" newline bitfld.long 0x08 2.--3. "MODE,Loopback generator mode bits.0x2 " "MODE_0,MODE_1,?,?" bitfld.long 0x08 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" newline bitfld.long 0x08 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" line.long 0x0C "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the MCASP" hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" newline bitfld.long 0x0C 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" bitfld.long 0x0C 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 0. "DITEN,DIT mode enable bit" "DITEN_0,DITEN_1" group.long 0x60++0x2F line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED," rbitfld.long 0x00 12. "XFRST,Frame sync generator reset" "XFRST_0,XFRST_1" newline rbitfld.long 0x00 11. "XSMRST,XMT state machine reset" "XSMRST_0,XSMRST_1" rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear" "XSRCLR_0,XSRCLR_1" newline rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "RFRST,Frame sync generator reset" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,RCV state machine reset" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" line.long 0x08 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" hexmask.long.word 0x08 18.--31. 1. "RESERVED," bitfld.long 0x08 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n]" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" newline bitfld.long 0x08 15. "RRVRS,Receive serial bitstream order" "RRVRS_0,RRVRS_1" bitfld.long 0x08 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" newline bitfld.long 0x08 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x08 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" newline bitfld.long 0x08 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" bitfld.long 0x08 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" line.long 0x0C "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," abitfld.long 0x0C 7.--15. "RMOD,Receive frame sync mode select" "0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x1FF=Reserved" newline bitfld.long 0x0C 5.--6. "RESERVED," "0,1,2,3" bitfld.long 0x0C 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" newline bitfld.long 0x0C 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x0C 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" newline bitfld.long 0x0C 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" line.long 0x10 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" hexmask.long.word 0x10 21.--31. 1. "RESERVED," bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" hexmask.long.byte 0x10 8.--15. 1. "RESERVED," newline bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" bitfld.long 0x10 6. "RESERVED," "0,1" newline bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" bitfld.long 0x10 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" hexmask.long.word 0x14 21.--31. 1. "RESERVED," bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" bitfld.long 0x14 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" bitfld.long 0x14 12.--13. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to" line.long 0x18 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" line.long 0x1C "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT)" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit" "RSTAFRM_0,RSTAFRM_1" newline bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "RDATA,Receive data-ready interrupt enable bit" "RDATA_0,RDATA_1" newline bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit" "RLAST_0,RLAST_1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit" "ROVRN_0,ROVRN_1" line.long 0x20 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED," bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" newline bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" newline bitfld.long 0x20 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" bitfld.long 0x20 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" newline bitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" newline bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" line.long 0x24 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED," hexmask.long.word 0x24 0.--8. 1. "RSLOTCNT," line.long 0x28 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "RCNT," hexmask.long.byte 0x28 16.--23. 1. "RMAX," newline hexmask.long.byte 0x28 8.--15. 1. "RMIN," bitfld.long 0x28 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 0.--3. "RPS,Receive clock check prescaler value.0x9" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" line.long 0x2C "MCASP_REVTCTL,Receiver DMA event control register" hexmask.long 0x2C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0xA0++0x33 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED," bitfld.long 0x00 12. "XFRST,Frame sync generator reset" "XFRST_0,XFRST_1" newline bitfld.long 0x00 11. "XSMRST,XMT state machine reset" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,XMT serializer clear" "XSRCLR_0,XSRCLR_1" newline bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x00 4. "RFRST,Frame sync generator reset" "RFRST_0,RFRST_1" newline rbitfld.long 0x00 3. "RSMRST,RCV state machine reset" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear" "RSRCLKR_0,RSRCLKR_1" newline rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" line.long 0x08 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 16.--17. "XDATDLY,Transmit sync bit delay" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" newline bitfld.long 0x08 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" bitfld.long 0x08 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" newline bitfld.long 0x08 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" newline bitfld.long 0x08 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" bitfld.long 0x08 0.--2. "XROT,Right-rotation value for transmit rotate right format unit" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" line.long 0x0C "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,Reserved" abitfld.long 0x0C 7.--15. "XMOD,Transmit frame-sync mode select bits" "0x000=Burst mode,0x001=Reserved,0x002=2-slot TDM mode (),0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x180=384-slot DIT mode All other: Reserved" newline bitfld.long 0x0C 5.--6. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0C 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" newline bitfld.long 0x0C 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0C 1. "FSXM,Transmit frame-sync generation select bit" "FSXM_0,FSXM_1" newline bitfld.long 0x0C 0. "FSXP,Transmit frame-sync polarity select bit" "FSXP_0,FSXP_1" line.long 0x10 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" hexmask.long.word 0x10 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" hexmask.long.byte 0x10 8.--15. 1. "RESERVED," newline bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" bitfld.long 0x10 6. "ASYNC,Transmit operation asynchronous enable bit" "ASYNC_0,ASYNC_1" newline bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit" "CLKXM_0,CLKXM_1" bitfld.long 0x10 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "Divide-by-1,Divide-by-2 0x2 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide-by-3 to divide-by-32" line.long 0x14 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" hexmask.long.word 0x14 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit" "HCLKXM_0,HCLKXM_1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" bitfld.long 0x14 12.--13. "RESERVED,Reserved" "0,1,2,3" newline abitfld.long 0x14 0.--11. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" "0x000=Divide-by-1,0x001=Divide-by-2 0x2 to,0xFFF=Divide-by-3 to divide-by-4096" line.long 0x18 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" line.long 0x1C "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit" "XSTAFRM_0,XSTAFRM_1" newline bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data-ready interrupt enable bit" "XDATA_0,XDATA_1" newline bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit" "XLAST_0,XLAST_1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit" "XUNDRN_0,XUNDRN_1" line.long 0x20 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the MCASP logic has priority and the flag remains set" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" newline bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" newline bitfld.long 0x20 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" newline bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" line.long 0x24 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 0.--8. 1. "XSLOTCNT,Current transmit time slot count" line.long 0x28 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x28 16.--23. 1. "XMAX,0x0 to" newline hexmask.long.byte 0x28 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x28 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 0.--3. "XPS,Transmit clock check prescaler value" "MCASP interface clock divided by 1,MCASP interface clock divided by 2,MCASP interface clock divided by 4,MCASP interface clock divided by 8,MCASP interface clock divided by 16,MCASP interface clock divided by 32,MCASP interface clock divided by 64,MCASP interface clock divided by 128,MCASP interface clock divided by 256 0x9 to,?,?,?,?,?,?,Reserved" line.long 0x2C "MCASP_XEVTCTL,Transmitter DMA event control register" hexmask.long 0x2C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" line.long 0x30 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" hexmask.long 0x30 1.--31. 1. "RESERVED," bitfld.long 0x30 0. "ENABLE,One-shot clock adjust enable" "ENABLE_0,ENABLE_1" group.long 0x100++0x5F line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x04 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x08 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x0C "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x10 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x14 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x18 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x1C "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x20 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x24 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x28 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x2C "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x30 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x34 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x38 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x3C "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x40 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x44 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x48 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x4C "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x50 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x54 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x58 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x5C "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x180++0x17 line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" hexmask.long 0x00 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x04 "MCASP_XRSRCTLn_1,Serializer n control register" hexmask.long 0x04 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x04 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x04 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x04 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x08 "MCASP_XRSRCTLn_2,Serializer n control register" hexmask.long 0x08 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x08 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x08 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x08 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x08 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x0C "MCASP_XRSRCTLn_3,Serializer n control register" hexmask.long 0x0C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0C 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x0C 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x0C 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x0C 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x10 "MCASP_XRSRCTLn_4,Serializer n control register" hexmask.long 0x10 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x14 "MCASP_XRSRCTLn_5,Serializer n control register" hexmask.long 0x14 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" group.long 0x200++0x17 line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x04 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x08 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x0C "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x10 "MCASP_TXBUFn_4,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x14 "MCASP_TXBUFn_5,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x280++0x17 line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x04 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x08 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x0C "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x10 "MCASP_RXBUFn_4,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x14 "MCASP_RXBUFn_5,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" width 0x0B tree.end tree "MCASP2_DAT" base ad:0x48436000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" width 0x0B tree.end tree "MCASP3_AFIFO" base ad:0x48471000 group.long 0x00++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" abitfld.long 0x00 8.--15. "WNUMEVT,Write word count (32-bit) to generate TX event to host" "0x40=3 to 64 words currently..,0xFF=Reserved" abitfld.long 0x00 0.--7. "WNUMDMA,Write word count (32-bit words)" "0x10=3 to 16 words,0xFF=Reserved" line.long 0x04 "WFIFOSTS,The Write FIFO status register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently..,0xFF=Reserved" line.long 0x08 "RFIFOCTL,The Read FIFO control register" hexmask.long.word 0x08 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" abitfld.long 0x08 8.--15. "RNUMEVT,Read word count (32-bit) to generate RX event to host" "0x40=3 to 64 words..,0xFF=Reserved" abitfld.long 0x08 0.--7. "RNUMDMA,Read word count (32-bit words)" "0x10=3-16 words,0xFF=Reserved" line.long 0x0C "RFIFOSTS,The Read FIFO status register" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently..,0xFF=Reserved" width 0x0B tree.end tree "MCASP3_CFG" base ad:0x48470000 rgroup.long 0x00++0x07 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x00 28.--29. "RESV,Reserved" "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. "FUNCTION,MCASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "0,1,2,3" newline bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PWRIDLESYSCONFIG,Power idle module configuration register" hexmask.long 0x04 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2.--5. "OTHER,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--1. "IDLE_MODE," "?,No-idle mode,Smart-idle mode - default..,Reserved" group.long 0x10++0x0F line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" newline bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x00 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x04 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x04 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x04 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" newline bitfld.long 0x04 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" newline bitfld.long 0x04 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" newline bitfld.long 0x04 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" newline bitfld.long 0x04 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" bitfld.long 0x04 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" newline bitfld.long 0x04 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" newline bitfld.long 0x04 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x08 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x08 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" newline bitfld.long 0x08 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1" "ACLKR_0,ACLKR_1" bitfld.long 0x08 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" newline bitfld.long 0x08 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" bitfld.long 0x08 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x08 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x08 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" newline bitfld.long 0x08 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" newline bitfld.long 0x08 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" bitfld.long 0x08 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" newline bitfld.long 0x08 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" newline bitfld.long 0x08 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" newline bitfld.long 0x08 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" newline bitfld.long 0x08 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" bitfld.long 0x08 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" newline bitfld.long 0x08 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x0C "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins" bitfld.long 0x0C 31. "AFSR,Logic level on AFSR pin (device level: mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x0C 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 29. "ACLKR,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" bitfld.long 0x0C 28. "AFSX,Logic level on AFSX pin (device level: mcaspi_fsx signal)" "AFSX_0,AFSX_1" newline bitfld.long 0x0C 27. "AHCLKX,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" bitfld.long 0x0C 26. "ACLKX,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x0C 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x0C 15. "AXR15,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" newline bitfld.long 0x0C 14. "AXR14,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x0C 13. "AXR13,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" newline bitfld.long 0x0C 12. "AXR12,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x0C 11. "AXR11,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x0C 10. "AXR10,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x0C 9. "AXR9,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" newline bitfld.long 0x0C 8. "AXR8,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x0C 7. "AXR7,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" newline bitfld.long 0x0C 6. "AXR6,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" bitfld.long 0x0C 5. "AXR5,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" newline bitfld.long 0x0C 4. "AXR4,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x0C 3. "AXR3,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" newline bitfld.long 0x0C 2. "AXR2,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x0C 1. "AXR1,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x0C 0. "AXR0,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x1C++0x07 line.long 0x00 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" newline bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x00 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x04 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x04 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x04 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x04 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x04 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x04 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x04 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x04 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x04 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x04 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x44++0x0F line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit" "XFRST_0,XFRST_1" newline bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bitAXR[n] pin state : If[n] = 0 and [n] = 1 the corresponding serializer [n] drives the AXR[n] pin to the state specified for inactive time slot" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" newline bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" line.long 0x08 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode" hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects between and loopback modes" "IOLBEN_0,IOLBEN_1" newline bitfld.long 0x08 2.--3. "MODE,Loopback generator mode bits.0x2 " "MODE_0,MODE_1,?,?" bitfld.long 0x08 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" newline bitfld.long 0x08 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" line.long 0x0C "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the MCASP" hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" newline bitfld.long 0x0C 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" bitfld.long 0x0C 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 0. "DITEN,DIT mode enable bit" "DITEN_0,DITEN_1" group.long 0x60++0x2F line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED," rbitfld.long 0x00 12. "XFRST,Frame sync generator reset" "XFRST_0,XFRST_1" newline rbitfld.long 0x00 11. "XSMRST,XMT state machine reset" "XSMRST_0,XSMRST_1" rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear" "XSRCLR_0,XSRCLR_1" newline rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "RFRST,Frame sync generator reset" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,RCV state machine reset" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" line.long 0x08 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" hexmask.long.word 0x08 18.--31. 1. "RESERVED," bitfld.long 0x08 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n]" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" newline bitfld.long 0x08 15. "RRVRS,Receive serial bitstream order" "RRVRS_0,RRVRS_1" bitfld.long 0x08 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" newline bitfld.long 0x08 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x08 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" newline bitfld.long 0x08 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" bitfld.long 0x08 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" line.long 0x0C "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," abitfld.long 0x0C 7.--15. "RMOD,Receive frame sync mode select" "0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x1FF=Reserved" newline bitfld.long 0x0C 5.--6. "RESERVED," "0,1,2,3" bitfld.long 0x0C 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" newline bitfld.long 0x0C 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x0C 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" newline bitfld.long 0x0C 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" line.long 0x10 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" hexmask.long.word 0x10 21.--31. 1. "RESERVED," bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" hexmask.long.byte 0x10 8.--15. 1. "RESERVED," newline bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" bitfld.long 0x10 6. "RESERVED," "0,1" newline bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" bitfld.long 0x10 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" hexmask.long.word 0x14 21.--31. 1. "RESERVED," bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" bitfld.long 0x14 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" bitfld.long 0x14 12.--13. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to" line.long 0x18 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" line.long 0x1C "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT)" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit" "RSTAFRM_0,RSTAFRM_1" newline bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "RDATA,Receive data-ready interrupt enable bit" "RDATA_0,RDATA_1" newline bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit" "RLAST_0,RLAST_1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit" "ROVRN_0,ROVRN_1" line.long 0x20 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED," bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" newline bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" newline bitfld.long 0x20 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" bitfld.long 0x20 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" newline bitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" newline bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" line.long 0x24 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED," hexmask.long.word 0x24 0.--8. 1. "RSLOTCNT," line.long 0x28 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "RCNT," hexmask.long.byte 0x28 16.--23. 1. "RMAX," newline hexmask.long.byte 0x28 8.--15. 1. "RMIN," bitfld.long 0x28 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 0.--3. "RPS,Receive clock check prescaler value.0x9" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" line.long 0x2C "MCASP_REVTCTL,Receiver DMA event control register" hexmask.long 0x2C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0xA0++0x33 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED," bitfld.long 0x00 12. "XFRST,Frame sync generator reset" "XFRST_0,XFRST_1" newline bitfld.long 0x00 11. "XSMRST,XMT state machine reset" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,XMT serializer clear" "XSRCLR_0,XSRCLR_1" newline bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x00 4. "RFRST,Frame sync generator reset" "RFRST_0,RFRST_1" newline rbitfld.long 0x00 3. "RSMRST,RCV state machine reset" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear" "RSRCLKR_0,RSRCLKR_1" newline rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" line.long 0x08 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 16.--17. "XDATDLY,Transmit sync bit delay" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" newline bitfld.long 0x08 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" bitfld.long 0x08 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" newline bitfld.long 0x08 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" newline bitfld.long 0x08 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" bitfld.long 0x08 0.--2. "XROT,Right-rotation value for transmit rotate right format unit" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" line.long 0x0C "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,Reserved" abitfld.long 0x0C 7.--15. "XMOD,Transmit frame-sync mode select bits" "0x000=Burst mode,0x001=Reserved,0x002=2-slot TDM mode (),0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x180=384-slot DIT mode All other: Reserved" newline bitfld.long 0x0C 5.--6. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0C 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" newline bitfld.long 0x0C 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0C 1. "FSXM,Transmit frame-sync generation select bit" "FSXM_0,FSXM_1" newline bitfld.long 0x0C 0. "FSXP,Transmit frame-sync polarity select bit" "FSXP_0,FSXP_1" line.long 0x10 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" hexmask.long.word 0x10 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" hexmask.long.byte 0x10 8.--15. 1. "RESERVED," newline bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" bitfld.long 0x10 6. "ASYNC,Transmit operation asynchronous enable bit" "ASYNC_0,ASYNC_1" newline bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit" "CLKXM_0,CLKXM_1" bitfld.long 0x10 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "Divide-by-1,Divide-by-2 0x2 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide-by-3 to divide-by-32" line.long 0x14 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" hexmask.long.word 0x14 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit" "HCLKXM_0,HCLKXM_1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" bitfld.long 0x14 12.--13. "RESERVED,Reserved" "0,1,2,3" newline abitfld.long 0x14 0.--11. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" "0x000=Divide-by-1,0x001=Divide-by-2 0x2 to,0xFFF=Divide-by-3 to divide-by-4096" line.long 0x18 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" line.long 0x1C "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit" "XSTAFRM_0,XSTAFRM_1" newline bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data-ready interrupt enable bit" "XDATA_0,XDATA_1" newline bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit" "XLAST_0,XLAST_1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit" "XUNDRN_0,XUNDRN_1" line.long 0x20 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the MCASP logic has priority and the flag remains set" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" newline bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" newline bitfld.long 0x20 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" newline bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" line.long 0x24 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 0.--8. 1. "XSLOTCNT,Current transmit time slot count" line.long 0x28 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x28 16.--23. 1. "XMAX,0x0 to" newline hexmask.long.byte 0x28 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x28 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 0.--3. "XPS,Transmit clock check prescaler value" "MCASP interface clock divided by 1,MCASP interface clock divided by 2,MCASP interface clock divided by 4,MCASP interface clock divided by 8,MCASP interface clock divided by 16,MCASP interface clock divided by 32,MCASP interface clock divided by 64,MCASP interface clock divided by 128,MCASP interface clock divided by 256 0x9 to,?,?,?,?,?,?,Reserved" line.long 0x2C "MCASP_XEVTCTL,Transmitter DMA event control register" hexmask.long 0x2C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" line.long 0x30 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" hexmask.long 0x30 1.--31. 1. "RESERVED," bitfld.long 0x30 0. "ENABLE,One-shot clock adjust enable" "ENABLE_0,ENABLE_1" group.long 0x100++0x5F line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x04 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x08 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x0C "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x10 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x14 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x18 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x1C "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x20 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x24 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x28 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x2C "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x30 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x34 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x38 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x3C "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x40 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x44 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x48 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x4C "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x50 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x54 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x58 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x5C "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x180++0x17 line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" hexmask.long 0x00 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x04 "MCASP_XRSRCTLn_1,Serializer n control register" hexmask.long 0x04 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x04 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x04 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x04 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x08 "MCASP_XRSRCTLn_2,Serializer n control register" hexmask.long 0x08 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x08 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x08 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x08 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x08 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x0C "MCASP_XRSRCTLn_3,Serializer n control register" hexmask.long 0x0C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0C 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x0C 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x0C 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x0C 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x10 "MCASP_XRSRCTLn_4,Serializer n control register" hexmask.long 0x10 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x14 "MCASP_XRSRCTLn_5,Serializer n control register" hexmask.long 0x14 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" group.long 0x200++0x17 line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x04 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x08 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x0C "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x10 "MCASP_TXBUFn_4,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x14 "MCASP_TXBUFn_5,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x280++0x17 line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x04 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x08 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x0C "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x10 "MCASP_RXBUFn_4,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x14 "MCASP_RXBUFn_5,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" width 0x0B tree.end tree "MCASP3_DAT" base ad:0x4843A000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" width 0x0B tree.end tree "MCASP_CFG_TARG" base ad:0x48462000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCRC" base ad:0x4BC00000 group.long 0x00++0x03 line.long 0x00 "CRC_CTRL0," hexmask.long.byte 0x00 25.--31. 1. "RESERVED," newline bitfld.long 0x00 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset" newline hexmask.long.byte 0x00 17.--23. 1. "RESERVED," newline bitfld.long 0x00 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," newline bitfld.long 0x00 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset" group.long 0x08++0x03 line.long 0x00 "CRC_CTRL1," hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "PWDN,Power Down" "MCRC is not in power down mode,MCRC is in power down mode" group.long 0x10++0x03 line.long 0x00 "CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 24.--25. "CH4_MODE,Channel 4 Mode" "Data Capture mode,AUTO mode,?,Full-CPU mode For all four channels the seed.." newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 16.--17. "CH3_MODE,Channel 3 Mode" "Data Capture mode,AUTO mode,?,Full-CPU mode" newline rbitfld.long 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--9. "CH2_MODE,Channel 2 Mode" "Data Capture mode,AUTO mode,?,Full-CPU mode" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode" "Data Trace disable,Data Trace enable" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 0.--1. "CH1_MODE,Channel 1 Mode" "Data Capture mode,AUTO mode,?,Full-CPU mode" group.long 0x18++0x03 line.long 0x00 "CRC_INTS," rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 28. "CH4_TIME_OUT_ENS,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable" newline bitfld.long 0x00 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable" newline bitfld.long 0x00 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable" newline bitfld.long 0x00 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable" newline bitfld.long 0x00 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable" newline rbitfld.long 0x00 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable" newline bitfld.long 0x00 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable" newline bitfld.long 0x00 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable" newline bitfld.long 0x00 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable" newline bitfld.long 0x00 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable" newline rbitfld.long 0x00 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12. "CH2_TIME_OUT_ENS,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable" newline bitfld.long 0x00 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable" newline bitfld.long 0x00 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable" newline bitfld.long 0x00 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable" newline bitfld.long 0x00 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "CH1_TIME_OUT_ENS,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable" newline bitfld.long 0x00 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable" newline bitfld.long 0x00 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable" newline bitfld.long 0x00 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable" newline bitfld.long 0x00 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable" group.long 0x20++0x03 line.long 0x00 "CRC_INTR," rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable" newline bitfld.long 0x00 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable" newline bitfld.long 0x00 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable" newline bitfld.long 0x00 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable" newline bitfld.long 0x00 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable" newline rbitfld.long 0x00 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. "CH3_TIME_OUT_ENR,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable" newline bitfld.long 0x00 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable" newline bitfld.long 0x00 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable" newline bitfld.long 0x00 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable" newline bitfld.long 0x00 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable" newline rbitfld.long 0x00 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12. "CH2_TIME_OUT_ENR,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable" newline bitfld.long 0x00 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable" newline bitfld.long 0x00 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable" newline bitfld.long 0x00 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable" newline bitfld.long 0x00 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "CH1_TIME_OUT_ENR,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable" newline bitfld.long 0x00 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable" newline bitfld.long 0x00 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable" newline bitfld.long 0x00 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable" newline bitfld.long 0x00 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable" group.long 0x28++0x03 line.long 0x00 "CRC_STATUS," rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active" newline bitfld.long 0x00 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active" newline bitfld.long 0x00 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active" newline bitfld.long 0x00 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active" newline bitfld.long 0x00 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.." newline rbitfld.long 0x00 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active" newline bitfld.long 0x00 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active" newline bitfld.long 0x00 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active" newline bitfld.long 0x00 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active" newline bitfld.long 0x00 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.." newline rbitfld.long 0x00 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active" newline bitfld.long 0x00 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active" newline bitfld.long 0x00 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active" newline bitfld.long 0x00 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active" newline bitfld.long 0x00 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.." newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active" newline bitfld.long 0x00 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active" newline bitfld.long 0x00 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active" newline bitfld.long 0x00 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active" newline bitfld.long 0x00 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.." group.long 0x30++0x03 line.long 0x00 "CRC_INT_OFFSET_REG," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--7. 1. "CRC,Interrupt Offset" rgroup.long 0x38++0x03 line.long 0x00 "CRC_BUSY," hexmask.long.byte 0x00 25.--31. 1. "RESERVED," newline bitfld.long 0x00 24. "CH4_BUSY,ARRAY(0x243e780)" "0,1" newline hexmask.long.byte 0x00 17.--23. 1. "RESERVED," newline bitfld.long 0x00 16. "CH3_BUSY,ARRAY(0x243e9a0)" "0,1" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "CH2_BUSY,ARRAY(0x243eba0)" "0,1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," newline bitfld.long 0x00 0. "CH1_BUSY,ARRAY(0x243eda0)" "0,1" group.long 0x40++0x13 line.long 0x00 "CRC_PCOUNT_REG1," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register" line.long 0x04 "CRC_SCOUNT_REG1," hexmask.long.word 0x04 16.--31. 1. "RESERVED," newline hexmask.long.word 0x04 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register" line.long 0x08 "CRC_CURSEC_REG1," hexmask.long.word 0x08 16.--31. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register" line.long 0x0C "CRC_WDTOPLD1," hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x0C 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register" line.long 0x10 "CRC_BCTOPLD1," hexmask.long.byte 0x10 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register" group.long 0x60++0x33 line.long 0x00 "PSA_SIGREGL1," line.long 0x04 "PSA_SIGREGH1," line.long 0x08 "CRC_REGL1," line.long 0x0C "CRC_REGH1," line.long 0x10 "PSA_SECSIGREGL1," line.long 0x14 "PSA_SECSIGREGH1," line.long 0x18 "RAW_DATAREGL1," line.long 0x1C "RAW_DATAREGH1," line.long 0x20 "CRC_PCOUNT_REG2," hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed" line.long 0x24 "CRC_SCOUNT_REG2," hexmask.long.word 0x24 16.--31. 1. "RESERVED," newline hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register" line.long 0x28 "CRC_CURSEC_REG2," hexmask.long.word 0x28 16.--31. 1. "RESERVED," newline hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register" line.long 0x2C "CRC_WDTOPLD2," hexmask.long.byte 0x2C 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register" line.long 0x30 "CRC_BCTOPLD2," hexmask.long.byte 0x30 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register" group.long 0xA0++0x33 line.long 0x00 "PSA_SIGREGL2," line.long 0x04 "PSA_SIGREGH2," line.long 0x08 "CRC_REGL2," line.long 0x0C "CRC_REGH2," line.long 0x10 "PSA_SECSIGREGL2," line.long 0x14 "PSA_SECSIGREGH2," line.long 0x18 "RAW_DATAREGL2," line.long 0x1C "RAW_DATAREGH2," line.long 0x20 "CRC_PCOUNT_REG3," hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register" line.long 0x24 "CRC_SCOUNT_REG3," hexmask.long.word 0x24 16.--31. 1. "RESERVED," newline hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register" line.long 0x28 "CRC_CURSEC_REG3," hexmask.long.word 0x28 16.--31. 1. "RESERVED," newline hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register" line.long 0x2C "CRC_WDTOPLD3," hexmask.long.word 0x2C 16.--31. 1. "RESERVED," newline hexmask.long.word 0x2C 0.--15. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register" line.long 0x30 "CRC_BCTOPLD3," hexmask.long.byte 0x30 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register" group.long 0xE0++0x33 line.long 0x00 "PSA_SIGREGL3," line.long 0x04 "PSA_SIGREGH3," line.long 0x08 "CRC_REGL3," line.long 0x0C "CRC_REGH3," line.long 0x10 "PSA_SECSIGREGL3," line.long 0x14 "PSA_SECSIGREGH3," line.long 0x18 "RAW_DATAREGL3," line.long 0x1C "RAW_DATAREGH3," line.long 0x20 "CRC_PCOUNT_REG4," hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register" line.long 0x24 "CRC_SCOUNT_REG4," hexmask.long.word 0x24 16.--31. 1. "RESERVED," newline hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register" line.long 0x28 "CRC_CURSEC_REG4," hexmask.long.word 0x28 16.--31. 1. "RESERVED," newline hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails" line.long 0x2C "CRC_WDTOPLD4," hexmask.long.byte 0x2C 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns" line.long 0x30 "CRC_BCTOPLD4," hexmask.long.byte 0x30 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated" group.long 0x120++0x23 line.long 0x00 "PSA_SIGREGL4," hexmask.long.byte 0x00 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--23. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register" line.long 0x04 "PSA_SIGREGH4," line.long 0x08 "CRC_REGL4," line.long 0x0C "CRC_REGH4," line.long 0x10 "PSA_SECSIGREGL4," line.long 0x14 "PSA_SECSIGREGH4," line.long 0x18 "RAW_DATAREGL4," line.long 0x1C "RAW_DATAREGH4," line.long 0x20 "MCRC_BUS_SEL," hexmask.long 0x20 3.--31. 1. "RESERVED," newline bitfld.long 0x20 2. "MEN,Enable/disables the tracing of VBUSM" "Tracing of VBUSM master bus has been disabled,Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x20 1. "DTC_MEN,Enable/disables the tracing of data TCM" "Tracing of DTCM_ODD and DTCM_EVEN buses have..,Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x20 0. "ITC_MEN,Enable/disables the tracing of instruction TCM" "Tracing of ITCM bus has been disabled,Tracing of ITCM bus has been enabled Please.." width 0x0B tree.end repeat 2. (list 2. 3. )(list ad:0x4809A000 ad:0x480B8000 ) tree "MCSPI$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any)" hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to 0 and writes to them are ignored" bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter" "Retention mode disabled,Retention mode enabled" bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This field defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "?,FFNBYTE_1_r,FFNBYTE_2_r,?,FFNBYTE_4_r,?,?,?,FFNBYTE_8_r,?,?,?,?,?,?,?,FFNBYTE_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management" "USEFIFO_0_r,USEFIFO_1_r" group.long 0x10++0x03 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" hexmask.long 0x00 4.--31. 1. "RSVD," bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_w" rgroup.long 0x100++0x03 line.long 0x00 "MCSPI_REVISION,This register contains the revision number" group.long 0x110++0x1F line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface and is not affected by software reset" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" bitfld.long 0x00 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "SIDLEMODE,Power management" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wake-up feature control" "ENAWAKEUP_0,ENAWAKEUP_1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock-gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved for module specific status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]" "EOW_0_r,EOW_1_w" bitfld.long 0x08 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "WKS_0_w,WKS_1_r" newline bitfld.long 0x08 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full" "RX3_FULL_0_w,RX3_FULL_1_r" bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow" "TX3_UNDERFLOW_0_w,TX3_UNDERFLOW_1_r" newline bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty" "TX3_EMPTY_0_w,TX3_EMPTY_1_r" bitfld.long 0x08 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full" "RX2_FULL_0_w,RX2_FULL_1_r" newline bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow" "TX2_UNDERFLOW_0_w,TX2_UNDERFLOW_1_r" bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty" "TX2_EMPTY_0_w,TX2_EMPTY_1_r" bitfld.long 0x08 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full" "RX1_FULL_0_w,RX1_FULL_1_r" bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow" "TX1_UNDERFLOW_0_w,TX1_UNDERFLOW_1_r" bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty" "TX1_EMPTY_0_w,TX1_EMPTY_1_r" newline bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only)" "RX0_OVERFLOW_0_w,RX0_OVERFLOW_1_r" bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full" "RX0_FULL_0_w,RX0_FULL_1_r" bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow" "TX0_UNDERFLOW_0_w,TX0_UNDERFLOW_1_r" newline bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty" "TX0_EMPTY_0_w,TX0_EMPTY_1_r" line.long 0x0C "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis" hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "EOW_ENABLE_0,EOW_ENABLE_1" bitfld.long 0x0C 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "WKE_0,WKE_1" newline bitfld.long 0x0C 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX3_FULL_ENABLE_0,RX3_FULL_ENABLE_1" bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX3_UNDERFLOW_ENABLE_0,TX3_UNDERFLOW_ENABLE_1" newline bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX3_EMPTY_ENABLE_0,TX3_EMPTY_ENABLE_1" bitfld.long 0x0C 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX2_FULL_ENABLE_0,RX2_FULL_ENABLE_1" newline bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX2_UNDERFLOW_ENABLE_0,TX2_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX2_EMPTY_ENABLE_0,TX2_EMPTY_ENABLE_1" bitfld.long 0x0C 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX1_FULL_ENABLE_0,RX1_FULL_ENABLE_1" bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX1_UNDERFLOW_ENABLE_0,TX1_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX1_EMPTY_ENABLE_0,TX1_EMPTY_ENABLE_1" newline bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable" "RX0_OVERFLOW_ENABLE_0,RX0_OVERFLOW_ENABLE_1" bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX0_FULL_ENABLE_0,RX0_FULL_ENABLE_1" bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX0_UNDERFLOW_ENABLE_0,TX0_UNDERFLOW_ENABLE_1" newline bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX0_EMPTY_ENABLE_0,TX0_EMPTY_ENABLE_1" line.long 0x10 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis" hexmask.long 0x10 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x10 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "WKEN_0,WKEN_1" line.long 0x14 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode" hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "SSB_0,SSB_1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "SPIENDIR_0,SPIENDIR_1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "SPIDATDIR1_0,SPIDATDIR1_1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "SPIDATDIR0_0,SPIDATDIR0_1" bitfld.long 0x14 7. "WAKD,SWAKEUP output (signal data value of internal signal to system)" "WAKD_0,WAKD_1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction) this bit returns the value on the CLKSPI line (high or low) and a write into this bit has no effect" "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction) the SPIDAT[1] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction) the SPIDAT[0] line is driven high or low according to the value written into this bit" "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[3] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[2] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[1] line is driven high or low according to the value written into this bit" "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[0] line is driven high or low according to the value written into this bit" "0,1" line.long 0x18 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface" hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA address 256-bit aligned this bit is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address" "FDAA_0,FDAA_1" bitfld.long 0x18 7. "MOA,Multiple word OCP access: this bit can only be used when a channel is enabled using a FIFO" "MOA_0,MOA_1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial SPI delay for first transfer: this field is an option only available in SINGLE master mode" "INITDLY_0,INITDLY_1,INITDLY_2,INITDLY_3,INITDLY_4,?,?,?" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "SYSTEM_TEST_0,SYSTEM_TEST_1" bitfld.long 0x18 2. "MS,Master/slave" "MS_0,MS_1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This bit is used in master or slave mode to configure the SPI pin mode (3-pin or 4-pin)" "PIN34_0,PIN34_1" bitfld.long 0x18 0. "SINGLE,Single channel/Multi Channel (master mode only)" "SINGLE_0,SINGLE_1" line.long 0x1C "MCSPI_CHxCONF_0,This register is dedicated to the configuration of the channel x" rbitfld.long 0x1C 30.--31. "RESERVED,Read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x1C 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x1C 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" newline bitfld.long 0x1C 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x1C 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x1C 17. "DPE1,Transmission enable for data line 1" "DPE1_0,DPE1_1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0" "DPE0_0,DPE0_1" bitfld.long 0x1C 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x1C 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x1C 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" newline bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x1C 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x1C 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" group.long 0x140++0x03 line.long 0x00 "MCSPI_CHxCONF_1,This register is dedicated to the configuration of the channel x" rbitfld.long 0x00 30.--31. "RESERVED,Read returns 0" "0,1,2,3" bitfld.long 0x00 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x00 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" newline bitfld.long 0x00 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x00 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x00 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" newline bitfld.long 0x00 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x00 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" bitfld.long 0x00 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" newline bitfld.long 0x00 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x00 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x00 17. "DPE1,Transmission enable for data line 1" "DPE1_0,DPE1_1" newline bitfld.long 0x00 16. "DPE0,Transmission Enable for data line 0" "DPE0_0,DPE0_1" bitfld.long 0x00 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x00 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x00 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x00 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x00 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" newline bitfld.long 0x00 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x00 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x00 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" rgroup.long 0x130++0x03 line.long 0x00 "MCSPI_CHxSTAT_0,This register provides status information about transmitter and receiver registers of channel x" hexmask.long 0x00 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" newline bitfld.long 0x00 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" newline bitfld.long 0x00 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" rgroup.long 0x144++0x03 line.long 0x00 "MCSPI_CHxSTAT_1,This register provides status information about transmitter and receiver registers of channel x" hexmask.long 0x00 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" newline bitfld.long 0x00 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" newline bitfld.long 0x00 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" group.long 0x134++0x03 line.long 0x00 "MCSPI_CHxCTRL_0,This register is dedicated to enable channel x" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" hexmask.long.byte 0x00 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" group.long 0x148++0x03 line.long 0x00 "MCSPI_CHxCTRL_1,This register is dedicated to enable channel x" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" hexmask.long.byte 0x00 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" group.long 0x138++0x03 line.long 0x00 "MCSPI_TXx_0,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" group.long 0x14C++0x03 line.long 0x00 "MCSPI_TXx_1,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" rgroup.long 0x13C++0x03 line.long 0x00 "MCSPI_RXx_0,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" rgroup.long 0x150++0x03 line.long 0x00 "MCSPI_RXx_1,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" group.long 0x17C++0x07 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer" hexmask.long.word 0x00 16.--31. 1. "WCNT,SPI word counter" hexmask.long.byte 0x00 8.--15. 1. "AFL,Buffer almost full this field holds the programmable almost full level value used to determine almost full buffer condition" hexmask.long.byte 0x00 0.--7. 1. "AEL,Buffer almost empty" line.long 0x04 "MCSPI_DAFTX,This register contains the SPI words to be transmitted on the SPI bus when FIFO is used and DMA address is aligned on 256 bit" rgroup.long 0x1A0++0x03 line.long 0x00 "MCSPI_DAFRX,This register contains the SPI words received from the SPI bus when FIFO is used and DMA address is aligned on 256 bit" width 0x0B tree.end repeat.end tree "MCSPI1" base ad:0x48098000 rgroup.long 0x00++0x07 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any)" hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to 0 and writes to them are ignored" bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter" "Retention mode disabled,Retention mode enabled" bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This field defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "?,FFNBYTE_1_r,FFNBYTE_2_r,?,FFNBYTE_4_r,?,?,?,FFNBYTE_8_r,?,?,?,?,?,?,?,FFNBYTE_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management" "USEFIFO_0_r,USEFIFO_1_r" group.long 0x10++0x03 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" hexmask.long 0x00 4.--31. 1. "RSVD," bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_w" rgroup.long 0x100++0x03 line.long 0x00 "MCSPI_REVISION,This register contains the revision number" group.long 0x110++0x1F line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface and is not affected by software reset" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" bitfld.long 0x00 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "SIDLEMODE,Power management" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wake-up feature control" "ENAWAKEUP_0,ENAWAKEUP_1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock-gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved for module specific status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]" "EOW_0_r,EOW_1_w" bitfld.long 0x08 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "WKS_0_w,WKS_1_r" newline bitfld.long 0x08 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full" "RX3_FULL_0_w,RX3_FULL_1_r" bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow" "TX3_UNDERFLOW_0_w,TX3_UNDERFLOW_1_r" newline bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty" "TX3_EMPTY_0_w,TX3_EMPTY_1_r" bitfld.long 0x08 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full" "RX2_FULL_0_w,RX2_FULL_1_r" newline bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow" "TX2_UNDERFLOW_0_w,TX2_UNDERFLOW_1_r" bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty" "TX2_EMPTY_0_w,TX2_EMPTY_1_r" bitfld.long 0x08 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full" "RX1_FULL_0_w,RX1_FULL_1_r" bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow" "TX1_UNDERFLOW_0_w,TX1_UNDERFLOW_1_r" bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty" "TX1_EMPTY_0_w,TX1_EMPTY_1_r" newline bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only)" "RX0_OVERFLOW_0_w,RX0_OVERFLOW_1_r" bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full" "RX0_FULL_0_w,RX0_FULL_1_r" bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow" "TX0_UNDERFLOW_0_w,TX0_UNDERFLOW_1_r" newline bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty" "TX0_EMPTY_0_w,TX0_EMPTY_1_r" line.long 0x0C "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis" hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "EOW_ENABLE_0,EOW_ENABLE_1" bitfld.long 0x0C 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "WKE_0,WKE_1" newline bitfld.long 0x0C 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX3_FULL_ENABLE_0,RX3_FULL_ENABLE_1" bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX3_UNDERFLOW_ENABLE_0,TX3_UNDERFLOW_ENABLE_1" newline bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX3_EMPTY_ENABLE_0,TX3_EMPTY_ENABLE_1" bitfld.long 0x0C 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX2_FULL_ENABLE_0,RX2_FULL_ENABLE_1" newline bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX2_UNDERFLOW_ENABLE_0,TX2_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX2_EMPTY_ENABLE_0,TX2_EMPTY_ENABLE_1" bitfld.long 0x0C 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX1_FULL_ENABLE_0,RX1_FULL_ENABLE_1" bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX1_UNDERFLOW_ENABLE_0,TX1_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX1_EMPTY_ENABLE_0,TX1_EMPTY_ENABLE_1" newline bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable" "RX0_OVERFLOW_ENABLE_0,RX0_OVERFLOW_ENABLE_1" bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX0_FULL_ENABLE_0,RX0_FULL_ENABLE_1" bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX0_UNDERFLOW_ENABLE_0,TX0_UNDERFLOW_ENABLE_1" newline bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX0_EMPTY_ENABLE_0,TX0_EMPTY_ENABLE_1" line.long 0x10 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis" hexmask.long 0x10 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x10 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "WKEN_0,WKEN_1" line.long 0x14 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode" hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "SSB_0,SSB_1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "SPIENDIR_0,SPIENDIR_1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "SPIDATDIR1_0,SPIDATDIR1_1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "SPIDATDIR0_0,SPIDATDIR0_1" bitfld.long 0x14 7. "WAKD,SWAKEUP output (signal data value of internal signal to system)" "WAKD_0,WAKD_1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction) this bit returns the value on the CLKSPI line (high or low) and a write into this bit has no effect" "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction) the SPIDAT[1] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction) the SPIDAT[0] line is driven high or low according to the value written into this bit" "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[3] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[2] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[1] line is driven high or low according to the value written into this bit" "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[0] line is driven high or low according to the value written into this bit" "0,1" line.long 0x18 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface" hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA address 256-bit aligned this bit is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address" "FDAA_0,FDAA_1" bitfld.long 0x18 7. "MOA,Multiple word OCP access: this bit can only be used when a channel is enabled using a FIFO" "MOA_0,MOA_1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial SPI delay for first transfer: this field is an option only available in SINGLE master mode" "INITDLY_0,INITDLY_1,INITDLY_2,INITDLY_3,INITDLY_4,?,?,?" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "SYSTEM_TEST_0,SYSTEM_TEST_1" bitfld.long 0x18 2. "MS,Master/slave" "MS_0,MS_1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This bit is used in master or slave mode to configure the SPI pin mode (3-pin or 4-pin)" "PIN34_0,PIN34_1" bitfld.long 0x18 0. "SINGLE,Single channel/Multi Channel (master mode only)" "SINGLE_0,SINGLE_1" line.long 0x1C "MCSPI_CHxCONF_0,This register is dedicated to the configuration of the channel x" rbitfld.long 0x1C 30.--31. "RESERVED,Read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x1C 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x1C 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" newline bitfld.long 0x1C 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x1C 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x1C 17. "DPE1,Transmission enable for data line 1" "DPE1_0,DPE1_1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0" "DPE0_0,DPE0_1" bitfld.long 0x1C 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x1C 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x1C 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" newline bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x1C 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x1C 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" group.long 0x140++0x03 line.long 0x00 "MCSPI_CHxCONF_1,This register is dedicated to the configuration of the channel x" rbitfld.long 0x00 30.--31. "RESERVED,Read returns 0" "0,1,2,3" bitfld.long 0x00 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x00 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" newline bitfld.long 0x00 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x00 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x00 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" newline bitfld.long 0x00 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x00 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" bitfld.long 0x00 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" newline bitfld.long 0x00 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x00 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x00 17. "DPE1,Transmission enable for data line 1" "DPE1_0,DPE1_1" newline bitfld.long 0x00 16. "DPE0,Transmission Enable for data line 0" "DPE0_0,DPE0_1" bitfld.long 0x00 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x00 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x00 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x00 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x00 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" newline bitfld.long 0x00 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x00 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x00 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" group.long 0x154++0x03 line.long 0x00 "MCSPI_CHxCONF_2,This register is dedicated to the configuration of the channel x" rbitfld.long 0x00 30.--31. "RESERVED,Read returns 0" "0,1,2,3" bitfld.long 0x00 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x00 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" newline bitfld.long 0x00 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x00 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x00 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" newline bitfld.long 0x00 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x00 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" bitfld.long 0x00 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" newline bitfld.long 0x00 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x00 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x00 17. "DPE1,Transmission enable for data line 1" "DPE1_0,DPE1_1" newline bitfld.long 0x00 16. "DPE0,Transmission Enable for data line 0" "DPE0_0,DPE0_1" bitfld.long 0x00 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x00 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x00 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x00 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x00 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" newline bitfld.long 0x00 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x00 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x00 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" group.long 0x168++0x03 line.long 0x00 "MCSPI_CHxCONF_3,This register is dedicated to the configuration of the channel x" rbitfld.long 0x00 30.--31. "RESERVED,Read returns 0" "0,1,2,3" bitfld.long 0x00 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x00 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" newline bitfld.long 0x00 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x00 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x00 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" newline bitfld.long 0x00 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x00 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" bitfld.long 0x00 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" newline bitfld.long 0x00 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x00 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x00 17. "DPE1,Transmission enable for data line 1" "DPE1_0,DPE1_1" newline bitfld.long 0x00 16. "DPE0,Transmission Enable for data line 0" "DPE0_0,DPE0_1" bitfld.long 0x00 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x00 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x00 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x00 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x00 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" newline bitfld.long 0x00 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x00 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x00 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" rgroup.long 0x130++0x03 line.long 0x00 "MCSPI_CHxSTAT_0,This register provides status information about transmitter and receiver registers of channel x" hexmask.long 0x00 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" newline bitfld.long 0x00 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" newline bitfld.long 0x00 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" rgroup.long 0x144++0x03 line.long 0x00 "MCSPI_CHxSTAT_1,This register provides status information about transmitter and receiver registers of channel x" hexmask.long 0x00 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" newline bitfld.long 0x00 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" newline bitfld.long 0x00 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" rgroup.long 0x158++0x03 line.long 0x00 "MCSPI_CHxSTAT_2,This register provides status information about transmitter and receiver registers of channel x" hexmask.long 0x00 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" newline bitfld.long 0x00 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" newline bitfld.long 0x00 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" rgroup.long 0x16C++0x03 line.long 0x00 "MCSPI_CHxSTAT_3,This register provides status information about transmitter and receiver registers of channel x" hexmask.long 0x00 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" newline bitfld.long 0x00 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" newline bitfld.long 0x00 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" group.long 0x134++0x03 line.long 0x00 "MCSPI_CHxCTRL_0,This register is dedicated to enable channel x" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" hexmask.long.byte 0x00 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" group.long 0x148++0x03 line.long 0x00 "MCSPI_CHxCTRL_1,This register is dedicated to enable channel x" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" hexmask.long.byte 0x00 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" group.long 0x15C++0x03 line.long 0x00 "MCSPI_CHxCTRL_2,This register is dedicated to enable channel x" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" hexmask.long.byte 0x00 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" group.long 0x170++0x03 line.long 0x00 "MCSPI_CHxCTRL_3,This register is dedicated to enable channel x" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" hexmask.long.byte 0x00 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" group.long 0x138++0x03 line.long 0x00 "MCSPI_TXx_0,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" group.long 0x14C++0x03 line.long 0x00 "MCSPI_TXx_1,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" group.long 0x160++0x03 line.long 0x00 "MCSPI_TXx_2,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" group.long 0x174++0x03 line.long 0x00 "MCSPI_TXx_3,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" rgroup.long 0x13C++0x03 line.long 0x00 "MCSPI_RXx_0,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" rgroup.long 0x150++0x03 line.long 0x00 "MCSPI_RXx_1,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" rgroup.long 0x164++0x03 line.long 0x00 "MCSPI_RXx_2,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" rgroup.long 0x178++0x0B line.long 0x00 "MCSPI_RXx_3,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" line.long 0x04 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer" hexmask.long.word 0x04 16.--31. 1. "WCNT,SPI word counter" hexmask.long.byte 0x04 8.--15. 1. "AFL,Buffer almost full this field holds the programmable almost full level value used to determine almost full buffer condition" hexmask.long.byte 0x04 0.--7. 1. "AEL,Buffer almost empty" line.long 0x08 "MCSPI_DAFTX,This register contains the SPI words to be transmitted on the SPI bus when FIFO is used and DMA address is aligned on 256 bit" rgroup.long 0x1A0++0x03 line.long 0x00 "MCSPI_DAFRX,This register contains the SPI words received from the SPI bus when FIFO is used and DMA address is aligned on 256 bit" width 0x0B tree.end tree "MCSPI1_TARG" base ad:0x48099000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCSPI2_TARG" base ad:0x4809B000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCSPI3_TARG" base ad:0x480B9000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCSPI4" base ad:0x480BA000 rgroup.long 0x00++0x07 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any)" hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to 0 and writes to them are ignored" bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter" "Retention mode disabled,Retention mode enabled" bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This field defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "?,FFNBYTE_1_r,FFNBYTE_2_r,?,FFNBYTE_4_r,?,?,?,FFNBYTE_8_r,?,?,?,?,?,?,?,FFNBYTE_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management" "USEFIFO_0_r,USEFIFO_1_r" group.long 0x10++0x03 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" hexmask.long 0x00 4.--31. 1. "RSVD," bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_w" rgroup.long 0x100++0x03 line.long 0x00 "MCSPI_REVISION,This register contains the revision number" group.long 0x110++0x2F line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface and is not affected by software reset" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" bitfld.long 0x00 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "SIDLEMODE,Power management" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wake-up feature control" "ENAWAKEUP_0,ENAWAKEUP_1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock-gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved for module specific status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]" "EOW_0_r,EOW_1_w" bitfld.long 0x08 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "WKS_0_w,WKS_1_r" newline bitfld.long 0x08 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full" "RX3_FULL_0_w,RX3_FULL_1_r" bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow" "TX3_UNDERFLOW_0_w,TX3_UNDERFLOW_1_r" newline bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty" "TX3_EMPTY_0_w,TX3_EMPTY_1_r" bitfld.long 0x08 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full" "RX2_FULL_0_w,RX2_FULL_1_r" newline bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow" "TX2_UNDERFLOW_0_w,TX2_UNDERFLOW_1_r" bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty" "TX2_EMPTY_0_w,TX2_EMPTY_1_r" bitfld.long 0x08 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full" "RX1_FULL_0_w,RX1_FULL_1_r" bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow" "TX1_UNDERFLOW_0_w,TX1_UNDERFLOW_1_r" bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty" "TX1_EMPTY_0_w,TX1_EMPTY_1_r" newline bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only)" "RX0_OVERFLOW_0_w,RX0_OVERFLOW_1_r" bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full" "RX0_FULL_0_w,RX0_FULL_1_r" bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow" "TX0_UNDERFLOW_0_w,TX0_UNDERFLOW_1_r" newline bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty" "TX0_EMPTY_0_w,TX0_EMPTY_1_r" line.long 0x0C "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis" hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "EOW_ENABLE_0,EOW_ENABLE_1" bitfld.long 0x0C 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "WKE_0,WKE_1" newline bitfld.long 0x0C 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX3_FULL_ENABLE_0,RX3_FULL_ENABLE_1" bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX3_UNDERFLOW_ENABLE_0,TX3_UNDERFLOW_ENABLE_1" newline bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX3_EMPTY_ENABLE_0,TX3_EMPTY_ENABLE_1" bitfld.long 0x0C 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX2_FULL_ENABLE_0,RX2_FULL_ENABLE_1" newline bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX2_UNDERFLOW_ENABLE_0,TX2_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX2_EMPTY_ENABLE_0,TX2_EMPTY_ENABLE_1" bitfld.long 0x0C 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX1_FULL_ENABLE_0,RX1_FULL_ENABLE_1" bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX1_UNDERFLOW_ENABLE_0,TX1_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX1_EMPTY_ENABLE_0,TX1_EMPTY_ENABLE_1" newline bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable" "RX0_OVERFLOW_ENABLE_0,RX0_OVERFLOW_ENABLE_1" bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX0_FULL_ENABLE_0,RX0_FULL_ENABLE_1" bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX0_UNDERFLOW_ENABLE_0,TX0_UNDERFLOW_ENABLE_1" newline bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX0_EMPTY_ENABLE_0,TX0_EMPTY_ENABLE_1" line.long 0x10 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis" hexmask.long 0x10 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x10 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "WKEN_0,WKEN_1" line.long 0x14 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode" hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "SSB_0,SSB_1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "SPIENDIR_0,SPIENDIR_1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "SPIDATDIR1_0,SPIDATDIR1_1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "SPIDATDIR0_0,SPIDATDIR0_1" bitfld.long 0x14 7. "WAKD,SWAKEUP output (signal data value of internal signal to system)" "WAKD_0,WAKD_1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction) this bit returns the value on the CLKSPI line (high or low) and a write into this bit has no effect" "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction) the SPIDAT[1] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction) the SPIDAT[0] line is driven high or low according to the value written into this bit" "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[3] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[2] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[1] line is driven high or low according to the value written into this bit" "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[0] line is driven high or low according to the value written into this bit" "0,1" line.long 0x18 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface" hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA address 256-bit aligned this bit is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address" "FDAA_0,FDAA_1" bitfld.long 0x18 7. "MOA,Multiple word OCP access: this bit can only be used when a channel is enabled using a FIFO" "MOA_0,MOA_1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial SPI delay for first transfer: this field is an option only available in SINGLE master mode" "INITDLY_0,INITDLY_1,INITDLY_2,INITDLY_3,INITDLY_4,?,?,?" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "SYSTEM_TEST_0,SYSTEM_TEST_1" bitfld.long 0x18 2. "MS,Master/slave" "MS_0,MS_1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This bit is used in master or slave mode to configure the SPI pin mode (3-pin or 4-pin)" "PIN34_0,PIN34_1" bitfld.long 0x18 0. "SINGLE,Single channel/Multi Channel (master mode only)" "SINGLE_0,SINGLE_1" line.long 0x1C "MCSPI_CHxCONF,This register is dedicated to the configuration of the channel x" rbitfld.long 0x1C 30.--31. "RESERVED,Read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x1C 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x1C 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" newline bitfld.long 0x1C 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x1C 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x1C 17. "DPE1,Transmission enable for data line 1" "DPE1_0,DPE1_1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0" "DPE0_0,DPE0_1" bitfld.long 0x1C 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x1C 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x1C 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" newline bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x1C 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x1C 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" line.long 0x20 "MCSPI_CHxSTAT,This register provides status information about transmitter and receiver registers of channel x" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x20 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x20 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" newline bitfld.long 0x20 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x20 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x20 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" newline bitfld.long 0x20 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x20 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" line.long 0x24 "MCSPI_CHxCTRL,This register is dedicated to enable channel x" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x24 0. "EN,Channel enable" "EN_0,EN_1" line.long 0x28 "MCSPI_TXx,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" line.long 0x2C "MCSPI_RXx,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" group.long 0x17C++0x07 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer" hexmask.long.word 0x00 16.--31. 1. "WCNT,SPI word counter" hexmask.long.byte 0x00 8.--15. 1. "AFL,Buffer almost full this field holds the programmable almost full level value used to determine almost full buffer condition" hexmask.long.byte 0x00 0.--7. 1. "AEL,Buffer almost empty" line.long 0x04 "MCSPI_DAFTX,This register contains the SPI words to be transmitted on the SPI bus when FIFO is used and DMA address is aligned on 256 bit" rgroup.long 0x1A0++0x03 line.long 0x00 "MCSPI_DAFRX,This register contains the SPI words received from the SPI bus when FIFO is used and DMA address is aligned on 256 bit" width 0x0B tree.end tree "MCSPI4_TARG" base ad:0x480BB000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MDIO" base ad:0x48485000 group.long 0x00++0x17 line.long 0x00 "MDIO_VER,MDIO Revision" line.long 0x04 "MDIO_CONTROL,MDIO Control register" bitfld.long 0x04 31. "IDLE,MDIO state machine IDLE" "State machine is not in idle state,State machine is in idle state" newline bitfld.long 0x04 30. "ENABLE,Enable control" "Disables the MDIO state machine,Enable the MDIO state machine" newline rbitfld.long 0x04 29. "RESERVED," "0,1" newline rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "Standard MDIO preamble is used,Disables this device from sending MDIO frame.." newline bitfld.long 0x04 19. "FAULT,Fault indicator" "No failure,Physical layer fault; the.." newline bitfld.long 0x04 18. "FAULTENB,Fault detect enable" "Disables the physical layer fault detection,Enables the physical layer fault detection" newline bitfld.long 0x04 17. "INTTESTENB,Interrupt test enable" "Interrupt bits are not set,Enables the host to set the USERINT and LINKINT.." newline rbitfld.long 0x04 16. "RESERVED," "0,1" newline hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock divider" line.long 0x08 "MDIO_ALIVE,PHY Alive Status Register" line.long 0x0C "MDIO_LINK,PHY Link Status" line.long 0x10 "MDIO_LINKINTRAW," hexmask.long 0x10 2.--31. 1. "RESERVED," newline bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3" line.long 0x14 "MDIO_LINKINTMASKED,MDIO Link Status Change Interrupt Register" hexmask.long 0x14 2.--31. 1. "RESERVED," newline bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3" group.long 0x20++0x0F line.long 0x00 "MDIO_USERINTRAW,MDIO User Command Complete Interrupt" hexmask.long 0x00 2.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "USERINTRAW,Raw value of MDIO user command complete event for theMDIO_USERACCESS1 and MDIO_USERACCESS0 register respectively" "0,1,2,3" line.long 0x04 "MDIO_USERINTMASKED,MDIO User Command Complete Interrupt" hexmask.long 0x04 2.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--1. "USERINTMASKED,Masked value of MDIO user command complete interrupt for theMDIO_USERACCESS1 and MDIO_USERACCESS0 register respectively" "0,1,2,3" line.long 0x08 "MDIO_USERINTMASKSET,MDIO User Command Complete Interrupt Mask Set" hexmask.long 0x08 2.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--1. "USERINTMASKSET,MDIO user interrupt mask set for USERINTMASKED[1:0] respectively" "0,1,2,3" line.long 0x0C "MDIO_USERINTMASKCLR,MDIO User Command Complete Interrupt Mask Clear" hexmask.long 0x0C 2.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--1. "USERINTMASKCLEAR,MDIO user command complete interrupt mask clear for USERINTMASKED[1:0] respectively" "0,1,2,3" group.long 0x80++0x0F line.long 0x00 "MDIO_USERACCESS0,MDIO_User_Access" bitfld.long 0x00 31. "GO,Go" "0,1" newline bitfld.long 0x00 30. "WRITE,Write enable" "0,1" newline bitfld.long 0x00 29. "ACK,Acknowledge" "0,1" newline rbitfld.long 0x00 26.--28. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--15. 1. "DATA,User data" line.long 0x04 "MDIO_USERPHYSEL0,MDIO User PHY Select" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," newline bitfld.long 0x04 7. "LINKSEL,Link status determination select" "0,1" newline bitfld.long 0x04 6. "LINKINTENB,Link change interrupt enable" "Link change interrupts are disabled,Link change status interrupts for PHY address.." newline rbitfld.long 0x04 5. "RESERVED," "0,1" newline bitfld.long 0x04 0.--4. "PHYADDRMON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "MDIO_USERACCESS1,MDIO User Access" bitfld.long 0x08 31. "GO,Go" "0,1" newline bitfld.long 0x08 30. "WRITE,Write enable" "0,1" newline bitfld.long 0x08 29. "ACK,Acknowledge" "0,1" newline rbitfld.long 0x08 26.--28. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x08 0.--15. 1. "DATA,User data" line.long 0x0C "MDIO_USERPHYSEL1,MDIO User PHY Select" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED," newline bitfld.long 0x0C 7. "LINKSEL,Link status determination select" "0,1" newline bitfld.long 0x0C 6. "LINKINTENB,Link change interrupt enable" "Link change interrupts are disabled,Link change status interrupts for PHY address.." newline rbitfld.long 0x0C 5. "RESERVED," "0,1" newline bitfld.long 0x0C 0.--4. "PHYADDRMON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "MMC" base ad:0x480D1000 rgroup.long 0x00++0x07 line.long 0x00 "MMCHS_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "MMCHS_HL_HWINFO,Information about the IP module's hardware configuration" hexmask.long 0x04 7.--31. 1. "RESERVED," bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "RETMODE_0_r,RETMODE_1_r" bitfld.long 0x04 2.--5. "MEM_SIZE,Memory size for FIFO buffer" "?,MEM_SIZE_1_r,MEM_SIZE_2_r,?,MEM_SIZE_4_r,?,?,?,MEM_SIZE_8_r,?,?,?,?,?,?,?" newline bitfld.long 0x04 1. "MERGE_MEM,Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture" "MERGE_MEM_0_r,MERGE_MEM_1_r" bitfld.long 0x04 0. "MADMA_EN,Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA" "MADMA_EN_0_r,MADMA_EN_1_r" group.long 0x10++0x03 line.long 0x00 "MMCHS_HL_SYSCONFIG,Clock Management Configuration Register" hexmask.long 0x00 4.--31. 1. "RESERVED," bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_r" group.long 0x110++0x07 line.long 0x00 "MMCHS_SYSCONFIG,System Configuration Register This register allows controlling various parameters of the Interconnect interface" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" rbitfld.long 0x00 5.--7. "RESERVED,This bit is initialized to zero and writes to it are ignored" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "SIDLEMODE,Power management" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wakeup feature control" "ENAWAKEUP_0,ENAWAKEUP_1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_r" newline bitfld.long 0x00 0. "AUTOIDLE,Internal Clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMCHS_SYSSTATUS,System Status Register This register provides status information about the module excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "RESETDONE,Internal Reset Monitoring Note: the debounce clock the system clock (Interface) and the functional clock shall be provided to the SDIO host controller to allow the internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" group.long 0x124++0x0F line.long 0x00 "MMCHS_CSRE,Card Status Response Error This register enables the host controller to detect card status errors of response type R1. R1b for all cards and of R5. R5b and R6 response for cards types SD or SDIO" line.long 0x04 "MMCHS_SYSTEST,System Test Register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED," bitfld.long 0x04 13. "WAKD,Wake request output signal data value" "WAKD_0_r,WAKD_1_r" bitfld.long 0x04 12. "SSB,Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (MMCHS_STAT)" "SSB_0_r,SSB_1_r" newline rbitfld.long 0x04 8.--11. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 7. "D3D,DAT3 input/output signal data value" "D3D_0_r,D3D_1_r" bitfld.long 0x04 6. "D2D,DAT2 input/output signal data value" "D2D_0_r,D2D_1_r" newline bitfld.long 0x04 5. "D1D,DAT1 input/output signal data value" "D1D_0_r,D1D_1_r" bitfld.long 0x04 4. "D0D,DAT0 input/output signal data value" "D0D_0_r,D0D_1_r" bitfld.long 0x04 3. "DDIR,Control of the DAT[7:0] pins direction" "DDIR_0_r,DDIR_1_r" newline bitfld.long 0x04 2. "CDAT,CMD input/output signal data value" "CDAT_0_r,CDAT_1_r" bitfld.long 0x04 1. "CDIR,Control of the CMD pin direction" "CDIR_0_r,CDIR_1_r" bitfld.long 0x04 0. "MCKD,SDIO clock output signal data value" "MCKD_0_r,MCKD_1_r" line.long 0x08 "MMCHS_CON,Configuration Register This register is used: - to select the functional mode or the SYSTEST mode for any card" hexmask.long.word 0x08 22.--31. 1. "RESERVED," bitfld.long 0x08 21. "SDMA_LNE,Slave DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCHS_DATA register or late de-assertion request remains active until last allowed data written.." "SDMA_LNE_0,SDMA_LNE_1" bitfld.long 0x08 20. "DMA_MNS,DMA Master or Slave selection: When this bit is set and the controller is configured to use the DMA Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory).This option is only available.." "DMA_MNS_0,DMA_MNS_1" newline bitfld.long 0x08 19. "DDR,Dual Data Rate mode: When this register is set the controller uses both clock edge to emit or receive data" "DDR_0,DDR_1" rbitfld.long 0x08 17.--18. "RESERVED," "0,1,2,3" bitfld.long 0x08 16. "CLKEXTFREE,External clock free running: This register is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]" "CLKEXTFREE_0,CLKEXTFREE_1" newline bitfld.long 0x08 15. "PADEN,Control Power for SDIO Lines: This register is only useful when SDIO PADs contain power saving mechanism to minimize its leakage power" "PADEN_0,PADEN_1" rbitfld.long 0x08 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x08 11. "CTPL,Control Power for DAT[1] line SD cards: By default this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current" "CTPL_0,CTPL_1" newline bitfld.long 0x08 6.--10. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 5. "DW8,8-bit mode MMC select" "DW8_0,DW8_1" bitfld.long 0x08 4. "MODE,Mode select This bit select between Functional mode and SYSTEST mode" "MODE_0,MODE_1" newline rbitfld.long 0x08 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x08 1. "INIT,Send initialization stream All cards" "INIT_0,INIT_1" rbitfld.long 0x08 0. "RESERVED," "0,1" line.long 0x0C "MMCHS_PWCNT,Power Counter Register This register is used to program a counter to delay command transfers after activating the PAD power. this value depends on PAD characteristics and voltage" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," hexmask.long.word 0x0C 0.--15. 1. "PWRCNT,Power counter register" group.long 0x200++0x4B line.long 0x00 "MMCHS_SDMASA,This register contains the physical system memory address used for DMA transfers" line.long 0x04 "MMCHS_BLK,Transfer Length Configuration Register [BLEN] is the block size register" hexmask.long.word 0x04 16.--31. 1. "NBLK,Blocks count for current transfer This register is enabled when Block count Enable (MMCHS_CMD[BCE]) is set to 1 and is valid only for multiple block transfers" rbitfld.long 0x04 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. "BLEN,Transfer Block Size" line.long 0x08 "MMCHS_ARG,Command Argument Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register register)" line.long 0x0C "MMCHS_CMD,Command and Transfer Mode Register [31:16] = the command register [15:0] = the transfer mode" rbitfld.long 0x0C 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x0C 24.--29. "INDX,Command indexBinary encoded value from 0 to 63 specifying the command number send to card" "INDX_0,INDX_1,INDX_2,INDX_3,INDX_4,INDX_5,INDX_6,INDX_7,INDX_8,INDX_9,INDX_10,INDX_11,INDX_12,INDX_13,INDX_14,INDX_15,INDX_16,INDX_17,INDX_18,INDX_19,INDX_20,INDX_21,INDX_22,INDX_23,INDX_24,INDX_25,INDX_26,INDX_27,INDX_28,INDX_29,INDX_30,INDX_31,INDX_32,INDX_33,INDX_34,INDX_35,INDX_36,INDX_37,INDX_38,INDX_39,INDX_40,INDX_41,INDX_42,INDX_43,INDX_44,INDX_45,INDX_46,INDX_47,INDX_48,INDX_49,INDX_50,INDX_51,INDX_52,INDX_53,INDX_54,INDX_55,INDX_56,INDX_57,INDX_58,INDX_59,INDX_60,INDX_61,INDX_62,INDX_63" bitfld.long 0x0C 22.--23. "CMD_TYPE,Command typeThis register specifies three types of special command: Suspend Resume and Abort" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3" newline bitfld.long 0x0C 21. "DP,Data present selectThis register indicates that data is present and DAT line shall be used" "DP_0,DP_1" bitfld.long 0x0C 20. "CICE,Command Index check enableThis bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command" "CICE_0,CICE_1" bitfld.long 0x0C 19. "CCCE,Command CRC check enableThis bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus" "CCCE_0,CCCE_1" newline rbitfld.long 0x0C 18. "RESERVED," "0,1" bitfld.long 0x0C 16.--17. "RSP_TYPE,Response typeThis bits defines the response type of the command" "RSP_TYPE_0,RSP_TYPE_1,RSP_TYPE_2,RSP_TYPE_3" hexmask.long.word 0x0C 6.--15. 1. "RESERVED," newline bitfld.long 0x0C 5. "MSBS,Multi/Single block selectThis bit must be set to 1 for data transfer in case of multi block command" "MSBS_0,MSBS_1" bitfld.long 0x0C 4. "DDIR,Data transfer Direction SelectThis bit defines either data transfer will be a read or a" "DDIR_0,DDIR_1" bitfld.long 0x0C 2.--3. "ACEN,Auto CMD Enable - SD card only.This field determines use of auto command functions" "ACEN_0,ACEN_1,ACEN_2,ACEN_3" newline bitfld.long 0x0C 1. "BCE,Block Count EnableMultiple block transfers only" "BCE_0,BCE_1" bitfld.long 0x0C 0. "DE,DMA EnableThis bit is used to enable DMA mode for host data access" "DE_0,DE_1" line.long 0x10 "MMCHS_RSP10,Command Response[31:0] Register (bits [31:0] of the internal RSP register)" hexmask.long.word 0x10 16.--31. 1. "RSP1,Command Response [31:16]" hexmask.long.word 0x10 0.--15. 1. "RSP0,Command Response [15:0]" line.long 0x14 "MMCHS_RSP32,Command Response[63:32] Register (bits [63:32] of the internal RSP register) This 32-bit register holds bits positions [63:32] of command response type R2" hexmask.long.word 0x14 16.--31. 1. "RSP3,Command Response [63:48]" hexmask.long.word 0x14 0.--15. 1. "RSP2,Command Response [47:32]" line.long 0x18 "MMCHS_RSP54,Command Response[95:64] Register (bits [95:64] of the internal RSP register) This 32-bit register holds bits positions [95:64] of command response type R2" hexmask.long.word 0x18 16.--31. 1. "RSP5,Command Response [95:80]" hexmask.long.word 0x18 0.--15. 1. "RSP4,Command Response [79:64]" line.long 0x1C "MMCHS_RSP76,Command Response[127:96] Register (bits [127:96] of the internal RSP register) This 32-bit register holds bits positions [127:96] of command response type R1/R1b(Auto CMD12)/R2" hexmask.long.word 0x1C 16.--31. 1. "RSP7,Command Response [127:112]" hexmask.long.word 0x1C 0.--15. 1. "RSP6,Command Response [111:96]" line.long 0x20 "MMCHS_DATA,Data Register This register is the 32-bit entry point of the buffer for read or write data transfers" line.long 0x24 "MMCHS_PSTATE,Present State Register The Host can get status of the Host Controller from this 32-bit read only register" hexmask.long.byte 0x24 25.--31. 1. "RESERVED," bitfld.long 0x24 24. "CLEV,CMD line signal level This status is used to check the CMD line level to recover from errors and for debugging" "CLEV_0_r,CLEV_1_r" bitfld.long 0x24 20.--23. "DLEV,DAT[3:0] line signal level DAT[3] => bit 23 DAT[2] => bit 22 DAT[1] => bit 21 DAT[0] => bit 20 This status is used to check DAT line level to recover from errors and for debugging" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 12.--19. 1. "RESERVED," bitfld.long 0x24 11. "BRE,Buffer read enable This bit is used for non-DMA read transfers" "BRE_0_r,BRE_1_r" bitfld.long 0x24 10. "BWE,Buffer Write enable This status is used for non-DMA write transfers" "BWE_0_r,BWE_1_r" newline bitfld.long 0x24 9. "RTA,Read transfer active This status is used for detecting completion of a read transfer" "RTA_0_r,RTA_1_r" bitfld.long 0x24 8. "WTA,Write transfer active This status indicates a write transfer active" "WTA_0_r,WTA_1_r" bitfld.long 0x24 3.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x24 2. "DLA,DAT line active This status bit indicates whether one of the DAT line is in use" "DLA_0_r,DLA_1_r" bitfld.long 0x24 1. "DATI,Command inhibit(DAT) This status bit is generated if either DAT line is active (MMCHS_PSTATE[DLA]) or Read transfer is active (MMCHS_PSTATE[RTA]) or when a command with busy is issued" "DATI_0_r,DATI_1_r" bitfld.long 0x24 0. "CMDI,Command inhibit(CMD) This status bit indicates that the CMD line is in use" "CMDI_0_r,CMDI_1_r" line.long 0x28 "MMCHS_HCTL,Host Control Register This register defines the host controls to set power. wakeup and transfer parameters" hexmask.long.byte 0x28 25.--31. 1. "RESERVED," bitfld.long 0x28 24. "IWE,Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion" "IWE_0,IWE_1" rbitfld.long 0x28 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 19. "IBG,Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer" "IBG_0,IBG_1" bitfld.long 0x28 18. "RWC,Read wait control The read wait function is optional only for SDIO cards" "RWC_0,RWC_1" bitfld.long 0x28 17. "CR,Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (MMCHS_HCTL[SBGR])" "CR_0,CR_1" newline bitfld.long 0x28 16. "SBGR,Stop at block gap request This bit is used to stop executing a transaction at the next block gap" "SBGR_0,SBGR_1" rbitfld.long 0x28 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x28 9.--11. "SDVS,SD bus voltage select All cards" "?,?,?,?,?,SDVS_5,SDVS_6,SDVS_7" newline bitfld.long 0x28 8. "SDBP,SD bus power Before setting this bit the host driver shall select the SD bus voltage (MMCHS_HCTL[SDVS])" "SDBP_0,SDBP_1" rbitfld.long 0x28 3.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 2. "HSPE,Before setting this bit the Host Driver shall check theMMCHS_CAPA[21] HSS" "HSPE_0,HSPE_1" newline bitfld.long 0x28 1. "DTW,Data transfer width For SD/SDIO cards this bit must be set following a valid SET_BUS_WIDTH command (ACMD6) with the value written in bit 1 of the argument" "DTW_0,DTW_1" rbitfld.long 0x28 0. "RESERVED," "0,1" line.long 0x2C "MMCHS_SYSCTL,SD System Control Register This register defines the system controls to set software resets. clock frequency management and data timeout" rbitfld.long 0x2C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x2C 26. "SRD,Software reset for DAT line This bit is set to 1 for reset and released to 0 when completed" "SRD_0,SRD_1" bitfld.long 0x2C 25. "SRC,Software reset for CMD line For more information about SRC bit manipulation see" "SRC_0,SRC_1" newline bitfld.long 0x2C 24. "SRA,Software reset for all This bit is set to 1 for reset and released to 0 when completed" "SRA_0,SRA_1" rbitfld.long 0x2C 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x2C 16.--19. "DTO,Data timeout counter value and busy timeout" "DTO_0,DTO_1,?,?,?,?,?,?,?,?,?,?,?,?,DTO_14,DTO_15" newline hexmask.long.word 0x2C 6.--15. 1. "CLKD,Clock frequency select These bits define the ratio between MMC_FCLK and the output clock frequency on the mmc_clk pin" rbitfld.long 0x2C 5. "CGS,Clock Generator Select - For SD cards Host Controller Version 3.00 supports this bit" "0,1" rbitfld.long 0x2C 3.--4. "RESERVED," "0,1,2,3" newline bitfld.long 0x2C 2. "CEN,Clock enable This bit controls if the clock is provided to the card or not" "CEN_0,CEN_1" rbitfld.long 0x2C 1. "ICS,Internal clock stable (status) This bit indicates either the internal clock is stable or not" "ICS_0_r,ICS_1_r" bitfld.long 0x2C 0. "ICE,Internal clock enable This register controls the internal clock activity" "ICE_0,ICE_1" line.long 0x30 "MMCHS_STAT,Interrupt Status Register The interrupt status regroups all the status of the module internal events that can generate an interrupt" rbitfld.long 0x30 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x30 29. "BADA,Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register (MMCHS_DATA) while buffer reads are not allowed (MMCHS_PSTATE[BRE] =0) -This bit.." "BADA_0_r,BADA_1_r" bitfld.long 0x30 28. "CERR,Card error This bit is set automatically when there is at least one error in a response of type R1 R1b R6 R5 or R5b" "CERR_0_r,CERR_1_r" newline rbitfld.long 0x30 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x30 24. "ACE,Auto CMD error Auto CMD12 uses this error status" "ACE_0_r,ACE_1_r" rbitfld.long 0x30 23. "RESERVED," "0,1" newline bitfld.long 0x30 22. "DEB,Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode" "DEB_0_r,DEB_1_r" bitfld.long 0x30 21. "DCRC,Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command" "DCRC_0_r,DCRC_1_r" bitfld.long 0x30 20. "DTO,Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout" "DTO_0_r,DTO_1_r" newline bitfld.long 0x30 19. "CIE,Command index error This bit is set automatically when response index differs from corresponding command index previously emitted" "CIE_0_r,CIE_1_r" bitfld.long 0x30 18. "CEB,Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response" "CEB_0_r,CEB_1_r" bitfld.long 0x30 17. "CCRC,Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCHS_CMD[CCCE] register" "CCRC_0_r,CCRC_1_r" newline bitfld.long 0x30 16. "CTO,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command" "CTO_0_r,CTO_1_r" rbitfld.long 0x30 15. "ERRI,Error Interrupt If any of the bits in the Error Interrupt Status register (MMCHS_STAT[31:16]) are set then this bit is set to 1" "ERRI_0_r,ERRI_1_r" rbitfld.long 0x30 9.--14. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x30 8. "CIRQ,Card interrupt This bit is only used for SD and SDIO cards" "CIRQ_0_r,CIRQ_1_r" rbitfld.long 0x30 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x30 5. "BRR,Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by MMCHS_BLK[BLEN] is completely written in the buffer" "BRR_0_r,BRR_1_r" newline bitfld.long 0x30 4. "BWR,Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCHS_BLK[BLEN]" "BWR_0_r,BWR_1_r" rbitfld.long 0x30 3. "RESERVED," "0,1" bitfld.long 0x30 2. "BGE,Block gap event When a stop at block gap is requested (MMCHS_HCTL[SBGR]) this bit is automatically set when transaction is stopped at the block gap during a read or write operation" "BGE_0_r,BGE_1_r" newline bitfld.long 0x30 1. "TC,Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCHS_HCTL[SBGR])" "TC_0_r,TC_1_r" bitfld.long 0x30 0. "CC,Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCHS_PSTATE[CMDI]) If the command is a type for which no response is expected then the command complete interrupt is generated at the end of the command" "CC_0_r,CC_1_r" line.long 0x34 "MMCHS_IE,Interrupt Status Enable Register This register allows to enable/disable the module to set status bits. on an event-by-event basis" rbitfld.long 0x34 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x34 29. "BADA_ENABLE,Bad access to data space Status Enable" "BADA_ENABLE_0,BADA_ENABLE_1" bitfld.long 0x34 28. "CERR_ENABLE,Card Error Status Enable" "CERR_ENABLE_0,CERR_ENABLE_1" newline rbitfld.long 0x34 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x34 24. "ACE_ENABLE,Auto CMD Error Status Enable" "ACE_ENABLE_0,ACE_ENABLE_1" rbitfld.long 0x34 23. "RESERVED," "0,1" newline bitfld.long 0x34 22. "DEB_ENABLE,Data End Bit Error Status Enable" "DEB_ENABLE_0,DEB_ENABLE_1" bitfld.long 0x34 21. "DCRC_ENABLE,Data CRC Error Status Enable" "DCRC_ENABLE_0,DCRC_ENABLE_1" bitfld.long 0x34 20. "DTO_ENABLE,Data Timeout Error Status Enable" "DTO_ENABLE_0,DTO_ENABLE_1" newline bitfld.long 0x34 19. "CIE_ENABLE,Command Index Error Status Enable" "CIE_ENABLE_0,CIE_ENABLE_1" bitfld.long 0x34 18. "CEB_ENABLE,Command End Bit Error Status Enable" "CEB_ENABLE_0,CEB_ENABLE_1" bitfld.long 0x34 17. "CCRC_ENABLE,Command CRC Error Status Enable" "CCRC_ENABLE_0,CCRC_ENABLE_1" newline bitfld.long 0x34 16. "CTO_ENABLE,Command Timeout Error Status Enable" "CTO_ENABLE_0,CTO_ENABLE_1" rbitfld.long 0x34 15. "NULL,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register" "0,1" rbitfld.long 0x34 9.--14. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x34 8. "CIRQ_ENABLE,Card Status Enable A clear of this bit also clears the corresponding status bit" "CIRQ_ENABLE_0,CIRQ_ENABLE_1" rbitfld.long 0x34 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x34 5. "BRR_ENABLE,Buffer Read Ready Status Enable" "BRR_ENABLE_0,BRR_ENABLE_1" newline bitfld.long 0x34 4. "BWR_ENABLE,Buffer Write Ready Status Enable" "BWR_ENABLE_0,BWR_ENABLE_1" rbitfld.long 0x34 3. "RESERVED," "0,1" bitfld.long 0x34 2. "BGE_ENABLE,Block Gap Event Status Enable" "BGE_ENABLE_0,BGE_ENABLE_1" newline bitfld.long 0x34 1. "TC_ENABLE,Transfer Complete Status Enable" "TC_ENABLE_0,TC_ENABLE_1" bitfld.long 0x34 0. "CC_ENABLE,Command Complete Status Enable" "CC_ENABLE_0,CC_ENABLE_1" line.long 0x38 "MMCHS_ISE,Interrupt Signal Enable Register This register allows to enable/disable the module internal sources of status. on an event-by-event basis" rbitfld.long 0x38 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x38 29. "BADA_SIGEN,Bad access to data space Signal Enable" "BADA_SIGEN_0,BADA_SIGEN_1" bitfld.long 0x38 28. "CERR_SIGEN,Card Error Interrupt Signal Enable" "CERR_SIGEN_0,CERR_SIGEN_1" newline rbitfld.long 0x38 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x38 24. "ACE_SIGEN,Auto CMD Error Signal Enable" "ACE_SIGEN_0,ACE_SIGEN_1" rbitfld.long 0x38 23. "RESERVED," "0,1" newline bitfld.long 0x38 22. "DEB_SIGEN,Data End Bit Error Signal Enable" "DEB_SIGEN_0,DEB_SIGEN_1" bitfld.long 0x38 21. "DCRC_SIGEN,Data CRC Error Signal Enable" "DCRC_SIGEN_0,DCRC_SIGEN_1" bitfld.long 0x38 20. "DTO_SIGEN,Data Timeout Error Signal Enable" "DTO_SIGEN_0,DTO_SIGEN_1" newline bitfld.long 0x38 19. "CIE_SIGEN,Command Index Error Signal Enable" "CIE_SIGEN_0,CIE_SIGEN_1" bitfld.long 0x38 18. "CEB_SIGEN,Command End Bit Error Signal Enable" "CEB_SIGEN_0,CEB_SIGEN_1" bitfld.long 0x38 17. "CCRC_SIGEN,Command CRC Error Signal Enable" "CCRC_SIGEN_0,CCRC_SIGEN_1" newline bitfld.long 0x38 16. "CTO_SIGEN,Command timeout Error Signal Enable" "CTO_SIGEN_0,CTO_SIGEN_1" rbitfld.long 0x38 15. "NULL,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register" "0,1" rbitfld.long 0x38 9.--14. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x38 8. "CIRQ_SIGEN,Card Interrupt Signal Enable" "CIRQ_SIGEN_0,CIRQ_SIGEN_1" rbitfld.long 0x38 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x38 5. "BRR_SIGEN,Buffer Read Ready Signal Enable" "BRR_SIGEN_0,BRR_SIGEN_1" newline bitfld.long 0x38 4. "BWR_SIGEN,Buffer Write Ready Signal Enable" "BWR_SIGEN_0,BWR_SIGEN_1" rbitfld.long 0x38 3. "RESERVED," "0,1" bitfld.long 0x38 2. "BGE_SIGEN,Black Gap Event Signal Enable" "BGE_SIGEN_0,BGE_SIGEN_1" newline bitfld.long 0x38 1. "TC_SIGEN,Transfer Completed Status Enable" "TC_SIGEN_0,TC_SIGEN_1" bitfld.long 0x38 0. "CC_SIGEN,Command Complete Status Enable" "CC_SIGEN_0,CC_SIGEN_1" line.long 0x3C "MMCHS_AC12,Host Control 2 Register and Auto CMD Error Status Register This register is used to indicate CMD12 response error of Auto CMD12" bitfld.long 0x3C 31. "PV_ENABLE,Preset Value Enable Host Controller Version 3.00 supports this bit" "PV_ENABLE_0,PV_ENABLE_1" bitfld.long 0x3C 30. "AI_ENABLE,Asynchronous Interrupt Enable This bit can be set to 1 if a card supports asynchronous interrupts and MMCHS_CAPA[29] AIS is set to 1" "AI_ENABLE_0,AI_ENABLE_1" hexmask.long.byte 0x3C 22.--29. 1. "RESERVED," newline bitfld.long 0x3C 20.--21. "DS_SEL,Driver Strength Select Host Controller output driver in 1.8V signaling is selected by this bit" "DS_SEL_0,DS_SEL_1,DS_SEL_2,DS_SEL_3" bitfld.long 0x3C 19. "V1V8_SIGEN,1.8V Signaling Enable This bit controls voltage regulator for I/O cell" "V1V8_SIGEN_0,V1V8_SIGEN_1" bitfld.long 0x3C 16.--18. "UHSMS,UHS Mode Select This field is used to select one of UHS-I modes and effective when 1.8V Signaling Enable is set to 1" "UHSMS_0,UHSMS_1,?,?,?,?,?,?" newline hexmask.long.byte 0x3C 8.--15. 1. "RESERVED," rbitfld.long 0x3C 7. "CNI,Command Not Issued By Auto CMD12 Error Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register" "CNI_0_r,CNI_1_r" rbitfld.long 0x3C 5.--6. "RESERVED," "0,1,2,3" newline rbitfld.long 0x3C 4. "ACIE,Auto CMD Index Error for Auto CMD12 This bit is set if the Command Index error occurs in response to a command" "ACIE_0_r,ACIE_1_r" rbitfld.long 0x3C 3. "ACEB,Auto CMD End Bit Error for Auto CMD12 This bit is set when detecting that the end bit of command response is 0" "ACEB_0_r,ACEB_1_r" rbitfld.long 0x3C 2. "ACCE,Auto CMD CRC Error for Auto CMD12 This bit is set when detecting a CRC error in the command response" "ACCE_0_r,ACCE_1_r" newline rbitfld.long 0x3C 1. "ACTO,Auto CMD Timeout Error for Auto CMD12 This bit is set if no response is returned within 64 SDCLK cycles from the end bit of command" "ACTO_0_r,ACTO_1_r" rbitfld.long 0x3C 0. "ACNE,Auto CMD12 Not Executed If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12" "ACNE_0_r,ACNE_1_r" line.long 0x40 "MMCHS_CAPA,Capabilities Register This register lists the capabilities of the SDIO host controller" rbitfld.long 0x40 30.--31. "RESERVED," "0,1,2,3" rbitfld.long 0x40 29. "AIS,Asynchronous Interrupt Support Refer to SDIO Specification Version 3.00 about asynchronous interrupt" "AIS_0_r,AIS_1_r" rbitfld.long 0x40 28. "BIT64,64 Bit System Bus Support Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus" "BIT64_0_r,BIT64_1_r" newline rbitfld.long 0x40 27. "RESERVED," "0,1" bitfld.long 0x40 26. "VS18,Voltage support 1.8V Initialization of this register (via a write access to this register) depends on the system capabilities" "VS18_0_r,VS18_1_r" bitfld.long 0x40 25. "VS30,Voltage support 3.0V Initialization of this register (via a write access to this register) depends on the system capabilities" "VS30_0_r,VS30_1_r" newline bitfld.long 0x40 24. "VS33,Voltage support 3.3V Initialization of this register (via a write access to this register) depends on the system capabilities" "VS33_0_r,VS33_1_r" rbitfld.long 0x40 23. "SRS,Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports Suspend/Resume functionality" "SRS_0_r,SRS_1_r" rbitfld.long 0x40 22. "DS,DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly" "DS_0_r,DS_1_r" newline rbitfld.long 0x40 21. "HSS,High speed support This bit indicates that the host controller supports high speed operations and can supply an up-to maximum card frequency" "HSS_0_r,HSS_1_r" rbitfld.long 0x40 20. "RESERVED," "0,1" rbitfld.long 0x40 19. "AD2S,ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2" "AD2S_0_r,AD2S_1_r" newline rbitfld.long 0x40 18. "RESERVED," "0,1" rbitfld.long 0x40 16.--17. "MBL,Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller" "MBL_0_r,MBL_1_r,MBL_2_r,?" abitfld.long 0x40 8.--15. "BCF,Base Clock Frequency For SD Clock This value indicates the base (maximum) clock frequency for the SD Clock" "0x00=Get information via..,0x01=1MHz,0x02=2MHz,0xFF=255MHz" newline rbitfld.long 0x40 7. "TCU,Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCHS_STAT[DTO])" "TCU_0_r,TCU_1_r" rbitfld.long 0x40 6. "RESERVED," "0,1" rbitfld.long 0x40 0.--5. "TCF,Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (MMCHS_STAT[DTO])" "TCF_0_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x44 "MMCHS_CAPA2,Capabilities 2 Register This register provides the Host Driver with information specific to the Host Controller implementation" hexmask.long.byte 0x44 24.--31. 1. "RESERVED," abitfld.long 0x44 16.--23. "CM,Clock Multiplier This field indicates clock multiplier value of programmable clock generator" "0x00=Clock Multiplier is Not Supported,0x01=Clock Multiplier M = 2,0x02=Clock Multiplier M = 3,0xFF=Clock Multiplier M = 256" bitfld.long 0x44 14.--15. "RTM,Re-Tuning Modes This field selects re-tuning method and limits the maximum data length" "RTM_0_r,RTM_1_r,RTM_2_r,RTM_3_r" newline bitfld.long 0x44 13. "TSDR50,Use Tuning for SDR50 If this bit is set to 1 this Host Controller requires tuning to operate SDR50" "TSDR50_0_r,TSDR50_1_r" bitfld.long 0x44 12. "RESERVED," "0,1" bitfld.long 0x44 8.--11. "TCRT,Timer Count for Re-Tuning This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3" "TCRT_0_r,TCRT_1_r,TCRT_2_r,TCRT_3_r,TCRT_4_r,TCRT_5_r,TCRT_6_r,TCRT_7_r,TCRT_8_r,TCRT_9_r,TCRT_10_r,TCRT_11_r,TCRT_12_r,TCRT_13_r,TCRT_14_r,TCRT_15_r" newline bitfld.long 0x44 7. "RESERVED," "0,1" bitfld.long 0x44 6. "DTD,Driver Type D Support This bit indicates support of Driver Type D for 1.8 Signaling" "DTD_0_r,DTD_1_r" bitfld.long 0x44 5. "DTC,Driver Type C Support This bit indicates support of Driver Type C for 1.8 Signaling" "DTC_0_r,DTC_1_r" newline bitfld.long 0x44 4. "DTA,Driver Type A Support This bit indicates support of Driver Type A for 1.8 Signaling" "DTA_0_r,DTA_1_r" bitfld.long 0x44 3. "RESERVED," "0,1" bitfld.long 0x44 2. "DDR50,DDR50 Support" "DDR50_0_r,DDR50_1_r" newline bitfld.long 0x44 1. "SDR104,SDR104 Support" "SDR104_0_r,SDR104_1_r" bitfld.long 0x44 0. "SDR50,SDR50 Support If SDR104 is supported this bit shall be set to 1" "SDR50_0_r,SDR50_1_r" line.long 0x48 "MMCHS_CUR_CAPA,Maximum Current Capabilities Register This register indicates the maximum current capability for each voltage" hexmask.long.byte 0x48 24.--31. 1. "RESERVED," hexmask.long.byte 0x48 16.--23. 1. "CUR_1V8,Maximum current for 1.8V" hexmask.long.byte 0x48 8.--15. 1. "CUR_3V0,Maximum current for 3.0V" newline hexmask.long.byte 0x48 0.--7. 1. "CUR_3V3,Maximum current for 3.3V" group.long 0x250++0x03 line.long 0x00 "MMCHS_FE,Force Event Register for Auto CMD Error Status and Error Interrupt status The Force Event Register is not a physically implemented register" bitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x00 29. "FE_BADA,Force Event Bad access to data space" "FE_BADA_0_w,FE_BADA_1_w" bitfld.long 0x00 28. "FE_CERR,Force Event Card error" "FE_CERR_0_w,FE_CERR_1_w" newline bitfld.long 0x00 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 24. "FE_ACE,Force Event for Auto CMD Error - For Auto CMD12" "FE_ACE_0_w,FE_ACE_1_w" bitfld.long 0x00 23. "RESERVED," "0,1" newline bitfld.long 0x00 22. "FE_DEB,Force Event Data End Bit error" "FE_DEB_0_w,FE_DEB_1_w" bitfld.long 0x00 21. "FE_DCRC,Force Event Data CRC Error" "FE_DCRC_0_w,FE_DCRC_1_w" bitfld.long 0x00 20. "FE_DTO,Force Event Data Timeout Error" "FE_DTO_0_w,FE_DTO_1_w" newline bitfld.long 0x00 19. "FE_CIE,Force Event Command Index Error" "FE_CIE_0_w,FE_CIE_1_w" bitfld.long 0x00 18. "FE_CEB,Force Event Command End Bit Error" "FE_CEB_0_w,FE_CEB_1_w" bitfld.long 0x00 17. "FE_CCRC,Force Event Command CRC Error" "FE_CCRC_0_w,FE_CCRC_1_w" newline bitfld.long 0x00 16. "FE_CTO,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command" "FE_CTO_0_w,FE_CTO_1_w" hexmask.long.byte 0x00 8.--15. 1. "RESERVED," bitfld.long 0x00 7. "FE_CNI,Force Event Command not issued by Auto CMD12 error" "FE_CNI_0_w,FE_CNI_1_w" newline bitfld.long 0x00 5.--6. "RESERVED," "0,1,2,3" bitfld.long 0x00 4. "FE_ACIE,Force Event for Auto CMD Index Error - For Auto CMD12" "FE_ACIE_0_w,FE_ACIE_1_w" bitfld.long 0x00 3. "FE_ACEB,Force Event Auto CMD End Bit Error" "FE_ACEB_0_w,FE_ACEB_1_w" newline bitfld.long 0x00 2. "FE_ACCE,Force Event Auto CMD CRC Error" "FE_ACCE_0_w,FE_ACCE_1_w" bitfld.long 0x00 1. "FE_ACTO,Force Event Auto CMD Timeout Error" "FE_ACTO_0_w,FE_ACTO_1_w" bitfld.long 0x00 0. "FE_ACNE,Force Event Auto CMD12 Not Executed" "FE_ACNE_0_w,FE_ACNE_1_w" rgroup.long 0x260++0x0B line.long 0x00 "MMCHS_PVINITSD,Preset Value for Initialization and Default Speed modes" bitfld.long 0x00 30.--31. "DSDS_SEL,Driver Strength Select Value - Default Speed mode Driver Strength is supported by 1.8V signaling bus speed modes" "DSDS_SEL_0_r,DSDS_SEL_1_r,DSDS_SEL_2_r,DSDS_SEL_3_r" bitfld.long 0x00 27.--29. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 26. "DSCLKGEN_SEL,Clock Generator Select Value - Default Speed mode This bit is effective when Host Controller supports programmable clock generator" "DSCLKGEN_SEL_0_r,DSCLKGEN_SEL_1_r" newline hexmask.long.word 0x00 16.--25. 1. "DSSDCLK_SEL,SDCLK Frequency Select Value - Default Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" bitfld.long 0x00 14.--15. "INITDS_SEL,Driver Strength Select Value - Initialization mode Driver Strength is supported by 1.8V signaling bus speed modes" "INITDS_SEL_0_r,INITDS_SEL_1_r,INITDS_SEL_2_r,INITDS_SEL_3_r" bitfld.long 0x00 11.--13. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10. "INITCLKGEN_SEL,Clock Generator Select Value - Initialization mode This bit is effective when Host Controller supports programmable clock generator" "INITCLKGEN_SEL_0_r,INITCLKGEN_SEL_1_r" hexmask.long.word 0x00 0.--9. 1. "INITSDCLK_SEL,SDCLK Frequency Select Value - Initialization mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" line.long 0x04 "MMCHS_PVHSSDR12,Preset Value for High Speed and SDR12 speed modes" bitfld.long 0x04 30.--31. "SDR12DS_SEL,Driver Strength Select Value - SDR12 mode Driver Strength is supported by 1.8V signaling bus speed modes" "SDR12DS_SEL_0_r,SDR12DS_SEL_1_r,SDR12DS_SEL_2_r,SDR12DS_SEL_3_r" bitfld.long 0x04 27.--29. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 26. "SDR12CLKGEN_SEL,Clock Generator Select Value - SDR12 mode This bit is effective when Host Controller supports programmable clock generator" "SDR12CLKGEN_SEL_0_r,SDR12CLKGEN_SEL_1_r" newline hexmask.long.word 0x04 16.--25. 1. "SDR12SDCLK_SEL,SDCLK Frequency Select Value - SDR12 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" bitfld.long 0x04 14.--15. "HSDS_SEL,Driver Strength Select Value - High Speed mode Driver Strength is supported by 1.8V signaling bus speed modes" "HSDS_SEL_0_r,HSDS_SEL_1_r,HSDS_SEL_2_r,HSDS_SEL_3_r" bitfld.long 0x04 11.--13. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 10. "HSCLKGEN_SEL,Clock Generator Select Value - High Speed mode This bit is effective when Host Controller supports programmable clock generator" "HSCLKGEN_SEL_0_r,HSCLKGEN_SEL_1_r" hexmask.long.word 0x04 0.--9. 1. "HSSDCLK_SEL,SDCLK Frequency Select Value - High Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" line.long 0x08 "MMCHS_PVSDR25SDR50,Preset Value for SDR25 speed mode" hexmask.long.word 0x08 16.--31. 1. "RESERVED," bitfld.long 0x08 14.--15. "SDR25DS_SEL,Driver Strength Select Value - SDR25 mode Driver Strength is supported by 1.8V signaling bus speed modes" "SDR25DS_SEL_0_r,SDR25DS_SEL_1_r,SDR25DS_SEL_2_r,SDR25DS_SEL_3_r" bitfld.long 0x08 11.--13. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 10. "SDR25CLKGEN_SEL,Clock Generator Select Value - SDR25 mode This bit is effective when Host Controller supports programmable clock generator" "SDR25CLKGEN_SEL_0_r,SDR25CLKGEN_SEL_1_r" hexmask.long.word 0x08 0.--9. 1. "SDR25SDCLK_SEL,SDCLK Frequency Select Value - SDR25 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" rgroup.long 0x2FC++0x03 line.long 0x00 "MMCHS_REV,Versions Register This register contains the hard coded RTL vendor revision number. the version number of SD specification compliancy and a slot status bit" hexmask.long.byte 0x00 24.--31. 1. "VREV,Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" hexmask.long.byte 0x00 16.--23. 1. "SREV,Specification Version Number This status indicates the Host Controller Spec" hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "SIS,Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module" "0,1" width 0x0B tree.end tree "MMC_TARG" base ad:0x480D2000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MMU_TARG" base ad:0x44002200 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "MMU_TARG" base ad:0x4881D000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MPU_CM_CORE_AON" base ad:0x4A005300 group.long 0x00++0x0B line.long 0x00 "CM_MPU_CLKSTCTRL,This register enables the MPU domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_MPU_GCLK,This field indicates the state of the MPU_DPLL_CLK clock in the domain" "CLKACTIVITY_MPU_GCLK_0,CLKACTIVITY_MPU_GCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the MPU clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_MPU_STATICDEP,This register controls the static domain depedencies from MPU domain towards 'target' domains" rbitfld.long 0x04 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE clock domain" "PCIE_STATDEP_0,PCIE_STATDEP_1" newline bitfld.long 0x04 28. "ISS_STATDEP,Static dependency towards ISS clock domain" "ISS_STATDEP_0,ISS_STATDEP_1" bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain" "GMAC_STATDEP_0,GMAC_STATDEP_1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain" "IPU_STATDEP_0,IPU_STATDEP_1" bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain" "EVE2_STATDEP_0,EVE2_STATDEP_1" bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain" "EVE1_STATDEP_0,EVE1_STATDEP_1" newline bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain" "DSP2_STATDEP_0,DSP2_STATDEP_1" rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain" "CUSTEFUSE_STATDEP_0,?" newline rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain" "COREAON_STATDEP_0,?" bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" rbitfld.long 0x04 11. "SDMA_STATDEP,Static dependency towards SDMA clock domain" "SDMA_STATDEP_0,?" newline bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU clock domain" "GPU_STATDEP_0,GPU_STATDEP_1" bitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain" "CAM_STATDEP_0,CAM_STATDEP_1" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain" "DSS_STATDEP_0,DSS_STATDEP_1" bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline rbitfld.long 0x04 6. "RESERVED," "0,1" bitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN clock domain" "L3MAIN1_STATDEP_0,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP1 clock domain" "DSP1_STATDEP_0,DSP1_STATDEP_1" newline bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_MPU_DYNAMICDEP,This register controls the dynamic domain depedencies from MPU domain towards 'target' domains" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.tbyte 0x08 6.--23. 1. "RESERVED," rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x08 4. "EMIF_DYNDEP,Dynamic dependency towards EMIF clock domain" "?,EMIF_DYNDEP_1" rbitfld.long 0x08 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x03 line.long 0x00 "CM_MPU_MPU_CLKCTRL,This register manages the MPU clocks" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 26. "CLKSEL_ABE_DIV_MODE,Selects the ratio for MPU - ABE async bridge versus MPU DPLL clock" "CLKSEL_ABE_DIV_MODE_0,CLKSEL_ABE_DIV_MODE_1" newline bitfld.long 0x00 24.--25. "CLKSEL_EMIF_DIV_MODE,Selects the ratio for MPU - L3 async bridge versus MPU DPLL clock" "CLKSEL_EMIF_DIV_MODE_0,CLKSEL_EMIF_DIV_MODE_1,CLKSEL_EMIF_DIV_MODE_2,CLKSEL_EMIF_DIV_MODE_3" rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," rbitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x28++0x03 line.long 0x00 "CM_MPU_MPU_MPU_DBG_CLKCTRL,This register manages the MPU_MPU_DBG clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" width 0x0B tree.end tree "MPU_PRM" base ad:0x4AE06300 group.long 0x00++0x07 line.long 0x00 "PM_MPU_PWRSTCTRL,This register controls the MPU domain power state to reach upon a domain sleep transition" hexmask.long.word 0x00 22.--31. 1. "RESERVED," rbitfld.long 0x00 20.--21. "MPU_RAM_ONSTATE,MPU_RAM memory state when domain is ON" "?,?,?,MPU_RAM_ONSTATE_3" rbitfld.long 0x00 18.--19. "MPU_L2_ONSTATE,MPU_L2 memory state when domain is ON" "?,?,?,MPU_L2_ONSTATE_3" newline hexmask.long.byte 0x00 11.--17. 1. "RESERVED," rbitfld.long 0x00 10. "MPU_RAM_RETSTATE,MPU_RAM memory state when domain is RETENTION" "?,MPU_RAM_RETSTATE_1" bitfld.long 0x00 9. "MPU_L2_RETSTATE,MPU_L2 memory state when domain is RETENTION" "MPU_L2_RETSTATE_0,MPU_L2_RETSTATE_1" newline rbitfld.long 0x00 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,?" rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION" "LOGICRETSTATE_0,LOGICRETSTATE_1" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_MPU_PWRSTST,This register provides a status on the MPU domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" hexmask.long.word 0x04 10.--19. 1. "RESERVED," rbitfld.long 0x04 8.--9. "MPU_RAM_STATEST,MPU_RAM memory state status" "MPU_RAM_STATEST_0,MPU_RAM_STATEST_1,MPU_RAM_STATEST_2,MPU_RAM_STATEST_3" newline rbitfld.long 0x04 6.--7. "MPU_L2_STATEST,MPU_L2 memory state status" "MPU_L2_STATEST_0,MPU_L2_STATEST_1,MPU_L2_STATEST_2,MPU_L2_STATEST_3" rbitfld.long 0x04 3.--5. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_MPU_MPU_CONTEXT,This register contains dedicated MPU context statuses" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," bitfld.long 0x00 10. "LOSTMEM_MPU_RAM,Specify if memory-based context in MPU_RAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_MPU_RAM_0,LOSTMEM_MPU_RAM_1" bitfld.long 0x00 9. "LOSTMEM_MPU_L2,Specify if memory-based context in MPU_L2 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_MPU_L2_0,LOSTMEM_MPU_L2_1" newline hexmask.long.byte 0x00 2.--8. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "OCMC_RAM" base ad:0x48804000 rgroup.long 0x00++0x0F line.long 0x00 "OCMC_ECC_PID," line.long 0x04 "OCMC_SYSCONFIG_PM," hexmask.long 0x04 4.--31. 1. "RESERVED," newline bitfld.long 0x04 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" line.long 0x08 "OCMC_SYSCONFIG_RST," hexmask.long 0x08 1.--31. 1. "RESERVED," newline bitfld.long 0x08 0. "SW_RST,Software reset of the OCM controller configuration and history logic (does not reset L4 interface)" "SW_RST_0,SW_RST_1" line.long 0x0C "OCMC_MEM_SIZE_READ,This register provides the status of the OCM Controller configuration" hexmask.long.word 0x0C 17.--31. 1. "RESERVED," newline bitfld.long 0x0C 12.--16. "VBUF_ADDR_MSB,This bit field returns the MSB bit of the valid VBUF address range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 9. "MEM_CBUF_ENABLE,Indicates whether CBUF is supported or not" "MEM_CBUF_ENABLE_0,MEM_CBUF_ENABLE_1" newline bitfld.long 0x0C 8. "MEM_ECC_ENABLE,Indicates whether ECC is supported or not" "MEM_ECC_ENABLE_0,MEM_ECC_ENABLE_1" newline bitfld.long 0x0C 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 0.--4. "MEM_SIZE_128K_CNT,This bit field indicates how many 128KiB memory blocks are present in the SRAM" "?,One 128KiB memory block,Two 128KiB memory blocks,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,20 memory blocks of 128KiB,?..." group.long 0x40++0x13 line.long 0x00 "INTR0_STATUS_RAW_SET,This register contains the raw interrupt status" hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED," newline bitfld.long 0x00 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x00 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x00 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x00 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x00 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x00 0. "SEC_ERR_FOUND," "0,1" line.long 0x04 "INTR0_STATUS_ENABLED_CLEAR,Read indicates ENABLED interrupt status (0=inactive. 1=active)" hexmask.long.tbyte 0x04 15.--31. 1. "RESERVED," newline bitfld.long 0x04 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x04 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x04 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x04 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x04 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x04 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x04 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x04 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x04 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x04 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x04 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x04 0. "SEC_ERR_FOUND," "0,1" line.long 0x08 "INTR0_ENABLE_SET,Read indicates interrupt enable (0=disabled. 1=enabled) Writing 1 will set the corresponding interrupt enable bit" hexmask.long.tbyte 0x08 15.--31. 1. "RESERVED," newline bitfld.long 0x08 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x08 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x08 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x08 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x08 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x08 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x08 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x08 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x08 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x08 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x08 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x08 0. "SEC_ERR_FOUND," "0,1" line.long 0x0C "INTR0_ENABLE_CLEAR,Read indicates interrupt enable (0=disabled. 1=enabled) Writing 1 will clear interrupt enabled" hexmask.long.tbyte 0x0C 15.--31. 1. "RESERVED," newline bitfld.long 0x0C 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x0C 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x0C 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x0C 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x0C 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x0C 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x0C 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x0C 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x0C 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x0C 0. "SEC_ERR_FOUND," "0,1" line.long 0x10 "OCMC_INTR0_EOI,This register contains the EOI vector" hexmask.long 0x10 1.--31. 1. "RESERVED," newline bitfld.long 0x10 0. "EOI_VECTOR," "0,1" group.long 0x60++0x13 line.long 0x00 "INTR1_STATUS_RAW_SET,This register contains the raw interrupt status" hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED," newline bitfld.long 0x00 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x00 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x00 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x00 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x00 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x00 0. "SEC_ERR_FOUND," "0,1" line.long 0x04 "INTR1_STATUS_ENABLED_CLEAR,Read indicates ENABLED interrupt status (0=inactive. 1=active)" hexmask.long.tbyte 0x04 15.--31. 1. "RESERVED," newline bitfld.long 0x04 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x04 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x04 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x04 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x04 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x04 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x04 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x04 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x04 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x04 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x04 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x04 0. "SEC_ERR_FOUND," "0,1" line.long 0x08 "INTR1_ENABLE_SET,Read indicates interrupt enable (0=disabled. 1=enabled) Writing 1 will set the corresponding interrupt enable bit" hexmask.long.tbyte 0x08 15.--31. 1. "RESERVED," newline bitfld.long 0x08 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x08 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x08 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x08 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x08 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x08 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x08 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x08 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x08 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x08 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x08 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x08 0. "SEC_ERR_FOUND," "0,1" line.long 0x0C "INTR1_ENABLE_CLEAR,Read indicates interrupt enable (0=disabled. 1=enabled) Writing 1 will clear interrupt enabled" hexmask.long.tbyte 0x0C 15.--31. 1. "RESERVED," newline bitfld.long 0x0C 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x0C 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x0C 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x0C 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x0C 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x0C 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x0C 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x0C 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x0C 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x0C 0. "SEC_ERR_FOUND," "0,1" line.long 0x10 "OCMC_INTR1_EOI,This register contains the EOI vector" hexmask.long 0x10 1.--31. 1. "RESERVED," newline bitfld.long 0x10 0. "EOI_VECTOR," "0,1" group.long 0x80++0x33 line.long 0x00 "CFG_OCMC_ECC," hexmask.long 0x00 6.--31. 1. "RESERVED," newline bitfld.long 0x00 5. "CFG_ECC_OPT_NON_ECC_READ,Optimize read latency for non-ECC" "Disable,Enable" newline bitfld.long 0x00 4. "CFG_ECC_ERR_SRESP_EN,ECC non-correctable error SRESP enable" "Disable,Enable" newline bitfld.long 0x00 3. "CFG_ECC_SEC_AUTO_CORRECT,SEC error auto correction mode" "Disable,Enable (If the OCM.." newline bitfld.long 0x00 0.--2. "CFG_OCMC_MODE,OCM Controller memory access modes" "Non-ECC mode (data access),Non-ECC mode (code access),Full ECC enabled mode,Block ECC enabled mode 0x4-0x7,?..." line.long 0x04 "CFG_OCMC_ECC_MEM_BLK," hexmask.long.word 0x04 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x04 0.--19. 1. "CFG_ECC_ENABLED_128K_BLK,ECC memory block enable bits" line.long 0x08 "CFG_OCMC_ECC_ERROR," hexmask.long.byte 0x08 25.--31. 1. "RESERVED," newline bitfld.long 0x08 24. "CFG_DISCARD_DUP_ADDR,Do not save duplicate error address" "Save the duplicated addresses,Save only the unique addresses" newline bitfld.long 0x08 20.--23. "CFG_ADDR_ERR_CNT_MAX,Number of ADDR errors to trigger an interrupt (The value configured must be > 0 to generate an interrupt)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 16.--19. "CFG_DED_CNT_MAX,Number of DED errors to trigger an interrupt (The value configured must be > 0 to generate an interrupt)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 0.--15. 1. "CFG_SEC_CNT_MAX,Number of SEC error to trigger an interrupt (The value configured must be > 0 to generate an interrupt)" line.long 0x0C "CFG_OCMC_ECC_CLEAR_HIST," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 3. "CLEAR_SEC_BIT_DISTR,Clear stored single error correction (SEC) bit distribution history" "Reserved (not used),Cleares the following registers" newline bitfld.long 0x0C 2. "CLEAR_ADDR_ERR_CNT,Clear stored address error history" "Reserved (not used),Clears" newline bitfld.long 0x0C 1. "CLEAR_DED_ERR_CNT,Clear stored double error detection (DED) history" "Reserved (not used),Clears" newline bitfld.long 0x0C 0. "CLEAR_SEC_ERR_CNT,Clear stored single error correction history" "Reserved (not used),Clears" line.long 0x10 "STATUS_ERROR_CNT,OCM Controller error status" hexmask.long.byte 0x10 24.--31. 1. "RESERVED," newline bitfld.long 0x10 20.--23. "ADDR_ERROR_CNT,Counter for the address errors found" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 16.--19. "DED_ERROR_CNT,Counter for the double error detections" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x10 0.--15. 1. "SEC_ERROR_CNT,Counter for the single errors occured" line.long 0x14 "STATUS_SEC_ERROR_TRACE,SEC error 128-bit memory address" hexmask.long.word 0x14 19.--31. 1. "RESERVED," newline bitfld.long 0x14 18. "VALID,SEC FIFO valid addres indication" "VALID_0,VALID_1" newline hexmask.long.tbyte 0x14 0.--17. 1. "ADDRESS_128BIT,SEC error 128-bit memory address (Read from the SEC error address trace fifo)" line.long 0x18 "STATUS_DED_ERROR_TRACE,DED error 128-bit memory address" hexmask.long.word 0x18 19.--31. 1. "RESERVED," newline bitfld.long 0x18 18. "VALID,DED FIFO valid addres indication" "The DED FIFO is empty,There is a valid address in the DED FIFO" newline hexmask.long.tbyte 0x18 0.--17. 1. "ADDRESS_128BIT,DED error 128-bit memory address (Read from the DED error address trace fifo)" line.long 0x1C "STATUS_ADDR_TRANSLATION_ERROR_TRACE,ADDR error 128-bit memory address" hexmask.long.word 0x1C 19.--31. 1. "RESERVED," newline bitfld.long 0x1C 18. "VALID,ADDRERR FIFO valid addres indication" "The ADDRERR FIFO is empty,There is a valid address in the ADDRERR FIFO" newline hexmask.long.tbyte 0x1C 0.--17. 1. "ADDRESS_128BIT,ADDR error 128-bit memory address (Read from the ADDR error address trace fifo)" line.long 0x20 "STATUS_SEC_ERROR_DISTR_0,SEC data error bit distribution status [31:0]" line.long 0x24 "STATUS_SEC_ERROR_DISTR_1,SEC data error bit distribution status [63:32]" line.long 0x28 "STATUS_SEC_ERROR_DISTR_2,SEC data error bit distribution status [95:64]" line.long 0x2C "STATUS_SEC_ERROR_DISTR_3,SEC data error bit distribution status [127:96]" line.long 0x30 "STATUS_SEC_ERROR_DISTR_4,SEC ecc code error bit distribution status [7:0]" hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED," newline abitfld.long 0x30 0.--7. "SEC_ECC_CODE_ERROR_FOUND,ECC Code (excluding the parity bit) error distribution [7:0]" "0x00=SEC error not found,0x01=SEC error found In the corresponding bit.." group.long 0x200++0x33 line.long 0x00 "CFG_OCMC_CBUF_EN,CBUF mode enable register" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "CBUF_EN_11,CBUF 11 enable" "Disable,Enable" newline bitfld.long 0x00 26. "CBUF_EN_10,CBUF 10 enable" "Disable,Enable" newline bitfld.long 0x00 25. "CBUF_EN_9,CBUF 9 enable" "Disable,Enable" newline bitfld.long 0x00 24. "CBUF_EN_8,CBUF 8 enable" "Disable,Enable" newline bitfld.long 0x00 23. "CBUF_EN_7,CBUF 7 enable" "Disable,Enable" newline bitfld.long 0x00 22. "CBUF_EN_6,CBUF 6 enable" "Disable,Enable" newline bitfld.long 0x00 21. "CBUF_EN_5,CBUF 5 enable" "Disable,Enable" newline bitfld.long 0x00 20. "CBUF_EN_4,CBUF 4 enable" "Disable,Enable" newline bitfld.long 0x00 19. "CBUF_EN_3,CBUF 3 enable" "Disable,Enable" newline bitfld.long 0x00 18. "CBUF_EN_2,CBUF 2 enable" "Disable,Enable" newline bitfld.long 0x00 17. "CBUF_EN_1,CBUF 1 enable" "Disable,Enable" newline bitfld.long 0x00 16. "CBUF_EN_0,CBUF 0 enable" "Disable,Enable" newline hexmask.long.word 0x00 3.--15. 1. "RESERVED," newline bitfld.long 0x00 2. "NEW_FRAME_SEL,CBUF New Frame Event Definition Select" "New frame event flag is set when a VBUF access..,New frame event flag is set when a VBUF access.." newline bitfld.long 0x00 1. "CBUF_DEBUG_EN,CBUF Debug Enable Mode" "Default Normal mode,Debug mode" newline bitfld.long 0x00 0. "CBUF_MODE_EN,CBUF Mode Enable" "Disable all CBUF address translation,Enable CBUF address translation" line.long 0x04 "CFG_OCMC_CBUF_RESET,Writing 1 to bit n will set a reset bit to clear the corresponding CBUF_n address translation logic" hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED," newline bitfld.long 0x04 11. "CBUF_RESET_11,cbuf_reset_11" "0,1" newline bitfld.long 0x04 10. "CBUF_RESET_10,cbuf_reset_10" "0,1" newline bitfld.long 0x04 9. "CBUF_RESET_9,cbuf_reset_9" "0,1" newline bitfld.long 0x04 8. "CBUF_RESET_8,cbuf_reset_8" "0,1" newline bitfld.long 0x04 7. "CBUF_RESET_7,cbuf_reset_7" "0,1" newline bitfld.long 0x04 6. "CBUF_RESET_6,cbuf_reset_6" "0,1" newline bitfld.long 0x04 5. "CBUF_RESET_5,cbuf_reset_5" "0,1" newline bitfld.long 0x04 4. "CBUF_RESET_4,cbuf_reset_4" "0,1" newline bitfld.long 0x04 3. "CBUF_RESET_3,cbuf_reset_3" "0,1" newline bitfld.long 0x04 2. "CBUF_RESET_2,cbuf_reset_2" "0,1" newline bitfld.long 0x04 1. "CBUF_RESET_1,cbuf_reset_1" "0,1" newline bitfld.long 0x04 0. "CBUF_RESET_0,cbuf_reset_0" "0,1" line.long 0x08 "CFG_OCMC_CBUF_ERR_HANDLER," hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," newline bitfld.long 0x08 8. "UNDERFLOW_LAST_CBUF_SLICE_DISABLE," "0,1" newline bitfld.long 0x08 6.--7. "OVERFLOW_CHECK_REENABLE_SEL,Overflow check re-enable selection" "Overflow check is disabled until next wtire to..,Overflow check is disabled until next write to..,Overflow check is disabled until next read from..,Overflow check is re-enabled immediately" newline bitfld.long 0x08 4.--5. "OVERFLOW_WRITE_HANDLER_SEL,Overflow write handler selection" "Writes disabled only on CBUF_overflow_wrap cases..,Writes disabled on all overflow cases until next..,Writes serviced with CBUF pointer updated even..,Reserved" newline bitfld.long 0x08 3. "UNDERFLOW_ERR_CHECK_EN,Underflow chek enable" "UNDERFLOW_ERR_CHECK_EN_0,UNDERFLOW_ERR_CHECK_EN_1" newline bitfld.long 0x08 2. "OVERFLOW_ERR_CHECK_EN,Overflow chek enable" "OVERFLOW_ERR_CHECK_EN_0,OVERFLOW_ERR_CHECK_EN_1" newline bitfld.long 0x08 1. "SHORT_FRAME_PREV_EOF_SEL," "0,1" newline bitfld.long 0x08 0. "SHORT_FRAME_DETECT_CHECK_EN,Short frame detection enable" "SHORT_FRAME_DETECT_CHECK_EN_0,SHORT_FRAME_DETECT_CHECK_EN_1" line.long 0x0C "STATUS_CBUF_WR_OUT_OF_RANGE_ERR," hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--11. 1. "CBUF_ERR,Indicates that the CBUF write address is out of the CBUF range" line.long 0x10 "STATUS_CBUF_WR_VBUF_START_ERR," hexmask.long.tbyte 0x10 12.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--11. 1. "CBUF_ERR,CBUF write is not to the base address at vbuf access start" line.long 0x14 "STATUS_CBUF_WR_ADDR_SEQ_ERROR," hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED," newline hexmask.long.word 0x14 0.--11. 1. "CBUF_ERR,CBUF address is not incrementing in raster scan order" line.long 0x18 "STATUS_CBUF_RD_OUT_OF_RANGE_ERROR," hexmask.long.tbyte 0x18 12.--31. 1. "RESERVED," newline hexmask.long.word 0x18 0.--11. 1. "CBUF_ERR,Indicates that the CBUF read address is out of the CBUF range" line.long 0x1C "STATUS_CBUF_VBUF_RD_START_ERROR," hexmask.long.tbyte 0x1C 12.--31. 1. "RESERVED," newline hexmask.long.word 0x1C 0.--11. 1. "CBUF_ERR,CBUF read is not from the base address at VBUF access start" line.long 0x20 "STATUS_CBUF_RD_ADDR_SEQ_ERROR," hexmask.long.tbyte 0x20 12.--31. 1. "RESERVED," newline hexmask.long.word 0x20 0.--11. 1. "CBUF_ERR,CBUF read address is not incrementing in raster scan order" line.long 0x24 "STATUS_CBUF_OVERFLOW_MID," hexmask.long.tbyte 0x24 12.--31. 1. "RESERVED," newline hexmask.long.word 0x24 0.--11. 1. "CBUF_ERR,CBUF overflow condition detected in the middle of a frame" line.long 0x28 "STATUS_CBUF_OVERFLOW_WRAP," hexmask.long.tbyte 0x28 12.--31. 1. "RESERVED," newline hexmask.long.word 0x28 0.--11. 1. "CBUF_ERR,CBUF overflow condition detected during buffer switching" line.long 0x2C "STATUS_CBUF_UNDERFLOW," hexmask.long.tbyte 0x2C 12.--31. 1. "RESERVED," newline hexmask.long.word 0x2C 0.--11. 1. "CBUF_ERR,CBUF underflow condition detected" line.long 0x30 "STATUS_CBUF_SHORT_FRAME_DETECT," hexmask.long.tbyte 0x30 12.--31. 1. "RESERVED," newline hexmask.long.word 0x30 0.--11. 1. "CBUF_ERR,CBUF short frame detected" group.long 0x240++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_0," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x256++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_1," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x26C++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_2," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x282++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_3," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x298++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_4," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2AE++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_5," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2C4++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_6," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2DA++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_7," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2F0++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_8," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x306++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_9," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x31C++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_10," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x332++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_11," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x244++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_0," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x25A++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_1," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x270++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_2," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x286++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_3," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x29C++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_4," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2B2++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_5," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2C8++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_6," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2DE++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_7," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2F4++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_8," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30A++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_9," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x320++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_10," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x336++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_11," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x248++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_0," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x25E++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_1," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x274++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_2," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x28A++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_3," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2A0++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_4," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2B6++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_5," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2CC++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_6," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2E2++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_7," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2F8++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_8," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30E++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_9," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x324++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_10," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x33A++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_11," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x24C++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_0," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x262++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_1," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x278++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_2," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x28E++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_3," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2A4++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_4," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2BA++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_5," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2D0++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_6," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2E6++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_7," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2FC++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_8," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x312++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_9," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x328++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_10," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x33E++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_11," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x300++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_0," rgroup.long 0x308++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_1," rgroup.long 0x310++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_2," rgroup.long 0x318++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_3," rgroup.long 0x320++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_4," rgroup.long 0x328++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_5," rgroup.long 0x330++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_6," rgroup.long 0x338++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_7," rgroup.long 0x340++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_8," rgroup.long 0x348++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_9," rgroup.long 0x350++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_10," rgroup.long 0x358++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_11," rgroup.long 0x304++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_0," rgroup.long 0x30C++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_1," rgroup.long 0x314++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_2," rgroup.long 0x31C++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_3," rgroup.long 0x324++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_4," rgroup.long 0x32C++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_5," rgroup.long 0x334++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_6," rgroup.long 0x33C++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_7," rgroup.long 0x344++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_8," rgroup.long 0x34C++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_9," rgroup.long 0x354++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_10," rgroup.long 0x35C++0x07 line.long 0x00 "CBUF_k_LAST_RD_ADDR_11," line.long 0x04 "LAST_ILLEGAL_OCMC_ADDR," width 0x0B tree.end tree "OCMC_RAM_CFG_TARG" base ad:0x48805000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "OCMC_RAM_FW" base ad:0x4A212000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" newline rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x100++0x03 line.long 0x00 "START_REGION_i_8,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x110++0x03 line.long 0x00 "START_REGION_i_9,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x120++0x03 line.long 0x00 "START_REGION_i_10,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x130++0x03 line.long 0x00 "START_REGION_i_11,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x140++0x03 line.long 0x00 "START_REGION_i_12,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x150++0x03 line.long 0x00 "START_REGION_i_13,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x160++0x03 line.long 0x00 "START_REGION_i_14,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x170++0x03 line.long 0x00 "START_REGION_i_15,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x180++0x03 line.long 0x00 "START_REGION_i_16,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x190++0x03 line.long 0x00 "START_REGION_i_17,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1A0++0x03 line.long 0x00 "START_REGION_i_18,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1B0++0x03 line.long 0x00 "START_REGION_i_19,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1C0++0x03 line.long 0x00 "START_REGION_i_20,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1D0++0x03 line.long 0x00 "START_REGION_i_21,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1E0++0x03 line.long 0x00 "START_REGION_i_22,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1F0++0x03 line.long 0x00 "START_REGION_i_23,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x104++0x03 line.long 0x00 "END_REGION_i_8,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x114++0x03 line.long 0x00 "END_REGION_i_9,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x124++0x03 line.long 0x00 "END_REGION_i_10,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x134++0x03 line.long 0x00 "END_REGION_i_11,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x144++0x03 line.long 0x00 "END_REGION_i_12,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x154++0x03 line.long 0x00 "END_REGION_i_13,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x164++0x03 line.long 0x00 "END_REGION_i_14,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x174++0x03 line.long 0x00 "END_REGION_i_15,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x184++0x03 line.long 0x00 "END_REGION_i_16,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x194++0x03 line.long 0x00 "END_REGION_i_17,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1A4++0x03 line.long 0x00 "END_REGION_i_18,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1B4++0x03 line.long 0x00 "END_REGION_i_19,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1C4++0x03 line.long 0x00 "END_REGION_i_20,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1D4++0x03 line.long 0x00 "END_REGION_i_21,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1E4++0x03 line.long 0x00 "END_REGION_i_22,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1F4++0x03 line.long 0x00 "END_REGION_i_23,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x108++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_8,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x118++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_9,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x128++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_10,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x138++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_11,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x148++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_12,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x158++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_13,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x168++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_14,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x178++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_15,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x188++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_16,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x198++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_17,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1A8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_18,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1B8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_19,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_20,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1D8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_21,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_22,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1F8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_23,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x10C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_8,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x11C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_9,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x12C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_10,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x13C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_11,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x14C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_12,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x15C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_13,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x16C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_14,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x17C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_15,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x18C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_16,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x19C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_17,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1AC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_18,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1BC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_19,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1CC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_20,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1DC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_21,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1EC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_22,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1FC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_23,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "OCMC_RAM_FW_CFG_TARG" base ad:0x4A213000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "OCMC_RAM_TARG" base ad:0x44000F00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "OCP_SOCKET_CM_CORE" base ad:0x4A008000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION_CM_CORE,This register contains the IP revision code for the CM_CORE part of the PRCM" bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3" bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. "R_RTL,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "CUSTOM_0,?,?,?" newline bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision (Y)" "Y_MINOR_0,Y_MINOR_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x40++0x03 line.long 0x00 "CM_CM_CORE_PROFILING_CLKCTRL,This register manages the CM_CORE_PROFILING clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xF0++0x03 line.long 0x00 "CM_CORE_DEBUG_CFG,This register is used to configure the CM_CORE's 32-bit debug output" hexmask.long.byte 0x00 24.--31. 1. "SEL3,Internal signal block select for debug word byte-3" hexmask.long.byte 0x00 16.--23. 1. "SEL2,Internal signal block select for debug word byte-2" hexmask.long.byte 0x00 8.--15. 1. "SEL1,Internal signal block select for debug word byte-1" hexmask.long.byte 0x00 0.--7. 1. "SEL0,Internal signal block select for debug word byte-0" width 0x0B tree.end tree "OCP_SOCKET_CM_CORE_AON" base ad:0x4A005000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION_CM_CORE_AON,This register contains the IP revision code for the CM_CORE_AON part of the PRCM" bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3" bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. "R_RTL,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "CUSTOM_0,?,?,?" newline bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision (Y)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x40++0x03 line.long 0x00 "CM_CM_CORE_AON_PROFILING_CLKCTRL,This register manages the CM_CORE_AON_PROFILING clock" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0xEC++0x03 line.long 0x00 "CM_CORE_AON_DEBUG_OUT,This register is used to monitor the CM_COREAON's 32 bit HEDEBUG BUS [warm reset insensitive]" repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0xF0)++0x03 line.long 0x00 "CM_CORE_AON_DEBUG_CFG$1,This register is used to configure the CM_CORE_AON's 32-bit debug output" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," hexmask.long.word 0x00 0.--9. 1. "SEL0,Internal signal block select for debug word byte-0" repeat.end width 0x0B tree.end tree "OCP_SOCKET_PRM" base ad:0x4AE06000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION_PRM,This register contains the IP revision code for the PRM part of the PRCM" bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3" bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family" newline bitfld.long 0x00 11.--15. "R_RTL,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "CUSTOM_0,?,?,?" newline bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision (Y)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x13 line.long 0x00 "PRM_IRQSTATUS_MPU,This register provides status on MPU interrupt events" rbitfld.long 0x00 31. "RESERVED," "0,1" bitfld.long 0x00 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x00 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x00 13.--27. 1. "RESERVED," bitfld.long 0x00 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x00 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" rbitfld.long 0x00 10. "RESERVED," "0,1" bitfld.long 0x00 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline bitfld.long 0x00 8. "TRANSITION_ST,Software supervised transition completed event interrupt status (any domain)" "TRANSITION_ST_0,TRANSITION_ST_1" bitfld.long 0x00 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x00 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x00 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x00 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x00 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x00 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x00 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x00 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x04 "PRM_IRQSTATUS_MPU_2,This register provides status on MPU interrupt events" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," bitfld.long 0x04 7. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" hexmask.long.byte 0x04 0.--6. 1. "RESERVED," line.long 0x08 "PRM_IRQENABLE_MPU,This register is used to enable or disable MPU interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x08 31. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x08 30. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" bitfld.long 0x08 29. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" newline hexmask.long.tbyte 0x08 12.--28. 1. "RESERVED," bitfld.long 0x08 11. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x08 10. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" newline bitfld.long 0x08 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" bitfld.long 0x08 8. "TRANSITION_EN,Software supervised transition completed event interrupt enable (any domain)" "TRANSITION_EN_0,TRANSITION_EN_1" bitfld.long 0x08 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" newline bitfld.long 0x08 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x08 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x08 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" newline bitfld.long 0x08 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x08 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x08 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" newline bitfld.long 0x08 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x0C "PRM_IRQENABLE_MPU_2,This register is used to enable or disable MPU interrupt activation upon presence of corresponding IRQSTATUS bit" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED," bitfld.long 0x0C 7. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" hexmask.long.byte 0x0C 0.--6. 1. "RESERVED," line.long 0x10 "PRM_IRQSTATUS_IPU2,This register provides status on IPU2 interrupt events" bitfld.long 0x10 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x10 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x10 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x10 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x10 13.--27. 1. "RESERVED," bitfld.long 0x10 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x10 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x10 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x10 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline bitfld.long 0x10 8. "TRANSITION_ST,Software supervised transition completed event interrupt status (any domain)" "TRANSITION_ST_0,TRANSITION_ST_1" bitfld.long 0x10 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x10 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x10 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x10 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x10 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x10 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x10 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x10 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" group.long 0x28++0x03 line.long 0x00 "PRM_IRQENABLE_IPU2,This register is used to enable or disable IPU2 interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x00 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x00 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x00 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" hexmask.long.word 0x00 13.--27. 1. "RESERVED," bitfld.long 0x00 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" newline bitfld.long 0x00 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x00 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x00 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" newline bitfld.long 0x00 8. "TRANSITION_EN,Software supervised transition completed event interrupt enable (any domain)" "TRANSITION_EN_0,TRANSITION_EN_1" bitfld.long 0x00 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x00 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" newline bitfld.long 0x00 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x00 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x00 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" newline bitfld.long 0x00 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x00 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x00 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" group.long 0x30++0x03 line.long 0x00 "PRM_IRQSTATUS_DSP1,This register provides status on DSP1 interrupt events" bitfld.long 0x00 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x00 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x00 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x00 13.--27. 1. "RESERVED," bitfld.long 0x00 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x00 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x00 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x00 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline rbitfld.long 0x00 8. "RESERVED," "0,1" bitfld.long 0x00 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x00 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x00 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x00 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x00 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x00 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x00 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x00 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" group.long 0x38++0x03 line.long 0x00 "PRM_IRQENABLE_DSP1,This register is used to enable or disable DSP1 interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x00 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x00 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x00 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" hexmask.long.word 0x00 14.--27. 1. "RESERVED," bitfld.long 0x00 13. "DPLL_USB_RECAL_EN,USB DPLL recalibration interrupt enable" "DPLL_USB_RECAL_EN_0,DPLL_USB_RECAL_EN_1" newline bitfld.long 0x00 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x00 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x00 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" newline bitfld.long 0x00 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" rbitfld.long 0x00 8. "RESERVED," "0,1" bitfld.long 0x00 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" newline bitfld.long 0x00 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x00 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x00 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" newline bitfld.long 0x00 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x00 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x00 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" newline bitfld.long 0x00 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" group.long 0x40++0x33 line.long 0x00 "CM_PRM_PROFILING_CLKCTRL,This register manages the PRM_PROFILING clock" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x04 "PRM_IRQENABLE_DSP2,This register is used to enable or disable DSP2 interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x04 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x04 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x04 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x04 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" hexmask.long.word 0x04 13.--27. 1. "RESERVED," bitfld.long 0x04 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" newline bitfld.long 0x04 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x04 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x04 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" newline rbitfld.long 0x04 8. "RESERVED," "0,1" bitfld.long 0x04 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x04 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" newline bitfld.long 0x04 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x04 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x04 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" newline bitfld.long 0x04 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x04 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x04 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x08 "PRM_IRQENABLE_EVE1,This register is used to enable or disable EVE1 interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x08 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x08 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x08 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x08 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" hexmask.long.word 0x08 13.--27. 1. "RESERVED," bitfld.long 0x08 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" newline bitfld.long 0x08 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x08 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x08 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" newline rbitfld.long 0x08 8. "RESERVED," "0,1" bitfld.long 0x08 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x08 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" newline bitfld.long 0x08 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x08 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x08 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" newline bitfld.long 0x08 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x08 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x08 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x0C "PRM_IRQENABLE_EVE2,This register is used to enable or disable EVE2 interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x0C 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x0C 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x0C 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x0C 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" hexmask.long.word 0x0C 13.--27. 1. "RESERVED," bitfld.long 0x0C 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" newline bitfld.long 0x0C 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x0C 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x0C 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" newline rbitfld.long 0x0C 8. "RESERVED," "0,1" bitfld.long 0x0C 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x0C 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" newline bitfld.long 0x0C 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x0C 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x0C 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" newline bitfld.long 0x0C 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x0C 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x0C 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x10 "PRM_IRQENABLE_EVE3,This register is used to enable or disable EVE3 interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x10 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x10 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x10 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x10 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" hexmask.long.word 0x10 13.--27. 1. "RESERVED," bitfld.long 0x10 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" newline bitfld.long 0x10 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x10 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x10 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" newline rbitfld.long 0x10 8. "RESERVED," "0,1" bitfld.long 0x10 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x10 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" newline bitfld.long 0x10 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x10 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x10 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" newline bitfld.long 0x10 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x10 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x10 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x14 "PRM_IRQENABLE_EVE4,This register is used to enable or disable EVE4 interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x14 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x14 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x14 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x14 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" hexmask.long.word 0x14 13.--27. 1. "RESERVED," bitfld.long 0x14 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" newline bitfld.long 0x14 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x14 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x14 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" newline rbitfld.long 0x14 8. "RESERVED," "0,1" bitfld.long 0x14 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x14 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" newline bitfld.long 0x14 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x14 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x14 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" newline bitfld.long 0x14 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x14 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x14 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x18 "PRM_IRQENABLE_IPU1,This register is used to enable or disable IPU1 interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x18 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x18 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x18 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x18 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" hexmask.long.word 0x18 13.--27. 1. "RESERVED," bitfld.long 0x18 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" newline bitfld.long 0x18 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x18 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x18 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" newline bitfld.long 0x18 8. "TRANSITION_EN,Software supervised transition completed event interrupt enable (any domain)" "TRANSITION_EN_0,TRANSITION_EN_1" bitfld.long 0x18 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x18 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" newline bitfld.long 0x18 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x18 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x18 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" newline bitfld.long 0x18 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x18 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x18 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x1C "PRM_IRQSTATUS_DSP2,This register provides status on DSP interrupt events" bitfld.long 0x1C 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x1C 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x1C 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x1C 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x1C 13.--27. 1. "RESERVED," bitfld.long 0x1C 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x1C 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x1C 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x1C 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline rbitfld.long 0x1C 8. "RESERVED," "0,1" bitfld.long 0x1C 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x1C 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x1C 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x1C 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x1C 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x1C 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x1C 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x1C 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x20 "PRM_IRQSTATUS_EVE1,This register provides status on EVE interrupt events" bitfld.long 0x20 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x20 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x20 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x20 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x20 13.--27. 1. "RESERVED," bitfld.long 0x20 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x20 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x20 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x20 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline rbitfld.long 0x20 8. "RESERVED," "0,1" bitfld.long 0x20 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x20 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x20 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x20 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x20 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x20 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x20 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x20 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x24 "PRM_IRQSTATUS_EVE2,This register provides status on EVE interrupt events" bitfld.long 0x24 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x24 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x24 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x24 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x24 13.--27. 1. "RESERVED," bitfld.long 0x24 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x24 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x24 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x24 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline rbitfld.long 0x24 8. "RESERVED," "0,1" bitfld.long 0x24 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x24 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x24 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x24 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x24 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x24 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x24 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x24 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x28 "PRM_IRQSTATUS_EVE3,This register provides status on EVE interrupt events" bitfld.long 0x28 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x28 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x28 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x28 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x28 13.--27. 1. "RESERVED," bitfld.long 0x28 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x28 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x28 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x28 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline rbitfld.long 0x28 8. "RESERVED," "0,1" bitfld.long 0x28 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x28 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x28 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x28 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x28 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x28 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x28 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x28 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x2C "PRM_IRQSTATUS_EVE4,This register provides status on EVE interrupt events" bitfld.long 0x2C 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x2C 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x2C 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x2C 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x2C 13.--27. 1. "RESERVED," bitfld.long 0x2C 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x2C 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x2C 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x2C 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline rbitfld.long 0x2C 8. "RESERVED," "0,1" bitfld.long 0x2C 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x2C 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x2C 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x2C 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x2C 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x2C 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x2C 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x2C 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x30 "PRM_IRQSTATUS_IPU1,This register provides status on IPU1 interrupt events" bitfld.long 0x30 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x30 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x30 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x30 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x30 13.--27. 1. "RESERVED," bitfld.long 0x30 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x30 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x30 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x30 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline bitfld.long 0x30 8. "TRANSITION_ST,Software supervised transition completed event interrupt status (any domain)" "TRANSITION_ST_0,TRANSITION_ST_1" bitfld.long 0x30 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x30 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x30 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x30 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x30 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x30 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x30 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x30 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" rgroup.long 0xF4++0x03 line.long 0x00 "PRM_DEBUG_OUT,This register is used to monitor the PRM's 32 bit HEDEBUG BUS [warm reset insensitive]" repeat 4. (list 1. 2. 3. 4. )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0xE4)++0x03 line.long 0x00 "PRM_DEBUG_CFG$1,This register is used to configure the PRM's 32-bit debug output" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," hexmask.long.word 0x00 0.--8. 1. "SEL1,Internal signal block select for debug word byte-1" repeat.end width 0x0B tree.end tree "OCP_WP_NOC_TARG" base ad:0x4A103000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_H,Error reporting" line.long 0x14 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x14 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x14 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x14 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x14 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x14 0. "OCP_RESET,L3 Reset" "0,1" width 0x0B tree.end tree "PORT" base ad:0x48484100 group.long 0x00++0x03 line.long 0x00 "P0_CONTROL,CPSW PORT 0 control register" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 28.--30. "P0_DLR_CPDMA_CH,Port 0 DLR CPDMA Channel This field indicates the CPDMA channel that DLR packets will be received on" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "Priority tagged packets have the zero VID..,Priority tagged packets are processed unchanged" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 21. "P0_VLAN_LTYPE2_EN,Port 0 VLAN LTYPE 2 enable" "disabled,enabled" newline bitfld.long 0x00 20. "P0_VLAN_LTYPE1_EN,Port 0 VLAN LTYPE 1 enable" "disabled,enabled" newline rbitfld.long 0x00 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. "P0_DSCP_PRI_EN,Port 0 DSCP Priority Enable" "DSCP priority disabled,DSCP priority enabled" newline hexmask.long.word 0x00 0.--15. 1. "RESERVED," group.long 0x08++0x1B line.long 0x00 "P0_MAX_BLKS,CPSW PORT 0 maximum FIFO blocks register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 4.--8. "P0_TX_MAX_BLKS,Transmit FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical transmit priority queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--3. "P0_RX_MAX_BLKS,Receive FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical receive queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "P0_BLK_CNT,CPSW PORT 0 FIFO block usage count (read only)" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," newline bitfld.long 0x04 4.--8. "P0_TX_BLK_CNT,Port 0 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--3. "P0_RX_BLK_CNT,Port 0 Receive Block Count Usage - This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "P0_TX_IN_CTL,CPSW PORT 0 transmit FIFO control" hexmask.long.byte 0x08 24.--31. 1. "RESERVED," newline bitfld.long 0x08 20.--23. "TX_RATE_EN,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x08 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 16.--17. "TX_IN_SEL,Transmit FIFO Input Queue Type Select" "Normal priority mode,Dual MAC mode,Rate Limit mode,reserved Note that Dual MAC mode is not.." newline bitfld.long 0x08 12.--15. "TX_BLKS_REM,Transmit FIFO Input Blocks to subtract in dual MAC mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x08 10.--11. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x08 0.--9. 1. "TX_PRI_WDS,Transmit FIFO Words in queue" line.long 0x0C "P0_PORT_VLAN,CPSW PORT 0 VLAN register" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," newline bitfld.long 0x0C 13.--15. "PORT_PRI,Port VLAN Priority (7 is highest priority)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0C 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x10 "P0_TX_PRI_MAP,CPSW PORT 0 TX header priority to switch priority mapping register" rbitfld.long 0x10 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 28.--29. "PRI7,Priority" "0,1,2,3" newline rbitfld.long 0x10 26.--27. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 24.--25. "PRI6,Priority" "0,1,2,3" newline rbitfld.long 0x10 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 20.--21. "PRI5,Priority" "0,1,2,3" newline rbitfld.long 0x10 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 16.--17. "PRI4,Priority" "0,1,2,3" newline rbitfld.long 0x10 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 12.--13. "PRI3,Priority" "0,1,2,3" newline rbitfld.long 0x10 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 8.--9. "PRI2,Priority" "0,1,2,3" newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 4.--5. "PRI1,Priority" "0,1,2,3" newline rbitfld.long 0x10 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRI0,Priority" "0,1,2,3" line.long 0x14 "P0_CPDMA_TX_PRI_MAP,CPSW CPDMA TX (PORT 0 RX) packet priority to header priority" rbitfld.long 0x14 31. "RESERVED," "0,1" newline bitfld.long 0x14 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED," "0,1" newline bitfld.long 0x14 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED," "0,1" newline bitfld.long 0x14 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED," "0,1" newline bitfld.long 0x14 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED," "0,1" newline bitfld.long 0x14 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED," "0,1" newline bitfld.long 0x14 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED," "0,1" newline bitfld.long 0x14 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x18 "P0_CPDMA_RX_CH_MAP,CPSW CPDMA RX (PORT 0 TX) switch priority to DMA channel" rbitfld.long 0x18 31. "RESERVED," "0,1" newline bitfld.long 0x18 28.--30. "P2_PRI3,Port 2 Priority 3 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED," "0,1" newline bitfld.long 0x18 24.--26. "P2_PRI2,Port 2 Priority 2 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED," "0,1" newline bitfld.long 0x18 20.--22. "P2_PRI1,Port 2 Priority 1 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED," "0,1" newline bitfld.long 0x18 16.--18. "P2_PRI0,Port 2 Priority 0 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED," "0,1" newline bitfld.long 0x18 12.--14. "P1_PRI3,Port 1 Priority 3 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED," "0,1" newline bitfld.long 0x18 8.--10. "P1_PRI2,Port 1 Priority 2 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED," "0,1" newline bitfld.long 0x18 4.--6. "P1_PRI1,Port 1 Priority 1 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED," "0,1" newline bitfld.long 0x18 0.--2. "P1_PRI0,Port 1 Priority 0 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" group.long 0x30++0x27 line.long 0x00 "P0_RX_DSCP_PRI_MAP0,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 0" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 27. "RESERVED," "0,1" newline bitfld.long 0x00 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 23. "RESERVED," "0,1" newline bitfld.long 0x00 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED," "0,1" newline bitfld.long 0x00 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. "RESERVED," "0,1" newline bitfld.long 0x00 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED," "0,1" newline bitfld.long 0x00 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x04 "P0_RX_DSCP_PRI_MAP1,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 1" rbitfld.long 0x04 31. "RESERVED," "0,1" newline bitfld.long 0x04 28.--30. "PRI15,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 27. "RESERVED," "0,1" newline bitfld.long 0x04 24.--26. "PRI14,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 23. "RESERVED," "0,1" newline bitfld.long 0x04 20.--22. "PRI13,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED," "0,1" newline bitfld.long 0x04 16.--18. "PRI12,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 15. "RESERVED," "0,1" newline bitfld.long 0x04 12.--14. "PRI11,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 11. "RESERVED," "0,1" newline bitfld.long 0x04 8.--10. "PRI10,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED," "0,1" newline bitfld.long 0x04 4.--6. "PRI9,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 0.--2. "PRI8,Priority" "0,1,2,3,4,5,6,7" line.long 0x08 "P0_RX_DSCP_PRI_MAP2,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 2" rbitfld.long 0x08 31. "RESERVED," "0,1" newline bitfld.long 0x08 28.--30. "PRI23,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 27. "RESERVED," "0,1" newline bitfld.long 0x08 24.--26. "PRI22,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 23. "RESERVED," "0,1" newline bitfld.long 0x08 20.--22. "PRI21,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED," "0,1" newline bitfld.long 0x08 16.--18. "PRI20,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 15. "RESERVED," "0,1" newline bitfld.long 0x08 12.--14. "PRI19,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 11. "RESERVED," "0,1" newline bitfld.long 0x08 8.--10. "PRI18,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED," "0,1" newline bitfld.long 0x08 4.--6. "PRI17,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 0.--2. "PRI16,Priority" "0,1,2,3,4,5,6,7" line.long 0x0C "P0_RX_DSCP_PRI_MAP3,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 3" rbitfld.long 0x0C 31. "RESERVED," "0,1" newline bitfld.long 0x0C 28.--30. "PRI31,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 27. "RESERVED," "0,1" newline bitfld.long 0x0C 24.--26. "PRI30,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 23. "RESERVED," "0,1" newline bitfld.long 0x0C 20.--22. "PRI29,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED," "0,1" newline bitfld.long 0x0C 16.--18. "PRI28,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 15. "RESERVED," "0,1" newline bitfld.long 0x0C 12.--14. "PRI27,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 11. "RESERVED," "0,1" newline bitfld.long 0x0C 8.--10. "PRI26,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED," "0,1" newline bitfld.long 0x0C 4.--6. "PRI25,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 0.--2. "PRI24,Priority" "0,1,2,3,4,5,6,7" line.long 0x10 "P0_RX_DSCP_PRI_MAP4,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 4" rbitfld.long 0x10 31. "RESERVED," "0,1" newline bitfld.long 0x10 28.--30. "PRI39,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED," "0,1" newline bitfld.long 0x10 24.--26. "PRI38,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED," "0,1" newline bitfld.long 0x10 20.--22. "PRI37,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "RESERVED," "0,1" newline bitfld.long 0x10 16.--18. "PRI36,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 15. "RESERVED," "0,1" newline bitfld.long 0x10 12.--14. "PRI35,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 11. "RESERVED," "0,1" newline bitfld.long 0x10 8.--10. "PRI34,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 7. "RESERVED," "0,1" newline bitfld.long 0x10 4.--6. "PRI33,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 3. "RESERVED," "0,1" newline bitfld.long 0x10 0.--2. "PRI32,Priority" "0,1,2,3,4,5,6,7" line.long 0x14 "P0_RX_DSCP_PRI_MAP5,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 5" rbitfld.long 0x14 31. "RESERVED," "0,1" newline bitfld.long 0x14 28.--30. "PRI47,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED," "0,1" newline bitfld.long 0x14 24.--26. "PRI46,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED," "0,1" newline bitfld.long 0x14 20.--22. "PRI45,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED," "0,1" newline bitfld.long 0x14 16.--18. "PRI44,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED," "0,1" newline bitfld.long 0x14 12.--14. "PRI43,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED," "0,1" newline bitfld.long 0x14 8.--10. "PRI42,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED," "0,1" newline bitfld.long 0x14 4.--6. "PRI41,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 0.--2. "PRI40,Priority" "0,1,2,3,4,5,6,7" line.long 0x18 "P0_RX_DSCP_PRI_MAP6,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 6" rbitfld.long 0x18 31. "RESERVED," "0,1" newline bitfld.long 0x18 28.--30. "PRI55,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED," "0,1" newline bitfld.long 0x18 24.--26. "PRI54,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED," "0,1" newline bitfld.long 0x18 20.--22. "PRI53,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED," "0,1" newline bitfld.long 0x18 16.--18. "PRI52,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED," "0,1" newline bitfld.long 0x18 12.--14. "PRI51,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED," "0,1" newline bitfld.long 0x18 8.--10. "PRI50,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED," "0,1" newline bitfld.long 0x18 4.--6. "PRI49,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED," "0,1" newline bitfld.long 0x18 0.--2. "PRI48,Priority" "0,1,2,3,4,5,6,7" line.long 0x1C "P0_RX_DSCP_PRI_MAP7,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 7" rbitfld.long 0x1C 31. "RESERVED," "0,1" newline bitfld.long 0x1C 28.--30. "PRI63,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 27. "RESERVED," "0,1" newline bitfld.long 0x1C 24.--26. "PRI62,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 23. "RESERVED," "0,1" newline bitfld.long 0x1C 20.--22. "PRI61,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 19. "RESERVED," "0,1" newline bitfld.long 0x1C 16.--18. "PRI60,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 15. "RESERVED," "0,1" newline bitfld.long 0x1C 12.--14. "PRI59,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 11. "RESERVED," "0,1" newline bitfld.long 0x1C 8.--10. "PRI58,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 7. "RESERVED," "0,1" newline bitfld.long 0x1C 4.--6. "PRI57,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 3. "RESERVED," "0,1" newline bitfld.long 0x1C 0.--2. "PRI56,Priority" "0,1,2,3,4,5,6,7" line.long 0x20 "P0_IDLE2LPI,Port 0 EEE Idle to LPI Counter Load Value Register" hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x20 0.--19. 1. "P0_IDLE2LPI,Port 0 EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted this value is loaded into the port 0 idle to LPI counter on each clock that the port 0 transmit is not idle" line.long 0x24 "P0_LPI2WAKE,Port 0 EEE LPI to Wake Counter Load Value Register" hexmask.long.word 0x24 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x24 0.--19. 1. "P0_LPI2WAKE,Port 0 EEE LPI to wake counter load value - When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted this value is loaded into the port 0 LPI to wake counter" group.long 0x100++0x03 line.long 0x00 "P1_CONTROL,CPSW PORT 1 control register" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 25. "P1_TX_CLKSTOP_EN,Port 1 Transmit clockstop enable 0 - RGMII transmit clockstop not enabled 1 - RGMII transmit clockstop enabled" "0,1" newline bitfld.long 0x00 24. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "Priority tagged packets have the zero VID..,Priority tagged packets are processed unchanged" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 21. "P1_VLAN_LTYPE2_EN,Port 1 VLAN LTYPE 2 enable" "disabled,VLAN LTYPE2 enabled on.." newline bitfld.long 0x00 20. "P1_VLAN_LTYPE1_EN,Port 1 VLAN LTYPE 1 enable" "disabled,VLAN LTYPE1 enabled on.." newline rbitfld.long 0x00 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. "P1_DSCP_PRI_EN,Port 1 DSCP Priority Enable" "DSCP priority disabled,DSCP priority enabled" newline bitfld.long 0x00 15. "P1_TS_107,Port 1 Time Sync Destination IP Address 107 enable 0 - disabled 1 - destination IP address (dec) 224.0.0.107 is enabled" "0,1" newline bitfld.long 0x00 14. "P1_TS_320,Port 1 Time Sync Destination Port Number 320 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 13. "P1_TS_319,Port 1 Time Sync Destination Port Number 319 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 12. "P1_TS_132,Port 1 Time Sync Destination IP Address 132 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 11. "P1_TS_131,Port 1 Time Sync Destination IP Address 131 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 10. "P1_TS_130,Port 1 Time Sync Destination IP Address 130 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 9. "P1_TS_129,Port 1 Time Sync Destination IP Address 129 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 8. "P1_TS_TTL_NONZERO,Port 1 Time Sync Time To Live Non-zero enable" "TTL must be zero,TTL may be any value" newline bitfld.long 0x00 7. "P1_TS_UNI_EN,Port 1 Time Sync Unicast Enable 0 - Unicast disabled 1 - Unicast enabled" "0,1" newline bitfld.long 0x00 6. "P1_TS_ANNEX_F_EN,Port 1 Time Sync Annex F enable 0 - Annex F disabled 1 - Annex F enabled" "0,1" newline bitfld.long 0x00 5. "P1_TS_ANNEX_E_EN,Port 1 Time Sync Annex E enable 0 - Annex E disabled 1 - Annex E enabled" "0,1" newline bitfld.long 0x00 4. "P1_TS_ANNEX_D_EN,Port 1 Time Sync Annex D enable" "Annex D disabled,Annex D enabled" newline bitfld.long 0x00 3. "P1_TS_LTYPE2_EN,Port 1 Time Sync LTYPE 2 enable" "disabled,enabled" newline bitfld.long 0x00 2. "P1_TS_LTYPE1_EN,Port 1 Time Sync LTYPE 1 enable" "disabled,enabled" newline bitfld.long 0x00 1. "P1_TS_TX_EN,Port 1 Time Sync Transmit Enable" "disabled,enabled" newline bitfld.long 0x00 0. "P1_TS_RX_EN,Port 1 Time Sync Receive Enable" "Port 1 Receive Time Sync disabled,Port 1 Receive Time Sync enabled" group.long 0x108++0x23 line.long 0x00 "P1_MAX_BLKS,CPSW PORT 1 maximum FIFO blocks register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 4.--8. "P1_TX_MAX_BLKS,Transmit FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical transmit priority queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--3. "P1_RX_MAX_BLKS,Receive FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical receive queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "P1_BLK_CNT,CPSW PORT 1 FIFO block usage count (read only)" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," newline bitfld.long 0x04 4.--8. "P1_TX_BLK_CNT,Port 1 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--3. "P1_RX_BLK_CNT,Port 1 Receive Block Count Usage - This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "P1_TX_IN_CTL,CPSW PORT 1 transmit FIFO control" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPDMA channel can begin sending a packet to the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 20.--23. "TX_RATE_EN,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x08 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 16.--17. "TX_IN_SEL,Transmit FIFO Input Queue Type Select" "Normal priority mode,reserved,Rate Limit mode,reserved" newline bitfld.long 0x08 12.--15. "TX_BLKS_REM,Transmit FIFO Input blocks to subtract on non rate-limited traffic in rate limit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x08 10.--11. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x08 0.--9. 1. "TX_PRI_WDS,Transmit FIFO Words in queue" line.long 0x0C "P1_PORT_VLAN,CPSW PORT 1 VLAN register" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," newline bitfld.long 0x0C 13.--15. "PORT_PRI,Port VLAN Priority (7 is highest priority)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0C 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x10 "P1_TX_PRI_MAP,CPSW PORT 1 TX header priority to switch priority mapping register" rbitfld.long 0x10 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 28.--29. "PRI7,Priority" "0,1,2,3" newline rbitfld.long 0x10 26.--27. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 24.--25. "PRI6,Priority" "0,1,2,3" newline rbitfld.long 0x10 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 20.--21. "PRI5,Priority" "0,1,2,3" newline rbitfld.long 0x10 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 16.--17. "PRI4,Priority" "0,1,2,3" newline rbitfld.long 0x10 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 12.--13. "PRI3,Priority" "0,1,2,3" newline rbitfld.long 0x10 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 8.--9. "PRI2,Priority" "0,1,2,3" newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 4.--5. "PRI1,Priority" "0,1,2,3" newline rbitfld.long 0x10 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRI0,Priority" "0,1,2,3" line.long 0x14 "P1_TS_SEQ_MTYPE,CPSW PORT 1 time sync sequence ID offset and message type" hexmask.long.word 0x14 22.--31. 1. "RESERVED," newline bitfld.long 0x14 16.--21. "P1_TS_SEQ_ID_OFFSET,Port 1 Time Sync Sequence ID Offset This is the number of octets that the sequence ID is offset in the tx and rx time sync message header" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x14 0.--15. 1. "P1_TS_MSG_TYPE_EN,Port 1 Time Sync Message Type Enable - Each bit in this field enables the corresponding message type in receive and transmit time sync messages (Bit 0 enables message type 0 etc.)" line.long 0x18 "P1_SA_LO,CPSW CPGMAC_SL1 source address low register" hexmask.long.word 0x18 16.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits (byte 0)" newline hexmask.long.byte 0x18 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15:8 (byte 1)" line.long 0x1C "P1_SA_HI,CPSW CPGMAC_SL1 source address high register" hexmask.long.byte 0x1C 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23:16 (byte 2)" newline hexmask.long.byte 0x1C 16.--23. 1. "MACSRCADDR_31_24,Source Address bits 31:24 (byte 3)" newline hexmask.long.byte 0x1C 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39:32 (byte 4)" newline hexmask.long.byte 0x1C 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47:40 (byte 5)" line.long 0x20 "P1_SEND_PERCENT,CPSW PORT 1 transmit queue send percentages" hexmask.long.word 0x20 23.--31. 1. "RESERVED," newline hexmask.long.byte 0x20 16.--22. 1. "PRI3_SEND_PERCENT,Priority 3 Transmit Percentage - This percentage value is sent from FIFO priority 3 (maximum) whenCPSW_PTYPE[18] P1_PRI3_SHAPE_EN is set (queue shaping enabled)" newline rbitfld.long 0x20 15. "RESERVED," "0,1" newline hexmask.long.byte 0x20 8.--14. 1. "PRI2_SEND_PERCENT,Priority 2 Transmit Percentage - This percentage value is sent from FIFO priority 2 (maximum) whenCPSW_PTYPE[17] P1_PRI2_SHAPE_EN is set (queue shaping enabled)" newline rbitfld.long 0x20 7. "RESERVED," "0,1" newline hexmask.long.byte 0x20 0.--6. 1. "PRI1_SEND_PERCENT,Priority 1 Transmit Percentage - This percentage value is sent from FIFO priority 1 (maximum) when theCPSW_PTYPE[16] P1_PRI1_SHAPE_EN is set (queue shaping enabled)" group.long 0x130++0x27 line.long 0x00 "P1_RX_DSCP_PRI_MAP0,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 0" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 27. "RESERVED," "0,1" newline bitfld.long 0x00 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 23. "RESERVED," "0,1" newline bitfld.long 0x00 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED," "0,1" newline bitfld.long 0x00 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. "RESERVED," "0,1" newline bitfld.long 0x00 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED," "0,1" newline bitfld.long 0x00 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x04 "P1_RX_DSCP_PRI_MAP1,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 1" rbitfld.long 0x04 31. "RESERVED," "0,1" newline bitfld.long 0x04 28.--30. "PRI15,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 27. "RESERVED," "0,1" newline bitfld.long 0x04 24.--26. "PRI14,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 23. "RESERVED," "0,1" newline bitfld.long 0x04 20.--22. "PRI13,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED," "0,1" newline bitfld.long 0x04 16.--18. "PRI12,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 15. "RESERVED," "0,1" newline bitfld.long 0x04 12.--14. "PRI11,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 11. "RESERVED," "0,1" newline bitfld.long 0x04 8.--10. "PRI10,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED," "0,1" newline bitfld.long 0x04 4.--6. "PRI9,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 0.--2. "PRI8,Priority" "0,1,2,3,4,5,6,7" line.long 0x08 "P1_RX_DSCP_PRI_MAP2,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 2" rbitfld.long 0x08 31. "RESERVED," "0,1" newline bitfld.long 0x08 28.--30. "PRI23,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 27. "RESERVED," "0,1" newline bitfld.long 0x08 24.--26. "PRI22,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 23. "RESERVED," "0,1" newline bitfld.long 0x08 20.--22. "PRI21,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED," "0,1" newline bitfld.long 0x08 16.--18. "PRI20,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 15. "RESERVED," "0,1" newline bitfld.long 0x08 12.--14. "PRI19,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 11. "RESERVED," "0,1" newline bitfld.long 0x08 8.--10. "PRI18,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED," "0,1" newline bitfld.long 0x08 4.--6. "PRI17,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 0.--2. "PRI16,Priority" "0,1,2,3,4,5,6,7" line.long 0x0C "P1_RX_DSCP_PRI_MAP3,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 3" rbitfld.long 0x0C 31. "RESERVED," "0,1" newline bitfld.long 0x0C 28.--30. "PRI31,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 27. "RESERVED," "0,1" newline bitfld.long 0x0C 24.--26. "PRI30,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 23. "RESERVED," "0,1" newline bitfld.long 0x0C 20.--22. "PRI29,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED," "0,1" newline bitfld.long 0x0C 16.--18. "PRI28,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 15. "RESERVED," "0,1" newline bitfld.long 0x0C 12.--14. "PRI27,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 11. "RESERVED," "0,1" newline bitfld.long 0x0C 8.--10. "PRI26,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED," "0,1" newline bitfld.long 0x0C 4.--6. "PRI25,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 0.--2. "PRI24,Priority" "0,1,2,3,4,5,6,7" line.long 0x10 "P1_RX_DSCP_PRI_MAP4,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 4" rbitfld.long 0x10 31. "RESERVED," "0,1" newline bitfld.long 0x10 28.--30. "PRI39,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED," "0,1" newline bitfld.long 0x10 24.--26. "PRI38,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED," "0,1" newline bitfld.long 0x10 20.--22. "PRI37,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "RESERVED," "0,1" newline bitfld.long 0x10 16.--18. "PRI36,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 15. "RESERVED," "0,1" newline bitfld.long 0x10 12.--14. "PRI35,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 11. "RESERVED," "0,1" newline bitfld.long 0x10 8.--10. "PRI34,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 7. "RESERVED," "0,1" newline bitfld.long 0x10 4.--6. "PRI33,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 3. "RESERVED," "0,1" newline bitfld.long 0x10 0.--2. "PRI32,Priority" "0,1,2,3,4,5,6,7" line.long 0x14 "P1_RX_DSCP_PRI_MAP5,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 5" rbitfld.long 0x14 31. "RESERVED," "0,1" newline bitfld.long 0x14 28.--30. "PRI47,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED," "0,1" newline bitfld.long 0x14 24.--26. "PRI46,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED," "0,1" newline bitfld.long 0x14 20.--22. "PRI45,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED," "0,1" newline bitfld.long 0x14 16.--18. "PRI44,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED," "0,1" newline bitfld.long 0x14 12.--14. "PRI43,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED," "0,1" newline bitfld.long 0x14 8.--10. "PRI42,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED," "0,1" newline bitfld.long 0x14 4.--6. "PRI41,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 0.--2. "PRI40,Priority" "0,1,2,3,4,5,6,7" line.long 0x18 "P1_RX_DSCP_PRI_MAP6,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 6" rbitfld.long 0x18 31. "RESERVED," "0,1" newline bitfld.long 0x18 28.--30. "PRI55,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED," "0,1" newline bitfld.long 0x18 24.--26. "PRI54,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED," "0,1" newline bitfld.long 0x18 20.--22. "PRI53,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED," "0,1" newline bitfld.long 0x18 16.--18. "PRI52,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED," "0,1" newline bitfld.long 0x18 12.--14. "PRI51,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED," "0,1" newline bitfld.long 0x18 8.--10. "PRI50,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED," "0,1" newline bitfld.long 0x18 4.--6. "PRI49,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED," "0,1" newline bitfld.long 0x18 0.--2. "PRI48,Priority" "0,1,2,3,4,5,6,7" line.long 0x1C "P1_RX_DSCP_PRI_MAP7,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 7" rbitfld.long 0x1C 31. "RESERVED," "0,1" newline bitfld.long 0x1C 28.--30. "PRI63,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 27. "RESERVED," "0,1" newline bitfld.long 0x1C 24.--26. "PRI62,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 23. "RESERVED," "0,1" newline bitfld.long 0x1C 20.--22. "PRI61,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 19. "RESERVED," "0,1" newline bitfld.long 0x1C 16.--18. "PRI60,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 15. "RESERVED," "0,1" newline bitfld.long 0x1C 12.--14. "PRI59,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 11. "RESERVED," "0,1" newline bitfld.long 0x1C 8.--10. "PRI58,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 7. "RESERVED," "0,1" newline bitfld.long 0x1C 4.--6. "PRI57,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 3. "RESERVED," "0,1" newline bitfld.long 0x1C 0.--2. "PRI56,Priority" "0,1,2,3,4,5,6,7" line.long 0x20 "P1_IDLE2LPI,Port 1 EEE Idle to LPI Counter Load Value Register" hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x20 0.--19. 1. "P1_IDLE2LPI,Port 1 EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted this value is loaded into the port 1 idle to LPI counter on each clock that the port 1 transmit is not idle" line.long 0x24 "P1_LPI2WAKE,Port 1 EEE LPI to Wake Counter Load Value Register" hexmask.long.word 0x24 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x24 0.--19. 1. "P1_LPI2WAKE,Port 1 EEE LPI to wake counter load value - When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted this value is loaded into the port 1 LPI to wake counter" group.long 0x200++0x03 line.long 0x00 "P2_CONTROL,CPSW_3GF PORT 2 control register" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 25. "P2_TX_CLKSTOP_EN,Port 2 Transmit clockstop enable 0 - RGMII transmit clockstop not enabled 1 - RGMII transmit clockstop enabled" "0,1" newline bitfld.long 0x00 24. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged" "Priority tagged packets have the zero VID..,Priority tagged packets are processed unchanged" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 21. "P2_VLAN_LTYPE2_EN,Port 2 VLAN LTYPE 2 enable" "disabled,VLAN LTYPE2 enabled on.." newline bitfld.long 0x00 20. "P2_VLAN_LTYPE1_EN,Port 2 VLAN LTYPE 1 enable" "disabled,VLAN LTYPE1 enabled on.." newline rbitfld.long 0x00 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. "P2_DSCP_PRI_EN,Port 0 DSCP Priority Enable" "DSCP priority disabled,DSCP priority enabled" newline bitfld.long 0x00 15. "P2_TS_107,Port 2 Time Sync Destination IP Address 107 enable 0 - disabled 1 - destination IP address (dec) 224.0.0.107 is enabled" "0,1" newline bitfld.long 0x00 14. "P2_TS_320,Port 2 Time Sync Destination Port Number 320 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 13. "P2_TS_319,Port 2 Time Sync Destination Port Number 319 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 12. "P2_TS_132,Port 2 Time Sync Destination IP Address 132 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 11. "P2_TS_131,Port 2 Time Sync Destination IP Address 131 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 10. "P2_TS_130,Port 2 Time Sync Destination IP Address 130 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 9. "P2_TS_129,Port 2 Time Sync Destination IP Address 129 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 8. "P2_TS_TTL_NONZERO,Port 2 Time Sync Time To Live Non-zero enable" "TTL must be zero,TTL may be any value" newline bitfld.long 0x00 7. "P2_TS_UNI_EN,Port 2 Time Sync Unicast Enable 0 - Unicast disabled 1 - Unicast enabled" "0,1" newline bitfld.long 0x00 6. "P2_TS_ANNEX_F_EN,Port 2 Time Sync Annex F enable 0 - Annex F disabled 1 - Annex F enabled" "0,1" newline bitfld.long 0x00 5. "P2_TS_ANNEX_E_EN,Port 2 Time Sync Annex E enable 0 - Annex E disabled 1 - Annex E enabled" "0,1" newline bitfld.long 0x00 4. "P2_TS_ANNEX_D_EN,Port 2 Time Sync Annex D enable" "Annex D disabled,Annex D enabled" newline bitfld.long 0x00 3. "P2_TS_LTYPE2_EN,Port 2 Time Sync LTYPE 2 enable" "disabled,enabled" newline bitfld.long 0x00 2. "P2_TS_LTYPE1_EN,Port 2 Time Sync LTYPE 1 enable" "disabled,enabled" newline bitfld.long 0x00 1. "P2_TS_TX_EN,Port 2 Time Sync Transmit Enable" "disabled,enabled" newline bitfld.long 0x00 0. "P2_TS_RX_EN,Port 2 Time Sync Receive Enable" "Port 1 Receive Time Sync disabled,Port 1 Receive Time Sync enabled" group.long 0x208++0x23 line.long 0x00 "P2_MAX_BLKS,CPSW PORT 2 maximum FIFO blocks register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 4.--8. "P2_TX_MAX_BLKS,Transmit FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical transmit priority queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--3. "P2_RX_MAX_BLKS,Receive FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical receive queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "P2_BLK_CNT,CPSW PORT 2 FIFO block usage count (read only)" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," newline bitfld.long 0x04 4.--8. "P2_TX_BLK_CNT,Port 2 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--3. "P2_RX_BLK_CNT,Port 2 Receive Block Count Usage - This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "P2_TX_IN_CTL,CPSW PORT 2 transmit FIFO control" bitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPDMA channel can begin sending a packet to the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 20.--23. "TX_RATE_EN,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 16.--17. "TX_IN_SEL,Transmit FIFO Input Queue Type Select" "Normal priority mode,reserved,Rate Limit mode,reserved" newline bitfld.long 0x08 12.--15. "TX_BLKS_REM,Transmit FIFO Input blocks to subtract on non rate-limited traffic in rate limit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 10.--11. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x08 0.--9. 1. "TX_PRI_WDS,Transmit FIFO Words in queue" line.long 0x0C "P2_PORT_VLAN,CPSW PORT 2 VLAN register" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," newline bitfld.long 0x0C 13.--15. "PORT_PRI,Port VLAN Priority (7 is highest priority)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0C 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x10 "P2_TX_PRI_MAP,CPSW PORT 2 TX header priority to switch priority mapping register" rbitfld.long 0x10 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 28.--29. "PRI7,Priority" "0,1,2,3" newline rbitfld.long 0x10 26.--27. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 24.--25. "PRI6,Priority" "0,1,2,3" newline rbitfld.long 0x10 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 20.--21. "PRI5,Priority" "0,1,2,3" newline rbitfld.long 0x10 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 16.--17. "PRI4,Priority" "0,1,2,3" newline rbitfld.long 0x10 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 12.--13. "PRI3,Priority" "0,1,2,3" newline rbitfld.long 0x10 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 8.--9. "PRI2,Priority" "0,1,2,3" newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 4.--5. "PRI1,Priority" "0,1,2,3" newline rbitfld.long 0x10 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRI0,Priority" "0,1,2,3" line.long 0x14 "P2_TS_SEQ_MTYPE,CPSW_3GF PORT 2 time sync sequence ID offset and message type" hexmask.long.word 0x14 22.--31. 1. "RESERVED," newline bitfld.long 0x14 16.--21. "P2_TS_SEQ_ID_OFFSET,Port 2 Time Sync Sequence ID Offset This is the number of octets that the sequence ID is offset in the tx and rx time sync message header" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x14 0.--15. 1. "P2_TS_MSG_TYPE_EN,Port 2 Time Sync Message Type Enable - Each bit in this field enables the corresponding message type in receive and transmit time sync messages (Bit 0 enables message type 0 etc.)" line.long 0x18 "P2_SA_LO,CPSW CPGMAC_SL2 source address low register" hexmask.long.word 0x18 16.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits (byte 0)" newline hexmask.long.byte 0x18 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15:8 (byte 1)" line.long 0x1C "P2_SA_HI,CPSW CPGMAC_SL2 source address high register" hexmask.long.byte 0x1C 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23:16 (byte 2)" newline hexmask.long.byte 0x1C 16.--23. 1. "MACSRCADDR_31_23,Source Address bits 31:23 (byte 3)" newline hexmask.long.byte 0x1C 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39:32 (byte 4)" newline hexmask.long.byte 0x1C 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47:40 (byte 5)" line.long 0x20 "P2_SEND_PERCENT,CPSW PORT 2 transmit queue send percentages" hexmask.long.word 0x20 23.--31. 1. "RESERVED," newline hexmask.long.byte 0x20 16.--22. 1. "PRI3_SEND_PERCENT,Priority 3 Transmit Percentage - This percentage value is sent from FIFO priority 3 (maximum) when theCPSW_PTYPE[21] P2_PRI3_SHAPE_EN is set (queue shaping enabled)" newline rbitfld.long 0x20 15. "RESERVED," "0,1" newline hexmask.long.byte 0x20 8.--14. 1. "PRI2_SEND_PERCENT,Priority 2 Transmit Percentage - This percentage value is sent from FIFO priority 2 (maximum) when theCPSW_PTYPE[20] P2_PRI2_SHAPE_EN is set (queue shaping enabled)" newline rbitfld.long 0x20 7. "RESERVED," "0,1" newline hexmask.long.byte 0x20 0.--6. 1. "PRI1_SEND_PERCENT,Priority 1 Transmit Percentage - This percentage value is sent from FIFO priority 1 (maximum) when theCPSW_PTYPE[19] P2_PRI1_SHAPE_EN is set (queue shaping enabled)" group.long 0x230++0x27 line.long 0x00 "P2_RX_DSCP_PRI_MAP0,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 0" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 27. "RESERVED," "0,1" newline bitfld.long 0x00 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 23. "RESERVED," "0,1" newline bitfld.long 0x00 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED," "0,1" newline bitfld.long 0x00 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. "RESERVED," "0,1" newline bitfld.long 0x00 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED," "0,1" newline bitfld.long 0x00 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x04 "P2_RX_DSCP_PRI_MAP1,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 1" rbitfld.long 0x04 31. "RESERVED," "0,1" newline bitfld.long 0x04 28.--30. "PRI15,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 27. "RESERVED," "0,1" newline bitfld.long 0x04 24.--26. "PRI14,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 23. "RESERVED," "0,1" newline bitfld.long 0x04 20.--22. "PRI13,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED," "0,1" newline bitfld.long 0x04 16.--18. "PRI12,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 15. "RESERVED," "0,1" newline bitfld.long 0x04 12.--14. "PRI11,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 11. "RESERVED," "0,1" newline bitfld.long 0x04 8.--10. "PRI10,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED," "0,1" newline bitfld.long 0x04 4.--6. "PRI9,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 0.--2. "PRI8,Priority" "0,1,2,3,4,5,6,7" line.long 0x08 "P2_RX_DSCP_PRI_MAP2,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 2" rbitfld.long 0x08 31. "RESERVED," "0,1" newline bitfld.long 0x08 28.--30. "PRI23,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 27. "RESERVED," "0,1" newline bitfld.long 0x08 24.--26. "PRI22,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 23. "RESERVED," "0,1" newline bitfld.long 0x08 20.--22. "PRI21,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED," "0,1" newline bitfld.long 0x08 16.--18. "PRI20,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 15. "RESERVED," "0,1" newline bitfld.long 0x08 12.--14. "PRI19,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 11. "RESERVED," "0,1" newline bitfld.long 0x08 8.--10. "PRI18,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED," "0,1" newline bitfld.long 0x08 4.--6. "PRI17,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 0.--2. "PRI16,Priority" "0,1,2,3,4,5,6,7" line.long 0x0C "P2_RX_DSCP_PRI_MAP3,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 3" rbitfld.long 0x0C 31. "RESERVED," "0,1" newline bitfld.long 0x0C 28.--30. "PRI31,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 27. "RESERVED," "0,1" newline bitfld.long 0x0C 24.--26. "PRI30,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 23. "RESERVED," "0,1" newline bitfld.long 0x0C 20.--22. "PRI29,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED," "0,1" newline bitfld.long 0x0C 16.--18. "PRI28,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 15. "RESERVED," "0,1" newline bitfld.long 0x0C 12.--14. "PRI27,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 11. "RESERVED," "0,1" newline bitfld.long 0x0C 8.--10. "PRI26,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED," "0,1" newline bitfld.long 0x0C 4.--6. "PRI25,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 0.--2. "PRI24,Priority" "0,1,2,3,4,5,6,7" line.long 0x10 "P2_RX_DSCP_PRI_MAP4,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 4" rbitfld.long 0x10 31. "RESERVED," "0,1" newline bitfld.long 0x10 28.--30. "PRI39,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED," "0,1" newline bitfld.long 0x10 24.--26. "PRI38,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED," "0,1" newline bitfld.long 0x10 20.--22. "PRI37,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "RESERVED," "0,1" newline bitfld.long 0x10 16.--18. "PRI36,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 15. "RESERVED," "0,1" newline bitfld.long 0x10 12.--14. "PRI35,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 11. "RESERVED," "0,1" newline bitfld.long 0x10 8.--10. "PRI34,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 7. "RESERVED," "0,1" newline bitfld.long 0x10 4.--6. "PRI33,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 3. "RESERVED," "0,1" newline bitfld.long 0x10 0.--2. "PRI32,Priority" "0,1,2,3,4,5,6,7" line.long 0x14 "P2_RX_DSCP_PRI_MAP5,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 5" rbitfld.long 0x14 31. "RESERVED," "0,1" newline bitfld.long 0x14 28.--30. "PRI47,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED," "0,1" newline bitfld.long 0x14 24.--26. "PRI46,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED," "0,1" newline bitfld.long 0x14 20.--22. "PRI45,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED," "0,1" newline bitfld.long 0x14 16.--18. "PRI44,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED," "0,1" newline bitfld.long 0x14 12.--14. "PRI43,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED," "0,1" newline bitfld.long 0x14 8.--10. "PRI42,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED," "0,1" newline bitfld.long 0x14 4.--6. "PRI41,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 0.--2. "PRI40,Priority" "0,1,2,3,4,5,6,7" line.long 0x18 "P2_RX_DSCP_PRI_MAP6,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 6" rbitfld.long 0x18 31. "RESERVED," "0,1" newline bitfld.long 0x18 28.--30. "PRI55,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED," "0,1" newline bitfld.long 0x18 24.--26. "PRI54,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED," "0,1" newline bitfld.long 0x18 20.--22. "PRI53,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED," "0,1" newline bitfld.long 0x18 16.--18. "PRI52,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED," "0,1" newline bitfld.long 0x18 12.--14. "PRI51,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED," "0,1" newline bitfld.long 0x18 8.--10. "PRI50,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED," "0,1" newline bitfld.long 0x18 4.--6. "PRI49,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED," "0,1" newline bitfld.long 0x18 0.--2. "PRI48,Priority" "0,1,2,3,4,5,6,7" line.long 0x1C "P2_RX_DSCP_PRI_MAP7,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 7" rbitfld.long 0x1C 31. "RESERVED," "0,1" newline bitfld.long 0x1C 28.--30. "PRI63,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 27. "RESERVED," "0,1" newline bitfld.long 0x1C 24.--26. "PRI62,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 23. "RESERVED," "0,1" newline bitfld.long 0x1C 20.--22. "PRI61,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 19. "RESERVED," "0,1" newline bitfld.long 0x1C 16.--18. "PRI60,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 15. "RESERVED," "0,1" newline bitfld.long 0x1C 12.--14. "PRI59,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 11. "RESERVED," "0,1" newline bitfld.long 0x1C 8.--10. "PRI58,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 7. "RESERVED," "0,1" newline bitfld.long 0x1C 4.--6. "PRI57,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 3. "RESERVED," "0,1" newline bitfld.long 0x1C 0.--2. "PRI56,Priority" "0,1,2,3,4,5,6,7" line.long 0x20 "P2_IDLE2LPI,Port 2 EEE Idle to LPI Counter Load Value Register" hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x20 0.--19. 1. "P2_IDLE2LPI,Port 2 EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted this value is loaded into the port 2 idle to LPI counter on each clock that the port 2 transmit is not idle" line.long 0x24 "P2_LPI2WAKE,Port 2 EEE LPI to Wake Counter Load Value Register" hexmask.long.word 0x24 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x24 0.--19. 1. "P2_LPI2WAKE,Port 2 EEE LPI to wake counter load value - When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted this value is loaded into the port 2 LPI to wake counter" width 0x0B tree.end tree "PRM_TARG" base ad:0x4AE08000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "PWMSS_CFG" base ad:0x4843E000 rgroup.long 0x00++0x0F line.long 0x00 "PWMSS_IDVER,IP Revision Register" line.long 0x04 "PWMSS_SYSCONFIG,This register controls the PWMSS local Idle mode clock management and software reset" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline rbitfld.long 0x04 1. "RESERVED," "0,1" bitfld.long 0x04 0. "SOFTRESET,Software reset" "Software reset is completed,Software reset assertion" line.long 0x08 "PWMSS_CLKCONFIG,The clock configuration register is used in the PWMSS for clkstop req and clk_en control to the ePWM/ eHRPWM. eCAP and eQEP submodules.Note: PWMSS Module Local Clock Gating feature is not supported" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "EPWM_CLKSTOP_REQ,This bit controls the clock stop input to the ePWM / eHRPWM module" "No effect,A request to stop.." newline bitfld.long 0x08 8. "EPWM_CLK_EN,This bit controls the interface clock enable (clk_en) input to the ePWM / eHRPWM module" "No effect,Enables the interface.." rbitfld.long 0x08 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 5. "EQEP_CLKSTOP_REQ,This bit controls the clock stop input to the eQEP module" "No effect,A request to stop.." bitfld.long 0x08 4. "EQEP_CLK_EN,This bit controls the interface clock enable (clk_en) input to the eQEP module" "No effect,Enables the interface.." newline rbitfld.long 0x08 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x08 1. "ECAP_CLKSTOP_REQ,This bit controls the clock stop input to the eCAP module" "No effect,A request to stop.." newline bitfld.long 0x08 0. "ECAP_CLK_EN,This bit controls the interface clock enable (clk_en) input to the eCAP module" "No effect,Enables the interface.." line.long 0x0C "PWMSS_CLKSTATUS,The clock status register is used in the PWMSS to indicate clock stop acknowledge (clkstop_ack) and clock enable (clk_en) acknowledge status for the ePWM/ eHRPWM. eCAP and eQEP submodules.Note:PWMSS Module Local Clock Gating feature is.." hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED," bitfld.long 0x0C 9. "EPWM_CLKSTOP_ACK,This bit is the clkstop_req_ack status output of the ePWM / eHRPWM module" "No interface clock stop acknowledged,Interface clock stop request is acknowledged for.." newline bitfld.long 0x0C 8. "EPWM_CLK_EN_ACK,This bit is the clk_en status output of the ePWM / eHRPWM module" "No clock enable request acknowledged,Interface clock enable request is acknowledged.." bitfld.long 0x0C 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 5. "EQEP_CLKSTOP_ACK,This bit is the clkstop_req_ack status output of the eQEP module" "No interface clock stop acknowledged,Interface clock stop request is acknowledged for.." bitfld.long 0x0C 4. "EQEP_CLK_EN_ACK,This bit is the clk_en status output of the eQEP module" "No clock enable request acknowledged,Interface clock enable request is acknowledged.." newline bitfld.long 0x0C 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x0C 1. "ECAP_CLKSTOP_ACK,TThis bit is the clkstop_req_ack status output of the eCAP module" "No interface clock stop acknowledged,Interface clock stop request is acknowledged for.." newline bitfld.long 0x0C 0. "ECAP_CLK_EN_ACK,TThis bit is the clk_en status output of the eCAP module" "No clock enable request acknowledged,Interface clock enable request is acknowledged.." width 0x0B tree.end tree "PWMSS_ECAP" base ad:0x4843E100 group.long 0x00++0x17 line.long 0x00 "PWMSS_ECAP_TSCNT,Time Stamp Counter Register" line.long 0x04 "PWMSS_ECAP_CNTPHS,Counter Phase Control Register" line.long 0x08 "PWMSS_ECAP_CAP1,Capture-1 Register" line.long 0x0C "PWMSS_ECAP_CAP2,Capture-2 Register" line.long 0x10 "PWMSS_ECAP_CAP3,Capture-3 Register" line.long 0x14 "PWMSS_ECAP_CAP4,Capture-4 Register" group.word 0x28++0x0B line.word 0x00 "PWMSS_ECAP_ECCTL1,ECAP Control Register1" bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Control" "TSCNT counter stops immediately on emulation..,TSCNT counter runs until = 0,TSCNT counter is unaffected by emulation suspend..,TSCNT counter is unaffected by emulation suspend.." bitfld.word 0x00 9.--13. "EVTFLTPS,Event Filter prescale select" "Divide by 1 (i.e . no prescale..,Divide by 2,Divide by 4,Divide by 6,Divide by 8,Divide by 10,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 60,Divide by 62" newline bitfld.word 0x00 8. "CAPLDEN,Enable Loading ofPWMSS_ECAP_CAP1 to PWMSS_ECAP_CAP4 registers on a capture event" "Disable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register..,Enable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register.." bitfld.word 0x00 7. "CTRRST4,Counter Reset on Capture Event 4" "Do not reset counter on Capture Event 4..,Reset counter after Capture Event 4 time-stamp.." newline bitfld.word 0x00 6. "CAP4POL,Capture Event 4 Polarity select" "Capture Event 4 triggered on a rising edge (RE),Capture Event 4 triggered on a falling edge (FE)" bitfld.word 0x00 5. "CTRRST3,Counter Reset on Capture Event 3" "Do not reset counter on Capture Event 3..,Reset counter after Event 3 time-stamp has been.." newline bitfld.word 0x00 4. "CAP3POL,Capture Event 3 Polarity select" "Capture Event 3 triggered on a rising edge (RE),Capture Event 3 triggered on a falling edge (FE)" bitfld.word 0x00 3. "CTRRST2,Counter Reset on Capture Event 2" "Do not reset counter on Capture Event 2..,Reset counter after Event 2 time-stamp has been.." newline bitfld.word 0x00 2. "CAP2POL,Capture Event 2 Polarity select" "Capture Event 2 triggered on a rising edge (RE),Capture Event 2 triggered on a falling edge (FE)" bitfld.word 0x00 1. "CTRRST1,Counter Reset on Capture Event 1" "Do not reset counter on Capture Event 1..,Reset counter after Event 1 time-stamp has been.." newline bitfld.word 0x00 0. "CAP1POL,Capture Event 1 Polarity select" "Capture Event 1 triggered on a rising edge (RE),Capture Event 1 triggered on a falling edge (FE)" line.word 0x02 "PWMSS_ECAP_ECCTL2,ECAP Control Register 2" rbitfld.word 0x02 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 10. "APWMPOL,APWM output polarity select" "Output is active high (Compare value defines..,Output is active low (Compare value defines low.." newline bitfld.word 0x02 9. "CAPAPWM,CAP/APWM operating mode select" "0,1" bitfld.word 0x02 8. "SWSYNC,Software-forced Counter (TSCNT) Synchronizing" "Writing a zero has no effect,Writing a one forces a TSCNT shadow load of ECAP.." newline bitfld.word 0x02 6.--7. "SYNCO_SEL,Sync-Out Select" "Select sync-in event to be the sync-out signal..,Select TSCNT = PRD event to be the sync-out signal,Disable sync out signal,Disable sync out signal" bitfld.word 0x02 5. "SYNCI_EN,Counter (TSCNT) Sync-In select mode" "Disable sync-in option,Enable counter (TSCNT) to be loaded from" newline bitfld.word 0x02 4. "TSCNTSTP,Time Stamp (TSCNT) Counter Stop (freeze) Control" "TSCNT stopped,TSCNT free-running" bitfld.word 0x02 3. "REARMRESET,One-Shot Re-Arming Control that is wait for stop trigger" "Has no effect (reading always returns a 0),Arms the one-shot sequence as follows" newline bitfld.word 0x02 1.--2. "STOPVALUE,Stop value for one-shot mode" "Stop after Capture Event 1 in one-shot mode,Stop after Capture Event 2 in one-shot mode,Stop after Capture Event 3 in one-shot mode,Stop after Capture Event 4 in one-shot mode" bitfld.word 0x02 0. "CONTONESHT,Continuous or one-shot mode control (applicable only in capture mode)" "Operate in continuous mode,Operate in one-shot mode" line.word 0x04 "PWMSS_ECAP_ECEINT,ECAP Interrupt Enable Register" hexmask.word.byte 0x04 8.--15. 1. "RESERVED," bitfld.word 0x04 7. "CMPEQ,Counter Equal" "Disable Compare Equal as an Interrupt source,Enable Compare Equal as an Interrupt source" newline bitfld.word 0x04 6. "PRDEQ,Counter Equal" "Disable Period Equal as an Interrupt source,Enable Period Equal as an Interrupt source" bitfld.word 0x04 5. "CNTOVF,Counter Overflow Interrupt Enable" "Disable counter Overflow as an Interrupt source,Enable counter Overflow as an Interrupt source" newline bitfld.word 0x04 4. "CEVT4,Capture Event 4 Interrupt Enable" "Disable Capture Event 4 as an Interrupt source,Enable Capture Event 4 as an Interrupt source" bitfld.word 0x04 3. "CEVT3,Capture Event 3 Interrupt Enable" "Disable Capture Event 3 as an Interrupt source,Enable Capture Event 3 as an Interrupt source" newline bitfld.word 0x04 2. "CEVT2,Capture Event 2 Interrupt Enable" "Disable Capture Event 2 as an Interrupt source,Enable Capture Event 2 as an Interrupt source" bitfld.word 0x04 1. "CEVT1,Capture Event 1 Interrupt Enable" "Disable Capture Event 1 as an Interrupt source,Enable Capture Event 1 as an Interrupt source" newline rbitfld.word 0x04 0. "RESERVED," "0,1" line.word 0x06 "PWMSS_ECAP_ECFLG,ECAP Interrupt Flag Register" hexmask.word.byte 0x06 8.--15. 1. "RESERVED," bitfld.word 0x06 7. "CMPEQ,Compare Equal Compare Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) reached the.." newline bitfld.word 0x06 6. "PRDEQ,Counter Equal Period Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) reached the period.." bitfld.word 0x06 5. "CNTOVF,Counter Overflow Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) has made the.." newline bitfld.word 0x06 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode" "Indicates no event occurred,Indicates the fourth event occurred at ECAP pin" bitfld.word 0x06 3. "CEVT3,Capture Event 3 Status Flag" "Indicates no event occurred,Indicates the third event occurred at ECAP pin" newline bitfld.word 0x06 2. "CEVT2,Capture Event 2 Status Flag" "Indicates no event occurred,Indicates the second event occurred at ECAP pin" bitfld.word 0x06 1. "CEVT1,Capture Event 1 Status Flag" "Indicates no event occurred,Indicates the first event occurred at ECAP pin" newline bitfld.word 0x06 0. "INT,Global Interrupt Status Flag" "Indicates no interrupt generated,Indicates that an interrupt was generated" line.word 0x08 "PWMSS_ECAP_ECCLR,ECAP Interrupt Clear Register" hexmask.word.byte 0x08 8.--15. 1. "RESERVED," bitfld.word 0x08 7. "CMPEQ,Counter Equal Compare Status Flag" "Writing a 0 has no effect,Writing a 1 clears the TSCNT=CMP flag condition" newline bitfld.word 0x08 6. "PRDEQ,Counter Equal Period Status Flag" "Writing a 0 has no effect,Writing a 1 clears the TSCNT=PRD flag condition" bitfld.word 0x08 5. "CNTOVF,Counter Overflow Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CNTOVF flag condition" newline bitfld.word 0x08 4. "CEVT4,Capture Event 4 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT3 flag condition" bitfld.word 0x08 3. "CEVT3,Capture Event 3 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT3 flag condition" newline bitfld.word 0x08 2. "CEVT2,Capture Event 2 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT2 flag condition" bitfld.word 0x08 1. "CEVT1,Capture Event 1 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT1 flag condition" newline bitfld.word 0x08 0. "INT,Global Interrupt Clear Flag" "Writing a 0 has no effect,Writing a 1 clears the INT flag and enable.." line.word 0x0A "PWMSS_ECAP_ECFRC,ECAP Interrupt Forcing Register" hexmask.word.byte 0x0A 8.--15. 1. "RESERVED," bitfld.word 0x0A 7. "CMPEQ,Force Counter Equal Compare Interrupt" "No effect,Writing a 1 sets the TSCNT=CMP flag bit" newline bitfld.word 0x0A 6. "PRDEQ,Force Counter Equal Period Interrupt" "No effect,Writing a 1 sets the TSCNT=PRD flag bit" bitfld.word 0x0A 5. "CNTOVF,Force Counter Overflow" "No effect,Writing a 1 to this bit sets the CNTOVF flag bit" newline bitfld.word 0x0A 4. "CEVT4,Force Capture Event 4" "No effect,Writing a 1 sets the CEVT4 flag bit" bitfld.word 0x0A 3. "CEVT3,Force Capture Event 3" "No effect,Writing a 1 sets the CEVT3 flag bit" newline bitfld.word 0x0A 2. "CEVT2,Force Capture Event 2" "No effect,Writing a 1 sets the CEVT2 flag bit" bitfld.word 0x0A 1. "CEVT1,Always reads back a 0" "No effect,Writing a 1 sets the.." newline rbitfld.word 0x0A 0. "RESERVED," "0,1" rgroup.long 0x5C++0x03 line.long 0x00 "PWMSS_ECAP_PID,ECAP Revision ID" width 0x0B tree.end tree "PWMSS_EPWM" base ad:0x4843E200 group.word 0x00++0x0B line.word 0x00 "EPWM_TBCTL," bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Mode Bits" "Stop after the next time-base counter increment..,Stop when counter completes a whole cycle,Free run,Free run" bitfld.word 0x00 13. "PHSDIR,Phase Direction Bit" "Count down after the synchronization event,Count up after the synchronization event" newline bitfld.word 0x00 10.--12. "CLKDIV,Time-base Clock Prescale Bits" "/1..,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits" "/1,/2..,/4,/6,/8,/10,/12,/14" newline bitfld.word 0x00 6. "SWFSYNC,Software Forced Synchronization Pulse" "Writing a 0 has no effect and reads always..,Writing a 1 forces a one-time synchronization.." bitfld.word 0x00 4.--5. "SYNCOSEL,Synchronization Output Select" "Time-base counter equal to zero (,TBCNT =,TBCNT = CMPB,Disable EPWM_SYNCO signal" newline bitfld.word 0x00 3. "PRDLD,Active Period Register Load From Shadow Register Select" "The period register (,Load" bitfld.word 0x00 2. "PHSEN,Counter Register Load From Phase Register Enable" "Do not load the time-base counter (,Load the time-base counter with the phase.." newline bitfld.word 0x00 0.--1. "CTRMODE,Counter Mode" "Up-count mode,Down-count mode,Up-down-count mode,Stop-freeze counter operation (default on.." line.word 0x02 "EPWM_TBSTS," hexmask.word 0x02 3.--15. 1. "RESERVED," bitfld.word 0x02 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "Reading a 0 indicates the time-base counter..,Reading a 1 on this bit indicates that the.." newline bitfld.word 0x02 1. "SYNCI,Input Synchronization Latched Status Bit" "Writing a 0 will have no effect,Reading a 1 on this bit indicates that an.." bitfld.word 0x02 0. "CTRDIR,Time-Base Counter Direction Status Bit" "Time-Base Counter is currently counting down,Time-Base Counter is currently counting up" line.word 0x04 "HRPWM_TBPHSHR," hexmask.word.byte 0x04 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" hexmask.word.byte 0x04 0.--7. 1. "RESERVED," line.word 0x06 "EPWM_TBPHS," line.word 0x08 "EPWM_TBCNT," line.word 0x0A "EPWM_TBPRD," group.word 0x0E++0x17 line.word 0x00 "EPWM_CMPCTL," rbitfld.word 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 9. "SHDWBFULL,Counter-compare B ( 0x0 = CMPB shadow FIFO not full yet 0x1 = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value" "CMPB shadow FIFO not full yet,Indicates the CMPB shadow FIFO is full" newline bitfld.word 0x00 8. "SHDWAFULL,Counter-compare A ( 0x0 = CMPA shadow FIFO not full yet 0x1 = Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value" "CMPA shadow FIFO not full yet,Indicates the CMPA shadow FIFO is full a CPU.." rbitfld.word 0x00 7. "RESERVED," "0,1" newline bitfld.word 0x00 6. "SHDWBMODE,Counter-compare B ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register.." "Shadow mode,Immediate mode" rbitfld.word 0x00 5. "RESERVED," "0,1" newline bitfld.word 0x00 4. "SHDWAMODE,Counter-compare A ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register .." "Shadow mode,Immediate mode" bitfld.word 0x00 2.--3. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode" "Time-base counter equal to zero (,Load on TBCNT = PRD,Load on either TBCNT = 0 or TBCNT = PRD,Freeze (no loads possible)" newline bitfld.word 0x00 0.--1. "LOADAMODE,Active Counter-Compare A ( 0x0 = Load on TBCNT = 0: Time-base counter equal to zero ( 0x1 = Load on TBCNT = PRD: Time-base counter equal to period ( 0x2 = Load on either TBCNT = 0 or TBCNT = PRD 0x3 = Freeze (no loads possible)" "Time-base counter equal to zero (,Load on TBCNT = PRD,Load on either TBCNT = 0 or TBCNT = PRD,Freeze (no loads possible)" line.word 0x02 "HRPWM_CMPAHR," hexmask.word.byte 0x02 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control" hexmask.word.byte 0x02 0.--7. 1. "RESERVED," line.word 0x04 "EPWM_CMPA," line.word 0x06 "EPWM_CMPB," line.word 0x08 "EPWM_AQCTLA," rbitfld.word 0x08 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x08 10.--11. "CBD,Action when the time-base counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWM1A output" newline bitfld.word 0x08 8.--9. "CBU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWM1A output" bitfld.word 0x08 6.--7. "CAD,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWM1A output" newline bitfld.word 0x08 4.--5. "CAU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWM1A output" bitfld.word 0x08 2.--3. "PRD,Action when the counter equals the period" "Do nothing (action disabled),Clear,Set,Toggle EPWM1A output" newline bitfld.word 0x08 0.--1. "ZRO,Action when counter equals zero" "Do nothing (action disabled),Clear,Set,Toggle EPWM1A output" line.word 0x0A "EPWM_AQCTLB," rbitfld.word 0x0A 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0A 10.--11. "CBD,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWM1B output" newline bitfld.word 0x0A 8.--9. "CBU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWM1B output" bitfld.word 0x0A 6.--7. "CAD,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWM1B output" newline bitfld.word 0x0A 4.--5. "CAU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWM1B output" bitfld.word 0x0A 2.--3. "PRD,Action when the counter equals the period" "Do nothing (action disabled),Clear,Set,Toggle EPWM1B output" newline bitfld.word 0x0A 0.--1. "ZRO,Action when counter equals zero" "Do nothing (action disabled),Clear,Set,Toggle EPWM1B output" line.word 0x0C "EPWM_AQSFRC," hexmask.word.byte 0x0C 8.--15. 1. "RESERVED," bitfld.word 0x0C 6.--7. "RLDCSF," "?,Load on event counter equals period,Load on event counter equals zero or counter..,Load immediately (the active register is.." newline bitfld.word 0x0C 5. "OTSFB,One-Time Software Forced Event on Output B" "Writing a 0 (zero) has no effect,Initiates a single s/w forced event" bitfld.word 0x0C 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "Does nothing (action disabled),Clear (low),Set (high),Toggle (Low -> High High -> Low)" newline bitfld.word 0x0C 2. "OTSFA,One-Time Software Forced Event on Output A" "Writing a 0 (zero) has no effect,Initiates a single software forced event" bitfld.word 0x0C 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "Does nothing (action disabled),Clear (low),Set (high),Toggle (Low -> High High -> Low)" line.word 0x0E "EPWM_AQCSFRC," hexmask.word 0x0E 4.--15. 1. "RESERVED," bitfld.word 0x0E 2.--3. "CSFB,Continuous Software Force on Output B" "Forcing disabled that is has no effect,Forces a continuous low on output B,Forces a continuous high on output B,Software forcing is disabled and has no effect" newline bitfld.word 0x0E 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "Forcing disabled that is has no effect,Forces a continuous low on output A,Forces a continuous high on output A,Software forcing is disabled and has no effect" line.word 0x10 "EPWM_DBCTL," hexmask.word 0x10 6.--15. 1. "RESERVED," bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control" "EPWM1A In (from the action-qualifier) is the..,EPWM1B In (from the action-qualifier) is the..,EPWM1A In (from the action-qualifier) is the..,EPWM1B In (from the action-qualifier) is the.." newline bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control" "Active high (AH) mode,Active low complementary (ALC) mode,Active high complementary (AHC),Active low (AL) mode" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control" "Dead-band generation is bypassed for both output..,Disable rising-edge delay,Disable falling-edge delay,Dead-band is fully enabled for both rising-edge.." line.word 0x12 "EPWM_DBRED," rbitfld.word 0x12 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count" line.word 0x14 "EPWM_DBFED," rbitfld.word 0x14 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count" line.word 0x16 "EPWM_TZSEL," abitfld.word 0x16 8.--15. "OSHTN,Trip-zone n (TZn) select" "0x00=Disable TZn as a one-shot trip source for..,0x01=Enable TZn as a one-shot trip source for.." hexmask.word.byte 0x16 1.--7. 1. "RESERVED," newline bitfld.word 0x16 0. "CBC0,Trip-zone 0 (TZ0) select" "Disable TZ0 as a CBC trip source for this ePWM..,Enable TZ0 as a CBC trip source for this ePWM.." group.word 0x28++0x15 line.word 0x00 "EPWM_TZCTL," hexmask.word 0x00 4.--15. 1. "RESERVED," bitfld.word 0x00 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWM1B" "High impedance (EPWM1B = High-impedance state),Force EPWM1B to a high state,Force EPWM1B to a low state,Do nothing no action is taken on EPWM1B" newline bitfld.word 0x00 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWM1A" "High impedance (EPWM1A = High-impedance state),Force EPWM1A to a high state,Force EPWM1A to a low state,Do nothing no action is taken on EPWM1A" line.word 0x02 "EPWM_TZEINT," hexmask.word 0x02 3.--15. 1. "RESERVED," bitfld.word 0x02 2. "OST,Trip-zone One-Shot Interrupt Enable" "Disable one-shot interrupt generation,Enable Interrupt generation; a one-shot trip.." newline bitfld.word 0x02 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disable cycle-by-cycle interrupt generation,Enable interrupt generation; a cycle-by-cycle.." rbitfld.word 0x02 0. "RESERVED," "0,1" line.word 0x04 "EPWM_TZFLG," hexmask.word 0x04 3.--15. 1. "RESERVED," bitfld.word 0x04 2. "OST,Latched Status Flag for A One-Shot Trip Event" "No one-shot trip event has occurred,Indicates a trip event has occurred on a pin.." newline bitfld.word 0x04 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "No cycle-by-cycle trip event has occurred,Indicates a trip event has occurred on a pin.." bitfld.word 0x04 0. "INT,Latched Trip Interrupt Status Flag" "Indicates no interrupt has been generated,Indicates an ePWM0_TZINT interrupt was generated.." line.word 0x06 "EPWM_TZCLR," hexmask.word 0x06 3.--15. 1. "RESERVED," bitfld.word 0x06 2. "OST,Clear Flag for One-Shot Trip (OST) Latch" "Has no effect,Clears this Trip (set) condition" newline bitfld.word 0x06 1. "CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "Has no effect,Clears this Trip (set) condition" bitfld.word 0x06 0. "INT,Global Interrupt Clear Flag" "Has no effect,Clears the trip-interrupt flag for this ePWM.." line.word 0x08 "EPWM_TZFRC," hexmask.word 0x08 3.--15. 1. "RESERVED," bitfld.word 0x08 2. "OST,Force a One-Shot Trip Event via Software" "Writing of 0 is ignored,Forces a one-shot trip event and sets" newline bitfld.word 0x08 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "Writing of 0 is ignored,Forces a cycle-by-cycle trip event and sets" rbitfld.word 0x08 0. "RESERVED," "0,1" line.word 0x0A "EPWM_ETSEL," hexmask.word 0x0A 4.--15. 1. "RESERVED," bitfld.word 0x0A 3. "INTEN,Enable ePWM Interrupt (ePWM0INT) Generation" "Disable ePWM0INT generation,Enable ePWM0INT generation" newline bitfld.word 0x0A 0.--2. "INTSEL,ePWM Interrupt (ePWM0INT) Selection Options" "Reserved,Enable event time-base counter equal to zero,Enable event time-base counter equal to period..,Reserved,Enable event time-base counter equal to CMPA..,Enable event time-base counter equal to CMPA..,Enable event,Enable event" line.word 0x0C "EPWM_ETPS," hexmask.word 0x0C 4.--15. 1. "RESERVED," bitfld.word 0x0C 2.--3. "INTCNT,ePWM Interrupt Event (ePWM0INT) Counter Register" "No events have occurred,1 event has occurred,2 events have occurred,3 events have occurred" newline bitfld.word 0x0C 0.--1. "INTPRD,ePWM Interrupt (ePWM0INT) Period Select" "Disable the interrupt event counter,Generate an interrupt on the first event INTCNT..,Generate interrupt on,Generate interrupt on" line.word 0x0E "EPWM_ETFLG," hexmask.word 0x0E 1.--15. 1. "RESERVED," bitfld.word 0x0E 0. "INT,Latched ePWM Interrupt (EPWM_INT) Status Flag" "Indicates no event occurred,Indicates that an ePWM interrupt (EWPM_INT) was.." line.word 0x10 "EPWM_ETCLR," hexmask.word 0x10 1.--15. 1. "RESERVED," bitfld.word 0x10 0. "INT,ePWM Interrupt (ePWM0INT) Flag Clear Bit" "Writing a 0 has no effect,Writing 1 clears" line.word 0x12 "EPWM_ETFRC," hexmask.word 0x12 1.--15. 1. "RESERVED," bitfld.word 0x12 0. "INT,INT Force Bit" "Writing 0 to this bit will be ignored,Writing 1 generates an interrupt on ePWM0INT and.." line.word 0x14 "EPWM_PCCTL," rbitfld.word 0x14 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x14 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "Duty = 1/8 (12.5%),Duty = 2/8 (25.0%),Duty = 3/8 (37.5%),Duty = 4/8 (50.0%),Duty = 5/8 (62.5%),Duty = 6/8 (75.0%),Duty = 7/8 (87.5%),Reserved" newline bitfld.word 0x14 5.--7. "CHPFREQ,Chopping Clock Frequency" "Divide by 1 (no prescale),Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7,Divide by 8" bitfld.word 0x14 1.--4. "OSHTWTH,One-Shot Pulse Width" "?,SYSCLKOUT/8 wide,SYSCLKOUT/8 wide,SYSCLKOUT/8 wide,SYSCLKOUT/8 wide,?..." newline bitfld.word 0x14 0. "CHPEN,PWM-chopping Enable" "Disable (bypass) PWM chopping function,Enable chopping function" group.word 0xC0++0x01 line.word 0x00 "HRPWM_HRCTL," hexmask.word 0x00 4.--15. 1. "RESERVED," bitfld.word 0x00 3. "PULSESEL,Pulse select bits" "Select CNT_zero pulse,Select PRD_eq pulse" newline bitfld.word 0x00 2. "DELBUSSEL,Delay Bus Select Bit: Selects which bus is used to select the delay for the PWM pulse" "Select CMPAHR(8) bus from compare module of EPWM..,Select TBPHSHR(8) bus from time base module" bitfld.word 0x00 0.--1. "DELMODE,Delay Mode Bits: Selects which edge of the PWM pulse the delay is inserted" "No delay inserted (default on reset),Delay inserted rising edge,Delay inserted falling edge,Delay inserted on both edges" width 0x0B tree.end tree "PWMSS_EQEP" base ad:0x4843E180 group.long 0x00++0x23 line.long 0x00 "EQEP_QPOSCNT," line.long 0x04 "EQEP_QPOSINIT," line.long 0x08 "EQEP_QPOSMAX," line.long 0x0C "EQEP_QPOSCMP," line.long 0x10 "EQEP_QPOSILAT," line.long 0x14 "EQEP_QPOSSLAT," line.long 0x18 "EQEP_QPOSLAT," line.long 0x1C "EQEP_QUTMR," line.long 0x20 "EQEP_QUPRD," group.word 0x24++0x1D line.word 0x00 "EQEP_QWDTMR," line.word 0x02 "EQEP_QWDPRD," line.word 0x04 "EQEP_QDECCTL," bitfld.word 0x04 14.--15. "QSRC,Position-counter source selection" "Quadrature count mode (QCLK = iCLK QDIR = iDIR),Direction-count mode (QCLK = xCLK QDIR = xDIR),UP count mode for frequency measurement (QCLK =..,DOWN count mode for frequency measurement (QCLK.." bitfld.word 0x04 13. "SOEN,Sync output-enable" "Disable position-compare sync output,Enable position-compare sync output" newline bitfld.word 0x04 12. "SPSEL,Sync output pin selection" "Index pin is used for sync output,Strobe pin is used for sync output" bitfld.word 0x04 11. "XCR,External clock rate" "2x resolution,1x resolution" newline bitfld.word 0x04 10. "SWAP,Swap quadrature clock inputs" "Quadrature-clock inputs are not swapped,Quadrature-clock inputs are swapped" bitfld.word 0x04 9. "IGATE,Index pulse gating option" "Disable gating of Index pulse,Gate the index pin with strobe" newline bitfld.word 0x04 8. "QAP,QEPA input polarity" "No effect,Negates QEPA input" bitfld.word 0x04 7. "QBP,QEPB input polarity" "No effect,Negates QEPB input" newline bitfld.word 0x04 6. "QIP,QEPI input polarity" "No effect,Negates QEPI input" bitfld.word 0x04 5. "QSP,QEPS input polarity" "No effect,Negates QEPS input" newline rbitfld.word 0x04 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x06 "EQEP_QEPCTL," bitfld.word 0x06 14.--15. "FREE_SOFT,Emulation Control Bits" "x stops immediately,x continues to count until the rollover,x is unaffected by emulation suspend,x is unaffected by emulation suspend" bitfld.word 0x06 12.--13. "PCRM,Position counter reset mode" "Position counter reset on an index event,Position counter reset on the maximum position,Position counter reset on the first index event,Position counter reset on a unit time event" newline bitfld.word 0x06 10.--11. "SEI,Strobe event initialization of position counter" "Does nothing (action disabled),Does nothing (action disabled),Initializes the position counter on rising edge..,Clockwise Direction" bitfld.word 0x06 8.--9. "IEI,Index event initialization of position counter" "Do nothing (action disabled),Do nothing (action disabled),Initializes the position counter on the rising..,Initializes the position counter on the falling.." newline bitfld.word 0x06 7. "SWI,Software initialization of position counter" "Do nothing (action disabled),Initialize position counter this bit is cleared.." bitfld.word 0x06 6. "SEL,Strobe event latch of position counter" "The position counter is latched on the rising..,Clockwise Direction" newline bitfld.word 0x06 4.--5. "IEL,Index event latch of position counter (software index marker)" "Reserved,Latches position counter on rising edge of the..,Latches position counter on falling edge of the..,Software index marker" bitfld.word 0x06 3. "PHEN,Quadrature position counter enable/software reset" "Reset the eQEP peripheral internal operating..,eQEP position counter is enabled" newline bitfld.word 0x06 2. "QCLM,eQEP capture latch mode" "Latch on position counter read by CPU,Latch on unit time out" bitfld.word 0x06 1. "UTE,eQEP unit timer enable" "Disable eQEP unit timer,Enable unit timer" newline bitfld.word 0x06 0. "WDE,eQEP watchdog enable" "Disable the eQEP watchdog timer,Enable the eQEP watchdog timer" line.word 0x08 "EQEP_QCAPCTL," bitfld.word 0x08 15. "CEN,Enable eQEP capture" "eQEP capture unit is disabled,eQEP capture unit is enabled" hexmask.word.byte 0x08 7.--14. 1. "RESERVED," newline bitfld.word 0x08 4.--6. "CCPS,eQEP capture timer clock prescaler" "CAPCLK = SYSCLKOUT/1,CAPCLK = SYSCLKOUT/2,CAPCLK = SYSCLKOUT/4,CAPCLK = SYSCLKOUT/8,CAPCLK = SYSCLKOUT/16,CAPCLK = SYSCLKOUT/32,CAPCLK = SYSCLKOUT/64,CAPCLK = SYSCLKOUT/128" bitfld.word 0x08 0.--3. "UPPS,Unit position event prescaler" "UPEVNT = QCLK/1,UPEVNT = QCLK/2,UPEVNT = QCLK/4,UPEVNT = QCLK/8,UPEVNT = QCLK/16,UPEVNT = QCLK/32,UPEVNT = QCLK/64,UPEVNT = QCLK/128,UPEVNT = QCLK/256,UPEVNT = QCLK/512,UPEVNT = QCLK/1024,UPEVNT = QCLK/2048,Reserved,Reserved,Reserved,Reserved" line.word 0x0A "EQEP_QPOSCTL," bitfld.word 0x0A 15. "PCSHDW,Position-compare shadow enable" "Shadow disabled load Immediate,Shadow enabled" bitfld.word 0x0A 14. "PCLOAD,Position-compare shadow load mode" "Load on QPOSCNT = 0,Load when QPOSCNT = QPOSCMP" newline bitfld.word 0x0A 13. "PCPOL,Polarity of sync output" "Active HIGH pulse output,Active LOW pulse output" bitfld.word 0x0A 12. "PCE,Position-compare enable/disable" "Disable position compare unit,Enable position compare unit" newline abitfld.word 0x0A 0.--11. "PCSPW,Select-position-compare sync output pulse width" "0x000=1 x 4 x SYSCLKOUT cycles,0x001=2 x 4 x SYSCLKOUT cycles,0x002=3 x 4 x SYSCLKOUT cycles to 4096 x 4 x..,0xFFF=3 x 4 x SYSCLKOUT cycles to 4096 x 4 x.." line.word 0x0C "EQEP_QEINT," rbitfld.word 0x0C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0C 11. "UTO,Unit time out interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 10. "IEL,Index event latch interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 9. "SEL,Strobe event latch interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 8. "PCM,Position-compare match interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 7. "PCR,Position-compare ready interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 6. "PCO,Position counter overflow interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 5. "PCU,Position counter underflow interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 4. "WTO,Watchdog time out interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 3. "QDC,Quadrature direction change interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 2. "PHE,Quadrature phase error interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 1. "PCE,Position counter error interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline rbitfld.word 0x0C 0. "RESERVED," "0,1" line.word 0x0E "EQEP_QFLG," bitfld.word 0x0E 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0E 11. "UTO,Unit time out interrupt flag" "No interrupt generated,Set by eQEP unit timer period match" newline bitfld.word 0x0E 10. "IEL,Index event latch interrupt flag" "No interrupt generated,This bit is set after latching the QPOSCNT to.." bitfld.word 0x0E 9. "SEL,Strobe event latch interrupt flag" "No interrupt generated,This bit is set after latching the QPOSCNT to" newline bitfld.word 0x0E 8. "PCM,eQEP compare match event interrupt flag" "No interrupt generated,This bit is set on position-compare match" bitfld.word 0x0E 7. "PCR,Position-compare ready interrupt flag" "No interrupt generated,This bit is set after transferring the shadow.." newline bitfld.word 0x0E 6. "PCO,Position counter overflow interrupt flag" "No interrupt generated,This bit is set on position counter overflow" bitfld.word 0x0E 5. "PCU,Position counter underflow interrupt flag" "No interrupt generated,This bit is set on position counter underflow" newline bitfld.word 0x0E 4. "WTO,Watchdog timeout interrupt flag" "No interrupt generated,Set by watch dog timeout" bitfld.word 0x0E 3. "QDC,Quadrature direction change interrupt flag" "No interrupt generated,This bit is set during change of direction" newline bitfld.word 0x0E 2. "PHE,Quadrature phase error interrupt flag" "No interrupt generated,Set on simultaneous transition of QEPA and QEPB" bitfld.word 0x0E 1. "PCE,Position counter error interrupt flag" "No interrupt generated,Position counter error" newline bitfld.word 0x0E 0. "INT,Global interrupt status flag" "No interrupt generated,Interrupt was generated" line.word 0x10 "EQEP_QCLR," rbitfld.word 0x10 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x10 11. "UTO,Clear unit time out interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 10. "IEL,Clear index event latch interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 9. "SEL,Clear strobe event latch interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 8. "PCM,Clear eQEP compare match event interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 7. "PCR,Clear position-compare ready interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 6. "PCO,Clear position counter overflow interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 5. "PCU,Clear position counter underflow interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 4. "WTO,Clear watchdog timeout interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 3. "QDC,Clear quadrature direction change interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 2. "PHE,Clear quadrature phase error interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 1. "PCE,Clear position counter error interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 0. "INT,Global interrupt clear flag" "No effect,Clears the interrupt flag.." line.word 0x12 "EQEP_QFRC," rbitfld.word 0x12 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x12 11. "UTO,Force unit time out interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 10. "IEL,Force index event latch interrupt" "No effect,Force the interrupt" bitfld.word 0x12 9. "SEL,Force strobe event latch interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 8. "PCM,Force position-compare match interrupt" "No effect,Force the interrupt" bitfld.word 0x12 7. "PCR,Force position-compare ready interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 6. "PCO,Force position counter overflow interrupt" "No effect,Force the interrupt" bitfld.word 0x12 5. "PCU,Force position counter underflow interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 4. "WTO,Force watchdog time out interrupt" "No effect,Force the interrupt" bitfld.word 0x12 3. "QDC,Force quadrature direction change interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 2. "PHE,Force quadrature phase error interrupt" "No effect,Force the interrupt" bitfld.word 0x12 1. "PCE,Force position counter error interrupt" "No effect,Force the interrupt" newline rbitfld.word 0x12 0. "RESERVED," "0,1" line.word 0x14 "EQEP_QEPSTS," hexmask.word.byte 0x14 8.--15. 1. "RESERVED," bitfld.word 0x14 7. "UPEVNT,Unit position event flag" "No unit position event detected,Unit position event detected" newline bitfld.word 0x14 6. "FDF,Direction on the first index marker" "Counter-clockwise rotation (or reverse movement)..,Clockwise rotation (or forward movement) on the.." bitfld.word 0x14 5. "QDF,Quadrature direction flag" "Counter-clockwise rotation (or reverse movement),Clockwise rotation (or forward movement)" newline bitfld.word 0x14 4. "QDLF,eQEP direction latch flag" "Counter-clockwise rotation (or reverse movement)..,Clockwise rotation (or forward movement) on.." bitfld.word 0x14 3. "COEF,Capture overflow error flag" "Sticky bit cleared by writing 1,Overflow occurred in eQEP Capture timer (QEPCTMR)" newline bitfld.word 0x14 2. "CDEF,Capture direction error flag" "Sticky bit cleared by writing 1,Direction change occurred between the capture.." bitfld.word 0x14 1. "FIMF,First index marker flag" "Sticky bit cleared by writing 1,Set by first occurrence of index pulse" newline bitfld.word 0x14 0. "PCEF,Position counter error flag" "No error occurred during the last index transition,Position counter error" line.word 0x16 "EQEP_QCTMR," line.word 0x18 "EQEP_QCPRD," line.word 0x1A "EQEP_QCTMRLAT," line.word 0x1C "EQEP_QCPRDLAT," rgroup.long 0x5C++0x03 line.long 0x00 "EQEP_REVID," width 0x0B tree.end tree "PWMSS_TARG" base ad:0x4843F000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "QSPI" base ad:0x4B300000 rgroup.long 0x00++0x03 line.long 0x00 "QSPI_PID,Revision register" group.long 0x10++0x03 line.long 0x00 "QSPI_SYSCONFIG," hexmask.long 0x00 4.--31. 1. "RESERVED," bitfld.long 0x00 2.--3. "IDLE_MODE,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Reserved" newline rbitfld.long 0x00 0.--1. "RESERVED," "0,1,2,3" group.long 0x20++0x13 line.long 0x00 "QSPI_INTR_STATUS_RAW_SET,This register contains raw interrupt status flags" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "WIRQ_RAW,Word Interrupt Status" "WIRQ_RAW_0,WIRQ_RAW_1" newline bitfld.long 0x00 0. "FIRQ_RAW,Frame Interrupt Status" "FIRQ_RAW_0,FIRQ_RAW_1" line.long 0x04 "QSPI_INTR_STATUS_ENABLED_CLEAR,This register contains status flags of the enabled interrupts" hexmask.long 0x04 2.--31. 1. "RESERVED," bitfld.long 0x04 1. "WIRQ_ENA,Word Interrupt Enabled Status" "WIRQ_ENA_0,WIRQ_ENA_1" newline bitfld.long 0x04 0. "FIRQ_ENA,Frame Interrupt Enabled Status" "FIRQ_ENA_0,FIRQ_ENA_1" line.long 0x08 "QSPI_INTR_ENABLE_SET_REG,This register enables the interrupts" hexmask.long 0x08 2.--31. 1. "RESERVED," bitfld.long 0x08 1. "WIRQ_ENA_SET,Word interrupt enable.Read" "WIRQ_ENA_SET_0,WIRQ_ENA_SET_1" newline bitfld.long 0x08 0. "FIRQ_ENA_SET,Frame interrupt enable.Read" "FIRQ_ENA_SET_0,FIRQ_ENA_SET_1" line.long 0x0C "QSPI_INTR_ENABLE_CLEAR_REG,This register disables the interrupts" hexmask.long 0x0C 2.--31. 1. "RESERVED," bitfld.long 0x0C 1. "WIRQ_ENA_CLR,Word interrupt disable.Read" "WIRQ_ENA_CLR_0,WIRQ_ENA_CLR_1" newline bitfld.long 0x0C 0. "FIRQ_ENA_CLR,Frame interrupt disable.Read" "FIRQ_ENA_CLR_0,FIRQ_ENA_CLR_1" line.long 0x10 "QSPI_INTC_EOI_REG,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" group.long 0x40++0x33 line.long 0x00 "QSPI_SPI_CLOCK_CNTRL_REG,This register controls the external SPI clock generation" bitfld.long 0x00 31. "CLKEN,External SPI clock (qspi1_sclk) enable" "CLKEN_0,CLKEN_1" hexmask.long.word 0x00 16.--30. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "DCLK_DIV,Divide ratio for the external SPI clock (qspi1_sclk)" line.long 0x04 "QSPI_SPI_DC_REG,This register controls the different modes for each output chip select" rbitfld.long 0x04 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. "DD3,Data delay for chip select 3" "Data is output on the same cycle as the..,Data is output 1 qspi1_sclk cycle after the..,Data is output 2 qspi1_sclk cycles after the..,Data is output 3 qspi1_sclk cycles after the.." newline bitfld.long 0x04 26. "CKPH3,Clock phase for chip select 3" "Data shifted out on rising edge; input on,Data shifted out on falling edge; input on" bitfld.long 0x04 25. "CSP3,Chip select polarity for chip select 3" "CSP3_0,CSP3_1" newline bitfld.long 0x04 24. "CKP3,Clock polarity for chip select 3" "CKP3_0,CKP3_1" rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 19.--20. "DD2,Data delay for chip select 2" "Data is output on the same cycle as the..,Data is output 1 qspi1_sclk cycle after the..,Data is output 2 qspi1_sclk cycles after the..,Data is output 3 qspi1_sclk cycles after the.." bitfld.long 0x04 18. "CKPH2,Clock phase for chip select 2" "Data shifted out on rising edge; input on,Data shifted out on falling edge; input on" newline bitfld.long 0x04 17. "CSP2,Chip select polarity for chip select 2" "CSP2_0,CSP2_1" bitfld.long 0x04 16. "CKP2,Clock polarity for chip select 2" "CKP2_0,CKP2_1" newline rbitfld.long 0x04 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 11.--12. "DD1,Data delay for chip select 1" "Data is output on the same cycle as the..,Data is output 1 qspi1_sclk cycle after the..,Data is output 2 qspi1_sclk cycles after the..,Data is output 3 qspi1_sclk cycles after the.." newline bitfld.long 0x04 10. "CKPH1,Clock phase for chip select 1" "Data shifted out on rising edge; input on,Data shifted out on falling edge; input on" bitfld.long 0x04 9. "CSP1,Chip select polarity for chip select 1" "CSP1_0,CSP1_1" newline bitfld.long 0x04 8. "CKP1,Clock polarity for chip select 1" "CKP1_0,CKP1_1" rbitfld.long 0x04 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 3.--4. "DD0,Data delay for chip select 0" "Data is output on the same cycle as the..,Data is output 1 qspi1_sclk cycle after the..,Data is output 2 qspi1_sclk cycles after the..,Data is output 3 qspi1_sclk cycles after the.." bitfld.long 0x04 2. "CKPH0,Clock phase for chip select 0" "Data shifted out on rising edge; input on,Data shifted out on falling edge; input on" newline bitfld.long 0x04 1. "CSP0,Chip select polarity for chip select 0" "CSP0_0,CSP0_1" bitfld.long 0x04 0. "CKP0,Clock polarity for chip select 0" "CKP0_0,CKP0_1" line.long 0x08 "QSPI_SPI_CMD_REG,This register sets up the SPI command" rbitfld.long 0x08 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x08 28.--29. "CSNUM,Device select" "Chip Select 0 active,Chip Select 1 active,Chip Select 2 active,Chip Select 3 active" newline rbitfld.long 0x08 26.--27. "RESERVED," "0,1,2,3" abitfld.long 0x08 19.--25. "WLEN,Word length" "0x00=1 bit,0x01=2 bits,0x7F=128 bits" newline bitfld.long 0x08 16.--18. "CMD,Transfer command" "Reserved,4-pin Read Single,4-pin Write Single,4-pin Read Dual,Reserved,3-pin Read Single,3-pin Write Single,6-pin Read Quad" bitfld.long 0x08 15. "FIRQ,Frame complete interrupt enable" "FIRQ_0,FIRQ_1" newline bitfld.long 0x08 14. "WIRQ,Word complete interrupt enable" "WIRQ_0,WIRQ_1" rbitfld.long 0x08 12.--13. "RESERVED," "0,1,2,3" newline abitfld.long 0x08 0.--11. "FLEN,Frame Length" "0x000=1 word,0x001=2 words,0xFFF=4096 words" line.long 0x0C "QSPI_SPI_STATUS_REG,This register contains indicators to allow the user to monitor the progression of a frame transfer" bitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0C 16.--27. 1. "WDCNT,Word count" newline hexmask.long.word 0x0C 3.--15. 1. "RESERVED," bitfld.long 0x0C 2. "FC,Frame complete" "FC_0,FC_1" newline bitfld.long 0x0C 1. "WC,Word complete" "WC_0,WC_1" bitfld.long 0x0C 0. "BUSY,Busy bit" "BUSY_0,BUSY_1" line.long 0x10 "QSPI_SPI_DATA_REG,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left" line.long 0x14 "QSPI_SPI_SETUP0_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 0 output)" rbitfld.long 0x14 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.byte 0x14 16.--23. 1. "WCMD,Write command" rbitfld.long 0x14 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command" "Normal read (all data input on qspi1_d[1]),Dual read (odd bytes input on qspi1_d[1]; even..,Normal read (all data input on qspi1_d[1]),Quad read (uses also qspi1_d[2] and qspi1_d[3])" bitfld.long 0x14 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "No dummy bytes required,Use 8 bits,Use 16 bits,Use 24 bits" newline bitfld.long 0x14 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x14 0.--7. 1. "RCMD,Read Command" line.long 0x18 "QSPI_SPI_SETUP1_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 1 output)" rbitfld.long 0x18 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.byte 0x18 16.--23. 1. "WCMD,Write command" rbitfld.long 0x18 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x18 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command" "Normal read (all data input on qspi1_d[1]),Dual read (odd bytes input on qspi1_d[1]; even..,Normal read (all data input on qspi1_d[1]),Quad read (uses also qspi1_d[2] and qspi1_d[3])" bitfld.long 0x18 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "No dummy bytes required,Use 8 bits,Use 16 bits,Use 24 bits" newline bitfld.long 0x18 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x18 0.--7. 1. "RCMD,Read Command" line.long 0x1C "QSPI_SPI_SETUP2_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 2 output)" rbitfld.long 0x1C 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.byte 0x1C 16.--23. 1. "WCMD,Write command" rbitfld.long 0x1C 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x1C 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command" "Normal read (all data input on qspi1_d[1]),Dual read (odd bytes input on qspi1_d[1]; even..,Normal read (all data input on qspi1_d[1]),Quad read (uses also qspi1_d[2] and qspi1_d[3])" bitfld.long 0x1C 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "No dummy bytes required,Use 8 bits,Use 16 bits,Use 24 bits" newline bitfld.long 0x1C 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x1C 0.--7. 1. "RCMD,Read Command" line.long 0x20 "QSPI_SPI_SETUP3_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 3 output)" rbitfld.long 0x20 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x20 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.byte 0x20 16.--23. 1. "WCMD,Write command" rbitfld.long 0x20 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x20 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command" "Normal read (all data input on qspi1_d[1]),Dual read (odd bytes input on qspi1_d[1]; even..,Normal read (all data input on qspi1_d[1]),Quad read (uses also qspi1_d[2] and qspi1_d[3])" bitfld.long 0x20 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "No dummy bytes required,Use 8 bits,Use 16 bits,Use 24 bits" newline bitfld.long 0x20 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x20 0.--7. 1. "RCMD,Read Command" line.long 0x24 "QSPI_SPI_SWITCH_REG,This register allows initiators to switch control of the SPI core port between the configuration port and the SFI translator" hexmask.long 0x24 2.--31. 1. "RESERVED," bitfld.long 0x24 1. "MM_INT_EN,Memory mapped mode interrupt enable" "MM_INT_EN_0,MM_INT_EN_1" newline bitfld.long 0x24 0. "MMPT_S,MPT select" "MMPT_S_0,MMPT_S_1" line.long 0x28 "QSPI_SPI_DATA_REG_1,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left" line.long 0x2C "QSPI_SPI_DATA_REG_2,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left" line.long 0x30 "QSPI_SPI_DATA_REG_3,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left" width 0x0B tree.end tree "QSPI_FW" base ad:0x4A179000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" newline rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "QSPI_FW_CFG_TARG" base ad:0x4A17A000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "QSPI_TARG" base ad:0x44003900 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "RESTORE_CM_CORE" base ad:0x4A009E18 group.long 0x00++0x03 line.long 0x00 "CM_L3MAIN1_CLKSTCTRL_RESTORE,Second address map for register" group.long 0x08++0x03 line.long 0x00 "CM_L4CFG_CLKSTCTRL_RESTORE,Second address map for register" group.long 0x10++0x17 line.long 0x00 "CM_L4PER_CLKSTCTRL_RESTORE,Second address map for register" line.long 0x04 "CM_L3INIT_CLKSTCTRL_RESTORE,Second address map for register" line.long 0x08 "CM_L3INSTR_L3_MAIN_2_CLKCTRL_RESTORE,Second address map for register" line.long 0x0C "CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,Second address map for register" line.long 0x10 "CM_L3INSTR_OCP_WP_NOC_CLKCTRL_RESTORE,Second address map for register" line.long 0x14 "CM_CM_CORE_PROFILING_CLKCTRL_RESTORE,Second address map for register" group.long 0x30++0x03 line.long 0x00 "CM_L3MAIN1_DYNAMICDEP_RESTORE,Second address map for register" group.long 0x40++0x0B line.long 0x00 "CM_L4CFG_DYNAMICDEP_RESTORE,Second address map for register" line.long 0x04 "CM_L4PER_DYNAMICDEP_RESTORE,Second address map for register" line.long 0x08 "CM_COREAON_IO_SRCOMP_CLKCTRL_RESTORE,Second address map for register CM_COREAON_IO_SRCOMP_CLKCTRL" group.long 0x54++0x03 line.long 0x00 "CM_DMA_STATICDEP_RESTORE,Second address map for register CM_DMA_STATICDEP" width 0x0B tree.end tree "RESTORE_CM_CORE_AON" base ad:0x4A005E00 group.long 0x00++0x53 line.long 0x00 "CM_CLKSEL_CORE_RESTORE,Second address map for register" line.long 0x04 "CM_DIV_M2_DPLL_CORE_RESTORE,Second address map for register" line.long 0x08 "CM_DIV_M3_DPLL_CORE_RESTORE,Second address map for register CM_DIV_M3_DPLL_CORE" line.long 0x0C "CM_DIV_H11_DPLL_CORE_RESTORE,Second address map for register CM_DIV_H11_DPLL_CORE" line.long 0x10 "CM_DIV_H12_DPLL_CORE_RESTORE,Second address map for register" line.long 0x14 "CM_DIV_H13_DPLL_CORE_RESTORE,Second address map for register CM_DIV_H13_DPLL_CORE" line.long 0x18 "CM_DIV_H14_DPLL_CORE_RESTORE,Second address map for register" line.long 0x1C "CM_DIV_H21_DPLL_CORE_RESTORE,Second address map for register CM_DIV_H21_DPLL_CORE" line.long 0x20 "CM_DIV_H22_DPLL_CORE_RESTORE,Second address map for register" line.long 0x24 "CM_DIV_H23_DPLL_CORE_RESTORE,Second address map for register" line.long 0x28 "CM_DIV_H24_DPLL_CORE_RESTORE,Second address map for register" line.long 0x2C "CM_CLKSEL_DPLL_CORE_RESTORE,Second address map for register" line.long 0x30 "CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE,Second address map for register CM_SSC_DELTAMSTEP_DPLL_CORE" line.long 0x34 "CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,Second address map for register CM_SSC_MODFREQDIV_DPLL_CORE" line.long 0x38 "CM_CLKMODE_DPLL_CORE_RESTORE,Second address map for register" line.long 0x3C "CM_SHADOW_FREQ_CONFIG2_RESTORE,Second address map for register" line.long 0x40 "CM_SHADOW_FREQ_CONFIG1_RESTORE,Second address map for register" line.long 0x44 "CM_AUTOIDLE_DPLL_CORE_RESTORE,Second address map for register" line.long 0x48 "CM_MPU_CLKSTCTRL_RESTORE,Second address map for register CM_MPU_CLKSTCTRL" line.long 0x4C "CM_CM_CORE_AON_PROFILING_CLKCTRL_RESTORE,Second address map for register" line.long 0x50 "CM_DYN_DEP_PRESCAL_RESTORE,Second address map for register" width 0x0B tree.end tree "RTC_CM_CORE_AON" base ad:0x4A005740 group.long 0x00++0x07 line.long 0x00 "CM_RTC_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," rbitfld.long 0x00 10. "CLKACTIVITY_RTC_AUX_CLK,This field indicates the state of the RTC_AUX_CLK in the domain" "CLKACTIVITY_RTC_AUX_CLK_0,CLKACTIVITY_RTC_AUX_CLK_1" newline rbitfld.long 0x00 9. "RESERVED," "0,1" rbitfld.long 0x00 8. "CLKACTIVITY_RTC_L4_GICLK,This field indicates the state of the RTC_L4_GICLK clock in the domain" "CLKACTIVITY_RTC_L4_GICLK_0,CLKACTIVITY_RTC_L4_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the WKUPAON clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_RTC_RTCSS_CLKCTRL,This register manages the RTC clocks" hexmask.long.word 0x04 18.--31. 1. "RESERVED," rbitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x04 2.--15. 1. "RESERVED," bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "RTC_PRM" base ad:0x4AE07C60 group.long 0x00++0x07 line.long 0x00 "PM_RTC_RTCSS_WKDEP,This register controls wakeup dependency based on RTCSS service requests" hexmask.long.word 0x00 20.--31. 1. "RESERVED," bitfld.long 0x00 19. "WKUPDEP_RTC_IRQ2_EVE4,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_EVE4_0,WKUPDEP_RTC_IRQ2_EVE4_1" newline bitfld.long 0x00 18. "WKUPDEP_RTC_IRQ2_EVE3,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_EVE3_0,WKUPDEP_RTC_IRQ2_EVE3_1" bitfld.long 0x00 17. "WKUPDEP_RTC_IRQ2_EVE2,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_EVE2_0,WKUPDEP_RTC_IRQ2_EVE2_1" newline bitfld.long 0x00 16. "WKUPDEP_RTC_IRQ2_EVE1,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_EVE1_0,WKUPDEP_RTC_IRQ2_EVE1_1" bitfld.long 0x00 15. "WKUPDEP_RTC_IRQ2_DSP2,Wakeup dependency from RTCSS module (timer_swakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_DSP2_0,WKUPDEP_RTC_IRQ2_DSP2_1" newline bitfld.long 0x00 14. "WKUPDEP_RTC_IRQ2_IPU1,Wakeup dependency from RTCSS module (timer_swakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_IPU1_0,WKUPDEP_RTC_IRQ2_IPU1_1" rbitfld.long 0x00 13. "RESERVED," "0,1" newline bitfld.long 0x00 12. "WKUPDEP_RTC_IRQ2_DSP1,Wakeup dependency from RTCSS module (timer_swakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_DSP1_0,WKUPDEP_RTC_IRQ2_DSP1_1" bitfld.long 0x00 11. "WKUPDEP_RTC_IRQ2_IPU2,Wakeup dependency from RTCSS module (timer_swakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_IPU2_0,WKUPDEP_RTC_IRQ2_IPU2_1" newline bitfld.long 0x00 10. "WKUPDEP_RTC_IRQ2_MPU,Wakeup dependency from RTCSS module (timer_swakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_MPU_0,WKUPDEP_RTC_IRQ2_MPU_1" bitfld.long 0x00 9. "WKUPDEP_RTC_IRQ1_EVE4,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_EVE4_0,WKUPDEP_RTC_IRQ1_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_RTC_IRQ1_EVE3,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_EVE3_0,WKUPDEP_RTC_IRQ1_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_RTC_IRQ1_EVE2,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_EVE2_0,WKUPDEP_RTC_IRQ1_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_RTC_IRQ1_EVE1,Wakeup dependency from RTCSS module ( alarm_swakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_EVE1_0,WKUPDEP_RTC_IRQ1_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_RTC_IRQ1_DSP2,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_DSP2_0,WKUPDEP_RTC_IRQ1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_RTC_IRQ1_IPU1,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_IPU1_0,WKUPDEP_RTC_IRQ1_IPU1_1" rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_RTC_IRQ1_DSP1,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_DSP1_0,WKUPDEP_RTC_IRQ1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_RTC_IRQ1_IPU2,Wakeup dependency from RTCSS module ( alarm_swakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_IPU2_0,WKUPDEP_RTC_IRQ1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_RTC_IRQ1_MPU,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_MPU_0,WKUPDEP_RTC_IRQ1_MPU_1" line.long 0x04 "RM_RTC_RTCSS_CONTEXT,This register contains dedicated RTCSS context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end repeat 5. (list 1. 2. 3. 4. 5. )(list ad:0x4AE31000 ad:0x4AE33000 ad:0x4AE35000 ad:0x4AE37000 ad:0x4AE39000 ) tree "RTI$1" base $2 group.long 0x00++0x03 line.long 0x00 "RTIGCTRL," hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. "COS,Continue On Suspend" "stop counters in debug mode,continue counting in debug mode" hexmask.long.word 0x00 2.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "CNT1EN,Counter 1 Enable" "stop counters,start counters" bitfld.long 0x00 0. "CNT0EN,Counter 0 Enable" "stop counters,start counters" group.long 0x08++0x13 line.long 0x00 "RTICAPCTRL," hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "CAPCNTR1,Capture Counter 0" "0,1" newline bitfld.long 0x00 0. "CAPCNTR0,Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.." line.long 0x04 "RTICOMPCTRL," hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED," bitfld.long 0x04 12. "COMPSEL3,Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1" newline rbitfld.long 0x04 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 8. "COMPSEL2,Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1" newline rbitfld.long 0x04 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 4. "COMPSEL1,Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1" newline rbitfld.long 0x04 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. "COMPSEL0,Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1" line.long 0x08 "RTIFRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously" line.long 0x0C "RTIUC0," line.long 0x10 "RTICPUC0," rgroup.long 0x20++0x07 line.long 0x00 "RTICAFRC0," line.long 0x04 "RTICAUC0," group.long 0x30++0x0B line.long 0x00 "RTIFRC1," line.long 0x04 "RTIUC1," line.long 0x08 "RTICPUC1," rgroup.long 0x40++0x07 line.long 0x00 "RTICAFRC1," line.long 0x04 "RTICAUC1," group.long 0x50++0x1F line.long 0x00 "RTICOMP0," line.long 0x04 "RTIUDCP0," line.long 0x08 "RTICOMP1," line.long 0x0C "RTIUDCP1," line.long 0x10 "RTICOMP2," line.long 0x14 "RTIUDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches" line.long 0x18 "RTICOMP3," line.long 0x1C "RTIUDCP3," group.long 0x80++0x0B line.long 0x00 "RTISETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled" hexmask.long.word 0x00 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt" newline bitfld.long 0x00 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt" bitfld.long 0x00 16. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. "SETDMA3,Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request" newline bitfld.long 0x00 10. "SETDMA2,Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request" bitfld.long 0x00 9. "SETDMA1,Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request" newline bitfld.long 0x00 8. "SETDMA0,Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request" rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. "SETINT3,Set Compare Interrupt 3" "leaves the corresponding bit unchanged,enable interrupt" bitfld.long 0x00 2. "SETINT2,Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt" newline bitfld.long 0x00 1. "SETINT1,Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt" bitfld.long 0x00 0. "SETINT0,Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt" line.long 0x04 "RTICLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled" hexmask.long.word 0x04 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt" newline bitfld.long 0x04 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt" bitfld.long 0x04 16. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 11. "CLEARDMA3,Clear Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request" newline bitfld.long 0x04 10. "CLEARDMA2,Clear Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request" bitfld.long 0x04 9. "CLEARDMA1,Clear Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request" newline bitfld.long 0x04 8. "CLEARDMA0,Clear Compare DMA Request 0" "0,1" rbitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 3. "CLEARINT3,Clear Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt" bitfld.long 0x04 2. "CLEARINT2,Clear Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt" newline bitfld.long 0x04 1. "CLEARINT1,Clear Compare Interrupt 1" "0,1" bitfld.long 0x04 0. "CLEARINT0,Clear Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt" line.long 0x08 "RTIINTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not" hexmask.long.word 0x08 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0" newline bitfld.long 0x08 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0" bitfld.long 0x08 16. "RESERVED,Reserved" "0,1" newline hexmask.long.word 0x08 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x08 3. "INT3,Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0" newline bitfld.long 0x08 2. "INT2,Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0" bitfld.long 0x08 1. "INT1,Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0" newline bitfld.long 0x08 0. "INT0,Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0" group.long 0x90++0x17 line.long 0x00 "RTIDWDCTRL,This register s functionality is dependent on whether the DWD is implemented to be always enabled or not" hexmask.long.word 0x00 16.--31. 1. "DWDCTRL_31_16,Digital Watchdog Control" hexmask.long.word 0x00 0.--15. 1. "DWDCTRL_15_0,Digital Watchdog Control" line.long 0x04 "RTIDWDPRLD," hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED," hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value" line.long 0x08 "RTIWDSTATUS,The values of the following status bits will not be affected by a system reset" hexmask.long 0x08 6.--31. 1. "RESERVED," bitfld.long 0x08 5. "DWWD_ST,Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0" newline bitfld.long 0x08 4. "END_TIME_VIOL,Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0" bitfld.long 0x08 3. "START_TIME_VIOL,Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0" newline bitfld.long 0x08 2. "KEYST,Watchdog KeyStatus" "0,1" bitfld.long 0x08 1. "DWDST,Digital Watchdog Status" "0,1" newline bitfld.long 0x08 0. "AWDST,Analog Watchdog Status" "0,1" line.long 0x0C "RTIWDKEY," hexmask.long.word 0x0C 16.--31. 1. "RESERVED," hexmask.long.word 0x0C 0.--15. 1. "WDKEY,Watchdog Key" line.long 0x10 "RTIDWDCNTR," hexmask.long.byte 0x10 25.--31. 1. "RESERVED," hexmask.long.word 0x10 16.--24. 1. "DWDCNTR_24_16,Digital Watchdog Down Counter" newline hexmask.long.word 0x10 0.--15. 1. "DWDCNTR_15_0,Digital Watchdog Down Counter" line.long 0x14 "RTIWWDRXNCTRL," hexmask.long 0x14 4.--31. 1. "RESERVED," bitfld.long 0x14 0.--3. "WWDRXN,Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..." group.word 0xA8++0x01 line.word 0x00 "RTIWWDSIZECTRL," group.long 0xAC++0x13 line.long 0x00 "RTIINTCLRENABLE," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "RTICOMP0CLR," line.long 0x08 "RTICOMP1CLR," line.long 0x0C "RTICOMP2CLR," line.long 0x10 "RTICOMP3CLR," width 0x0B tree.end repeat.end tree "RTI1_TARG" base ad:0x4AE32000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "RTI2_TARG" base ad:0x4AE34000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "RTI3_TARG" base ad:0x4AE36000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "RTI4_TARG" base ad:0x4AE38000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "RTI5_TARG" base ad:0x4AE3A000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "SIMCOP" base ad:0x52020000 rgroup.long 0x00++0x07 line.long 0x00 "SIMCOP_HL_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "SIMCOP_HL_HWINFO,Information about the IP module's hardware configuration" hexmask.long.word 0x04 17.--31. 1. "RESERVED," bitfld.long 0x04 16. "VTNF_ENABLE,The VTNF module is present when this parameter is set" "0,1" newline bitfld.long 0x04 14.--15. "LDCIMXNSF_BOOST," "LDCIMXNSF_BOOST_0,LDCIMXNSF_BOOST_1,LDCIMXNSF_BOOST_2,LDCIMXNSF_BOOST_3" bitfld.long 0x04 10.--13. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--9. "IMAGE_BUFFERS,This parameter defines the image buffer count" "IMAGE_BUFFERS_0,IMAGE_BUFFERS_1,?,?" bitfld.long 0x04 7. "NSF3_ENABLE,The NSF3 module is present when this parameter is set" "NSF3_ENABLE_0,NSF3_ENABLE_1" newline bitfld.long 0x04 6. "ROT_A_ENABLE,The ROT #a module is present when this parameter is set" "ROT_A_ENABLE_0,ROT_A_ENABLE_1" bitfld.long 0x04 5. "IMX_B_ENABLE,The iMX #b module and the CMD#b COEFF#b memories are present when this parameter is set" "IMX_B_ENABLE_0,IMX_B_ENABLE_1" newline bitfld.long 0x04 4. "IMX_A_ENABLE,The iMX #a module and the CMD#a COEFF#a memories are present when this parameter is set" "IMX_A_ENABLE_0,IMX_A_ENABLE_1" bitfld.long 0x04 3. "NSF_ENABLE,The NSF2 module is present when this parameter is set" "NSF_ENABLE_0,NSF_ENABLE_1" newline bitfld.long 0x04 2. "VLCDJ_ENABLE,The VLCD module and the QUANT HUFFMAN BITSTREAM memories are present when this parameter is set" "VLCDJ_ENABLE_0,VLCDJ_ENABLE_1" bitfld.long 0x04 1. "DCT_ENABLE,The DCT module is present when this parameter is set" "DCT_ENABLE_0,DCT_ENABLE_1" newline bitfld.long 0x04 0. "LDC_ENABLE,The LDC module and the LDC LUT are present when this parameter is set" "LDC_ENABLE_0,LDC_ENABLE_1" group.long 0x10++0x03 line.long 0x00 "SIMCOP_HL_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x1C++0x07 line.long 0x00 "SIMCOP_HL_IRQ_EOI,End Of Interrupt number specification" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 0.--1. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1,LINE_NUMBER_2,LINE_NUMBER_3" line.long 0x04 "SIMCOP_HL_IRQSTATUS_RAW_i_0,Per-event raw interrupt status vector Raw status is set even if event is not enabled" hexmask.long.word 0x04 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x04 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" newline rbitfld.long 0x04 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" rbitfld.long 0x04 17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x04 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x04 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x04 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x04 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x04 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x04 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer" "STEP1_IRQ_0,STEP1_IRQ_1" newline bitfld.long 0x04 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer" "STEP0_IRQ_0,STEP0_IRQ_1" bitfld.long 0x04 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" newline bitfld.long 0x04 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x04 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location.Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer" "0,1" bitfld.long 0x04 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline rbitfld.long 0x04 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x30++0x03 line.long 0x00 "SIMCOP_HL_IRQSTATUS_RAW_i_1,Per-event raw interrupt status vector Raw status is set even if event is not enabled" hexmask.long.word 0x00 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" newline rbitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" rbitfld.long 0x00 17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer" "STEP1_IRQ_0,STEP1_IRQ_1" newline bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer" "STEP0_IRQ_0,STEP0_IRQ_1" bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" newline bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location.Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline rbitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x40++0x03 line.long 0x00 "SIMCOP_HL_IRQSTATUS_RAW_i_2,Per-event raw interrupt status vector Raw status is set even if event is not enabled" hexmask.long.word 0x00 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" newline rbitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" rbitfld.long 0x00 17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer" "STEP1_IRQ_0,STEP1_IRQ_1" newline bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer" "STEP0_IRQ_0,STEP0_IRQ_1" bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" newline bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location.Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline rbitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x50++0x03 line.long 0x00 "SIMCOP_HL_IRQSTATUS_RAW_i_3,Per-event raw interrupt status vector Raw status is set even if event is not enabled" hexmask.long.word 0x00 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" newline rbitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" rbitfld.long 0x00 17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer" "STEP1_IRQ_0,STEP1_IRQ_1" newline bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer" "STEP0_IRQ_0,STEP0_IRQ_1" bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" newline bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location.Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline rbitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x24++0x03 line.long 0x00 "SIMCOP_HL_IRQSTATUS_i_0,Per-event 'enabled' interrupt status vector Enabled status isn't set unless event is enabled" hexmask.long.word 0x00 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" newline rbitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" rbitfld.long 0x00 17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer" "STEP1_IRQ_0,STEP1_IRQ_1" newline bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer" "STEP0_IRQ_0,STEP0_IRQ_1" bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" newline bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline rbitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x34++0x03 line.long 0x00 "SIMCOP_HL_IRQSTATUS_i_1,Per-event 'enabled' interrupt status vector Enabled status isn't set unless event is enabled" hexmask.long.word 0x00 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" newline rbitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" rbitfld.long 0x00 17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer" "STEP1_IRQ_0,STEP1_IRQ_1" newline bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer" "STEP0_IRQ_0,STEP0_IRQ_1" bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" newline bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline rbitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x44++0x03 line.long 0x00 "SIMCOP_HL_IRQSTATUS_i_2,Per-event 'enabled' interrupt status vector Enabled status isn't set unless event is enabled" hexmask.long.word 0x00 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" newline rbitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" rbitfld.long 0x00 17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer" "STEP1_IRQ_0,STEP1_IRQ_1" newline bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer" "STEP0_IRQ_0,STEP0_IRQ_1" bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" newline bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline rbitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x54++0x03 line.long 0x00 "SIMCOP_HL_IRQSTATUS_i_3,Per-event 'enabled' interrupt status vector Enabled status isn't set unless event is enabled" hexmask.long.word 0x00 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" newline rbitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" rbitfld.long 0x00 17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer" "STEP1_IRQ_0,STEP1_IRQ_1" newline bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer" "STEP0_IRQ_0,STEP0_IRQ_1" bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" newline bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline rbitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x28++0x03 line.long 0x00 "SIMCOP_HL_IRQENABLE_SET_i_0,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" hexmask.long.word 0x00 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" newline bitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" rbitfld.long 0x00 17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer" "STEP1_IRQ_0,STEP1_IRQ_1" newline bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer" "STEP0_IRQ_0,STEP0_IRQ_1" bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" newline bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline bitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x38++0x03 line.long 0x00 "SIMCOP_HL_IRQENABLE_SET_i_1,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" hexmask.long.word 0x00 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" newline bitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" rbitfld.long 0x00 17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer" "STEP1_IRQ_0,STEP1_IRQ_1" newline bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer" "STEP0_IRQ_0,STEP0_IRQ_1" bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" newline bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline bitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x48++0x03 line.long 0x00 "SIMCOP_HL_IRQENABLE_SET_i_2,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" hexmask.long.word 0x00 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" newline bitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" rbitfld.long 0x00 17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer" "STEP1_IRQ_0,STEP1_IRQ_1" newline bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer" "STEP0_IRQ_0,STEP0_IRQ_1" bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" newline bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline bitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x58++0x03 line.long 0x00 "SIMCOP_HL_IRQENABLE_SET_i_3,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" hexmask.long.word 0x00 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" newline bitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" rbitfld.long 0x00 17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer" "STEP1_IRQ_0,STEP1_IRQ_1" newline bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer" "STEP0_IRQ_0,STEP0_IRQ_1" bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" newline bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline bitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x2C++0x03 line.long 0x00 "SIMCOP_HL_IRQENABLE_CLR_i_0,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" hexmask.long.word 0x00 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" newline bitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" rbitfld.long 0x00 17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer" "STEP1_IRQ_0,STEP1_IRQ_1" newline bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer" "STEP0_IRQ_0,STEP0_IRQ_1" bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" newline bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline bitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x3C++0x03 line.long 0x00 "SIMCOP_HL_IRQENABLE_CLR_i_1,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" hexmask.long.word 0x00 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" newline bitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" rbitfld.long 0x00 17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer" "STEP1_IRQ_0,STEP1_IRQ_1" newline bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer" "STEP0_IRQ_0,STEP0_IRQ_1" bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" newline bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline bitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x4C++0x03 line.long 0x00 "SIMCOP_HL_IRQENABLE_CLR_i_2,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" hexmask.long.word 0x00 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" newline bitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" rbitfld.long 0x00 17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer" "STEP1_IRQ_0,STEP1_IRQ_1" newline bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer" "STEP0_IRQ_0,STEP0_IRQ_1" bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" newline bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline bitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x5C++0x0B line.long 0x00 "SIMCOP_HL_IRQENABLE_CLR_i_3,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" hexmask.long.word 0x00 20.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" newline bitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" rbitfld.long 0x00 17. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer" "STEP1_IRQ_0,STEP1_IRQ_1" newline bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer" "STEP0_IRQ_0,STEP0_IRQ_1" bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" newline bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline bitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" line.long 0x04 "SIMCOP_CTRL,SIMCOP control register" rbitfld.long 0x04 29.--31. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3,4,5,6,7" bitfld.long 0x04 28. "LDC_R_BURST_BREAK,Controls if bursts issued by LDC bridge could cross burst length boundaries" "LDC_R_BURST_BREAK_0,LDC_R_BURST_BREAK_1" newline bitfld.long 0x04 26.--27. "LDC_R_MAX_BURST_LENGTH,Limits the maximum burst length that could be used by LDC" "LDC_R_MAX_BURST_LENGTH_0,LDC_R_MAX_BURST_LENGTH_1,LDC_R_MAX_BURST_LENGTH_2,LDC_R_MAX_BURST_LENGTH_3" rbitfld.long 0x04 25. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x04 21.--24. "LDC_R_TAG_CNT,Limits the maximum number of outstanding LDC requests to LDC_R_TAG_CNT+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 20. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x04 16.--19. "LDC_R_TAG_OFST,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 15. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x04 14. "IMX_B_CMD,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_CMD_0,IMX_B_CMD_1" bitfld.long 0x04 12.--13. "IMX_A_CMD,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_CMD_0,IMX_A_CMD_1,IMX_A_CMD_2,?" newline bitfld.long 0x04 11. "HUFF,This bit field is reserved and users should write the reset value to this bit location" "HUFF_0,HUFF_1" bitfld.long 0x04 10. "QUANT,This bit field is reserved and users should write the reset value to this bit location" "QUANT_0,QUANT_1" newline rbitfld.long 0x04 9. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 8. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x04 6.--7. "LDC_INPUT,This bit field is reserved and users should write the reset value to this bit location" "LDC_INPUT_0,LDC_INPUT_1,LDC_INPUT_2,LDC_INPUT_3" bitfld.long 0x04 4.--5. "NSF_WMEM,This bit field is reserved and users should write the reset value to this bit location" "NSF_WMEM_0,NSF_WMEM_1,NSF_WMEM_2,NSF_WMEM_3" newline bitfld.long 0x04 3. "IRQ3_MODE,Interrupt generation method" "IRQ3_MODE_0,IRQ3_MODE_1" bitfld.long 0x04 2. "IRQ2_MODE,Interrupt generation method" "IRQ2_MODE_0,IRQ2_MODE_1" newline bitfld.long 0x04 1. "IRQ1_MODE,Interrupt generation method" "IRQ1_MODE_0,IRQ1_MODE_1" bitfld.long 0x04 0. "IRQ0_MODE,Interrupt generation method" "IRQ0_MODE_0,IRQ0_MODE_1" line.long 0x08 "SIMCOP_CLKCTRL,SIMCOP clock control register" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" bitfld.long 0x08 9. "VTNF,VTNF" "VTNF_0,VTNF_1" newline rbitfld.long 0x08 8. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x08 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "ROT_A_0,ROT_A_1" newline bitfld.long 0x08 6. "IMX_B,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_0,IMX_B_1" bitfld.long 0x08 5. "IMX_A,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_0,IMX_A_1" newline bitfld.long 0x08 4. "NSF2,This bit field is reserved and users should write the reset value to this bit location" "NSF2_0,NSF2_1" bitfld.long 0x08 3. "VLCDJ,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_0,VLCDJ_1" newline bitfld.long 0x08 2. "DCT,This bit field is reserved and users should write the reset value to this bit location" "DCT_0,DCT_1" bitfld.long 0x08 1. "LDC,LDC" "LDC_0,LDC_1" newline bitfld.long 0x08 0. "DMA,DMA" "DMA_0,DMA_1" group.long 0xFC++0x03 line.long 0x00 "SIMCOP_CTRL2,Simcop control register" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,This bit field is reserved and users should write the reset value to this bit location" abitfld.long 0x00 0.--11. "LDCR_BW_CTRL,Limits the mean bandwidth (computed over one block) that the LDC module can request for read from system memory" "0x000=The BW limiter is bypassed 1~4095,0x001=1.6 MBytes/s @ 426 MHz,0xFFF=6.8 GBytes/s @ 426 Mhz" width 0x0B tree.end repeat 2. (list 1. 2. )(list ad:0x48484D80 ad:0x48484DC0 ) tree "SL$1" base $2 rgroup.long 0x00++0x2B line.long 0x00 "SL_IDVER,CPGMAC_SL revision register" line.long 0x04 "SL_MACCONTROL,CPGMAC_SL MAC control register" hexmask.long.byte 0x04 25.--31. 1. "RESERVED," bitfld.long 0x04 24. "RX_CMF_EN,RX Copy MAC Control Frames Enable - Enables MAC control frames to be transferred to memory" "MAC control frames are filtered (but acted upon..,MAC control frames are transferred to memory" newline bitfld.long 0x04 23. "RX_CSF_EN,RX Copy Short Frames Enable - Enables frames or fragments shorter than 64 bytes to be copied to memory" "Short frames are filtered,Short frames are transferred to memory" bitfld.long 0x04 22. "RX_CEF_EN,RX Copy Error Frames Enable - Enables frames containing errors to be transferred to memory" "Frames containing errors are filtered,Frames containing errors are transferred to memory" newline bitfld.long 0x04 21. "TX_SHORT_GAP_LIM_EN,Transmit Short Gap Limit Enable When set this bit limits the number of short gap packets transmitted to 100ppm" "0,1" rbitfld.long 0x04 19.--20. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 18. "EXT_EN,Control Enable - Enables the fullduplex and gigabit mode to be selected from the FULLDUPLEX_IN and GIG_IN input signals and not from the FULLDUPLEX and GIG bits in this register" "Use this setting for RMII/GMII mode,Use this setting for RGMII mode" bitfld.long 0x04 17. "GIG_FORCE,Gigabit Mode Force - This bit is used to force the CPGMAC_SL into gigabit mode if the input GMII_MTCLK has been stopped by the PHY" "0,1" newline bitfld.long 0x04 16. "IFCTL_B,Interface Control B (NOT FUNCTIONAL)" "0,1" bitfld.long 0x04 15. "IFCTL_A,Interface Control A" "0,1" newline rbitfld.long 0x04 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 11. "CMD_IDLE,Command Idle" "Idle not commanded,Idle Commanded (read IDLE in SL_MACSTATUS)" newline bitfld.long 0x04 10. "TX_SHORT_GAP_EN,Transmit Short Gap Enable" "Transmit with a short IPG is disabled,Transmit with a short IPG (when TX_SHORT_GAP.." rbitfld.long 0x04 8.--9. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 7. "GIG,Gigabit Mode" "0,1" bitfld.long 0x04 6. "TX_PACE,Transmit Pacing Enable" "Transmit Pacing Disabled,Transmit Pacing Enabled" newline bitfld.long 0x04 5. "GMII_EN,GMII Enable" "GMII RX and TX held in reset,GMII RX and TX released from reset" bitfld.long 0x04 4. "TX_FLOW_EN,Transmit Flow Control Enable - Determines if incoming pause frames are acted upon in full-duplex mode" "Transmit Flow Control Disabled,Transmit Flow Control Enabled" newline bitfld.long 0x04 3. "RX_FLOW_EN,Receive Flow Control Enable" "Receive Flow Control Disabled Half-duplex mode -..,Receive Flow Control Enabled Half-duplex mode -.." bitfld.long 0x04 2. "MTEST,Manufacturing Test mode - This bit must be set to allow writes to theSL_BOFFTEST and SL_RX_PAUSE/SL_TX_PAUSE registers" "0,1" newline bitfld.long 0x04 1. "LOOPBACK,Loop Back Mode - Loopback mode forces internal fullduplex mode regardless of whether the FULLDUPLEX bit is set or not" "Not looped back,Loop Back Mode enabled" bitfld.long 0x04 0. "FULLDUPLEX,Full Duplex mode - Gigabit mode forces fullduplex mode regardless of whether the FULLDUPLEX bit is set or not" "half duplex mode,full duplex mode" line.long 0x08 "SL_MACSTATUS,CPGMAC_SL MAC status register" bitfld.long 0x08 31. "IDLE,CPGMAC_SL IDLE - The CPGMAC_SL is in the idle state (valid after an idle command)" "The CPGMAC_SL is not in the idle state,The CPGMAC_SL is in the idle state" hexmask.long 0x08 5.--30. 1. "RESERVED," newline bitfld.long 0x08 4. "EXT_GIG,External GIG - This is the value of the EXT_GIG input bit" "0,1" bitfld.long 0x08 3. "EXT_FULLDUPLEX,External Fullduplex - This is the value of the EXT_FULLDUPLEX input bit" "0,1" newline bitfld.long 0x08 2. "RESERVED," "0,1" bitfld.long 0x08 1. "RX_FLOW_ACT,Receive Flow Control Active - When asserted indicates that receive flow control is enabled and triggered" "0,1" newline bitfld.long 0x08 0. "TX_FLOW_ACT,Transmit Flow Control Active - When asserted this bit indicates that the pause time period is being observed for a received pause frame" "0,1" line.long 0x0C "SL_SOFT_RESET,CPGMAC_SL soft reset register" hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the CPGMAC_SL logic to be reset" "0,1" line.long 0x10 "SL_RX_MAXLEN,CPGMAC_SL RX Maximum length register" hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," hexmask.long.word 0x10 0.--13. 1. "RX_MAXLEN,RX Maximum Frame Length - This field determines the maximum length of a received frame" line.long 0x14 "SL_BOFFTEST,CPGMAC_SL backoff test register" rbitfld.long 0x14 31. "RESERVED," "0,1" bitfld.long 0x14 26.--30. "PACEVAL,Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x14 16.--25. 1. "RNDNUM,Backoff Random Number Generator - This field allows the Backoff Random Number Generator to be read (or written in test mode only)" rbitfld.long 0x14 12.--15. "COLL_COUNT,Collision Count - The number of collisions the current frame has experienced" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x14 10.--11. "RESERVED," "0,1,2,3" hexmask.long.word 0x14 0.--9. 1. "TX_BACKOFF,Backoff Count - This field allows the current value of the backoff counter to be observed for test purposes" line.long 0x18 "SL_RX_PAUSE,CPGMAC_SL receive pause timer register" hexmask.long.word 0x18 16.--31. 1. "RESERVED," hexmask.long.word 0x18 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value - This field allows the contents of the receive pause timer to be observed (and written in test mode)" line.long 0x1C "SL_TX_PAUSE,CPGMAC_SL transmit pause timer register" hexmask.long.word 0x1C 16.--31. 1. "RESERVED," hexmask.long.word 0x1C 0.--15. 1. "TX_PAUSETIMER,TX Pause Timer Value - This field allows the contents of the transmit pause timer to be observed (and written in test mode)" line.long 0x20 "SL_EMCONTROL,CPGMAC_SL emulation control register" hexmask.long 0x20 2.--31. 1. "RESERVED," bitfld.long 0x20 1. "SOFT,Emulation Soft Bit" "0,1" newline bitfld.long 0x20 0. "FREE,Emulation Free Bit" "0,1" line.long 0x24 "SL_RX_PRI_MAP,CPGMAC_SL RX packet priority to header priority mapping register" rbitfld.long 0x24 31. "RESERVED," "0,1" bitfld.long 0x24 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 27. "RESERVED," "0,1" bitfld.long 0x24 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 23. "RESERVED," "0,1" bitfld.long 0x24 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 19. "RESERVED," "0,1" bitfld.long 0x24 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 15. "RESERVED," "0,1" bitfld.long 0x24 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 11. "RESERVED," "0,1" bitfld.long 0x24 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 7. "RESERVED," "0,1" bitfld.long 0x24 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 3. "RESERVED," "0,1" bitfld.long 0x24 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x28 "SL_TX_GAP,Transmit inter-packet gap register" hexmask.long.tbyte 0x28 9.--31. 1. "RESERVED," hexmask.long.word 0x28 0.--8. 1. "TX_GAP,Transmit Inter-Packet Gap" width 0x0B tree.end repeat.end tree "SMARTREFLEX_CORE" base ad:0x4A0DD000 group.long 0x00++0x3B line.long 0x00 "SRCONFIG,Configuration bits for the Sensor Core and the Digital Processing" hexmask.long.word 0x00 22.--31. 1. "ACCUMDATA,Number of values to accumulate" hexmask.long.word 0x00 12.--21. 1. "SRCLKLENGTH,Determines the frequency of SRClk" newline bitfld.long 0x00 11. "SRENABLE," "0,1" bitfld.long 0x00 10. "SENENABLE," "0,1" newline bitfld.long 0x00 9. "ERRORGENERATORENABLE," "0,1" bitfld.long 0x00 8. "MINMAXAVGENABLE," "0,1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1. "SENNENABLE," "0,1" newline bitfld.long 0x00 0. "SENPENABLE," "0,1" line.long 0x04 "SRSTATUS,Status bits that indicate that the values in the register are valid or events have occurred" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "AVGERRVALID," "0,1" newline bitfld.long 0x04 2. "MINMAXAVGVALID," "0,1" bitfld.long 0x04 1. "ERRORGENERATORVALID," "0,1" newline bitfld.long 0x04 0. "MINMAXAVGACCUMVALID," "0,1" line.long 0x08 "SENVAL,The current sensor values from the Sensor Core(SVT)" hexmask.long.word 0x08 16.--31. 1. "SENPVAL,The latest value of the SenPVal from the SVT sensor core" hexmask.long.word 0x08 0.--15. 1. "SENNVAL,The latest value of the SenNVal from the SVT sensor core" line.long 0x0C "SENMIN,The minimum sensor values(SVT)" hexmask.long.word 0x0C 16.--31. 1. "SENPMIN,The minimum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x0C 0.--15. 1. "SENNMIN,The minimum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x10 "SENMAX,The maximum sensor values(SVT)" hexmask.long.word 0x10 16.--31. 1. "SENPMAX,The maximum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x10 0.--15. 1. "SENNMAX,The maximum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x14 "SENAVG,The average sensor values(SVT)" hexmask.long.word 0x14 16.--31. 1. "SENPAVG,The running average of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x14 0.--15. 1. "SENNAVG,The running average of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x18 "AVGWEIGHT,The weighting factor in the average computation" hexmask.long.word 0x18 16.--31. 1. "SENPAVGWEIGHT1,The weighting factor for the SenP averager" hexmask.long.word 0x18 0.--15. 1. "SENNAVGWEIGHT,The weighting factor for the SenN averager" line.long 0x1C "NVALUERECIPROCAL,The reciprocal of the SenN and SenP values used in error generation(SVT)" hexmask.long.byte 0x1C 24.--31. 1. "RESERVED," bitfld.long 0x1C 20.--23. "SENPGAIN,The gain value for the SVT SenP reciprocal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 16.--19. "SENNGAIN,The gain value for the SVT SenN reciprocal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x1C 8.--15. 1. "SENPRN,The scale value for the SVT SenP reciprocal" newline hexmask.long.byte 0x1C 0.--7. 1. "SENNRN,The scale value for the SVT SenN reciprocal" line.long 0x20 "IRQ_EOI,EOI protocol re-trigger" hexmask.long 0x20 1.--31. 1. "RESERVED," bitfld.long 0x20 0. "EOI,The value read is always '0' Write" "re-evaluate pending sources re-send intr*,No change to interrupt" line.long 0x24 "IRQSTATUS_RAW,MCU raw interrupt raw status and set" hexmask.long 0x24 4.--31. 1. "RESERVED," bitfld.long 0x24 3. "MCUACCUMINTSTATRAW,Read:Accum interrupt status Write" "Accum interrupt status is unchanged,Accum interrupt status is set" newline bitfld.long 0x24 2. "MCUVALIDINTSTATRAW,Read:Valid interrupt status Write" "Valid status is unchanged,Valid status is set" bitfld.long 0x24 1. "MCUBOUNDSINTSTATRAW,Read:Bounds interrupt status Write" "Bounds interrupt status is unchanged,Bounds interrupt status is set" newline bitfld.long 0x24 0. "MCUDISABLEACKINTSTATRAW,Read:MCUDisable acknowledge interrupt status Write" "MCUDisable acknowledge status is unchanged,MCUDisable acknowledge status is set" line.long 0x28 "IRQSTATUS,MCU masked interrupt status and clear" hexmask.long 0x28 4.--31. 1. "RESERVED," bitfld.long 0x28 3. "MCUACCUMINTSTATENA,Read:Accum interrupt status if enabled Write" "Accum interrupt status is unchanged,Accum interrupt status is cleared" newline bitfld.long 0x28 2. "MCUVALIDINTSTATENA,Read:Valid interrupt status if enabled Write" "Valid interrupt status is unchanged,Valid interrupt status is cleared" bitfld.long 0x28 1. "MCUBOUNDSINTSTATENA,Read:Bounds interrupt status if enabled Write" "Bounds interrupt status is unchanged,Bounds interrupt status is cleared" newline bitfld.long 0x28 0. "MCUDISABLEACKINTSTATENA,Read:MCUDisable acknowledge interrupt status if enabled Write" "MCUDisable acknowledge status is unchanged,MCUDisable acknowledge status is cleared" line.long 0x2C "IRQENABLE_SET,MCU interrupt enable flag set" hexmask.long 0x2C 4.--31. 1. "RESERVED," bitfld.long 0x2C 3. "MCUACCUMINTENASET,Read" "No change to Accum interrupt enable,Enable Accum interrupt generation" newline bitfld.long 0x2C 2. "MCUVALIDINTENASET,Read" "No change to Valid interrupt enable,Enable Valid interrupt generation" bitfld.long 0x2C 1. "MCUBOUNDSINTENASET,Read" "No change to Bounds interrupt enable,Enable Bounds interrupt generation" newline bitfld.long 0x2C 0. "MCUDISABLEACKINTENASET,Read" "No change to MCUDisAck interrupt enable,Enable MCUDisableAck interrupt generation" line.long 0x30 "IRQENABLE_CLR,MCU interrupt enable flag clear" hexmask.long 0x30 4.--31. 1. "RESERVED," bitfld.long 0x30 3. "MCUACCUMINTENACLR,Read" "No change to Disable Accum interrupt enable,Disable Accum interrupt generation" newline bitfld.long 0x30 2. "MCUVALIDINTENACLR,Read" "No change to Disable Valid interrupt enable,Disable Valid interrupt generation" bitfld.long 0x30 1. "MCUBOUNDSINTENACLR,Read" "No change to Bounds interrupt enable,Disable Bounds interrupt generation" newline bitfld.long 0x30 0. "MCUDISABLEACKINTENACLR,Read" "No change to MCUDisAck interrupt enable,Disable MCUDisableAck interrupt generation" line.long 0x34 "SENERROR,The sensor error from the error generator" hexmask.long.word 0x34 16.--31. 1. "RESERVED," hexmask.long.byte 0x34 8.--15. 1. "AVGERROR,The average sensor error" newline hexmask.long.byte 0x34 0.--7. 1. "SENERROR,The percentage of sensor error" line.long 0x38 "ERRCONFIG,The sensor error configuration" rbitfld.long 0x38 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 26. "WAKEUPENABLE,Wakeup from MCU Interrupts enable" "0,1" newline bitfld.long 0x38 24.--25. "IDLEMODE," "0,1,2,3" bitfld.long 0x38 23. "VPBOUNDSINTSTATENA,Read: Bounds interrupt status if enabled Write" "Bounds interrupt status is unchanged,Bounds interrupt status is cleared" newline bitfld.long 0x38 22. "VPBOUNDSINTENABLE," "0,1" rbitfld.long 0x38 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 16.--18. "ERRWEIGHT,The AvgSenError weight" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 8.--15. 1. "ERRMAXLIMIT,The upper limit of SenError for interrupt generation" newline hexmask.long.byte 0x38 0.--7. 1. "ERRMINLIMIT,The lower limit of SenError for interrupt generation" width 0x0B tree.end tree "SMARTREFLEX_DSPEVE" base ad:0x4A183000 group.long 0x00++0x3B line.long 0x00 "SRCONFIG,Configuration bits for the Sensor Core and the Digital Processing" hexmask.long.word 0x00 22.--31. 1. "ACCUMDATA,Number of values to accumulate" hexmask.long.word 0x00 12.--21. 1. "SRCLKLENGTH,Determines the frequency of SRClk" newline bitfld.long 0x00 11. "SRENABLE," "0,1" bitfld.long 0x00 10. "SENENABLE," "0,1" newline bitfld.long 0x00 9. "ERRORGENERATORENABLE," "0,1" bitfld.long 0x00 8. "MINMAXAVGENABLE," "0,1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1. "SENNENABLE," "0,1" newline bitfld.long 0x00 0. "SENPENABLE," "0,1" line.long 0x04 "SRSTATUS,Status bits that indicate that the values in the register are valid or events have occurred" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "AVGERRVALID," "0,1" newline bitfld.long 0x04 2. "MINMAXAVGVALID," "0,1" bitfld.long 0x04 1. "ERRORGENERATORVALID," "0,1" newline bitfld.long 0x04 0. "MINMAXAVGACCUMVALID," "0,1" line.long 0x08 "SENVAL,The current sensor values from the Sensor Core(SVT)" hexmask.long.word 0x08 16.--31. 1. "SENPVAL,The latest value of the SenPVal from the SVT sensor core" hexmask.long.word 0x08 0.--15. 1. "SENNVAL,The latest value of the SenNVal from the SVT sensor core" line.long 0x0C "SENMIN,The minimum sensor values(SVT)" hexmask.long.word 0x0C 16.--31. 1. "SENPMIN,The minimum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x0C 0.--15. 1. "SENNMIN,The minimum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x10 "SENMAX,The maximum sensor values(SVT)" hexmask.long.word 0x10 16.--31. 1. "SENPMAX,The maximum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x10 0.--15. 1. "SENNMAX,The maximum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x14 "SENAVG,The average sensor values(SVT)" hexmask.long.word 0x14 16.--31. 1. "SENPAVG,The running average of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x14 0.--15. 1. "SENNAVG,The running average of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x18 "AVGWEIGHT,The weighting factor in the average computation" hexmask.long.word 0x18 16.--31. 1. "SENPAVGWEIGHT1,The weighting factor for the SenP averager" hexmask.long.word 0x18 0.--15. 1. "SENNAVGWEIGHT,The weighting factor for the SenN averager" line.long 0x1C "NVALUERECIPROCAL,The reciprocal of the SenN and SenP values used in error generation(SVT)" hexmask.long.byte 0x1C 24.--31. 1. "RESERVED," bitfld.long 0x1C 20.--23. "SENPGAIN,The gain value for the SVT SenP reciprocal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 16.--19. "SENNGAIN,The gain value for the SVT SenN reciprocal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x1C 8.--15. 1. "SENPRN,The scale value for the SVT SenP reciprocal" newline hexmask.long.byte 0x1C 0.--7. 1. "SENNRN,The scale value for the SVT SenN reciprocal" line.long 0x20 "IRQ_EOI,EOI protocol re-trigger" hexmask.long 0x20 1.--31. 1. "RESERVED," bitfld.long 0x20 0. "EOI,The value read is always '0' Write" "re-evaluate pending sources re-send intr*,No change to interrupt" line.long 0x24 "IRQSTATUS_RAW,MCU raw interrupt raw status and set" hexmask.long 0x24 4.--31. 1. "RESERVED," bitfld.long 0x24 3. "MCUACCUMINTSTATRAW,Read:Accum interrupt status Write" "Accum interrupt status is unchanged,Accum interrupt status is set" newline bitfld.long 0x24 2. "MCUVALIDINTSTATRAW,Read:Valid interrupt status Write" "Valid status is unchanged,Valid status is set" bitfld.long 0x24 1. "MCUBOUNDSINTSTATRAW,Read:Bounds interrupt status Write" "Bounds interrupt status is unchanged,Bounds interrupt status is set" newline bitfld.long 0x24 0. "MCUDISABLEACKINTSTATRAW,Read:MCUDisable acknowledge interrupt status Write" "MCUDisable acknowledge status is unchanged,MCUDisable acknowledge status is set" line.long 0x28 "IRQSTATUS,MCU masked interrupt status and clear" hexmask.long 0x28 4.--31. 1. "RESERVED," bitfld.long 0x28 3. "MCUACCUMINTSTATENA,Read:Accum interrupt status if enabled Write" "Accum interrupt status is unchanged,Accum interrupt status is cleared" newline bitfld.long 0x28 2. "MCUVALIDINTSTATENA,Read:Valid interrupt status if enabled Write" "Valid interrupt status is unchanged,Valid interrupt status is cleared" bitfld.long 0x28 1. "MCUBOUNDSINTSTATENA,Read:Bounds interrupt status if enabled Write" "Bounds interrupt status is unchanged,Bounds interrupt status is cleared" newline bitfld.long 0x28 0. "MCUDISABLEACKINTSTATENA,Read:MCUDisable acknowledge interrupt status if enabled Write" "MCUDisable acknowledge status is unchanged,MCUDisable acknowledge status is cleared" line.long 0x2C "IRQENABLE_SET,MCU interrupt enable flag set" hexmask.long 0x2C 4.--31. 1. "RESERVED," bitfld.long 0x2C 3. "MCUACCUMINTENASET,Read" "No change to Accum interrupt enable,Enable Accum interrupt generation" newline bitfld.long 0x2C 2. "MCUVALIDINTENASET,Read" "No change to Valid interrupt enable,Enable Valid interrupt generation" bitfld.long 0x2C 1. "MCUBOUNDSINTENASET,Read" "No change to Bounds interrupt enable,Enable Bounds interrupt generation" newline bitfld.long 0x2C 0. "MCUDISABLEACKINTENASET,Read" "No change to MCUDisAck interrupt enable,Enable MCUDisableAck interrupt generation" line.long 0x30 "IRQENABLE_CLR,MCU interrupt enable flag clear" hexmask.long 0x30 4.--31. 1. "RESERVED," bitfld.long 0x30 3. "MCUACCUMINTENACLR,Read" "No change to Disable Accum interrupt enable,Disable Accum interrupt generation" newline bitfld.long 0x30 2. "MCUVALIDINTENACLR,Read" "No change to Disable Valid interrupt enable,Disable Valid interrupt generation" bitfld.long 0x30 1. "MCUBOUNDSINTENACLR,Read" "No change to Bounds interrupt enable,Disable Bounds interrupt generation" newline bitfld.long 0x30 0. "MCUDISABLEACKINTENACLR,Read" "No change to MCUDisAck interrupt enable,Disable MCUDisableAck interrupt generation" line.long 0x34 "SENERROR,The sensor error from the error generator" hexmask.long.word 0x34 16.--31. 1. "RESERVED," hexmask.long.byte 0x34 8.--15. 1. "AVGERROR,The average sensor error" newline hexmask.long.byte 0x34 0.--7. 1. "SENERROR,The percentage of sensor error" line.long 0x38 "ERRCONFIG,The sensor error configuration" rbitfld.long 0x38 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 26. "WAKEUPENABLE,Wakeup from MCU Interrupts enable" "0,1" newline bitfld.long 0x38 24.--25. "IDLEMODE," "0,1,2,3" bitfld.long 0x38 23. "VPBOUNDSINTSTATENA,Read: Bounds interrupt status if enabled Write" "Bounds interrupt status is unchanged,Bounds interrupt status is cleared" newline bitfld.long 0x38 22. "VPBOUNDSINTENABLE," "0,1" rbitfld.long 0x38 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 16.--18. "ERRWEIGHT,The AvgSenError weight" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 8.--15. 1. "ERRMAXLIMIT,The upper limit of SenError for interrupt generation" newline hexmask.long.byte 0x38 0.--7. 1. "ERRMINLIMIT,The lower limit of SenError for interrupt generation" width 0x0B tree.end repeat 2. (list 1. 2. )(list ad:0x48485C00 ad:0x48485E00 ) tree "SPF$1" base $2 rgroup.long 0x00++0x27 line.long 0x00 "SPF_IDVER,SPF revision register" line.long 0x04 "SPF_STATUS,Status register" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "SPF_BUSY,SPF is Busy/Idle Busy Packet processing or logging in progress" "0,1" line.long 0x08 "SPF_CONTROL,SPF control register" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "SPF_LOGOW_EN,SPF Log Overwrite Enable" "0,1" bitfld.long 0x08 8. "SPF_LOG_EN,SPF Log Enable" "0,1" rbitfld.long 0x08 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 3. "SPF_RULE_LOG,SPF Rule Engine Log Enable" "0,1" bitfld.long 0x08 2. "SPF_EXT_BYPASS,SPF Extractor Bypass Enable" "0,1" newline bitfld.long 0x08 1. "SPF_DROP,SPF Drop Enable" "0,1" bitfld.long 0x08 0. "SPF_ENABLE,SPF Enable" "0,1" line.long 0x0C "SPF_DROPCOUNT,Drop Count Register" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x0C 0.--23. 1. "SPF_DROPCNT,SPF Drop counter indicates the number of packets dropped so far" line.long 0x10 "SPF_SWRESET,Software Reset Register" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "SPF_SWRST,SPF Software reset bit can be set to initiate a software reset" "0,1" line.long 0x14 "SPF_PRESCALE,Rate Limit Prescale Register" hexmask.long.word 0x14 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x14 0.--19. 1. "SPF_PRESCALE,The MAIN clock is divided by this value for use in Rate Limiters" line.long 0x18 "SPF_RATELIMi_0,Rate Limit Register" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," hexmask.long.byte 0x18 0.--7. 1. "SPF_RATELIM,SPF Rate Limit Register" line.long 0x1C "SPF_RATELIMi_1,Rate Limit Register" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," hexmask.long.byte 0x1C 0.--7. 1. "SPF_RATELIM,SPF Rate Limit Register" line.long 0x20 "SPF_RATELIMi_2,Rate Limit Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED," hexmask.long.byte 0x20 0.--7. 1. "SPF_RATELIM,SPF Rate Limit Register" line.long 0x24 "SPF_RATELIMi_3,Rate Limit Register" hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED," hexmask.long.byte 0x24 0.--7. 1. "SPF_RATELIM,SPF Rate Limit Register" group.long 0x1C++0x1F line.long 0x00 "SPF_CONSTj_0,Constant Register" line.long 0x04 "SPF_CONSTj_1,Constant Register" line.long 0x08 "SPF_CONSTj_2,Constant Register" line.long 0x0C "SPF_CONSTj_3,Constant Register" line.long 0x10 "SPF_CONSTj_4,Constant Register" line.long 0x14 "SPF_CONSTj_5,Constant Register" line.long 0x18 "SPF_CONSTj_6,Constant Register" line.long 0x1C "SPF_CONSTj_7,Constant Register" group.long 0x50++0x5F line.long 0x00 "SPF_INSTRW2,Instruction Word 2 Register" hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED," hexmask.long.word 0x00 0.--13. 1. "SPF_INSTR_W2,SPF Rule Engine Instruction Word [75:64] is read from or written to this field" line.long 0x04 "SPF_INSTRW1,Instruction Word 1 Register" line.long 0x08 "SPF_INSTRW0,Instruction Word 0 Register" line.long 0x0C "SPF_INSTR_CTL,Instruction Control Register" bitfld.long 0x0C 31. "SPF_INSTR_WEN,SPF Write enable bit specifies whether a write operation is to be performed" "0,1" bitfld.long 0x0C 30. "SPF_INSTR_REN,SPF Read enable bit specifies whether a read operation is to be performed" "0,1" hexmask.long.tbyte 0x0C 6.--29. 1. "RESERVED," bitfld.long 0x0C 0.--5. "SPF_INSTR_PTR,The address in the instruction memory that is to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "SPF_LOG_BEGIN,Log Begin Address Register" line.long 0x14 "SPF_LOG_END,Log End Address Register" line.long 0x18 "SPF_LOG_HWPTR,Log Hardware Pointer Register" line.long 0x1C "SPF_LOG_SWPTR,Log Software Pointer Register" line.long 0x20 "SPF_LOG_MAP0,Filter Code Map Register 0" hexmask.long.byte 0x20 24.--31. 1. "SPF_LOGMAP3,Mapping of drop code 3 to log threshold 3" hexmask.long.byte 0x20 16.--23. 1. "SPF_LOGMAP2,Mapping of drop code 2 to log threshold 2" hexmask.long.byte 0x20 8.--15. 1. "SPF_LOGMAP1,Mapping of drop code 1 to log threshold 1" hexmask.long.byte 0x20 0.--7. 1. "SPF_LOGMAP0,Mapping of drop code 0 to log threshold 0" line.long 0x24 "SPF_LOG_MAP1,Filter Code Map Register 1" hexmask.long.byte 0x24 24.--31. 1. "SPF_LOGMAP7,Mapping of drop code 7 to log threshold 7" hexmask.long.byte 0x24 16.--23. 1. "SPF_LOGMAP6,Mapping of drop code 6 to log threshold 6" hexmask.long.byte 0x24 8.--15. 1. "SPF_LOGMAP5,Mapping of drop code 5 to log threshold 5" hexmask.long.byte 0x24 0.--7. 1. "SPF_LOGMAP4,Mapping of drop code 4 to log threshold 4" line.long 0x28 "SPF_LOG_THRESHk_0,Log Threshold and Count Register" hexmask.long.word 0x28 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x28 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x2C "SPF_LOG_THRESHk_1,Log Threshold and Count Register" hexmask.long.word 0x2C 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x2C 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x30 "SPF_LOG_THRESHk_2,Log Threshold and Count Register" hexmask.long.word 0x30 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x30 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x34 "SPF_LOG_THRESHk_3,Log Threshold and Count Register" hexmask.long.word 0x34 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x34 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x38 "SPF_LOG_THRESHk_4,Log Threshold and Count Register" hexmask.long.word 0x38 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x38 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x3C "SPF_LOG_THRESHk_5,Log Threshold and Count Register" hexmask.long.word 0x3C 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x3C 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x40 "SPF_LOG_THRESHk_6,Log Threshold and Count Register" hexmask.long.word 0x40 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x40 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x44 "SPF_LOG_THRESHk_7,Log Threshold and Count Register" hexmask.long.word 0x44 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x44 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x48 "SPF_LOG_THRESHk_8,Log Threshold and Count Register" hexmask.long.word 0x48 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x48 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x4C "SPF_INTCNT,Interrupt Frequency Control Register" hexmask.long 0x4C 5.--31. 1. "RESERVED," bitfld.long 0x4C 0.--4. "SPF_INTCNT,Number of time thresholds must be met before a drop interrupt is triggered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "SPF_INT_RAW,Raw Interrupt Status register" hexmask.long 0x50 1.--31. 1. "RESERVED," bitfld.long 0x50 0. "SPF_INT_RAW,Status of Raw interrupt signal" "0,1" line.long 0x54 "SPF_INT_MASKED,Interrupt Status register" hexmask.long 0x54 1.--31. 1. "RESERVED," bitfld.long 0x54 0. "SPF_INT_MASKED,Status of interrupt signal with mask" "0,1" line.long 0x58 "SPF_MASK_SET,Interrupt Mask Set Register" hexmask.long 0x58 1.--31. 1. "RESERVED," bitfld.long 0x58 0. "SPF_MASKSET,Write a 1 to this bit to enable the interrupt" "0,1" line.long 0x5C "SPF_MASK_CLR,Interrupt Mask Clear Register" hexmask.long 0x5C 1.--31. 1. "RESERVED," bitfld.long 0x5C 0. "SPF_MASKCLR,Write a 1 to this bit to disable the interrupt" "0,1" width 0x0B tree.end repeat.end tree "Spinlock" base ad:0x4A0F6000 rgroup.long 0x00++0x03 line.long 0x00 "SPINLOCK_REVISION,This register contains the IP revision code" group.long 0x10++0x07 line.long 0x00 "SPINLOCK_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 3.--4. "SIDLEMODE,Slave interface power management (IDLE request/acknowledgement control)" "SIDLEMODE_0_r,SIDLEMODE_1_r,SIDLEMODE_2_r,SIDLEMODE_3_r" rbitfld.long 0x00 2. "ENWAKEUP,Asynchronous wakeup gereration" "ENWAKEUP_0_r,ENWAKEUP_1_r" bitfld.long 0x00 1. "SOFTRESET,Module software reset" "SOFTRESET_0_w,SOFTRESET_1_w" rbitfld.long 0x00 0. "AUTOGATING,Internal interface clock gating strategy" "AUTOGATING_0_r,AUTOGATING_1_r" line.long 0x04 "SPINLOCK_SYSTATUS,This register provides status information about this instance of the Spinlock module" hexmask.long.byte 0x04 24.--31. 1. "NUMLOCKS,Number of lock registers implemeted" hexmask.long.byte 0x04 16.--23. 1. "RESERVED,Reserved" bitfld.long 0x04 15. "IU7,In-Use flag 0 covering lock registers" "IU7_0_r,IU7_1_r" bitfld.long 0x04 14. "IU6,In-Use flag 0 covering lock registers" "IU6_0_r,IU6_1_r" bitfld.long 0x04 13. "IU5,In-Use flag 0 covering lock registers" "IU5_0_r,IU5_1_r" newline bitfld.long 0x04 12. "IU4,In-Use flag 0 covering lock registers" "IU4_0_r,IU4_1_r" bitfld.long 0x04 11. "IU3,In-Use flag 0 covering lock registers" "IU3_0_r,IU3_1_r" bitfld.long 0x04 10. "IU2,In-Use flag 0 covering lock registers" "IU2_0_r,IU2_1_r" bitfld.long 0x04 9. "IU1,In-Use flag 0 covering lock registers" "IU1_0_r,IU1_1_r" bitfld.long 0x04 8. "IU0,In-Use flag 0 covering lock registers" "IU0_0_r,IU0_1_r" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x04 0. "RESETDONE,Reset done status" "RESETDONE_0_r,RESETDONE_1_r" group.long 0x800++0x3FF line.long 0x00 "SPINLOCK_LOCK_REG_i_0,This register contains the state of one lock" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x04 "SPINLOCK_LOCK_REG_i_1,This register contains the state of one lock" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x08 "SPINLOCK_LOCK_REG_i_2,This register contains the state of one lock" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x0C "SPINLOCK_LOCK_REG_i_3,This register contains the state of one lock" hexmask.long 0x0C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x10 "SPINLOCK_LOCK_REG_i_4,This register contains the state of one lock" hexmask.long 0x10 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x14 "SPINLOCK_LOCK_REG_i_5,This register contains the state of one lock" hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x18 "SPINLOCK_LOCK_REG_i_6,This register contains the state of one lock" hexmask.long 0x18 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1C "SPINLOCK_LOCK_REG_i_7,This register contains the state of one lock" hexmask.long 0x1C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x20 "SPINLOCK_LOCK_REG_i_8,This register contains the state of one lock" hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x24 "SPINLOCK_LOCK_REG_i_9,This register contains the state of one lock" hexmask.long 0x24 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x28 "SPINLOCK_LOCK_REG_i_10,This register contains the state of one lock" hexmask.long 0x28 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2C "SPINLOCK_LOCK_REG_i_11,This register contains the state of one lock" hexmask.long 0x2C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x30 "SPINLOCK_LOCK_REG_i_12,This register contains the state of one lock" hexmask.long 0x30 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x30 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x34 "SPINLOCK_LOCK_REG_i_13,This register contains the state of one lock" hexmask.long 0x34 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x38 "SPINLOCK_LOCK_REG_i_14,This register contains the state of one lock" hexmask.long 0x38 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x38 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3C "SPINLOCK_LOCK_REG_i_15,This register contains the state of one lock" hexmask.long 0x3C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x40 "SPINLOCK_LOCK_REG_i_16,This register contains the state of one lock" hexmask.long 0x40 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x40 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x44 "SPINLOCK_LOCK_REG_i_17,This register contains the state of one lock" hexmask.long 0x44 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x44 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x48 "SPINLOCK_LOCK_REG_i_18,This register contains the state of one lock" hexmask.long 0x48 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x48 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x4C "SPINLOCK_LOCK_REG_i_19,This register contains the state of one lock" hexmask.long 0x4C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x50 "SPINLOCK_LOCK_REG_i_20,This register contains the state of one lock" hexmask.long 0x50 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x50 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x54 "SPINLOCK_LOCK_REG_i_21,This register contains the state of one lock" hexmask.long 0x54 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x54 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x58 "SPINLOCK_LOCK_REG_i_22,This register contains the state of one lock" hexmask.long 0x58 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x58 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x5C "SPINLOCK_LOCK_REG_i_23,This register contains the state of one lock" hexmask.long 0x5C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x5C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x60 "SPINLOCK_LOCK_REG_i_24,This register contains the state of one lock" hexmask.long 0x60 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x60 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x64 "SPINLOCK_LOCK_REG_i_25,This register contains the state of one lock" hexmask.long 0x64 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x64 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x68 "SPINLOCK_LOCK_REG_i_26,This register contains the state of one lock" hexmask.long 0x68 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x68 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x6C "SPINLOCK_LOCK_REG_i_27,This register contains the state of one lock" hexmask.long 0x6C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x6C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x70 "SPINLOCK_LOCK_REG_i_28,This register contains the state of one lock" hexmask.long 0x70 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x70 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x74 "SPINLOCK_LOCK_REG_i_29,This register contains the state of one lock" hexmask.long 0x74 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x74 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x78 "SPINLOCK_LOCK_REG_i_30,This register contains the state of one lock" hexmask.long 0x78 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x78 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x7C "SPINLOCK_LOCK_REG_i_31,This register contains the state of one lock" hexmask.long 0x7C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x7C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x80 "SPINLOCK_LOCK_REG_i_32,This register contains the state of one lock" hexmask.long 0x80 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x80 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x84 "SPINLOCK_LOCK_REG_i_33,This register contains the state of one lock" hexmask.long 0x84 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x84 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x88 "SPINLOCK_LOCK_REG_i_34,This register contains the state of one lock" hexmask.long 0x88 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x88 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x8C "SPINLOCK_LOCK_REG_i_35,This register contains the state of one lock" hexmask.long 0x8C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x8C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x90 "SPINLOCK_LOCK_REG_i_36,This register contains the state of one lock" hexmask.long 0x90 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x90 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x94 "SPINLOCK_LOCK_REG_i_37,This register contains the state of one lock" hexmask.long 0x94 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x94 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x98 "SPINLOCK_LOCK_REG_i_38,This register contains the state of one lock" hexmask.long 0x98 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x98 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x9C "SPINLOCK_LOCK_REG_i_39,This register contains the state of one lock" hexmask.long 0x9C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x9C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xA0 "SPINLOCK_LOCK_REG_i_40,This register contains the state of one lock" hexmask.long 0xA0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xA0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xA4 "SPINLOCK_LOCK_REG_i_41,This register contains the state of one lock" hexmask.long 0xA4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xA4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xA8 "SPINLOCK_LOCK_REG_i_42,This register contains the state of one lock" hexmask.long 0xA8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xA8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xAC "SPINLOCK_LOCK_REG_i_43,This register contains the state of one lock" hexmask.long 0xAC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xAC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xB0 "SPINLOCK_LOCK_REG_i_44,This register contains the state of one lock" hexmask.long 0xB0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xB0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xB4 "SPINLOCK_LOCK_REG_i_45,This register contains the state of one lock" hexmask.long 0xB4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xB4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xB8 "SPINLOCK_LOCK_REG_i_46,This register contains the state of one lock" hexmask.long 0xB8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xB8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xBC "SPINLOCK_LOCK_REG_i_47,This register contains the state of one lock" hexmask.long 0xBC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xBC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xC0 "SPINLOCK_LOCK_REG_i_48,This register contains the state of one lock" hexmask.long 0xC0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xC4 "SPINLOCK_LOCK_REG_i_49,This register contains the state of one lock" hexmask.long 0xC4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xC8 "SPINLOCK_LOCK_REG_i_50,This register contains the state of one lock" hexmask.long 0xC8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xCC "SPINLOCK_LOCK_REG_i_51,This register contains the state of one lock" hexmask.long 0xCC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xCC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xD0 "SPINLOCK_LOCK_REG_i_52,This register contains the state of one lock" hexmask.long 0xD0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xD0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xD4 "SPINLOCK_LOCK_REG_i_53,This register contains the state of one lock" hexmask.long 0xD4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xD4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xD8 "SPINLOCK_LOCK_REG_i_54,This register contains the state of one lock" hexmask.long 0xD8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xD8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xDC "SPINLOCK_LOCK_REG_i_55,This register contains the state of one lock" hexmask.long 0xDC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xDC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xE0 "SPINLOCK_LOCK_REG_i_56,This register contains the state of one lock" hexmask.long 0xE0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xE0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xE4 "SPINLOCK_LOCK_REG_i_57,This register contains the state of one lock" hexmask.long 0xE4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xE4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xE8 "SPINLOCK_LOCK_REG_i_58,This register contains the state of one lock" hexmask.long 0xE8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xE8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xEC "SPINLOCK_LOCK_REG_i_59,This register contains the state of one lock" hexmask.long 0xEC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xEC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xF0 "SPINLOCK_LOCK_REG_i_60,This register contains the state of one lock" hexmask.long 0xF0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xF0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xF4 "SPINLOCK_LOCK_REG_i_61,This register contains the state of one lock" hexmask.long 0xF4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xF4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xF8 "SPINLOCK_LOCK_REG_i_62,This register contains the state of one lock" hexmask.long 0xF8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xF8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xFC "SPINLOCK_LOCK_REG_i_63,This register contains the state of one lock" hexmask.long 0xFC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xFC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x100 "SPINLOCK_LOCK_REG_i_64,This register contains the state of one lock" hexmask.long 0x100 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x100 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x104 "SPINLOCK_LOCK_REG_i_65,This register contains the state of one lock" hexmask.long 0x104 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x104 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x108 "SPINLOCK_LOCK_REG_i_66,This register contains the state of one lock" hexmask.long 0x108 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x108 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x10C "SPINLOCK_LOCK_REG_i_67,This register contains the state of one lock" hexmask.long 0x10C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x10C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x110 "SPINLOCK_LOCK_REG_i_68,This register contains the state of one lock" hexmask.long 0x110 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x110 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x114 "SPINLOCK_LOCK_REG_i_69,This register contains the state of one lock" hexmask.long 0x114 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x114 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x118 "SPINLOCK_LOCK_REG_i_70,This register contains the state of one lock" hexmask.long 0x118 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x118 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x11C "SPINLOCK_LOCK_REG_i_71,This register contains the state of one lock" hexmask.long 0x11C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x11C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x120 "SPINLOCK_LOCK_REG_i_72,This register contains the state of one lock" hexmask.long 0x120 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x120 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x124 "SPINLOCK_LOCK_REG_i_73,This register contains the state of one lock" hexmask.long 0x124 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x124 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x128 "SPINLOCK_LOCK_REG_i_74,This register contains the state of one lock" hexmask.long 0x128 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x128 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x12C "SPINLOCK_LOCK_REG_i_75,This register contains the state of one lock" hexmask.long 0x12C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x12C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x130 "SPINLOCK_LOCK_REG_i_76,This register contains the state of one lock" hexmask.long 0x130 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x130 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x134 "SPINLOCK_LOCK_REG_i_77,This register contains the state of one lock" hexmask.long 0x134 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x134 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x138 "SPINLOCK_LOCK_REG_i_78,This register contains the state of one lock" hexmask.long 0x138 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x138 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x13C "SPINLOCK_LOCK_REG_i_79,This register contains the state of one lock" hexmask.long 0x13C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x13C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x140 "SPINLOCK_LOCK_REG_i_80,This register contains the state of one lock" hexmask.long 0x140 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x140 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x144 "SPINLOCK_LOCK_REG_i_81,This register contains the state of one lock" hexmask.long 0x144 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x144 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x148 "SPINLOCK_LOCK_REG_i_82,This register contains the state of one lock" hexmask.long 0x148 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x148 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x14C "SPINLOCK_LOCK_REG_i_83,This register contains the state of one lock" hexmask.long 0x14C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x14C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x150 "SPINLOCK_LOCK_REG_i_84,This register contains the state of one lock" hexmask.long 0x150 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x150 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x154 "SPINLOCK_LOCK_REG_i_85,This register contains the state of one lock" hexmask.long 0x154 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x154 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x158 "SPINLOCK_LOCK_REG_i_86,This register contains the state of one lock" hexmask.long 0x158 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x158 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x15C "SPINLOCK_LOCK_REG_i_87,This register contains the state of one lock" hexmask.long 0x15C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x15C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x160 "SPINLOCK_LOCK_REG_i_88,This register contains the state of one lock" hexmask.long 0x160 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x160 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x164 "SPINLOCK_LOCK_REG_i_89,This register contains the state of one lock" hexmask.long 0x164 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x164 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x168 "SPINLOCK_LOCK_REG_i_90,This register contains the state of one lock" hexmask.long 0x168 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x168 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x16C "SPINLOCK_LOCK_REG_i_91,This register contains the state of one lock" hexmask.long 0x16C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x16C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x170 "SPINLOCK_LOCK_REG_i_92,This register contains the state of one lock" hexmask.long 0x170 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x170 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x174 "SPINLOCK_LOCK_REG_i_93,This register contains the state of one lock" hexmask.long 0x174 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x174 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x178 "SPINLOCK_LOCK_REG_i_94,This register contains the state of one lock" hexmask.long 0x178 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x178 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x17C "SPINLOCK_LOCK_REG_i_95,This register contains the state of one lock" hexmask.long 0x17C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x17C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x180 "SPINLOCK_LOCK_REG_i_96,This register contains the state of one lock" hexmask.long 0x180 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x180 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x184 "SPINLOCK_LOCK_REG_i_97,This register contains the state of one lock" hexmask.long 0x184 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x184 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x188 "SPINLOCK_LOCK_REG_i_98,This register contains the state of one lock" hexmask.long 0x188 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x188 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x18C "SPINLOCK_LOCK_REG_i_99,This register contains the state of one lock" hexmask.long 0x18C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x18C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x190 "SPINLOCK_LOCK_REG_i_100,This register contains the state of one lock" hexmask.long 0x190 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x190 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x194 "SPINLOCK_LOCK_REG_i_101,This register contains the state of one lock" hexmask.long 0x194 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x194 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x198 "SPINLOCK_LOCK_REG_i_102,This register contains the state of one lock" hexmask.long 0x198 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x198 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x19C "SPINLOCK_LOCK_REG_i_103,This register contains the state of one lock" hexmask.long 0x19C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x19C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1A0 "SPINLOCK_LOCK_REG_i_104,This register contains the state of one lock" hexmask.long 0x1A0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1A0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1A4 "SPINLOCK_LOCK_REG_i_105,This register contains the state of one lock" hexmask.long 0x1A4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1A4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1A8 "SPINLOCK_LOCK_REG_i_106,This register contains the state of one lock" hexmask.long 0x1A8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1A8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1AC "SPINLOCK_LOCK_REG_i_107,This register contains the state of one lock" hexmask.long 0x1AC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1AC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1B0 "SPINLOCK_LOCK_REG_i_108,This register contains the state of one lock" hexmask.long 0x1B0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1B0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1B4 "SPINLOCK_LOCK_REG_i_109,This register contains the state of one lock" hexmask.long 0x1B4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1B4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1B8 "SPINLOCK_LOCK_REG_i_110,This register contains the state of one lock" hexmask.long 0x1B8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1B8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1BC "SPINLOCK_LOCK_REG_i_111,This register contains the state of one lock" hexmask.long 0x1BC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1BC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1C0 "SPINLOCK_LOCK_REG_i_112,This register contains the state of one lock" hexmask.long 0x1C0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1C4 "SPINLOCK_LOCK_REG_i_113,This register contains the state of one lock" hexmask.long 0x1C4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1C8 "SPINLOCK_LOCK_REG_i_114,This register contains the state of one lock" hexmask.long 0x1C8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1CC "SPINLOCK_LOCK_REG_i_115,This register contains the state of one lock" hexmask.long 0x1CC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1CC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1D0 "SPINLOCK_LOCK_REG_i_116,This register contains the state of one lock" hexmask.long 0x1D0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1D0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1D4 "SPINLOCK_LOCK_REG_i_117,This register contains the state of one lock" hexmask.long 0x1D4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1D4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1D8 "SPINLOCK_LOCK_REG_i_118,This register contains the state of one lock" hexmask.long 0x1D8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1D8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1DC "SPINLOCK_LOCK_REG_i_119,This register contains the state of one lock" hexmask.long 0x1DC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1DC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1E0 "SPINLOCK_LOCK_REG_i_120,This register contains the state of one lock" hexmask.long 0x1E0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1E0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1E4 "SPINLOCK_LOCK_REG_i_121,This register contains the state of one lock" hexmask.long 0x1E4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1E4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1E8 "SPINLOCK_LOCK_REG_i_122,This register contains the state of one lock" hexmask.long 0x1E8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1E8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1EC "SPINLOCK_LOCK_REG_i_123,This register contains the state of one lock" hexmask.long 0x1EC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1EC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1F0 "SPINLOCK_LOCK_REG_i_124,This register contains the state of one lock" hexmask.long 0x1F0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1F0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1F4 "SPINLOCK_LOCK_REG_i_125,This register contains the state of one lock" hexmask.long 0x1F4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1F4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1F8 "SPINLOCK_LOCK_REG_i_126,This register contains the state of one lock" hexmask.long 0x1F8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1F8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1FC "SPINLOCK_LOCK_REG_i_127,This register contains the state of one lock" hexmask.long 0x1FC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1FC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x200 "SPINLOCK_LOCK_REG_i_128,This register contains the state of one lock" hexmask.long 0x200 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x200 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x204 "SPINLOCK_LOCK_REG_i_129,This register contains the state of one lock" hexmask.long 0x204 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x204 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x208 "SPINLOCK_LOCK_REG_i_130,This register contains the state of one lock" hexmask.long 0x208 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x208 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x20C "SPINLOCK_LOCK_REG_i_131,This register contains the state of one lock" hexmask.long 0x20C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x20C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x210 "SPINLOCK_LOCK_REG_i_132,This register contains the state of one lock" hexmask.long 0x210 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x210 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x214 "SPINLOCK_LOCK_REG_i_133,This register contains the state of one lock" hexmask.long 0x214 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x214 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x218 "SPINLOCK_LOCK_REG_i_134,This register contains the state of one lock" hexmask.long 0x218 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x218 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x21C "SPINLOCK_LOCK_REG_i_135,This register contains the state of one lock" hexmask.long 0x21C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x21C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x220 "SPINLOCK_LOCK_REG_i_136,This register contains the state of one lock" hexmask.long 0x220 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x220 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x224 "SPINLOCK_LOCK_REG_i_137,This register contains the state of one lock" hexmask.long 0x224 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x224 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x228 "SPINLOCK_LOCK_REG_i_138,This register contains the state of one lock" hexmask.long 0x228 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x228 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x22C "SPINLOCK_LOCK_REG_i_139,This register contains the state of one lock" hexmask.long 0x22C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x22C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x230 "SPINLOCK_LOCK_REG_i_140,This register contains the state of one lock" hexmask.long 0x230 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x230 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x234 "SPINLOCK_LOCK_REG_i_141,This register contains the state of one lock" hexmask.long 0x234 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x234 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x238 "SPINLOCK_LOCK_REG_i_142,This register contains the state of one lock" hexmask.long 0x238 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x238 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x23C "SPINLOCK_LOCK_REG_i_143,This register contains the state of one lock" hexmask.long 0x23C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x23C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x240 "SPINLOCK_LOCK_REG_i_144,This register contains the state of one lock" hexmask.long 0x240 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x240 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x244 "SPINLOCK_LOCK_REG_i_145,This register contains the state of one lock" hexmask.long 0x244 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x244 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x248 "SPINLOCK_LOCK_REG_i_146,This register contains the state of one lock" hexmask.long 0x248 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x248 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x24C "SPINLOCK_LOCK_REG_i_147,This register contains the state of one lock" hexmask.long 0x24C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x24C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x250 "SPINLOCK_LOCK_REG_i_148,This register contains the state of one lock" hexmask.long 0x250 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x250 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x254 "SPINLOCK_LOCK_REG_i_149,This register contains the state of one lock" hexmask.long 0x254 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x254 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x258 "SPINLOCK_LOCK_REG_i_150,This register contains the state of one lock" hexmask.long 0x258 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x258 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x25C "SPINLOCK_LOCK_REG_i_151,This register contains the state of one lock" hexmask.long 0x25C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x25C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x260 "SPINLOCK_LOCK_REG_i_152,This register contains the state of one lock" hexmask.long 0x260 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x260 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x264 "SPINLOCK_LOCK_REG_i_153,This register contains the state of one lock" hexmask.long 0x264 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x264 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x268 "SPINLOCK_LOCK_REG_i_154,This register contains the state of one lock" hexmask.long 0x268 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x268 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x26C "SPINLOCK_LOCK_REG_i_155,This register contains the state of one lock" hexmask.long 0x26C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x26C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x270 "SPINLOCK_LOCK_REG_i_156,This register contains the state of one lock" hexmask.long 0x270 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x270 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x274 "SPINLOCK_LOCK_REG_i_157,This register contains the state of one lock" hexmask.long 0x274 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x274 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x278 "SPINLOCK_LOCK_REG_i_158,This register contains the state of one lock" hexmask.long 0x278 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x278 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x27C "SPINLOCK_LOCK_REG_i_159,This register contains the state of one lock" hexmask.long 0x27C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x27C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x280 "SPINLOCK_LOCK_REG_i_160,This register contains the state of one lock" hexmask.long 0x280 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x280 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x284 "SPINLOCK_LOCK_REG_i_161,This register contains the state of one lock" hexmask.long 0x284 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x284 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x288 "SPINLOCK_LOCK_REG_i_162,This register contains the state of one lock" hexmask.long 0x288 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x288 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x28C "SPINLOCK_LOCK_REG_i_163,This register contains the state of one lock" hexmask.long 0x28C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x28C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x290 "SPINLOCK_LOCK_REG_i_164,This register contains the state of one lock" hexmask.long 0x290 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x290 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x294 "SPINLOCK_LOCK_REG_i_165,This register contains the state of one lock" hexmask.long 0x294 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x294 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x298 "SPINLOCK_LOCK_REG_i_166,This register contains the state of one lock" hexmask.long 0x298 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x298 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x29C "SPINLOCK_LOCK_REG_i_167,This register contains the state of one lock" hexmask.long 0x29C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x29C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2A0 "SPINLOCK_LOCK_REG_i_168,This register contains the state of one lock" hexmask.long 0x2A0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2A0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2A4 "SPINLOCK_LOCK_REG_i_169,This register contains the state of one lock" hexmask.long 0x2A4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2A4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2A8 "SPINLOCK_LOCK_REG_i_170,This register contains the state of one lock" hexmask.long 0x2A8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2A8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2AC "SPINLOCK_LOCK_REG_i_171,This register contains the state of one lock" hexmask.long 0x2AC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2AC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2B0 "SPINLOCK_LOCK_REG_i_172,This register contains the state of one lock" hexmask.long 0x2B0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2B0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2B4 "SPINLOCK_LOCK_REG_i_173,This register contains the state of one lock" hexmask.long 0x2B4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2B4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2B8 "SPINLOCK_LOCK_REG_i_174,This register contains the state of one lock" hexmask.long 0x2B8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2B8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2BC "SPINLOCK_LOCK_REG_i_175,This register contains the state of one lock" hexmask.long 0x2BC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2BC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2C0 "SPINLOCK_LOCK_REG_i_176,This register contains the state of one lock" hexmask.long 0x2C0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2C4 "SPINLOCK_LOCK_REG_i_177,This register contains the state of one lock" hexmask.long 0x2C4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2C8 "SPINLOCK_LOCK_REG_i_178,This register contains the state of one lock" hexmask.long 0x2C8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2CC "SPINLOCK_LOCK_REG_i_179,This register contains the state of one lock" hexmask.long 0x2CC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2CC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2D0 "SPINLOCK_LOCK_REG_i_180,This register contains the state of one lock" hexmask.long 0x2D0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2D0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2D4 "SPINLOCK_LOCK_REG_i_181,This register contains the state of one lock" hexmask.long 0x2D4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2D4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2D8 "SPINLOCK_LOCK_REG_i_182,This register contains the state of one lock" hexmask.long 0x2D8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2D8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2DC "SPINLOCK_LOCK_REG_i_183,This register contains the state of one lock" hexmask.long 0x2DC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2DC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2E0 "SPINLOCK_LOCK_REG_i_184,This register contains the state of one lock" hexmask.long 0x2E0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2E0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2E4 "SPINLOCK_LOCK_REG_i_185,This register contains the state of one lock" hexmask.long 0x2E4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2E4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2E8 "SPINLOCK_LOCK_REG_i_186,This register contains the state of one lock" hexmask.long 0x2E8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2E8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2EC "SPINLOCK_LOCK_REG_i_187,This register contains the state of one lock" hexmask.long 0x2EC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2EC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2F0 "SPINLOCK_LOCK_REG_i_188,This register contains the state of one lock" hexmask.long 0x2F0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2F0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2F4 "SPINLOCK_LOCK_REG_i_189,This register contains the state of one lock" hexmask.long 0x2F4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2F4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2F8 "SPINLOCK_LOCK_REG_i_190,This register contains the state of one lock" hexmask.long 0x2F8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2F8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2FC "SPINLOCK_LOCK_REG_i_191,This register contains the state of one lock" hexmask.long 0x2FC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2FC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x300 "SPINLOCK_LOCK_REG_i_192,This register contains the state of one lock" hexmask.long 0x300 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x300 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x304 "SPINLOCK_LOCK_REG_i_193,This register contains the state of one lock" hexmask.long 0x304 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x304 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x308 "SPINLOCK_LOCK_REG_i_194,This register contains the state of one lock" hexmask.long 0x308 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x308 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x30C "SPINLOCK_LOCK_REG_i_195,This register contains the state of one lock" hexmask.long 0x30C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x30C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x310 "SPINLOCK_LOCK_REG_i_196,This register contains the state of one lock" hexmask.long 0x310 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x310 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x314 "SPINLOCK_LOCK_REG_i_197,This register contains the state of one lock" hexmask.long 0x314 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x314 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x318 "SPINLOCK_LOCK_REG_i_198,This register contains the state of one lock" hexmask.long 0x318 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x318 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x31C "SPINLOCK_LOCK_REG_i_199,This register contains the state of one lock" hexmask.long 0x31C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x31C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x320 "SPINLOCK_LOCK_REG_i_200,This register contains the state of one lock" hexmask.long 0x320 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x320 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x324 "SPINLOCK_LOCK_REG_i_201,This register contains the state of one lock" hexmask.long 0x324 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x324 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x328 "SPINLOCK_LOCK_REG_i_202,This register contains the state of one lock" hexmask.long 0x328 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x328 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x32C "SPINLOCK_LOCK_REG_i_203,This register contains the state of one lock" hexmask.long 0x32C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x32C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x330 "SPINLOCK_LOCK_REG_i_204,This register contains the state of one lock" hexmask.long 0x330 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x330 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x334 "SPINLOCK_LOCK_REG_i_205,This register contains the state of one lock" hexmask.long 0x334 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x334 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x338 "SPINLOCK_LOCK_REG_i_206,This register contains the state of one lock" hexmask.long 0x338 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x338 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x33C "SPINLOCK_LOCK_REG_i_207,This register contains the state of one lock" hexmask.long 0x33C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x33C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x340 "SPINLOCK_LOCK_REG_i_208,This register contains the state of one lock" hexmask.long 0x340 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x340 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x344 "SPINLOCK_LOCK_REG_i_209,This register contains the state of one lock" hexmask.long 0x344 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x344 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x348 "SPINLOCK_LOCK_REG_i_210,This register contains the state of one lock" hexmask.long 0x348 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x348 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x34C "SPINLOCK_LOCK_REG_i_211,This register contains the state of one lock" hexmask.long 0x34C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x34C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x350 "SPINLOCK_LOCK_REG_i_212,This register contains the state of one lock" hexmask.long 0x350 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x350 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x354 "SPINLOCK_LOCK_REG_i_213,This register contains the state of one lock" hexmask.long 0x354 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x354 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x358 "SPINLOCK_LOCK_REG_i_214,This register contains the state of one lock" hexmask.long 0x358 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x358 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x35C "SPINLOCK_LOCK_REG_i_215,This register contains the state of one lock" hexmask.long 0x35C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x35C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x360 "SPINLOCK_LOCK_REG_i_216,This register contains the state of one lock" hexmask.long 0x360 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x360 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x364 "SPINLOCK_LOCK_REG_i_217,This register contains the state of one lock" hexmask.long 0x364 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x364 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x368 "SPINLOCK_LOCK_REG_i_218,This register contains the state of one lock" hexmask.long 0x368 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x368 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x36C "SPINLOCK_LOCK_REG_i_219,This register contains the state of one lock" hexmask.long 0x36C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x36C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x370 "SPINLOCK_LOCK_REG_i_220,This register contains the state of one lock" hexmask.long 0x370 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x370 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x374 "SPINLOCK_LOCK_REG_i_221,This register contains the state of one lock" hexmask.long 0x374 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x374 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x378 "SPINLOCK_LOCK_REG_i_222,This register contains the state of one lock" hexmask.long 0x378 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x378 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x37C "SPINLOCK_LOCK_REG_i_223,This register contains the state of one lock" hexmask.long 0x37C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x37C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x380 "SPINLOCK_LOCK_REG_i_224,This register contains the state of one lock" hexmask.long 0x380 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x380 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x384 "SPINLOCK_LOCK_REG_i_225,This register contains the state of one lock" hexmask.long 0x384 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x384 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x388 "SPINLOCK_LOCK_REG_i_226,This register contains the state of one lock" hexmask.long 0x388 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x388 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x38C "SPINLOCK_LOCK_REG_i_227,This register contains the state of one lock" hexmask.long 0x38C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x38C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x390 "SPINLOCK_LOCK_REG_i_228,This register contains the state of one lock" hexmask.long 0x390 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x390 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x394 "SPINLOCK_LOCK_REG_i_229,This register contains the state of one lock" hexmask.long 0x394 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x394 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x398 "SPINLOCK_LOCK_REG_i_230,This register contains the state of one lock" hexmask.long 0x398 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x398 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x39C "SPINLOCK_LOCK_REG_i_231,This register contains the state of one lock" hexmask.long 0x39C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x39C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3A0 "SPINLOCK_LOCK_REG_i_232,This register contains the state of one lock" hexmask.long 0x3A0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3A0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3A4 "SPINLOCK_LOCK_REG_i_233,This register contains the state of one lock" hexmask.long 0x3A4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3A4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3A8 "SPINLOCK_LOCK_REG_i_234,This register contains the state of one lock" hexmask.long 0x3A8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3A8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3AC "SPINLOCK_LOCK_REG_i_235,This register contains the state of one lock" hexmask.long 0x3AC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3AC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3B0 "SPINLOCK_LOCK_REG_i_236,This register contains the state of one lock" hexmask.long 0x3B0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3B0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3B4 "SPINLOCK_LOCK_REG_i_237,This register contains the state of one lock" hexmask.long 0x3B4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3B4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3B8 "SPINLOCK_LOCK_REG_i_238,This register contains the state of one lock" hexmask.long 0x3B8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3B8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3BC "SPINLOCK_LOCK_REG_i_239,This register contains the state of one lock" hexmask.long 0x3BC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3BC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3C0 "SPINLOCK_LOCK_REG_i_240,This register contains the state of one lock" hexmask.long 0x3C0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3C4 "SPINLOCK_LOCK_REG_i_241,This register contains the state of one lock" hexmask.long 0x3C4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3C8 "SPINLOCK_LOCK_REG_i_242,This register contains the state of one lock" hexmask.long 0x3C8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3CC "SPINLOCK_LOCK_REG_i_243,This register contains the state of one lock" hexmask.long 0x3CC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3CC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3D0 "SPINLOCK_LOCK_REG_i_244,This register contains the state of one lock" hexmask.long 0x3D0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3D0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3D4 "SPINLOCK_LOCK_REG_i_245,This register contains the state of one lock" hexmask.long 0x3D4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3D4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3D8 "SPINLOCK_LOCK_REG_i_246,This register contains the state of one lock" hexmask.long 0x3D8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3D8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3DC "SPINLOCK_LOCK_REG_i_247,This register contains the state of one lock" hexmask.long 0x3DC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3DC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3E0 "SPINLOCK_LOCK_REG_i_248,This register contains the state of one lock" hexmask.long 0x3E0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3E0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3E4 "SPINLOCK_LOCK_REG_i_249,This register contains the state of one lock" hexmask.long 0x3E4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3E4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3E8 "SPINLOCK_LOCK_REG_i_250,This register contains the state of one lock" hexmask.long 0x3E8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3E8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3EC "SPINLOCK_LOCK_REG_i_251,This register contains the state of one lock" hexmask.long 0x3EC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3EC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3F0 "SPINLOCK_LOCK_REG_i_252,This register contains the state of one lock" hexmask.long 0x3F0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3F0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3F4 "SPINLOCK_LOCK_REG_i_253,This register contains the state of one lock" hexmask.long 0x3F4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3F4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3F8 "SPINLOCK_LOCK_REG_i_254,This register contains the state of one lock" hexmask.long 0x3F8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3F8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3FC "SPINLOCK_LOCK_REG_i_255,This register contains the state of one lock" hexmask.long 0x3FC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3FC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" width 0x0B tree.end tree "SPINLOCK_TARG" base ad:0x4A0F7000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_H,Error reporting" line.long 0x14 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x14 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x14 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x14 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x14 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x14 0. "OCP_RESET,L3 Reset" "0,1" width 0x0B tree.end tree "SS" base ad:0x48484000 rgroup.long 0x00++0x37 line.long 0x00 "CPSW_ID_VER,CPSW_3G ID version register" line.long 0x04 "CPSW_CONTROL,Switch control register" hexmask.long 0x04 5.--31. 1. "RESERVED," bitfld.long 0x04 4. "EEE_EN,EEE (Energy Efficient Ethernet) enable 0 - EEE is disabled" "0,1" newline bitfld.long 0x04 3. "DLR_EN,DLR enable" "DLR is disabled,DLR is disabled" bitfld.long 0x04 2. "RX_VLAN_ENCAP,Port 0 VLAN Encapsulation (egress)" "Port 0 receive packets (from CPSW_3G) are not..,Port 0 receive packets (from CPSW_3G) are VLAN.." newline bitfld.long 0x04 1. "VLAN_AWARE,VLAN Aware Mode" "CPSW_3G is in the VLAN unaware mode,CPSW_3G is in the VLAN aware mode" bitfld.long 0x04 0. "FIFO_LOOPBACK,FIFO Loopback Mode" "Loopback is disabled,FIFO Loopback mode enabled" line.long 0x08 "CPSW_SOFT_RESET,Soft reset register" hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the 3G logic (INT REGS CPPI and SPF modules) to be reset" "0,1" line.long 0x0C "CPSW_STAT_PORT_EN,Statistics port enable register" hexmask.long 0x0C 3.--31. 1. "RESERVED," bitfld.long 0x0C 2. "P2_STAT_EN,Port 2 (GMII2 and Port 2 FIFO) Statistics Enable" "Port 2 statistics are not enabled,Port 2 statistics are enabled" newline bitfld.long 0x0C 1. "P1_STAT_EN,Port 1 (GMII1 and Port 1 FIFO) Statistics Enable" "Port 1 statistics are not enabled,Port 1 statistics are enabled" bitfld.long 0x0C 0. "P0_STAT_EN,Port 0 Statistics Enable" "Port 0 statistics are not enabled,Port 0 statistics are enabled" line.long 0x10 "CPSW_PTYPE,Transmit priority type register" hexmask.long.word 0x10 22.--31. 1. "RESERVED," bitfld.long 0x10 21. "P2_PRI3_SHAPE_EN,Port 2 Queue Priority 3 Transmit Shape Enable - If there is only one shaping queue then it must be priority 3" "0,1" newline bitfld.long 0x10 20. "P2_PRI2_SHAPE_EN,Port 2 Queue Priority 2 Transmit Shape Enable - If there are two shaping queues then they must be priorities 3 and 2" "0,1" bitfld.long 0x10 19. "P2_PRI1_SHAPE_EN,Port 2 Queue Priority 1 Transmit Shape Enable - If there are three shaping queues all three bits should be set" "0,1" newline bitfld.long 0x10 18. "P1_PRI3_SHAPE_EN,Port 1 Queue Priority 3 Transmit Shape Enable - If there is only one shaping queue then it must be priority 3" "0,1" bitfld.long 0x10 17. "P1_PRI2_SHAPE_EN,Port 1 Queue Priority 2 Transmit Shape Enable- If there are two shaping queues then they must be priorities 3 and 2" "0,1" newline bitfld.long 0x10 16. "P1_PRI1_SHAPE_EN,Port 1 Queue Priority 1 Transmit Shape Enable- If there are three shaping queues all three bits should be set" "0,1" rbitfld.long 0x10 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x10 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate" "Port 2 priority type fixed,Port 2 priority type escalate Escalate should.." bitfld.long 0x10 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate" "Port 1 priority type fixed,Port 1 priority type escalate Escalate should.." newline bitfld.long 0x10 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate" "Port 0 priority type fixed,Port 0 priority type escalate Escalate should.." rbitfld.long 0x10 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--4. "ESC_PRI_LD_VAL,Escalate Priority Load Value When a port is in escalate priority this is the number of higher priority packets sent before the next lower priority is allowed to send a packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "CPSW_SOFT_IDLE,Software idle" hexmask.long 0x14 1.--31. 1. "RESERVED," bitfld.long 0x14 0. "SOFT_IDLE,Software Idle - Setting this bit causes the switch fabric to stop forwarding packets at the next start of packet" "0,1" line.long 0x18 "CPSW_THRU_RATE,Throughput rate" hexmask.long.word 0x18 16.--31. 1. "RESERVED," bitfld.long 0x18 12.--15. "SL_RX_THRU_RATE,CPGMAC_SL Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x18 4.--11. 1. "RESERVED," bitfld.long 0x18 0.--3. "CPDMA_THRU_RATE,CPDMA Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "CPSW_GAP_THRESH,CPGMAC_SL short gap threshold" hexmask.long 0x1C 5.--31. 1. "RESERVED," bitfld.long 0x1C 0.--4. "GAP_THRESH,CPGMAC_SL Short Gap Threshold - This is the CPGMAC_SL associated FIFO transmit block usage value for triggering TX_SHORT_GAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "CPSW_TX_START_WDS,Transmit start words" hexmask.long.tbyte 0x20 11.--31. 1. "RESERVED," hexmask.long.word 0x20 0.--10. 1. "TX_START_WDS,FIFO Packet Transmit (egress) Start Words" line.long 0x24 "CPSW_FLOW_CONTROL,Flow control" hexmask.long 0x24 3.--31. 1. "RESERVED," bitfld.long 0x24 2. "P2_FLOW_EN,Port 2 Receive flow control enable" "0,1" newline bitfld.long 0x24 1. "P1_FLOW_EN,Port 1 Receive flow control enable" "0,1" bitfld.long 0x24 0. "P0_FLOW_EN,Port 0 Receive flow control enable" "0,1" line.long 0x28 "CPSW_VLAN_LTYPE,LTYPE1 and LTYPE 2 Register" hexmask.long.word 0x28 16.--31. 1. "VLAN_LTYPE2,Time Sync VLAN LTYPE2 This VLAN LTYPE value is used for tx and rx" hexmask.long.word 0x28 0.--15. 1. "VLAN_LTYPE1,Time Sync VLAN LTYPE1 This VLAN LTYPE value is used for tx and rx" line.long 0x2C "CPSW_TS_LTYPE,VLAN_LTYPE1 and VLAN_LTYPE2 Register" hexmask.long.word 0x2C 16.--31. 1. "TS_LTYPE2,Time Sync LTYPE2 This is an Ethertype value to match for tx and rx time sync packets" hexmask.long.word 0x2C 0.--15. 1. "TS_LTYPE1,Time Sync LTYPE1 This is an ethertype value to match for tx and rx time sync packets" line.long 0x30 "CPSW_DLR_LTYPE,DLR LTYPE register" hexmask.long.word 0x30 16.--31. 1. "RESERVED," hexmask.long.word 0x30 0.--15. 1. "DLR_LTYPE,DLR LTYPE" line.long 0x34 "CPSW_EEE_PRESCALE,EEE Pre-scale Counter Load Value Register" hexmask.long.tbyte 0x34 12.--31. 1. "RESERVED," hexmask.long.word 0x34 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value - This value is loaded into the EEE pre-scale counter each time the pre-scale count decrements to zero" width 0x0B tree.end tree "STATERAM" base ad:0x48484A00 group.long 0x00++0x7F line.long 0x00 "TX0_HDP,CPDMA_STATERAM TX channel 0 head descriptor pointer" line.long 0x04 "TX1_HDP,CPDMA_STATERAM TX channel 1 head descriptor pointer" line.long 0x08 "TX2_HDP,CPDMA_STATERAM TX channel 2 head descriptor pointer" line.long 0x0C "TX3_HDP,CPDMA_STATERAM TX channel 3 head descriptor pointer" line.long 0x10 "TX4_HDP,CPDMA_STATERAM TX channel 4 head descriptor pointer" line.long 0x14 "TX5_HDP,CPDMA_STATERAM TX channel 5 head descriptor pointer" line.long 0x18 "TX6_HDP,CPDMA_STATERAM TX channel 6 head descriptor pointer" line.long 0x1C "TX7_HDP,CPDMA_STATERAM TX channel 7 head descriptor pointer" line.long 0x20 "RX0_HDP,CPDMA_STATERAM RX 0 channel 0 head descriptor pointer" line.long 0x24 "RX1_HDP,CPDMA_STATERAM RX 1 channel 1 head descriptor pointer" line.long 0x28 "RX2_HDP,CPDMA_STATERAM RX 2 channel 2 head descriptor pointer" line.long 0x2C "RX3_HDP,CPDMA_STATERAM RX 3 channel 3 head descriptor pointer" line.long 0x30 "RX4_HDP,CPDMA_STATERAM RX 4 channel 4 head descriptor pointer" line.long 0x34 "RX5_HDP,CPDMA_STATERAM RX 5 channel 5 head descriptor pointer" line.long 0x38 "RX6_HDP,CPDMA_STATERAM RX 6 channel 6 head desc pointer" line.long 0x3C "RX7_HDP,CPDMA_STATERAM RX 7 channel 7 head desc pointer" line.long 0x40 "TX0_CP,CPDMA_STATERAM TX channel 0 completion pointer register" line.long 0x44 "TX1_CP,CPDMA_STATERAM TX channel 1 completion pointer register" line.long 0x48 "TX2_CP,CPDMA_STATERAM TX channel 2 completion pointer register" line.long 0x4C "TX3_CP,CPDMA_STATERAM TX channel 3 completion pointer register" line.long 0x50 "TX4_CP,CPDMA_STATERAM TX channel 4 completion pointer register" line.long 0x54 "TX5_CP,CPDMA_STATERAM TX channel 5 completion pointer register" line.long 0x58 "TX6_CP,CPDMA_STATERAM TX channel 6 completion pointer register" line.long 0x5C "TX7_CP,CPDMA_STATERAM TX channel 7 completion pointer register" line.long 0x60 "RX0_CP,CPDMA_STATERAM RX channel 0 completion pointer register" line.long 0x64 "RX1_CP,CPDMA_STATERAM RX channel 1 completion pointer register" line.long 0x68 "RX2_CP,CPDMA_STATERAM RX channel 2 completion pointer register" line.long 0x6C "RX3_CP,CPDMA_STATERAM RX channel 3 completion pointer register" line.long 0x70 "RX4_CP,CPDMA_STATERAM RX channel 4 completion pointer register" line.long 0x74 "RX5_CP,CPDMA_STATERAM RX channel 5 completion pointer register" line.long 0x78 "RX6_CP,CPDMA_STATERAM RX channel 6 completion pointer register" line.long 0x7C "RX7_CP,CPDMA_STATERAM RX channel 7 completion pointer register" width 0x0B tree.end tree "STATS" base ad:0x48484900 group.long 0x00++0x27 line.long 0x00 "GOOD_RX_FRAMES,The total number of good frames received on the port" line.long 0x04 "BROADCAST_RX_FRAMES,The total number of good broadcast frames received on the port" line.long 0x08 "MULTICAST_RX_FRAMES,The total number of good multicast frames received on the port" line.long 0x0C "PAUSE_RX_FRAMES,The total number of IEEE 802.3X pause frames received by the port (whether acted upon or not)" line.long 0x10 "RX_CRC_ERRORS,The total number of frames received on the port that experienced a CRC error" line.long 0x14 "RX_ALIGN_CODE_ERRORS,The total number of frames received on the port that experienced an alignment error or code error" line.long 0x18 "OVERSIZE_RX_FRAMES,The total number of oversized frames received on the port" line.long 0x1C "RX_JABBERS,The total number of jabber frames received on the port" line.long 0x20 "UNDERSIZE_RX_FRAMES,The total number of undersized frames received on the port" line.long 0x24 "RX_FRAGMENTS,The total number of frame fragments received on the port" group.long 0x30++0x5F line.long 0x00 "RX_OCTETS,The total number of bytes in all good frames received on the port" line.long 0x04 "GOOD_TX_FRAMES,The total number of good frames received on the port" line.long 0x08 "BROADCAST_TX_FRAMES,The total number of good broadcast frames received on the port" line.long 0x0C "MULTICAST_TX_FRAMES,The total number of good multicast frames received on the port" line.long 0x10 "PAUSE_TX_FRAMES,This statistic indicates the number of IEEE 802.3X pause frames transmitted by the port" line.long 0x14 "DEFERRED_TX_FRAMES,The total number of frames transmitted on the port that first experienced deferment" line.long 0x18 "COLLISIONS,This statistic records the total number of times that the port experienced a collision" line.long 0x1C "SINGLE_COLLISION_TX_FRAMES,The total number of frames transmitted on the port that experienced exactly one collision" line.long 0x20 "MULTIPLE_COLLISION_TX_FRAMES,The total number of frames transmitted on the port that experienced multiple collisions" line.long 0x24 "EXCESSIVE_COLLISIONS,The total number of frames for which transmission was abandoned due to excessive collisions" line.long 0x28 "LATE_COLLISIONS,The total number of frames on the port for which transmission was abandoned because they experienced a late collision" line.long 0x2C "TX_UNDERRUN,There should be no transmitted frames that experience underrun" line.long 0x30 "CARRIER_SENSE_ERRORS,The total number of frames received on the port that had a CPDMA middle of frame (MOF) overrun" line.long 0x34 "TX_OCTETS,The total number of bytes in all good frames transmitted on the port" line.long 0x38 "RX_TX_64_OCTET_FRAMES,The total number of 64-byte frames received and transmitted on the port" line.long 0x3C "RX_TX_65_127_OCTET_FRAMES,The total number of frames of size 65 to 127 bytes received and transmitted on the port" line.long 0x40 "RX_TX_128_255_OCTET_FRAMES,The total number of frames of size 128 to 255 bytes received and transmitted on the port" line.long 0x44 "RX_TX_256_511_OCTET_FRAMES,The total number of frames of size 256 to 511 bytes received and transmitted on the port" line.long 0x48 "RX_TX_512_1023_OCTET_FRAMES,The total number of frames of size 512 to 1023 bytes received and transmitted on the port" line.long 0x4C "RX_TX_1024_UP_OCTET_FRAMES,The total number of frames of size 1024 to[13:0] RX_MAXLEN bytes for receive or 1024 up for transmit on the port" line.long 0x50 "NET_OCTETS,The total number of bytes of frame data received and transmitted on the port" line.long 0x54 "RX_START_OF_FRAME_OVERRUNS,The total number of frames received on the port that had a CPDMA start of frame (SOF) overrun or were dropped by due to FIFO resource limitations. or were dropped by the SPF" line.long 0x58 "RX_MIDDLE_OF_FRAME_OVERRUNS,The total number of frames received on the port that had a CPDMA middle of frame (MOF) overrun" line.long 0x5C "RX_DMA_OVERRUNS,The total number of frames received on the port that had either a DMA start of frame (SOF) overrun or a DMA MOF overrun" width 0x0B tree.end tree "SYS_EDMA_TPCC" base ad:0x43300000 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x04 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x04 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" newline rbitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x04 22.--23. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x04 19. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x04 15. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x04 11. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7" group.long 0xFC++0x113 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" line.long 0x04 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x04 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x08 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x08 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x0C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x10 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x14 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x18 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x1C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" hexmask.long.tbyte 0x20 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x20 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" hexmask.long.tbyte 0x24 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x24 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" hexmask.long.tbyte 0x28 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x28 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x28 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x2C "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.tbyte 0x2C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x2C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x2C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" hexmask.long.tbyte 0x30 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x30 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x30 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" hexmask.long.tbyte 0x34 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x34 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x34 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x38 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" hexmask.long.tbyte 0x38 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x38 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x38 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x3C "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" hexmask.long.tbyte 0x3C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x3C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x3C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" hexmask.long.tbyte 0x40 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x40 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x40 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x44 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" hexmask.long.tbyte 0x44 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x44 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x44 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x48 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" hexmask.long.tbyte 0x48 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x48 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x48 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x4C "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" hexmask.long.tbyte 0x4C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x4C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" hexmask.long.tbyte 0x50 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x50 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x50 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x54 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" hexmask.long.tbyte 0x54 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x54 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x54 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x58 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" hexmask.long.tbyte 0x58 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x58 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x58 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x5C "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" hexmask.long.tbyte 0x5C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x5C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x5C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x60 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" hexmask.long.tbyte 0x60 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x60 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x60 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x64 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" hexmask.long.tbyte 0x64 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x64 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x64 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x68 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" hexmask.long.tbyte 0x68 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x68 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x68 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x6C "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" hexmask.long.tbyte 0x6C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x6C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x6C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x70 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" hexmask.long.tbyte 0x70 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x70 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x70 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x74 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" hexmask.long.tbyte 0x74 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x74 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x74 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x78 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" hexmask.long.tbyte 0x78 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x78 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x78 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x7C "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" hexmask.long.tbyte 0x7C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x7C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x7C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x80 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" hexmask.long.tbyte 0x80 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x80 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x80 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x84 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" hexmask.long.tbyte 0x84 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x84 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x84 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x88 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" hexmask.long.tbyte 0x88 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x88 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x88 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x8C "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" hexmask.long.tbyte 0x8C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x8C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x8C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x90 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" hexmask.long.tbyte 0x90 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x90 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x90 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x94 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" hexmask.long.tbyte 0x94 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x94 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x94 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x98 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" hexmask.long.tbyte 0x98 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x98 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x98 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x9C "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" hexmask.long.tbyte 0x9C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x9C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x9C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA0 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA4 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA8 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xAC "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" hexmask.long.tbyte 0xAC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xAC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xAC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB0 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB4 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB8 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xBC "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" hexmask.long.tbyte 0xBC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xBC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xBC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC0 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC4 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC8 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xCC "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" hexmask.long.tbyte 0xCC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xCC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xCC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD0 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD4 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD8 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xDC "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" hexmask.long.tbyte 0xDC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xDC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xDC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE0 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE4 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE8 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xEC "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" hexmask.long.tbyte 0xEC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xEC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xEC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF0 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF4 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF8 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xFC "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" hexmask.long.tbyte 0xFC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xFC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xFC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x100 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" hexmask.long.tbyte 0x100 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x100 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x100 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x104 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x104 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x104 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x104 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x104 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x108 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x108 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x108 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x108 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x108 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x10C "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x10C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10C 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x10C 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x10C 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x110 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x110 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x110 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x110 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x110 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x240++0x23 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x00 31. "RESERVED,Reserved" "0,1" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 27. "RESERVED,Reserved" "0,1" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 23. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Reserved" "0,1" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 15. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x04 31. "RESERVED,Reserved" "0,1" bitfld.long 0x04 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 27. "RESERVED,Reserved" "0,1" bitfld.long 0x04 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 23. "RESERVED,Reserved" "0,1" bitfld.long 0x04 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED,Reserved" "0,1" bitfld.long 0x04 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 15. "RESERVED,Reserved" "0,1" bitfld.long 0x04 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 11. "RESERVED,Reserved" "0,1" bitfld.long 0x04 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED,Reserved" "0,1" bitfld.long 0x04 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x08 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x08 31. "RESERVED,Reserved" "0,1" bitfld.long 0x08 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 27. "RESERVED,Reserved" "0,1" bitfld.long 0x08 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 23. "RESERVED,Reserved" "0,1" bitfld.long 0x08 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED,Reserved" "0,1" bitfld.long 0x08 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 15. "RESERVED,Reserved" "0,1" bitfld.long 0x08 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 11. "RESERVED,Reserved" "0,1" bitfld.long 0x08 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED,Reserved" "0,1" bitfld.long 0x08 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x0C "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x0C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x10 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x10 31. "RESERVED,Reserved" "0,1" bitfld.long 0x10 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED,Reserved" "0,1" bitfld.long 0x10 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED,Reserved" "0,1" bitfld.long 0x10 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "RESERVED,Reserved" "0,1" bitfld.long 0x10 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 15. "RESERVED,Reserved" "0,1" bitfld.long 0x10 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 11. "RESERVED,Reserved" "0,1" bitfld.long 0x10 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" bitfld.long 0x10 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 3. "RESERVED,Reserved" "0,1" bitfld.long 0x10 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x14 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x14 31. "RESERVED,Reserved" "0,1" bitfld.long 0x14 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED,Reserved" "0,1" bitfld.long 0x14 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED,Reserved" "0,1" bitfld.long 0x14 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED,Reserved" "0,1" bitfld.long 0x14 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED,Reserved" "0,1" bitfld.long 0x14 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" bitfld.long 0x14 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED,Reserved" "0,1" bitfld.long 0x14 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x18 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x18 31. "RESERVED,Reserved" "0,1" bitfld.long 0x18 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED,Reserved" "0,1" bitfld.long 0x18 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED,Reserved" "0,1" bitfld.long 0x18 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED,Reserved" "0,1" bitfld.long 0x18 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED,Reserved" "0,1" bitfld.long 0x18 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED,Reserved" "0,1" bitfld.long 0x18 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED,Reserved" "0,1" bitfld.long 0x18 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED,Reserved" "0,1" bitfld.long 0x18 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x1C "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x1C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x20 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" rbitfld.long 0x20 31. "RESERVED," "0,1" bitfld.long 0x20 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 27. "RESERVED," "0,1" bitfld.long 0x20 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 23. "RESERVED," "0,1" bitfld.long 0x20 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 19. "RESERVED," "0,1" bitfld.long 0x20 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 15. "RESERVED," "0,1" bitfld.long 0x20 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 11. "RESERVED," "0,1" bitfld.long 0x20 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 7. "RESERVED," "0,1" bitfld.long 0x20 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 3. "RESERVED," "0,1" bitfld.long 0x20 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x280++0x07 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_QUEPRI,Queue Priority" hexmask.long 0x04 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" rgroup.long 0x300++0x23 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" newline bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" newline bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" newline bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" newline bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" newline bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" newline bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" newline bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" newline bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" newline bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" newline bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" newline bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" newline bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" newline bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" newline bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" newline bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" newline bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" newline bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" newline bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" newline bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" newline bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" line.long 0x08 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1" newline bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1" bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1" newline bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1" newline bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1" bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1" newline bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1" newline bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1" bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1" newline bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1" newline bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1" bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1" newline bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1" newline bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1" bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1" newline bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1" line.long 0x0C "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1" bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1" bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1" bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1" bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1" bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1" line.long 0x10 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,Event Missed #7" "0,1" newline bitfld.long 0x10 6. "E6,Event Missed #6" "0,1" bitfld.long 0x10 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x10 4. "E4,Event Missed #4" "0,1" bitfld.long 0x10 3. "E3,Event Missed #3" "0,1" newline bitfld.long 0x10 2. "E2,Event Missed #2" "0,1" bitfld.long 0x10 1. "E1,Event Missed #1" "0,1" newline bitfld.long 0x10 0. "E0,Event Missed #0" "0,1" line.long 0x14 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1" newline bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1" newline bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1" bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1" newline bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1" line.long 0x18 "EDMA_TPCC_CCERR,CC Error Register" hexmask.long.word 0x18 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 16. "TCERR,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register" "TCERR_0,TCERR_1" newline hexmask.long.byte 0x18 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD7_0,QTHRXCD7_1" newline bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD6_0,QTHRXCD6_1" bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD5_0,QTHRXCD5_1" newline bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD4_0,QTHRXCD4_1" bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD3_0,QTHRXCD3_1" newline bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD1_0,QTHRXCD1_1" newline bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x1C "EDMA_TPCC_CCERRCLR,CC Error Clear Register" hexmask.long.word 0x1C 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR" "0,1" newline hexmask.long.byte 0x1C 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect" "0,1" bitfld.long 0x1C 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect" "0,1" bitfld.long 0x1C 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" newline bitfld.long 0x1C 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect" "0,1" bitfld.long 0x1C 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" newline bitfld.long 0x1C 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect" "0,1" line.long 0x20 "EDMA_TPCC_EEVAL,Error Eval Register" hexmask.long 0x20 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 1. "SET,Error Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x20 0. "EVAL,Error Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x348++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x350++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x358++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x360++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x368++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x370++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x378++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x344++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x34C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x354++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x35C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x364++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x36C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x374++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x37C++0x23 line.long 0x00 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" line.long 0x04 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x04 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x04 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x04 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x04 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x04 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x04 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x04 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x08 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x08 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x08 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x08 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x08 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x08 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x08 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x08 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x0C "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x0C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x0C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x0C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x0C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x0C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x0C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x0C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x10 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x10 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x10 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x10 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x10 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x10 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x10 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x10 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x14 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x14 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x14 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x14 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x14 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x14 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x14 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x14 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x18 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x18 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x18 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x18 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x18 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x18 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x18 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x18 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x1C "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x1C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x1C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x1C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x1C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x1C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x1C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x1C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x20 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x20 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x20 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x20 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x20 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x20 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x20 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x20 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" rgroup.long 0x400++0x7F line.long 0x00 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x04 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x08 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x10 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x14 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x18 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x1C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x20 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x24 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x28 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x2C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x30 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x30 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x30 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x34 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x34 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x38 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x38 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x3C "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x3C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x40 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x40 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x44 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x44 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x44 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x48 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x48 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x48 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x4C "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x4C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x4C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x50 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x50 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x50 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x54 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x54 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x54 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x54 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x58 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x58 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x58 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x58 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x5C "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x5C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x5C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x5C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x60 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x60 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x60 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x60 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x64 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x64 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x64 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x64 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x68 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x68 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x68 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x68 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x6C "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x6C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x6C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x6C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x70 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x70 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x70 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x70 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x74 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x74 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x74 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x74 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x78 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x78 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x78 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x78 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x7C "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x7C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x7C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x7C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x600++0x07 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" line.long 0x04 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" hexmask.long.byte 0x04 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" rbitfld.long 0x00 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" rbitfld.long 0x04 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,reads return 0's" rbitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" newline rbitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" rbitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" newline rbitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" rbitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" newline bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2" rbitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" newline rbitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 14.--15. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" rbitfld.long 0x00 5.--7. "RESERVED,reads return 0's" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" rbitfld.long 0x00 3. "RESERVED,reads return 0's" "0,1" newline bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.." rbitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" newline rbitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" group.long 0x700++0x0B line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" hexmask.long.tbyte 0x00 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" line.long 0x08 "EDMA_TPCC_AETCMD,AET Command" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "CLR,AET Clear commandCPU writes 0x0 has no effect" "0,1" rgroup.long 0x800++0x2F line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" line.long 0x04 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" newline rbitfld.long 0x04 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" rbitfld.long 0x04 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" newline rbitfld.long 0x04 2. "URE,User Read Error" "URE_0,URE_1" rbitfld.long 0x04 1. "UWE,User Write Error" "UWE_0,UWE_1" newline rbitfld.long 0x04 0. "UXE,User Execute Error" "UXE_0,UXE_1" line.long 0x08 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" line.long 0x0C "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x0C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x0C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x0C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x0C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x0C 10. "AID0,Allowed ID 0" "AID0_0,AID0_1" bitfld.long 0x0C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x0C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x0C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x0C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x0C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x0C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x0C 0. "UX,User Execute permission" "UX_0,UX_1" line.long 0x10 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x10 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x10 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x10 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x10 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x10 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x10 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x10 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x10 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x10 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x10 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x10 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x10 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x10 0. "UX,User Execute permission" "UX_0,?" line.long 0x14 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x14 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x14 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x14 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x14 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x14 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x14 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x14 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x14 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x14 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x14 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x14 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x14 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x14 0. "UX,User Execute permission" "UX_0,?" line.long 0x18 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x18 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x18 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x18 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x18 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x18 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x18 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x18 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x18 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x18 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x18 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x18 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x18 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x18 0. "UX,User Execute permission" "UX_0,?" line.long 0x1C "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x1C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x1C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x1C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x1C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x1C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x1C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x1C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x1C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x1C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x1C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x1C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x1C 0. "UX,User Execute permission" "UX_0,?" line.long 0x20 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x20 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x20 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x20 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x20 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x20 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x20 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x20 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x20 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x20 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x20 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x20 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x20 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x20 0. "UX,User Execute permission" "UX_0,?" line.long 0x24 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x24 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x24 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x24 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x24 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x24 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x24 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x24 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x24 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x24 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x24 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x24 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x24 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x24 0. "UX,User Execute permission" "UX_0,?" line.long 0x28 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" hexmask.long.word 0x28 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x28 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x28 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x28 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x28 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x28 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x28 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x28 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x28 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x28 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x28 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x28 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x28 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x28 0. "UX,User Execute permission" "UX_0,?" line.long 0x2C "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" hexmask.long.word 0x2C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x2C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x2C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x2C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x2C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x2C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x2C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x2C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x2C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x2C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x2C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x2C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x2C 0. "UX,User Execute permission" "UX_0,?" rgroup.long 0x1000++0x47 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" newline bitfld.long 0x04 29. "E61,Event #61" "0,1" bitfld.long 0x04 28. "E60,Event #60" "0,1" newline bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" newline bitfld.long 0x04 23. "E55,Event #55" "0,1" bitfld.long 0x04 22. "E54,Event #54" "0,1" newline bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" newline bitfld.long 0x04 17. "E49,Event #49" "0,1" bitfld.long 0x04 16. "E48,Event #48" "0,1" newline bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" newline bitfld.long 0x04 11. "E43,Event #43" "0,1" bitfld.long 0x04 10. "E42,Event #42" "0,1" newline bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" newline bitfld.long 0x04 5. "E37,Event #37" "0,1" bitfld.long 0x04 4. "E36,Event #36" "0,1" newline bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" line.long 0x08 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event #31" "0,1" bitfld.long 0x08 30. "E30,Event #30" "0,1" newline bitfld.long 0x08 29. "E29,Event #29" "0,1" bitfld.long 0x08 28. "E28,Event #28" "0,1" newline bitfld.long 0x08 27. "E27,Event #27" "0,1" bitfld.long 0x08 26. "E26,Event #26" "0,1" newline bitfld.long 0x08 25. "E25,Event #25" "0,1" bitfld.long 0x08 24. "E24,Event #24" "0,1" newline bitfld.long 0x08 23. "E23,Event #23" "0,1" bitfld.long 0x08 22. "E22,Event #22" "0,1" newline bitfld.long 0x08 21. "E21,Event #21" "0,1" bitfld.long 0x08 20. "E20,Event #20" "0,1" newline bitfld.long 0x08 19. "E19,Event #19" "0,1" bitfld.long 0x08 18. "E18,Event #18" "0,1" newline bitfld.long 0x08 17. "E17,Event #17" "0,1" bitfld.long 0x08 16. "E16,Event #16" "0,1" newline bitfld.long 0x08 15. "E15,Event #15" "0,1" bitfld.long 0x08 14. "E14,Event #14" "0,1" newline bitfld.long 0x08 13. "E13,Event #13" "0,1" bitfld.long 0x08 12. "E12,Event #12" "0,1" newline bitfld.long 0x08 11. "E11,Event #11" "0,1" bitfld.long 0x08 10. "E10,Event #10" "0,1" newline bitfld.long 0x08 9. "E9,Event #9" "0,1" bitfld.long 0x08 8. "E8,Event #8" "0,1" newline bitfld.long 0x08 7. "E7,Event #7" "0,1" bitfld.long 0x08 6. "E6,Event #6" "0,1" newline bitfld.long 0x08 5. "E5,Event #5" "0,1" bitfld.long 0x08 4. "E4,Event #4" "0,1" newline bitfld.long 0x08 3. "E3,Event #3" "0,1" bitfld.long 0x08 2. "E2,Event #2" "0,1" newline bitfld.long 0x08 1. "E1,Event #1" "0,1" bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event #63" "0,1" bitfld.long 0x0C 30. "E62,Event #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event #61" "0,1" bitfld.long 0x0C 28. "E60,Event #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event #59" "0,1" bitfld.long 0x0C 26. "E58,Event #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event #57" "0,1" bitfld.long 0x0C 24. "E56,Event #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event #55" "0,1" bitfld.long 0x0C 22. "E54,Event #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event #53" "0,1" bitfld.long 0x0C 20. "E52,Event #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event #51" "0,1" bitfld.long 0x0C 18. "E50,Event #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event #49" "0,1" bitfld.long 0x0C 16. "E48,Event #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event #47" "0,1" bitfld.long 0x0C 14. "E46,Event #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event #45" "0,1" bitfld.long 0x0C 12. "E44,Event #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event #43" "0,1" bitfld.long 0x0C 10. "E42,Event #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event #41" "0,1" bitfld.long 0x0C 8. "E40,Event #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event #39" "0,1" bitfld.long 0x0C 6. "E38,Event #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event #37" "0,1" bitfld.long 0x0C 4. "E36,Event #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event #35" "0,1" bitfld.long 0x0C 2. "E34,Event #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event #33" "0,1" bitfld.long 0x0C 0. "E32,Event #32" "0,1" line.long 0x10 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x10 31. "E31,Event #31" "0,1" bitfld.long 0x10 30. "E30,Event #30" "0,1" newline bitfld.long 0x10 29. "E29,Event #29" "0,1" bitfld.long 0x10 28. "E28,Event #28" "0,1" newline bitfld.long 0x10 27. "E27,Event #27" "0,1" bitfld.long 0x10 26. "E26,Event #26" "0,1" newline bitfld.long 0x10 25. "E25,Event #25" "0,1" bitfld.long 0x10 24. "E24,Event #24" "0,1" newline bitfld.long 0x10 23. "E23,Event #23" "0,1" bitfld.long 0x10 22. "E22,Event #22" "0,1" newline bitfld.long 0x10 21. "E21,Event #21" "0,1" bitfld.long 0x10 20. "E20,Event #20" "0,1" newline bitfld.long 0x10 19. "E19,Event #19" "0,1" bitfld.long 0x10 18. "E18,Event #18" "0,1" newline bitfld.long 0x10 17. "E17,Event #17" "0,1" bitfld.long 0x10 16. "E16,Event #16" "0,1" newline bitfld.long 0x10 15. "E15,Event #15" "0,1" bitfld.long 0x10 14. "E14,Event #14" "0,1" newline bitfld.long 0x10 13. "E13,Event #13" "0,1" bitfld.long 0x10 12. "E12,Event #12" "0,1" newline bitfld.long 0x10 11. "E11,Event #11" "0,1" bitfld.long 0x10 10. "E10,Event #10" "0,1" newline bitfld.long 0x10 9. "E9,Event #9" "0,1" bitfld.long 0x10 8. "E8,Event #8" "0,1" newline bitfld.long 0x10 7. "E7,Event #7" "0,1" bitfld.long 0x10 6. "E6,Event #6" "0,1" newline bitfld.long 0x10 5. "E5,Event #5" "0,1" bitfld.long 0x10 4. "E4,Event #4" "0,1" newline bitfld.long 0x10 3. "E3,Event #3" "0,1" bitfld.long 0x10 2. "E2,Event #2" "0,1" newline bitfld.long 0x10 1. "E1,Event #1" "0,1" bitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x14 31. "E63,Event #63" "0,1" bitfld.long 0x14 30. "E62,Event #62" "0,1" newline bitfld.long 0x14 29. "E61,Event #61" "0,1" bitfld.long 0x14 28. "E60,Event #60" "0,1" newline bitfld.long 0x14 27. "E59,Event #59" "0,1" bitfld.long 0x14 26. "E58,Event #58" "0,1" newline bitfld.long 0x14 25. "E57,Event #57" "0,1" bitfld.long 0x14 24. "E56,Event #56" "0,1" newline bitfld.long 0x14 23. "E55,Event #55" "0,1" bitfld.long 0x14 22. "E54,Event #54" "0,1" newline bitfld.long 0x14 21. "E53,Event #53" "0,1" bitfld.long 0x14 20. "E52,Event #52" "0,1" newline bitfld.long 0x14 19. "E51,Event #51" "0,1" bitfld.long 0x14 18. "E50,Event #50" "0,1" newline bitfld.long 0x14 17. "E49,Event #49" "0,1" bitfld.long 0x14 16. "E48,Event #48" "0,1" newline bitfld.long 0x14 15. "E47,Event #47" "0,1" bitfld.long 0x14 14. "E46,Event #46" "0,1" newline bitfld.long 0x14 13. "E45,Event #45" "0,1" bitfld.long 0x14 12. "E44,Event #44" "0,1" newline bitfld.long 0x14 11. "E43,Event #43" "0,1" bitfld.long 0x14 10. "E42,Event #42" "0,1" newline bitfld.long 0x14 9. "E41,Event #41" "0,1" bitfld.long 0x14 8. "E40,Event #40" "0,1" newline bitfld.long 0x14 7. "E39,Event #39" "0,1" bitfld.long 0x14 6. "E38,Event #38" "0,1" newline bitfld.long 0x14 5. "E37,Event #37" "0,1" bitfld.long 0x14 4. "E36,Event #36" "0,1" newline bitfld.long 0x14 3. "E35,Event #35" "0,1" bitfld.long 0x14 2. "E34,Event #34" "0,1" newline bitfld.long 0x14 1. "E33,Event #33" "0,1" bitfld.long 0x14 0. "E32,Event #32" "0,1" line.long 0x18 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x18 31. "E31,Event #31" "0,1" bitfld.long 0x18 30. "E30,Event #30" "0,1" newline bitfld.long 0x18 29. "E29,Event #29" "0,1" bitfld.long 0x18 28. "E28,Event #28" "0,1" newline bitfld.long 0x18 27. "E27,Event #27" "0,1" bitfld.long 0x18 26. "E26,Event #26" "0,1" newline bitfld.long 0x18 25. "E25,Event #25" "0,1" bitfld.long 0x18 24. "E24,Event #24" "0,1" newline bitfld.long 0x18 23. "E23,Event #23" "0,1" bitfld.long 0x18 22. "E22,Event #22" "0,1" newline bitfld.long 0x18 21. "E21,Event #21" "0,1" bitfld.long 0x18 20. "E20,Event #20" "0,1" newline bitfld.long 0x18 19. "E19,Event #19" "0,1" bitfld.long 0x18 18. "E18,Event #18" "0,1" newline bitfld.long 0x18 17. "E17,Event #17" "0,1" bitfld.long 0x18 16. "E16,Event #16" "0,1" newline bitfld.long 0x18 15. "E15,Event #15" "0,1" bitfld.long 0x18 14. "E14,Event #14" "0,1" newline bitfld.long 0x18 13. "E13,Event #13" "0,1" bitfld.long 0x18 12. "E12,Event #12" "0,1" newline bitfld.long 0x18 11. "E11,Event #11" "0,1" bitfld.long 0x18 10. "E10,Event #10" "0,1" newline bitfld.long 0x18 9. "E9,Event #9" "0,1" bitfld.long 0x18 8. "E8,Event #8" "0,1" newline bitfld.long 0x18 7. "E7,Event #7" "0,1" bitfld.long 0x18 6. "E6,Event #6" "0,1" newline bitfld.long 0x18 5. "E5,Event #5" "0,1" bitfld.long 0x18 4. "E4,Event #4" "0,1" newline bitfld.long 0x18 3. "E3,Event #3" "0,1" bitfld.long 0x18 2. "E2,Event #2" "0,1" newline bitfld.long 0x18 1. "E1,Event #1" "0,1" bitfld.long 0x18 0. "E0,Event #0" "0,1" line.long 0x1C "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x1C 31. "E63,Event #63" "0,1" bitfld.long 0x1C 30. "E62,Event #62" "0,1" newline bitfld.long 0x1C 29. "E61,Event #61" "0,1" bitfld.long 0x1C 28. "E60,Event #60" "0,1" newline bitfld.long 0x1C 27. "E59,Event #59" "0,1" bitfld.long 0x1C 26. "E58,Event #58" "0,1" newline bitfld.long 0x1C 25. "E57,Event #57" "0,1" bitfld.long 0x1C 24. "E56,Event #56" "0,1" newline bitfld.long 0x1C 23. "E55,Event #55" "0,1" bitfld.long 0x1C 22. "E54,Event #54" "0,1" newline bitfld.long 0x1C 21. "E53,Event #53" "0,1" bitfld.long 0x1C 20. "E52,Event #52" "0,1" newline bitfld.long 0x1C 19. "E51,Event #51" "0,1" bitfld.long 0x1C 18. "E50,Event #50" "0,1" newline bitfld.long 0x1C 17. "E49,Event #49" "0,1" bitfld.long 0x1C 16. "E48,Event #48" "0,1" newline bitfld.long 0x1C 15. "E47,Event #47" "0,1" bitfld.long 0x1C 14. "E46,Event #46" "0,1" newline bitfld.long 0x1C 13. "E45,Event #45" "0,1" bitfld.long 0x1C 12. "E44,Event #44" "0,1" newline bitfld.long 0x1C 11. "E43,Event #43" "0,1" bitfld.long 0x1C 10. "E42,Event #42" "0,1" newline bitfld.long 0x1C 9. "E41,Event #41" "0,1" bitfld.long 0x1C 8. "E40,Event #40" "0,1" newline bitfld.long 0x1C 7. "E39,Event #39" "0,1" bitfld.long 0x1C 6. "E38,Event #38" "0,1" newline bitfld.long 0x1C 5. "E37,Event #37" "0,1" bitfld.long 0x1C 4. "E36,Event #36" "0,1" newline bitfld.long 0x1C 3. "E35,Event #35" "0,1" bitfld.long 0x1C 2. "E34,Event #34" "0,1" newline bitfld.long 0x1C 1. "E33,Event #33" "0,1" bitfld.long 0x1C 0. "E32,Event #32" "0,1" line.long 0x20 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x20 31. "E31,Event #31" "0,1" bitfld.long 0x20 30. "E30,Event #30" "0,1" newline bitfld.long 0x20 29. "E29,Event #29" "0,1" bitfld.long 0x20 28. "E28,Event #28" "0,1" newline bitfld.long 0x20 27. "E27,Event #27" "0,1" bitfld.long 0x20 26. "E26,Event #26" "0,1" newline bitfld.long 0x20 25. "E25,Event #25" "0,1" bitfld.long 0x20 24. "E24,Event #24" "0,1" newline bitfld.long 0x20 23. "E23,Event #23" "0,1" bitfld.long 0x20 22. "E22,Event #22" "0,1" newline bitfld.long 0x20 21. "E21,Event #21" "0,1" bitfld.long 0x20 20. "E20,Event #20" "0,1" newline bitfld.long 0x20 19. "E19,Event #19" "0,1" bitfld.long 0x20 18. "E18,Event #18" "0,1" newline bitfld.long 0x20 17. "E17,Event #17" "0,1" bitfld.long 0x20 16. "E16,Event #16" "0,1" newline bitfld.long 0x20 15. "E15,Event #15" "0,1" bitfld.long 0x20 14. "E14,Event #14" "0,1" newline bitfld.long 0x20 13. "E13,Event #13" "0,1" bitfld.long 0x20 12. "E12,Event #12" "0,1" newline bitfld.long 0x20 11. "E11,Event #11" "0,1" bitfld.long 0x20 10. "E10,Event #10" "0,1" newline bitfld.long 0x20 9. "E9,Event #9" "0,1" bitfld.long 0x20 8. "E8,Event #8" "0,1" newline bitfld.long 0x20 7. "E7,Event #7" "0,1" bitfld.long 0x20 6. "E6,Event #6" "0,1" newline bitfld.long 0x20 5. "E5,Event #5" "0,1" bitfld.long 0x20 4. "E4,Event #4" "0,1" newline bitfld.long 0x20 3. "E3,Event #3" "0,1" bitfld.long 0x20 2. "E2,Event #2" "0,1" newline bitfld.long 0x20 1. "E1,Event #1" "0,1" bitfld.long 0x20 0. "E0,Event #0" "0,1" line.long 0x24 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x24 31. "E63,Event #63" "0,1" bitfld.long 0x24 30. "E62,Event #62" "0,1" newline bitfld.long 0x24 29. "E61,Event #61" "0,1" bitfld.long 0x24 28. "E60,Event #60" "0,1" newline bitfld.long 0x24 27. "E59,Event #59" "0,1" bitfld.long 0x24 26. "E58,Event #58" "0,1" newline bitfld.long 0x24 25. "E57,Event #57" "0,1" bitfld.long 0x24 24. "E56,Event #56" "0,1" newline bitfld.long 0x24 23. "E55,Event #55" "0,1" bitfld.long 0x24 22. "E54,Event #54" "0,1" newline bitfld.long 0x24 21. "E53,Event #53" "0,1" bitfld.long 0x24 20. "E52,Event #52" "0,1" newline bitfld.long 0x24 19. "E51,Event #51" "0,1" bitfld.long 0x24 18. "E50,Event #50" "0,1" newline bitfld.long 0x24 17. "E49,Event #49" "0,1" bitfld.long 0x24 16. "E48,Event #48" "0,1" newline bitfld.long 0x24 15. "E47,Event #47" "0,1" bitfld.long 0x24 14. "E46,Event #46" "0,1" newline bitfld.long 0x24 13. "E45,Event #45" "0,1" bitfld.long 0x24 12. "E44,Event #44" "0,1" newline bitfld.long 0x24 11. "E43,Event #43" "0,1" bitfld.long 0x24 10. "E42,Event #42" "0,1" newline bitfld.long 0x24 9. "E41,Event #41" "0,1" bitfld.long 0x24 8. "E40,Event #40" "0,1" newline bitfld.long 0x24 7. "E39,Event #39" "0,1" bitfld.long 0x24 6. "E38,Event #38" "0,1" newline bitfld.long 0x24 5. "E37,Event #37" "0,1" bitfld.long 0x24 4. "E36,Event #36" "0,1" newline bitfld.long 0x24 3. "E35,Event #35" "0,1" bitfld.long 0x24 2. "E34,Event #34" "0,1" newline bitfld.long 0x24 1. "E33,Event #33" "0,1" bitfld.long 0x24 0. "E32,Event #32" "0,1" line.long 0x28 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x28 31. "E31,Event #31" "0,1" bitfld.long 0x28 30. "E30,Event #30" "0,1" newline bitfld.long 0x28 29. "E29,Event #29" "0,1" bitfld.long 0x28 28. "E28,Event #28" "0,1" newline bitfld.long 0x28 27. "E27,Event #27" "0,1" bitfld.long 0x28 26. "E26,Event #26" "0,1" newline bitfld.long 0x28 25. "E25,Event #25" "0,1" bitfld.long 0x28 24. "E24,Event #24" "0,1" newline bitfld.long 0x28 23. "E23,Event #23" "0,1" bitfld.long 0x28 22. "E22,Event #22" "0,1" newline bitfld.long 0x28 21. "E21,Event #21" "0,1" bitfld.long 0x28 20. "E20,Event #20" "0,1" newline bitfld.long 0x28 19. "E19,Event #19" "0,1" bitfld.long 0x28 18. "E18,Event #18" "0,1" newline bitfld.long 0x28 17. "E17,Event #17" "0,1" bitfld.long 0x28 16. "E16,Event #16" "0,1" newline bitfld.long 0x28 15. "E15,Event #15" "0,1" bitfld.long 0x28 14. "E14,Event #14" "0,1" newline bitfld.long 0x28 13. "E13,Event #13" "0,1" bitfld.long 0x28 12. "E12,Event #12" "0,1" newline bitfld.long 0x28 11. "E11,Event #11" "0,1" bitfld.long 0x28 10. "E10,Event #10" "0,1" newline bitfld.long 0x28 9. "E9,Event #9" "0,1" bitfld.long 0x28 8. "E8,Event #8" "0,1" newline bitfld.long 0x28 7. "E7,Event #7" "0,1" bitfld.long 0x28 6. "E6,Event #6" "0,1" newline bitfld.long 0x28 5. "E5,Event #5" "0,1" bitfld.long 0x28 4. "E4,Event #4" "0,1" newline bitfld.long 0x28 3. "E3,Event #3" "0,1" bitfld.long 0x28 2. "E2,Event #2" "0,1" newline bitfld.long 0x28 1. "E1,Event #1" "0,1" bitfld.long 0x28 0. "E0,Event #0" "0,1" line.long 0x2C "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x2C 31. "E63,Event #63" "0,1" bitfld.long 0x2C 30. "E62,Event #62" "0,1" newline bitfld.long 0x2C 29. "E61,Event #61" "0,1" bitfld.long 0x2C 28. "E60,Event #60" "0,1" newline bitfld.long 0x2C 27. "E59,Event #59" "0,1" bitfld.long 0x2C 26. "E58,Event #58" "0,1" newline bitfld.long 0x2C 25. "E57,Event #57" "0,1" bitfld.long 0x2C 24. "E56,Event #56" "0,1" newline bitfld.long 0x2C 23. "E55,Event #55" "0,1" bitfld.long 0x2C 22. "E54,Event #54" "0,1" newline bitfld.long 0x2C 21. "E53,Event #53" "0,1" bitfld.long 0x2C 20. "E52,Event #52" "0,1" newline bitfld.long 0x2C 19. "E51,Event #51" "0,1" bitfld.long 0x2C 18. "E50,Event #50" "0,1" newline bitfld.long 0x2C 17. "E49,Event #49" "0,1" bitfld.long 0x2C 16. "E48,Event #48" "0,1" newline bitfld.long 0x2C 15. "E47,Event #47" "0,1" bitfld.long 0x2C 14. "E46,Event #46" "0,1" newline bitfld.long 0x2C 13. "E45,Event #45" "0,1" bitfld.long 0x2C 12. "E44,Event #44" "0,1" newline bitfld.long 0x2C 11. "E43,Event #43" "0,1" bitfld.long 0x2C 10. "E42,Event #42" "0,1" newline bitfld.long 0x2C 9. "E41,Event #41" "0,1" bitfld.long 0x2C 8. "E40,Event #40" "0,1" newline bitfld.long 0x2C 7. "E39,Event #39" "0,1" bitfld.long 0x2C 6. "E38,Event #38" "0,1" newline bitfld.long 0x2C 5. "E37,Event #37" "0,1" bitfld.long 0x2C 4. "E36,Event #36" "0,1" newline bitfld.long 0x2C 3. "E35,Event #35" "0,1" bitfld.long 0x2C 2. "E34,Event #34" "0,1" newline bitfld.long 0x2C 1. "E33,Event #33" "0,1" bitfld.long 0x2C 0. "E32,Event #32" "0,1" line.long 0x30 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x30 31. "E31,Event #31" "0,1" bitfld.long 0x30 30. "E30,Event #30" "0,1" newline bitfld.long 0x30 29. "E29,Event #29" "0,1" bitfld.long 0x30 28. "E28,Event #28" "0,1" newline bitfld.long 0x30 27. "E27,Event #27" "0,1" bitfld.long 0x30 26. "E26,Event #26" "0,1" newline bitfld.long 0x30 25. "E25,Event #25" "0,1" bitfld.long 0x30 24. "E24,Event #24" "0,1" newline bitfld.long 0x30 23. "E23,Event #23" "0,1" bitfld.long 0x30 22. "E22,Event #22" "0,1" newline bitfld.long 0x30 21. "E21,Event #21" "0,1" bitfld.long 0x30 20. "E20,Event #20" "0,1" newline bitfld.long 0x30 19. "E19,Event #19" "0,1" bitfld.long 0x30 18. "E18,Event #18" "0,1" newline bitfld.long 0x30 17. "E17,Event #17" "0,1" bitfld.long 0x30 16. "E16,Event #16" "0,1" newline bitfld.long 0x30 15. "E15,Event #15" "0,1" bitfld.long 0x30 14. "E14,Event #14" "0,1" newline bitfld.long 0x30 13. "E13,Event #13" "0,1" bitfld.long 0x30 12. "E12,Event #12" "0,1" newline bitfld.long 0x30 11. "E11,Event #11" "0,1" bitfld.long 0x30 10. "E10,Event #10" "0,1" newline bitfld.long 0x30 9. "E9,Event #9" "0,1" bitfld.long 0x30 8. "E8,Event #8" "0,1" newline bitfld.long 0x30 7. "E7,Event #7" "0,1" bitfld.long 0x30 6. "E6,Event #6" "0,1" newline bitfld.long 0x30 5. "E5,Event #5" "0,1" bitfld.long 0x30 4. "E4,Event #4" "0,1" newline bitfld.long 0x30 3. "E3,Event #3" "0,1" bitfld.long 0x30 2. "E2,Event #2" "0,1" newline bitfld.long 0x30 1. "E1,Event #1" "0,1" bitfld.long 0x30 0. "E0,Event #0" "0,1" line.long 0x34 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x34 31. "E63,Event #63" "0,1" bitfld.long 0x34 30. "E62,Event #62" "0,1" newline bitfld.long 0x34 29. "E61,Event #61" "0,1" bitfld.long 0x34 28. "E60,Event #60" "0,1" newline bitfld.long 0x34 27. "E59,Event #59" "0,1" bitfld.long 0x34 26. "E58,Event #58" "0,1" newline bitfld.long 0x34 25. "E57,Event #57" "0,1" bitfld.long 0x34 24. "E56,Event #56" "0,1" newline bitfld.long 0x34 23. "E55,Event #55" "0,1" bitfld.long 0x34 22. "E54,Event #54" "0,1" newline bitfld.long 0x34 21. "E53,Event #53" "0,1" bitfld.long 0x34 20. "E52,Event #52" "0,1" newline bitfld.long 0x34 19. "E51,Event #51" "0,1" bitfld.long 0x34 18. "E50,Event #50" "0,1" newline bitfld.long 0x34 17. "E49,Event #49" "0,1" bitfld.long 0x34 16. "E48,Event #48" "0,1" newline bitfld.long 0x34 15. "E47,Event #47" "0,1" bitfld.long 0x34 14. "E46,Event #46" "0,1" newline bitfld.long 0x34 13. "E45,Event #45" "0,1" bitfld.long 0x34 12. "E44,Event #44" "0,1" newline bitfld.long 0x34 11. "E43,Event #43" "0,1" bitfld.long 0x34 10. "E42,Event #42" "0,1" newline bitfld.long 0x34 9. "E41,Event #41" "0,1" bitfld.long 0x34 8. "E40,Event #40" "0,1" newline bitfld.long 0x34 7. "E39,Event #39" "0,1" bitfld.long 0x34 6. "E38,Event #38" "0,1" newline bitfld.long 0x34 5. "E37,Event #37" "0,1" bitfld.long 0x34 4. "E36,Event #36" "0,1" newline bitfld.long 0x34 3. "E35,Event #35" "0,1" bitfld.long 0x34 2. "E34,Event #34" "0,1" newline bitfld.long 0x34 1. "E33,Event #33" "0,1" bitfld.long 0x34 0. "E32,Event #32" "0,1" line.long 0x38 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x38 31. "E31,Event #31" "0,1" bitfld.long 0x38 30. "E30,Event #30" "0,1" newline bitfld.long 0x38 29. "E29,Event #29" "0,1" bitfld.long 0x38 28. "E28,Event #28" "0,1" newline bitfld.long 0x38 27. "E27,Event #27" "0,1" bitfld.long 0x38 26. "E26,Event #26" "0,1" newline bitfld.long 0x38 25. "E25,Event #25" "0,1" bitfld.long 0x38 24. "E24,Event #24" "0,1" newline bitfld.long 0x38 23. "E23,Event #23" "0,1" bitfld.long 0x38 22. "E22,Event #22" "0,1" newline bitfld.long 0x38 21. "E21,Event #21" "0,1" bitfld.long 0x38 20. "E20,Event #20" "0,1" newline bitfld.long 0x38 19. "E19,Event #19" "0,1" bitfld.long 0x38 18. "E18,Event #18" "0,1" newline bitfld.long 0x38 17. "E17,Event #17" "0,1" bitfld.long 0x38 16. "E16,Event #16" "0,1" newline bitfld.long 0x38 15. "E15,Event #15" "0,1" bitfld.long 0x38 14. "E14,Event #14" "0,1" newline bitfld.long 0x38 13. "E13,Event #13" "0,1" bitfld.long 0x38 12. "E12,Event #12" "0,1" newline bitfld.long 0x38 11. "E11,Event #11" "0,1" bitfld.long 0x38 10. "E10,Event #10" "0,1" newline bitfld.long 0x38 9. "E9,Event #9" "0,1" bitfld.long 0x38 8. "E8,Event #8" "0,1" newline bitfld.long 0x38 7. "E7,Event #7" "0,1" bitfld.long 0x38 6. "E6,Event #6" "0,1" newline bitfld.long 0x38 5. "E5,Event #5" "0,1" bitfld.long 0x38 4. "E4,Event #4" "0,1" newline bitfld.long 0x38 3. "E3,Event #3" "0,1" bitfld.long 0x38 2. "E2,Event #2" "0,1" newline bitfld.long 0x38 1. "E1,Event #1" "0,1" bitfld.long 0x38 0. "E0,Event #0" "0,1" line.long 0x3C "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x3C 31. "E63,Event #63" "0,1" bitfld.long 0x3C 30. "E62,Event #62" "0,1" newline bitfld.long 0x3C 29. "E61,Event #61" "0,1" bitfld.long 0x3C 28. "E60,Event #60" "0,1" newline bitfld.long 0x3C 27. "E59,Event #59" "0,1" bitfld.long 0x3C 26. "E58,Event #58" "0,1" newline bitfld.long 0x3C 25. "E57,Event #57" "0,1" bitfld.long 0x3C 24. "E56,Event #56" "0,1" newline bitfld.long 0x3C 23. "E55,Event #55" "0,1" bitfld.long 0x3C 22. "E54,Event #54" "0,1" newline bitfld.long 0x3C 21. "E53,Event #53" "0,1" bitfld.long 0x3C 20. "E52,Event #52" "0,1" newline bitfld.long 0x3C 19. "E51,Event #51" "0,1" bitfld.long 0x3C 18. "E50,Event #50" "0,1" newline bitfld.long 0x3C 17. "E49,Event #49" "0,1" bitfld.long 0x3C 16. "E48,Event #48" "0,1" newline bitfld.long 0x3C 15. "E47,Event #47" "0,1" bitfld.long 0x3C 14. "E46,Event #46" "0,1" newline bitfld.long 0x3C 13. "E45,Event #45" "0,1" bitfld.long 0x3C 12. "E44,Event #44" "0,1" newline bitfld.long 0x3C 11. "E43,Event #43" "0,1" bitfld.long 0x3C 10. "E42,Event #42" "0,1" newline bitfld.long 0x3C 9. "E41,Event #41" "0,1" bitfld.long 0x3C 8. "E40,Event #40" "0,1" newline bitfld.long 0x3C 7. "E39,Event #39" "0,1" bitfld.long 0x3C 6. "E38,Event #38" "0,1" newline bitfld.long 0x3C 5. "E37,Event #37" "0,1" bitfld.long 0x3C 4. "E36,Event #36" "0,1" newline bitfld.long 0x3C 3. "E35,Event #35" "0,1" bitfld.long 0x3C 2. "E34,Event #34" "0,1" newline bitfld.long 0x3C 1. "E33,Event #33" "0,1" bitfld.long 0x3C 0. "E32,Event #32" "0,1" line.long 0x40 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x40 31. "E31,Event #31" "0,1" bitfld.long 0x40 30. "E30,Event #30" "0,1" newline bitfld.long 0x40 29. "E29,Event #29" "0,1" bitfld.long 0x40 28. "E28,Event #28" "0,1" newline bitfld.long 0x40 27. "E27,Event #27" "0,1" bitfld.long 0x40 26. "E26,Event #26" "0,1" newline bitfld.long 0x40 25. "E25,Event #25" "0,1" bitfld.long 0x40 24. "E24,Event #24" "0,1" newline bitfld.long 0x40 23. "E23,Event #23" "0,1" bitfld.long 0x40 22. "E22,Event #22" "0,1" newline bitfld.long 0x40 21. "E21,Event #21" "0,1" bitfld.long 0x40 20. "E20,Event #20" "0,1" newline bitfld.long 0x40 19. "E19,Event #19" "0,1" bitfld.long 0x40 18. "E18,Event #18" "0,1" newline bitfld.long 0x40 17. "E17,Event #17" "0,1" bitfld.long 0x40 16. "E16,Event #16" "0,1" newline bitfld.long 0x40 15. "E15,Event #15" "0,1" bitfld.long 0x40 14. "E14,Event #14" "0,1" newline bitfld.long 0x40 13. "E13,Event #13" "0,1" bitfld.long 0x40 12. "E12,Event #12" "0,1" newline bitfld.long 0x40 11. "E11,Event #11" "0,1" bitfld.long 0x40 10. "E10,Event #10" "0,1" newline bitfld.long 0x40 9. "E9,Event #9" "0,1" bitfld.long 0x40 8. "E8,Event #8" "0,1" newline bitfld.long 0x40 7. "E7,Event #7" "0,1" bitfld.long 0x40 6. "E6,Event #6" "0,1" newline bitfld.long 0x40 5. "E5,Event #5" "0,1" bitfld.long 0x40 4. "E4,Event #4" "0,1" newline bitfld.long 0x40 3. "E3,Event #3" "0,1" bitfld.long 0x40 2. "E2,Event #2" "0,1" newline bitfld.long 0x40 1. "E1,Event #1" "0,1" bitfld.long 0x40 0. "E0,Event #0" "0,1" line.long 0x44 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x44 31. "E63,Event #63" "0,1" bitfld.long 0x44 30. "E62,Event #62" "0,1" newline bitfld.long 0x44 29. "E61,Event #61" "0,1" bitfld.long 0x44 28. "E60,Event #60" "0,1" newline bitfld.long 0x44 27. "E59,Event #59" "0,1" bitfld.long 0x44 26. "E58,Event #58" "0,1" newline bitfld.long 0x44 25. "E57,Event #57" "0,1" bitfld.long 0x44 24. "E56,Event #56" "0,1" newline bitfld.long 0x44 23. "E55,Event #55" "0,1" bitfld.long 0x44 22. "E54,Event #54" "0,1" newline bitfld.long 0x44 21. "E53,Event #53" "0,1" bitfld.long 0x44 20. "E52,Event #52" "0,1" newline bitfld.long 0x44 19. "E51,Event #51" "0,1" bitfld.long 0x44 18. "E50,Event #50" "0,1" newline bitfld.long 0x44 17. "E49,Event #49" "0,1" bitfld.long 0x44 16. "E48,Event #48" "0,1" newline bitfld.long 0x44 15. "E47,Event #47" "0,1" bitfld.long 0x44 14. "E46,Event #46" "0,1" newline bitfld.long 0x44 13. "E45,Event #45" "0,1" bitfld.long 0x44 12. "E44,Event #44" "0,1" newline bitfld.long 0x44 11. "E43,Event #43" "0,1" bitfld.long 0x44 10. "E42,Event #42" "0,1" newline bitfld.long 0x44 9. "E41,Event #41" "0,1" bitfld.long 0x44 8. "E40,Event #40" "0,1" newline bitfld.long 0x44 7. "E39,Event #39" "0,1" bitfld.long 0x44 6. "E38,Event #38" "0,1" newline bitfld.long 0x44 5. "E37,Event #37" "0,1" bitfld.long 0x44 4. "E36,Event #36" "0,1" newline bitfld.long 0x44 3. "E35,Event #35" "0,1" bitfld.long 0x44 2. "E34,Event #34" "0,1" newline bitfld.long 0x44 1. "E33,Event #33" "0,1" bitfld.long 0x44 0. "E32,Event #32" "0,1" rgroup.long 0x1050++0x2B line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x08 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x0C "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x10 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x14 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x18 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x1C "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x20 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x24 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x28 "EDMA_TPCC_IEVAL,Interrupt Eval Register" hexmask.long 0x28 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" newline bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1080++0x17 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 7. "E7,Event #7" "0,1" newline rbitfld.long 0x04 6. "E6,Event #6" "0,1" rbitfld.long 0x04 5. "E5,Event #5" "0,1" newline rbitfld.long 0x04 4. "E4,Event #4" "0,1" rbitfld.long 0x04 3. "E3,Event #3" "0,1" newline rbitfld.long 0x04 2. "E2,Event #2" "0,1" rbitfld.long 0x04 1. "E1,Event #1" "0,1" newline rbitfld.long 0x04 0. "E0,Event #0" "0,1" line.long 0x08 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,Event #7" "0,1" newline bitfld.long 0x08 6. "E6,Event #6" "0,1" bitfld.long 0x08 5. "E5,Event #5" "0,1" newline bitfld.long 0x08 4. "E4,Event #4" "0,1" bitfld.long 0x08 3. "E3,Event #3" "0,1" newline bitfld.long 0x08 2. "E2,Event #2" "0,1" bitfld.long 0x08 1. "E1,Event #1" "0,1" newline bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,Event #7" "0,1" newline bitfld.long 0x0C 6. "E6,Event #6" "0,1" bitfld.long 0x0C 5. "E5,Event #5" "0,1" newline bitfld.long 0x0C 4. "E4,Event #4" "0,1" bitfld.long 0x0C 3. "E3,Event #3" "0,1" newline bitfld.long 0x0C 2. "E2,Event #2" "0,1" bitfld.long 0x0C 1. "E1,Event #1" "0,1" newline bitfld.long 0x0C 0. "E0,Event #0" "0,1" line.long 0x10 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 7. "E7,Event #7" "0,1" newline rbitfld.long 0x10 6. "E6,Event #6" "0,1" rbitfld.long 0x10 5. "E5,Event #5" "0,1" newline rbitfld.long 0x10 4. "E4,Event #4" "0,1" rbitfld.long 0x10 3. "E3,Event #3" "0,1" newline rbitfld.long 0x10 2. "E2,Event #2" "0,1" rbitfld.long 0x10 1. "E1,Event #1" "0,1" newline rbitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event #7" "0,1" newline bitfld.long 0x14 6. "E6,Event #6" "0,1" bitfld.long 0x14 5. "E5,Event #5" "0,1" newline bitfld.long 0x14 4. "E4,Event #4" "0,1" bitfld.long 0x14 3. "E3,Event #3" "0,1" newline bitfld.long 0x14 2. "E2,Event #2" "0,1" bitfld.long 0x14 1. "E1,Event #1" "0,1" newline bitfld.long 0x14 0. "E0,Event #0" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2200++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2600++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2204++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2604++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2208++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2608++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x220C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x260C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2210++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2610++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2214++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2614++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2218++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2618++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x221C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x261C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2220++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2620++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2224++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2624++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2228++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2628++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x222C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x262C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2230++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2630++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2234++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2634++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2238++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2638++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x223C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x263C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2240++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2640++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2244++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2644++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2250++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2650++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2254++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2654++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2258++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2658++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x225C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x265C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2260++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2660++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2264++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2664++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2268++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2668++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x226C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x266C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2270++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2670++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2274++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2674++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2278++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2678++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2A78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2C78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2E78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2280++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2680++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2284++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2684++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2288++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2688++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x228C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x268C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2290++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2690++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2294++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2694++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4020++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_1,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4060++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_3,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_5,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_6,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_7,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4100++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_8,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4120++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_9,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4140++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4160++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_11,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4180++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_12,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_13,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_14,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_15,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4200++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4220++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_17,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4240++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_18,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4260++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_19,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4280++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_20,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_21,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_22,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_23,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4300++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_24,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4320++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_25,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4340++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_26,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4360++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_27,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4380++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_28,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_29,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_30,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_31,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4400++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4420++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_33,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4440++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_34,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4460++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_35,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4480++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_36,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_37,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_38,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_39,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4500++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_40,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4520++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_41,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4540++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_42,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4560++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_43,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4580++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_44,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_45,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_46,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_47,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4600++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4620++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_49,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4640++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_50,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4660++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_51,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4680++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_52,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_53,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_54,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_55,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4700++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_56,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4720++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_57,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4740++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_58,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4760++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_59,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4780++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_60,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_61,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_62,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_63,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4800++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4820++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_65,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4840++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_66,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4860++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_67,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4880++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_68,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_69,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_70,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_71,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4900++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_72,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4920++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_73,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4940++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_74,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4960++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_75,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4980++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_76,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_77,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_78,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_79,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_81,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_82,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_83,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_84,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_85,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_86,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_87,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_88,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_89,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_90,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_91,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_92,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_93,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_94,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_95,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_96,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_97,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_98,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_99,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_101,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_102,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_103,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_104,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_105,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_106,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_107,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_108,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_109,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_110,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_111,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_113,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_114,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_115,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_116,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_117,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_118,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_119,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_120,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_121,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_122,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_123,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_124,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_125,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_126,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_127,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" group.long 0x4024++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_1,Source Address" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" group.long 0x4064++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_3,Source Address" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" group.long 0x40A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_5,Source Address" group.long 0x40C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_6,Source Address" group.long 0x40E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_7,Source Address" group.long 0x4104++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_8,Source Address" group.long 0x4124++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_9,Source Address" group.long 0x4144++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_10,Source Address" group.long 0x4164++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_11,Source Address" group.long 0x4184++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_12,Source Address" group.long 0x41A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_13,Source Address" group.long 0x41C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_14,Source Address" group.long 0x41E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_15,Source Address" group.long 0x4204++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_16,Source Address" group.long 0x4224++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_17,Source Address" group.long 0x4244++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_18,Source Address" group.long 0x4264++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_19,Source Address" group.long 0x4284++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_20,Source Address" group.long 0x42A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_21,Source Address" group.long 0x42C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_22,Source Address" group.long 0x42E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_23,Source Address" group.long 0x4304++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_24,Source Address" group.long 0x4324++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_25,Source Address" group.long 0x4344++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_26,Source Address" group.long 0x4364++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_27,Source Address" group.long 0x4384++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_28,Source Address" group.long 0x43A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_29,Source Address" group.long 0x43C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_30,Source Address" group.long 0x43E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_31,Source Address" group.long 0x4404++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_32,Source Address" group.long 0x4424++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_33,Source Address" group.long 0x4444++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_34,Source Address" group.long 0x4464++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_35,Source Address" group.long 0x4484++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_36,Source Address" group.long 0x44A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_37,Source Address" group.long 0x44C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_38,Source Address" group.long 0x44E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_39,Source Address" group.long 0x4504++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_40,Source Address" group.long 0x4524++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_41,Source Address" group.long 0x4544++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_42,Source Address" group.long 0x4564++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_43,Source Address" group.long 0x4584++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_44,Source Address" group.long 0x45A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_45,Source Address" group.long 0x45C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_46,Source Address" group.long 0x45E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_47,Source Address" group.long 0x4604++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_48,Source Address" group.long 0x4624++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_49,Source Address" group.long 0x4644++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_50,Source Address" group.long 0x4664++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_51,Source Address" group.long 0x4684++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_52,Source Address" group.long 0x46A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_53,Source Address" group.long 0x46C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_54,Source Address" group.long 0x46E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_55,Source Address" group.long 0x4704++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_56,Source Address" group.long 0x4724++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_57,Source Address" group.long 0x4744++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_58,Source Address" group.long 0x4764++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_59,Source Address" group.long 0x4784++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_60,Source Address" group.long 0x47A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_61,Source Address" group.long 0x47C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_62,Source Address" group.long 0x47E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_63,Source Address" group.long 0x4804++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_64,Source Address" group.long 0x4824++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_65,Source Address" group.long 0x4844++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_66,Source Address" group.long 0x4864++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_67,Source Address" group.long 0x4884++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_68,Source Address" group.long 0x48A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_69,Source Address" group.long 0x48C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_70,Source Address" group.long 0x48E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_71,Source Address" group.long 0x4904++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_72,Source Address" group.long 0x4924++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_73,Source Address" group.long 0x4944++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_74,Source Address" group.long 0x4964++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_75,Source Address" group.long 0x4984++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_76,Source Address" group.long 0x49A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_77,Source Address" group.long 0x49C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_78,Source Address" group.long 0x49E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_79,Source Address" group.long 0x4A04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_80,Source Address" group.long 0x4A24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_81,Source Address" group.long 0x4A44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_82,Source Address" group.long 0x4A64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_83,Source Address" group.long 0x4A84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_84,Source Address" group.long 0x4AA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_85,Source Address" group.long 0x4AC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_86,Source Address" group.long 0x4AE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_87,Source Address" group.long 0x4B04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_88,Source Address" group.long 0x4B24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_89,Source Address" group.long 0x4B44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_90,Source Address" group.long 0x4B64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_91,Source Address" group.long 0x4B84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_92,Source Address" group.long 0x4BA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_93,Source Address" group.long 0x4BC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_94,Source Address" group.long 0x4BE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_95,Source Address" group.long 0x4C04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_96,Source Address" group.long 0x4C24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_97,Source Address" group.long 0x4C44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_98,Source Address" group.long 0x4C64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_99,Source Address" group.long 0x4C84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_100,Source Address" group.long 0x4CA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_101,Source Address" group.long 0x4CC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_102,Source Address" group.long 0x4CE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_103,Source Address" group.long 0x4D04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_104,Source Address" group.long 0x4D24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_105,Source Address" group.long 0x4D44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_106,Source Address" group.long 0x4D64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_107,Source Address" group.long 0x4D84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_108,Source Address" group.long 0x4DA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_109,Source Address" group.long 0x4DC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_110,Source Address" group.long 0x4DE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_111,Source Address" group.long 0x4E04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_112,Source Address" group.long 0x4E24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_113,Source Address" group.long 0x4E44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_114,Source Address" group.long 0x4E64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_115,Source Address" group.long 0x4E84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_116,Source Address" group.long 0x4EA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_117,Source Address" group.long 0x4EC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_118,Source Address" group.long 0x4EE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_119,Source Address" group.long 0x4F04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_120,Source Address" group.long 0x4F24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_121,Source Address" group.long 0x4F44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_122,Source Address" group.long 0x4F64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_123,Source Address" group.long 0x4F84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_124,Source Address" group.long 0x4FA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_125,Source Address" group.long 0x4FC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_126,Source Address" group.long 0x4FE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_127,Source Address" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x402C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_1,Destination Address" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x406C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_3,Destination Address" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x40AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_5,Destination Address" group.long 0x40CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_6,Destination Address" group.long 0x40EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_7,Destination Address" group.long 0x410C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_8,Destination Address" group.long 0x412C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_9,Destination Address" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x416C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_11,Destination Address" group.long 0x418C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_12,Destination Address" group.long 0x41AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_13,Destination Address" group.long 0x41CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_14,Destination Address" group.long 0x41EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_15,Destination Address" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x422C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_17,Destination Address" group.long 0x424C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_18,Destination Address" group.long 0x426C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_19,Destination Address" group.long 0x428C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_20,Destination Address" group.long 0x42AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_21,Destination Address" group.long 0x42CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_22,Destination Address" group.long 0x42EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_23,Destination Address" group.long 0x430C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_24,Destination Address" group.long 0x432C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_25,Destination Address" group.long 0x434C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_26,Destination Address" group.long 0x436C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_27,Destination Address" group.long 0x438C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_28,Destination Address" group.long 0x43AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_29,Destination Address" group.long 0x43CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_30,Destination Address" group.long 0x43EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_31,Destination Address" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x442C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_33,Destination Address" group.long 0x444C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_34,Destination Address" group.long 0x446C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_35,Destination Address" group.long 0x448C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_36,Destination Address" group.long 0x44AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_37,Destination Address" group.long 0x44CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_38,Destination Address" group.long 0x44EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_39,Destination Address" group.long 0x450C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_40,Destination Address" group.long 0x452C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_41,Destination Address" group.long 0x454C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_42,Destination Address" group.long 0x456C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_43,Destination Address" group.long 0x458C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_44,Destination Address" group.long 0x45AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_45,Destination Address" group.long 0x45CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_46,Destination Address" group.long 0x45EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_47,Destination Address" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x462C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_49,Destination Address" group.long 0x464C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_50,Destination Address" group.long 0x466C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_51,Destination Address" group.long 0x468C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_52,Destination Address" group.long 0x46AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_53,Destination Address" group.long 0x46CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_54,Destination Address" group.long 0x46EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_55,Destination Address" group.long 0x470C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_56,Destination Address" group.long 0x472C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_57,Destination Address" group.long 0x474C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_58,Destination Address" group.long 0x476C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_59,Destination Address" group.long 0x478C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_60,Destination Address" group.long 0x47AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_61,Destination Address" group.long 0x47CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_62,Destination Address" group.long 0x47EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_63,Destination Address" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x482C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_65,Destination Address" group.long 0x484C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_66,Destination Address" group.long 0x486C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_67,Destination Address" group.long 0x488C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_68,Destination Address" group.long 0x48AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_69,Destination Address" group.long 0x48CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_70,Destination Address" group.long 0x48EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_71,Destination Address" group.long 0x490C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_72,Destination Address" group.long 0x492C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_73,Destination Address" group.long 0x494C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_74,Destination Address" group.long 0x496C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_75,Destination Address" group.long 0x498C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_76,Destination Address" group.long 0x49AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_77,Destination Address" group.long 0x49CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_78,Destination Address" group.long 0x49EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_79,Destination Address" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_81,Destination Address" group.long 0x4A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_82,Destination Address" group.long 0x4A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_83,Destination Address" group.long 0x4A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_84,Destination Address" group.long 0x4AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_85,Destination Address" group.long 0x4ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_86,Destination Address" group.long 0x4AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_87,Destination Address" group.long 0x4B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_88,Destination Address" group.long 0x4B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_89,Destination Address" group.long 0x4B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_90,Destination Address" group.long 0x4B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_91,Destination Address" group.long 0x4B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_92,Destination Address" group.long 0x4BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_93,Destination Address" group.long 0x4BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_94,Destination Address" group.long 0x4BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_95,Destination Address" group.long 0x4C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_96,Destination Address" group.long 0x4C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_97,Destination Address" group.long 0x4C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_98,Destination Address" group.long 0x4C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_99,Destination Address" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_101,Destination Address" group.long 0x4CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_102,Destination Address" group.long 0x4CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_103,Destination Address" group.long 0x4D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_104,Destination Address" group.long 0x4D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_105,Destination Address" group.long 0x4D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_106,Destination Address" group.long 0x4D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_107,Destination Address" group.long 0x4D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_108,Destination Address" group.long 0x4DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_109,Destination Address" group.long 0x4DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_110,Destination Address" group.long 0x4DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_111,Destination Address" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_113,Destination Address" group.long 0x4E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_114,Destination Address" group.long 0x4E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_115,Destination Address" group.long 0x4E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_116,Destination Address" group.long 0x4EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_117,Destination Address" group.long 0x4ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_118,Destination Address" group.long 0x4EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_119,Destination Address" group.long 0x4F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_120,Destination Address" group.long 0x4F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_121,Destination Address" group.long 0x4F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_122,Destination Address" group.long 0x4F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_123,Destination Address" group.long 0x4F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_124,Destination Address" group.long 0x4FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_125,Destination Address" group.long 0x4FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_126,Destination Address" group.long 0x4FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_127,Destination Address" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_1," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_3," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_5," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_6," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_7," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_8," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_9," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_11," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_12," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_13," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_14," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_15," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_17," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_18," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_19," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_20," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_21," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_22," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_23," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_24," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_25," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_26," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_27," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_28," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_29," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_30," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_31," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_33," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_34," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_35," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_36," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_37," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_38," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_39," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_40," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_41," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_42," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_43," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_44," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_45," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_46," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_47," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_49," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_50," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_51," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_52," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_53," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_54," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_55," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_56," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_57," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_58," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_59," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_60," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_61," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_62," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_63," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_65," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_66," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_67," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_68," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_69," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_70," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_71," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_72," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_73," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_74," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_75," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_76," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_77," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_78," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_79," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_81," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_82," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_83," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_84," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_85," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_86," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_87," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_88," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_89," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_90," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_91," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_92," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_93," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_94," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_95," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_96," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_97," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_98," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_99," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_101," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_102," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_103," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_104," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_105," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_106," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_107," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_108," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_109," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_110," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_111," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_113," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_114," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_115," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_116," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_117," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_118," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_119," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_120," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_121," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_122," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_123," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_124," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_125," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_126," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_127," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x403C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x407C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x411C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x413C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x417C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x419C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x423C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x425C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x427C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x429C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x431C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x433C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x435C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x437C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x439C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x443C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x445C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x447C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x449C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x451C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x453C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x455C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x457C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x459C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x463C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x465C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x467C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x469C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x471C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x473C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x475C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x477C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x479C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x483C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x485C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x487C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x489C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x491C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x493C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x495C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x497C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x499C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x43400000 ad:0x43500000 ) tree "SYS_EDMA_TPTC$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPTCn_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPTCn_TCCFG,TC Configuration Register" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 8.--9. "DREGDEPTH,Destination Register FIFO Depth Parameterization" "0,1,2,3" bitfld.long 0x04 6.--7. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" group.long 0x100++0x13 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 11.--12. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" rbitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" rbitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" line.long 0x04 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" rbitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x08 "EDMA_TPTCn_INTEN,Interrupt Enable Register" hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x0C "EDMA_TPTCn_INTCLR,Interrupt Clear Register" hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x10 "EDMA_TPTCn_INTCMD,Interrupt Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" group.long 0x120++0x13 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" rbitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 1. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" line.long 0x04 "EDMA_TPTCn_ERREN,Error Enable Register" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x04 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x04 1. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" line.long 0x08 "EDMA_TPTCn_ERRCLR,Error Clear Register" hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x08 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x08 1. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" line.long 0x0C "EDMA_TPTCn_ERRDET,Error Details Register" hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0C 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" rbitfld.long 0x0C 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 14.--15. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EDMA_TPTCn_ERRCMD,Error Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" group.long 0x200++0x17 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" rbitfld.long 0x00 21. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" rbitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "Highest priority,Priority 1,?,?,?,?,?,Lowest priority" newline rbitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" line.long 0x08 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count" line.long 0x0C "EDMA_TPTCn_PDST,Program Set Destination Address" line.long 0x10 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" line.long 0x14 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x240++0x23 line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" line.long 0x08 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" line.long 0x0C "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved. return 0x0 w/o AERROR" line.long 0x10 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" line.long 0x14 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" line.long 0x1C "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" line.long 0x20 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" group.long 0x280++0x0B line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" line.long 0x04 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" line.long 0x08 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" group.long 0x300++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x304++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x344++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x308++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x348++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x30C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x34C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x350++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" group.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x354++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end repeat.end tree "System_MMU" base ad:0x4881C000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Write 0's for future compatibility" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" rbitfld.long 0x00 5.--7. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x00 2. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" hexmask.long 0x08 5.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" newline bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0_w,EMUMISS_1_r" bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" hexmask.long 0x0C 5.--31. 1. "RESERVED,Write 0's for future compatibility Read returns 0" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" newline bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0,EMUMISS_1" bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" hexmask.long 0x00 1.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" hexmask.long 0x04 4.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable" "TWLENABLE_0,TWLENABLE_1" newline bitfld.long 0x04 1. "MMUENABLE,MMU enable" "MMUENABLE_0,MMUENABLE_1" rbitfld.long 0x04 0. "RESERVED,Write 0's for future compatibility" "0,1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" hexmask.long.byte 0x0C 0.--6. 1. "RESERVED,Write 0's for future compatibility" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 9. "RESERVED,Write 0's for future compatibility" "0,1" newline bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 0.--3. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" hexmask.long 0x14 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x18 4.--11. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x18 3. "P,Preserved bit" "P_0,P_1" newline bitfld.long 0x18 2. "V,Valid bit" "V_0,V_1" bitfld.long 0x18 0.--1. "PAGESIZE,Page size" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x1C 0.--11. 1. "RESERVED,Write 0's for future compatibility" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" hexmask.long 0x20 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" hexmask.long 0x24 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x28 4.--11. 1. "RESERVED,Reads return 0" bitfld.long 0x28 3. "P,Preserved bit" "P_0_r,P_1_r" newline bitfld.long 0x28 2. "V,Valid bit" "V_0_r,V_1_r" bitfld.long 0x28 0.--1. "PAGESIZE,Page size" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x2C 0.--11. 1. "RESERVED,Reads return 0" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" newline rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "0,1,2,3" bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "0,1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" hexmask.long.word 0x08 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 0.--15. 1. "RESERVED,Reserved" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 0.--15. 1. "RESERVED,Reserved" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 0.--15. 1. "RESERVED,Reserved" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the fourth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 0.--15. 1. "RESERVED,Reserved" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of fourth NO TRANSLATION REGION for 2D bursts" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" width 0x0B tree.end tree "TESOC" base ad:0x4B800000 rgroup.long 0x00++0x03 line.long 0x00 "TESOC_IP_REVISION,IP Revision Information" rgroup.long 0x10++0x03 line.long 0x00 "TESOC_IP_HWINFO,IP Hardware Information" group.long 0x20++0x03 line.long 0x00 "TESOC_IP_SYSCONFIG," group.long 0x80++0x03 line.long 0x00 "TESOC_INTR_EOI,End Of Interrupt register - Interrupt handler" group.long 0x90++0x03 line.long 0x00 "TESOC_INTR_STATUS_RAW_SET,Set Interrupt Status Raw register" group.long 0xA0++0x03 line.long 0x00 "TESOC_INTR_STATUS_ENABLED_CLEAR,This register contains status flags of the enabled interrupts" group.long 0xB0++0x03 line.long 0x00 "TESOC_INTR_ENABLE_SET,Interrupt enable register" group.long 0xC0++0x03 line.long 0x00 "TESOC_INTR_ENABLE_CLEAR,Interrupt clear register" group.long 0xD0++0x03 line.long 0x00 "TESOC_LOCK,LOCK Register" hexmask.long 0x00 4.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "LOCK,Lock feature prevents unintentional updates to TESOC registers" "?,?,?,?,?,Locked,?,?,?,?,Unlocked,?..." group.long 0xE0++0x03 line.long 0x00 "TESOC_ABORT,ABORT Register" hexmask.long 0x00 4.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "ABORT,This has to be written into by the software to abort field-test immediately and transfer control on test module to application" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xF0++0x03 line.long 0x00 "TESOC_BUSY,BUSY Register" hexmask.long 0x00 4.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "BUSY,During BUSY state" "Not busy..,?,?,?,?,Busy,?..." group.long 0x110++0x103 line.long 0x00 "TESOC_DIAG_INFO_0_i_0,Error Diagnostics Information Register bank" line.long 0x04 "TESOC_DIAG_INFO_0_i_1,Error Diagnostics Information Register bank" line.long 0x08 "TESOC_DIAG_INFO_0_i_2,Error Diagnostics Information Register bank" line.long 0x0C "TESOC_DIAG_INFO_0_i_3,Error Diagnostics Information Register bank" line.long 0x10 "TESOC_DIAG_INFO_1_i_0,Error Diagnostics Information Register bank" line.long 0x14 "TESOC_DIAG_INFO_1_i_1,Error Diagnostics Information Register bank" line.long 0x18 "TESOC_DIAG_INFO_1_i_2,Error Diagnostics Information Register bank" line.long 0x1C "TESOC_DIAG_INFO_1_i_3,Error Diagnostics Information Register bank" line.long 0x20 "TESOC_DIAG_INFO_2_i_0,Error Diagnostics Information Register bank" line.long 0x24 "TESOC_DIAG_INFO_2_i_1,Error Diagnostics Information Register bank" line.long 0x28 "TESOC_DIAG_INFO_2_i_2,Error Diagnostics Information Register bank" line.long 0x2C "TESOC_DIAG_INFO_2_i_3,Error Diagnostics Information Register bank" line.long 0x30 "TESOC_DIAG_INFO_3_i_0,Error Diagnostics Information Register bank" line.long 0x34 "TESOC_DIAG_INFO_3_i_1,Error Diagnostics Information Register bank" line.long 0x38 "TESOC_DIAG_INFO_3_i_2,Error Diagnostics Information Register bank" line.long 0x3C "TESOC_DIAG_INFO_3_i_3,Error Diagnostics Information Register bank" line.long 0x40 "TESOC_DIAG_INFO_4_i_0,Error Diagnostics Information Register bank" line.long 0x44 "TESOC_DIAG_INFO_4_i_1,Error Diagnostics Information Register bank" line.long 0x48 "TESOC_DIAG_INFO_4_i_2,Error Diagnostics Information Register bank" line.long 0x4C "TESOC_DIAG_INFO_4_i_3,Error Diagnostics Information Register bank" line.long 0x50 "TESOC_DIAG_INFO_5_i_0,Error Diagnostics Information Register bank" line.long 0x54 "TESOC_DIAG_INFO_5_i_1,Error Diagnostics Information Register bank" line.long 0x58 "TESOC_DIAG_INFO_5_i_2,Error Diagnostics Information Register bank" line.long 0x5C "TESOC_DIAG_INFO_5_i_3,Error Diagnostics Information Register bank" line.long 0x60 "TESOC_DIAG_INFO_6_i_0,Error Diagnostics Information Register bank" line.long 0x64 "TESOC_DIAG_INFO_6_i_1,Error Diagnostics Information Register bank" line.long 0x68 "TESOC_DIAG_INFO_6_i_2,Error Diagnostics Information Register bank" line.long 0x6C "TESOC_DIAG_INFO_6_i_3,Error Diagnostics Information Register bank" line.long 0x70 "TESOC_DIAG_INFO_7_i_0,Error Diagnostics Information Register bank" line.long 0x74 "TESOC_DIAG_INFO_7_i_1,Error Diagnostics Information Register bank" line.long 0x78 "TESOC_DIAG_INFO_7_i_2,Error Diagnostics Information Register bank" line.long 0x7C "TESOC_DIAG_INFO_7_i_3,Error Diagnostics Information Register bank" line.long 0x80 "TESOC_DIAG_INFO_8_i_0,Error Diagnostics Information Register bank" line.long 0x84 "TESOC_DIAG_INFO_8_i_1,Error Diagnostics Information Register bank" line.long 0x88 "TESOC_DIAG_INFO_8_i_2,Error Diagnostics Information Register bank" line.long 0x8C "TESOC_DIAG_INFO_8_i_3,Error Diagnostics Information Register bank" line.long 0x90 "TESOC_DIAG_INFO_9_i_0,Error Diagnostics Information Register bank" line.long 0x94 "TESOC_DIAG_INFO_9_i_1,Error Diagnostics Information Register bank" line.long 0x98 "TESOC_DIAG_INFO_9_i_2,Error Diagnostics Information Register bank" line.long 0x9C "TESOC_DIAG_INFO_9_i_3,Error Diagnostics Information Register bank" line.long 0xA0 "TESOC_DIAG_INFO_10_i_0,Error Diagnostics Information Register bank" line.long 0xA4 "TESOC_DIAG_INFO_10_i_1,Error Diagnostics Information Register bank" line.long 0xA8 "TESOC_DIAG_INFO_10_i_2,Error Diagnostics Information Register bank" line.long 0xAC "TESOC_DIAG_INFO_10_i_3,Error Diagnostics Information Register bank" line.long 0xB0 "TESOC_DIAG_INFO_11_i_0,Error Diagnostics Information Register bank" line.long 0xB4 "TESOC_DIAG_INFO_11_i_1,Error Diagnostics Information Register bank" line.long 0xB8 "TESOC_DIAG_INFO_11_i_2,Error Diagnostics Information Register bank" line.long 0xBC "TESOC_DIAG_INFO_11_i_3,Error Diagnostics Information Register bank" line.long 0xC0 "TESOC_DIAG_INFO_12_i_0,Error Diagnostics Information Register bank" line.long 0xC4 "TESOC_DIAG_INFO_12_i_1,Error Diagnostics Information Register bank" line.long 0xC8 "TESOC_DIAG_INFO_12_i_2,Error Diagnostics Information Register bank" line.long 0xCC "TESOC_DIAG_INFO_12_i_3,Error Diagnostics Information Register bank" line.long 0xD0 "TESOC_DIAG_INFO_13_i_0,Error Diagnostics Information Register bank" line.long 0xD4 "TESOC_DIAG_INFO_13_i_1,Error Diagnostics Information Register bank" line.long 0xD8 "TESOC_DIAG_INFO_13_i_2,Error Diagnostics Information Register bank" line.long 0xDC "TESOC_DIAG_INFO_13_i_3,Error Diagnostics Information Register bank" line.long 0xE0 "TESOC_DIAG_INFO_14_i_0,Error Diagnostics Information Register bank" line.long 0xE4 "TESOC_DIAG_INFO_14_i_1,Error Diagnostics Information Register bank" line.long 0xE8 "TESOC_DIAG_INFO_14_i_2,Error Diagnostics Information Register bank" line.long 0xEC "TESOC_DIAG_INFO_14_i_3,Error Diagnostics Information Register bank" line.long 0xF0 "TESOC_DIAG_INFO_15_i_0,Error Diagnostics Information Register bank" line.long 0xF4 "TESOC_DIAG_INFO_15_i_1,Error Diagnostics Information Register bank" line.long 0xF8 "TESOC_DIAG_INFO_15_i_2,Error Diagnostics Information Register bank" line.long 0xFC "TESOC_DIAG_INFO_15_i_3,Error Diagnostics Information Register bank" line.long 0x100 "TESOC_DOMAIN_EN_DOM0,Start Domain Register for domain PD_IPU" hexmask.long 0x100 1.--31. 1. "RESERVED," newline bitfld.long 0x100 0. "START_DOMAIN,This bitfield indicates that a particular processor can be moved into field-test mode" "Field test for domain PD_IPU is disabled,Field test for domain PD_IPU is enabled This.." group.long 0x220++0x03 line.long 0x00 "TESOC_DOMAIN_EN_DOM1,Start Domain Register for domain PD_EVE1" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "START_DOMAIN,This bitfield indicates that a particular processor can be moved into field-test mode" "Field test for domain PD_EVE1 is disabled,Field test for domain PD_EVE1 is enabled This.." group.long 0x230++0x03 line.long 0x00 "TESOC_DOMAIN_EN_DOM2,Start Domain Register for domain PD_DSP1" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "START_DOMAIN,This bitfield indicates that a particular processor can be moved into field-test mode" "Field test for domain PD_DSP1 is disabled,Field test for domain PD_DSP1 is enabled This.." group.long 0x240++0x03 line.long 0x00 "TESOC_DOMAIN_EN_DOM3,Start Domain Register for domain PD_DSP2" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "START_DOMAIN,This bitfield indicates that a particular processor can be moved into field-test mode" "Field test for domain PD_DSP2 is disabled,Field test for domain PD_DSP2 is enabled This.." group.long 0x250++0x03 line.long 0x00 "TESOC_DOMAIN_EN_DOM4,Start Domain Register for domains PD_ISS and PD_DSS" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "START_DOMAIN,This bitfield indicates that a particular processor can be moved into field-test mode" "Field test for domains PD_ISS and PD_DSS is..,Field test for domains PD_ISS and PD_DSS is.." group.long 0x260++0x1DF line.long 0x00 "TESOC_SLICE_CONFIG_DOM0_n_0,Slice Configuration Register" line.long 0x04 "TESOC_SLICE_CONFIG_DOM0_n_1,Slice Configuration Register" line.long 0x08 "TESOC_SLICE_CONFIG_DOM0_n_2,Slice Configuration Register" line.long 0x0C "TESOC_SLICE_CONFIG_DOM0_n_3,Slice Configuration Register" line.long 0x10 "TESOC_SLICE_CONFIG_DOM0_n_4,Slice Configuration Register" line.long 0x14 "TESOC_SLICE_CONFIG_DOM0_n_5,Slice Configuration Register" line.long 0x18 "TESOC_SLICE_CONFIG_DOM0_n_6,Slice Configuration Register" line.long 0x1C "TESOC_SLICE_CONFIG_DOM0_n_7,Slice Configuration Register" line.long 0x20 "TESOC_SLICE_CONFIG_DOM1_n_0,Slice Configuration Register" line.long 0x24 "TESOC_SLICE_CONFIG_DOM1_n_1,Slice Configuration Register" line.long 0x28 "TESOC_SLICE_CONFIG_DOM1_n_2,Slice Configuration Register" line.long 0x2C "TESOC_SLICE_CONFIG_DOM1_n_3,Slice Configuration Register" line.long 0x30 "TESOC_SLICE_CONFIG_DOM1_n_4,Slice Configuration Register" line.long 0x34 "TESOC_SLICE_CONFIG_DOM1_n_5,Slice Configuration Register" line.long 0x38 "TESOC_SLICE_CONFIG_DOM1_n_6,Slice Configuration Register" line.long 0x3C "TESOC_SLICE_CONFIG_DOM1_n_7,Slice Configuration Register" line.long 0x40 "TESOC_SLICE_CONFIG_DOM2_n_0,Slice Configuration Register" line.long 0x44 "TESOC_SLICE_CONFIG_DOM2_n_1,Slice Configuration Register" line.long 0x48 "TESOC_SLICE_CONFIG_DOM2_n_2,Slice Configuration Register" line.long 0x4C "TESOC_SLICE_CONFIG_DOM2_n_3,Slice Configuration Register" line.long 0x50 "TESOC_SLICE_CONFIG_DOM2_n_4,Slice Configuration Register" line.long 0x54 "TESOC_SLICE_CONFIG_DOM2_n_5,Slice Configuration Register" line.long 0x58 "TESOC_SLICE_CONFIG_DOM2_n_6,Slice Configuration Register" line.long 0x5C "TESOC_SLICE_CONFIG_DOM2_n_7,Slice Configuration Register" line.long 0x60 "TESOC_SLICE_CONFIG_DOM3_n_0,Slice Configuration Register" line.long 0x64 "TESOC_SLICE_CONFIG_DOM3_n_1,Slice Configuration Register" line.long 0x68 "TESOC_SLICE_CONFIG_DOM3_n_2,Slice Configuration Register" line.long 0x6C "TESOC_SLICE_CONFIG_DOM3_n_3,Slice Configuration Register" line.long 0x70 "TESOC_SLICE_CONFIG_DOM3_n_4,Slice Configuration Register" line.long 0x74 "TESOC_SLICE_CONFIG_DOM3_n_5,Slice Configuration Register" line.long 0x78 "TESOC_SLICE_CONFIG_DOM3_n_6,Slice Configuration Register" line.long 0x7C "TESOC_SLICE_CONFIG_DOM3_n_7,Slice Configuration Register" line.long 0x80 "TESOC_SLICE_CONFIG_DOM4_n_0,Slice Configuration Register" line.long 0x84 "TESOC_SLICE_CONFIG_DOM4_n_1,Slice Configuration Register" line.long 0x88 "TESOC_SLICE_CONFIG_DOM4_n_2,Slice Configuration Register" line.long 0x8C "TESOC_SLICE_CONFIG_DOM4_n_3,Slice Configuration Register" line.long 0x90 "TESOC_SLICE_CONFIG_DOM4_n_4,Slice Configuration Register" line.long 0x94 "TESOC_SLICE_CONFIG_DOM4_n_5,Slice Configuration Register" line.long 0x98 "TESOC_SLICE_CONFIG_DOM4_n_6,Slice Configuration Register" line.long 0x9C "TESOC_SLICE_CONFIG_DOM4_n_7,Slice Configuration Register" line.long 0xA0 "TESOC_SLICE_STATUS_DOM0_n_0,Slice Completion Status Register" line.long 0xA4 "TESOC_SLICE_STATUS_DOM0_n_1,Slice Completion Status Register" line.long 0xA8 "TESOC_SLICE_STATUS_DOM0_n_2,Slice Completion Status Register" line.long 0xAC "TESOC_SLICE_STATUS_DOM0_n_3,Slice Completion Status Register" line.long 0xB0 "TESOC_SLICE_STATUS_DOM0_n_4,Slice Completion Status Register" line.long 0xB4 "TESOC_SLICE_STATUS_DOM0_n_5,Slice Completion Status Register" line.long 0xB8 "TESOC_SLICE_STATUS_DOM0_n_6,Slice Completion Status Register" line.long 0xBC "TESOC_SLICE_STATUS_DOM0_n_7,Slice Completion Status Register" line.long 0xC0 "TESOC_SLICE_STATUS_DOM1_n_0,Slice Completion Status Register" line.long 0xC4 "TESOC_SLICE_STATUS_DOM1_n_1,Slice Completion Status Register" line.long 0xC8 "TESOC_SLICE_STATUS_DOM1_n_2,Slice Completion Status Register" line.long 0xCC "TESOC_SLICE_STATUS_DOM1_n_3,Slice Completion Status Register" line.long 0xD0 "TESOC_SLICE_STATUS_DOM1_n_4,Slice Completion Status Register" line.long 0xD4 "TESOC_SLICE_STATUS_DOM1_n_5,Slice Completion Status Register" line.long 0xD8 "TESOC_SLICE_STATUS_DOM1_n_6,Slice Completion Status Register" line.long 0xDC "TESOC_SLICE_STATUS_DOM1_n_7,Slice Completion Status Register" line.long 0xE0 "TESOC_SLICE_STATUS_DOM2_n_0,Slice Completion Status Register" line.long 0xE4 "TESOC_SLICE_STATUS_DOM2_n_1,Slice Completion Status Register" line.long 0xE8 "TESOC_SLICE_STATUS_DOM2_n_2,Slice Completion Status Register" line.long 0xEC "TESOC_SLICE_STATUS_DOM2_n_3,Slice Completion Status Register" line.long 0xF0 "TESOC_SLICE_STATUS_DOM2_n_4,Slice Completion Status Register" line.long 0xF4 "TESOC_SLICE_STATUS_DOM2_n_5,Slice Completion Status Register" line.long 0xF8 "TESOC_SLICE_STATUS_DOM2_n_6,Slice Completion Status Register" line.long 0xFC "TESOC_SLICE_STATUS_DOM2_n_7,Slice Completion Status Register" line.long 0x100 "TESOC_SLICE_STATUS_DOM3_n_0,Slice Completion Status Register" line.long 0x104 "TESOC_SLICE_STATUS_DOM3_n_1,Slice Completion Status Register" line.long 0x108 "TESOC_SLICE_STATUS_DOM3_n_2,Slice Completion Status Register" line.long 0x10C "TESOC_SLICE_STATUS_DOM3_n_3,Slice Completion Status Register" line.long 0x110 "TESOC_SLICE_STATUS_DOM3_n_4,Slice Completion Status Register" line.long 0x114 "TESOC_SLICE_STATUS_DOM3_n_5,Slice Completion Status Register" line.long 0x118 "TESOC_SLICE_STATUS_DOM3_n_6,Slice Completion Status Register" line.long 0x11C "TESOC_SLICE_STATUS_DOM3_n_7,Slice Completion Status Register" line.long 0x120 "TESOC_SLICE_STATUS_DOM4_n_0,Slice Completion Status Register" line.long 0x124 "TESOC_SLICE_STATUS_DOM4_n_1,Slice Completion Status Register" line.long 0x128 "TESOC_SLICE_STATUS_DOM4_n_2,Slice Completion Status Register" line.long 0x12C "TESOC_SLICE_STATUS_DOM4_n_3,Slice Completion Status Register" line.long 0x130 "TESOC_SLICE_STATUS_DOM4_n_4,Slice Completion Status Register" line.long 0x134 "TESOC_SLICE_STATUS_DOM4_n_5,Slice Completion Status Register" line.long 0x138 "TESOC_SLICE_STATUS_DOM4_n_6,Slice Completion Status Register" line.long 0x13C "TESOC_SLICE_STATUS_DOM4_n_7,Slice Completion Status Register" line.long 0x140 "TESOC_SLICE_RESULT_DOM0_n_0,Slice Result Register" line.long 0x144 "TESOC_SLICE_RESULT_DOM0_n_1,Slice Result Register" line.long 0x148 "TESOC_SLICE_RESULT_DOM0_n_2,Slice Result Register" line.long 0x14C "TESOC_SLICE_RESULT_DOM0_n_3,Slice Result Register" line.long 0x150 "TESOC_SLICE_RESULT_DOM0_n_4,Slice Result Register" line.long 0x154 "TESOC_SLICE_RESULT_DOM0_n_5,Slice Result Register" line.long 0x158 "TESOC_SLICE_RESULT_DOM0_n_6,Slice Result Register" line.long 0x15C "TESOC_SLICE_RESULT_DOM0_n_7,Slice Result Register" line.long 0x160 "TESOC_SLICE_RESULT_DOM1_n_0,Slice Result Register" line.long 0x164 "TESOC_SLICE_RESULT_DOM1_n_1,Slice Result Register" line.long 0x168 "TESOC_SLICE_RESULT_DOM1_n_2,Slice Result Register" line.long 0x16C "TESOC_SLICE_RESULT_DOM1_n_3,Slice Result Register" line.long 0x170 "TESOC_SLICE_RESULT_DOM1_n_4,Slice Result Register" line.long 0x174 "TESOC_SLICE_RESULT_DOM1_n_5,Slice Result Register" line.long 0x178 "TESOC_SLICE_RESULT_DOM1_n_6,Slice Result Register" line.long 0x17C "TESOC_SLICE_RESULT_DOM1_n_7,Slice Result Register" line.long 0x180 "TESOC_SLICE_RESULT_DOM2_n_0,Slice Result Register" line.long 0x184 "TESOC_SLICE_RESULT_DOM2_n_1,Slice Result Register" line.long 0x188 "TESOC_SLICE_RESULT_DOM2_n_2,Slice Result Register" line.long 0x18C "TESOC_SLICE_RESULT_DOM2_n_3,Slice Result Register" line.long 0x190 "TESOC_SLICE_RESULT_DOM2_n_4,Slice Result Register" line.long 0x194 "TESOC_SLICE_RESULT_DOM2_n_5,Slice Result Register" line.long 0x198 "TESOC_SLICE_RESULT_DOM2_n_6,Slice Result Register" line.long 0x19C "TESOC_SLICE_RESULT_DOM2_n_7,Slice Result Register" line.long 0x1A0 "TESOC_SLICE_RESULT_DOM3_n_0,Slice Result Register" line.long 0x1A4 "TESOC_SLICE_RESULT_DOM3_n_1,Slice Result Register" line.long 0x1A8 "TESOC_SLICE_RESULT_DOM3_n_2,Slice Result Register" line.long 0x1AC "TESOC_SLICE_RESULT_DOM3_n_3,Slice Result Register" line.long 0x1B0 "TESOC_SLICE_RESULT_DOM3_n_4,Slice Result Register" line.long 0x1B4 "TESOC_SLICE_RESULT_DOM3_n_5,Slice Result Register" line.long 0x1B8 "TESOC_SLICE_RESULT_DOM3_n_6,Slice Result Register" line.long 0x1BC "TESOC_SLICE_RESULT_DOM3_n_7,Slice Result Register" line.long 0x1C0 "TESOC_SLICE_RESULT_DOM4_n_0,Slice Result Register" line.long 0x1C4 "TESOC_SLICE_RESULT_DOM4_n_1,Slice Result Register" line.long 0x1C8 "TESOC_SLICE_RESULT_DOM4_n_2,Slice Result Register" line.long 0x1CC "TESOC_SLICE_RESULT_DOM4_n_3,Slice Result Register" line.long 0x1D0 "TESOC_SLICE_RESULT_DOM4_n_4,Slice Result Register" line.long 0x1D4 "TESOC_SLICE_RESULT_DOM4_n_5,Slice Result Register" line.long 0x1D8 "TESOC_SLICE_RESULT_DOM4_n_6,Slice Result Register" line.long 0x1DC "TESOC_SLICE_RESULT_DOM4_n_7,Slice Result Register" rgroup.long 0x10500++0x07 line.long 0x00 "TESOC_TESOC_ROM_k_0,This MMR space maps to TESOC ROM TESOC ROM is logically 64 bit wide" line.long 0x04 "TESOC_TESOC_ROM_k_1,This MMR space maps to TESOC ROM TESOC ROM is logically 64 bit wide" width 0x0B tree.end tree "TESOC_FW" base ad:0x4A240000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" newline rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "TESOC_FW_CFG_TARG" base ad:0x4A241000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TESOC_TARG" base ad:0x44001300 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "TIMER1_L4_WKUPInterconnect" base ad:0x4AE18000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 1. "EMUFREE,Emulation mode" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x4F line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" hexmask.long 0x04 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" newline bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQSTATUS_SET,Component interrupt-request enable" hexmask.long 0x0C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQSTATUS_CLR,Component interrupt-request enable" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" newline bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" newline bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "TCM_0,TCM_1,TCM_2,TCM_3" newline bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable" "CE_0,CE_1" newline bitfld.long 0x18 5. "PRE,Prescaler enable" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 1. "AR,Autoreload mode" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" newline bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" newline bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "0,1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "0,1" newline bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "0,1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "0,1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "0,1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode(POSTED = '1') this bit is not used" "READ_MODE_0,READ_MODE_1" newline bitfld.long 0x34 2. "POSTED,Posted mode selection" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" newline rbitfld.long 0x34 0. "RESERVED,Reserved" "0,1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" line.long 0x3C "TPIR,This register is used for 1-ms tick generation" line.long 0x40 "TNIR,This register is used for 1-ms tick generation" line.long 0x44 "TCVR,This register is used for 1-ms tick generation" line.long 0x48 "TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.byte 0x48 24.--31. 1. "RESERVED,Reads return 0" hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x4C "TOWR,This register holds the number of masked overflow interrupts" hexmask.long.byte 0x4C 24.--31. 1. "RESERVED,Reads return 0" hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" width 0x0B tree.end tree "TIMER1_TARG" base ad:0x4AE19000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER2_L4_PER1Interconnect" base ad:0x48032000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" hexmask.long 0x04 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" hexmask.long 0x0C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "TCM_0,TCM_1,TCM_2,TCM_3" newline bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" newline bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "0,1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "0,1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "0,1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "0,1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "0,1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode(POSTED = '1') this bit is not used" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" rbitfld.long 0x34 0. "RESERVED,Reserved" "0,1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER2_TARG" base ad:0x48033000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER3_L4_PER1Interconnect" base ad:0x48034000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" hexmask.long 0x04 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" hexmask.long 0x0C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "TCM_0,TCM_1,TCM_2,TCM_3" newline bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" newline bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "0,1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "0,1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "0,1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "0,1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "0,1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode(POSTED = '1') this bit is not used" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" rbitfld.long 0x34 0. "RESERVED,Reserved" "0,1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER3_TARG" base ad:0x48035000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER4_L4_PER1Interconnect" base ad:0x48036000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" hexmask.long 0x04 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" hexmask.long 0x0C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "TCM_0,TCM_1,TCM_2,TCM_3" newline bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" newline bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "0,1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "0,1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "0,1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "0,1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "0,1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode(POSTED = '1') this bit is not used" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" rbitfld.long 0x34 0. "RESERVED,Reserved" "0,1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER4_TARG" base ad:0x48037000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER5_L4_PER3Interconnect" base ad:0x48820000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" hexmask.long 0x04 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" hexmask.long 0x0C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "TCM_0,TCM_1,TCM_2,TCM_3" newline bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" newline bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "0,1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "0,1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "0,1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "0,1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "0,1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode(POSTED = '1') this bit is not used" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" rbitfld.long 0x34 0. "RESERVED,Reserved" "0,1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER5_TARG" base ad:0x48821000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER6_L4_PER3Interconnect" base ad:0x48822000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" hexmask.long 0x04 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" hexmask.long 0x0C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "TCM_0,TCM_1,TCM_2,TCM_3" newline bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" newline bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "0,1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "0,1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "0,1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "0,1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "0,1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode(POSTED = '1') this bit is not used" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" rbitfld.long 0x34 0. "RESERVED,Reserved" "0,1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER6_TARG" base ad:0x48823000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER7_L4_PER3Interconnect" base ad:0x48824000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" hexmask.long 0x04 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" hexmask.long 0x0C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "TCM_0,TCM_1,TCM_2,TCM_3" newline bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" newline bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "0,1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "0,1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "0,1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "0,1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "0,1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode(POSTED = '1') this bit is not used" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" rbitfld.long 0x34 0. "RESERVED,Reserved" "0,1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER7_TARG" base ad:0x48825000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER8_L4_PER3Interconnect" base ad:0x48826000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" hexmask.long 0x04 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" hexmask.long 0x0C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "TCM_0,TCM_1,TCM_2,TCM_3" newline bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" newline bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "0,1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "0,1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "0,1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "0,1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "0,1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode(POSTED = '1') this bit is not used" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" rbitfld.long 0x34 0. "RESERVED,Reserved" "0,1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER8_TARG" base ad:0x48827000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TPTC1_TARG" base ad:0x44002E00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "TPTC2_TARG" base ad:0x44002B00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "TPTC_FW" base ad:0x4A163000 group.long 0x00++0x03 line.long 0x00 "ERROR_LOG_k_0,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" group.long 0x10++0x03 line.long 0x00 "ERROR_LOG_k_1,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x04++0x03 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k_0,Logical Physical Address Error log register for port k" rgroup.long 0x14++0x03 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k_1,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x07 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" line.long 0x04 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x04 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x04 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x04 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "TSC_ADC_CFG_TARG" base ad:0x4A265000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TSC_ADC_FW_CFG_TARG" base ad:0x4A16E000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end repeat 3. (list 3. 1. 2. )(list ad:0x48020000 ad:0x4806A000 ad:0x4806C000 ) tree "UART$1" base $2 group.long 0x00++0x03 line.long 0x00 "UART_DLL,This register. with. stores the 14-bit divisor for generation of the baud clock in the baud rate generator" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x00 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value" rgroup.long 0x00++0x03 line.long 0x00 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x00 0.--7. 1. "RHR,Receive holding register" group.long 0x00++0x07 line.long 0x00 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Write has no effect" newline hexmask.long.byte 0x00 0.--7. 1. "THR,Transmit holding register" line.long 0x04 "UART_DLH,This register. with. stores the 14-bit divisor for generating the baud clock in the baud rate generator" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x04 6.--7. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x04 0.--5. "CLOCK_MSB,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x04++0x07 line.long 0x00 "UART_IER,Interrupt enable register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 7. "CTS_IT," "CTS_IT_0,CTS_IT_1" newline bitfld.long 0x00 6. "RTS_IT," "RTS_IT_0,RTS_IT_1" newline bitfld.long 0x00 5. "XOFF_IT," "XOFF_IT_0,XOFF_IT_1" newline bitfld.long 0x00 4. "SLEEP_MODE," "SLEEP_MODE_0,SLEEP_MODE_1" newline bitfld.long 0x00 3. "MODEM_STS_IT," "MODEM_STS_IT_0,MODEM_STS_IT_1" newline bitfld.long 0x00 2. "LINE_STS_IT," "LINE_STS_IT_0,LINE_STS_IT_1" newline bitfld.long 0x00 1. "THR_IT," "THR_IT_0,THR_IT_1" newline bitfld.long 0x00 0. "RHR_IT," "RHR_IT_0,RHR_IT_1" line.long 0x04 "UART_EFR,Enhanced feature register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x04 7. "AUTO_CTS_EN,Auto-CTS enable bit" "AUTO_CTS_EN_0,AUTO_CTS_EN_1" newline bitfld.long 0x04 6. "AUTO_RTS_EN,Auto-RTS enable bit" "AUTO_RTS_EN_0,AUTO_RTS_EN_1" newline bitfld.long 0x04 5. "SPECIAL_CHAR_DETECT," "SPECIAL_CHAR_DETECT_0,SPECIAL_CHAR_DETECT_1" newline bitfld.long 0x04 4. "ENHANCED_EN,Enhanced functions write enable bit" "ENHANCED_EN_0,ENHANCED_EN_1" newline bitfld.long 0x04 0.--3. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x08++0x03 line.long 0x00 "UART_FCR,FIFO control register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Write has no effect" newline bitfld.long 0x00 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If UART_SCR[7] = 0 and UART_TLR[7:4] =" "8 characters,16 characters,56 characters,60 characters If UART_SCR[7] = 0 and.." newline bitfld.long 0x00 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If UART_SCR[6] = 0 and UART_TLR[3:0] =" "8 spaces,16 spaces,32 spaces,56 spaces If UART_SCR[6].." newline bitfld.long 0x00 3. "DMA_MODE,This register is considered ifUART_SCR[0] = 0" "DMA_MODE_0_w,DMA_MODE_1_w" newline bitfld.long 0x00 2. "TX_FIFO_CLEAR," "TX_FIFO_CLEAR_0_w,TX_FIFO_CLEAR_1_w" newline bitfld.long 0x00 1. "RX_FIFO_CLEAR," "RX_FIFO_CLEAR_0_w,RX_FIFO_CLEAR_1_w" newline bitfld.long 0x00 0. "FIFO_EN," "FIFO_EN_0_w,FIFO_EN_1_w" rgroup.long 0x08++0x0B line.long 0x00 "UART_IIR,Interrupt identification register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 6.--7. "FCR_MIRROR,Mirror the contents ofUART_FCR[0] on both bits" "0,1,2,3" newline bitfld.long 0x00 1.--5. "IT_TYPE," "?,IT_TYPE_1_r,IT_TYPE_2_r,IT_TYPE_3_r,?,?,IT_TYPE_6_r,?,IT_TYPE_8_r,?,?,?,?,?,?,?,IT_TYPE_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 0. "IT_PENDING," "?,IT_PENDING_1_r" line.long 0x04 "UART_LCR,Line control register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x04 7. "DIV_EN," "DIV_EN_0,DIV_EN_1" newline bitfld.long 0x04 6. "BREAK_EN,Break control bit" "BREAK_EN_0,BREAK_EN_1" newline bitfld.long 0x04 5. "PARITY_TYPE2,Selects the forced parity format (ifUART_LCR[3] = 1)" "0,1" newline bitfld.long 0x04 4. "PARITY_TYPE1," "PARITY_TYPE1_0,PARITY_TYPE1_1" newline bitfld.long 0x04 3. "PARITY_EN," "?,PARITY_EN_1" newline bitfld.long 0x04 2. "NB_STOP,Specifies the number of stop-bits" "NB_STOP_0,NB_STOP_1" newline bitfld.long 0x04 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "CHAR_LENGTH_0,CHAR_LENGTH_1,CHAR_LENGTH_2,CHAR_LENGTH_3" line.long 0x08 "UART_MCR,Modem control register" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 7. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x08 6. "TCR_TLR," "?,TCR_TLR_1" newline bitfld.long 0x08 5. "XON_EN," "?,XON_EN_1" newline bitfld.long 0x08 4. "LOOPBACK_EN," "?,LOOPBACK_EN_1" newline bitfld.long 0x08 3. "CD_STS_CH," "?,CD_STS_CH_1" newline bitfld.long 0x08 2. "RI_STS_CH," "?,RI_STS_CH_1" newline bitfld.long 0x08 1. "RTS,In loopback controls theUART_MSR[4] bit" "RTS_0,RTS_1" newline bitfld.long 0x08 0. "DTR," "?,DTR_1" group.long 0x10++0x07 line.long 0x00 "UART_XON1_ADDR1,UART mode: XON1 character" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x00 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes" line.long 0x04 "UART_LSR,Line status register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x04 7. "RX_FIFO_STS," "?,RX_FIFO_STS_1_r" newline bitfld.long 0x04 6. "TX_SR_E," "?,TX_SR_E_1_r" newline bitfld.long 0x04 5. "TX_FIFO_E," "?,TX_FIFO_E_1_r" newline bitfld.long 0x04 4. "RX_BI," "?,RX_BI_1_r" newline bitfld.long 0x04 3. "RX_FE," "?,RX_FE_1_r" newline bitfld.long 0x04 2. "RX_PE," "?,RX_PE_1_r" newline bitfld.long 0x04 1. "RX_OE," "?,RX_OE_1_r" newline bitfld.long 0x04 0. "RX_FIFO_E," "?,RX_FIFO_E_1_r" group.long 0x14++0x07 line.long 0x00 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x00 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes" line.long 0x04 "UART_MSR,Modem status register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x04 7. "NCD_STS,This bit is the complement of the DCD* input" "0,1" newline bitfld.long 0x04 6. "NRI_STS,This bit is the complement of the RI* input" "0,1" newline bitfld.long 0x04 5. "NDSR_STS,This bit is the complement of the DSR* input" "0,1" newline bitfld.long 0x04 4. "NCTS_STS,This bit is the complement of the CTS* input" "0,1" newline bitfld.long 0x04 3. "DCD_STS,Indicates that DCD* input (orUART_MCR[3] in loopback) changed" "0,1" newline bitfld.long 0x04 2. "RI_STS,Indicates that RI* input (orUART_MCR[2] in loopback) changed state from low to high" "0,1" newline bitfld.long 0x04 1. "DSR_STS," "?,DSR_STS_1_r" newline bitfld.long 0x04 0. "CTS_STS," "?,CTS_STS_1_r" group.long 0x18++0x03 line.long 0x00 "UART_TCR,Transmission control register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x07 line.long 0x00 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes" line.long 0x04 "UART_SPR,Scratchpad register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x04 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x03 line.long 0x00 "UART_TLR,Trigger level register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x07 line.long 0x00 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes" line.long 0x04 "UART_MDR1,Mode definition register 1" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x04 7. "FRAME_END_MODE,Reserved" "0,1" newline bitfld.long 0x04 6. "SIP_MODE,Reserved" "0,1" newline bitfld.long 0x04 5. "SCT,Reserved" "0,1" newline bitfld.long 0x04 4. "SET_TXIR,Reserved" "0,1" newline bitfld.long 0x04 3. "IR_SLEEP,Reserved" "0,1" newline bitfld.long 0x04 0.--2. "MODE_SELECT," "?,MODE_SELECT_1,MODE_SELECT_2,MODE_SELECT_3,MODE_SELECT_4,MODE_SELECT_5,MODE_SELECT_6,MODE_SELECT_7" rgroup.long 0x38++0x03 line.long 0x00 "UART_UASR,UART autobauding status register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 6.--7. "PARITY_TYPE," "?,PARITY_TYPE_1_r,PARITY_TYPE_2_r,PARITY_TYPE_3_r" newline bitfld.long 0x00 5. "BIT_BY_CHAR," "?,BIT_BY_CHAR_1_r" newline bitfld.long 0x00 0.--4. "SPEED,Used to report the speed identified" "SPEED_0_r,SPEED_1_r,SPEED_2_r,SPEED_3_r,SPEED_4_r,SPEED_5_r,SPEED_6_r,SPEED_7_r,SPEED_8_r,SPEED_9_r,SPEED_10_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x40++0x07 line.long 0x00 "UART_SCR,Supplementary control register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 7. "RX_TRIG_GRANU1," "?,RX_TRIG_GRANU1_1" newline bitfld.long 0x00 6. "TX_TRIG_GRANU1," "?,TX_TRIG_GRANU1_1" newline bitfld.long 0x00 5. "DSR_IT,NOT USED IN THIS DEVICE" "0,1" newline bitfld.long 0x00 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "?,RX_CTS_DSR_WAKE_UP_ENABLE_1" newline bitfld.long 0x00 3. "TX_EMPTY_CTL_IT," "?,TX_EMPTY_CTL_IT_1" newline bitfld.long 0x00 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if theUART_SCR[0] bit = 1" "DMA_MODE_2_0,DMA_MODE_2_1,DMA_MODE_2_2,DMA_MODE_2_3" newline bitfld.long 0x00 0. "DMA_MODE_CTL," "?,DMA_MODE_CTL_1" line.long 0x04 "UART_SSR,Supplementary status register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline rbitfld.long 0x04 3.--7. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 2. "DMA_COUNTER_RST," "?,DMA_COUNTER_RST_1" newline rbitfld.long 0x04 1. "RX_CTS_DSR_WAKE_UP_STS," "?,RX_CTS_DSR_WAKE_UP_STS_1_r" newline rbitfld.long 0x04 0. "TX_FIFO_FULL," "?,TX_FIFO_FULL_1_r" rgroup.long 0x50++0x0F line.long 0x00 "UART_MVR,Module version register" line.long 0x04 "UART_SYSC,System configuration register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline rbitfld.long 0x04 5.--7. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 3.--4. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x04 2. "ENAWAKEUP,Wake-up feature control" "ENAWAKEUP_0,ENAWAKEUP_1" newline bitfld.long 0x04 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x04 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x08 "UART_SYSS,System status register" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x0C "UART_WER,Wake-up enable register" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x0C 7. "TX_WAKEUP_EN," "?,TX_WAKEUP_EN_1" newline bitfld.long 0x0C 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "?,EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_1" newline bitfld.long 0x0C 5. "EVENT_5_RHR_INTERRUPT," "?,EVENT_5_RHR_INTERRUPT_1" newline bitfld.long 0x0C 4. "EVENT_4_RX_ACTIVITY," "?,EVENT_4_RX_ACTIVITY_1" newline bitfld.long 0x0C 3. "EVENT_3_DCD_CD_ACTIVITY," "?,EVENT_3_DCD_CD_ACTIVITY_1" newline bitfld.long 0x0C 2. "EVENT_2_RI_ACTIVITY," "?,EVENT_2_RI_ACTIVITY_1" newline bitfld.long 0x0C 1. "EVENT_1_DSR_ACTIVITY," "?,EVENT_1_DSR_ACTIVITY_1" newline bitfld.long 0x0C 0. "EVENT_0_CTS_ACTIVITY," "?,EVENT_0_CTS_ACTIVITY_1" rgroup.long 0x64++0x13 line.long 0x00 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x00 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO" line.long 0x04 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x04 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO" line.long 0x08 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" hexmask.long 0x08 2.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "EN_TXFIFO_EMPTY_0,EN_TXFIFO_EMPTY_1" newline bitfld.long 0x08 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "EN_RXFIFO_EMPTY_0,EN_RXFIFO_EMPTY_1" line.long 0x0C "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" hexmask.long 0x0C 2.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x0C 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "TXFIFO_EMPTY_STS_0,TXFIFO_EMPTY_STS_1" newline bitfld.long 0x0C 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "RXFIFO_EMPTY_STS_0,RXFIFO_EMPTY_STS_1" line.long 0x10 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x10 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used.UART_MDR3[1] must be set to 1 after this value is set" group.long 0x80++0x07 line.long 0x00 "UART_MDR3,Mode definition register 3" hexmask.long 0x00 3.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold inUART_TX_DMA_THRESHOLD register" "0,1" newline bitfld.long 0x00 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies" "NONDEFAULT_FREQ_0,NONDEFAULT_FREQ_1" newline bitfld.long 0x00 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation" "DISABLE_CIR_RX_DEMOD_0,DISABLE_CIR_RX_DEMOD_1" line.long 0x04 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level" hexmask.long 0x04 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--5. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end repeat.end tree "UART1_TARG" base ad:0x4806B000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "UART2_TARG" base ad:0x4806D000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "UART3_TARG" base ad:0x48021000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "VENC" base ad:0x58005000 rgroup.long 0x00++0x0B line.long 0x00 "VENC_REV_ID,Revision ID for the encoder" line.long 0x04 "VENC_STATUS,STATUS" hexmask.long 0x04 5.--31. 1. "RESERVED," bitfld.long 0x04 4. "CCE,Closed Caption Status for Even Field" "0,1" bitfld.long 0x04 3. "CCO,Closed Caption Status for Odd Field" "0,1" newline bitfld.long 0x04 0.--2. "FSQ,Field Sequence ID" "FSQ_0_r,FSQ_1_r,?,?,?,?,?,?" line.long 0x08 "VENC_F_CONTROL,This register specifies the input video source and format" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," bitfld.long 0x08 8. "RESET,RESET the encoder" "RESET_0,RESET_1" bitfld.long 0x08 6.--7. "SVDS,Select Video Data Source" "SVDS_0,SVDS_1,SVDS_2,SVDS_3" newline bitfld.long 0x08 5. "RGBF,RGB /YCrCb input coding range" "RGBF_0,RGBF_1" bitfld.long 0x08 2.--4. "BCOLOR,Background color select" "BCOLOR_0,BCOLOR_1,BCOLOR_2,BCOLOR_3,BCOLOR_4,BCOLOR_5,BCOLOR_6,BCOLOR_7" bitfld.long 0x08 0.--1. "FMT,These two bits specify the video input data stream format and timing" "FMT_0,FMT_1,FMT_2,FMT_3" group.long 0x10++0x07 line.long 0x00 "VENC_VIDOUT_CTRL,Encoder output clock" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "MHZ_27_54,Encoder output clock" "MHZ_27_54_0,MHZ_27_54_1" line.long 0x04 "VENC_SYNC_CTRL,SYNC Control register" hexmask.long.word 0x04 16.--31. 1. "RESERVED,reserved_5" bitfld.long 0x04 15. "FREE,Free running" "FREE_0,FREE_1" bitfld.long 0x04 14. "ESAV,Enable to detect F and V bits only on EAV in ITU-R 656 input mode" "ESAV_0,ESAV_1" newline bitfld.long 0x04 13. "IGNP,Ignore protection bits in ITU-R 656 input mode" "IGNP_0,IGNP_1" bitfld.long 0x04 12. "NBLNKS,Blank shaping" "NBLNKS_0,NBLNKS_1" bitfld.long 0x04 10.--11. "VBLKM,Vertical blanking mode" "VBLKM_0,VBLKM_1,VBLKM_2,VBLKM_3" newline bitfld.long 0x04 8.--9. "HBLKM,Horizontal blanking mode" "HBLKM_0,HBLKM_1,HBLKM_2,HBLKM_3" bitfld.long 0x04 7. "M_S,Encoder is master or slave of external sync" "M_S_0,M_S_1" bitfld.long 0x04 6. "FID_POL,FID output polarity" "FID_POL_0,FID_POL_1" newline rbitfld.long 0x04 4.--5. "RESERVED," "0,1,2,3" bitfld.long 0x04 3. "VS_POL,VS input polarity" "VS_POL_0,VS_POL_1" bitfld.long 0x04 2. "HS_POL,HS input polarity" "HS_POL_0,HS_POL_1" newline rbitfld.long 0x04 1. "RESERVED," "0,1" bitfld.long 0x04 0. "FHVMOD,FID extracted from external FID or HSYNC and VSYNC" "FHVMOD_0,FHVMOD_1" group.long 0x1C++0x6F line.long 0x00 "VENC_LLEN,LLEN" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "LLEN_EN,LLEN_EN" "LLEN_EN_0,LLEN_EN_1" rbitfld.long 0x00 11.--14. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. "LLEN,LLEN[10:0] Line length or total number of pixels in a scan line including active video and blanking" line.long 0x04 "VENC_FLENS,FLENS" hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED," hexmask.long.word 0x04 0.--10. 1. "FLENS,The frame length or total number of lines in a frame including active video and blanking from the source image" line.long 0x08 "VENC_HFLTR_CTRL,HFLTR_CTRL" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 1.--2. "CINTP,Chrominance interpolation filter control" "CINTP_0,CINTP_1,CINTP_2,CINTP_3" bitfld.long 0x08 0. "YINTP,Luminance interpolation filter control" "YINTP_0,YINTP_1" line.long 0x0C "VENC_CC_CARR_WSS_CARR,Frequencie code control" hexmask.long.word 0x0C 16.--31. 1. "FWSS,Wide screen signaling run-in code frequency control" hexmask.long.word 0x0C 0.--15. 1. "FCC,Close caption run-in code frequency control" line.long 0x10 "VENC_C_PHASE,C_PHASE" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED," hexmask.long.byte 0x10 0.--7. 1. "CPHS,Phase of the encoded video color subcarrier (including the color burst) relative to H-sync" line.long 0x14 "VENC_GAIN_U,Gain control for Cb signal" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED," hexmask.long.word 0x14 0.--8. 1. "GU,Gain control for Cb signal" line.long 0x18 "VENC_GAIN_V,Gain control of Cr signal" hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED," hexmask.long.word 0x18 0.--8. 1. "GV,Gain control of Cr signal" line.long 0x1C "VENC_GAIN_Y,Gain control of Y signal" hexmask.long.tbyte 0x1C 9.--31. 1. "RESERVED," hexmask.long.word 0x1C 0.--8. 1. "GY,Gain control of Y signal" line.long 0x20 "VENC_BLACK_LEVEL,BLACK LEVEL" hexmask.long 0x20 7.--31. 1. "RESERVED," hexmask.long.byte 0x20 0.--6. 1. "BLACK,Black level setting" line.long 0x24 "VENC_BLANK_LEVEL,BLANK LEVEL" hexmask.long 0x24 7.--31. 1. "RESERVED," hexmask.long.byte 0x24 0.--6. 1. "BLANK,Blank level setting" line.long 0x28 "VENC_X_COLOR,Cross-Colour Control register" hexmask.long 0x28 7.--31. 1. "RESERVED," bitfld.long 0x28 6. "XCE,Cross color reduction enable for composite video output" "XCE_0,XCE_1" rbitfld.long 0x28 5. "RESERVED," "0,1" newline bitfld.long 0x28 3.--4. "XCBW,Cross color reduction filter selection" "XCBW_0,XCBW_1,XCBW_2,XCBW_3" bitfld.long 0x28 0.--2. "LCD,These three bits can be used for chroma channel delay compensation" "LCD_0,LCD_1,LCD_2,LCD_3,LCD_4,LCD_5,LCD_6,LCD_7" line.long 0x2C "VENC_M_CONTROL,M_CONTROL" hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 7. "PALI,PAL I enable" "PALI_0,PALI_1" bitfld.long 0x2C 6. "PALN,PAL N Enable" "PALN_0,PALN_1" newline bitfld.long 0x2C 5. "PALPHS,PAL switch phase setting" "PALPHS_0,PALPHS_1" bitfld.long 0x2C 2.--4. "CBW,Chrominance lowpass filter bandwidth control" "CBW_0,CBW_1,CBW_2,CBW_3,CBW_4,CBW_5,CBW_6,CBW_7" bitfld.long 0x2C 1. "PAL,Phase alternation line encoding selection" "PAL_0,PAL_1" newline bitfld.long 0x2C 0. "FFRQ,The value of this field and the SQP bit in the BSTAMP_WSS_DATA register control the number of horizontal pixels displayed per scan line # OF MODE SQP FFRQ PIXEL PER LINE ITU-R 601 NTSC 0 1 858 Square pixel NTSC 1 1 780 ITU-R 601 PAL 0 0 864 Square.." "0,1" line.long 0x30 "VENC_BSTAMP_WSS_DATA,BSTAMP and WSS_DATA" rbitfld.long 0x30 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x30 8.--27. 1. "WSS_D,Wide Screen Signaling data NTSC: WORD 0 D0 D1 WORD 1 D2 D3 D4 D5 WORD 2 D6 D7 D8 D9 D10 D11 D12 D13 CRC D14 D15 D16 D17 D18 D19 PAL: GROUP A D0 D1 D2 D3 GROUP B D4 D5 D6 D7 GROUP C D8 D9 D10 GROUP D D11 D12 D13" bitfld.long 0x30 7. "SQP,Square-pixel sampling rate" "SQP_0,SQP_1" newline hexmask.long.byte 0x30 0.--6. 1. "BSTAP,Setting of amplitude of color burst" line.long 0x34 "VENC_S_CARR,Color Subcarrier Frequency Registers" line.long 0x38 "VENC_LINE21,LINE 21" hexmask.long.word 0x38 16.--31. 1. "L21E,The two bytes of the closed caption data in the even field.For the data stream content see" hexmask.long.word 0x38 0.--15. 1. "L21O,The two bytes of the closed caption data in the odd fieldFor the data stream content see" line.long 0x3C "VENC_LN_SEL,LN_SEL" rbitfld.long 0x3C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x3C 16.--25. 1. "LN21_RUNIN,The two Bytes of the closed caption runin code position from the HSYNC" hexmask.long.word 0x3C 5.--15. 1. "RESERVED," newline bitfld.long 0x3C 0.--4. "SLINE,Selects the line where closed caption or extended service data are encoded.PAL mode: Because there is a one-line offset program the desired line number - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "VENC_L21_WC_CTL,L21 and WC_CTL registers" hexmask.long.word 0x40 16.--31. 1. "RESERVED," bitfld.long 0x40 15. "INV,WSS inverter" "INV_0,INV_1" bitfld.long 0x40 13.--14. "EVEN_ODD_EN,This bit controls the WSS encoding" "EVEN_ODD_EN_0,EVEN_ODD_EN_1,EVEN_ODD_EN_2,EVEN_ODD_EN_3" newline bitfld.long 0x40 8.--12. "LINE,Selects the line where WSS data are encoded.PAL mode: Because there is a one-line offset program the desired line number - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x40 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 0.--1. "L21EN,Those bits controls the Line21 closed caption encoding according to the mode" "L21EN_0,L21EN_1,L21EN_2,L21EN_3" line.long 0x44 "VENC_HTRIGGER_VTRIGGER,HTRIGGER and VTRIGGER" rbitfld.long 0x44 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x44 16.--25. 1. "VTRIG,Vertical trigger reference for VSYNC" rbitfld.long 0x44 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x44 0.--10. 1. "HTRIG,Horizontal trigger phase which sets HSYNC" line.long 0x48 "VENC_SAVID_EAVID,SAVID and EAVID" rbitfld.long 0x48 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x48 16.--26. 1. "EAVID,End of active video" rbitfld.long 0x48 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 0.--10. 1. "SAVID,Start of active video" line.long 0x4C "VENC_FLEN_FAL,FLEN and FAL" hexmask.long.byte 0x4C 25.--31. 1. "RESERVED," hexmask.long.word 0x4C 16.--24. 1. "FAL,First Active Line of Field" rbitfld.long 0x4C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x4C 0.--9. 1. "FLEN,Field length" line.long 0x50 "VENC_LAL_PHASE_RESET,LAL and PHASE_RESET" hexmask.long.word 0x50 19.--31. 1. "RESERVED," bitfld.long 0x50 17.--18. "PRES,Phase reset mode" "PRES_0,PRES_1,PRES_2,PRES_3" bitfld.long 0x50 16. "SBLANK,Vertical blanking setting" "SBLANK_0,SBLANK_1" newline hexmask.long.byte 0x50 9.--15. 1. "RESERVED," hexmask.long.word 0x50 0.--8. 1. "LAL,Last Active Line of Field" line.long 0x54 "VENC_HS_INT_START_STOP_X,HS_INT_START_STOP_X" rbitfld.long 0x54 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x54 16.--25. 1. "HS_INT_STOP_X,HSYNC internal stop" rbitfld.long 0x54 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x54 0.--9. 1. "HS_INT_START_X,HSYNC internal start" line.long 0x58 "VENC_HS_EXT_START_STOP_X,HS_EXT_START_STOP_X" rbitfld.long 0x58 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x58 16.--25. 1. "HS_EXT_STOP_X,HSYNC external stop" rbitfld.long 0x58 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x58 0.--9. 1. "HS_EXT_START_X,HSYNC external start" line.long 0x5C "VENC_VS_INT_START_X,VS_INT_START_X" rbitfld.long 0x5C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x5C 16.--25. 1. "VS_INT_START_X,VSYNC internal start" hexmask.long.word 0x5C 0.--15. 1. "RESERVED," line.long 0x60 "VENC_VS_INT_STOP_X_VS_INT_START_Y,VS_INT_STOP_X and VS_INT_START_Y" rbitfld.long 0x60 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x60 16.--25. 1. "VS_INT_START_Y,VSYNC internal start" rbitfld.long 0x60 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x60 0.--9. 1. "VS_INT_STOP_X,VSYNC internal stop" line.long 0x64 "VENC_VS_INT_STOP_Y_VS_EXT_START_X,VS_INT_STOP_Y and VS_EXT_START_X" rbitfld.long 0x64 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x64 16.--25. 1. "VS_EXT_START_X,VSYNC external start" rbitfld.long 0x64 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x64 0.--9. 1. "VS_INT_STOP_Y,VSYNC internal stop" line.long 0x68 "VENC_VS_EXT_STOP_X_VS_EXT_START_Y,VS_EXT_STOP_X and VS_EXT_START_Y" rbitfld.long 0x68 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x68 16.--25. 1. "VS_EXT_START_Y,VSYNC external start" rbitfld.long 0x68 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x68 0.--9. 1. "VS_EXT_STOP_X,VSYNC external stop" line.long 0x6C "VENC_VS_EXT_STOP_Y,VS_EXT_STOP_Y" hexmask.long.tbyte 0x6C 10.--31. 1. "RESERVED," hexmask.long.word 0x6C 0.--9. 1. "VS_EXT_STOP_Y,VSYNC external stop" group.long 0x90++0x07 line.long 0x00 "VENC_AVID_START_STOP_X,AVID_START_STOP_X" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "AVID_STOP_X,AVID stop" rbitfld.long 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--9. 1. "AVID_START_X,AVID start" line.long 0x04 "VENC_AVID_START_STOP_Y,AVID_START_STOP_Y" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x04 16.--25. 1. "AVID_STOP_Y,AVID stop" rbitfld.long 0x04 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x04 0.--9. 1. "AVID_START_Y,AVID start" group.long 0xA0++0x0B line.long 0x00 "VENC_FID_INT_START_X_FID_INT_START_Y,FID_INT_START_X and FID_INT_START_Y" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "FID_INT_START_Y,FID internal stop" rbitfld.long 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--9. 1. "FID_INT_START_X,FID internal start" line.long 0x04 "VENC_FID_INT_OFFSET_Y_FID_EXT_START_X,FID_INT_OFFSET_Y and FID_EXT_START_X" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x04 16.--25. 1. "FID_EXT_START_X,FID external start" rbitfld.long 0x04 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x04 0.--9. 1. "FID_INT_OFFSET_Y,FID internal offset" line.long 0x08 "VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y,FID_EXT_START_Y and FID_EXT_OFFSET_Y" rbitfld.long 0x08 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x08 16.--25. 1. "FID_EXT_OFFSET_Y,FID external offset" rbitfld.long 0x08 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x08 0.--9. 1. "FID_EXT_START_Y,FID external start" group.long 0xB0++0x0B line.long 0x00 "VENC_TVDETGP_INT_START_STOP_X,TVDETGP_INT_START_STOP_X" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "TVDETGP_INT_STOP_X,TVDETGP internal stop" rbitfld.long 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--9. 1. "TVDETGP_INT_START_X,TVDETGP internal start" line.long 0x04 "VENC_TVDETGP_INT_START_STOP_Y,TVDETGP_INT_START_STOP_Y" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x04 16.--25. 1. "TVDETGP_INT_STOP_Y,TVDETGP internal stop" rbitfld.long 0x04 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x04 0.--9. 1. "TVDETGP_INT_START_Y,TVDETGP internal start" line.long 0x08 "VENC_GEN_CTRL,TVDETGP enable and SYNC_POLARITY and UVPHASE_POL" rbitfld.long 0x08 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 26. "MS,UVPHASE_POL MS mode UV phase" "MS_0,MS_1" bitfld.long 0x08 25. "UVPHASE_POL_656,UVPHASE_POL 656 input mode UV phase" "UVPHASE_POL_656_0,UVPHASE_POL_656_1" newline bitfld.long 0x08 24. "CBAR,UVPHASE_POL CBAR mode UV phase" "CBAR_0,CBAR_1" bitfld.long 0x08 23. "HIP,HSYNC internal polarity" "HIP_0,HIP_1" bitfld.long 0x08 22. "VIP,VSYNC internal polarity" "VIP_0,VIP_1" newline bitfld.long 0x08 21. "HEP,HSYNC external polarity" "HEP_0,HEP_1" bitfld.long 0x08 20. "VEP,VSYNC externall polarity" "VEP_0,VEP_1" bitfld.long 0x08 19. "AVIDP,AVID polarity" "AVIDP_0,AVIDP_1" newline bitfld.long 0x08 18. "FIP,FID internal polarity" "FIP_0,FIP_1" bitfld.long 0x08 17. "FEP,FID external polarity" "FEP_0,FEP_1" bitfld.long 0x08 16. "TVDP,TVDETGP polarity" "TVDP_0,TVDP_1" newline hexmask.long.word 0x08 1.--15. 1. "RESERVED," bitfld.long 0x08 0. "EN,TVDETGP generation enable" "EN_0,EN_1" group.long 0xC4++0x07 line.long 0x00 "VENC_OUTPUT_CONTROL,Output channel control register Also contains some test control features" hexmask.long 0x00 7.--31. 1. "RESERVED," bitfld.long 0x00 6. "COMPOSITE_SOURCE,Source of composite video data in test mode" "COMPOSITE_SOURCE_0,COMPOSITE_SOURCE_1" bitfld.long 0x00 5. "RESERVED," "0,1" newline bitfld.long 0x00 4. "TEST_MODE,This enables the video DACs to be tested" "TEST_MODE_0,TEST_MODE_1" bitfld.long 0x00 3. "VIDEO_INVERT,Controls the video output polarity" "VIDEO_INVERT_0,VIDEO_INVERT_1" bitfld.long 0x00 2. "RESERVED," "0,1" newline bitfld.long 0x00 1. "COMPOSITE_ENABLE,Enable the Composite output channel" "COMPOSITE_ENABLE_0,COMPOSITE_ENABLE_1" bitfld.long 0x00 0. "RESERVED," "0,1" line.long 0x04 "VENC_OUTPUT_TEST,Test values for the Luma/Composite Video DAC" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," hexmask.long.word 0x04 0.--9. 1. "COMPOSITE_TEST,In test mode DAC input value (if composite video is selected)" width 0x0B tree.end tree "VIP_Slice0_csc" base ad:0x48975700 group.long 0x00++0x17 line.long 0x00 "VIP_CSC00," bitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "B0,Coefficients of color space converter" bitfld.long 0x00 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--12. 1. "A0,Coefficients of color space converter" line.long 0x04 "VIP_CSC01," bitfld.long 0x04 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 16.--28. 1. "A1,Coefficients of color space converter" bitfld.long 0x04 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 0.--12. 1. "C0,Coefficients of color space converter" line.long 0x08 "VIP_CSC02," bitfld.long 0x08 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 16.--28. 1. "C1,Coefficients of color space converter" bitfld.long 0x08 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--12. 1. "B1,Coefficients of color space converter" line.long 0x0C "VIP_CSC03," bitfld.long 0x0C 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 16.--28. 1. "B2,Coefficients of color space converter" bitfld.long 0x0C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 0.--12. 1. "A2,Coefficients of color space converter" line.long 0x10 "VIP_CSC04," bitfld.long 0x10 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x10 16.--27. 1. "D0,Coefficients of color space converter" bitfld.long 0x10 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--12. 1. "C2,Coefficients of color space converter" line.long 0x14 "VIP_CSC05," bitfld.long 0x14 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x14 28. "BYPASS,Full CSC bypass mode" "0,1" hexmask.long.word 0x14 16.--27. 1. "D2,Coefficients of color space converter" bitfld.long 0x14 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x14 0.--11. 1. "D1,Coefficients of color space converter" width 0x0B tree.end tree "VIP_Slice0_parser" base ad:0x48975500 group.long 0x00++0xE7 line.long 0x00 "VIP_MAIN,ain Configuration for VIP Parser" hexmask.long 0x00 6.--31. 1. "RESERVED," newline bitfld.long 0x00 5. "CLIP_ACTIVE,Discrete Sync Only" "Do not clip active pixels,Clip Active Pixels as follows" newline bitfld.long 0x00 4. "CLIP_BLNK,Discrete Sync Only" "Do not clip Blanking Data,Clip Blanking Data as follows" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 0.--1. "DATA_INTERFACE_MODE," "?,16b data interface,Dual independent 8b data interfaces,Undefined" line.long 0x04 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x04 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "Ignore the protection bits in the XV (fvh)..,Use the protection bits in an attempt to do.." newline bitfld.long 0x04 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "For 2x/4x mux mode srcnum is in the least..,For 2x/4x mux mode srcnum is in the least.." newline bitfld.long 0x04 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. "SW_RESET," "0,1" newline bitfld.long 0x04 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "Normal Discrete Mode,Basic Discrete Mode" newline bitfld.long 0x04 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "Use HSYNC style line capture,Use ACTVID style line capture" newline bitfld.long 0x04 14. "FID_DETECT_MODE,Discrete Sync Only" "Take FID from pin,FID is determined by VSYNC skew" newline bitfld.long 0x04 13. "ACTVID_POLARITY,Discrete Sync Only" "ACTVID is active low,ACTVID is active high" newline bitfld.long 0x04 12. "VSYNC_POLARITY,Discrete Sync Only" "VSYNC is active low,VSYNC is active high" newline bitfld.long 0x04 11. "HSYNC_POLARITY,Discrete Sync Only" "HSYNC is active low,HSYNC is active high" newline bitfld.long 0x04 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x04 9. "FID_POLARITY," "0,1" newline bitfld.long 0x04 8. "ENABLE," "0,1" newline bitfld.long 0x04 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x04 6. "CLR_ASYNC_FIFO_WR," "0,1" newline bitfld.long 0x04 4.--5. "CTRL_CHAN_SEL,Embedded Sync Only In 8b mode" "Use data[7:0] to extract control codes,Use data[15:8] to extract control codes,Use data[23:16] to extract control codes,Undefined In 16b and 24b modes" newline bitfld.long 0x04 0.--3. "SYNC_TYPE," "?,embedded sync 2x multiplexed 4:2:2 YUV stream,embedded sync 4x multiplexed 4:2:2 YUV stream,embedded sync line multiplexed 4:2:2 YUV stream,discrete sync single 4:2:2 YUV stream,embedded sync single RGB stream or single 444..,reserved,reserved,reserved,reserved,discrete sync single 24b RGB stream,?..." line.long 0x08 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" rbitfld.long 0x08 31. "RESERVED," "0,1" newline bitfld.long 0x08 28.--30. "REPACK_SEL," "?,Cross Swap,Left Center Swap,Center Right Swap,Right Rotate,Left Rotate,RAW16 to RGB565 Mapping,RAW12 Swap" newline hexmask.long.word 0x08 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" newline rbitfld.long 0x08 15. "RESERVED," "0,1" newline bitfld.long 0x08 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "Extract 8b Mode Vertical Ancillary Data from..,Extract 8b Mode Vertical Ancillary Data from..,?,Extract every single sample of vertical.." newline rbitfld.long 0x08 12. "RESERVED," "0,1" newline hexmask.long.word 0x08 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x0C "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0C 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "Ignore the protection bits in the XV (fvh)..,Use the protection bits in an attempt to do.." newline bitfld.long 0x0C 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "For 2x/4x mux mode srcnum is in the least..,For 2x/4x mux mode srcnum is in the least.." newline bitfld.long 0x0C 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 23. "SW_RESET," "0,1" newline bitfld.long 0x0C 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "Normal Discrete Mode,Basic Discrete Mode" newline bitfld.long 0x0C 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "Use HSYNC style line capture,Use ACTVID style line capture" newline bitfld.long 0x0C 14. "FID_DETECT_MODE,Discrete Sync Only" "Take FID from pin,FID is determined by VSYNC skew" newline bitfld.long 0x0C 13. "ACTVID_POLARITY,Discrete Sync Only" "ACTVID is active low,ACTVID is active high" newline bitfld.long 0x0C 12. "VSYNC_POLARITY,Discrete Sync Only" "VSYNC is active low,VSYNC is active high" newline bitfld.long 0x0C 11. "HSYNC_POLARITY,Discrete Sync Only" "HSYNC is active low,HSYNC is active high" newline bitfld.long 0x0C 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x0C 9. "FID_POLARITY," "0,1" newline bitfld.long 0x0C 8. "ENABLE," "0,1" newline bitfld.long 0x0C 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x0C 6. "CLR_ASYNC_FIFO_WR," "0,1" newline bitfld.long 0x0C 4.--5. "CTRL_CHAN_SEL,PORT B supports on 8b mode" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "SYNC_TYPE," "?,embedded sync 2x multiplexed YUV stream,embedded sync 4x multiplexed YUV stream,embedded sync line multiplexed YUV stream,discrete sync single YUV stream,embedded sync single RGB stream,reserved,reserved,reserved,reserved,discrete sync single 24b RGB stream,?..." line.long 0x10 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" rbitfld.long 0x10 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x10 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" newline rbitfld.long 0x10 15. "RESERVED," "0,1" newline bitfld.long 0x10 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "Extract 8b Mode Vertical Ancillary Data from..,Extract 8b Mode Vertical Ancillary Data from..,?,Extract every single sample of vertical.." newline rbitfld.long 0x10 12. "RESERVED," "0,1" newline hexmask.long.word 0x10 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x14 "VIP_FIQ_MASK,ask Bits for ARM FIQs" hexmask.long.word 0x14 22.--31. 1. "RESERVED," newline bitfld.long 0x14 21. "PORT_B_CFG_DISABLE_COMPLETE_MASK,Port B Cfg Disable Complete Mask" "0,1" newline bitfld.long 0x14 20. "PORT_A_CFG_DISABLE_COMPLETE_MASK,Port A Cfg Disable Complete Mask" "0,1" newline bitfld.long 0x14 19. "PORT_B_ANC_PROTOCOL_VIOLATION_MASK,Port B ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 18. "PORT_B_YUV_PROTOCOL_VIOLATION_MASK,Port B YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 17. "PORT_A_ANC_PROTOCOL_VIOLATION_MASK,Port A ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 16. "PORT_A_YUV_PROTOCOL_VIOLATION_MASK,Port A YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 15. "PORT_B_SRC0_SIZE,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" newline bitfld.long 0x14 14. "PORT_A_SRC0_SIZE,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" newline bitfld.long 0x14 13. "PORT_B_DISCONN,Port B Link Disconnect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 12. "PORT_B_CONN,Port B Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 11. "PORT_A_DISCONN,Port A Link Disconnect Scrnum 0 Mask" "0,1" newline bitfld.long 0x14 10. "PORT_A_CONN,Port A Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 9. "OUTPUT_FIFO_PRTB_ANC_OF,Output FIFO Port B Ancillary Overflow Mask" "0,1" newline rbitfld.long 0x14 8. "RESERVED," "0,1" newline bitfld.long 0x14 7. "OUTPUT_FIFO_PRTB_YUV_OF,Output FIFO Port B Luma Overflow Mask" "0,1" newline bitfld.long 0x14 6. "OUTPUT_FIFO_PRTA_ANC_OF,Output FIFO Port A Ancillary Overflow Mask" "0,1" newline rbitfld.long 0x14 5. "RESERVED," "0,1" newline bitfld.long 0x14 4. "OUTPUT_FIFO_PRTA_YUV_OF,Output FIFO Port A Luma Overflow Mask" "0,1" newline bitfld.long 0x14 3. "ASYNC_FIFO_PRTB_OF,Port B Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 2. "ASYNC_FIFO_PRTA_OF,Port A Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 1. "PRTB_VDET_MASK,Port B Video Detect FIQ Mask" "0,1" newline bitfld.long 0x14 0. "PRTA_VDET_MASK,Port A Video Detect FIQ Mask" "0,1" line.long 0x18 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" hexmask.long.word 0x18 22.--31. 1. "RESERVED," newline bitfld.long 0x18 21. "PORT_A_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x18 20. "PORT_A_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x18 19. "PORT_B_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 18. "PORT_B_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 17. "PORT_A_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 16. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 15. "PORT_B_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" newline bitfld.long 0x18 14. "PORT_A_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" newline bitfld.long 0x18 13. "PORT_B_DISCONN_CLR,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 12. "PORT_B_CONN_CLR,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" newline bitfld.long 0x18 11. "PORT_A_DISCONN_CLR,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 10. "PORT_A_CONN_CLR,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" newline bitfld.long 0x18 9. "OUTPUT_FIFO_PRTB_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" newline rbitfld.long 0x18 8. "RESERVED," "0,1" newline bitfld.long 0x18 7. "OUTPUT_FIFO_PRTB_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" newline bitfld.long 0x18 6. "OUTPUT_FIFO_PRTA_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" newline rbitfld.long 0x18 5. "RESERVED," "0,1" newline bitfld.long 0x18 4. "OUTPUT_FIFO_PRTA_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" newline bitfld.long 0x18 3. "ASYNC_FIFO_PRTB_CLR,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" newline bitfld.long 0x18 2. "ASYNC_FIFO_PRTA_CLR,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" newline bitfld.long 0x18 1. "PRTB_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" newline bitfld.long 0x18 0. "PRTA_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" line.long 0x1C "VIP_FIQ_STATUS,FIQ Status values" hexmask.long.word 0x1C 22.--31. 1. "RESERVED," newline bitfld.long 0x1C 21. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Port B Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x1C 20. "PORT_A_CFG_DISABLE_COMPLETE,Port A Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x1C 19. "PORT_B_ANC_PROTOCOL_VIOLATION,Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 18. "PORT_B_YUV_PROTOCOL_VIOLATION,Port B YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 17. "PORT_A_ANC_PROTOCOL_VIOLATION,Port A ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 16. "PORT_A_YUV_PROTOCOL_VIOLATION,Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 15. "PORT_B_SRC0_SIZE_STATUS,Port B Source 0 Size FIQ" "0,1" newline bitfld.long 0x1C 14. "PORT_A_SRC0_SIZE_STATUS,Port A Source 0 Size FIQ" "0,1" newline bitfld.long 0x1C 13. "PORT_B_DISCONN_STATUS,Port B Disconnect FIQ" "0,1" newline bitfld.long 0x1C 12. "PORT_B_CONN_STATUS,Port B Connect FIQ" "0,1" newline bitfld.long 0x1C 11. "PORT_A_DISCONN_STATUS,Port A Disconnect FIQ" "0,1" newline bitfld.long 0x1C 10. "PORT_A_CONN_STATUS,Port A Connect FIQ" "0,1" newline bitfld.long 0x1C 9. "OUTPUT_FIFO_PRTB_ANC_STATUS,Output FIFO Port B Ancillary Overflow Status" "0,1" newline bitfld.long 0x1C 8. "OUTPUT_FIFO_PRTB_CHROMA_STATUS,Output FIFO Port B Chroma Overflow Status" "0,1" newline bitfld.long 0x1C 7. "OUTPUT_FIFO_PRTB_LUMA_STATUS,Output FIFO Port B Luma Overflow Status" "0,1" newline bitfld.long 0x1C 6. "OUTPUT_FIFO_PRTA_ANC_STATUS,Output FIFO Port A Ancillary Overflow Status" "0,1" newline bitfld.long 0x1C 5. "OUTPUT_FIFO_PRTA_CHROMA_STATUS,Output FIFO Port A Chroma Overflow Status" "0,1" newline bitfld.long 0x1C 4. "OUTPUT_FIFO_PRTA_LUMA_STATUS,Output FIFO Port A Luma Overflow Status" "0,1" newline bitfld.long 0x1C 3. "ASYNC_FIFO_PRTB_STATUS,Async FIFO Port B Overflow Status" "0,1" newline bitfld.long 0x1C 2. "ASYNC_FIFO_PRTA_STATUS,Async FIFO Port A Overflow Status" "0,1" newline bitfld.long 0x1C 1. "PRTB_VDET_STATUS,VDET Status for Port B" "0,1" newline bitfld.long 0x1C 0. "PRTA_VDET_STATUS,VDET Status for Port A" "0,1" line.long 0x20 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x20 31. "PRTA_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x20 30. "PRTA_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x20 29. "PRTA_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 28. "PRTA_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 27. "PRTA_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 26. "PRTA_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 25. "PRTA_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x20 24. "PRTA_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x20 23. "PRTA_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 22. "PRTA_SRC11_PREV_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 21. "PRTA_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 20. "PRTA_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 19. "PRTA_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x20 18. "PRTA_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x20 17. "PRTA_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 16. "PRTA_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 15. "PRTA_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 14. "PRTA_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 13. "PRTA_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x20 12. "PRTA_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x20 11. "PRTA_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 10. "PRTA_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 9. "PRTA_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 8. "PRTA_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 7. "PRTA_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x20 6. "PRTA_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x20 5. "PRTA_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 4. "PRTA_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 3. "PRTA_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 2. "PRTA_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 1. "PRTA_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port A" "0,1" newline bitfld.long 0x20 0. "PRTA_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port A" "0,1" line.long 0x24 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x24 31. "PRTA_SRC15_CURR_ENC_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x24 30. "PRTA_SRC15_PREV_ENC_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x24 29. "PRTA_SRC14_CURR_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 28. "PRTA_SRC14_PREV_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 27. "PRTA_SRC13_CURR_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 26. "PRTA_SRC13_PREV_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 25. "PRTA_SRC12_CURR_ENC_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x24 24. "PRTA_SRC12_PREV_ENC_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x24 23. "PRTA_SRC11_CURR_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 22. "PRTA_SRC11_PREV_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 21. "PRTA_SRC10_CURR_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 20. "PRTA_SRC10_PREV_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 19. "PRTA_SRC9_CURR_ENC_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x24 18. "PRTA_SRC9_PREV_ENC_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x24 17. "PRTA_SRC8_CURR_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 16. "PRTA_SRC8_PREV_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 15. "PRTA_SRC7_CURR_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 14. "PRTA_SRC7_PREV_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 13. "PRTA_SRC6_CURR_ENC_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x24 12. "PRTA_SRC6_PREV_ENC_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x24 11. "PRTA_SRC5_CURR_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 10. "PRTA_SRC5_PREV_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 9. "PRTA_SRC4_CURR_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 8. "PRTA_SRC4_PREV_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 7. "PRTA_SRC3_CURR_ENC_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x24 6. "PRTA_SRC3_PREV_ENC_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x24 5. "PRTA_SRC2_CURR_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 4. "PRTA_SRC2_PREV_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 3. "PRTA_SRC1_CURR_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 2. "PRTA_SRC1_PREV_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 1. "PRTA_SRC0_CURR_ENC_FID,For Source ID 0 from Port A" "0,1" newline bitfld.long 0x24 0. "PRTA_SRC0_PREV_ENC_FID,For Source ID 0 from Port A" "0,1" line.long 0x28 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x28 31. "PRTB_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x28 30. "PRTB_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x28 29. "PRTB_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 28. "PRTB_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 27. "PRTB_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 26. "PRTB_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 25. "PRTB_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x28 24. "PRTB_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x28 23. "PRTB_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x28 22. "PRTB_SRC11_PREV_SOURCE_FID,For Source ID 11" "0,1" newline bitfld.long 0x28 21. "PRTB_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 20. "PRTB_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 19. "PRTB_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x28 18. "PRTB_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x28 17. "PRTB_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 16. "PRTB_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 15. "PRTB_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 14. "PRTB_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 13. "PRTB_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x28 12. "PRTB_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x28 11. "PRTB_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 10. "PRTB_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 9. "PRTB_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 8. "PRTB_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 7. "PRTB_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x28 6. "PRTB_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x28 5. "PRTB_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 4. "PRTB_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 3. "PRTB_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 2. "PRTB_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 1. "PRTB_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port B" "0,1" newline bitfld.long 0x28 0. "PRTB_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port B" "0,1" line.long 0x2C "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x2C 31. "PRTB_SRC15_CURR_ENC_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x2C 30. "PRTB_SRC15_PREV_ENC_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x2C 29. "PRTB_SRC14_CURR_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 28. "PRTB_SRC14_PREV_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 27. "PRTB_SRC13_CURR_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 26. "PRTB_SRC13_PREV_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 25. "PRTB_SRC12_CURR_ENC_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x2C 24. "PRTB_SRC12_PREV_ENC_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x2C 23. "PRTB_SRC11_CURR_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 22. "PRTB_SRC11_PREV_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 21. "PRTB_SRC10_CURR_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 20. "PRTB_SRC10_PREV_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 19. "PRTB_SRC9_CURR_ENC_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x2C 18. "PRTB_SRC9_PREV_ENC_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x2C 17. "PRTB_SRC8_CURR_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 16. "PRTB_SRC8_PREV_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 15. "PRTB_SRC7_CURR_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 14. "PRTB_SRC7_PREV_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 13. "PRTB_SRC6_CURR_ENC_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x2C 12. "PRTB_SRC6_PREV_ENC_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x2C 11. "PRTB_SRC5_CURR_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 10. "PRTB_SRC5_PREV_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 9. "PRTB_SRC4_CURR_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 8. "PRTB_SRC4_PREV_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 7. "PRTB_SRC3_CURR_ENC_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x2C 6. "PRTB_SRC3_PREV_ENC_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x2C 5. "PRTB_SRC2_CURR_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 4. "PRTB_SRC2_PREV_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 3. "PRTB_SRC1_CURR_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 2. "PRTB_SRC1_PREV_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 1. "PRTB_SRC0_CURR_ENC_FID,For Source ID 0 from Port B" "0,1" newline bitfld.long 0x2C 0. "PRTB_SRC0_PREV_ENC_FID,For Source ID 0 from Port B" "0,1" line.long 0x30 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" bitfld.long 0x30 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x30 16.--26. 1. "PRTA_SRC0_WIDTH,On Port A" newline bitfld.long 0x30 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x30 0.--10. 1. "PRTA_SRC0_HEIGHT,On Port A" line.long 0x34 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" bitfld.long 0x34 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x34 16.--26. 1. "PRTA_SRC1_WIDTH,On Port A" newline bitfld.long 0x34 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x34 0.--10. 1. "PRTA_SRC1_HEIGHT,On Port A" line.long 0x38 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" bitfld.long 0x38 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x38 16.--26. 1. "PRTA_SRC2_WIDTH,On Port A" newline bitfld.long 0x38 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x38 0.--10. 1. "PRTA_SRC2_HEIGHT,On Port A" line.long 0x3C "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" bitfld.long 0x3C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x3C 16.--26. 1. "PRTA_SRC3_WIDTH,On Port A" newline bitfld.long 0x3C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x3C 0.--10. 1. "PRTA_SRC3_HEIGHT,On Port A" line.long 0x40 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" bitfld.long 0x40 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x40 16.--26. 1. "PRTA_SRC4_WIDTH,On Port A" newline bitfld.long 0x40 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x40 0.--10. 1. "PRTA_SRC4_HEIGHT,On Port A" line.long 0x44 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" bitfld.long 0x44 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x44 16.--26. 1. "PRTA_SRC5_WIDTH,On Port A" newline bitfld.long 0x44 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x44 0.--10. 1. "PRTA_SRC5_HEIGHT,On Port A" line.long 0x48 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" bitfld.long 0x48 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 16.--26. 1. "PRTA_SRC6_WIDTH,On Port A" newline bitfld.long 0x48 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 0.--10. 1. "PRTA_SRC6_HEIGHT,On Port A" line.long 0x4C "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" bitfld.long 0x4C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x4C 16.--26. 1. "PRTA_SRC7_WIDTH,On Port A" newline bitfld.long 0x4C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x4C 0.--10. 1. "PRTA_SRC7_HEIGHT,On Port A" line.long 0x50 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" bitfld.long 0x50 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x50 16.--26. 1. "PRTA_SRC8_WIDTH,On Port A" newline bitfld.long 0x50 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x50 0.--10. 1. "PRTA_SRC8_HEIGHT,On Port A" line.long 0x54 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" bitfld.long 0x54 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x54 16.--26. 1. "PRTA_SRC9_WIDTH,On Port A" newline bitfld.long 0x54 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x54 0.--10. 1. "PRTA_SRC9_HEIGHT,On Port A" line.long 0x58 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" bitfld.long 0x58 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x58 16.--26. 1. "PRTA_SRC10_WIDTH,On Port A" newline bitfld.long 0x58 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x58 0.--10. 1. "PRTA_SRC10_HEIGHT,On Port A" line.long 0x5C "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" bitfld.long 0x5C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x5C 16.--26. 1. "PRTA_SRC11_WIDTH,On Port A" newline bitfld.long 0x5C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x5C 0.--10. 1. "PRTA_SRC11_HEIGHT,On Port A" line.long 0x60 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" bitfld.long 0x60 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x60 16.--26. 1. "PRTA_SRC12_WIDTH,On Port A" newline bitfld.long 0x60 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x60 0.--10. 1. "PRTA_SRC12_HEIGHT,On Port A" line.long 0x64 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" bitfld.long 0x64 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x64 16.--26. 1. "PRTA_SRC13_WIDTH,On Port A" newline bitfld.long 0x64 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x64 0.--10. 1. "PRTA_SRC13_HEIGHT,On Port A" line.long 0x68 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" bitfld.long 0x68 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x68 16.--26. 1. "PRTA_SRC14_WIDTH,On Port A" newline bitfld.long 0x68 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x68 0.--10. 1. "PRTA_SRC14_HEIGHT,On Port A" line.long 0x6C "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" bitfld.long 0x6C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x6C 16.--26. 1. "PRTA_SRC15_WIDTH,On Port A" newline bitfld.long 0x6C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x6C 0.--10. 1. "PRTA_SRC15_HEIGHT,On Port A" line.long 0x70 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" bitfld.long 0x70 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x70 16.--26. 1. "PRTB_SRC0_WIDTH,On Port B" newline bitfld.long 0x70 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x70 0.--10. 1. "PRTB_SRC0_HEIGHT,On Port B" line.long 0x74 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" bitfld.long 0x74 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x74 16.--26. 1. "PRTB_SRC1_WIDTH,On Port B" newline bitfld.long 0x74 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x74 0.--10. 1. "PRTB_SRC1_HEIGHT,On Port B" line.long 0x78 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" bitfld.long 0x78 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x78 16.--26. 1. "PRTB_SRC2_WIDTH,On Port B" newline bitfld.long 0x78 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x78 0.--10. 1. "PRTB_SRC2_HEIGHT,On Port B" line.long 0x7C "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" bitfld.long 0x7C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x7C 16.--26. 1. "PRTB_SRC3_WIDTH,On Port B" newline bitfld.long 0x7C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x7C 0.--10. 1. "PRTB_SRC3_HEIGHT,On Port B" line.long 0x80 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" bitfld.long 0x80 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x80 16.--26. 1. "PRTB_SRC4_WIDTH,On Port B" newline bitfld.long 0x80 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x80 0.--10. 1. "PRTB_SRC4_HEIGHT,On Port B" line.long 0x84 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" bitfld.long 0x84 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x84 16.--26. 1. "PRTB_SRC5_WIDTH,On Port B" newline bitfld.long 0x84 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x84 0.--10. 1. "PRTB_SRC5_HEIGHT,On Port B" line.long 0x88 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" bitfld.long 0x88 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x88 16.--26. 1. "PRTB_SRC6_WIDTH,On Port B" newline bitfld.long 0x88 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x88 0.--10. 1. "PRTB_SRC6_HEIGHT,On Port B" line.long 0x8C "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" bitfld.long 0x8C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x8C 16.--26. 1. "PRTB_SRC7_WIDTH,On Port B" newline bitfld.long 0x8C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x8C 0.--10. 1. "PRTB_SRC7_HEIGHT,On Port B" line.long 0x90 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" bitfld.long 0x90 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x90 16.--26. 1. "PRTB_SRC8_WIDTH,On Port B" newline bitfld.long 0x90 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x90 0.--10. 1. "PRTB_SRC8_HEIGHT,On Port B" line.long 0x94 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" bitfld.long 0x94 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x94 16.--26. 1. "PRTB_SRC9_WIDTH,On Port B" newline bitfld.long 0x94 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x94 0.--10. 1. "PRTB_SRC9_HEIGHT,On Port B" line.long 0x98 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" bitfld.long 0x98 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x98 16.--26. 1. "PRTB_SRC10_WIDTH,On Port B" newline bitfld.long 0x98 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x98 0.--10. 1. "PRTB_SRC10_HEIGHT,On Port B" line.long 0x9C "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" bitfld.long 0x9C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x9C 16.--26. 1. "PRTB_SRC11_WIDTH,On Port B" newline bitfld.long 0x9C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x9C 0.--10. 1. "PRTB_SRC11_HEIGHT,On Port B" line.long 0xA0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" bitfld.long 0xA0 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA0 16.--26. 1. "PRTB_SRC12_WIDTH,On Port B" newline bitfld.long 0xA0 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA0 0.--10. 1. "PRTB_SRC12_HEIGHT,On Port B" line.long 0xA4 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" bitfld.long 0xA4 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA4 16.--26. 1. "PRTB_SRC13_WIDTH,On Port B" newline bitfld.long 0xA4 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA4 0.--10. 1. "PRTB_SRC13_HEIGHT,On Port B" line.long 0xA8 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" bitfld.long 0xA8 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA8 16.--26. 1. "PRTB_SRC14_WIDTH,On Port B" newline bitfld.long 0xA8 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA8 0.--10. 1. "PRTB_SRC14_HEIGHT,On Port B" line.long 0xAC "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" bitfld.long 0xAC 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xAC 16.--26. 1. "PRTB_SRC15_WIDTH,On Port B" newline bitfld.long 0xAC 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xAC 0.--10. 1. "PRTB_SRC15_HEIGHT,On Port B" line.long 0xB0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB4 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB8 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" bitfld.long 0xB8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xB8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xB8 15. "ANC_BYPASS_N," "0,1" newline rbitfld.long 0xB8 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xB8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xBC "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" rbitfld.long 0xBC 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xBC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline rbitfld.long 0xBC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xBC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xC0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" bitfld.long 0xC0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xC0 15. "ACT_BYPASS_N," "0,1" newline rbitfld.long 0xC0 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xC4 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" rbitfld.long 0xC4 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC4 16.--27. 1. "ACT_USE_NUMLINES,When cropping" newline rbitfld.long 0xC4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xC8 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" bitfld.long 0xC8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xC8 15. "ANC_BYPASS_N," "0,1" newline rbitfld.long 0xC8 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xCC "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" rbitfld.long 0xCC 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xCC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline rbitfld.long 0xCC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xCC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xD0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" bitfld.long 0xD0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xD0 15. "ACT_BYPASS_N," "0,1" newline rbitfld.long 0xD0 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xD0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xD4 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" rbitfld.long 0xD4 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD4 16.--27. 1. "ACT_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline rbitfld.long 0xD4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xD8 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0xD8 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" newline hexmask.long.word 0xD8 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xDC "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0xDC 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" newline hexmask.long.word 0xDC 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xE0 "VIP_XTRA8_PORT_A,Reserved Register for Port A" line.long 0xE4 "VIP_XTRA9_PORT_B,Reserved Register for Port B" width 0x0B tree.end tree "VIP_Slice0_sc" base ad:0x48975800 group.long 0x00++0x1B line.long 0x00 "VIP_CFG_SC0," hexmask.long.word 0x00 17.--31. 1. "RESERVED," newline bitfld.long 0x00 16. "CFG_FID_SELFGEN,FID self generate enable" "0,1" newline bitfld.long 0x00 15. "CFG_TRIM,Trimming enable" "disable trimming,enable trimming" newline bitfld.long 0x00 14. "CFG_Y_PK_EN,This parameter is used by peaking block" "disable luma peaking,enable luma peaking" newline rbitfld.long 0x00 11.--13. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10. "CFG_INTERLACE_I,This parameter is used by both horizontal and vertical scaling" "the input video format is progressive,the input video format is interlace" newline bitfld.long 0x00 9. "CFG_HP_BYPASS,This parameter is used by horizontal scaling" "The polyphase scaler is always used regardless..,The polyphase scaler is bypassed only when.." newline bitfld.long 0x00 8. "CFG_DCM_4X,This parameter is used by horizontal scaling" "the 4X decimation filter is disabled,the 4X decimation filter is enabled" newline bitfld.long 0x00 7. "CFG_DCM_2X,This parameter is used by horizontal scaling" "the 2X decimation filter is disabled,the 2X decimation filter is enabled" newline bitfld.long 0x00 6. "CFG_AUTO_HS,This parameter is used by horizontal scaling" "the cfg_dcm_2x and cfg_dcm_4x bits will enable..,HW will decide whether up-scaling or.." newline bitfld.long 0x00 5. "CFG_ENABLE_EV,This parameter is used by the edge-detection block" "The output of edge-detection block will be force..,The calculation results of edge-detection block.." newline bitfld.long 0x00 4. "CFG_USE_RAV,This parameter is used by vertical scaling" "Poly-phase filter will be used for the vertical..,Running average filter will be used for the.." newline bitfld.long 0x00 3. "CFG_INVT_FID,This parameter is used by vertical scaling" "Progressive input,Interlaced input Must be set to 1 when.." newline bitfld.long 0x00 2. "CFG_SC_BYPASS,This parameter is a general purpose" "Scaling module will engaged,Scaling module will be bypassed" newline bitfld.long 0x00 1. "CFG_LINEAR,This parameter is used by horizontal scaling" "Anamorphic scaling,Linear scaling" newline bitfld.long 0x00 0. "CFG_INTERLACE_O,This parameter is used by vertical scaling" "The output format of SC is progressive,The output format of SC is interlace" line.long 0x04 "VIP_CFG_SC1," rbitfld.long 0x04 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long 0x04 0.--26. 1. "CFG_ROW_ACC_INC,This parameter is used by vertical scaling" line.long 0x08 "VIP_CFG_SC2," rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x08 0.--27. 1. "CFG_ROW_ACC_OFFSET,This parameter is used by vertical scaling" line.long 0x0C "VIP_CFG_SC3," rbitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x0C 0.--27. 1. "CFG_ROW_ACC_OFFSET_B,This parameter is used by vertical scaling" line.long 0x10 "VIP_CFG_SC4," rbitfld.long 0x10 31. "RESERVED," "0,1" newline bitfld.long 0x10 28.--30. "CFG_NLIN_ACC_INIT_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED," "0,1" newline bitfld.long 0x10 24.--26. "CFG_LIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED," "0,1" newline hexmask.long.word 0x10 12.--22. 1. "CFG_TAR_W,This parameter is a general purpose" newline rbitfld.long 0x10 11. "RESERVED," "0,1" newline hexmask.long.word 0x10 0.--10. 1. "CFG_TAR_H,This parameter is a general purpose" line.long 0x14 "VIP_CFG_SC5," rbitfld.long 0x14 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 24.--26. "CFG_NLIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED," "0,1" newline hexmask.long.word 0x14 12.--22. 1. "CFG_SRC_W,This parameter is a general purpose" newline rbitfld.long 0x14 11. "RESERVED," "0,1" newline hexmask.long.word 0x14 0.--10. 1. "CFG_SRC_H,This parameter is a general purpose" line.long 0x18 "VIP_CFG_SC6," hexmask.long.word 0x18 20.--31. 1. "RESERVED," newline hexmask.long.word 0x18 10.--19. 1. "CFG_ROW_ACC_INIT_RAV_B,This parameter is used by vertical scaling" newline hexmask.long.word 0x18 0.--9. 1. "CFG_ROW_ACC_INIT_RAV,This parameter is used by vertical scaling" group.long 0x20++0x17 line.long 0x00 "VIP_CFG_SC8," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.word 0x00 12.--22. 1. "CFG_NLIN_RIGHT,This parameter is used by horizontal scaling" newline rbitfld.long 0x00 11. "RESERVED," "0,1" newline hexmask.long.word 0x00 0.--10. 1. "CFG_NLIN_LEFT,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC9," line.long 0x08 "VIP_CFG_SC10," line.long 0x0C "VIP_CFG_SC11," line.long 0x10 "VIP_CFG_SC12," hexmask.long.byte 0x10 25.--31. 1. "RESERVED," newline hexmask.long 0x10 0.--24. 1. "CFG_COL_ACC_OFFSET,This parameter is used in horizontal scaling" line.long 0x14 "VIP_CFG_SC13," hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," newline hexmask.long.word 0x14 0.--9. 1. "CFG_SC_FACTOR_RAV,This parameter is used by vertical scaling" group.long 0x48++0x13 line.long 0x00 "VIP_CFG_SC18," hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--9. 1. "CFG_HS_FACTOR,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC19," hexmask.long.byte 0x04 24.--31. 1. "CFG_HPF_COEF3,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 16.--23. 1. "CFG_HPF_COEF2,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 8.--15. 1. "CFG_HPF_COEF1,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 0.--7. 1. "CFG_HPF_COEF0,This parameter is used by the peaking block" line.long 0x08 "VIP_CFG_SC20," rbitfld.long 0x08 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x08 20.--28. 1. "CFG_NL_LIMIT,This parameter is used by the peaking block" newline rbitfld.long 0x08 19. "RESERVED," "0,1" newline bitfld.long 0x08 16.--18. "CFG_HPF_NORM_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 8.--15. 1. "CFG_HPF_COEF5,This parameter is used by the peaking block" newline hexmask.long.byte 0x08 0.--7. 1. "CFG_HPF_COEF4,This parameter is used by the peaking block" line.long 0x0C "VIP_CFG_SC21," hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x0C 16.--23. 1. "CFG_NL_LO_SLOPE,This parameter is used by the peaking block" newline hexmask.long.byte 0x0C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--8. 1. "CFG_NL_LO_THR,This parameter is used by the peaking block" line.long 0x10 "VIP_CFG_SC22," hexmask.long.word 0x10 19.--31. 1. "RESERVED," newline bitfld.long 0x10 16.--18. "CFG_NL_HI_SLOPE_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED," newline hexmask.long.word 0x10 0.--8. 1. "CFG_NL_HI_THR,This parameter is used by the peaking block" group.long 0x60++0x07 line.long 0x00 "VIP_CFG_SC24," rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 16.--26. 1. "CFG_ORG_W,This parameter is used by the trimmer" newline rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--10. 1. "CFG_ORG_H,This parameter is used by the trimmer" line.long 0x04 "VIP_CFG_SC25," rbitfld.long 0x04 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x04 16.--26. 1. "CFG_OFF_W,This parameter is used by the trimmer" newline rbitfld.long 0x04 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x04 0.--10. 1. "CFG_OFF_H,This parameter is used by the trimmer" width 0x0B tree.end tree "VIP_Slice1_csc" base ad:0x48975C00 group.long 0x00++0x17 line.long 0x00 "VIP_CSC00," bitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "B0,Coefficients of color space converter" bitfld.long 0x00 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--12. 1. "A0,Coefficients of color space converter" line.long 0x04 "VIP_CSC01," bitfld.long 0x04 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 16.--28. 1. "A1,Coefficients of color space converter" bitfld.long 0x04 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 0.--12. 1. "C0,Coefficients of color space converter" line.long 0x08 "VIP_CSC02," bitfld.long 0x08 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 16.--28. 1. "C1,Coefficients of color space converter" bitfld.long 0x08 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--12. 1. "B1,Coefficients of color space converter" line.long 0x0C "VIP_CSC03," bitfld.long 0x0C 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 16.--28. 1. "B2,Coefficients of color space converter" bitfld.long 0x0C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 0.--12. 1. "A2,Coefficients of color space converter" line.long 0x10 "VIP_CSC04," bitfld.long 0x10 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x10 16.--27. 1. "D0,Coefficients of color space converter" bitfld.long 0x10 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--12. 1. "C2,Coefficients of color space converter" line.long 0x14 "VIP_CSC05," bitfld.long 0x14 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x14 28. "BYPASS,Full CSC bypass mode" "0,1" hexmask.long.word 0x14 16.--27. 1. "D2,Coefficients of color space converter" bitfld.long 0x14 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x14 0.--11. 1. "D1,Coefficients of color space converter" width 0x0B tree.end tree "VIP_Slice1_parser" base ad:0x48975A00 group.long 0x00++0xE7 line.long 0x00 "VIP_MAIN,ain Configuration for VIP Parser" hexmask.long 0x00 6.--31. 1. "RESERVED," newline bitfld.long 0x00 5. "CLIP_ACTIVE,Discrete Sync Only" "Do not clip active pixels,Clip Active Pixels as follows" newline bitfld.long 0x00 4. "CLIP_BLNK,Discrete Sync Only" "Do not clip Blanking Data,Clip Blanking Data as follows" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 0.--1. "DATA_INTERFACE_MODE," "?,16b data interface,Dual independent 8b data interfaces,Undefined" line.long 0x04 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x04 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "Ignore the protection bits in the XV (fvh)..,Use the protection bits in an attempt to do.." newline bitfld.long 0x04 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "For 2x/4x mux mode srcnum is in the least..,For 2x/4x mux mode srcnum is in the least.." newline bitfld.long 0x04 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. "SW_RESET," "0,1" newline bitfld.long 0x04 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "Normal Discrete Mode,Basic Discrete Mode" newline bitfld.long 0x04 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "Use HSYNC style line capture,Use ACTVID style line capture" newline bitfld.long 0x04 14. "FID_DETECT_MODE,Discrete Sync Only" "Take FID from pin,FID is determined by VSYNC skew" newline bitfld.long 0x04 13. "ACTVID_POLARITY,Discrete Sync Only" "ACTVID is active low,ACTVID is active high" newline bitfld.long 0x04 12. "VSYNC_POLARITY,Discrete Sync Only" "VSYNC is active low,VSYNC is active high" newline bitfld.long 0x04 11. "HSYNC_POLARITY,Discrete Sync Only" "HSYNC is active low,HSYNC is active high" newline bitfld.long 0x04 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x04 9. "FID_POLARITY," "0,1" newline bitfld.long 0x04 8. "ENABLE," "0,1" newline bitfld.long 0x04 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x04 6. "CLR_ASYNC_FIFO_WR," "0,1" newline bitfld.long 0x04 4.--5. "CTRL_CHAN_SEL,Embedded Sync Only In 8b mode" "Use data[7:0] to extract control codes,Use data[15:8] to extract control codes,Use data[23:16] to extract control codes,Undefined In 16b and 24b modes" newline bitfld.long 0x04 0.--3. "SYNC_TYPE," "?,embedded sync 2x multiplexed 4:2:2 YUV stream,embedded sync 4x multiplexed 4:2:2 YUV stream,embedded sync line multiplexed 4:2:2 YUV stream,discrete sync single 4:2:2 YUV stream,embedded sync single RGB stream or single 444..,reserved,reserved,reserved,reserved,discrete sync single 24b RGB stream,?..." line.long 0x08 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" rbitfld.long 0x08 31. "RESERVED," "0,1" newline bitfld.long 0x08 28.--30. "REPACK_SEL," "?,Cross Swap,Left Center Swap,Center Right Swap,Right Rotate,Left Rotate,RAW16 to RGB565 Mapping,RAW12 Swap" newline hexmask.long.word 0x08 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" newline rbitfld.long 0x08 15. "RESERVED," "0,1" newline bitfld.long 0x08 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "Extract 8b Mode Vertical Ancillary Data from..,Extract 8b Mode Vertical Ancillary Data from..,?,Extract every single sample of vertical.." newline rbitfld.long 0x08 12. "RESERVED," "0,1" newline hexmask.long.word 0x08 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x0C "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0C 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "Ignore the protection bits in the XV (fvh)..,Use the protection bits in an attempt to do.." newline bitfld.long 0x0C 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "For 2x/4x mux mode srcnum is in the least..,For 2x/4x mux mode srcnum is in the least.." newline bitfld.long 0x0C 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 23. "SW_RESET," "0,1" newline bitfld.long 0x0C 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "Normal Discrete Mode,Basic Discrete Mode" newline bitfld.long 0x0C 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "Use HSYNC style line capture,Use ACTVID style line capture" newline bitfld.long 0x0C 14. "FID_DETECT_MODE,Discrete Sync Only" "Take FID from pin,FID is determined by VSYNC skew" newline bitfld.long 0x0C 13. "ACTVID_POLARITY,Discrete Sync Only" "ACTVID is active low,ACTVID is active high" newline bitfld.long 0x0C 12. "VSYNC_POLARITY,Discrete Sync Only" "VSYNC is active low,VSYNC is active high" newline bitfld.long 0x0C 11. "HSYNC_POLARITY,Discrete Sync Only" "HSYNC is active low,HSYNC is active high" newline bitfld.long 0x0C 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x0C 9. "FID_POLARITY," "0,1" newline bitfld.long 0x0C 8. "ENABLE," "0,1" newline bitfld.long 0x0C 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x0C 6. "CLR_ASYNC_FIFO_WR," "0,1" newline bitfld.long 0x0C 4.--5. "CTRL_CHAN_SEL,PORT B supports on 8b mode" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "SYNC_TYPE," "?,embedded sync 2x multiplexed YUV stream,embedded sync 4x multiplexed YUV stream,embedded sync line multiplexed YUV stream,discrete sync single YUV stream,embedded sync single RGB stream,reserved,reserved,reserved,reserved,discrete sync single 24b RGB stream,?..." line.long 0x10 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" rbitfld.long 0x10 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x10 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" newline rbitfld.long 0x10 15. "RESERVED," "0,1" newline bitfld.long 0x10 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "Extract 8b Mode Vertical Ancillary Data from..,Extract 8b Mode Vertical Ancillary Data from..,?,Extract every single sample of vertical.." newline rbitfld.long 0x10 12. "RESERVED," "0,1" newline hexmask.long.word 0x10 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x14 "VIP_FIQ_MASK,ask Bits for ARM FIQs" hexmask.long.word 0x14 22.--31. 1. "RESERVED," newline bitfld.long 0x14 21. "PORT_B_CFG_DISABLE_COMPLETE_MASK,Port B Cfg Disable Complete Mask" "0,1" newline bitfld.long 0x14 20. "PORT_A_CFG_DISABLE_COMPLETE_MASK,Port A Cfg Disable Complete Mask" "0,1" newline bitfld.long 0x14 19. "PORT_B_ANC_PROTOCOL_VIOLATION_MASK,Port B ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 18. "PORT_B_YUV_PROTOCOL_VIOLATION_MASK,Port B YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 17. "PORT_A_ANC_PROTOCOL_VIOLATION_MASK,Port A ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 16. "PORT_A_YUV_PROTOCOL_VIOLATION_MASK,Port A YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 15. "PORT_B_SRC0_SIZE,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" newline bitfld.long 0x14 14. "PORT_A_SRC0_SIZE,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" newline bitfld.long 0x14 13. "PORT_B_DISCONN,Port B Link Disconnect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 12. "PORT_B_CONN,Port B Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 11. "PORT_A_DISCONN,Port A Link Disconnect Scrnum 0 Mask" "0,1" newline bitfld.long 0x14 10. "PORT_A_CONN,Port A Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 9. "OUTPUT_FIFO_PRTB_ANC_OF,Output FIFO Port B Ancillary Overflow Mask" "0,1" newline rbitfld.long 0x14 8. "RESERVED," "0,1" newline bitfld.long 0x14 7. "OUTPUT_FIFO_PRTB_YUV_OF,Output FIFO Port B Luma Overflow Mask" "0,1" newline bitfld.long 0x14 6. "OUTPUT_FIFO_PRTA_ANC_OF,Output FIFO Port A Ancillary Overflow Mask" "0,1" newline rbitfld.long 0x14 5. "RESERVED," "0,1" newline bitfld.long 0x14 4. "OUTPUT_FIFO_PRTA_YUV_OF,Output FIFO Port A Luma Overflow Mask" "0,1" newline bitfld.long 0x14 3. "ASYNC_FIFO_PRTB_OF,Port B Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 2. "ASYNC_FIFO_PRTA_OF,Port A Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 1. "PRTB_VDET_MASK,Port B Video Detect FIQ Mask" "0,1" newline bitfld.long 0x14 0. "PRTA_VDET_MASK,Port A Video Detect FIQ Mask" "0,1" line.long 0x18 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" hexmask.long.word 0x18 22.--31. 1. "RESERVED," newline bitfld.long 0x18 21. "PORT_A_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x18 20. "PORT_A_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x18 19. "PORT_B_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 18. "PORT_B_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 17. "PORT_A_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 16. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 15. "PORT_B_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" newline bitfld.long 0x18 14. "PORT_A_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" newline bitfld.long 0x18 13. "PORT_B_DISCONN_CLR,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 12. "PORT_B_CONN_CLR,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" newline bitfld.long 0x18 11. "PORT_A_DISCONN_CLR,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 10. "PORT_A_CONN_CLR,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" newline bitfld.long 0x18 9. "OUTPUT_FIFO_PRTB_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" newline rbitfld.long 0x18 8. "RESERVED," "0,1" newline bitfld.long 0x18 7. "OUTPUT_FIFO_PRTB_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" newline bitfld.long 0x18 6. "OUTPUT_FIFO_PRTA_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" newline rbitfld.long 0x18 5. "RESERVED," "0,1" newline bitfld.long 0x18 4. "OUTPUT_FIFO_PRTA_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" newline bitfld.long 0x18 3. "ASYNC_FIFO_PRTB_CLR,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" newline bitfld.long 0x18 2. "ASYNC_FIFO_PRTA_CLR,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" newline bitfld.long 0x18 1. "PRTB_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" newline bitfld.long 0x18 0. "PRTA_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" line.long 0x1C "VIP_FIQ_STATUS,FIQ Status values" hexmask.long.word 0x1C 22.--31. 1. "RESERVED," newline bitfld.long 0x1C 21. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Port B Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x1C 20. "PORT_A_CFG_DISABLE_COMPLETE,Port A Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x1C 19. "PORT_B_ANC_PROTOCOL_VIOLATION,Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 18. "PORT_B_YUV_PROTOCOL_VIOLATION,Port B YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 17. "PORT_A_ANC_PROTOCOL_VIOLATION,Port A ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 16. "PORT_A_YUV_PROTOCOL_VIOLATION,Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 15. "PORT_B_SRC0_SIZE_STATUS,Port B Source 0 Size FIQ" "0,1" newline bitfld.long 0x1C 14. "PORT_A_SRC0_SIZE_STATUS,Port A Source 0 Size FIQ" "0,1" newline bitfld.long 0x1C 13. "PORT_B_DISCONN_STATUS,Port B Disconnect FIQ" "0,1" newline bitfld.long 0x1C 12. "PORT_B_CONN_STATUS,Port B Connect FIQ" "0,1" newline bitfld.long 0x1C 11. "PORT_A_DISCONN_STATUS,Port A Disconnect FIQ" "0,1" newline bitfld.long 0x1C 10. "PORT_A_CONN_STATUS,Port A Connect FIQ" "0,1" newline bitfld.long 0x1C 9. "OUTPUT_FIFO_PRTB_ANC_STATUS,Output FIFO Port B Ancillary Overflow Status" "0,1" newline bitfld.long 0x1C 8. "OUTPUT_FIFO_PRTB_CHROMA_STATUS,Output FIFO Port B Chroma Overflow Status" "0,1" newline bitfld.long 0x1C 7. "OUTPUT_FIFO_PRTB_LUMA_STATUS,Output FIFO Port B Luma Overflow Status" "0,1" newline bitfld.long 0x1C 6. "OUTPUT_FIFO_PRTA_ANC_STATUS,Output FIFO Port A Ancillary Overflow Status" "0,1" newline bitfld.long 0x1C 5. "OUTPUT_FIFO_PRTA_CHROMA_STATUS,Output FIFO Port A Chroma Overflow Status" "0,1" newline bitfld.long 0x1C 4. "OUTPUT_FIFO_PRTA_LUMA_STATUS,Output FIFO Port A Luma Overflow Status" "0,1" newline bitfld.long 0x1C 3. "ASYNC_FIFO_PRTB_STATUS,Async FIFO Port B Overflow Status" "0,1" newline bitfld.long 0x1C 2. "ASYNC_FIFO_PRTA_STATUS,Async FIFO Port A Overflow Status" "0,1" newline bitfld.long 0x1C 1. "PRTB_VDET_STATUS,VDET Status for Port B" "0,1" newline bitfld.long 0x1C 0. "PRTA_VDET_STATUS,VDET Status for Port A" "0,1" line.long 0x20 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x20 31. "PRTA_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x20 30. "PRTA_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x20 29. "PRTA_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 28. "PRTA_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 27. "PRTA_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 26. "PRTA_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 25. "PRTA_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x20 24. "PRTA_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x20 23. "PRTA_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 22. "PRTA_SRC11_PREV_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 21. "PRTA_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 20. "PRTA_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 19. "PRTA_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x20 18. "PRTA_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x20 17. "PRTA_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 16. "PRTA_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 15. "PRTA_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 14. "PRTA_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 13. "PRTA_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x20 12. "PRTA_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x20 11. "PRTA_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 10. "PRTA_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 9. "PRTA_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 8. "PRTA_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 7. "PRTA_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x20 6. "PRTA_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x20 5. "PRTA_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 4. "PRTA_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 3. "PRTA_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 2. "PRTA_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 1. "PRTA_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port A" "0,1" newline bitfld.long 0x20 0. "PRTA_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port A" "0,1" line.long 0x24 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x24 31. "PRTA_SRC15_CURR_ENC_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x24 30. "PRTA_SRC15_PREV_ENC_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x24 29. "PRTA_SRC14_CURR_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 28. "PRTA_SRC14_PREV_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 27. "PRTA_SRC13_CURR_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 26. "PRTA_SRC13_PREV_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 25. "PRTA_SRC12_CURR_ENC_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x24 24. "PRTA_SRC12_PREV_ENC_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x24 23. "PRTA_SRC11_CURR_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 22. "PRTA_SRC11_PREV_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 21. "PRTA_SRC10_CURR_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 20. "PRTA_SRC10_PREV_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 19. "PRTA_SRC9_CURR_ENC_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x24 18. "PRTA_SRC9_PREV_ENC_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x24 17. "PRTA_SRC8_CURR_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 16. "PRTA_SRC8_PREV_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 15. "PRTA_SRC7_CURR_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 14. "PRTA_SRC7_PREV_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 13. "PRTA_SRC6_CURR_ENC_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x24 12. "PRTA_SRC6_PREV_ENC_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x24 11. "PRTA_SRC5_CURR_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 10. "PRTA_SRC5_PREV_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 9. "PRTA_SRC4_CURR_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 8. "PRTA_SRC4_PREV_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 7. "PRTA_SRC3_CURR_ENC_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x24 6. "PRTA_SRC3_PREV_ENC_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x24 5. "PRTA_SRC2_CURR_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 4. "PRTA_SRC2_PREV_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 3. "PRTA_SRC1_CURR_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 2. "PRTA_SRC1_PREV_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 1. "PRTA_SRC0_CURR_ENC_FID,For Source ID 0 from Port A" "0,1" newline bitfld.long 0x24 0. "PRTA_SRC0_PREV_ENC_FID,For Source ID 0 from Port A" "0,1" line.long 0x28 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x28 31. "PRTB_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x28 30. "PRTB_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x28 29. "PRTB_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 28. "PRTB_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 27. "PRTB_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 26. "PRTB_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 25. "PRTB_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x28 24. "PRTB_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x28 23. "PRTB_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x28 22. "PRTB_SRC11_PREV_SOURCE_FID,For Source ID 11" "0,1" newline bitfld.long 0x28 21. "PRTB_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 20. "PRTB_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 19. "PRTB_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x28 18. "PRTB_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x28 17. "PRTB_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 16. "PRTB_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 15. "PRTB_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 14. "PRTB_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 13. "PRTB_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x28 12. "PRTB_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x28 11. "PRTB_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 10. "PRTB_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 9. "PRTB_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 8. "PRTB_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 7. "PRTB_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x28 6. "PRTB_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x28 5. "PRTB_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 4. "PRTB_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 3. "PRTB_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 2. "PRTB_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 1. "PRTB_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port B" "0,1" newline bitfld.long 0x28 0. "PRTB_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port B" "0,1" line.long 0x2C "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x2C 31. "PRTB_SRC15_CURR_ENC_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x2C 30. "PRTB_SRC15_PREV_ENC_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x2C 29. "PRTB_SRC14_CURR_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 28. "PRTB_SRC14_PREV_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 27. "PRTB_SRC13_CURR_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 26. "PRTB_SRC13_PREV_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 25. "PRTB_SRC12_CURR_ENC_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x2C 24. "PRTB_SRC12_PREV_ENC_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x2C 23. "PRTB_SRC11_CURR_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 22. "PRTB_SRC11_PREV_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 21. "PRTB_SRC10_CURR_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 20. "PRTB_SRC10_PREV_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 19. "PRTB_SRC9_CURR_ENC_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x2C 18. "PRTB_SRC9_PREV_ENC_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x2C 17. "PRTB_SRC8_CURR_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 16. "PRTB_SRC8_PREV_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 15. "PRTB_SRC7_CURR_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 14. "PRTB_SRC7_PREV_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 13. "PRTB_SRC6_CURR_ENC_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x2C 12. "PRTB_SRC6_PREV_ENC_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x2C 11. "PRTB_SRC5_CURR_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 10. "PRTB_SRC5_PREV_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 9. "PRTB_SRC4_CURR_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 8. "PRTB_SRC4_PREV_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 7. "PRTB_SRC3_CURR_ENC_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x2C 6. "PRTB_SRC3_PREV_ENC_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x2C 5. "PRTB_SRC2_CURR_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 4. "PRTB_SRC2_PREV_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 3. "PRTB_SRC1_CURR_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 2. "PRTB_SRC1_PREV_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 1. "PRTB_SRC0_CURR_ENC_FID,For Source ID 0 from Port B" "0,1" newline bitfld.long 0x2C 0. "PRTB_SRC0_PREV_ENC_FID,For Source ID 0 from Port B" "0,1" line.long 0x30 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" bitfld.long 0x30 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x30 16.--26. 1. "PRTA_SRC0_WIDTH,On Port A" newline bitfld.long 0x30 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x30 0.--10. 1. "PRTA_SRC0_HEIGHT,On Port A" line.long 0x34 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" bitfld.long 0x34 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x34 16.--26. 1. "PRTA_SRC1_WIDTH,On Port A" newline bitfld.long 0x34 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x34 0.--10. 1. "PRTA_SRC1_HEIGHT,On Port A" line.long 0x38 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" bitfld.long 0x38 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x38 16.--26. 1. "PRTA_SRC2_WIDTH,On Port A" newline bitfld.long 0x38 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x38 0.--10. 1. "PRTA_SRC2_HEIGHT,On Port A" line.long 0x3C "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" bitfld.long 0x3C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x3C 16.--26. 1. "PRTA_SRC3_WIDTH,On Port A" newline bitfld.long 0x3C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x3C 0.--10. 1. "PRTA_SRC3_HEIGHT,On Port A" line.long 0x40 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" bitfld.long 0x40 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x40 16.--26. 1. "PRTA_SRC4_WIDTH,On Port A" newline bitfld.long 0x40 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x40 0.--10. 1. "PRTA_SRC4_HEIGHT,On Port A" line.long 0x44 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" bitfld.long 0x44 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x44 16.--26. 1. "PRTA_SRC5_WIDTH,On Port A" newline bitfld.long 0x44 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x44 0.--10. 1. "PRTA_SRC5_HEIGHT,On Port A" line.long 0x48 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" bitfld.long 0x48 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 16.--26. 1. "PRTA_SRC6_WIDTH,On Port A" newline bitfld.long 0x48 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 0.--10. 1. "PRTA_SRC6_HEIGHT,On Port A" line.long 0x4C "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" bitfld.long 0x4C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x4C 16.--26. 1. "PRTA_SRC7_WIDTH,On Port A" newline bitfld.long 0x4C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x4C 0.--10. 1. "PRTA_SRC7_HEIGHT,On Port A" line.long 0x50 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" bitfld.long 0x50 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x50 16.--26. 1. "PRTA_SRC8_WIDTH,On Port A" newline bitfld.long 0x50 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x50 0.--10. 1. "PRTA_SRC8_HEIGHT,On Port A" line.long 0x54 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" bitfld.long 0x54 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x54 16.--26. 1. "PRTA_SRC9_WIDTH,On Port A" newline bitfld.long 0x54 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x54 0.--10. 1. "PRTA_SRC9_HEIGHT,On Port A" line.long 0x58 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" bitfld.long 0x58 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x58 16.--26. 1. "PRTA_SRC10_WIDTH,On Port A" newline bitfld.long 0x58 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x58 0.--10. 1. "PRTA_SRC10_HEIGHT,On Port A" line.long 0x5C "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" bitfld.long 0x5C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x5C 16.--26. 1. "PRTA_SRC11_WIDTH,On Port A" newline bitfld.long 0x5C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x5C 0.--10. 1. "PRTA_SRC11_HEIGHT,On Port A" line.long 0x60 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" bitfld.long 0x60 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x60 16.--26. 1. "PRTA_SRC12_WIDTH,On Port A" newline bitfld.long 0x60 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x60 0.--10. 1. "PRTA_SRC12_HEIGHT,On Port A" line.long 0x64 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" bitfld.long 0x64 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x64 16.--26. 1. "PRTA_SRC13_WIDTH,On Port A" newline bitfld.long 0x64 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x64 0.--10. 1. "PRTA_SRC13_HEIGHT,On Port A" line.long 0x68 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" bitfld.long 0x68 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x68 16.--26. 1. "PRTA_SRC14_WIDTH,On Port A" newline bitfld.long 0x68 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x68 0.--10. 1. "PRTA_SRC14_HEIGHT,On Port A" line.long 0x6C "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" bitfld.long 0x6C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x6C 16.--26. 1. "PRTA_SRC15_WIDTH,On Port A" newline bitfld.long 0x6C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x6C 0.--10. 1. "PRTA_SRC15_HEIGHT,On Port A" line.long 0x70 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" bitfld.long 0x70 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x70 16.--26. 1. "PRTB_SRC0_WIDTH,On Port B" newline bitfld.long 0x70 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x70 0.--10. 1. "PRTB_SRC0_HEIGHT,On Port B" line.long 0x74 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" bitfld.long 0x74 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x74 16.--26. 1. "PRTB_SRC1_WIDTH,On Port B" newline bitfld.long 0x74 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x74 0.--10. 1. "PRTB_SRC1_HEIGHT,On Port B" line.long 0x78 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" bitfld.long 0x78 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x78 16.--26. 1. "PRTB_SRC2_WIDTH,On Port B" newline bitfld.long 0x78 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x78 0.--10. 1. "PRTB_SRC2_HEIGHT,On Port B" line.long 0x7C "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" bitfld.long 0x7C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x7C 16.--26. 1. "PRTB_SRC3_WIDTH,On Port B" newline bitfld.long 0x7C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x7C 0.--10. 1. "PRTB_SRC3_HEIGHT,On Port B" line.long 0x80 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" bitfld.long 0x80 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x80 16.--26. 1. "PRTB_SRC4_WIDTH,On Port B" newline bitfld.long 0x80 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x80 0.--10. 1. "PRTB_SRC4_HEIGHT,On Port B" line.long 0x84 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" bitfld.long 0x84 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x84 16.--26. 1. "PRTB_SRC5_WIDTH,On Port B" newline bitfld.long 0x84 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x84 0.--10. 1. "PRTB_SRC5_HEIGHT,On Port B" line.long 0x88 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" bitfld.long 0x88 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x88 16.--26. 1. "PRTB_SRC6_WIDTH,On Port B" newline bitfld.long 0x88 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x88 0.--10. 1. "PRTB_SRC6_HEIGHT,On Port B" line.long 0x8C "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" bitfld.long 0x8C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x8C 16.--26. 1. "PRTB_SRC7_WIDTH,On Port B" newline bitfld.long 0x8C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x8C 0.--10. 1. "PRTB_SRC7_HEIGHT,On Port B" line.long 0x90 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" bitfld.long 0x90 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x90 16.--26. 1. "PRTB_SRC8_WIDTH,On Port B" newline bitfld.long 0x90 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x90 0.--10. 1. "PRTB_SRC8_HEIGHT,On Port B" line.long 0x94 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" bitfld.long 0x94 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x94 16.--26. 1. "PRTB_SRC9_WIDTH,On Port B" newline bitfld.long 0x94 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x94 0.--10. 1. "PRTB_SRC9_HEIGHT,On Port B" line.long 0x98 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" bitfld.long 0x98 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x98 16.--26. 1. "PRTB_SRC10_WIDTH,On Port B" newline bitfld.long 0x98 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x98 0.--10. 1. "PRTB_SRC10_HEIGHT,On Port B" line.long 0x9C "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" bitfld.long 0x9C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x9C 16.--26. 1. "PRTB_SRC11_WIDTH,On Port B" newline bitfld.long 0x9C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x9C 0.--10. 1. "PRTB_SRC11_HEIGHT,On Port B" line.long 0xA0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" bitfld.long 0xA0 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA0 16.--26. 1. "PRTB_SRC12_WIDTH,On Port B" newline bitfld.long 0xA0 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA0 0.--10. 1. "PRTB_SRC12_HEIGHT,On Port B" line.long 0xA4 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" bitfld.long 0xA4 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA4 16.--26. 1. "PRTB_SRC13_WIDTH,On Port B" newline bitfld.long 0xA4 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA4 0.--10. 1. "PRTB_SRC13_HEIGHT,On Port B" line.long 0xA8 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" bitfld.long 0xA8 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA8 16.--26. 1. "PRTB_SRC14_WIDTH,On Port B" newline bitfld.long 0xA8 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA8 0.--10. 1. "PRTB_SRC14_HEIGHT,On Port B" line.long 0xAC "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" bitfld.long 0xAC 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xAC 16.--26. 1. "PRTB_SRC15_WIDTH,On Port B" newline bitfld.long 0xAC 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xAC 0.--10. 1. "PRTB_SRC15_HEIGHT,On Port B" line.long 0xB0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB4 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB8 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" bitfld.long 0xB8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xB8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xB8 15. "ANC_BYPASS_N," "0,1" newline rbitfld.long 0xB8 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xB8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xBC "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" rbitfld.long 0xBC 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xBC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline rbitfld.long 0xBC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xBC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xC0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" bitfld.long 0xC0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xC0 15. "ACT_BYPASS_N," "0,1" newline rbitfld.long 0xC0 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xC4 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" rbitfld.long 0xC4 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC4 16.--27. 1. "ACT_USE_NUMLINES,When cropping" newline rbitfld.long 0xC4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xC8 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" bitfld.long 0xC8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xC8 15. "ANC_BYPASS_N," "0,1" newline rbitfld.long 0xC8 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xCC "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" rbitfld.long 0xCC 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xCC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline rbitfld.long 0xCC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xCC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xD0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" bitfld.long 0xD0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xD0 15. "ACT_BYPASS_N," "0,1" newline rbitfld.long 0xD0 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xD0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xD4 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" rbitfld.long 0xD4 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD4 16.--27. 1. "ACT_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline rbitfld.long 0xD4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xD8 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0xD8 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" newline hexmask.long.word 0xD8 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xDC "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0xDC 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" newline hexmask.long.word 0xDC 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xE0 "VIP_XTRA8_PORT_A,Reserved Register for Port A" line.long 0xE4 "VIP_XTRA9_PORT_B,Reserved Register for Port B" width 0x0B tree.end tree "VIP_Slice1_sc" base ad:0x48975D00 group.long 0x00++0x1B line.long 0x00 "VIP_CFG_SC0," hexmask.long.word 0x00 17.--31. 1. "RESERVED," newline bitfld.long 0x00 16. "CFG_FID_SELFGEN,FID self generate enable" "0,1" newline bitfld.long 0x00 15. "CFG_TRIM,Trimming enable" "disable trimming,enable trimming" newline bitfld.long 0x00 14. "CFG_Y_PK_EN,This parameter is used by peaking block" "disable luma peaking,enable luma peaking" newline rbitfld.long 0x00 11.--13. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10. "CFG_INTERLACE_I,This parameter is used by both horizontal and vertical scaling" "the input video format is progressive,the input video format is interlace" newline bitfld.long 0x00 9. "CFG_HP_BYPASS,This parameter is used by horizontal scaling" "The polyphase scaler is always used regardless..,The polyphase scaler is bypassed only when.." newline bitfld.long 0x00 8. "CFG_DCM_4X,This parameter is used by horizontal scaling" "the 4X decimation filter is disabled,the 4X decimation filter is enabled" newline bitfld.long 0x00 7. "CFG_DCM_2X,This parameter is used by horizontal scaling" "the 2X decimation filter is disabled,the 2X decimation filter is enabled" newline bitfld.long 0x00 6. "CFG_AUTO_HS,This parameter is used by horizontal scaling" "the cfg_dcm_2x and cfg_dcm_4x bits will enable..,HW will decide whether up-scaling or.." newline bitfld.long 0x00 5. "CFG_ENABLE_EV,This parameter is used by the edge-detection block" "The output of edge-detection block will be force..,The calculation results of edge-detection block.." newline bitfld.long 0x00 4. "CFG_USE_RAV,This parameter is used by vertical scaling" "Poly-phase filter will be used for the vertical..,Running average filter will be used for the.." newline bitfld.long 0x00 3. "CFG_INVT_FID,This parameter is used by vertical scaling" "Progressive input,Interlaced input Must be set to 1 when.." newline bitfld.long 0x00 2. "CFG_SC_BYPASS,This parameter is a general purpose" "Scaling module will engaged,Scaling module will be bypassed" newline bitfld.long 0x00 1. "CFG_LINEAR,This parameter is used by horizontal scaling" "Anamorphic scaling,Linear scaling" newline bitfld.long 0x00 0. "CFG_INTERLACE_O,This parameter is used by vertical scaling" "The output format of SC is progressive,The output format of SC is interlace" line.long 0x04 "VIP_CFG_SC1," rbitfld.long 0x04 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long 0x04 0.--26. 1. "CFG_ROW_ACC_INC,This parameter is used by vertical scaling" line.long 0x08 "VIP_CFG_SC2," rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x08 0.--27. 1. "CFG_ROW_ACC_OFFSET,This parameter is used by vertical scaling" line.long 0x0C "VIP_CFG_SC3," rbitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x0C 0.--27. 1. "CFG_ROW_ACC_OFFSET_B,This parameter is used by vertical scaling" line.long 0x10 "VIP_CFG_SC4," rbitfld.long 0x10 31. "RESERVED," "0,1" newline bitfld.long 0x10 28.--30. "CFG_NLIN_ACC_INIT_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED," "0,1" newline bitfld.long 0x10 24.--26. "CFG_LIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED," "0,1" newline hexmask.long.word 0x10 12.--22. 1. "CFG_TAR_W,This parameter is a general purpose" newline rbitfld.long 0x10 11. "RESERVED," "0,1" newline hexmask.long.word 0x10 0.--10. 1. "CFG_TAR_H,This parameter is a general purpose" line.long 0x14 "VIP_CFG_SC5," rbitfld.long 0x14 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 24.--26. "CFG_NLIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED," "0,1" newline hexmask.long.word 0x14 12.--22. 1. "CFG_SRC_W,This parameter is a general purpose" newline rbitfld.long 0x14 11. "RESERVED," "0,1" newline hexmask.long.word 0x14 0.--10. 1. "CFG_SRC_H,This parameter is a general purpose" line.long 0x18 "VIP_CFG_SC6," hexmask.long.word 0x18 20.--31. 1. "RESERVED," newline hexmask.long.word 0x18 10.--19. 1. "CFG_ROW_ACC_INIT_RAV_B,This parameter is used by vertical scaling" newline hexmask.long.word 0x18 0.--9. 1. "CFG_ROW_ACC_INIT_RAV,This parameter is used by vertical scaling" group.long 0x20++0x17 line.long 0x00 "VIP_CFG_SC8," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.word 0x00 12.--22. 1. "CFG_NLIN_RIGHT,This parameter is used by horizontal scaling" newline rbitfld.long 0x00 11. "RESERVED," "0,1" newline hexmask.long.word 0x00 0.--10. 1. "CFG_NLIN_LEFT,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC9," line.long 0x08 "VIP_CFG_SC10," line.long 0x0C "VIP_CFG_SC11," line.long 0x10 "VIP_CFG_SC12," hexmask.long.byte 0x10 25.--31. 1. "RESERVED," newline hexmask.long 0x10 0.--24. 1. "CFG_COL_ACC_OFFSET,This parameter is used in horizontal scaling" line.long 0x14 "VIP_CFG_SC13," hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," newline hexmask.long.word 0x14 0.--9. 1. "CFG_SC_FACTOR_RAV,This parameter is used by vertical scaling" group.long 0x48++0x13 line.long 0x00 "VIP_CFG_SC18," hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--9. 1. "CFG_HS_FACTOR,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC19," hexmask.long.byte 0x04 24.--31. 1. "CFG_HPF_COEF3,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 16.--23. 1. "CFG_HPF_COEF2,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 8.--15. 1. "CFG_HPF_COEF1,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 0.--7. 1. "CFG_HPF_COEF0,This parameter is used by the peaking block" line.long 0x08 "VIP_CFG_SC20," rbitfld.long 0x08 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x08 20.--28. 1. "CFG_NL_LIMIT,This parameter is used by the peaking block" newline rbitfld.long 0x08 19. "RESERVED," "0,1" newline bitfld.long 0x08 16.--18. "CFG_HPF_NORM_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 8.--15. 1. "CFG_HPF_COEF5,This parameter is used by the peaking block" newline hexmask.long.byte 0x08 0.--7. 1. "CFG_HPF_COEF4,This parameter is used by the peaking block" line.long 0x0C "VIP_CFG_SC21," hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x0C 16.--23. 1. "CFG_NL_LO_SLOPE,This parameter is used by the peaking block" newline hexmask.long.byte 0x0C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--8. 1. "CFG_NL_LO_THR,This parameter is used by the peaking block" line.long 0x10 "VIP_CFG_SC22," hexmask.long.word 0x10 19.--31. 1. "RESERVED," newline bitfld.long 0x10 16.--18. "CFG_NL_HI_SLOPE_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED," newline hexmask.long.word 0x10 0.--8. 1. "CFG_NL_HI_THR,This parameter is used by the peaking block" group.long 0x60++0x07 line.long 0x00 "VIP_CFG_SC24," rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 16.--26. 1. "CFG_ORG_W,This parameter is used by the trimmer" newline rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--10. 1. "CFG_ORG_H,This parameter is used by the trimmer" line.long 0x04 "VIP_CFG_SC25," rbitfld.long 0x04 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x04 16.--26. 1. "CFG_OFF_W,This parameter is used by the trimmer" newline rbitfld.long 0x04 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x04 0.--10. 1. "CFG_OFF_H,This parameter is used by the trimmer" width 0x0B tree.end tree "VIP_TARG" base ad:0x48980000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "VIP_top_level" base ad:0x48970000 rgroup.long 0x00++0x03 line.long 0x00 "VIP_CLKC_PID,This register follows the format described in PDR3.5" bitfld.long 0x00 30.--31. "SCHEME,The scheme of the register used" "0,1,2,3" newline bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. "FUNC,The function of the module being used" newline bitfld.long 0x00 11.--15. "RTL,RTL Release Version The PDR release number of this IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "MAJOR,ajor Release Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6.--7. "CUSTOM,Custom IP" "0,1,2,3" newline bitfld.long 0x00 0.--5. "MINOR,inor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "VIP_SYSCONFIG," hexmask.long 0x00 6.--31. 1. "RESERVED," newline bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "Force-standby mode,No-standby mode,Same behavior as bit-field value of 0x1,Reserved" newline bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" newline rbitfld.long 0x00 0.--1. "RESERVED," "0,1,2,3" group.long 0x20++0x3F line.long 0x00 "VIP_INTC_INTR0_STATUS_RAW0,INTC INTR0 Interrupt Status Raw/Set Register 0" hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 21. "VIP2_PARSER_INT_RAW,VIP2 Parser Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 20. "VIP1_PARSER_INT_RAW,VIP1 Parser Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline rbitfld.long 0x00 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. "VPDMA_INT0_DESCRIPTOR_RAW,VPDMA INT0 Descriptor Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 15. "VPDMA_INT0_LIST7_NOTIFY_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 14. "VPDMA_INT0_LIST7_COMPLETE_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 13. "VPDMA_INT0_LIST6_NOTIFY_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 12. "VPDMA_INT0_LIST6_COMPLETE_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 11. "VPDMA_INT0_LIST5_NOTIFY_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 10. "VPDMA_INT0_LIST5_COMPLETE_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 9. "VPDMA_INT0_LIST4_NOTIFY_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 8. "VPDMA_INT0_LIST4_COMPLETE_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 7. "VPDMA_INT0_LIST3_NOTIFY_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 6. "VPDMA_INT0_LIST3_COMPLETE_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 5. "VPDMA_INT0_LIST2_NOTIFY_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 4. "VPDMA_INT0_LIST2_COMPLETE_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 3. "VPDMA_INT0_LIST1_NOTIFY_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 2. "VPDMA_INT0_LIST1_COMPLETE_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 1. "VPDMA_INT0_LIST0_NOTIFY_RAW,VPDMA INT0 List0 Notify Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 0. "VPDMA_INT0_LIST0_COMPLETE_RAW,VPDMA INT0 List0 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x04 "VIP_INTC_INTR0_STATUS_RAW1,INTC INTR0 Interrupt Status Raw/Set Register 1" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 25. "VIP2_CHR_DS_2_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 24. "VIP2_CHR_DS_1_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 23. "VIP1_CHR_DS_2_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 22. "VIP1_CHR_DS_1_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline hexmask.long.word 0x04 8.--21. 1. "RESERVED," newline bitfld.long 0x04 7. "VPDMA_INT0_CLIENT_RAW,VPDMA INT0 Client Status Read indicates raw status" "inactive,active Writing 1 will.." newline rbitfld.long 0x04 6. "RESERVED," "0,1" newline bitfld.long 0x04 5. "VPDMA_INT0_CHANNEL_GROUP5_RAW,VPDMA INT0 Channel Group5 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 4. "VPDMA_INT0_CHANNEL_GROUP4_RAW,VPDMA INT0 Channel Group4 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 3. "VPDMA_INT0_CHANNEL_GROUP3_RAW,VPDMA INT0 Channel Group3 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 2. "VPDMA_INT0_CHANNEL_GROUP2_RAW,VPDMA INT0 Channel Group2 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 1. "VPDMA_INT0_CHANNEL_GROUP1_RAW,VPDMA INT0 Channel Group1 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 0. "VPDMA_INT0_CHANNEL_GROUP0_RAW,VPDMA INT0 Channel Group0 Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x08 "VIP_INTC_INTR0_STATUS_ENA0,INTC INTR0 Interrupt Status Enabled/Clear Register 0" hexmask.long.word 0x08 22.--31. 1. "RESERVED," newline bitfld.long 0x08 21. "VIP2_PARSER_INT_ENA,VIP2 Parser Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x08 20. "VIP1_PARSER_INT_ENA,VIP1 Parser Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline rbitfld.long 0x08 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 16. "VPDMA_INT0_DESCRIPTOR_ENA,VPDMA INT0 Descriptor Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 15. "VPDMA_INT0_LIST7_NOTIFY_ENA,VPDMA INT0 List7 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 14. "VPDMA_INT0_LIST7_COMPLETE_ENA,VPDMA INT0 List7 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 13. "VPDMA_INT0_LIST6_NOTIFY_ENA,VPDMA INT0 List6 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 12. "VPDMA_INT0_LIST6_COMPLETE_ENA,VPDMA INT0 List6 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 11. "VPDMA_INT0_LIST5_NOTIFY_ENA,VPDMA INT0 List5 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 10. "VPDMA_INT0_LIST5_COMPLETE_ENA,VPDMA INT0 List5 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 9. "VPDMA_INT0_LIST4_NOTIFY_ENA,VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 8. "VPDMA_INT0_LIST4_COMPLETE_ENA,VPDMA INT0 List4 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 7. "VPDMA_INT0_LIST3_NOTIFY_ENA,VPDMA INT0 List3 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 6. "VPDMA_INT0_LIST3_COMPLETE_ENA,VPDMA INT0 List3 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 5. "VPDMA_INT0_LIST2_NOTIFY_ENA,VPDMA INT0 List2 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 4. "VPDMA_INT0_LIST2_COMPLETE_ENA,VPDMA INT0 List2 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 3. "VPDMA_INT0_LIST1_NOTIFY_ENA,VPDMA INT0 List1 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 2. "VPDMA_INT0_LIST1_COMPLETE_ENA,VPDMA INT0 List1 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 1. "VPDMA_INT0_LIST0_NOTIFY_ENA,VPDMA INT0 List0 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 0. "VPDMA_INT0_LIST0_COMPLETE_ENA,VPDMA INT0 List0 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x0C "VIP_INTC_INTR0_STATUS_ENA1,INTC INTR0 Interrupt Status Enabled/Clear Register 1" rbitfld.long 0x0C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline hexmask.long.word 0x0C 8.--21. 1. "RESERVED," newline bitfld.long 0x0C 7. "VPDMA_INT0_CLIENT_ENA,VPDMA INT0 Client Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline rbitfld.long 0x0C 6. "RESERVED," "0,1" newline bitfld.long 0x0C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA,VPDMA INT0 Channel Group5 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA,VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA,VPDMA INT0 Channel Group1 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA,VPDMA INT0 Channel Group0 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x10 "VIP_INTC_INTR0_ENA_SET0,INTC INTR0 Interrupt Enable/Set Register 0" hexmask.long.word 0x10 22.--31. 1. "RESERVED," newline bitfld.long 0x10 21. "VIP2_PARSER_INT_ENA_SET,VIP2 Parser Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 20. "VIP1_PARSER_INT_ENA_SET,VIP1 Parser Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline rbitfld.long 0x10 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 16. "VPDMA_INT0_DESCRIPTOR_ENA_SET,VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_SET,VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_SET,VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_SET,VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_SET,VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_SET,VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_SET,VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_SET,VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_SET,VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_SET,VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_SET,VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_SET,VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_SET,VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_SET,VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_SET,VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_SET,VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_SET,VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x14 "VIP_INTC_INTR0_ENA_SET1,INTC INTR0 Interrupt Enable/Set Register 1" rbitfld.long 0x14 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x14 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline hexmask.long.word 0x14 8.--21. 1. "RESERVED," newline bitfld.long 0x14 7. "VPDMA_INT0_CLIENT_ENA_SET,VPDMA INT0 Client Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_SET,VPDMA INT0 Channel Group6 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_SET,VPDMA INT0 Channel Group5 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_SET,VPDMA INT0 Channel Group4 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_SET,VPDMA INT0 Channel Group3 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_SET,VPDMA INT0 Channel Group2 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_SET,VPDMA INT0 Channel Group1 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_SET,VPDMA INT0 Channel Group0 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x18 "VIP_INTC_INTR0_ENA_CLR0,INTC INTR0 Interrupt Enable/Clear Register 0" hexmask.long.word 0x18 22.--31. 1. "RESERVED," newline bitfld.long 0x18 21. "VIP2_PARSER_INT_ENA_CLR,VIP2 Parser Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 20. "VIP1_PARSER_INT_ENA_CLR,VIP1 Parser Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline rbitfld.long 0x18 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 16. "VPDMA_INT0_DESCRIPTOR_ENA_CLR,VPDMA INT0 Descriptor Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_CLR,VPDMA INT0 List7 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_CLR,VPDMA INT0 List7 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_CLR,VPDMA INT0 List6 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_CLR,VPDMA INT0 List6 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_CLR,VPDMA INT0 List5 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_CLR,VPDMA INT0 List5 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_CLR,VPDMA INT0 List4 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_CLR,VPDMA INT0 List4 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_CLR,VPDMA INT0 List3 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_CLR,VPDMA INT0 List3 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_CLR,VPDMA INT0 List2 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_CLR,VPDMA INT0 List2 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_CLR,VPDMA INT0 List1 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_CLR,VPDMA INT0 List1 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_CLR,VPDMA INT0 List0 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_CLR,VPDMA INT0 List0 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x1C "VIP_INTC_INTR0_ENA_CLR1,INTC INTR0 Interrupt Enable/Clear Register 1" rbitfld.long 0x1C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x1C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline hexmask.long.word 0x1C 8.--21. 1. "RESERVED," newline bitfld.long 0x1C 7. "VPDMA_INT0_CLIENT_ENA_CLR,VPDMA INT0 Client Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_CLR,VPDMA INT0 Channel Group6 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR,VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR,VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR,VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR,VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR,VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR,VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x20 "VIP_INTC_INTR1_STATUS_RAW0,INTC intr1 Interrupt Status Raw/Set Register 0" hexmask.long.word 0x20 22.--31. 1. "RESERVED," newline bitfld.long 0x20 21. "VIP2_PARSER_INT_RAW,VIP2 Parser Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 20. "VIP1_PARSER_INT_RAW,VIP1 Parser Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline rbitfld.long 0x20 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 16. "VPDMA_INT1_DESCRIPTOR_RAW,VPDMA INT1 Descriptor Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 15. "VPDMA_INT1_LIST7_NOTIFY_RAW,VPDMA INT1 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 14. "VPDMA_INT1_LIST7_COMPLETE_RAW,VPDMA INT1 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 13. "VPDMA_INT1_LIST6_NOTIFY_RAW,VPDMA INT1 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 12. "VPDMA_INT1_LIST6_COMPLETE_RAW,VPDMA INT1 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 11. "VPDMA_INT1_LIST5_NOTIFY_RAW,VPDMA INT1 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 10. "VPDMA_INT1_LIST5_COMPLETE_RAW,VPDMA INT1 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 9. "VPDMA_INT1_LIST4_NOTIFY_RAW,VPDMA INT1 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 8. "VPDMA_INT1_LIST4_COMPLETE_RAW,VPDMA INT1 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 7. "VPDMA_INT1_LIST3_NOTIFY_RAW,VPDMA INT1 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 6. "VPDMA_INT1_LIST3_COMPLETE_RAW,VPDMA INT1 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 5. "VPDMA_INT1_LIST2_NOTIFY_RAW,VPDMA INT1 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 4. "VPDMA_INT1_LIST2_COMPLETE_RAW,VPDMA INT1 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 3. "VPDMA_INT1_LIST1_NOTIFY_RAW,VPDMA INT1 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 2. "VPDMA_INT1_LIST1_COMPLETE_RAW,VPDMA INT1 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 1. "VPDMA_INT1_LIST0_NOTIFY_RAW,VPDMA INT1 List0 Notify Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 0. "VPDMA_INT1_LIST0_COMPLETE_RAW,VPDMA INT1 List0 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x24 "VIP_INTC_INTR1_STATUS_RAW1,INTC intr1 Interrupt Status Raw/Set Register 1" rbitfld.long 0x24 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x24 25. "VIP2_CHR_DS_2_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 24. "VIP2_CHR_DS_1_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 23. "VIP1_CHR_DS_2_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 22. "VIP1_CHR_DS_1_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline hexmask.long.word 0x24 8.--21. 1. "RESERVED," newline bitfld.long 0x24 7. "VPDMA_INT1_CLIENT_RAW,VPDMA INT1 Client Status Read indicates raw status" "inactive,active Writing 1 will.." newline rbitfld.long 0x24 6. "RESERVED," "0,1" newline bitfld.long 0x24 5. "VPDMA_INT1_CHANNEL_GROUP5_RAW,VPDMA INT1 Channel Group5 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 4. "VPDMA_INT1_CHANNEL_GROUP4_RAW,VPDMA INT1 Channel Group4 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 3. "VPDMA_INT1_CHANNEL_GROUP3_RAW,VPDMA INT1 Channel Group3 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 2. "VPDMA_INT1_CHANNEL_GROUP2_RAW,VPDMA INT1 Channel Group2 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 1. "VPDMA_INT1_CHANNEL_GROUP1_RAW,VPDMA INT1 Channel Group1 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 0. "VPDMA_INT1_CHANNEL_GROUP0_RAW,VPDMA INT1 Channel Group0 Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x28 "VIP_INTC_INTR1_STATUS_ENA0,INTC intr1 Interrupt Status Enabled/Clear Register 0" hexmask.long.word 0x28 22.--31. 1. "RESERVED," newline bitfld.long 0x28 21. "VIP2_PARSER_INT_ENA,VIP2 Parser Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x28 20. "VIP1_PARSER_INT_ENA,VIP1 Parser Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline rbitfld.long 0x28 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 16. "VPDMA_INT1_DESCRIPTOR_ENA,VPDMA INT1 Descriptor Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 15. "VPDMA_INT1_LIST7_NOTIFY_ENA,VPDMA INT1 List7 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 14. "VPDMA_INT1_LIST7_COMPLETE_ENA,VPDMA INT1 List7 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 13. "VPDMA_INT1_LIST6_NOTIFY_ENA,VPDMA INT1 List6 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 12. "VPDMA_INT1_LIST6_COMPLETE_ENA,VPDMA INT1 List6 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 11. "VPDMA_INT1_LIST5_NOTIFY_ENA,VPDMA INT1 List5 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 10. "VPDMA_INT1_LIST5_COMPLETE_ENA,VPDMA INT1 List5 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 9. "VPDMA_INT1_LIST4_NOTIFY_ENA,VPDMA INT1 List4 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 8. "VPDMA_INT1_LIST4_COMPLETE_ENA,VPDMA INT1 List4 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 7. "VPDMA_INT1_LIST3_NOTIFY_ENA,VPDMA INT1 List3 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 6. "VPDMA_INT1_LIST3_COMPLETE_ENA,VPDMA INT1 List3 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 5. "VPDMA_INT1_LIST2_NOTIFY_ENA,VPDMA INT1 List2 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 4. "VPDMA_INT1_LIST2_COMPLETE_ENA,VPDMA INT1 List2 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 3. "VPDMA_INT1_LIST1_NOTIFY_ENA,VPDMA INT1 List1 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 2. "VPDMA_INT1_LIST1_COMPLETE_ENA,VPDMA INT1 List1 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 1. "VPDMA_INT1_LIST0_NOTIFY_ENA,VPDMA INT1 List0 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 0. "VPDMA_INT1_LIST0_COMPLETE_ENA,VPDMA INT1 List0 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x2C "VIP_INTC_INTR1_STATUS_ENA1,INTC intr1 Interrupt Status Enabled/Clear Register 1" rbitfld.long 0x2C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x2C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline hexmask.long.word 0x2C 8.--21. 1. "RESERVED," newline bitfld.long 0x2C 7. "VPDMA_INT1_CLIENT_ENA,VPDMA INT1 Client Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline rbitfld.long 0x2C 6. "RESERVED," "0,1" newline bitfld.long 0x2C 5. "VPDMA_INT1_CHANNEL_GROUP5_ENA,VPDMA INT1 Channel Group5 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 4. "VPDMA_INT1_CHANNEL_GROUP4_ENA,VPDMA INT1 Channel Group4 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 3. "VPDMA_INT1_CHANNEL_GROUP3_ENA,VPDMA INT1 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 2. "VPDMA_INT1_CHANNEL_GROUP2_ENA,VPDMA INT1 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 1. "VPDMA_INT1_CHANNEL_GROUP1_ENA,VPDMA INT1 Channel Group1 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 0. "VPDMA_INT1_CHANNEL_GROUP0_ENA,VPDMA INT1 Channel Group0 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x30 "VIP_INTC_INTR1_ENA_SET0,INTC intr1 Interrupt Enable/Set Register 0" hexmask.long.word 0x30 22.--31. 1. "RESERVED," newline bitfld.long 0x30 21. "VIP2_PARSER_INT_ENA_SET,VIP2 Parser Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 20. "VIP1_PARSER_INT_ENA_SET,VIP1 Parser Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline rbitfld.long 0x30 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 16. "VPDMA_INT1_DESCRIPTOR_ENA_SET,VPDMA INT1 Descriptor Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 15. "VPDMA_INT1_LIST7_NOTIFY_ENA_SET,VPDMA INT1 List7 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 14. "VPDMA_INT1_LIST7_COMPLETE_ENA_SET,VPDMA INT1 List7 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 13. "VPDMA_INT1_LIST6_NOTIFY_ENA_SET,VPDMA INT1 List6 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 12. "VPDMA_INT1_LIST6_COMPLETE_ENA_SET,VPDMA INT1 List6 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 11. "VPDMA_INT1_LIST5_NOTIFY_ENA_SET,VPDMA INT1 List5 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 10. "VPDMA_INT1_LIST5_COMPLETE_ENA_SET,VPDMA INT1 List5 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 9. "VPDMA_INT1_LIST4_NOTIFY_ENA_SET,VPDMA INT1 List4 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 8. "VPDMA_INT1_LIST4_COMPLETE_ENA_SET,VPDMA INT1 List4 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 7. "VPDMA_INT1_LIST3_NOTIFY_ENA_SET,VPDMA INT1 List3 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 6. "VPDMA_INT1_LIST3_COMPLETE_ENA_SET,VPDMA INT1 List3 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 5. "VPDMA_INT1_LIST2_NOTIFY_ENA_SET,VPDMA INT1 List2 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 4. "VPDMA_INT1_LIST2_COMPLETE_ENA_SET,VPDMA INT1 List2 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 3. "VPDMA_INT1_LIST1_NOTIFY_ENA_SET,VPDMA INT1 List1 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 2. "VPDMA_INT1_LIST1_COMPLETE_ENA_SET,VPDMA INT1 List1 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 1. "VPDMA_INT1_LIST0_NOTIFY_ENA_SET,VPDMA INT1 List0 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 0. "VPDMA_INT1_LIST0_COMPLETE_ENA_SET,VPDMA INT1 List0 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x34 "VIP_INTC_INTR1_ENA_SET1,INTC intr1 Interrupt Enable/Set Register 1" rbitfld.long 0x34 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x34 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline hexmask.long.word 0x34 8.--21. 1. "RESERVED," newline bitfld.long 0x34 7. "VPDMA_INT1_CLIENT_ENA_SET,VPDMA INT1 Client Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 6. "VPDMA_INT1_CHANNEL_GROUP6_ENA_SET,VPDMA INT1 Channel Group6 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 5. "VPDMA_INT1_CHANNEL_GROUP5_ENA_SET,VPDMA INT1 Channel Group5 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 4. "VPDMA_INT1_CHANNEL_GROUP4_ENA_SET,VPDMA INT1 Channel Group4 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 3. "VPDMA_INT1_CHANNEL_GROUP3_ENA_SET,VPDMA INT1 Channel Group3 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 2. "VPDMA_INT1_CHANNEL_GROUP2_ENA_SET,VPDMA INT1 Channel Group2 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 1. "VPDMA_INT1_CHANNEL_GROUP1_ENA_SET,VPDMA INT1 Channel Group1 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 0. "VPDMA_INT1_CHANNEL_GROUP0_ENA_SET,VPDMA INT1 Channel Group0 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x38 "VIP_INTC_INTR1_ENA_CLR0,INTC intr1 Interrupt Enable/Clear Register 0" hexmask.long.word 0x38 22.--31. 1. "RESERVED," newline bitfld.long 0x38 21. "VIP2_PARSER_INT_ENA_CLR,VIP2 Parser Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 20. "VIP1_PARSER_INT_ENA_CLR,VIP1 Parser Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline rbitfld.long 0x38 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 16. "VPDMA_INT1_DESCRIPTOR_ENA_CLR,VPDMA INT1 Descriptor Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 15. "VPDMA_INT1_LIST7_NOTIFY_ENA_CLR,VPDMA INT1 List7 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 14. "VPDMA_INT1_LIST7_COMPLETE_ENA_CLR,VPDMA INT1 List7 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 13. "VPDMA_INT1_LIST6_NOTIFY_ENA_CLR,VPDMA INT1 List6 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 12. "VPDMA_INT1_LIST6_COMPLETE_ENA_CLR,VPDMA INT1 List6 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 11. "VPDMA_INT1_LIST5_NOTIFY_ENA_CLR,VPDMA INT1 List5 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 10. "VPDMA_INT1_LIST5_COMPLETE_ENA_CLR,VPDMA INT1 List5 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 9. "VPDMA_INT1_LIST4_NOTIFY_ENA_CLR,VPDMA INT1 List4 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 8. "VPDMA_INT1_LIST4_COMPLETE_ENA_CLR,VPDMA INT1 List4 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 7. "VPDMA_INT1_LIST3_NOTIFY_ENA_CLR,VPDMA INT1 List3 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 6. "VPDMA_INT1_LIST3_COMPLETE_ENA_CLR,VPDMA INT1 List3 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 5. "VPDMA_INT1_LIST2_NOTIFY_ENA_CLR,VPDMA INT1 List2 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 4. "VPDMA_INT1_LIST2_COMPLETE_ENA_CLR,VPDMA INT1 List2 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 3. "VPDMA_INT1_LIST1_NOTIFY_ENA_CLR,VPDMA INT1 List1 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 2. "VPDMA_INT1_LIST1_COMPLETE_ENA_CLR,VPDMA INT1 List1 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 1. "VPDMA_INT1_LIST0_NOTIFY_ENA_CLR,VPDMA INT1 List0 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 0. "VPDMA_INT1_LIST0_COMPLETE_ENA_CLR,VPDMA INT1 List0 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x3C "VIP_INTC_INTR1_ENA_CLR1,INTC intr1 Interrupt Enable/Clear Register 1" rbitfld.long 0x3C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x3C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline hexmask.long.word 0x3C 8.--21. 1. "RESERVED," newline bitfld.long 0x3C 7. "VPDMA_INT1_CLIENT_ENA_CLR,VPDMA INT1 Client Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 6. "VPDMA_INT1_CHANNEL_GROUP6_ENA_CLR,VPDMA INT1 Channel Group6 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 5. "VPDMA_INT1_CHANNEL_GROUP5_ENA_CLR,VPDMA INT1 Channel Group5 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 4. "VPDMA_INT1_CHANNEL_GROUP4_ENA_CLR,VPDMA INT1 Channel Group4 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 3. "VPDMA_INT1_CHANNEL_GROUP3_ENA_CLR,VPDMA INT1 Channel Group3 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 2. "VPDMA_INT1_CHANNEL_GROUP2_ENA_CLR,VPDMA INT1 Channel Group2 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 1. "VPDMA_INT1_CHANNEL_GROUP1_ENA_CLR,VPDMA INT1 Channel Group1 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 0. "VPDMA_INT1_CHANNEL_GROUP0_ENA_CLR,VPDMA INT1 Channel Group0 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." group.long 0xA0++0x03 line.long 0x00 "VIP_INTC_EOI,INTC EOI Register" group.long 0x100++0x13 line.long 0x00 "VIP_CLKC_CLKEN,CLKC Module Clock Enable Register" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 17. "VIP2_DP_EN,VIP Slice1 Data Path Clock Enable " "Clock Disabled,Clock Enabled" newline bitfld.long 0x00 16. "VIP1_DP_EN,VIP Slice0 Data Path Clock Enable " "Clock Disabled,Clock Enabled" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "VPDMA_EN,VPDMA Clock Enable " "Clock Disabled,Clock Enabled" line.long 0x04 "VIP_CLKC_RST,CLKC Module Reset Register" bitfld.long 0x04 31. "MAIN_RST,Reset for all modules in VIP Main Data Path" "0,1" newline rbitfld.long 0x04 29.--30. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x04 28. "S1_CHR_DS_1_RST,VIP Slice1 CHRDS1 reset" "0,1" newline bitfld.long 0x04 27. "S0_CHR_DS_1_RST,VIP Slice0 CHRDS1 reset" "0,1" newline bitfld.long 0x04 26. "S1_CHR_DS_0_RST,VIP Slice1 CHRDS0 reset" "0,1" newline bitfld.long 0x04 25. "S0_CHR_DS_0_RST,VIP Slice0 CHRDS0 reset" "0,1" newline bitfld.long 0x04 24. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 23. "S1_SC_RST,VIP Slice1 SC reset" "0,1" newline bitfld.long 0x04 22. "S0_SC_RST,VIP Slice0 SC reset" "0,1" newline bitfld.long 0x04 21. "S1_CSC_RST,VIP Slice1 CSC reset" "0,1" newline bitfld.long 0x04 20. "S0_CSC_RST,VIP Slice0 CSC reset" "0,1" newline bitfld.long 0x04 19. "S1_PARSER_RST,VIP Slice1 parser reset" "0,1" newline bitfld.long 0x04 18. "S0_PARSER_RST,VIP Slice0 parser reset" "0,1" newline bitfld.long 0x04 17. "VIP2_DP_RST,VIP Slice1 Data Path Reset" "0,1" newline bitfld.long 0x04 16. "VIP1_DP_RST,VIP Slice0 Data Path Reset" "0,1" newline hexmask.long.word 0x04 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0. "VPDMA_RST,VPDMA Reset" "0,1" line.long 0x08 "VIP_CLKC_DPS,CLKC Main Data Path Select Register" bitfld.long 0x08 31. "MAIN_RST,Reset for all modules in DSS Main Data Path" "0,1" newline hexmask.long.word 0x08 18.--30. 1. "RESERVED," newline bitfld.long 0x08 17. "VIP2_DP_RST,Video Input Port 2 Data Path Reset" "0,1" newline bitfld.long 0x08 16. "VIP1_DP_RST,Video Input Port 1 Data Path Reset" "0,1" newline hexmask.long.word 0x08 1.--15. 1. "RESERVED," newline bitfld.long 0x08 0. "VPDMA_RST,VPDMA Reset" "0,1" line.long 0x0C "VIP_CLKC_VIP0DPS,CLKC Video Input Port 1 Data Path Select Register" bitfld.long 0x0C 28.--31. "VIP1_DATAPATH_SELECT,VIP1 Datapath Register Field Enable" "All fields written,Only vip1_csc_src_select written,Only vip1_sc_src_select written,Only vip1_rgb_src_select written,Only vip1_rgb_out_lo_select written,Only vip1_rgb_out_hi_select written,Only vip1_chr_ds_1_src_select written,Only vip1_chr_ds_2_src_select written,Only vip1_multi_channel_select written,Only vip1_chr_ds_1_bypass written,Only vip1_chr_ds_2_bypass written,Reserved,Reserved,Reserved,Reserved,Reserved" newline bitfld.long 0x0C 27. "VIP1_TESTPORT_A_SELECT," "0,1" newline bitfld.long 0x0C 26. "VIP1_TESTPORT_B_SELECT," "0,1" newline hexmask.long.byte 0x0C 18.--25. 1. "RESERVED," newline bitfld.long 0x0C 17. "VIP1_CHR_DS_2_BYPASS,Video Input Port 1 Chroma Downsampler 2 Bypass" "VIP Chroma Downsampler 1 selected,VIP Chroma Downsampler 1 Bypassed Chroma.." newline bitfld.long 0x0C 16. "VIP1_CHR_DS_1_BYPASS,Video Input Port 1 Chroma Downsampler 1 Bypass" "VIP Chroma Downsampler 1 selected,VIP Chroma Downsampler 1 Bypassed Chroma.." newline bitfld.long 0x0C 15. "VIP1_MULTI_CHANNEL_SELECT,Video Input Port 1 Multi Channel Select" "VIP_PARSER A and B channels operate in single..,VIP_PARSER A and B channels directly drive VPDMA.." newline bitfld.long 0x0C 12.--14. "VIP1_CHR_DS_2_SRC_SELECT,Video Input Port 1 Chroma Downsampler 2 Source Select" "Path Disabled (no input to CHR_DS),Source from Scaler (SC_M),Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved" newline bitfld.long 0x0C 9.--11. "VIP1_CHR_DS_1_SRC_SELECT,Video Input Port 1 Chroma Downsampler 1 Source Select" "Path Disabled (no input to CHR_DS),Source from Scaler (SC_M),Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved" newline bitfld.long 0x0C 8. "VIP1_RGB_OUT_HI_SELECT,Video Input Port 1 HI RGB Output Select" "Output Type is 420/422,Output Type is RGB" newline bitfld.long 0x0C 7. "VIP1_RGB_OUT_LO_SELECT,Video Input Port 1 LO RGB Output Select" "Output Type is 420/422,Output Type is RGB" newline bitfld.long 0x0C 6. "VIP1_RGB_SRC_SELECT,Video Input Port 1 RGB Output Path Select" "Source from Compositor RGB input,Source from CSC" newline bitfld.long 0x0C 3.--5. "VIP1_SC_SRC_SELECT,Video Input Port 1 SC_M Source Select" "Path Disabled,Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved,Reserved" newline bitfld.long 0x0C 0.--2. "VIP1_CSC_SRC_SELECT,Video Input Port 1 CSC Source Select" "Path Disabled,Source from VIP_PARSER A (422) port,Source from VIP_PARSER B port,Source from Transcode (422),Source from VIP_PARSER A (RGB) port,Source from Compositor (RGB),Reserved,Reserved" line.long 0x10 "VIP_CLKC_VIP1DPS,CLKC Video Input Port 2 Data Path Select Register" bitfld.long 0x10 28.--31. "VIP2_DATAPATH_SELECT,VIP2 Datapath Register Field Enable" "All fields written,Only vip2_csc_src_select written,Only vip2_sc_src_select written,Only vip2_rgb_src_select written,Only vip2_rgb_out_lo_select written,Only vip2_rgb_out_hi_select written,Only vip2_chr_ds_1_src_select written,Only vip2_chr_ds_2_src_select written,Only vip2_multi_channel_select written,Only vip2_chr_ds_1_bypass written,Only vip2_chr_ds_2_bypass written,Reserved,Reserved,Reserved,Reserved,Reserved" newline bitfld.long 0x10 27. "VIP2_TESTPORT_A_SELECT," "0,1" newline bitfld.long 0x10 26. "VIP2_TESTPORT_B_SELECT," "0,1" newline hexmask.long.byte 0x10 18.--25. 1. "RESERVED," newline bitfld.long 0x10 17. "VIP2_CHR_DS_2_BYPASS,Video Input Port 2 Chroma Downsampler 2 Bypass" "VIP Chroma Downsampler 1 selected,VIP Chroma Downsampler 1 Bypassed Chroma.." newline bitfld.long 0x10 16. "VIP2_CHR_DS_1_BYPASS,Video Input Port 2 Chroma Downsampler 1 Bypass" "VIP Chroma Downsampler 1 selected,VIP Chroma Downsampler 1 Bypassed Chroma.." newline bitfld.long 0x10 15. "VIP2_MULTI_CHANNEL_SELECT,Video Input Port 2 Multi Channel Select" "VIP_PARSER A and B channels operate in single..,VIP_PARSER A and B channels directly drive VPDMA.." newline bitfld.long 0x10 12.--14. "VIP2_CHR_DS_2_SRC_SELECT,Video Input Port 2 Chroma Downsampler 2 Source Select" "Path Disabled (no input to CHR_DS),Source from Scaler (SC_M),Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved" newline bitfld.long 0x10 9.--11. "VIP2_CHR_DS_1_SRC_SELECT,Video Input Port 2 Chroma Downsampler 1 Source Select" "Path Disabled (no input to CHR_DS),Source from Scaler (SC_M),Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved" newline bitfld.long 0x10 8. "VIP2_RGB_OUT_HI_SELECT,Video Input Port 2 HI RGB Output Select" "Output Type is 420/422,Output Type is RGB" newline bitfld.long 0x10 7. "VIP2_RGB_OUT_LO_SELECT,Video Input Port 2 LO RGB Output Select" "Output Type is 420/422,Output Type is RGB" newline bitfld.long 0x10 6. "VIP2_RGB_SRC_SELECT,Video Input Port 2 RGB Output Path Select" "Source from Compositor RGB input,Source from CSC" newline bitfld.long 0x10 3.--5. "VIP2_SC_SRC_SELECT,Video Input Port 2 SC_M Source Select" "Path Disabled,Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved,Reserved" newline bitfld.long 0x10 0.--2. "VIP2_CSC_SRC_SELECT,Video Input Port 2 CSC Source Select" "Path Disabled,Source from VIP_PARSER A (422) port,Source from VIP_PARSER B port,Source from Transcode (422),Source from VIP_PARSER A (RGB) port,Source from Compositor (RGB),Reserved,Reserved" width 0x0B tree.end tree "VIP_VPDMA" base ad:0x4897D000 rgroup.long 0x00++0x0F line.long 0x00 "VIP_PID,PID VIP VPDMA register" line.long 0x04 "VIP_LIST_ADDR,The location of a new list to begin processing" line.long 0x08 "VIP_LIST_ATTR,The attributes of a new list" rbitfld.long 0x08 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 24.--26. "LIST_NUM,The list number that should be assigned to the list located atVIP_LIST_ADDR" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x08 20. "STOP,This bit is written with the LIST_NUMBER field to stop a self-modifying list" "0,1" newline rbitfld.long 0x08 19. "RDY,This bit is low when a new list cannot be written to theVIP_LIST_ADDR register" "0,1" bitfld.long 0x08 16.--18. "LIST_TYPE,The type of list that has been generated.\\n0: Normal List\\n1: Self-Modifying List\\n2: List Doorbell\\nOthers Reserved for future use" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x08 0.--15. 1. "LIST_SIZE,Number of 128 bit word in the new list of descriptors" line.long 0x0C "VIP_LIST_STAT_SYNC,The register is used for processor to List Manager syncronization and status registers for the list" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," rbitfld.long 0x0C 23. "LIST7_BUSY,The list 7 is currently running" "0,1" newline rbitfld.long 0x0C 22. "LIST6_BUSY,The list 6 is currently running" "0,1" rbitfld.long 0x0C 21. "LIST5_BUSY,The list 5 is currently running" "0,1" newline rbitfld.long 0x0C 20. "LIST4_BUSY,The list 4 is currently running" "0,1" rbitfld.long 0x0C 19. "LIST3_BUSY,The list 3 is currently running" "0,1" newline rbitfld.long 0x0C 18. "LIST2_BUSY,The list 2 is currently running" "0,1" rbitfld.long 0x0C 17. "LIST1_BUSY,The list 1 is currently running" "0,1" newline rbitfld.long 0x0C 16. "LIST0_BUSY,The list 0 is currently running" "0,1" hexmask.long.byte 0x0C 8.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 7. "SYNC_LISTS7,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 7 waiting on it" "0,1" bitfld.long 0x0C 6. "SYNC_LISTS6,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 6 waiting on it" "0,1" newline bitfld.long 0x0C 5. "SYNC_LISTS5,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 5 waiting on it" "0,1" bitfld.long 0x0C 4. "SYNC_LISTS4,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 4 waiting on it" "0,1" newline bitfld.long 0x0C 3. "SYNC_LISTS3,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 3 waiting on it" "0,1" bitfld.long 0x0C 2. "SYNC_LISTS2,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 2 waiting on it" "0,1" newline bitfld.long 0x0C 1. "SYNC_LISTS1,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 1 waiting on it" "0,1" bitfld.long 0x0C 0. "SYNC_LISTS0,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 0 waiting on it" "0,1" group.long 0x18++0x07 line.long 0x00 "VIP_BG_RGB,The registers used to set the background color for RGB" hexmask.long.byte 0x00 24.--31. 1. "RED,The red value to give on an RGB data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x00 16.--23. 1. "GREEN,The green value to give on an RGB data port for a blank pixel when using virtual video buffering" newline hexmask.long.byte 0x00 8.--15. 1. "BLUE,The blue value to give on an RGB data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x00 0.--7. 1. "BLEND,The blend value to give on an RGB data port for a blank pixel when using virtual video buffering" line.long 0x04 "VIP_BG_YUV,The registers used to set the background color for YUV" hexmask.long.byte 0x04 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x04 16.--23. 1. "Y,The Y value to give on a YUV data port for a blank pixel when using virtual video buffering" newline hexmask.long.byte 0x04 8.--15. 1. "CR,The Cr value to give on a YUV data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x04 0.--7. 1. "CB,The Cb value to give on a YUV data port for a blank pixel when using virtual video buffering" group.long 0x30++0x3F line.long 0x00 "VIP_VPDMA_SETUP,Configures global parameters that are shared by all clients" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "SEC_BASE_CH,Use Secondary Channels for Mosaic mode" "0,1" line.long 0x04 "VIP_MAX_SIZE1,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 1 in write descriptor" hexmask.long.word 0x04 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 1 in a write descriptor" hexmask.long.word 0x04 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 1 in a write descriptor" line.long 0x08 "VIP_MAX_SIZE2,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 2 in write descriptor" hexmask.long.word 0x08 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 2 in a write descriptor" hexmask.long.word 0x08 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 2 in a write descriptor" line.long 0x0C "VIP_MAX_SIZE3,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 3 in write descriptor" hexmask.long.word 0x0C 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 3 in a write descriptor" hexmask.long.word 0x0C 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 3 in a write descriptor" line.long 0x10 "VIP_INT0_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x10 31. "INT_STAT_GRPX3,The last read DMA transaction has occurred for channel grpx3 and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x10 30. "INT_STAT_GRPX2,The last read DMA transaction has occurred for channel grpx2 and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x10 29. "INT_STAT_GRPX1,The last read DMA transaction has occurred for channel grpx1 and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x10 28. "INT_STAT_SCALER_OUT,The last write DMA transaction has completed for channel scaler_out" "0,1" newline hexmask.long.byte 0x10 20.--27. 1. "RESERVED,Reserved" bitfld.long 0x10 19. "INT_STAT_SCALER_CHROMA,The last write DMA transaction has completed for channel scaler_chroma" "0,1" newline bitfld.long 0x10 18. "INT_STAT_SCALER_LUMA,The last write DMA transaction has completed for channel scaler_luma" "0,1" bitfld.long 0x10 17. "INT_STAT_HQ_SCALER,The last write DMA transaction has completed for channel hq_scaler" "0,1" newline rbitfld.long 0x10 16. "RESERVED,Reserved" "0,1" bitfld.long 0x10 15. "INT_STAT_HQ_MV_OUT,The last write DMA transaction has completed for channel hq_mv_out" "0,1" newline rbitfld.long 0x10 13.--14. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x10 12. "INT_STAT_HQ_MV,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer" "0,1" newline rbitfld.long 0x10 6.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 5. "INT_STAT_HQ_VID3_CHROMA,The last write DMA transaction has completed for channel hq_vid3_chroma" "0,1" newline bitfld.long 0x10 4. "INT_STAT_HQ_VID3_LUMA,The last write DMA transaction has completed for channel hq_vid3_luma" "0,1" bitfld.long 0x10 3. "INT_STAT_HQ_VID2_CHROMA,The last write DMA transaction has completed for channel hq_vid2_chroma" "0,1" newline bitfld.long 0x10 2. "INT_STAT_HQ_VID2_LUMA,The last write DMA transaction has completed for channel hq_vid2_luma" "0,1" bitfld.long 0x10 1. "INT_STAT_HQ_VID1_CHROMA,The last write DMA transaction has completed for channel hq_vid1_chroma" "0,1" newline bitfld.long 0x10 0. "INT_STAT_HQ_VID1_LUMA,The last write DMA transaction has completed for channel hq_vid1_luma" "0,1" line.long 0x14 "VIP_INT0_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x14 31. "INT_MASK_GRPX3,The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 30. "INT_MASK_GRPX2,The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 29. "INT_MASK_GRPX1,The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 28. "INT_MASK_SCALER_OUT,The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int0" "0,1" newline hexmask.long.byte 0x14 20.--27. 1. "RESERVED,Reserved" bitfld.long 0x14 19. "INT_MASK_SCALER_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 18. "INT_MASK_SCALER_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 17. "INT_MASK_HQ_SCALER,The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int0" "0,1" newline rbitfld.long 0x14 16. "RESERVED,Reserved" "0,1" bitfld.long 0x14 15. "INT_MASK_HQ_MV_OUT,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int0" "0,1" newline rbitfld.long 0x14 13.--14. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x14 12. "INT_MASK_HQ_MV,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int0" "0,1" newline rbitfld.long 0x14 6.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 5. "INT_MASK_HQ_VID3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 4. "INT_MASK_HQ_VID3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 3. "INT_MASK_HQ_VID2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 2. "INT_MASK_HQ_VID2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 1. "INT_MASK_HQ_VID1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 0. "INT_MASK_HQ_VID1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x18 "VIP_INT0_CHANNEL1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x18 31. "INT_STAT_VIP1_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip1_mult_portb_src9" "0,1" bitfld.long 0x18 30. "INT_STAT_VIP1_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip1_mult_portb_src8" "0,1" newline bitfld.long 0x18 29. "INT_STAT_VIP1_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip1_mult_portb_src7" "0,1" bitfld.long 0x18 28. "INT_STAT_VIP1_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip1_mult_portb_src6" "0,1" newline bitfld.long 0x18 27. "INT_STAT_VIP1_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip1_mult_portb_src5" "0,1" bitfld.long 0x18 26. "INT_STAT_VIP1_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip1_mult_portb_src4" "0,1" newline bitfld.long 0x18 25. "INT_STAT_VIP1_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip1_mult_portb_src3" "0,1" bitfld.long 0x18 24. "INT_STAT_VIP1_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip1_mult_portb_src2" "0,1" newline bitfld.long 0x18 23. "INT_STAT_VIP1_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip1_mult_portb_src1" "0,1" bitfld.long 0x18 22. "INT_STAT_VIP1_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip1_mult_portb_src0" "0,1" newline bitfld.long 0x18 21. "INT_STAT_VIP1_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip1_mult_porta_src15" "0,1" bitfld.long 0x18 20. "INT_STAT_VIP1_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip1_mult_porta_src14" "0,1" newline bitfld.long 0x18 19. "INT_STAT_VIP1_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip1_mult_porta_src13" "0,1" bitfld.long 0x18 18. "INT_STAT_VIP1_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip1_mult_porta_src12" "0,1" newline bitfld.long 0x18 17. "INT_STAT_VIP1_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip1_mult_porta_src11" "0,1" bitfld.long 0x18 16. "INT_STAT_VIP1_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip1_mult_porta_src10" "0,1" newline bitfld.long 0x18 15. "INT_STAT_VIP1_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip1_mult_porta_src9" "0,1" bitfld.long 0x18 14. "INT_STAT_VIP1_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip1_mult_porta_src8" "0,1" newline bitfld.long 0x18 13. "INT_STAT_VIP1_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip1_mult_porta_src7" "0,1" bitfld.long 0x18 12. "INT_STAT_VIP1_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip1_mult_porta_src6" "0,1" newline bitfld.long 0x18 11. "INT_STAT_VIP1_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip1_mult_porta_src5" "0,1" bitfld.long 0x18 10. "INT_STAT_VIP1_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip1_mult_porta_src4" "0,1" newline bitfld.long 0x18 9. "INT_STAT_VIP1_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip1_mult_porta_src3" "0,1" bitfld.long 0x18 8. "INT_STAT_VIP1_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip1_mult_porta_src2" "0,1" newline bitfld.long 0x18 7. "INT_STAT_VIP1_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip1_mult_porta_src1" "0,1" bitfld.long 0x18 6. "INT_STAT_VIP1_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip1_mult_porta_src0" "0,1" newline rbitfld.long 0x18 0.--5. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "VIP_INT0_CHANNEL1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x1C 31. "INT_MASK_VIP1_MULT_PORTB_SRC9,The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 30. "INT_MASK_VIP1_MULT_PORTB_SRC8,The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 29. "INT_MASK_VIP1_MULT_PORTB_SRC7,The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 28. "INT_MASK_VIP1_MULT_PORTB_SRC6,The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 27. "INT_MASK_VIP1_MULT_PORTB_SRC5,The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 26. "INT_MASK_VIP1_MULT_PORTB_SRC4,The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 25. "INT_MASK_VIP1_MULT_PORTB_SRC3,The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 24. "INT_MASK_VIP1_MULT_PORTB_SRC2,The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 23. "INT_MASK_VIP1_MULT_PORTB_SRC1,The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 22. "INT_MASK_VIP1_MULT_PORTB_SRC0,The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 21. "INT_MASK_VIP1_MULT_PORTA_SRC15,The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 20. "INT_MASK_VIP1_MULT_PORTA_SRC14,The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 19. "INT_MASK_VIP1_MULT_PORTA_SRC13,The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 18. "INT_MASK_VIP1_MULT_PORTA_SRC12,The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 17. "INT_MASK_VIP1_MULT_PORTA_SRC11,The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 16. "INT_MASK_VIP1_MULT_PORTA_SRC10,The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 15. "INT_MASK_VIP1_MULT_PORTA_SRC9,The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 14. "INT_MASK_VIP1_MULT_PORTA_SRC8,The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 13. "INT_MASK_VIP1_MULT_PORTA_SRC7,The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 12. "INT_MASK_VIP1_MULT_PORTA_SRC6,The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 11. "INT_MASK_VIP1_MULT_PORTA_SRC5,The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 10. "INT_MASK_VIP1_MULT_PORTA_SRC4,The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 9. "INT_MASK_VIP1_MULT_PORTA_SRC3,The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 8. "INT_MASK_VIP1_MULT_PORTA_SRC2,The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 7. "INT_MASK_VIP1_MULT_PORTA_SRC1,The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 6. "INT_MASK_VIP1_MULT_PORTA_SRC0,The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline rbitfld.long 0x1C 0.--5. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "VIP_INT0_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x20 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x20 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" newline bitfld.long 0x20 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" bitfld.long 0x20 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" newline bitfld.long 0x20 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x20 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x20 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x20 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" newline bitfld.long 0x20 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" bitfld.long 0x20 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" newline bitfld.long 0x20 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x20 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x20 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x20 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" newline bitfld.long 0x20 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" bitfld.long 0x20 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" newline bitfld.long 0x20 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x20 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x20 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x20 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" newline bitfld.long 0x20 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" bitfld.long 0x20 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" newline bitfld.long 0x20 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x20 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x20 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x20 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" newline bitfld.long 0x20 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" bitfld.long 0x20 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" newline bitfld.long 0x20 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x20 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x20 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x20 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x24 "VIP_INT0_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x24 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x28 "VIP_INT0_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x28 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x28 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" newline bitfld.long 0x28 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" bitfld.long 0x28 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" newline bitfld.long 0x28 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x28 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x28 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x28 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" newline bitfld.long 0x28 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" bitfld.long 0x28 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" newline bitfld.long 0x28 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x28 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x28 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x28 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" newline bitfld.long 0x28 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" bitfld.long 0x28 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" newline bitfld.long 0x28 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x28 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x28 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x28 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" newline bitfld.long 0x28 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" bitfld.long 0x28 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" newline bitfld.long 0x28 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x28 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x28 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x28 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" newline bitfld.long 0x28 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" bitfld.long 0x28 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" newline bitfld.long 0x28 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x28 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x28 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x28 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x2C "VIP_INT0_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x2C 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x30 "VIP_INT0_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x30 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x30 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" newline bitfld.long 0x30 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" bitfld.long 0x30 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" newline bitfld.long 0x30 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x30 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x30 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x30 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" newline bitfld.long 0x30 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" bitfld.long 0x30 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" newline bitfld.long 0x30 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x30 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x30 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x30 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" newline bitfld.long 0x30 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" bitfld.long 0x30 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" newline bitfld.long 0x30 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x30 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x30 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x30 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" newline bitfld.long 0x30 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" bitfld.long 0x30 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" newline bitfld.long 0x30 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x30 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x30 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x30 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" newline bitfld.long 0x30 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" bitfld.long 0x30 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" newline bitfld.long 0x30 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x30 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x30 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x30 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x34 "VIP_INT0_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x34 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x38 "VIP_INT0_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x38 31. "INT_STAT_TRANSCODE2_CHROMA,The last write DMA transaction has completed for channel transcode2_chroma" "0,1" bitfld.long 0x38 30. "INT_STAT_TRANSCODE2_LUMA,The last write DMA transaction has completed for channel transcode2_luma" "0,1" newline bitfld.long 0x38 29. "INT_STAT_TRANSCODE1_CHROMA,The last write DMA transaction has completed for channel transcode1_luma" "0,1" bitfld.long 0x38 28. "INT_STAT_TRANSCODE1_LUMA,The last write DMA transaction has completed for channel transcode1_luma" "0,1" newline bitfld.long 0x38 27. "INT_STAT_AUX_IN,The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x38 26. "INT_STAT_PIP_FRAME,The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x38 25. "INT_STAT_POST_COMP_WR,The last write DMA transaction has completed for channel post_comp_wr" "0,1" bitfld.long 0x38 24. "INT_STAT_VBI_SD_VENC,The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer" "0,1" newline rbitfld.long 0x38 23. "RESERVED,Reserved" "0,1" bitfld.long 0x38 22. "INT_STAT_NF_LAST_CHROMA,The last write DMA transaction has completed for channel nf_last_chroma" "0,1" newline bitfld.long 0x38 21. "INT_STAT_NF_LAST_LUMA,The last write DMA transaction has completed for channel nf_last_luma" "0,1" bitfld.long 0x38 20. "INT_STAT_NF_WRITE_CHROMA,The last write DMA transaction has completed for channel nf_write_chroma" "0,1" newline bitfld.long 0x38 19. "INT_STAT_NF_WRITE_LUMA,The last write DMA transaction has completed for channel nf_write_luma" "0,1" bitfld.long 0x38 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" newline bitfld.long 0x38 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x38 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x38 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x38 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" newline bitfld.long 0x38 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" bitfld.long 0x38 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" newline bitfld.long 0x38 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x38 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x38 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x38 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" newline bitfld.long 0x38 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" bitfld.long 0x38 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" newline bitfld.long 0x38 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x38 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x38 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x38 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" newline bitfld.long 0x38 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" bitfld.long 0x38 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x3C "VIP_INT0_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x3C 31. "INT_MASK_TRANSCODE2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 30. "INT_MASK_TRANSCODE2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 29. "INT_MASK_TRANSCODE1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 28. "INT_MASK_TRANSCODE1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 27. "INT_MASK_AUX_IN,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 26. "INT_MASK_PIP_FRAME,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 25. "INT_MASK_POST_COMP_WR,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 24. "INT_MASK_VBI_SD_VENC,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline rbitfld.long 0x3C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x3C 22. "INT_MASK_NF_LAST_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 21. "INT_MASK_NF_LAST_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 20. "INT_MASK_NF_WRITE_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 19. "INT_MASK_NF_WRITE_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" group.long 0x78++0x47 line.long 0x00 "VIP_INT0_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x00 31. "INT_STAT_GRPX1_DATA,The client interface grpx1_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 30. "INT_STAT_COMP_WRBK,The client interface comp_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 29. "INT_STAT_SC_OUT,The client interface sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" hexmask.long.byte 0x00 21.--28. 1. "RESERVED,Reserved" newline bitfld.long 0x00 20. "INT_STAT_SC_IN_LUMA,The client interface sc_in_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 19. "INT_STAT_SC_IN_CHROMA,The client interface sc_in_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 18. "INT_STAT_PIP_WRBK,The client interface pip_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 17. "INT_STAT_DEI_SC_OUT,The client interface dei_sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline rbitfld.long 0x00 16. "RESERVED,Reserved" "0,1" bitfld.long 0x00 15. "INT_STAT_DEI_HQ_MV_OUT,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline rbitfld.long 0x00 13.--14. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x00 12. "INT_STAT_DEI_HQ_MV_IN,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline rbitfld.long 0x00 6.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 5. "INT_STAT_DEI_HQ_3_CHROMA,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 4. "INT_STAT_DEI_HQ_3_LUMA,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 3. "INT_STAT_DEI_HQ_2_CHROMA,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 2. "INT_STAT_DEI_HQ_2_LUMA,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 1. "INT_STAT_DEI_HQ_1_LUMA,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 0. "INT_STAT_DEI_HQ_1_CHROMA,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x04 "VIP_INT0_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x04 31. "INT_MASK_GRPX1_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 30. "INT_MASK_COMP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 29. "INT_MASK_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" hexmask.long.byte 0x04 21.--28. 1. "RESERVED,Reserved" newline bitfld.long 0x04 20. "INT_MASK_SC_IN_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 19. "INT_MASK_SC_IN_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 18. "INT_MASK_PIP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 17. "INT_MASK_DEI_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline rbitfld.long 0x04 16. "RESERVED,Reserved" "0,1" bitfld.long 0x04 15. "INT_MASK_DEI_HQ_MV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline rbitfld.long 0x04 13.--14. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x04 12. "INT_MASK_DEI_HQ_MV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline rbitfld.long 0x04 6.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 5. "INT_MASK_DEI_HQ_3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 4. "INT_MASK_DEI_HQ_3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 3. "INT_MASK_DEI_HQ_2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 2. "INT_MASK_DEI_HQ_2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 1. "INT_MASK_DEI_HQ_1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 0. "INT_MASK_DEI_HQ_1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x08 "VIP_INT0_CLIENT1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" rbitfld.long 0x08 31. "RESERVED,Reserved" "0,1" rbitfld.long 0x08 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 29. "INT_STAT_VIP2_ANC_B,The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 28. "INT_STAT_VIP2_ANC_A,The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 27. "INT_STAT_VIP1_ANC_B,The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 26. "INT_STAT_VIP1_ANC_A,The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 25. "INT_STAT_TRANS2_LUMA,The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 24. "INT_STAT_TRANS2_CHROMA,The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 23. "INT_STAT_TRANS1_LUMA,The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 22. "INT_STAT_TRANS1_CHROMA,The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 21. "INT_STAT_HDMI_WRBK_OUT,The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 20. "INT_STAT_VPI_CTL,The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 19. "INT_STAT_VBI_SDVENC,The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" rbitfld.long 0x08 18. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 17. "INT_STAT_NF_420_UV_OUT,The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 16. "INT_STAT_NF_420_Y_OUT,The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 15. "INT_STAT_NF_420_UV_IN,The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 14. "INT_STAT_NF_420_Y_IN,The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 13. "INT_STAT_NF_422_IN,The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 12. "INT_STAT_GRPX3_ST,The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 11. "INT_STAT_GRPX2_ST,The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 10. "INT_STAT_GRPX1_ST,The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 9. "INT_STAT_VIP2_UP_UV,The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 8. "INT_STAT_VIP2_UP_Y,The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 7. "INT_STAT_VIP2_LO_UV,The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 6. "INT_STAT_VIP2_LO_Y,The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 5. "INT_STAT_VIP1_UP_UV,The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 4. "INT_STAT_VIP1_UP_Y,The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 3. "INT_STAT_VIP1_LO_UV,The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 2. "INT_STAT_VIP1_LO_Y,The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 1. "INT_STAT_GRPX3_DATA,The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 0. "INT_STAT_GRPX2_DATA,The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x0C "VIP_INT0_CLIENT1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" rbitfld.long 0x0C 31. "RESERVED,Reserved" "0,1" rbitfld.long 0x0C 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 29. "INT_MASK_VIP2_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 28. "INT_MASK_VIP2_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 27. "INT_MASK_VIP1_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 26. "INT_MASK_VIP1_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 25. "INT_MASK_TRANS2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 24. "INT_MASK_TRANS2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 23. "INT_MASK_TRANS1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 22. "INT_MASK_TRANS1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 21. "INT_MASK_HDMI_WRBK_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 20. "INT_MASK_VPI_CTL,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 19. "INT_MASK_VBI_SDVENC,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" rbitfld.long 0x0C 18. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 17. "INT_MASK_NF_420_UV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 16. "INT_MASK_NF_420_Y_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 15. "INT_MASK_NF_420_UV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 14. "INT_MASK_NF_420_Y_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 13. "INT_MASK_NF_422_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 12. "INT_MASK_GRPX3_ST,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 11. "INT_MASK_GRPX2_ST,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 10. "INT_MASK_GRPX1_ST,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 9. "INT_MASK_VIP2_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 8. "INT_MASK_VIP2_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 7. "INT_MASK_VIP2_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 6. "INT_MASK_VIP2_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 5. "INT_MASK_VIP1_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 4. "INT_MASK_VIP1_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 3. "INT_MASK_VIP1_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 2. "INT_MASK_VIP1_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 1. "INT_MASK_GRPX3_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 0. "INT_MASK_GRPX2_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x10 "VIP_INT0_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x10 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x10 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" newline bitfld.long 0x10 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" bitfld.long 0x10 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" newline bitfld.long 0x10 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x10 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x10 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x10 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" newline bitfld.long 0x10 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" bitfld.long 0x10 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" newline bitfld.long 0x10 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x10 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x10 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x10 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" newline bitfld.long 0x10 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" bitfld.long 0x10 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" newline bitfld.long 0x10 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x14 "VIP_INT0_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x14 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x18 "VIP_INT1_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x18 31. "INT_STAT_GRPX3,The last write DMA transaction has completed for channel scaler_out" "0,1" bitfld.long 0x18 30. "INT_STAT_GRPX2,The last write DMA transaction has completed for channel scaler_out" "0,1" newline bitfld.long 0x18 29. "INT_STAT_GRPX1,The last write DMA transaction has completed for channel scaler_out" "0,1" bitfld.long 0x18 28. "INT_STAT_SCALER_OUT,The last write DMA transaction has completed for channel scaler_out" "0,1" newline hexmask.long.byte 0x18 20.--27. 1. "RESERVED,Reserved" bitfld.long 0x18 19. "INT_STAT_SCALER_CHROMA,The last write DMA transaction has completed for channel scaler_luma" "0,1" newline bitfld.long 0x18 18. "INT_STAT_SCALER_LUMA,The last write DMA transaction has completed for channel scaler_luma" "0,1" bitfld.long 0x18 17. "INT_STAT_HQ_SCALER,The last write DMA transaction has completed for channel hq_scaler" "0,1" newline rbitfld.long 0x18 16. "RESERVED,Reserved" "0,1" bitfld.long 0x18 15. "INT_STAT_HQ_MV_OUT,The last write DMA transaction has completed for channel hq_mv_out" "0,1" newline rbitfld.long 0x18 13.--14. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x18 12. "INT_STAT_HQ_MV,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer" "0,1" newline rbitfld.long 0x18 6.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 5. "INT_STAT_HQ_VID3_CHROMA,The last write DMA transaction has completed for channel hq_vid3_chroma" "0,1" newline bitfld.long 0x18 4. "INT_STAT_HQ_VID3_LUMA,The last write DMA transaction has completed for channel hq_vid3_luma" "0,1" bitfld.long 0x18 3. "INT_STAT_HQ_VID2_CHROMA,The last write DMA transaction has completed for channel hq_vid2_chroma" "0,1" newline bitfld.long 0x18 2. "INT_STAT_HQ_VID2_LUMA,The last write DMA transaction has completed for channel hq_vid2_luma" "0,1" bitfld.long 0x18 1. "INT_STAT_HQ_VID1_CHROMA,The last write DMA transaction has completed for channel hq_vid1_chroma" "0,1" newline bitfld.long 0x18 0. "INT_STAT_HQ_VID1_LUMA,The last write DMA transaction has completed for channel hq_vid1_luma" "0,1" line.long 0x1C "VIP_INT1_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x1C 31. "INT_MASK_GRPX3,The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 30. "INT_MASK_GRPX2,The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 29. "INT_MASK_GRPX1,The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 28. "INT_MASK_SCALER_OUT,The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int1" "0,1" newline hexmask.long.byte 0x1C 20.--27. 1. "RESERVED,Reserved" bitfld.long 0x1C 19. "INT_MASK_SCALER_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 18. "INT_MASK_SCALER_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 17. "INT_MASK_HQ_SCALER,The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x1C 16. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 15. "INT_MASK_HQ_MV_OUT,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x1C 13.--14. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x1C 12. "INT_MASK_HQ_MV,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x1C 6.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 5. "INT_MASK_HQ_VID3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 4. "INT_MASK_HQ_VID3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 3. "INT_MASK_HQ_VID2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 2. "INT_MASK_HQ_VID2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 1. "INT_MASK_HQ_VID1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 0. "INT_MASK_HQ_VID1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x20 "VIP_INT1_CHANNEL1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x20 31. "INT_STAT_VIP1_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip1_mult_portb_src9" "0,1" bitfld.long 0x20 30. "INT_STAT_VIP1_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip1_mult_portb_src8" "0,1" newline bitfld.long 0x20 29. "INT_STAT_VIP1_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip1_mult_portb_src7" "0,1" bitfld.long 0x20 28. "INT_STAT_VIP1_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip1_mult_portb_src6" "0,1" newline bitfld.long 0x20 27. "INT_STAT_VIP1_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip1_mult_portb_src5" "0,1" bitfld.long 0x20 26. "INT_STAT_VIP1_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip1_mult_portb_src4" "0,1" newline bitfld.long 0x20 25. "INT_STAT_VIP1_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip1_mult_portb_src3" "0,1" bitfld.long 0x20 24. "INT_STAT_VIP1_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip1_mult_portb_src2" "0,1" newline bitfld.long 0x20 23. "INT_STAT_VIP1_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip1_mult_portb_src1" "0,1" bitfld.long 0x20 22. "INT_STAT_VIP1_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip1_mult_portb_src0" "0,1" newline bitfld.long 0x20 21. "INT_STAT_VIP1_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip1_mult_porta_src15" "0,1" bitfld.long 0x20 20. "INT_STAT_VIP1_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip1_mult_porta_src14" "0,1" newline bitfld.long 0x20 19. "INT_STAT_VIP1_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip1_mult_porta_src13" "0,1" bitfld.long 0x20 18. "INT_STAT_VIP1_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip1_mult_porta_src12" "0,1" newline bitfld.long 0x20 17. "INT_STAT_VIP1_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip1_mult_porta_src11" "0,1" bitfld.long 0x20 16. "INT_STAT_VIP1_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip1_mult_porta_src10" "0,1" newline bitfld.long 0x20 15. "INT_STAT_VIP1_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip1_mult_porta_src9" "0,1" bitfld.long 0x20 14. "INT_STAT_VIP1_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip1_mult_porta_src8" "0,1" newline bitfld.long 0x20 13. "INT_STAT_VIP1_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip1_mult_porta_src7" "0,1" bitfld.long 0x20 12. "INT_STAT_VIP1_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip1_mult_porta_src6" "0,1" newline bitfld.long 0x20 11. "INT_STAT_VIP1_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip1_mult_porta_src5" "0,1" bitfld.long 0x20 10. "INT_STAT_VIP1_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip1_mult_porta_src4" "0,1" newline bitfld.long 0x20 9. "INT_STAT_VIP1_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip1_mult_porta_src3" "0,1" bitfld.long 0x20 8. "INT_STAT_VIP1_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip1_mult_porta_src2" "0,1" newline bitfld.long 0x20 7. "INT_STAT_VIP1_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip1_mult_porta_src1" "0,1" bitfld.long 0x20 6. "INT_STAT_VIP1_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip1_mult_porta_src0" "0,1" newline rbitfld.long 0x20 0.--5. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "VIP_INT1_CHANNEL1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x24 31. "INT_MASK_VIP1_MULT_PORTB_SRC9,The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 30. "INT_MASK_VIP1_MULT_PORTB_SRC8,The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 29. "INT_MASK_VIP1_MULT_PORTB_SRC7,The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 28. "INT_MASK_VIP1_MULT_PORTB_SRC6,The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 27. "INT_MASK_VIP1_MULT_PORTB_SRC5,The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 26. "INT_MASK_VIP1_MULT_PORTB_SRC4,The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 25. "INT_MASK_VIP1_MULT_PORTB_SRC3,The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 24. "INT_MASK_VIP1_MULT_PORTB_SRC2,The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 23. "INT_MASK_VIP1_MULT_PORTB_SRC1,The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 22. "INT_MASK_VIP1_MULT_PORTB_SRC0,The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 21. "INT_MASK_VIP1_MULT_PORTA_SRC15,The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 20. "INT_MASK_VIP1_MULT_PORTA_SRC14,The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 19. "INT_MASK_VIP1_MULT_PORTA_SRC13,The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 18. "INT_MASK_VIP1_MULT_PORTA_SRC12,The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 17. "INT_MASK_VIP1_MULT_PORTA_SRC11,The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 16. "INT_MASK_VIP1_MULT_PORTA_SRC10,The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 15. "INT_MASK_VIP1_MULT_PORTA_SRC9,The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 14. "INT_MASK_VIP1_MULT_PORTA_SRC8,The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 13. "INT_MASK_VIP1_MULT_PORTA_SRC7,The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 12. "INT_MASK_VIP1_MULT_PORTA_SRC6,The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 11. "INT_MASK_VIP1_MULT_PORTA_SRC5,The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 10. "INT_MASK_VIP1_MULT_PORTA_SRC4,The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 9. "INT_MASK_VIP1_MULT_PORTA_SRC3,The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 8. "INT_MASK_VIP1_MULT_PORTA_SRC2,The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 7. "INT_MASK_VIP1_MULT_PORTA_SRC1,The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 6. "INT_MASK_VIP1_MULT_PORTA_SRC0,The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x24 0.--5. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "VIP_INT1_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x28 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x28 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" newline bitfld.long 0x28 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" bitfld.long 0x28 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" newline bitfld.long 0x28 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x28 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x28 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x28 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" newline bitfld.long 0x28 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" bitfld.long 0x28 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" newline bitfld.long 0x28 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x28 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x28 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x28 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" newline bitfld.long 0x28 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" bitfld.long 0x28 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" newline bitfld.long 0x28 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x28 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x28 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x28 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" newline bitfld.long 0x28 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" bitfld.long 0x28 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" newline bitfld.long 0x28 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x28 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x28 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x28 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" newline bitfld.long 0x28 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" bitfld.long 0x28 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" newline bitfld.long 0x28 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x28 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x28 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x28 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x2C "VIP_INT1_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x2C 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x30 "VIP_INT1_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x30 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x30 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" newline bitfld.long 0x30 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" bitfld.long 0x30 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" newline bitfld.long 0x30 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x30 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x30 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x30 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" newline bitfld.long 0x30 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" bitfld.long 0x30 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" newline bitfld.long 0x30 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x30 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x30 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x30 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" newline bitfld.long 0x30 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" bitfld.long 0x30 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" newline bitfld.long 0x30 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x30 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x30 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x30 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" newline bitfld.long 0x30 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" bitfld.long 0x30 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" newline bitfld.long 0x30 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x30 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x30 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x30 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" newline bitfld.long 0x30 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" bitfld.long 0x30 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" newline bitfld.long 0x30 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x30 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x30 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x30 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x34 "VIP_INT1_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x34 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x38 "VIP_INT1_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x38 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x38 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" newline bitfld.long 0x38 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" bitfld.long 0x38 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" newline bitfld.long 0x38 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x38 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x38 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x38 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" newline bitfld.long 0x38 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" bitfld.long 0x38 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" newline bitfld.long 0x38 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x38 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x38 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x38 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" newline bitfld.long 0x38 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" bitfld.long 0x38 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" newline bitfld.long 0x38 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x38 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x38 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x38 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" newline bitfld.long 0x38 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" bitfld.long 0x38 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" newline bitfld.long 0x38 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x38 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x38 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x38 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" newline bitfld.long 0x38 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" bitfld.long 0x38 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" newline bitfld.long 0x38 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x38 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x38 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x38 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x3C "VIP_INT1_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x3C 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x40 "VIP_INT1_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x40 31. "INT_STAT_TRANSCODE2_CHROMA,The last write DMA transaction has completed for channel transcode2_chroma" "0,1" bitfld.long 0x40 30. "INT_STAT_TRANSCODE2_LUMA,The last write DMA transaction has completed for channel transcode2_luma" "0,1" newline bitfld.long 0x40 29. "INT_STAT_TRANSCODE1_CHROMA,The last write DMA transaction has completed for channel transcode1_chroma" "0,1" bitfld.long 0x40 28. "INT_STAT_TRANSCODE1_LUMA,The last write DMA transaction has completed for channel transcode1_luma" "0,1" newline bitfld.long 0x40 27. "INT_STAT_AUX_IN,The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x40 26. "INT_STAT_PIP_FRAME,The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x40 25. "INT_STAT_POST_COMP_WR,The last write DMA transaction has completed for channel post_comp_wr" "0,1" bitfld.long 0x40 24. "INT_STAT_VBI_SD_VENC,The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer" "0,1" newline rbitfld.long 0x40 23. "RESERVED,Reserved" "0,1" bitfld.long 0x40 22. "INT_STAT_NF_LAST_CHROMA,The last write DMA transaction has completed for channel nf_last_chroma" "0,1" newline bitfld.long 0x40 21. "INT_STAT_NF_LAST_LUMA,The last write DMA transaction has completed for channel nf_last_luma" "0,1" bitfld.long 0x40 20. "INT_STAT_NF_WRITE_CHROMA,The last write DMA transaction has completed for channel nf_write_chroma" "0,1" newline bitfld.long 0x40 19. "INT_STAT_NF_WRITE_LUMA,The last write DMA transaction has completed for channel nf_write_luma" "0,1" bitfld.long 0x40 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" newline bitfld.long 0x40 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x40 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x40 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x40 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" newline bitfld.long 0x40 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" bitfld.long 0x40 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" newline bitfld.long 0x40 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x40 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x40 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x40 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" newline bitfld.long 0x40 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" bitfld.long 0x40 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" newline bitfld.long 0x40 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x40 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x40 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x40 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" newline bitfld.long 0x40 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" bitfld.long 0x40 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x44 "VIP_INT1_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x44 31. "INT_MASK_TRANSCODE2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 30. "INT_MASK_TRANSCODE2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 29. "INT_MASK_TRANSCODE1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 28. "INT_MASK_TRANSCODE1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 27. "INT_MASK_AUX_IN,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 26. "INT_MASK_PIP_FRAME,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 25. "INT_MASK_POST_COMP_WR,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 24. "INT_MASK_VBI_SD_VENC,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x44 23. "RESERVED,Reserved" "0,1" bitfld.long 0x44 22. "INT_MASK_NF_LAST_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 21. "INT_MASK_NF_LAST_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 20. "INT_MASK_NF_WRITE_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 19. "INT_MASK_NF_WRITE_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" group.long 0xC8++0x17 line.long 0x00 "VIP_INT1_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x00 31. "INT_MASK_TRANSCODE2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 30. "INT_MASK_TRANSCODE2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 29. "INT_MASK_TRANSCODE1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 28. "INT_MASK_TRANSCODE1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 27. "INT_MASK_AUX_IN,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 26. "INT_MASK_PIP_FRAME,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 25. "INT_MASK_POST_COMP_WR,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 24. "INT_MASK_VBI_SD_VENC,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x00 23. "RESERVED,Reserved" "0,1" bitfld.long 0x00 22. "INT_MASK_NF_LAST_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 21. "INT_MASK_NF_LAST_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 20. "INT_MASK_NF_WRITE_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 19. "INT_MASK_NF_WRITE_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 18. "INT_MASK_NF_READ,The interrupt for Noise Filter Input Data 422 Interleaved should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 15. "INT_STAT_DEI_HQ_MV_OUT,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" rbitfld.long 0x00 13.--14. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 12. "INT_STAT_DEI_HQ_MV_IN,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" rbitfld.long 0x00 6.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5. "INT_STAT_DEI_HQ_3_CHROMA,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 4. "INT_STAT_DEI_HQ_3_LUMA,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 3. "INT_STAT_DEI_HQ_2_CHROMA,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 2. "INT_STAT_DEI_HQ_2_LUMA,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 1. "INT_STAT_DEI_HQ_1_LUMA,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 0. "INT_STAT_DEI_HQ_1_CHROMA,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x04 "VIP_INT1_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x04 31. "INT_MASK_GRPX1_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 30. "INT_MASK_COMP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 29. "INT_MASK_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" hexmask.long.byte 0x04 21.--28. 1. "RESERVED,Reserved" newline bitfld.long 0x04 20. "INT_MASK_SC_IN_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 19. "INT_MASK_SC_IN_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 18. "INT_MASK_PIP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 17. "INT_MASK_DEI_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x04 16. "RESERVED,Reserved" "0,1" bitfld.long 0x04 15. "INT_MASK_DEI_HQ_MV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x04 13.--14. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x04 12. "INT_MASK_DEI_HQ_MV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x04 6.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 5. "INT_MASK_DEI_HQ_3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 4. "INT_MASK_DEI_HQ_3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 3. "INT_MASK_DEI_HQ_2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 2. "INT_MASK_DEI_HQ_2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 1. "INT_MASK_DEI_HQ_1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 0. "INT_MASK_DEI_HQ_1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x08 "VIP_INT1_CLIENT1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" rbitfld.long 0x08 31. "RESERVED,Reserved" "0,1" rbitfld.long 0x08 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 29. "INT_STAT_VIP2_ANC_B,The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 28. "INT_STAT_VIP2_ANC_A,The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 27. "INT_STAT_VIP1_ANC_B,The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 26. "INT_STAT_VIP1_ANC_A,The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 25. "INT_STAT_TRANS2_LUMA,The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 24. "INT_STAT_TRANS2_CHROMA,The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 23. "INT_STAT_TRANS1_LUMA,The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 22. "INT_STAT_TRANS1_CHROMA,The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 21. "INT_STAT_HDMI_WRBK_OUT,The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 20. "INT_STAT_VPI_CTL,The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 19. "INT_STAT_VBI_SDVENC,The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" rbitfld.long 0x08 18. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 17. "INT_STAT_NF_420_UV_OUT,The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 16. "INT_STAT_NF_420_Y_OUT,The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 15. "INT_STAT_NF_420_UV_IN,The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 14. "INT_STAT_NF_420_Y_IN,The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 13. "INT_STAT_NF_422_IN,The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 12. "INT_STAT_GRPX3_ST,The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 11. "INT_STAT_GRPX2_ST,The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 10. "INT_STAT_GRPX1_ST,The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 9. "INT_STAT_VIP2_UP_UV,The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 8. "INT_STAT_VIP2_UP_Y,The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 7. "INT_STAT_VIP2_LO_UV,The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 6. "INT_STAT_VIP2_LO_Y,The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 5. "INT_STAT_VIP1_UP_UV,The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 4. "INT_STAT_VIP1_UP_Y,The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 3. "INT_STAT_VIP1_LO_UV,The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 2. "INT_STAT_VIP1_LO_Y,The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 1. "INT_STAT_GRPX3_DATA,The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 0. "INT_STAT_GRPX2_DATA,The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x0C "VIP_INT1_CLIENT1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" rbitfld.long 0x0C 31. "RESERVED,Reserved" "0,1" rbitfld.long 0x0C 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 29. "INT_MASK_VIP2_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 28. "INT_MASK_VIP2_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 27. "INT_MASK_VIP1_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 26. "INT_MASK_VIP1_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 25. "INT_MASK_TRANS2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 24. "INT_MASK_TRANS2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 23. "INT_MASK_TRANS1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 22. "INT_MASK_TRANS1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 21. "INT_MASK_HDMI_WRBK_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 20. "INT_MASK_VPI_CTL,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 19. "INT_MASK_VBI_SDVENC,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" rbitfld.long 0x0C 18. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 17. "INT_MASK_NF_420_UV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 16. "INT_MASK_NF_420_Y_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 15. "INT_MASK_NF_420_UV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 14. "INT_MASK_NF_420_Y_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 13. "INT_MASK_NF_422_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 12. "INT_MASK_GRPX3_ST,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 11. "INT_MASK_GRPX2_ST,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 10. "INT_MASK_GRPX1_ST,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 9. "INT_MASK_VIP2_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 8. "INT_MASK_VIP2_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 7. "INT_MASK_VIP2_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 6. "INT_MASK_VIP2_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 5. "INT_MASK_VIP1_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 4. "INT_MASK_VIP1_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 3. "INT_MASK_VIP1_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 2. "INT_MASK_VIP1_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 1. "INT_MASK_GRPX3_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 0. "INT_MASK_GRPX2_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x10 "VIP_INT1_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x10 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x10 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" newline bitfld.long 0x10 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" bitfld.long 0x10 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" newline bitfld.long 0x10 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x10 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x10 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x10 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" newline bitfld.long 0x10 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" bitfld.long 0x10 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" newline bitfld.long 0x10 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x10 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x10 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x10 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" newline bitfld.long 0x10 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" bitfld.long 0x10 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" newline bitfld.long 0x10 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x14 "VIP_INT1_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x14 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" group.long 0x388++0x1F line.long 0x00 "VIP0_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--9. 1. "RESERVED," line.long 0x04 "VIP0_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--9. 1. "RESERVED," line.long 0x08 "VIP0_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x08 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x08 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x08 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x08 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x08 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x08 0.--9. 1. "RESERVED," line.long 0x0C "VIP0_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x0C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x0C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x0C 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x0C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x0C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0C 0.--9. 1. "RESERVED," line.long 0x10 "VIP1_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x10 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x10 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x10 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x10 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x10 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x10 0.--9. 1. "RESERVED," line.long 0x14 "VIP1_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x14 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x14 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x14 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x14 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x14 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x14 0.--9. 1. "RESERVED," line.long 0x18 "VIP1_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x18 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x18 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x18 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x18 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x18 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x18 0.--9. 1. "RESERVED," line.long 0x1C "VIP1_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x1C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x1C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x1C 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x1C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x1C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 0.--9. 1. "RESERVED," group.long 0x3D0++0x03 line.long 0x00 "VPI_CTL_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--9. 1. "RESERVED," group.long 0x3E8++0x0F line.long 0x00 "VIP0_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--9. 1. "RESERVED," line.long 0x04 "VIP0_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--9. 1. "RESERVED," line.long 0x08 "VIP1_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x08 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x08 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x08 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x08 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x08 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x08 0.--9. 1. "RESERVED," line.long 0x0C "VIP1_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x0C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x0C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x0C 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x0C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x0C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0C 0.--9. 1. "RESERVED," repeat 14. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 ) group.long ($2+0x2C0)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline rbitfld.long 0x00 27. "RESERVED," "0,1" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline rbitfld.long 0x00 19. "RESERVED," "0,1" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" newline hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x280)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline rbitfld.long 0x00 27. "RESERVED," "0,1" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline rbitfld.long 0x00 19. "RESERVED," "0,1" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" newline hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x240)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline rbitfld.long 0x00 27. "RESERVED," "0,1" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline rbitfld.long 0x00 19. "RESERVED," "0,1" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" newline hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x200)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline rbitfld.long 0x00 27. "RESERVED," "0,1" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline rbitfld.long 0x00 19. "RESERVED," "0,1" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" newline hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end width 0x0B tree.end tree "VTNF" base ad:0x52020A00 rgroup.long 0x00++0x63 line.long 0x00 "VTNF_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "VTNF_CTRL,Control" hexmask.long.word 0x04 17.--31. 1. "RESERVED," bitfld.long 0x04 16. "BUSY,Idle/busy status (read-only)" "idle,busy" rbitfld.long 0x04 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 10. "AUTOGATING,Internal clock gating on OCP clock and functional clock" "clocks are free-running,clocks are gated off in subblocks that are not.." bitfld.long 0x04 9. "TRIG_SRC,Starting mechanism trigger source" "software writing 1 to EN,HW sequencer sending pulse on START signal" bitfld.long 0x04 8. "INTEN,Interrupt enable" "disable,enable" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "EN,Write 1 when TRIG_SRC=0 to start module operation" "0,1" line.long 0x08 "VTNF_CFG," hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED," bitfld.long 0x08 4.--7. "T,Round-down number of bits for SAD calculation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x08 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 0. "FMT,Previous frame output and current frame output format" "NV12,YV12" line.long 0x0C "VTNF_SZ,Configuration" hexmask.long.word 0x0C 16.--31. 1. "BLKH,Block height valid range 4..128 multiple of 4" hexmask.long.word 0x0C 0.--15. 1. "BLKW,Block width valid range 32..512 multiple of 32" line.long 0x10 "VTNF_CADR,Current frame input byte address" hexmask.long.word 0x10 16.--31. 1. "RESERVED," hexmask.long.word 0x10 4.--15. 1. "ADDR,Address in 128-bit words" rbitfld.long 0x10 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "VTNF_PADR,Previous frame output byte address" hexmask.long.word 0x14 16.--31. 1. "RESERVED," hexmask.long.word 0x14 4.--15. 1. "ADDR,Address in 128-bit words" rbitfld.long 0x14 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "VTNF_OADR,Current frame output byte address" hexmask.long.word 0x18 16.--31. 1. "RESERVED," hexmask.long.word 0x18 4.--15. 1. "ADDR,Address in 128-bit words" rbitfld.long 0x18 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "VTNF_LOFST,Line offset for C. P. O arrays" hexmask.long.word 0x1C 16.--31. 1. "RESERVED," hexmask.long.word 0x1C 4.--15. 1. "LOFST,Line offset in 128-bit words" rbitfld.long 0x1C 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "VTNF_WEIGHTS,Weights for SAD calculation" hexmask.long.word 0x20 22.--31. 1. "RESERVED," bitfld.long 0x20 16.--21. "W2,W2 parameter chroma weight for SAD calculation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x20 6.--15. 1. "RESERVED," newline bitfld.long 0x20 0.--5. "W1,W1 oarameter luma weight for SAD calculation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "VTNF_LUT1_0,Lookup table 1" hexmask.long.byte 0x24 24.--31. 1. "LUT1_3,LUT1[3]" hexmask.long.byte 0x24 16.--23. 1. "LUT1_2,LUT1[2]" hexmask.long.byte 0x24 8.--15. 1. "LUT1_1,LUT1[1]" newline hexmask.long.byte 0x24 0.--7. 1. "LUT1_0,LUT1[0]" line.long 0x28 "VTNF_LUT1_4,Lookup table 1" hexmask.long.byte 0x28 24.--31. 1. "LUT1_7,LUT1[7]" hexmask.long.byte 0x28 16.--23. 1. "LUT1_6,LUT1[6]" hexmask.long.byte 0x28 8.--15. 1. "LUT1_5,LUT1[5]" newline hexmask.long.byte 0x28 0.--7. 1. "LUT1_4,LUT1[4]" line.long 0x2C "VTNF_LUT1_8,Lookup table 1" hexmask.long.byte 0x2C 24.--31. 1. "LUT1_11,LUT1[11]" hexmask.long.byte 0x2C 16.--23. 1. "LUT1_10,LUT1[10]" hexmask.long.byte 0x2C 8.--15. 1. "LUT1_9,LUT1[9]" newline hexmask.long.byte 0x2C 0.--7. 1. "LUT1_8,LUT1[8]" line.long 0x30 "VTNF_LUT1_12,Lookup table 1" hexmask.long.byte 0x30 24.--31. 1. "LUT1_15,LUT1[15]" hexmask.long.byte 0x30 16.--23. 1. "LUT1_14,LUT1[14]" hexmask.long.byte 0x30 8.--15. 1. "LUT1_13,LUT1[13]" newline hexmask.long.byte 0x30 0.--7. 1. "LUT1_12,LUT1[12]" line.long 0x34 "VTNF_LUT1_16,Lookup table 1" hexmask.long.byte 0x34 24.--31. 1. "LUT1_19,LUT1[19]" hexmask.long.byte 0x34 16.--23. 1. "LUT1_18,LUT1[18]" hexmask.long.byte 0x34 8.--15. 1. "LUT1_17,LUT1[17]" newline hexmask.long.byte 0x34 0.--7. 1. "LUT1_16,LUT1[16]" line.long 0x38 "VTNF_LUT1_20,Lookup table 1" hexmask.long.byte 0x38 24.--31. 1. "LUT1_23,LUT1[23]" hexmask.long.byte 0x38 16.--23. 1. "LUT1_22,LUT1[22]" hexmask.long.byte 0x38 8.--15. 1. "LUT1_21,LUT1[21]" newline hexmask.long.byte 0x38 0.--7. 1. "LUT1_20,LUT1[20]" line.long 0x3C "VTNF_LUT1_24,Lookup table 1" hexmask.long.byte 0x3C 24.--31. 1. "LUT1_27,LUT1[27]" hexmask.long.byte 0x3C 16.--23. 1. "LUT1_26,LUT1[26]" hexmask.long.byte 0x3C 8.--15. 1. "LUT1_25,LUT1[25]" newline hexmask.long.byte 0x3C 0.--7. 1. "LUT1_24,LUT1[24]" line.long 0x40 "VTNF_LUT1_28,Lookup table 1" hexmask.long.byte 0x40 24.--31. 1. "LUT1_31,LUT1[31]" hexmask.long.byte 0x40 16.--23. 1. "LUT1_30,LUT1[30]" hexmask.long.byte 0x40 8.--15. 1. "LUT1_29,LUT1[29]" newline hexmask.long.byte 0x40 0.--7. 1. "LUT1_28,LUT1[28]" line.long 0x44 "VTNF_LUT2_0,Lookup table 1" hexmask.long.byte 0x44 24.--31. 1. "LUT2_3,LUT2[3]" hexmask.long.byte 0x44 16.--23. 1. "LUT2_2,LUT2[2]" hexmask.long.byte 0x44 8.--15. 1. "LUT2_1,LUT2[1]" newline hexmask.long.byte 0x44 0.--7. 1. "LUT2_0,LUT2[0]" line.long 0x48 "VTNF_LUT2_4,Lookup table 1" hexmask.long.byte 0x48 24.--31. 1. "LUT2_7,LUT2[7]" hexmask.long.byte 0x48 16.--23. 1. "LUT2_6,LUT2[6]" hexmask.long.byte 0x48 8.--15. 1. "LUT2_5,LUT2[5]" newline hexmask.long.byte 0x48 0.--7. 1. "LUT2_4,LUT2[4]" line.long 0x4C "VTNF_LUT2_8,Lookup table 1" hexmask.long.byte 0x4C 24.--31. 1. "LUT2_11,LUT2[11]" hexmask.long.byte 0x4C 16.--23. 1. "LUT2_10,LUT2[10]" hexmask.long.byte 0x4C 8.--15. 1. "LUT2_9,LUT2[9]" newline hexmask.long.byte 0x4C 0.--7. 1. "LUT2_8,LUT2[8]" line.long 0x50 "VTNF_LUT2_12,Lookup table 1" hexmask.long.byte 0x50 24.--31. 1. "LUT2_15,LUT2[15]" hexmask.long.byte 0x50 16.--23. 1. "LUT2_14,LUT2[14]" hexmask.long.byte 0x50 8.--15. 1. "LUT2_13,LUT2[13]" newline hexmask.long.byte 0x50 0.--7. 1. "LUT2_12,LUT2[12]" line.long 0x54 "VTNF_LUT2_16,Lookup table 1" hexmask.long.byte 0x54 24.--31. 1. "LUT2_19,LUT2[19]" hexmask.long.byte 0x54 16.--23. 1. "LUT2_18,LUT2[18]" hexmask.long.byte 0x54 8.--15. 1. "LUT2_17,LUT2[17]" newline hexmask.long.byte 0x54 0.--7. 1. "LUT2_16,LUT2[16]" line.long 0x58 "VTNF_LUT2_20,Lookup table 1" hexmask.long.byte 0x58 24.--31. 1. "LUT2_23,LUT2[23]" hexmask.long.byte 0x58 16.--23. 1. "LUT2_22,LUT2[22]" hexmask.long.byte 0x58 8.--15. 1. "LUT2_21,LUT2[21]" newline hexmask.long.byte 0x58 0.--7. 1. "LUT2_20,LUT2[20]" line.long 0x5C "VTNF_LUT2_24,Lookup table 1" hexmask.long.byte 0x5C 24.--31. 1. "LUT2_27,LUT2[27]" hexmask.long.byte 0x5C 16.--23. 1. "LUT2_26,LUT2[26]" hexmask.long.byte 0x5C 8.--15. 1. "LUT2_25,LUT2[25]" newline hexmask.long.byte 0x5C 0.--7. 1. "LUT2_24,LUT2[24]" line.long 0x60 "VTNF_LUT2_28,Lookup table 1" hexmask.long.byte 0x60 24.--31. 1. "LUT2_31,LUT2[31]" hexmask.long.byte 0x60 16.--23. 1. "LUT2_30,LUT2[30]" hexmask.long.byte 0x60 8.--15. 1. "LUT2_29,LUT2[29]" newline hexmask.long.byte 0x60 0.--7. 1. "LUT2_28,LUT2[28]" width 0x0B tree.end tree "WKUPAON_CM" base ad:0x4AE07800 group.long 0x00++0x03 line.long 0x00 "CM_WKUPAON_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline rbitfld.long 0x00 19. "CLKACTIVITY_ADC_L3_GICLK,This field indicates the state of the ADC_L3_GICLK clock in the domain(it includes profiling EMU_SYS_GCLK and all functional SYS_CLK. [warm reset insensitive]" "CLKACTIVITY_ADC_L3_GICLK_0,CLKACTIVITY_ADC_L3_GICLK_1" newline rbitfld.long 0x00 18. "CLKACTIVITY_UART10_GFCLK,This field indicates the state of the UART10_GFCLK clock in the domain" "CLKACTIVITY_UART10_GFCLK_0,CLKACTIVITY_UART10_GFCLK_1" newline rbitfld.long 0x00 17. "CLKACTIVITY_TIMER1_GFCLK,This field indicates the state of the TIMER1_GFCLK clock in the domain" "CLKACTIVITY_TIMER1_GFCLK_0,CLKACTIVITY_TIMER1_GFCLK_1" newline rbitfld.long 0x00 16. "CLKACTIVITY_DCAN1_SYS_CLK,This field indicates the state of the DCAN1_SYS_CLK clock in the domain" "CLKACTIVITY_DCAN1_SYS_CLK_0,CLKACTIVITY_DCAN1_SYS_CLK_1" newline rbitfld.long 0x00 15. "CLKACTIVITY_SYS_CLK_ALL,This field indicates the state of the SYS_CLK runing at SCRM level because of any SCRM clock request" "CLKACTIVITY_SYS_CLK_ALL_0,CLKACTIVITY_SYS_CLK_ALL_1" newline rbitfld.long 0x00 14. "CLKACTIVITY_SYS_CLK_FUNC,This field indicates the state of the functional SYS_CLK clocks in the domain (this exclude activity of EMU_GCLK clock)" "CLKACTIVITY_SYS_CLK_FUNC_0,CLKACTIVITY_SYS_CLK_FUNC_1" newline rbitfld.long 0x00 13. "CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK,This field indicates the state of the WKUPAON_IO_SRCOMP_GFCLK clock in the domain" "CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_0,CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_WKUPAON_GICLK,This field indicates the state of the WKUPAON_GICLK clock in the domain" "CLKACTIVITY_WKUPAON_GICLK_0,CLKACTIVITY_WKUPAON_GICLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_WKUPAON_SYS_GFCLK,This field indicates the state of the WKUPAON_SYS_GFCLK clock in the domain" "CLKACTIVITY_WKUPAON_SYS_GFCLK_0,CLKACTIVITY_WKUPAON_SYS_GFCLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_ADC_GFCLK,This field indicates the state of the ADC_GFCLK clock in the domain" "CLKACTIVITY_ADC_GFCLK_0,CLKACTIVITY_ADC_GFCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_ABE_LP_CLK,This field indicates the state of the ABE_LP_CLK clock in the domain" "CLKACTIVITY_ABE_LP_CLK_0,CLKACTIVITY_ABE_LP_CLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_SYS_CLK,This field indicates the state of the SYS_CLK clock in the domain(it includes profiling EMU_SYS_GCLK and all functional SYS_CLK. [warm reset insensitive]" "CLKACTIVITY_SYS_CLK_0,CLKACTIVITY_SYS_CLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the WKUPAON clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" rgroup.long 0x20++0x03 line.long 0x00 "CM_WKUPAON_L4_WKUP_CLKCTRL,This register manages the WKUPAON clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x28++0x03 line.long 0x00 "CM_WKUPAON_WD_TIMER1_CLKCTRL,This register manages the WD_TIMER1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x30++0x03 line.long 0x00 "CM_WKUPAON_WD_TIMER2_CLKCTRL,This register manages the WD_TIMER2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x38++0x03 line.long 0x00 "CM_WKUPAON_GPIO1_CLKCTRL,This register manages the GPIO1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_WKUPAON_TIMER1_CLKCTRL,This register manages the TIMER1 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x48++0x03 line.long 0x00 "CM_WKUPAON_TIMER12_CLKCTRL,This register manages the TIMER12 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x50++0x03 line.long 0x00 "CM_WKUPAON_COUNTER_32K_CLKCTRL,This register manages the COUNTER_32K clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x60++0x03 line.long 0x00 "CM_WKUPAON_SAR_RAM_CLKCTRL,This register manages the SAR_RAM clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x78++0x03 line.long 0x00 "CM_WKUPAON_KBD_CLKCTRL,This register manages the KBD clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x80++0x03 line.long 0x00 "CM_WKUPAON_UART10_CLKCTRL,This register manages the UART10 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," newline bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x88++0x03 line.long 0x00 "CM_WKUPAON_DCAN1_CLKCTRL,This register manages the DCAN1 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," newline bitfld.long 0x00 24. "CLKSEL,Selects functional clock for DCAN1" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x90++0x03 line.long 0x00 "CM_WKUPAON_SCRM_CLKCTRL,This register manages the SCRM clocks" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline bitfld.long 0x00 9. "OPTFCLKEN_SCRM_PER,Optional functional clock control" "OPTFCLKEN_SCRM_PER_0,OPTFCLKEN_SCRM_PER_1" newline bitfld.long 0x00 8. "OPTFCLKEN_SCRM_CORE,Optional functional clock control" "OPTFCLKEN_SCRM_CORE_0,OPTFCLKEN_SCRM_CORE_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0x98++0x03 line.long 0x00 "CM_WKUPAON_IO_SRCOMP_CLKCTRL,This register manages the clock delivered to the IO Slew rate compensation cells" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "CLKEN_SRCOMP_FCLK,Functional clock control" "CLKEN_SRCOMP_FCLK_0,CLKEN_SRCOMP_FCLK_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0xA0++0x03 line.long 0x00 "CM_WKUPAON_ADC_CLKCTRL,This register manages the ADC clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0xB0++0x03 line.long 0x00 "CM_WKUPAON_SPARE_SAFETY1_CLKCTRL,This register manages the SPARE_SAFETY1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xB8++0x03 line.long 0x00 "CM_WKUPAON_RTI1_CLKCTRL,This register manages the RTI1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xC0++0x03 line.long 0x00 "CM_WKUPAON_RTI2_CLKCTRL,This register manages the RTI2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xC8++0x03 line.long 0x00 "CM_WKUPAON_RTI3_CLKCTRL,This register manages the RTI3 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xD0++0x03 line.long 0x00 "CM_WKUPAON_RTI4_CLKCTRL,This register manages the RTI4 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xD8++0x03 line.long 0x00 "CM_WKUPAON_RTI5_CLKCTRL,This register manages the RTI5 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" width 0x0B tree.end tree "WKUPAON_PRM" base ad:0x4AE07724 group.long 0x00++0x2B line.long 0x00 "RM_WKUPAON_L4_WKUP_CONTEXT,This register contains dedicated L4_WKUP context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_WKUPAON_WD_TIMER1_WKDEP,This register controls wakeup dependency based on WD_TIMER1 service requests" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "WKUPDEP_WD_TIMER1_EVE4,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER1_EVE4_0,WKUPDEP_WD_TIMER1_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_WD_TIMER1_EVE3,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER1_EVE3_0,WKUPDEP_WD_TIMER1_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_WD_TIMER1_EVE2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER1_EVE2_0,WKUPDEP_WD_TIMER1_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_WD_TIMER1_EVE1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER1_EVE1_0,WKUPDEP_WD_TIMER1_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_WD_TIMER1_DSP2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER1_DSP2_0,WKUPDEP_WD_TIMER1_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_WD_TIMER1_IPU1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER1_IPU1_0,WKUPDEP_WD_TIMER1_IPU1_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "WKUPDEP_WD_TIMER1_DSP1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER1_DSP1_0,WKUPDEP_WD_TIMER1_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_WD_TIMER1_IPU2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER1_IPU2_0,WKUPDEP_WD_TIMER1_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_WD_TIMER1_MPU,Wakeup dependency from WDT1 module (SWakeup signal) towards MPU + L3MAIN1 + L4CFG domains" "WKUPDEP_WD_TIMER1_MPU_0,WKUPDEP_WD_TIMER1_MPU_1" line.long 0x08 "RM_WKUPAON_WD_TIMER1_CONTEXT,This register contains dedicated WD_TIMER1 context statuses" hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x0C "PM_WKUPAON_WD_TIMER2_WKDEP,This register controls wakeup dependency based on WD_TIMER2 service requests" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED," bitfld.long 0x0C 9. "WKUPDEP_WD_TIMER2_EVE4,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_EVE4_0,WKUPDEP_WD_TIMER2_EVE4_1" newline bitfld.long 0x0C 8. "WKUPDEP_WD_TIMER2_EVE3,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_EVE3_0,WKUPDEP_WD_TIMER2_EVE3_1" bitfld.long 0x0C 7. "WKUPDEP_WD_TIMER2_EVE2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_EVE2_0,WKUPDEP_WD_TIMER2_EVE2_1" newline bitfld.long 0x0C 6. "WKUPDEP_WD_TIMER2_EVE1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_EVE1_0,WKUPDEP_WD_TIMER2_EVE1_1" bitfld.long 0x0C 5. "WKUPDEP_WD_TIMER2_DSP2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_DSP2_0,WKUPDEP_WD_TIMER2_DSP2_1" newline bitfld.long 0x0C 4. "WKUPDEP_WD_TIMER2_IPU1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_IPU1_0,WKUPDEP_WD_TIMER2_IPU1_1" rbitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "WKUPDEP_WD_TIMER2_DSP1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_DSP1_0,WKUPDEP_WD_TIMER2_DSP1_1" bitfld.long 0x0C 1. "WKUPDEP_WD_TIMER2_IPU2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_IPU2_0,WKUPDEP_WD_TIMER2_IPU2_1" newline bitfld.long 0x0C 0. "WKUPDEP_WD_TIMER2_MPU,Wakeup dependency from WDT2 module (SWakeup signal) towards MPU + L3MAIN1 + L4CFG domains" "WKUPDEP_WD_TIMER2_MPU_0,WKUPDEP_WD_TIMER2_MPU_1" line.long 0x10 "RM_WKUPAON_WD_TIMER2_CONTEXT,This register contains dedicated WD_TIMER2 context statuses" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x14 "PM_WKUPAON_GPIO1_WKDEP,This register controls wakeup dependency based on GPIO1 service requests" hexmask.long.word 0x14 20.--31. 1. "RESERVED," bitfld.long 0x14 19. "WKUPDEP_GPIO1_IRQ2_EVE4,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_EVE4_0,WKUPDEP_GPIO1_IRQ2_EVE4_1" newline bitfld.long 0x14 18. "WKUPDEP_GPIO1_IRQ2_EVE3,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_EVE3_0,WKUPDEP_GPIO1_IRQ2_EVE3_1" bitfld.long 0x14 17. "WKUPDEP_GPIO1_IRQ2_EVE2,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_EVE2_0,WKUPDEP_GPIO1_IRQ2_EVE2_1" newline bitfld.long 0x14 16. "WKUPDEP_GPIO1_IRQ2_EVE1,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_EVE1_0,WKUPDEP_GPIO1_IRQ2_EVE1_1" bitfld.long 0x14 15. "WKUPDEP_GPIO1_IRQ2_DSP2,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_DSP2_0,WKUPDEP_GPIO1_IRQ2_DSP2_1" newline bitfld.long 0x14 14. "WKUPDEP_GPIO1_IRQ2_IPU1,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_IPU1_0,WKUPDEP_GPIO1_IRQ2_IPU1_1" rbitfld.long 0x14 13. "RESERVED," "0,1" newline bitfld.long 0x14 12. "WKUPDEP_GPIO1_IRQ2_DSP1,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_DSP1_0,WKUPDEP_GPIO1_IRQ2_DSP1_1" bitfld.long 0x14 11. "WKUPDEP_GPIO1_IRQ2_IPU2,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_IPU2_0,WKUPDEP_GPIO1_IRQ2_IPU2_1" newline bitfld.long 0x14 10. "WKUPDEP_GPIO1_IRQ2_MPU,Wakeup dependency from GPIO1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_MPU_0,WKUPDEP_GPIO1_IRQ2_MPU_1" bitfld.long 0x14 9. "WKUPDEP_GPIO1_IRQ1_EVE4,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_EVE4_0,WKUPDEP_GPIO1_IRQ1_EVE4_1" newline bitfld.long 0x14 8. "WKUPDEP_GPIO1_IRQ1_EVE3,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_EVE3_0,WKUPDEP_GPIO1_IRQ1_EVE3_1" bitfld.long 0x14 7. "WKUPDEP_GPIO1_IRQ1_EVE2,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_EVE2_0,WKUPDEP_GPIO1_IRQ1_EVE2_1" newline bitfld.long 0x14 6. "WKUPDEP_GPIO1_IRQ1_EVE1,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_EVE1_0,WKUPDEP_GPIO1_IRQ1_EVE1_1" bitfld.long 0x14 5. "WKUPDEP_GPIO1_IRQ1_DSP2,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_DSP2_0,WKUPDEP_GPIO1_IRQ1_DSP2_1" newline bitfld.long 0x14 4. "WKUPDEP_GPIO1_IRQ1_IPU1,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_IPU1_0,WKUPDEP_GPIO1_IRQ1_IPU1_1" rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 2. "WKUPDEP_GPIO1_IRQ1_DSP1,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_DSP1_0,WKUPDEP_GPIO1_IRQ1_DSP1_1" bitfld.long 0x14 1. "WKUPDEP_GPIO1_IRQ1_IPU2,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_IPU2_0,WKUPDEP_GPIO1_IRQ1_IPU2_1" newline bitfld.long 0x14 0. "WKUPDEP_GPIO1_IRQ1_MPU,Wakeup dependency from GPIO1 module (SWakeup signal for POROCPSINTERRUPT1 ) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_MPU_0,WKUPDEP_GPIO1_IRQ1_MPU_1" line.long 0x18 "RM_WKUPAON_GPIO1_CONTEXT,This register contains dedicated GPIO1 context statuses" hexmask.long 0x18 1.--31. 1. "RESERVED," bitfld.long 0x18 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x1C "PM_WKUPAON_TIMER1_WKDEP,This register controls wakeup dependency based on TIMER1 service requests" hexmask.long.tbyte 0x1C 10.--31. 1. "RESERVED," bitfld.long 0x1C 9. "WKUPDEP_TIMER1_EVE4,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_EVE4_0,WKUPDEP_TIMER1_EVE4_1" newline bitfld.long 0x1C 8. "WKUPDEP_TIMER1_EVE3,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_EVE3_0,WKUPDEP_TIMER1_EVE3_1" bitfld.long 0x1C 7. "WKUPDEP_TIMER1_EVE2,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_EVE2_0,WKUPDEP_TIMER1_EVE2_1" newline bitfld.long 0x1C 6. "WKUPDEP_TIMER1_EVE1,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_EVE1_0,WKUPDEP_TIMER1_EVE1_1" bitfld.long 0x1C 5. "WKUPDEP_TIMER1_DSP2,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_DSP2_0,WKUPDEP_TIMER1_DSP2_1" newline bitfld.long 0x1C 4. "WKUPDEP_TIMER1_IPU1,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_IPU1_0,WKUPDEP_TIMER1_IPU1_1" rbitfld.long 0x1C 3. "RESERVED," "0,1" newline bitfld.long 0x1C 2. "WKUPDEP_TIMER1_DSP1,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_DSP1_0,WKUPDEP_TIMER1_DSP1_1" bitfld.long 0x1C 1. "WKUPDEP_TIMER1_IPU2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_IPU2_0,WKUPDEP_TIMER1_IPU2_1" newline bitfld.long 0x1C 0. "WKUPDEP_TIMER1_MPU,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_MPU_0,WKUPDEP_TIMER1_MPU_1" line.long 0x20 "RM_WKUPAON_TIMER1_CONTEXT,This register contains dedicated TIMER1 context statuses" hexmask.long 0x20 1.--31. 1. "RESERVED," bitfld.long 0x20 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x24 "PM_WKUPAON_TIMER12_WKDEP,This register controls wakeup dependency based on TIMER12 service requests" hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED," bitfld.long 0x24 9. "WKUPDEP_TIMER12_EVE4,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_EVE4_0,WKUPDEP_TIMER12_EVE4_1" newline bitfld.long 0x24 8. "WKUPDEP_TIMER12_EVE3,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_EVE3_0,WKUPDEP_TIMER12_EVE3_1" bitfld.long 0x24 7. "WKUPDEP_TIMER12_EVE2,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_EVE2_0,WKUPDEP_TIMER12_EVE2_1" newline bitfld.long 0x24 6. "WKUPDEP_TIMER12_EVE1,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_EVE1_0,WKUPDEP_TIMER12_EVE1_1" bitfld.long 0x24 5. "WKUPDEP_TIMER12_DSP2,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_DSP2_0,WKUPDEP_TIMER12_DSP2_1" newline bitfld.long 0x24 4. "WKUPDEP_TIMER12_IPU1,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_IPU1_0,WKUPDEP_TIMER12_IPU1_1" rbitfld.long 0x24 3. "RESERVED," "0,1" newline bitfld.long 0x24 2. "WKUPDEP_TIMER12_DSP1,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_DSP1_0,WKUPDEP_TIMER12_DSP1_1" bitfld.long 0x24 1. "WKUPDEP_TIMER12_IPU2,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_IPU2_0,WKUPDEP_TIMER12_IPU2_1" newline bitfld.long 0x24 0. "WKUPDEP_TIMER12_MPU,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_MPU_0,WKUPDEP_TIMER12_MPU_1" line.long 0x28 "RM_WKUPAON_TIMER12_CONTEXT,This register contains dedicated TIMER12 context statuses" hexmask.long 0x28 1.--31. 1. "RESERVED," bitfld.long 0x28 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x30++0x03 line.long 0x00 "RM_WKUPAON_COUNTER_32K_CONTEXT,This register contains dedicated COUNTER_32K context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x40++0x03 line.long 0x00 "RM_WKUPAON_SAR_RAM_CONTEXT,This register contains dedicated SAR_RAM context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_WKUP_BANK,Specify if memory-based context in WKUP_BANK memory bank has been lost due to a previous global cold reset" "LOSTMEM_WKUP_BANK_0,LOSTMEM_WKUP_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x54++0x17 line.long 0x00 "PM_WKUPAON_KBD_WKDEP,This register controls wakeup dependency based on KBD service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_KBD_EVE4,Wakeup dependency from KBD module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_EVE4_0,WKUPDEP_KBD_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_KBD_EVE3,Wakeup dependency from KBD module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_EVE3_0,WKUPDEP_KBD_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_KBD_EVE2,Wakeup dependency from KBD module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_EVE2_0,WKUPDEP_KBD_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_KBD_EVE1,Wakeup dependency from KBD module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_EVE1_0,WKUPDEP_KBD_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_KBD_DSP2,Wakeup dependency from KBD module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_DSP2_0,WKUPDEP_KBD_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_KBD_IPU1,Wakeup dependency from KBD module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_IPU1_0,WKUPDEP_KBD_IPU1_1" rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_KBD_DSP1,Wakeup dependency from KBD module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_DSP1_0,WKUPDEP_KBD_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_KBD_IPU2,Wakeup dependency from KBD module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_IPU2_0,WKUPDEP_KBD_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_KBD_MPU,Wakeup dependency from KBD module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_MPU_0,WKUPDEP_KBD_MPU_1" line.long 0x04 "RM_WKUPAON_KBD_CONTEXT,This register contains dedicated KBD context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_WKUPAON_UART10_WKDEP,This register controls wakeup dependency based on UART10 service requests" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "WKUPDEP_UART10_EVE4,Wakeup dependency from UART10 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_EVE4_0,WKUPDEP_UART10_EVE4_1" newline bitfld.long 0x08 8. "WKUPDEP_UART10_EVE3,Wakeup dependency from UART10 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_EVE3_0,WKUPDEP_UART10_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_UART10_EVE2,Wakeup dependency from UART10 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_EVE2_0,WKUPDEP_UART10_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_UART10_EVE1,Wakeup dependency from UART10 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_EVE1_0,WKUPDEP_UART10_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_UART10_DSP2,Wakeup dependency from UART10 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_DSP2_0,WKUPDEP_UART10_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_UART10_IPU1,Wakeup dependency from UART10 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_IPU1_0,WKUPDEP_UART10_IPU1_1" bitfld.long 0x08 3. "WKUPDEP_UART10_SDMA,Wakeup dependency from UART10 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_SDMA_0,WKUPDEP_UART10_SDMA_1" newline bitfld.long 0x08 2. "WKUPDEP_UART10_DSP1,Wakeup dependency from UART10 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_DSP1_0,WKUPDEP_UART10_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_UART10_IPU2,Wakeup dependency from UART10 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_IPU2_0,WKUPDEP_UART10_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_UART10_MPU,Wakeup dependency from UART10 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_MPU_0,WKUPDEP_UART10_MPU_1" line.long 0x0C "RM_WKUPAON_UART10_CONTEXT,This register contains dedicated UART10 context statuses" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED," bitfld.long 0x0C 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in UART memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline hexmask.long.byte 0x0C 1.--7. 1. "RESERVED," bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_WKUPAON_DCAN1_WKDEP,This register controls wakeup dependency based on DCAN1 service requests" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED," bitfld.long 0x10 9. "WKUPDEP_DCAN1_EVE4,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_EVE4_0,WKUPDEP_DCAN1_EVE4_1" newline bitfld.long 0x10 8. "WKUPDEP_DCAN1_EVE3,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_EVE3_0,WKUPDEP_DCAN1_EVE3_1" bitfld.long 0x10 7. "WKUPDEP_DCAN1_EVE2,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_EVE2_0,WKUPDEP_DCAN1_EVE2_1" newline bitfld.long 0x10 6. "WKUPDEP_DCAN1_EVE1,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_EVE1_0,WKUPDEP_DCAN1_EVE1_1" bitfld.long 0x10 5. "WKUPDEP_DCAN1_DSP2,Wakeup dependency from DCAN1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_DSP2_0,WKUPDEP_DCAN1_DSP2_1" newline bitfld.long 0x10 4. "WKUPDEP_DCAN1_IPU1,Wakeup dependency from DCAN1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_IPU1_0,WKUPDEP_DCAN1_IPU1_1" bitfld.long 0x10 3. "WKUPDEP_DCAN1_SDMA,Wakeup dependency from DCAN1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_SDMA_0,WKUPDEP_DCAN1_SDMA_1" newline bitfld.long 0x10 2. "WKUPDEP_DCAN1_DSP1,Wakeup dependency from DCAN1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_DSP1_0,WKUPDEP_DCAN1_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_DCAN1_IPU2,Wakeup dependency from DCAN1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_IPU2_0,WKUPDEP_DCAN1_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_DCAN1_MPU,Wakeup dependency from DCAN1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_MPU_0,WKUPDEP_DCAN1_MPU_1" line.long 0x14 "RM_WKUPAON_DCAN1_CONTEXT,This register contains dedicated DCAN1 context statuses" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED," bitfld.long 0x14 8. "LOSTMEM_DCAN_MEM,Specify if memory-based context in DCAN memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DCAN_MEM_0,LOSTMEM_DCAN_MEM_1" newline hexmask.long.byte 0x14 1.--7. 1. "RESERVED," bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x7C++0x07 line.long 0x00 "PM_WKUPAON_ADC_WKDEP,This register controls wakeup dependency based on ADC service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_ADC_EVE4,Wakeup dependency from ADC module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_EVE4_0,WKUPDEP_ADC_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_ADC_EVE3,Wakeup dependency from ADC module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_EVE3_0,WKUPDEP_ADC_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_ADC_EVE2,Wakeup dependency from ADC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_EVE2_0,WKUPDEP_ADC_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_ADC_EVE1,Wakeup dependency from ADC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_EVE1_0,WKUPDEP_ADC_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_ADC_DSP2,Wakeup dependency from ADC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_DSP2_0,WKUPDEP_ADC_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_ADC_IPU1,Wakeup dependency from ADC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IPU1_0,WKUPDEP_ADC_IPU1_1" rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_ADC_DSP1,Wakeup dependency from ADC module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_DSP1_0,WKUPDEP_ADC_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_ADC_IPU2,Wakeup dependency from ADC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IPU2_0,WKUPDEP_ADC_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_ADC_MPU,Wakeup dependency from ADC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_MPU_0,WKUPDEP_ADC_MPU_1" line.long 0x04 "RM_WKUPAON_ADC_CONTEXT,This register contains dedicated ADC context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x90++0x03 line.long 0x00 "RM_WKUPAON_SPARE_SAFETY1_CONTEXT,This register contains dedicated SPARE_SAFETY1 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x98++0x03 line.long 0x00 "RM_WKUPAON_RTI1_CONTEXT,This register contains dedicated RTI1 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xA0++0x03 line.long 0x00 "RM_WKUPAON_RTI2_CONTEXT,This register contains dedicated RTI2 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xA8++0x03 line.long 0x00 "RM_WKUPAON_RTI3_CONTEXT,This register contains dedicated RTI3 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xB0++0x03 line.long 0x00 "RM_WKUPAON_RTI4_CONTEXT,This register contains dedicated RTI4 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xB8++0x03 line.long 0x00 "RM_WKUPAON_RTI5_CONTEXT,This register contains dedicated RTI5 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "WR" base ad:0x48485200 rgroup.long 0x00++0x1F line.long 0x00 "WR_IDVER,Subsystem wrapper revision register" line.long 0x04 "WR_SOFT_RESET,Subsystem soft reset register" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the CPGMACSS_R logic to be reset (INT REGS CPPI)" "0,1" line.long 0x08 "WR_CONTROL,Subsystem control register" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 8. "SS_EEE_EN,Subsystem Energy Efficient Ethernet enable" "EEE disabled,EEE enabled" rbitfld.long 0x08 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 2.--3. "MMR_STDBYMODE,Configuration of the local initiator state management mode" "MMR_STDBYMODE_0,MMR_STDBYMODE_1,MMR_STDBYMODE_2,MMR_STDBYMODE_3" bitfld.long 0x08 0.--1. "MMR_IDLEMODE,Configuration of the local initiator state management mode" "MMR_IDLEMODE_0,MMR_IDLEMODE_1,MMR_IDLEMODE_2,MMR_IDLEMODE_3" line.long 0x0C "WR_INT_CONTROL,Subsystem interrupt control" bitfld.long 0x0C 31. "INT_TEST,Interrupt Test - Test bit to the interrupt pacing blocks" "0,1" hexmask.long.word 0x0C 22.--30. 1. "RESERVED," bitfld.long 0x0C 16.--21. "INT_PACE_EN,Interrupt Pacing Enable INT_PACE_EN[0] - Enables RX_PULSE Pacing (0 is pacing bypass) INT_PACE_EN[1] - Enables TX_PULSE Pacing (0 is pacing bypass)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x0C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0C 0.--11. 1. "INT_PRESCALE,Interrupt Counter Prescaler - The number of MAIN_CLK periods in 4us" line.long 0x10 "WR_C0_RX_THRESH_EN,Subsystem core 0 receive threshold int enable register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED," hexmask.long.byte 0x10 0.--7. 1. "C0_RX_THRESH_EN,Core 0 Receive Threshold Enable - Each bit in this register corresponds to the bit in the receive threshold interrupt that is enabled to generate an interrupt on RX_THRESH_PULSE" line.long 0x14 "WR_C0_RX_EN,Subsystem core 0 receive interrupt enable register" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," hexmask.long.byte 0x14 0.--7. 1. "C0_RX_EN,Core 0 Receive Enable - Each bit in this register corresponds to the bit in the rx interrupt that is enabled to generate an interrupt on RX_PULSE" line.long 0x18 "WR_C0_TX_EN,Subsystem core 0 transmit interrupt enable register" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," hexmask.long.byte 0x18 0.--7. 1. "C0_TX_EN,Core 0 Transmit Enable - Each bit in this register corresponds to the bit in the tx interrupt that is enabled to generate an interrupt on TX_PULSE" line.long 0x1C "WR_C0_MISC_EN,Subsystem core 0 misc interrupt enable register" hexmask.long 0x1C 5.--31. 1. "RESERVED," bitfld.long 0x1C 0.--4. "C0_MISC_EN,Core 0 Misc Enable - Each bit in this register corresponds to the miscellaneous interrupt (SPF2_PEND SPF1_PEND EVNT_PEND STAT_PEND HOST_PEND MDIO_LINKINT MDIO_USERINT) that is enabled to generate an interrupt on MISC_PULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x40++0x0F line.long 0x00 "WR_C0_RX_THRESH_STAT,Subsystem core 0 rx threshold masked int status register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," hexmask.long.byte 0x00 0.--7. 1. "C0_RX_THRESH_STAT,Core 0 Receive Threshold Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the receive threshold interrupt that is enabled and generating an interrupt on RX_THRESH_PULSE" line.long 0x04 "WR_C0_RX_STAT,Subsystem core 0 rx interrupt masked int status register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," hexmask.long.byte 0x04 0.--7. 1. "C0_RX_STAT,Core 0 Receive Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the Rx interrupt that is enabled and generating an interrupt on RX_PULSE" line.long 0x08 "WR_C0_TX_STAT,Subsystem core 0 tx interrupt masked int status register" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED," hexmask.long.byte 0x08 0.--7. 1. "C0_TX_STAT,Core 0 Transmit Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the Tx interrupt that is enabled and generating an interrupt on TX_PULSE" line.long 0x0C "WR_C0_MISC_STAT,Subsystem core 0 misc interrupt masked int status register" hexmask.long 0x0C 5.--31. 1. "RESERVED," bitfld.long 0x0C 0.--4. "C0_MISC_STAT,Core 0 Misc Masked Interrupt Status - Each bit corresponds to the miscellaneous interrupt (SPF2_PEND SPF1_PEND EVNT_PEND STAT_PEND HOST_PEND MDIO_LINKINT MDIO_USERINT) that is enabled and generating an interrupt on MISC_PULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x70++0x07 line.long 0x00 "WR_C0_RX_IMAX,Subsystem core 0 receive interrupts per millisecond" hexmask.long 0x00 6.--31. 1. "RESERVED," bitfld.long 0x00 0.--5. "C0_RX_IMAX,Core 0 Receive Interrupts per Millisecond - The maximum number of interrupts per millisecond generated on RX_PULSE if pacing is enabled for this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "WR_C0_TX_IMAX,Subsystem core 0 transmit interrupts per millisecond" hexmask.long 0x04 6.--31. 1. "RESERVED," bitfld.long 0x04 0.--5. "C0_TX_IMAX,Core 0 Transmit Interrupts per Millisecond - The maximum number of interrupts per millisecond generated on TX_PULSE if pacing is enabled for this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x88++0x07 line.long 0x00 "WR_RGMII_CTL,RGMII control signal register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," bitfld.long 0x00 7. "RGMII2_FULLDUPLEX,RGMII 2 Fullduplex - This is the CPRGMII fullduplex output signal" "Half-duplex mode,Full-duplex mode" bitfld.long 0x00 5.--6. "RGMII2_SPEED,RGMII2 Speed - This is the CPRGMII speed output signal" "0,1,2,3" newline bitfld.long 0x00 4. "RGMII2_LINK,RGMII2 Link Indicator - This is the CPRGMII link output signal" "RGMII2 link is down,RGMII2 link is up" bitfld.long 0x00 3. "RGMII1_FULLDUPLEX,RGMII1 Fullduplex - This is the CPRGMII fullduplex output signal" "Half-duplex mode,Full-duplex mode" bitfld.long 0x00 1.--2. "RGMII1_SPEED,RGMII1 Speed - This is the CPRGMII speed output signal" "0,1,2,3" newline bitfld.long 0x00 0. "RGMII1_LINK,RGMII1 Link Indicator - This is the CPRGMII link output signal" "RGMII1 link is down,RGMII1 link is up" line.long 0x04 "WR_STATUS,Subsystem Status register" hexmask.long 0x04 3.--31. 1. "RESERVED," bitfld.long 0x04 2. "SPF2_CLKSTOP_ACK,SPF2 Clockstop Acknowledge - When asserted the subsystem gated clock is not turned on due to SPF2" "0,1" bitfld.long 0x04 1. "SPF1_CLKSTOP_ACK,SPF1 Clockstop Acknowledge - When asserted the subsystem gated clock is not turned on due to SPF1" "0,1" newline bitfld.long 0x04 0. "EEE_CLKSTOP_ACK,CPSW_3G Clockstop Acknowledge - When asserted the subsystem gated clock is not turned on due to the CPSW_3G" "0,1" width 0x0B tree.end endif sif (cpuis("TDA3XDSP*")) tree "ADC" base ad:0x4A264000 rgroup.long 0x00++0x03 line.long 0x00 "ADC_REVISION,Revision identifier" group.long 0x10++0x03 line.long 0x00 "ADC_SYSCONFIG,System configuration register" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--3. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x20++0x13 line.long 0x00 "ADC_IRQ_EOI,Software end of interrupt" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_w,?" line.long 0x04 "ADC_IRQSTATUS_RAW,Per-event raw interrupt status vector. showing all active events (enabled and not enabled)" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 8. "OUT_OF_RANGE,Status raw for interrupt" "No event pending,Event pending" newline bitfld.long 0x04 7. "FIFO1_UNDERFLOW,Status raw for interrupt" "No event pending,Event pending" newline bitfld.long 0x04 6. "FIFO1_OVERRUN,Status raw for interrupt" "No event pending,Event pending" newline bitfld.long 0x04 5. "FIFO1_THRESHOLD,Status raw for interrupt" "No event pending,Event pending" newline bitfld.long 0x04 4. "FIFO0_UNDERFLOW,Status raw for interrupt" "No event pending,Event pending" newline bitfld.long 0x04 3. "FIFO0_OVERRUN,Status raw for interrupt" "No event pending,Event pending" newline bitfld.long 0x04 2. "FIFO0_THRESHOLD,Status raw for interrupt" "No event pending,Event pending" newline bitfld.long 0x04 1. "END_OF_SEQUENCE,Status raw for interrupt" "No event pending,Event pending" newline bitfld.long 0x04 0. "RESERVED,Reserved" "0,1" line.long 0x08 "ADC_IRQSTATUS,Per-event 'enabled' status register vector" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x08 8. "OUT_OF_RANGE,Enabled status for interrupt" "No (enabled) event pending,Event pending" newline bitfld.long 0x08 7. "FIFO1_UNDERFLOW,Enabled status for interrupt" "No (enabled) event pending,Event pending" newline bitfld.long 0x08 6. "FIFO1_OVERRUN,Enabled status for interrupt" "No (enabled) event pending,Event pending" newline bitfld.long 0x08 5. "FIFO1_THRESHOLD,Enabled status for interrupt" "No (enabled) event pending,Event pending" newline bitfld.long 0x08 4. "FIFO0_UNDERFLOW,Enabled status for interrupt" "No (enabled) event pending,Event pending" newline bitfld.long 0x08 3. "FIFO0_OVERRUN,Enabled status for interrupt" "No (enabled) event pending,Event pending" newline bitfld.long 0x08 2. "FIFO0_THRESHOLD,Enabled status for interrupt" "No (enabled) event pending,Event pending" newline bitfld.long 0x08 1. "END_OF_SEQUENCE,Enabled status for interrupt" "No (enabled) event pending,Event pending" newline bitfld.long 0x08 0. "RESERVED,Reserved" "0,1" line.long 0x0C "ADC_IRQENABLE_SET,Per-event interrupt enable bit vector" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 8. "OUT_OF_RANGE,Interrupt enable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x0C 7. "FIFO1_UNDERFLOW,Interrupt enable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x0C 6. "FIFO1_OVERRUN,Interrupt enable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x0C 5. "FIFO1_THRESHOLD,Interrupt enable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x0C 4. "FIFO0_UNDERFLOW,Interrupt enable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x0C 3. "FIFO0_OVERRUN,Interrupt enable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x0C 2. "FIFO0_THRESHOLD,Interrupt enable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x0C 1. "END_OF_SEQUENCE,Interrupt enable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x0C 0. "RESERVED,Reserved" "0,1" line.long 0x10 "ADC_IRQENABLE_CLR,Per-event interrupt disable bit vector" hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 8. "OUT_OF_RANGE,Interrupt disable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x10 7. "FIFO1_UNDERFLOW,Interrupt disable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x10 6. "FIFO1_OVERRUN,Interrupt disable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x10 5. "FIFO1_THRESHOLD,Interrupt disable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x10 4. "FIFO0_UNDERFLOW,Interrupt disable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x10 3. "FIFO0_OVERRUN,Interrupt disable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x10 2. "FIFO0_THRESHOLD,Interrupt disable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x10 1. "END_OF_SEQUENCE,Interrupt disable" "Interrupt disabled (masked),Interrupt enabled" newline bitfld.long 0x10 0. "RESERVED,Reserved" "0,1" group.long 0x38++0x1F line.long 0x00 "ADC_DMAENABLE_SET,Per-line DMA enable bit vector" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "ENABLE_1,Enable DMA request FIFO 1" "DMA line disabled,DMA line enabled" newline bitfld.long 0x00 0. "ENABLE_0,Enable DMA request FIFO 0" "DMA line disabled,DMA line enabled" line.long 0x04 "ADC_DMAENABLE_CLR,Per-line DMA disable bit vector" hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 1. "ENABLE_1,Disable DMA request FIFO 1" "DMA line disabled,DMA line enabled" newline bitfld.long 0x04 0. "ENABLE_0,Disable DMA request FIFO 0" "DMA line disabled,DMA line enabled" line.long 0x08 "ADC_CTRL,ADC control register" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x08 9. "HW_PREEMPT," "0,1" newline bitfld.long 0x08 5.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 4. "POWER_DOWN,ADC Power Down control" "AFE is powered up,AFE is powered down (default) At default AFE is.." newline bitfld.long 0x08 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 1. "STEP_ID_TAG,Writing 1 to this bit will store the Step ID number with the captured ADC data in the FIFO" "write zeros,store the channel id tag" newline bitfld.long 0x08 0. "ADC_MODULE_ENABLE,ADC module enable bit" "0,1" line.long 0x0C "ADC_ADCSTAT,ADC sequencer status" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 8. "AFE_BUSY,Monitor the AFE internal calibration (busy bit)" "0,1" newline bitfld.long 0x0C 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 5. "FSM_BUSY,Status of OCP FSM and ADC FSM" "idle,busy.." newline bitfld.long 0x0C 0.--4. "STEP_ID," "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Step 1 - Step 16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Reserved" line.long 0x10 "ADC_ADCRANGE,ADC range check register" rbitfld.long 0x10 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x10 16.--27. 1. "HIGH_RANGE_DATA,Sampled ADC data is compared to this value" newline rbitfld.long 0x10 12.--15. "RESERVED,Reseved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x10 0.--11. 1. "LOW_RANGE_DATA,Sampled ADC data is compared to this value" line.long 0x14 "ADC_ADC_CLKDIV,The ADC_CLK input will go through this clock divider first before being sent to the AFE clock input" hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x14 0.--11. 1. "ADC_CLKDIV,The input ADC clock will be divided by this value and sent to the AFE" line.long 0x18 "ADC_ADC_MISC,Zero Offset Correction Using Efuse: Pro: - Covers the ground bounce due to package routing" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 8.--15. 1. "AFE_SPARE_OUTPUT,Connected to AFE Spare Output pins" newline abitfld.long 0x18 0.--7. "AFE_SPARE_INPUT,Connected to AFE Spare Input pins" "0x00=No action,0x01=Start internal calibration,0x02=Internal calibration start (then monitor.." line.long 0x1C "ADC_STEPENABLE,This register contains the enable bit for each step in the sequencer" hexmask.long.word 0x1C 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 16. "STEP16,Enable step 16" "0,1" newline bitfld.long 0x1C 15. "STEP15,Enable step 15" "0,1" newline bitfld.long 0x1C 14. "STEP14,Enable step 14" "0,1" newline bitfld.long 0x1C 13. "STEP13,Enable step 13" "0,1" newline bitfld.long 0x1C 12. "STEP12,Enable step 12" "0,1" newline bitfld.long 0x1C 11. "STEP11,Enable step 11" "0,1" newline bitfld.long 0x1C 10. "STEP10,Enable step 10" "0,1" newline bitfld.long 0x1C 9. "STEP9,Enable step 9" "0,1" newline bitfld.long 0x1C 8. "STEP8,Enable step 8" "0,1" newline bitfld.long 0x1C 7. "STEP7,Enable step 7" "0,1" newline bitfld.long 0x1C 6. "STEP6,Enable step 6" "0,1" newline bitfld.long 0x1C 5. "STEP5,Enable step 5" "0,1" newline bitfld.long 0x1C 4. "STEP4,Enable step 4" "0,1" newline bitfld.long 0x1C 3. "STEP3,Enable step 3" "0,1" newline bitfld.long 0x1C 2. "STEP2,Enable step 2" "0,1" newline bitfld.long 0x1C 1. "STEP1,Enable step 1" "0,1" newline bitfld.long 0x1C 0. "RESERVED,Reserved" "0,1" group.long 0x64++0x03 line.long 0x00 "ADC_STEPCONFIGi_0,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0x6C++0x03 line.long 0x00 "ADC_STEPCONFIGi_1,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0x74++0x03 line.long 0x00 "ADC_STEPCONFIGi_2,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0x7C++0x03 line.long 0x00 "ADC_STEPCONFIGi_3,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0x84++0x03 line.long 0x00 "ADC_STEPCONFIGi_4,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0x8C++0x03 line.long 0x00 "ADC_STEPCONFIGi_5,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0x94++0x03 line.long 0x00 "ADC_STEPCONFIGi_6,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0x9C++0x03 line.long 0x00 "ADC_STEPCONFIGi_7,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0xA4++0x03 line.long 0x00 "ADC_STEPCONFIGi_8,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0xAC++0x03 line.long 0x00 "ADC_STEPCONFIGi_9,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0xB4++0x03 line.long 0x00 "ADC_STEPCONFIGi_10,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0xBC++0x03 line.long 0x00 "ADC_STEPCONFIGi_11,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0xC4++0x03 line.long 0x00 "ADC_STEPCONFIGi_12,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0xCC++0x03 line.long 0x00 "ADC_STEPCONFIGi_13,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0xD4++0x03 line.long 0x00 "ADC_STEPCONFIGi_14,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0xDC++0x03 line.long 0x00 "ADC_STEPCONFIGi_15,Values sent to the AFE during step i" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RANGE_CHECK," "0,1" newline bitfld.long 0x00 26. "FIFO_SELECT,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" newline bitfld.long 0x00 23.--25. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. "SEL_INP_SWC,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN all other values =..,?..." newline hexmask.long.word 0x00 5.--18. 1. "RESERVED,Reserved" newline bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..." newline bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot (NOT SUPPORTED IN THIS..,HW synchronized continuous (NOT SUPPORTED IN.." group.long 0x68++0x03 line.long 0x00 "ADC_STEPDELAYi_0,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0x70++0x03 line.long 0x00 "ADC_STEPDELAYi_1,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0x78++0x03 line.long 0x00 "ADC_STEPDELAYi_2,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0x80++0x03 line.long 0x00 "ADC_STEPDELAYi_3,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0x88++0x03 line.long 0x00 "ADC_STEPDELAYi_4,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0x90++0x03 line.long 0x00 "ADC_STEPDELAYi_5,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0x98++0x03 line.long 0x00 "ADC_STEPDELAYi_6,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xA0++0x03 line.long 0x00 "ADC_STEPDELAYi_7,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xA8++0x03 line.long 0x00 "ADC_STEPDELAYi_8,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xB0++0x03 line.long 0x00 "ADC_STEPDELAYi_9,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xB8++0x03 line.long 0x00 "ADC_STEPDELAYi_10,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xC0++0x03 line.long 0x00 "ADC_STEPDELAYi_11,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xC8++0x03 line.long 0x00 "ADC_STEPDELAYi_12,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xD0++0x03 line.long 0x00 "ADC_STEPDELAYi_13,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xD8++0x03 line.long 0x00 "ADC_STEPDELAYi_14,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" group.long 0xE0++0x1B line.long 0x00 "ADC_STEPDELAYi_15,Step i delay register" hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of ADC clock cycles to hold SOC high" newline bitfld.long 0x00 18.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion (SOC)" line.long 0x04 "ADC_FIFO0COUNT,FIFO0 word count register" hexmask.long 0x04 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x04 0.--6. 1. "WORDS_IN_FIFO,Number of words currently in the FIFO0" line.long 0x08 "ADC_FIFO0THRESHOLD,FIFO0 threshold level register" hexmask.long 0x08 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x08 0.--5. "FIFO_THRESHOLD_LEVEL,Program the desired FIFO0 data sample level to reach before generating interrupt to CPU (program to value minus 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "ADC_DMA0REQ,FIFO0 DMA request level register" hexmask.long 0x0C 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 0.--5. "DMA_REQUEST_LEVEL,Number of words in FIFO0 before generating a DMA request (program to value minus 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "ADC_FIFO1COUNT,FIFO1 word count register" hexmask.long 0x10 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--6. 1. "WORDS_IN_FIFO,Number of words currently in the FIFO1" line.long 0x14 "ADC_FIFO1THRESHOLD,FIFO1 threshold level register" hexmask.long 0x14 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0.--5. "FIFO_THRESHOLD_LEVEL,Program the desired FIFO1 data sample level to reach before generating interrupt to CPU (program to value minus 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "ADC_DMA1REQ,FIFO1 DMA request level register" hexmask.long 0x18 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x18 0.--5. "DMA_REQUEST_LEVEL,Number of words in FIFO1 before generating a DMA request (program to value minus 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x100++0x03 line.long 0x00 "ADC_FIFO0DATA,The CPU can read from this register to read data in FIFO 0" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--19. "ADCCHNLID,Optional ID tag of channel that captured the data" "Step 1,Step2;,?,?,?,?,?,?,?,?,?,?,?,?,?,Step 16" newline bitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--11. 1. "ADCDATA,12 bit sampled ADC converted data value stored in FIFO 0" rgroup.long 0x200++0x03 line.long 0x00 "ADC_FIFO1DATA,The CPU can read from this register to read data in FIFO 1" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--19. "ADCCHNLID,Optional ID tag of channel that captured the data" "Step 1,Step2;,?,?,?,?,?,?,?,?,?,?,?,?,?,Step 16" newline bitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--11. 1. "ADCDATA,12 bit sampled ADC converted data value stored in FIFO 1" width 0x0B tree.end tree "ALE" base ad:0x48484D00 rgroup.long 0x00++0x03 line.long 0x00 "ALE_IDVER,ADDRESS LOOKUP ENGINE revision register" group.long 0x08++0x03 line.long 0x00 "ALE_CONTROL,Address lookup engine control register" bitfld.long 0x00 31. "ENABLE_ALE,Enable ALE" "Drop all packets,Enable ALE packet processing" newline bitfld.long 0x00 30. "CLEAR_TABLE,Clear ALE address table - Setting this bit causes the ALE hardware to write all table bit values to zero" "0,1" newline bitfld.long 0x00 29. "AGE_OUT_NOW,Age Out Address Table Now - Setting this bit causes the ALE hardware to remove (free up) any ageable table entry that does not have a set touch bit" "0,1" newline hexmask.long.tbyte 0x00 9.--28. 1. "RESERVED," newline bitfld.long 0x00 8. "EN_P0_UNI_FLOOD,Enable Port 0 (Host Port) unicast flood" "do not flood unknown unicast packets to host..,flood unknown unicast packets to host port (p0)" newline bitfld.long 0x00 7. "LEARN_NO_VID,Learn No VID" "VID is learned with the source address,VID is not learned with the source address.." newline bitfld.long 0x00 6. "EN_VID0_MODE,Enable VLAN ID = 0 Mode" "Process the packet with VID = PORT_VLAN[11:0],Process the packet with VID = 0" newline bitfld.long 0x00 5. "ENABLE_OUI_DENY,Enable OUI Deny Mode - When set this bit indicates that a packet with a non OUI table entry matching source address will be dropped to the host unless the destination address matches a multicast table entry with the super bit set" "0,1" newline bitfld.long 0x00 4. "BYPASS,ALE Bypass - When set all packets received on ports 0 and 1 are sent to the host (only to the host)" "0,1" newline bitfld.long 0x00 3. "RATE_LIMIT_TX,Rate Limit Transmit mode" "Broadcast and multicast rate limit counters are..,Broadcast and multicast rate limit counters are.." newline bitfld.long 0x00 2. "VLAN_AWARE,ALE VLAN Aware - Determines what is done if VLAN not found" "Flood if VLAN not found,Drop packet if VLAN not found" newline bitfld.long 0x00 1. "ENABLE_AUTH_MODE,Enable MAC Authorization Mode - Mac authorization mode requires that all table entries be made by the host software" "The ALE is not in MAC authorization mode,The ALE is in MAC authorization mode" newline bitfld.long 0x00 0. "ENABLE_RATE_LIMIT,Enable Broadcast and Multicast Rate Limit" "Broadcast/Multicast rates not limited,Broadcast/Multicast packet reception limited to.." group.long 0x10++0x03 line.long 0x00 "ALE_PRESCALE,Address lookup engine prescale register" hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--19. 1. "PRESCALE,ALE Prescale Register - The input clock is divided by this value for use in the multicast/broadcast rate limiters" group.long 0x18++0x03 line.long 0x00 "ALE_UNKNOWN_VLAN,Address lookup engine unknown vlan register" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 24.--29. "UNKNOWN_FORCE_UNTAGGED_EGRESS,Unknown VLAN Force Untagged Egress" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 16.--21. "UNKNOWN_REG_MCAST_FLOOD_MASK,Unknown VLAN Registered Multicast Flood Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 8.--13. "UNKNOWN_MCAST_FLOOD_MASK,Unknown VLAN Multicast Flood Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 0.--5. "UNKNOWN_VLAN_MEMBER_LIST,Unknown VLAN Member List" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x20++0x03 line.long 0x00 "ALE_TBLCTL,Address lookup engine table control" bitfld.long 0x00 31. "WRITE_RDZ,Write Bit - This bit is always read as zero" "0,1" newline hexmask.long.tbyte 0x00 10.--30. 1. "RESERVED," newline hexmask.long.word 0x00 0.--9. 1. "ENTRY_POINTER,Table Entry Pointer - The entry_pointer contains the table entry value that will be read/written with accesses to the table word registers" group.long 0x34++0x23 line.long 0x00 "ALE_TBLW2,Address lookup engine table word 2 register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--7. 1. "ENTRY71_64,Table entry bits 71:64" line.long 0x04 "ALE_TBLW1,Address lookup engine table word 1 register" line.long 0x08 "ALE_TBLW0,Address lookup engine table word 0 register" line.long 0x0C "ALE_PORTCTL0,Address lookup engine port 0 control register" hexmask.long.byte 0x0C 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x0C 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline hexmask.long.word 0x0C 6.--15. 1. "RESERVED," newline bitfld.long 0x0C 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x0C 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x0C 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x0C 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x0C 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x10 "ALE_PORTCTL1,Address lookup engine port 1 control register" hexmask.long.byte 0x10 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x10 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline hexmask.long.word 0x10 6.--15. 1. "RESERVED," newline bitfld.long 0x10 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x10 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x10 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x10 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x10 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x14 "ALE_PORTCTL2,Address lookup engine port 2 control register" hexmask.long.byte 0x14 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x14 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline hexmask.long.word 0x14 6.--15. 1. "RESERVED," newline bitfld.long 0x14 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x14 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x14 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x14 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x14 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x18 "ALE_PORTCTL3,Address lookup engine port 3 control register" hexmask.long.byte 0x18 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x18 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline hexmask.long.word 0x18 6.--15. 1. "RESERVED," newline bitfld.long 0x18 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x18 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x18 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x18 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x18 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x1C "ALE_PORTCTL4,Address lookup engine port 4 control register" hexmask.long.byte 0x1C 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x1C 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline hexmask.long.word 0x1C 6.--15. 1. "RESERVED," newline bitfld.long 0x1C 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x1C 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x1C 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x1C 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x1C 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x20 "ALE_PORTCTL5,Address lookup engine port 5 control register" hexmask.long.byte 0x20 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x20 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline hexmask.long.word 0x20 6.--15. 1. "RESERVED," newline bitfld.long 0x20 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x20 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x20 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x20 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x20 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" width 0x0B tree.end tree "CAM_CM_CORE" base ad:0x4A009000 group.long 0x00++0x07 line.long 0x00 "CM_CAM_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED," rbitfld.long 0x00 12. "CLKACTIVITY_LVDSRX_96M_GFCLK,This field indicates the state of the LVDSRX_96M_GFCLK clock input of the domain" "CLKACTIVITY_LVDSRX_96M_GFCLK_0,CLKACTIVITY_LVDSRX_96M_GFCLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_LVDSRX_L4_GICLK,This field indicates the state of the LVDSRX_L4_GICLK clock input of the domain" "CLKACTIVITY_LVDSRX_L4_GICLK_0,CLKACTIVITY_LVDSRX_L4_GICLK_1" rbitfld.long 0x00 10. "CLKACTIVITY_VIP3_GCLK,This field indicates the state of the VIP3_GCLK clock input of the domain" "CLKACTIVITY_VIP3_GCLK_0,CLKACTIVITY_VIP3_GCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_VIP2_GCLK,This field indicates the state of the VIP2_GCLK clock input of the domain" "CLKACTIVITY_VIP2_GCLK_0,CLKACTIVITY_VIP2_GCLK_1" rbitfld.long 0x00 8. "CLKACTIVITY_VIP1_GCLK,This field indicates the state of the VIP1_GCLK clock input of the domain" "CLKACTIVITY_VIP1_GCLK_0,CLKACTIVITY_VIP1_GCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the CAM clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_CAM_STATICDEP,This register controls the static domain depedencies from CAM domain towards 'target' domains" rbitfld.long 0x04 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 28. "ISS_STATDEP,Static dependency towards ISS clock domain" "ISS_STATDEP_0,ISS_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" rbitfld.long 0x04 26. "RESERVED," "0,1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain" "GMAC_STATDEP_0,GMAC_STATDEP_1" rbitfld.long 0x04 23.--24. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain" "EVE2_STATDEP_0,EVE2_STATDEP_1" bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain" "EVE1_STATDEP_0,EVE1_STATDEP_1" newline rbitfld.long 0x04 13.--18. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,?" newline rbitfld.long 0x04 6.--11. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" group.long 0x20++0x03 line.long 0x00 "CM_CAM_VIP1_CLKCTRL,This register manages the VIP1 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for VIP between L3_ICLK and CORE_ISS_MAIN_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x28++0x03 line.long 0x00 "CM_CAM_VIP2_CLKCTRL,This register manages the VIP2 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for VIP between L3_ICLK and CORE_ISS_MAIN_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x30++0x03 line.long 0x00 "CM_CAM_VIP3_CLKCTRL,This register manages the VIP3 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for VIP between L3_ICLK and CORE_ISS_MAIN_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x38++0x03 line.long 0x00 "CM_CAM_LVDSRX_CLKCTRL,This register manages the LVDSRX clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x40++0x03 line.long 0x00 "CM_CAM_CSI1_CLKCTRL,This register manages the CSI1 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x48++0x03 line.long 0x00 "CM_CAM_CSI2_CLKCTRL,This register manages the CSI2 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" width 0x0B tree.end tree "CAM_PRM" base ad:0x4AE07000 group.long 0x00++0x07 line.long 0x00 "PM_CAM_PWRSTCTRL,This register controls the CAM power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "VIP_BANK_ONSTATE,VIP_BANK memory state when domain is ON" "?,?,?,VIP_BANK_ONSTATE_3" newline hexmask.long.word 0x00 5.--15. 1. "RESERVED," bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_CAM_PWRSTST,This register provides a status on the current CAM power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "VIP_BANK_STATEST,VIP_BANK memory state status" "VIP_BANK_STATEST_0,VIP_BANK_STATEST_1,VIP_BANK_STATEST_2,VIP_BANK_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x20++0x17 line.long 0x00 "PM_CAM_VIP1_WKDEP,This register controls wakeup dependency based on VIP1 service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_VIP1_EVE4,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_EVE4_0,WKUPDEP_VIP1_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_VIP1_EVE3,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_EVE3_0,WKUPDEP_VIP1_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_VIP1_EVE2,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_EVE2_0,WKUPDEP_VIP1_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_VIP1_EVE1,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_EVE1_0,WKUPDEP_VIP1_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_VIP1_DSP2,Wakeup dependency from VIP1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_DSP2_0,WKUPDEP_VIP1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_VIP1_IPU1,Wakeup dependency from VIP1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_IPU1_0,WKUPDEP_VIP1_IPU1_1" rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_VIP1_DSP1,Wakeup dependency from VIP1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_DSP1_0,WKUPDEP_VIP1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_VIP1_IPU2,Wakeup dependency from vip1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_IPU2_0,WKUPDEP_VIP1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_VIP1_MPU,Wakeup dependency from VIP1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_MPU_0,WKUPDEP_VIP1_MPU_1" line.long 0x04 "RM_CAM_VIP1_CONTEXT,This register contains dedicated VIP1 context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_VIP_BANK,Specify if memory-based context in VIP_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VIP_BANK_0,LOSTMEM_VIP_BANK_1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_CAM_VIP2_WKDEP,This register controls wakeup dependency based on VIP2 service requests" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "WKUPDEP_VIP2_EVE4,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_EVE4_0,WKUPDEP_VIP2_EVE4_1" newline bitfld.long 0x08 8. "WKUPDEP_VIP2_EVE3,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_EVE3_0,WKUPDEP_VIP2_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_VIP2_EVE2,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_EVE2_0,WKUPDEP_VIP2_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_VIP2_EVE1,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_EVE1_0,WKUPDEP_VIP2_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_VIP2_DSP2,Wakeup dependency from VIP1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_DSP2_0,WKUPDEP_VIP2_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_VIP2_IPU1,Wakeup dependency from VIP2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_IPU1_0,WKUPDEP_VIP2_IPU1_1" rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 2. "WKUPDEP_VIP2_DSP1,Wakeup dependency from VIP2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_DSP1_0,WKUPDEP_VIP2_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_VIP2_IPU2,Wakeup dependency from VIP2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_IPU2_0,WKUPDEP_VIP2_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_VIP2_MPU,Wakeup dependency from VIP2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_MPU_0,WKUPDEP_VIP2_MPU_1" line.long 0x0C "RM_CAM_VIP2_CONTEXT,This register contains dedicated VIP2 context statuses" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED," bitfld.long 0x0C 8. "LOSTMEM_VIP_BANK,Specify if memory-based context in VIP_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VIP_BANK_0,LOSTMEM_VIP_BANK_1" newline hexmask.long.byte 0x0C 1.--7. 1. "RESERVED," bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_CAM_VIP3_WKDEP,This register controls wakeup dependency based on VIP3 service requests" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED," bitfld.long 0x10 9. "WKUPDEP_VIP3_EVE4,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_EVE4_0,WKUPDEP_VIP3_EVE4_1" newline bitfld.long 0x10 8. "WKUPDEP_VIP3_EVE3,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_EVE3_0,WKUPDEP_VIP3_EVE3_1" bitfld.long 0x10 7. "WKUPDEP_VIP3_EVE2,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_EVE2_0,WKUPDEP_VIP3_EVE2_1" newline bitfld.long 0x10 6. "WKUPDEP_VIP3_EVE1,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_EVE1_0,WKUPDEP_VIP3_EVE1_1" bitfld.long 0x10 5. "WKUPDEP_VIP3_DSP2,Wakeup dependency from VIP3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_DSP2_0,WKUPDEP_VIP3_DSP2_1" newline bitfld.long 0x10 4. "WKUPDEP_VIP3_IPU1,Wakeup dependency from VIP3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_IPU1_0,WKUPDEP_VIP3_IPU1_1" rbitfld.long 0x10 3. "RESERVED," "0,1" newline bitfld.long 0x10 2. "WKUPDEP_VIP3_DSP1,Wakeup dependency from VIP3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_DSP1_0,WKUPDEP_VIP3_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_VIP3_IPU2,Wakeup dependency from vip3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_IPU2_0,WKUPDEP_VIP3_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_VIP3_MPU,Wakeup dependency from VIP3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_MPU_0,WKUPDEP_VIP3_MPU_1" line.long 0x14 "RM_CAM_VIP3_CONTEXT,This register contains dedicated VIP3 context statuses" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED," bitfld.long 0x14 8. "LOSTMEM_VIP_BANK,Specify if memory-based context in VIP_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VIP_BANK_0,LOSTMEM_VIP_BANK_1" newline hexmask.long.byte 0x14 1.--7. 1. "RESERVED," bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x3C++0x03 line.long 0x00 "RM_CAM_LVDSRX_CONTEXT,This register contains dedicated LVDSRX context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x44++0x03 line.long 0x00 "RM_CAM_CSI1_CONTEXT,This register contains dedicated CSI1 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x4C++0x03 line.long 0x00 "RM_CAM_CSI2_CONTEXT,This register contains dedicated CSI2 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "CKGEN_CM_CORE" base ad:0x4A008104 group.long 0x00++0x03 line.long 0x00 "CM_CLKSEL_USB_60MHZ,Selects the configuration of the divider generating 60MHz clock for USB from the DPLL_USB o/p" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "CLKSEL,Select the configuration of the divider" "CLKSEL_0,CLKSEL_1" group.long 0x3C++0x2F line.long 0x00 "CM_CLKMODE_DPLL_PER,This register allows controlling the DPLL modes" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x00 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x00 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x00 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x00 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x00 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x00 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x00 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x00 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x00 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_PER,This register allows monitoring DPLL activity" hexmask.long 0x04 5.--31. 1. "RESERVED," bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_PER,This register provides automatic control over the DPLL activity" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_PER,This register provides controls over the DPLL" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" rbitfld.long 0x0C 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0C 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x0C 7. "RESERVED," "0,1" newline hexmask.long.byte 0x0C 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_PER,This register provides controls over the M2 divider of DPLL_PER" hexmask.long.tbyte 0x10 12.--31. 1. "RESERVED," rbitfld.long 0x10 11. "CLKX2ST,DPLL CLKOUTX2 status" "CLKX2ST_0,CLKX2ST_1" newline rbitfld.long 0x10 10. "RESERVED," "0,1" rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x10 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "CM_DIV_M3_DPLL_PER,This register provides controls over the M3 divider of the DPLL_PER" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," rbitfld.long 0x14 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x14 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x18 "CM_DIV_H11_DPLL_PER,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1 DPLL_PER" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," rbitfld.long 0x18 9. "CLKST,HSDIVIDER1 CLKOUT1 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x18 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--5. "DIVHS,DPLL (H11+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x1C "CM_DIV_H12_DPLL_PER,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER1 DPLL_PER" hexmask.long.tbyte 0x1C 10.--31. 1. "RESERVED," rbitfld.long 0x1C 9. "CLKST,HSDIVIDER1 CLKOUT2 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x1C 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--5. "DIVHS,DPLL (H12+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x20 "CM_DIV_H13_DPLL_PER,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER1 DPLL_PER" hexmask.long.tbyte 0x20 10.--31. 1. "RESERVED," rbitfld.long 0x20 9. "CLKST,HSDIVIDER1 CLKOUT3 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x20 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x20 0.--5. "DIVHS,DPLL (H13+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x24 "CM_DIV_H14_DPLL_PER,This register provides controls over the CLKOUT4 o/p of the HSDIVIDER1" hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED," rbitfld.long 0x24 9. "CLKST,HSDIVIDER1 CLKOUT4 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x24 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--5. "DIVHS,DPLL (H14+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x28 "CM_SSC_DELTAMSTEP_DPLL_PER,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x28 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x28 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x2C "CM_SSC_MODFREQDIV_DPLL_PER,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x2C 11.--31. 1. "RESERVED," bitfld.long 0x2C 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x2C 7. "RESERVED," "0,1" hexmask.long.byte 0x2C 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" group.long 0x7C++0x13 line.long 0x00 "CM_CLKMODE_DPLL_USB,This register allows controlling the DPLL modes" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x00 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x00 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x00 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" hexmask.long.word 0x00 3.--11. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_USB,This register allows monitoring DPLL activity" hexmask.long 0x04 5.--31. 1. "RESERVED," bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_USB,This register provides automatic control over the DPLL activity" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_USB,This register provides controls over the DPLL" hexmask.long.byte 0x0C 24.--31. 1. "DPLL_SD_DIV,Sigma-Delta divider select (2-255)" bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for CLKOUT,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" bitfld.long 0x0C 21. "DPLL_SELFREQDCO,select DCO output according to required frequency" "DPLL_SELFREQDCO_0,DPLL_SELFREQDCO_1" newline rbitfld.long 0x0C 20. "RESERVED," "0,1" hexmask.long.word 0x0C 8.--19. 1. "DPLL_MULT,DPLL multiplier factor (2 to 4095)" newline hexmask.long.byte 0x0C 0.--7. 1. "DPLL_DIV,DPLL divider factor (0 to 255) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_USB,This register provides controls over the M2 divider of the DPLL" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED," rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x10 7.--8. "RESERVED," "0,1,2,3" hexmask.long.byte 0x10 0.--6. 1. "DIVHS,DPLL M2 post-divider factor (1 to 127)" group.long 0xA4++0x07 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_USB,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x00 21.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--20. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_USB,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED," bitfld.long 0x04 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED," "0,1" hexmask.long.byte 0x04 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" rgroup.long 0xB0++0x03 line.long 0x00 "CM_CLKDCOLDO_DPLL_USB,This register provides status over CLKDCOLDO output of the DPLL" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "ST_DPLL_CLKDCOLDO,DPLL CLKDCOLDO status" "ST_DPLL_CLKDCOLDO_0,ST_DPLL_CLKDCOLDO_1" newline hexmask.long.word 0x00 0.--8. 1. "RESERVED," group.long 0xFC++0x2B line.long 0x00 "CM_CLKMODE_DPLL_PCIE_REF,This register allows controlling the DPLL modes" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x00 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x00 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x00 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" hexmask.long.word 0x00 3.--11. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_PCIE_REF,This register allows monitoring DPLL activity" hexmask.long 0x04 5.--31. 1. "RESERVED," bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_PCIE_REF,This register provides automatic control over the DPLL activity" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_PCIE_REF,This register provides controls over the DPLL" hexmask.long.byte 0x0C 24.--31. 1. "DPLL_SD_DIV,Sigma-Delta divider select (2-255)" bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for CLKOUT,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" bitfld.long 0x0C 21. "DPLL_SELFREQDCO,select DCO output according to required frequency" "DPLL_SELFREQDCO_0,DPLL_SELFREQDCO_1" newline rbitfld.long 0x0C 20. "RESERVED," "0,1" hexmask.long.word 0x0C 8.--19. 1. "DPLL_MULT,DPLL multiplier factor (2 to 4095)" newline hexmask.long.byte 0x0C 0.--7. 1. "DPLL_DIV,DPLL divider factor (0 to 255) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_PCIE_REF,This register provides controls over the M2 divider of the DPLL" hexmask.long.tbyte 0x10 11.--31. 1. "RESERVED," rbitfld.long 0x10 10. "CLKLDOST,DPLL CLKOUTLDO status" "CLKLDOST_0,CLKLDOST_1" newline rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" rbitfld.long 0x10 7.--8. "RESERVED," "0,1,2,3" newline hexmask.long.byte 0x10 0.--6. 1. "DIVHS,DPLL M2 post-divider factor (1 to 127)" line.long 0x14 "CM_SSC_DELTAMSTEP_DPLL_PCIE_REF,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x14 21.--31. 1. "RESERVED," hexmask.long.tbyte 0x14 0.--20. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x18 "CM_SSC_MODFREQDIV_DPLL_PCIE_REF,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x18 11.--31. 1. "RESERVED," bitfld.long 0x18 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED," "0,1" hexmask.long.byte 0x18 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x1C "CM_CLKMODE_APLL_PCIE,This register allows controlling the APLL modes" hexmask.long.tbyte 0x1C 9.--31. 1. "RESERVED," bitfld.long 0x1C 8. "CLKDIV_BYPASS," "CLKDIV_BYPASS_0,CLKDIV_BYPASS_1" newline bitfld.long 0x1C 7. "REFSEL,Select source of reference input clock" "REFSEL_0,REFSEL_1" rbitfld.long 0x1C 6. "RESERVED," "0,1" newline rbitfld.long 0x1C 3.--5. "INPSEL,Reference clock is 100MHz" "0,1,2,3,4,5,6,7" rbitfld.long 0x1C 2. "MODE,APLLPCIE Mode Status" "MODE_0,?" newline bitfld.long 0x1C 0.--1. "MODE_SELECT,Control APLL mode" "MODE_SELECT_0,MODE_SELECT_1,MODE_SELECT_2,MODE_SELECT_3" line.long 0x20 "CM_IDLEST_APLL_PCIE,This register allows monitoring APLL activity" hexmask.long 0x20 1.--31. 1. "RESERVED," bitfld.long 0x20 0. "ST_APLL_CLK,APLL lock status" "ST_APLL_CLK_0,ST_APLL_CLK_1" line.long 0x24 "CM_DIV_M2_APLL_PCIE,This register provides controls over the M2 divider of the DPLL" hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED," bitfld.long 0x24 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline bitfld.long 0x24 7.--8. "RESERVED," "0,1,2,3" hexmask.long.byte 0x24 0.--6. 1. "DIVHS,DPLL M2 post-divider factor (1 to 127)" line.long 0x28 "CM_CLKVCOLDO_APLL_PCIE,This register provides status over CLKVCOLDO and CLKVCOLDO_DIV outputs of the APLL" hexmask.long.tbyte 0x28 11.--31. 1. "RESERVED," bitfld.long 0x28 10. "CLK_DIVST,APLL CLKVCOLDO_DIV status" "CLK_DIVST_0,CLK_DIVST_1" newline bitfld.long 0x28 9. "CLKST,APLL CLKVCOLDO status" "CLKST_0,CLKST_1" hexmask.long.word 0x28 0.--8. 1. "RESERVED," width 0x0B tree.end tree "CKGEN_CM_CORE_AON" base ad:0x4A005100 group.long 0x00++0x03 line.long 0x00 "CM_CLKSEL_CORE,CORE module clock selection" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKSEL_L4,Selects L4 interconnect clock (L4_clk)" "CLKSEL_L4_0,CLKSEL_L4_1" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "CLKSEL_L3,Selects L3 interconnect clock (L3_clk)" "CLKSEL_L3_0,CLKSEL_L3_1" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x08++0x03 line.long 0x00 "CM_CLKSEL_ABE,ABE module clock selection" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," bitfld.long 0x00 10. "SLIMBUS1_CLK_GATE,Gating control for SLIMBUS_CLK clock tree in ABE" "SLIMBUS1_CLK_GATE_0,SLIMBUS1_CLK_GATE_1" newline rbitfld.long 0x00 9. "RESERVED," "0,1" bitfld.long 0x00 8. "PAD_CLKS_GATE,Gating control for PAD_CLKS clock tree in ABE" "PAD_CLKS_GATE_0,PAD_CLKS_GATE_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKSEL_OPP,Selects the OPP divider ABE domain" "CLKSEL_OPP_0,CLKSEL_OPP_1,CLKSEL_OPP_2,CLKSEL_OPP_3" group.long 0x10++0x03 line.long 0x00 "CM_DLL_CTRL,Special register for DLL control" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "DLL_OVERRIDE,Control if DLL lock and code outputs are overriden or not" "DLL_OVERRIDE_0,DLL_OVERRIDE_1" group.long 0x20++0x53 line.long 0x00 "CM_CLKMODE_DPLL_CORE,This register allows controlling the DPLL modes" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x00 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x00 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x00 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x00 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x00 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x00 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x00 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x00 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x00 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_CORE,This register allows monitoring DPLL activity" hexmask.long 0x04 5.--31. 1. "RESERVED," bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_CORE,This register provides automatic control over the DPLL activity" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_CORE,This register provides controls over the DPLL" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" rbitfld.long 0x0C 21. "RESERVED," "0,1" newline bitfld.long 0x0C 20. "DPLL_CLKOUTHIF_CLKSEL,Selects the source of the DPLL CLKOUTHIF clock" "DPLL_CLKOUTHIF_CLKSEL_0,DPLL_CLKOUTHIF_CLKSEL_1" rbitfld.long 0x0C 19. "RESERVED," "0,1" newline hexmask.long.word 0x0C 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x0C 7. "RESERVED," "0,1" newline hexmask.long.byte 0x0C 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_CORE,This register provides controls over the M2 divider of DPLL_CORE" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED," rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x10 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "CM_DIV_M3_DPLL_CORE,This register provides controls over the M3 divider of the DPLL" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," rbitfld.long 0x14 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x14 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x18 "CM_DIV_H11_DPLL_CORE,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," rbitfld.long 0x18 9. "CLKST,HSDIVIDER1 CLKOUT1 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x18 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--5. "DIVHS,DPLL (H11+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x1C "CM_DIV_H12_DPLL_CORE,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER1 DPLL_CORE" hexmask.long.tbyte 0x1C 10.--31. 1. "RESERVED,Reserved" rbitfld.long 0x1C 9. "CLKST,HSDIVIDER1 CLKOUT2 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x1C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--5. "DIVHS,DPLL (H12+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x20 "CM_DIV_H13_DPLL_CORE,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER1" hexmask.long.tbyte 0x20 10.--31. 1. "RESERVED,Reserved" rbitfld.long 0x20 9. "CLKST,HSDIVIDER1 CLKOUT3 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x20 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x20 0.--5. "DIVHS,DPLL (H13+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x24 "CM_DIV_H14_DPLL_CORE,This register provides controls over the CLKOUT4 o/p of the HSDIVIDER1 DPLL_CORE" hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED," rbitfld.long 0x24 9. "CLKST,HSDIVIDER1 CLKOUT4 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x24 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--5. "DIVHS,DPLL (H14+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x28 "CM_SSC_DELTAMSTEP_DPLL_CORE,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x28 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x28 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x2C "CM_SSC_MODFREQDIV_DPLL_CORE,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x2C 11.--31. 1. "RESERVED," bitfld.long 0x2C 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x2C 7. "RESERVED," "0,1" hexmask.long.byte 0x2C 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x30 "CM_DIV_H21_DPLL_CORE,This register provides controls over the CLKOUT1 o/p of the 2nd HSDIVIDER" hexmask.long.tbyte 0x30 10.--31. 1. "RESERVED," rbitfld.long 0x30 9. "CLKST,HSDIVIDER2 CLKOUT2 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x30 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x30 0.--5. "DIVHS,DPLL (H21+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x34 "CM_DIV_H22_DPLL_CORE,This register provides controls over the CLKOUT2 o/p of the 2nd HSDIVIDER DPLL_CORE" hexmask.long.tbyte 0x34 10.--31. 1. "RESERVED," rbitfld.long 0x34 9. "CLKST,HSDIVIDER2 CLKOUT2 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x34 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x34 0.--5. "DIVHS,DPLL (H22+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x38 "CM_DIV_H23_DPLL_CORE,This register provides controls over the CLKOUT3 o/p of the 2nd HSDIVIDER DPLL_CORE" hexmask.long.tbyte 0x38 10.--31. 1. "RESERVED," rbitfld.long 0x38 9. "CLKST,HSDIVIDER2 CLKOUT3 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x38 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x38 0.--5. "DIVHS,DPLL (H23+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x3C "CM_DIV_H24_DPLL_CORE,This register provides controls over the CLKOUT4 o/p of the 2nd HSDIVIDER DPLL_CORE" hexmask.long.tbyte 0x3C 10.--31. 1. "RESERVED," rbitfld.long 0x3C 9. "CLKST,HSDIVIDER2 CLKOUT4 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x3C 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x3C 0.--5. "DIVHS,DPLL (H24+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x40 "CM_CLKMODE_DPLL_MPU,This register allows controlling the DPLL modes" hexmask.long.word 0x40 16.--31. 1. "RESERVED," bitfld.long 0x40 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x40 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x40 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x40 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x40 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x40 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x40 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x40 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x40 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x40 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x40 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x44 "CM_IDLEST_DPLL_MPU,This register allows monitoring DPLL activity" hexmask.long 0x44 5.--31. 1. "RESERVED," bitfld.long 0x44 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x44 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x44 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x48 "CM_AUTOIDLE_DPLL_MPU,This register provides automatic control over the DPLL activity" hexmask.long 0x48 3.--31. 1. "RESERVED," bitfld.long 0x48 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x4C "CM_CLKSEL_DPLL_MPU,This register provides controls over the DPLL" hexmask.long.byte 0x4C 24.--31. 1. "RESERVED," rbitfld.long 0x4C 23. "DPLL_BYP_CLKSEL,Only CLKINPULOW bypass clock supported for this PLL" "0,1" newline bitfld.long 0x4C 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,DCC_EN_1" rbitfld.long 0x4C 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4C 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x4C 7. "RESERVED," "0,1" newline hexmask.long.byte 0x4C 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x50 "CM_DIV_M2_DPLL_MPU,This register provides controls over the M2 divider of the DPLL" hexmask.long.tbyte 0x50 10.--31. 1. "RESERVED," rbitfld.long 0x50 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x50 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x50 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x88++0x07 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_MPU,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x00 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_MPU,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED," bitfld.long 0x04 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED," "0,1" hexmask.long.byte 0x04 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" group.long 0x9C++0x1B line.long 0x00 "CM_BYPCLK_DPLL_MPU,Control MPU PLL BYPASS clock" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 0.--1. "CLKSEL,Select the DPLL MPU bypass clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" line.long 0x04 "CM_CLKMODE_DPLL_IVA,This register allows controlling the DPLL modes" hexmask.long.word 0x04 16.--31. 1. "RESERVED," bitfld.long 0x04 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x04 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x04 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x04 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x04 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x04 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x04 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x04 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x04 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x04 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x04 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x08 "CM_IDLEST_DPLL_IVA,This register allows monitoring DPLL activity" hexmask.long 0x08 5.--31. 1. "RESERVED," bitfld.long 0x08 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x08 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x08 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x0C "CM_AUTOIDLE_DPLL_IVA,This register provides automatic control over the DPLL activity" hexmask.long 0x0C 3.--31. 1. "RESERVED," bitfld.long 0x0C 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x10 "CM_CLKSEL_DPLL_IVA,This register provides controls over the DPLL" hexmask.long.byte 0x10 24.--31. 1. "RESERVED," bitfld.long 0x10 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x10 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" rbitfld.long 0x10 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x10 7. "RESERVED," "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x14 "CM_DIV_M2_DPLL_IVA,This register provides controls over the M2 divider of the DPLL" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," rbitfld.long 0x14 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x14 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x18 "CM_DIV_M3_DPLL_IVA,This register provides controls over the M3 divider of the DPLL" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," rbitfld.long 0x18 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x18 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0xC8++0x07 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_IVA,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x00 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_IVA,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED," bitfld.long 0x04 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED," "0,1" hexmask.long.byte 0x04 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" group.long 0xDC++0x1B line.long 0x00 "CM_BYPCLK_DPLL_IVA,Control IVA PLL BYPASS clock" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 0.--1. "CLKSEL,Select the DPLL IVA bypass clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" line.long 0x04 "CM_CLKMODE_DPLL_ABE,This register allows controlling the DPLL modes" hexmask.long.word 0x04 16.--31. 1. "RESERVED," bitfld.long 0x04 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x04 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x04 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x04 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" bitfld.long 0x04 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,DPLL_REGM4XEN_1" newline bitfld.long 0x04 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x04 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x04 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x04 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x04 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x04 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x08 "CM_IDLEST_DPLL_ABE,This register allows monitoring DPLL activity" hexmask.long 0x08 5.--31. 1. "RESERVED," bitfld.long 0x08 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x08 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x08 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x0C "CM_AUTOIDLE_DPLL_ABE,This register provides automatic control over the DPLL activity" hexmask.long 0x0C 3.--31. 1. "RESERVED," bitfld.long 0x0C 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x10 "CM_CLKSEL_DPLL_ABE,This register provides controls over the DPLL" hexmask.long.byte 0x10 24.--31. 1. "RESERVED," rbitfld.long 0x10 23. "DPLL_BYP_CLKSEL,Only CLKINPULOW bypass clock supported for this PLL" "0,1" newline rbitfld.long 0x10 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" rbitfld.long 0x10 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x10 7. "RESERVED," "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x14 "CM_DIV_M2_DPLL_ABE,This register provides controls over the H12 divider of the DPLL_DDR" hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED," rbitfld.long 0x14 11. "CLKX2ST,DPLL CLKOUTX2 status" "CLKX2ST_0,CLKX2ST_1" newline rbitfld.long 0x14 10. "RESERVED," "0,1" rbitfld.long 0x14 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x14 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x18 "CM_DIV_M3_DPLL_ABE,This register provides controls over the M3 divider of the DPLL" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," rbitfld.long 0x18 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x18 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x108++0x4F line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_ABE,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x00 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_ABE,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED," bitfld.long 0x04 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED," "0,1" hexmask.long.byte 0x04 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x08 "CM_CLKMODE_DPLL_DDR,This register allows controlling the DPLL modes" hexmask.long.word 0x08 16.--31. 1. "RESERVED," bitfld.long 0x08 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x08 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x08 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x08 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x08 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x08 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x08 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x08 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x08 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x08 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x08 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x0C "CM_IDLEST_DPLL_DDR,This register allows monitoring DPLL activity" hexmask.long 0x0C 5.--31. 1. "RESERVED," bitfld.long 0x0C 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x0C 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x0C 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x10 "CM_AUTOIDLE_DPLL_DDR,This register provides automatic control over the DPLL activity" hexmask.long 0x10 3.--31. 1. "RESERVED," bitfld.long 0x10 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x14 "CM_CLKSEL_DPLL_DDR,This register provides controls over the DPLL" hexmask.long.byte 0x14 24.--31. 1. "RESERVED," bitfld.long 0x14 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline bitfld.long 0x14 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,DCC_EN_1" rbitfld.long 0x14 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x14 7. "RESERVED," "0,1" newline hexmask.long.byte 0x14 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x18 "CM_DIV_M2_DPLL_DDR,This register provides controls over the M2 divider of DPLL_DDR" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," rbitfld.long 0x18 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x18 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x1C "CM_DIV_M3_DPLL_DDR,This register provides controls over the M3 divider of DPLL_DDR" hexmask.long.tbyte 0x1C 10.--31. 1. "RESERVED," rbitfld.long 0x1C 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x1C 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x20 "CM_DIV_H11_DPLL_DDR,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1 DPLL_DDR" hexmask.long.tbyte 0x20 10.--31. 1. "RESERVED," rbitfld.long 0x20 9. "CLKST,HSDIVIDER1 CLKOUT1 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x20 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x20 0.--5. "DIVHS,DPLL (H11+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x24 "CM_SSC_DELTAMSTEP_DPLL_DDR,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x24 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x24 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x28 "CM_SSC_MODFREQDIV_DPLL_DDR,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x28 11.--31. 1. "RESERVED," bitfld.long 0x28 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x28 7. "RESERVED," "0,1" hexmask.long.byte 0x28 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x2C "CM_CLKMODE_DPLL_DSP,This register allows controlling the DPLL modes" hexmask.long.word 0x2C 16.--31. 1. "RESERVED," bitfld.long 0x2C 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x2C 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x2C 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x2C 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x2C 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x2C 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x2C 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x2C 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x2C 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x2C 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x2C 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x30 "CM_IDLEST_DPLL_DSP,This register allows monitoring DPLL activity" hexmask.long 0x30 5.--31. 1. "RESERVED," bitfld.long 0x30 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x30 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x30 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x34 "CM_AUTOIDLE_DPLL_DSP,This register provides automatic control over the DPLL activity" hexmask.long 0x34 3.--31. 1. "RESERVED," bitfld.long 0x34 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x38 "CM_CLKSEL_DPLL_DSP,This register provides controls over the DPLL" hexmask.long.byte 0x38 24.--31. 1. "RESERVED," bitfld.long 0x38 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x38 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" rbitfld.long 0x38 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x38 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x38 7. "RESERVED," "0,1" newline hexmask.long.byte 0x38 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x3C "CM_DIV_M2_DPLL_DSP,This register provides controls over the M3 divider of DPLL_EVE_VID_DSP" hexmask.long.tbyte 0x3C 10.--31. 1. "RESERVED," rbitfld.long 0x3C 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x3C 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x3C 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x40 "CM_DIV_M3_DPLL_DSP,This register provides controls over the M3 divider of DPLL_CORE" hexmask.long.tbyte 0x40 10.--31. 1. "RESERVED," rbitfld.long 0x40 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x40 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x40 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x44 "CM_SSC_DELTAMSTEP_DPLL_DSP,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x44 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x44 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x48 "CM_SSC_MODFREQDIV_DPLL_DSP,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x48 11.--31. 1. "RESERVED," bitfld.long 0x48 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x48 7. "RESERVED," "0,1" hexmask.long.byte 0x48 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x4C "CM_BYPCLK_DPLL_DSP,Control IVA PLL BYPASS clock" hexmask.long 0x4C 2.--31. 1. "RESERVED," bitfld.long 0x4C 0.--1. "CLKSEL,Select the DPLL IVA bypass clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" group.long 0x160++0x07 line.long 0x00 "CM_SHADOW_FREQ_CONFIG1,Shadow register to program new DPLL configuration affecting EMIF and GPMC (L3 clock) functional frequency during DVFS" hexmask.long.word 0x00 19.--31. 1. "RESERVED," bitfld.long 0x00 16.--18. "DPLL_DDR_DPLL_EN,Shadow register forCM_CLKMODE_DPLL_DDR.DPLL_EN" "DPLL_DDR_DPLL_EN_0,DPLL_DDR_DPLL_EN_1,DPLL_DDR_DPLL_EN_2,DPLL_DDR_DPLL_EN_3,DPLL_DDR_DPLL_EN_4,DPLL_DDR_DPLL_EN_5,DPLL_DDR_DPLL_EN_6,DPLL_DDR_DPLL_EN_7" newline bitfld.long 0x00 11.--15. "DPLL_DDR_M2_DIV,Shadow register forCM_DIV_M2_DPLL_DDR.DIVHS" "DPLL_DDR_M2_DIV_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" hexmask.long.byte 0x00 4.--10. 1. "RESERVED," newline bitfld.long 0x00 3. "DLL_RESET,Specify if DLL should be reset or not during the frequency change hardware sequence" "DLL_RESET_0,DLL_RESET_1" bitfld.long 0x00 2. "DLL_OVERRIDE,Shadow register forCM_DLL_CTRL.DLL_OVERRIDE.The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to '1'" "DLL_OVERRIDE_0,DLL_OVERRIDE_1" newline rbitfld.long 0x00 1. "RESERVED," "0,1" bitfld.long 0x00 0. "FREQ_UPDATE,Writing '1' indicates that a new configuration is available" "0,1" line.long 0x04 "CM_SHADOW_FREQ_CONFIG2,Shadow register to program new DPLL configuration affecting GPMC (L3 clock) functional frequency during DVFS" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," bitfld.long 0x04 2.--7. "DPLL_CORE_H12_DIV,Shadow register forCM_DIV_H12_DPLL_CORE.DIVHS" "DPLL_CORE_H12_DIV_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 1. "CLKSEL_L3,Shadow register forCM_CLKSEL_CORE.CLKSEL_L3" "CLKSEL_L3_0,CLKSEL_L3_1" bitfld.long 0x04 0. "GPMC_FREQ_UPDATE,Controls whether or not GPMC has to be put automatically into idle during the frequency change operation" "GPMC_FREQ_UPDATE_0,GPMC_FREQ_UPDATE_1" group.long 0x170++0x03 line.long 0x00 "CM_DYN_DEP_PRESCAL,Control the time unit of the sliding window for dynamic dependencies (auto-sleep feature)" hexmask.long 0x00 6.--31. 1. "RESERVED," bitfld.long 0x00 0.--5. "PRESCAL,Time unit is equal to (PRESCAL + 1) L4 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x180++0x77 line.long 0x00 "CM_RESTORE_ST,Automatic restore status" hexmask.long 0x00 3.--31. 1. "RESERVED," bitfld.long 0x00 2. "PHASE2B_COMPLETED,Indicates if restore phase 2b is completed" "0,1" newline bitfld.long 0x00 1. "PHASE2A_COMPLETED,Indicates if restore phase 2a is completed" "0,1" bitfld.long 0x00 0. "PHASE1_COMPLETED,Indicates if restore phase 1 is completed" "0,1" line.long 0x04 "CM_CLKMODE_DPLL_EVE,This register allows controlling the DPLL modes" hexmask.long.word 0x04 16.--31. 1. "RESERVED," bitfld.long 0x04 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x04 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x04 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x04 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x04 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x04 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x04 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x04 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x04 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x04 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x04 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x08 "CM_IDLEST_DPLL_EVE,This register allows monitoring DPLL activity" hexmask.long 0x08 5.--31. 1. "RESERVED," bitfld.long 0x08 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x08 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x08 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x0C "CM_AUTOIDLE_DPLL_EVE,This register provides automatic control over the DPLL activity" hexmask.long 0x0C 3.--31. 1. "RESERVED," bitfld.long 0x0C 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x10 "CM_CLKSEL_DPLL_EVE,This register provides controls over the DPLL" hexmask.long.byte 0x10 24.--31. 1. "RESERVED," bitfld.long 0x10 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x10 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" rbitfld.long 0x10 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x10 7. "RESERVED," "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x14 "CM_DIV_M2_DPLL_EVE,This register provides controls over the M2 divider of the DPLL" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," rbitfld.long 0x14 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x14 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x18 "CM_DIV_M3_DPLL_EVE,This register provides controls over the M3 divider of the DPLL" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," rbitfld.long 0x18 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x18 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x1C "CM_SSC_DELTAMSTEP_DPLL_EVE,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x1C 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x1C 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x20 "CM_SSC_MODFREQDIV_DPLL_EVE,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x20 11.--31. 1. "RESERVED," bitfld.long 0x20 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 7. "RESERVED," "0,1" hexmask.long.byte 0x20 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x24 "CM_BYPCLK_DPLL_EVE,Control IVA PLL BYPASS clock" hexmask.long 0x24 2.--31. 1. "RESERVED," bitfld.long 0x24 0.--1. "CLKSEL,Select the DPLL IVA bypass clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" line.long 0x28 "CM_CLKMODE_DPLL_GMAC,This register allows controlling the DPLL modes" hexmask.long.word 0x28 16.--31. 1. "RESERVED," bitfld.long 0x28 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x28 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x28 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x28 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x28 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x28 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x28 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x28 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x28 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x28 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x28 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x2C "CM_IDLEST_DPLL_GMAC,This register allows monitoring DPLL activity" hexmask.long 0x2C 5.--31. 1. "RESERVED," bitfld.long 0x2C 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x2C 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x2C 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x30 "CM_AUTOIDLE_DPLL_GMAC,This register provides automatic control over the DPLL activity" hexmask.long 0x30 3.--31. 1. "RESERVED," bitfld.long 0x30 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x34 "CM_CLKSEL_DPLL_GMAC,This register provides controls over the DPLL" hexmask.long.byte 0x34 24.--31. 1. "RESERVED," bitfld.long 0x34 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline bitfld.long 0x34 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,DCC_EN_1" rbitfld.long 0x34 21. "RESERVED," "0,1" newline bitfld.long 0x34 20. "DPLL_CLKOUTHIF_CLKSEL,Selects the source of the DPLL CLKOUTHIF clock" "DPLL_CLKOUTHIF_CLKSEL_0,DPLL_CLKOUTHIF_CLKSEL_1" rbitfld.long 0x34 19. "RESERVED," "0,1" newline hexmask.long.word 0x34 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x34 7. "RESERVED," "0,1" newline hexmask.long.byte 0x34 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x38 "CM_DIV_M2_DPLL_GMAC,This register provides controls over the M2 divider of DPLL_GMAC_DSP" hexmask.long.tbyte 0x38 10.--31. 1. "RESERVED," rbitfld.long 0x38 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x38 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x38 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x3C "CM_DIV_M3_DPLL_GMAC,This register provides controls over the M3 divider of DPLL_GMAC_DSP" hexmask.long.tbyte 0x3C 10.--31. 1. "RESERVED," rbitfld.long 0x3C 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x3C 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x3C 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x40 "CM_DIV_H11_DPLL_GMAC,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1 DPLL_GMAC_DSP" hexmask.long.tbyte 0x40 10.--31. 1. "RESERVED," rbitfld.long 0x40 9. "CLKST,HSDIVIDER1 CLKOUT1 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x40 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x40 0.--5. "DIVHS,DPLL (H11+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x44 "CM_DIV_H12_DPLL_GMAC,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER1 DPLL_GMAC_DSP" hexmask.long.tbyte 0x44 10.--31. 1. "RESERVED,Reserved" rbitfld.long 0x44 9. "CLKST,HSDIVIDER1 CLKOUT2 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x44 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x44 0.--5. "DIVHS,DPLL (H12+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x48 "CM_DIV_H13_DPLL_GMAC,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER1 DPLL_GMAC_DSP" hexmask.long.tbyte 0x48 10.--31. 1. "RESERVED,Reserved" rbitfld.long 0x48 9. "CLKST,HSDIVIDER1 CLKOUT3 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x48 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x48 0.--5. "DIVHS,DPLL (H13+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x4C "CM_DIV_H14_DPLL_GMAC,This register provides controls over the CLKOUT4 o/p of the HSDIVIDER1 DPLL_GMAC_DSP" hexmask.long.tbyte 0x4C 10.--31. 1. "RESERVED," rbitfld.long 0x4C 9. "CLKST,HSDIVIDER1 CLKOUT4 status" "CLKST_0,CLKST_1" newline rbitfld.long 0x4C 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x4C 0.--5. "DIVHS,DPLL (H14+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x50 "CM_SSC_DELTAMSTEP_DPLL_GMAC,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x50 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x50 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x54 "CM_SSC_MODFREQDIV_DPLL_GMAC,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x54 11.--31. 1. "RESERVED," bitfld.long 0x54 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x54 7. "RESERVED," "0,1" hexmask.long.byte 0x54 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x58 "CM_CLKMODE_DPLL_GPU,This register allows controlling the DPLL modes" hexmask.long.word 0x58 16.--31. 1. "RESERVED," bitfld.long 0x58 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x58 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" rbitfld.long 0x58 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x58 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" rbitfld.long 0x58 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x58 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" bitfld.long 0x58 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" newline bitfld.long 0x58 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x58 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" newline bitfld.long 0x58 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" bitfld.long 0x58 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x5C "CM_IDLEST_DPLL_GPU,This register allows monitoring DPLL activity" hexmask.long 0x5C 5.--31. 1. "RESERVED," bitfld.long 0x5C 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x5C 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" bitfld.long 0x5C 0. "ST_DPLL_CLK,DPLL lock status" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x60 "CM_AUTOIDLE_DPLL_GPU,This register provides automatic control over the DPLL activity" hexmask.long 0x60 3.--31. 1. "RESERVED," bitfld.long 0x60 0.--2. "AUTO_DPLL_MODE,DPLL automatic control" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x64 "CM_CLKSEL_DPLL_GPU,This register provides controls over the DPLL" hexmask.long.byte 0x64 24.--31. 1. "RESERVED," bitfld.long 0x64 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x64 22. "DCC_EN,Duty-cycle corrector for high frequency clock" "DCC_EN_0,?" rbitfld.long 0x64 21. "RESERVED," "0,1" newline bitfld.long 0x64 20. "DPLL_CLKOUTHIF_CLKSEL,Selects the source of the DPLL CLKOUTHIF clock" "DPLL_CLKOUTHIF_CLKSEL_0,DPLL_CLKOUTHIF_CLKSEL_1" rbitfld.long 0x64 19. "RESERVED," "0,1" newline hexmask.long.word 0x64 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" rbitfld.long 0x64 7. "RESERVED," "0,1" newline hexmask.long.byte 0x64 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x68 "CM_DIV_M2_DPLL_GPU,This register provides controls over the M2 divider of the DPLL" hexmask.long.tbyte 0x68 10.--31. 1. "RESERVED," rbitfld.long 0x68 9. "CLKST,DPLL CLKOUT status" "CLKST_0,CLKST_1" newline rbitfld.long 0x68 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x68 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x6C "CM_DIV_M3_DPLL_GPU,This register provides controls over the M3 divider of the DPLL" hexmask.long.tbyte 0x6C 10.--31. 1. "RESERVED," rbitfld.long 0x6C 9. "CLKST,DPLL CLKOUTHIF status" "CLKST_0,CLKST_1" newline rbitfld.long 0x6C 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x6C 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x70 "CM_SSC_DELTAMSTEP_DPLL_GPU,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.word 0x70 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x70 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x74 "CM_SSC_MODFREQDIV_DPLL_GPU,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" hexmask.long.tbyte 0x74 11.--31. 1. "RESERVED," bitfld.long 0x74 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x74 7. "RESERVED," "0,1" hexmask.long.byte 0x74 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" width 0x0B tree.end tree "CKGEN_PRM" base ad:0x4AE06100 group.long 0x00++0x03 line.long 0x00 "CM_CLKSEL_SYSCLK1,Select the SYS CLK for SYSCLK1_32K_CLK" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1" group.long 0x08++0x33 line.long 0x00 "CM_CLKSEL_WKUPAON,Control the functional clock source of WKUPAON. PRM and Smart Reflex functional clock" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "CLKSEL,Select the clock source for WKUPAON_ICLK clock" "CLKSEL_0,CLKSEL_1" line.long 0x04 "CM_CLKSEL_ABE_PLL_REF,Control the source of the reference clock for DPLL_ABE" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "CLKSEL,Select the source for the DPLL_ABE reference clock" "CLKSEL_0,CLKSEL_1" line.long 0x08 "CM_CLKSEL_SYS,Software (ROM Code) sets the SYS_CLK configuration corresponding to the frequency of SYS_CLK" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 0.--2. "SYS_CLKSEL,System clock input selection" "SYS_CLKSEL_0,SYS_CLKSEL_1,SYS_CLKSEL_2,SYS_CLKSEL_3,SYS_CLKSEL_4,SYS_CLKSEL_5,SYS_CLKSEL_6,SYS_CLKSEL_7" line.long 0x0C "CM_CLKSEL_ABE_PLL_BYPAS,Control the source of the bypass clock for DPLL_ABE" hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "CLKSEL,Control the source of the bypass clock for DPLL_ABE" "CLKSEL_0,CLKSEL_1" line.long 0x10 "CM_CLKSEL_ABE_PLL_SYS,Control the source of the SYS clock for DPLL_ABE" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "CLKSEL,Select the SYS clock for the DPLL_ABE reference and bypass clock" "CLKSEL_0,CLKSEL_1" line.long 0x14 "CM_CLKSEL_ABE_24M,Select the ABE_24M_FCLK for TIMERS subsystems" hexmask.long 0x14 1.--31. 1. "RESERVED," bitfld.long 0x14 0. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1" line.long 0x18 "CM_CLKSEL_ABE_SYS,Select the ABE_SYS_CLK" hexmask.long 0x18 1.--31. 1. "RESERVED," bitfld.long 0x18 0. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1" line.long 0x1C "CM_CLKSEL_HDMI_MCASP_AUX,Select the SYS_CLK1 for MCASP modules" hexmask.long 0x1C 3.--31. 1. "RESERVED," bitfld.long 0x1C 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x20 "CM_CLKSEL_HDMI_TIMER,Select the SYS_CLK1 for TIMER subsystems" hexmask.long 0x20 3.--31. 1. "RESERVED," bitfld.long 0x20 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x24 "CM_CLKSEL_MCASP_SYS,Select the SYS CLK for ABE_24M_FCLK" hexmask.long 0x24 1.--31. 1. "RESERVED," bitfld.long 0x24 0. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1" line.long 0x28 "CM_CLKSEL_MLBP_MCASP,Select the MLBP_CLK for MCASP subsystems" hexmask.long 0x28 3.--31. 1. "RESERVED," bitfld.long 0x28 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x2C "CM_CLKSEL_MLB_MCASP,Select the SYS_CLK1 for MCASP" hexmask.long 0x2C 3.--31. 1. "RESERVED," bitfld.long 0x2C 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x30 "CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX,Select the L4_ICLK (SR2.0) for MCASP modules" hexmask.long 0x30 3.--31. 1. "RESERVED," bitfld.long 0x30 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" group.long 0x40++0x3B line.long 0x00 "CM_CLKSEL_SYS_CLK1_32K,Control the source of the FUNC_32K_CLK clock for GPIO. WD_TIMER. KBD. etc" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "CLKSEL,Select the FUNC_32K_CLK clock" "CLKSEL_0,CLKSEL_1" line.long 0x04 "CM_CLKSEL_TIMER_SYS,Select the TIMER_SYS_CLK for TIMER modules" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1" line.long 0x08 "CM_CLKSEL_VIDEO1_MCASP_AUX,Select the SYS_CLK1 for MCASP modules" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x0C "CM_CLKSEL_VIDEO1_TIMER,Select the SYS_CLK1 for TIMER subsystems" hexmask.long 0x0C 3.--31. 1. "RESERVED," bitfld.long 0x0C 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x10 "CM_CLKSEL_VIDEO2_MCASP_AUX,Select the SYS_CLK1 for MCASP modules" hexmask.long 0x10 3.--31. 1. "RESERVED," bitfld.long 0x10 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x14 "CM_CLKSEL_VIDEO2_TIMER,Select the SYS_CLK1 for TIMER subsystems" hexmask.long 0x14 3.--31. 1. "RESERVED," bitfld.long 0x14 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x18 "CM_CLKSEL_CLKOUTMUX0,Control the source of the CLKOUTMUX0" hexmask.long 0x18 5.--31. 1. "RESERVED," bitfld.long 0x18 0.--4. "CLKSEL,Select the source of" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15,CLKSEL_16,CLKSEL_17,CLKSEL_18,CLKSEL_19,CLKSEL_20,?,?,?,?,?,?,?,?,?,?,?" line.long 0x1C "CM_CLKSEL_CLKOUTMUX1,Control the source of the CLKOUTMUX1" hexmask.long 0x1C 5.--31. 1. "RESERVED," bitfld.long 0x1C 0.--4. "CLKSEL,Select the source of" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15,CLKSEL_16,CLKSEL_17,CLKSEL_18,CLKSEL_19,CLKSEL_20,CLKSEL_21,?,?,?,?,?,?,?,?,?,?" line.long 0x20 "CM_CLKSEL_CLKOUTMUX2,Control the source of the CLKOUTMUX2" hexmask.long 0x20 5.--31. 1. "RESERVED," bitfld.long 0x20 0.--4. "CLKSEL,Select the source of" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15,CLKSEL_16,CLKSEL_17,CLKSEL_18,CLKSEL_19,CLKSEL_20,CLKSEL_21,?,?,?,?,?,?,?,?,?,?" line.long 0x24 "CM_CLKSEL_HDMI_PLL_SYS,Control the source of the SYS clock for DPLL_HDMI" hexmask.long 0x24 1.--31. 1. "RESERVED," bitfld.long 0x24 0. "CLKSEL,Select the SYS clock for the DPLL_HDMI" "CLKSEL_0,CLKSEL_1" line.long 0x28 "CM_CLKSEL_VIDEO1_PLL_SYS,Control the source of the SYS clock for DPLL_VIDEO1" hexmask.long 0x28 1.--31. 1. "RESERVED," bitfld.long 0x28 0. "CLKSEL,Select the SYS clock for the DPLL_VIDEO1" "CLKSEL_0,CLKSEL_1" line.long 0x2C "CM_CLKSEL_VIDEO2_PLL_SYS,Control the source of the SYS clock for DPLL_VIDEO1" hexmask.long 0x2C 1.--31. 1. "RESERVED," bitfld.long 0x2C 0. "CLKSEL,Select the SYS clock for the DPLL_VIDEO2" "CLKSEL_0,CLKSEL_1" line.long 0x30 "CM_CLKSEL_ABE_CLK_DIV,Select the ABE_CLK" hexmask.long 0x30 3.--31. 1. "RESERVED," bitfld.long 0x30 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x34 "CM_CLKSEL_ABE_GICLK_DIV,Select the ABE_GICLK" hexmask.long 0x34 1.--31. 1. "RESERVED," bitfld.long 0x34 0. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1" line.long 0x38 "CM_CLKSEL_AESS_FCLK_DIV,Select the AESS_FCLK" hexmask.long 0x38 1.--31. 1. "RESERVED," bitfld.long 0x38 0. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1" group.long 0x80++0x63 line.long 0x00 "CM_CLKSEL_EVE_CLK,Controls the source of the EVE_CLK for EVE" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "CLKSEL,Selects the EVE_CLK for EVE" "CLKSEL_0,CLKSEL_1" line.long 0x04 "CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX,Select the USB_OTG_CLK" hexmask.long 0x04 3.--31. 1. "RESERVED," bitfld.long 0x04 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x08 "CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX,Select the CORE_DPLL_OUT_CLK" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x0C "CM_CLKSEL_DSP_GFCLK_CLKOUTMUX,Select the DSP_GFCLK" hexmask.long 0x0C 3.--31. 1. "RESERVED," bitfld.long 0x0C 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x10 "CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX,Select the EMIF_PHY_GCLK" hexmask.long 0x10 3.--31. 1. "RESERVED," bitfld.long 0x10 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x14 "CM_CLKSEL_EMU_CLK_CLKOUTMUX,Select the EMU_CLK" hexmask.long 0x14 3.--31. 1. "RESERVED," bitfld.long 0x14 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x18 "CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX,Select the FUNC_96M_AON_CLK" hexmask.long 0x18 3.--31. 1. "RESERVED," bitfld.long 0x18 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x1C "CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX,Select the GMAC_250M_CLK" hexmask.long 0x1C 3.--31. 1. "RESERVED," bitfld.long 0x1C 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x20 "CM_CLKSEL_GPU_GCLK_CLKOUTMUX,Select the GPU_GCLK" hexmask.long 0x20 3.--31. 1. "RESERVED," bitfld.long 0x20 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x24 "CM_CLKSEL_HDMI_CLK_CLKOUTMUX,Select the HDMI_CLK" hexmask.long 0x24 3.--31. 1. "RESERVED," bitfld.long 0x24 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x28 "CM_CLKSEL_IVA_GCLK_CLKOUTMUX,Select the IVA_GCLK" hexmask.long 0x28 3.--31. 1. "RESERVED," bitfld.long 0x28 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x2C "CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX,Select the L3INIT_480M_GFCLK" hexmask.long 0x2C 3.--31. 1. "RESERVED," bitfld.long 0x2C 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x30 "CM_CLKSEL_MPU_GCLK_CLKOUTMUX,Select the MPU_GCLK" hexmask.long 0x30 3.--31. 1. "RESERVED," bitfld.long 0x30 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x34 "CM_CLKSEL_PCIE1_CLK_CLKOUTMUX,Select the PCIE1_CLK" hexmask.long 0x34 3.--31. 1. "RESERVED," bitfld.long 0x34 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x38 "CM_CLKSEL_PCIE2_CLK_CLKOUTMUX,Select the PCIE2_CLK" hexmask.long 0x38 3.--31. 1. "RESERVED," bitfld.long 0x38 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x3C "CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX,Select the PER_ABE_X1_CLK" hexmask.long 0x3C 3.--31. 1. "RESERVED," bitfld.long 0x3C 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x40 "CM_CLKSEL_SATA_CLK_CLKOUTMUX,Select the SATA_CLK" hexmask.long 0x40 3.--31. 1. "RESERVED," bitfld.long 0x40 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x44 "CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX,Select the RCOSC_32K_CLK" hexmask.long 0x44 3.--31. 1. "RESERVED," bitfld.long 0x44 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x48 "CM_CLKSEL_SYS_CLK1_CLKOUTMUX,Select the SYS_CLK1" hexmask.long 0x48 3.--31. 1. "RESERVED," bitfld.long 0x48 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x4C "CM_CLKSEL_SYS_CLK2_CLKOUTMUX,Select the SYS_CLK2" hexmask.long 0x4C 3.--31. 1. "RESERVED," bitfld.long 0x4C 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x50 "CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX,Select the VIDEO1_CLK" hexmask.long 0x50 3.--31. 1. "RESERVED," bitfld.long 0x50 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x54 "CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX,Select the VIDEO2_CLK" hexmask.long 0x54 3.--31. 1. "RESERVED," bitfld.long 0x54 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x58 "CM_CLKSEL_ABE_LP_CLK,Select the ABE_LP_CLK" hexmask.long 0x58 1.--31. 1. "RESERVED," bitfld.long 0x58 0. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1" line.long 0x5C "CM_CLKSEL_ADC_GFCLK,Control the source of the ADC_GFCLK clock for" hexmask.long 0x5C 2.--31. 1. "RESERVED," bitfld.long 0x5C 0.--1. "CLKSEL,Select the SYS clock for the DPLL_ABE reference and bypass clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" line.long 0x60 "CM_CLKSEL_EVE_GFCLK_CLKOUTMUX,Select the EVE_GFCLK" hexmask.long 0x60 3.--31. 1. "RESERVED," bitfld.long 0x60 0.--2. "CLKSEL,Selects the divider value" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" width 0x0B tree.end tree "CLK1_DSP1_EDMA_BW_LIMITER" base ad:0x44804B00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_DSP1_MDMA_BW_LIMITER" base ad:0x44806A00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_DSP1_MDMA_BW_REGULATOR" base ad:0x44804C00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_DSP2_EDMA_BW_LIMITER" base ad:0x44804A00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_DSP2_MDMA_BW_LIMITER" base ad:0x44806B00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_DSP2_MDMA_BW_REGULATOR" base ad:0x44804D00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_EVE_TC0_BW_LIMITER" base ad:0x44806C00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_EVE_TC0_BW_REGULATOR" base ad:0x44804200 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_EVE_TC1_BW_LIMITER" base ad:0x44806D00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_EVE_TC1_BW_REGULATOR" base ad:0x44804600 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_FLAGMUX_CLK1" base ad:0x44805700 rgroup.long 0x00++0x0F line.long 0x00 "L3_FLAGMUX_TIMEOUT1_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_TIMEOUT1_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_TIMEOUT1_MASK0," hexmask.long.word 0x08 18.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x08 0.--17. 1. "MASK0,mask flag inputs 0 Type: Control" line.long 0x0C "L3_FLAGMUX_TIMEOUT1_REGERR0," hexmask.long.word 0x0C 18.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x0C 0.--17. 1. "REGERR0,flag inputs 0 Type: Status" rgroup.long 0x100++0x0F line.long 0x00 "L3_FLAGMUX_TIMEOUT2_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_TIMEOUT2_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_TIMEOUT2_MASK0," hexmask.long.word 0x08 16.--31. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "MASK0,mask flag inputs 0 Type: Control" line.long 0x0C "L3_FLAGMUX_TIMEOUT2_REGERR0," hexmask.long.word 0x0C 16.--31. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--15. 1. "REGERR0,flag inputs 0 Type: Status" width 0x0B tree.end tree "CLK1_FLAGMUX_CLK1_1" base ad:0x44803500 rgroup.long 0x00++0x17 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_MASK0," hexmask.long.word 0x08 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x08 0.--19. 1. "MASK0,Mask flag inputs 0 Type: Control" line.long 0x0C "L3_FLAGMUX_REGERR0," line.long 0x10 "L3_FLAGMUX_MASK1," hexmask.long.word 0x10 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x10 0.--19. 1. "MASK1,Mask flag inputs 1 Type: Control" line.long 0x14 "L3_FLAGMUX_REGERR1," width 0x0B tree.end tree "CLK1_FLAGMUX_CLK1_2" base ad:0x44803600 rgroup.long 0x00++0x17 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_MASK0," hexmask.long.word 0x08 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x08 0.--19. 1. "MASK0,Mask flag inputs 0 Type: Control" line.long 0x0C "L3_FLAGMUX_REGERR0," line.long 0x10 "L3_FLAGMUX_MASK1," hexmask.long.word 0x10 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x10 0.--19. 1. "MASK1,Mask flag inputs 1 Type: Control" line.long 0x14 "L3_FLAGMUX_REGERR1," width 0x0B tree.end tree "CLK1_FLAGMUX_CLK1MERGE" base ad:0x44800400 rgroup.long 0x00++0x17 line.long 0x00 "L3_FLAGMUX_CLK1MERGE_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_CLK1MERGE_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_CLK1MERGE_MASK0," hexmask.long 0x08 2.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--1. "MASK0,Mask flag inputs 0 Type: Control" "0,1,2,3" line.long 0x0C "L3_FLAGMUX_CLK1MERGE_REGERR0," hexmask.long 0x0C 2.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--1. "REGERR0,Flag inputs 0 Type: Control" "0,1,2,3" line.long 0x10 "L3_FLAGMUX_CLK1MERGE_MASK1," hexmask.long 0x10 2.--31. 1. "RESERVED," newline bitfld.long 0x10 0.--1. "MASK1,Mask flag inputs 0 Type: Control" "0,1,2,3" line.long 0x14 "L3_FLAGMUX_CLK1MERGE_REGERR1," hexmask.long 0x14 2.--31. 1. "RESERVED," newline bitfld.long 0x14 0.--1. "REGERR1,Flag inputs 0 Type: Control" "0,1,2,3" width 0x0B tree.end tree "CLK1_GMAC_SW_BW_REGULATOR" base ad:0x44805600 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_HOST_CLK1_1" base ad:0x44000000 rgroup.long 0x00++0x0B line.long 0x00 "L3_HOST_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_HOST_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_HOST_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 3.--31. 1. "RESERVED," newline bitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Fault is asserted when the Fault Control register field indicates a Fault and de-asserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0.--1. "RESERVED," "0,1,2,3" group.long 0x40++0x37 line.long 0x00 "L3_HOST_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_HOST_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED," newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED," newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_HOST_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_HOST_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_HOST_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_HOST_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_HOST_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_HOST_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED," newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,Type: Status" line.long 0x28 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Type: Status" line.long 0x2C "L3_HOST_STDERRLOG_CUSTOMINFO_WR," hexmask.long 0x2C 1.--31. 1. "RESERVED," newline bitfld.long 0x2C 0. "STDERRLOG_CUSTOMINFO_WR,Type: Status" "0,1" line.long 0x30 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR," hexmask.long.word 0x30 21.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x30 0.--20. 1. "STDERRLOG_CUSTOMINFO_ADDR,Type: Status" line.long 0x34 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR," hexmask.long 0x34 1.--31. 1. "RESERVED," newline bitfld.long 0x34 0. "STDERRLOG_CUSTOMINFO_DECERR,Type: Status" "0,1" width 0x0B tree.end tree "CLK1_HOST_CLK1_2" base ad:0x44800000 rgroup.long 0x00++0x0B line.long 0x00 "L3_HOST_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_HOST_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_HOST_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 3.--31. 1. "RESERVED," newline bitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Fault is asserted when the Fault Control register field indicates a Fault and de-asserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0.--1. "RESERVED," "0,1,2,3" group.long 0x40++0x37 line.long 0x00 "L3_HOST_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_HOST_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED," newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED," newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_HOST_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_HOST_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_HOST_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_HOST_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_HOST_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_HOST_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED," newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,Type: Status" line.long 0x28 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Type: Status" line.long 0x2C "L3_HOST_STDERRLOG_CUSTOMINFO_WR," hexmask.long 0x2C 1.--31. 1. "RESERVED," newline bitfld.long 0x2C 0. "STDERRLOG_CUSTOMINFO_WR,Type: Status" "0,1" line.long 0x30 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR," hexmask.long.word 0x30 21.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x30 0.--20. 1. "STDERRLOG_CUSTOMINFO_ADDR,Type: Status" line.long 0x34 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR," hexmask.long 0x34 1.--31. 1. "RESERVED," newline bitfld.long 0x34 0. "STDERRLOG_CUSTOMINFO_DECERR,Type: Status" "0,1" width 0x0B tree.end tree "CLK1_IPU_BW_LIMITER" base ad:0x44803C00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_IPU_BW_REGULATOR" base ad:0x44804E00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_ISS_NRT1_BW_LIMITER" base ad:0x44806F00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_ISS_NRT2_BW_LIMITER" base ad:0x44806E00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_MMU_BW_LIMITER" base ad:0x44803A00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_TPTC1_RD_BW_LIMITER" base ad:0x44807000 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_TPTC1_WR_BW_LIMITER" base ad:0x44807100 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_TPTC2_RD_BW_LIMITER" base ad:0x44807200 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_TPTC2_WR_BW_LIMITER" base ad:0x44807300 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," hexmask.long 0x08 5.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK2_FLAGMUX_CLK2" base ad:0x45000400 rgroup.long 0x00++0x0F line.long 0x00 "L3_FLAGMUX_TIMEOUT_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_TIMEOUT_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_TIMEOUT_MASK0," hexmask.long 0x08 2.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--1. "MASK0,mask flag inputs 0 Type: Control" "0,1,2,3" line.long 0x0C "L3_FLAGMUX_TIMEOUT_REGERR0," hexmask.long 0x0C 2.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--1. "REGERR0,flag inputs 0 Type: Status" "0,1,2,3" width 0x0B tree.end tree "CLK2_FLAGMUX_CLK2_1" base ad:0x45000200 rgroup.long 0x00++0x17 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_MASK0," hexmask.long.word 0x08 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x08 0.--19. 1. "MASK0,Mask flag inputs 0 Type: Control" line.long 0x0C "L3_FLAGMUX_REGERR0," line.long 0x10 "L3_FLAGMUX_MASK1," hexmask.long.word 0x10 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x10 0.--19. 1. "MASK1,Mask flag inputs 1 Type: Control" line.long 0x14 "L3_FLAGMUX_REGERR1," width 0x0B tree.end tree "CLK2_FLAGMUX_STATCOLL" base ad:0x45000500 group.long 0x00++0x0F line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_STCOL_MASK0," hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," newline hexmask.long.word 0x08 0.--9. 1. "MASK0,mask flag inputs 0 Type: Control" line.long 0x0C "L3_STCOL_REGERR0," hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--9. 1. "REGERR0,flag inputs 0 Type: Status" width 0x0B tree.end tree "CLK2_HOST_CLK2_1" base ad:0x45000000 rgroup.long 0x00++0x0B line.long 0x00 "L3_HOST_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_HOST_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_HOST_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 3.--31. 1. "RESERVED," newline bitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Fault is asserted when the Fault Control register field indicates a Fault and de-asserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0.--1. "RESERVED," "0,1,2,3" group.long 0x40++0x37 line.long 0x00 "L3_HOST_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_HOST_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED," newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED," newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_HOST_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_HOST_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_HOST_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_HOST_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_HOST_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_HOST_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED," newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,Type: Status" line.long 0x28 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Type: Status" line.long 0x2C "L3_HOST_STDERRLOG_CUSTOMINFO_WR," hexmask.long 0x2C 1.--31. 1. "RESERVED," newline bitfld.long 0x2C 0. "STDERRLOG_CUSTOMINFO_WR,Type: Status" "0,1" line.long 0x30 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR," hexmask.long.word 0x30 21.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x30 0.--20. 1. "STDERRLOG_CUSTOMINFO_ADDR,Type: Status" line.long 0x34 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR," hexmask.long 0x34 1.--31. 1. "RESERVED," newline bitfld.long 0x34 0. "STDERRLOG_CUSTOMINFO_DECERR,Type: Status" "0,1" width 0x0B tree.end repeat 4. (list 1. 3. 2. 4. )(list ad:0x45002000 ad:0x45003000 ad:0x45004000 ad:0x45005000 ) tree "CLK2_STATCOLL$1" base $2 group.long 0x00++0x2F line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_STCOL_EN," hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x08 0. "EN,Enable performance monitoring this will also shut down the clock if En = 0 Type: Control" "0,1" line.long 0x0C "L3_STCOL_SOFTEN," hexmask.long 0x0C 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 0. "SOFTEN,Software enable for performance monitoring Type: Control" "0,1" line.long 0x10 "L3_STCOL_IGNORESUSPEND," hexmask.long 0x10 1.--31. 1. "RESERVED," newline bitfld.long 0x10 0. "IGNORESUSPEND,Ignore suspend if set to one for suspend mechanism Type: Control" "0,1" line.long 0x14 "L3_STCOL_TRIGEN," hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "TRIGEN,TrigEn when set it enable the external trigger start and stop Type: Control" "0,1" line.long 0x18 "L3_STCOL_REQEVT," hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x18 0.--3. "REQEVT,Req event select Type: Control" "REQEVT_0,REQEVT_1,REQEVT_2,REQEVT_3,REQEVT_4,REQEVT_5,REQEVT_6,REQEVT_7,REQEVT_8,?,?,?,?,?,?,?" line.long 0x1C "L3_STCOL_RSPEVT," hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 0.--3. "RSPEVT,Rsp event select Type: Control" "RSPEVT_0,RSPEVT_1,RSPEVT_2,RSPEVT_3,RSPEVT_4,RSPEVT_5,RSPEVT_6,RSPEVT_7,RSPEVT_8,?,?,?,?,?,?,?" line.long 0x20 "L3_STCOL_EVTMUX_SEL0," hexmask.long 0x20 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0.--2. "EVTMUX_SEL0,The select of the mux 0 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x24 "L3_STCOL_EVTMUX_SEL1," hexmask.long 0x24 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x24 0.--2. "EVTMUX_SEL1,The select of the mux 1 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x28 "L3_STCOL_EVTMUX_SEL2," hexmask.long 0x28 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x28 0.--2. "EVTMUX_SEL2,The select of the mux 2 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x2C "L3_STCOL_EVTMUX_SEL3," hexmask.long 0x2C 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--2. "EVTMUX_SEL3,The select of the mux 3 Type: Control" "0,1,2,3,4,5,6,7" rgroup.long 0x40++0x3B line.long 0x00 "L3_STCOL_DUMP_IDENTIFIER," hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--3. "DUMP_IDENTIFIER,Probe identifier Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "L3_STCOL_DUMP_COLLECTTIME," line.long 0x08 "L3_STCOL_DUMP_SLVADDR," hexmask.long 0x08 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x08 0.--6. 1. "DUMP_SLVADDR,Dump slave address Type: Control" line.long 0x0C "L3_STCOL_DUMP_MSTADDR," hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0C 0.--7. 1. "DUMP_MSTADDR,Dump master address Type: Control" line.long 0x10 "L3_STCOL_DUMP_SLVOFS," line.long 0x14 "L3_STCOL_DUMP_MODE," hexmask.long 0x14 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 1. "DUMP_MODE_CONDITIONAL,Define the stat conditional dump if one a dump will be generated when alarm is trigged Type: Control" "0,1" newline bitfld.long 0x14 0. "DUMP_MODE_MANUAL,Define the dump mode: if != 0 the dump is controlled by the Send register" "0,1" line.long 0x18 "L3_STCOL_DUMP_SEND," hexmask.long 0x18 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x18 0. "DUMP_SEND,In manual mode is used to send the dump content and initialize the counters" "0,1" line.long 0x1C "L3_STCOL_DUMP_DISABLE," hexmask.long 0x1C 1.--31. 1. "RESERVED," newline bitfld.long 0x1C 0. "DUMP_DISABLE,If 1 the dump frame will be disabled but counters still active.This is typically used when counters monitoring is enabled Type: Control" "0,1" line.long 0x20 "L3_STCOL_DUMP_ALARM_TRIG," hexmask.long 0x20 1.--31. 1. "RESERVED," newline bitfld.long 0x20 0. "DUMP_ALARM_TRIG,In Alarm Mode is used to reset Alarm Type: Take" "0,1" line.long 0x24 "L3_STCOL_DUMP_ALARM_MINVAL," line.long 0x28 "L3_STCOL_DUMP_ALARM_MAXVAL," line.long 0x2C "L3_STCOL_DUMP_ALARM_MODE0," hexmask.long 0x2C 2.--31. 1. "RESERVED," newline bitfld.long 0x2C 0.--1. "DUMP_ALARM_MODE0,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE0_0,DUMP_ALARM_MODE0_1,DUMP_ALARM_MODE0_2,DUMP_ALARM_MODE0_3" line.long 0x30 "L3_STCOL_DUMP_ALARM_MODE1," hexmask.long 0x30 2.--31. 1. "RESERVED," newline bitfld.long 0x30 0.--1. "DUMP_ALARM_MODE1,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE1_0,DUMP_ALARM_MODE1_1,DUMP_ALARM_MODE1_2,DUMP_ALARM_MODE1_3" line.long 0x34 "L3_STCOL_DUMP_ALARM_MODE2," hexmask.long 0x34 2.--31. 1. "RESERVED," newline bitfld.long 0x34 0.--1. "DUMP_ALARM_MODE2,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE2_0,DUMP_ALARM_MODE2_1,DUMP_ALARM_MODE2_2,DUMP_ALARM_MODE2_3" line.long 0x38 "L3_STCOL_DUMP_ALARM_MODE3," hexmask.long 0x38 2.--31. 1. "RESERVED," newline bitfld.long 0x38 0.--1. "DUMP_ALARM_MODE3,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE3_0,DUMP_ALARM_MODE3_1,DUMP_ALARM_MODE3_2,DUMP_ALARM_MODE3_3" group.long 0xAC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_0," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x204++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_1," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x35C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_2," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x4B4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_3," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0xB0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_0," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x208++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_1," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x360++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_2," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x4B8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_3," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0xB4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_0," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x20C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_1," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x364++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_2," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x4BC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_3," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0xB8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_0," hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x210++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_1," hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x368++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_2," hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x4C0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_3," hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0xBC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN0_0," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x214++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN0_1," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x36C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN0_2," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x4C4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN0_3," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0xC0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_RD_0," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x218++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_RD_1," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x370++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_RD_2," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x4C8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_RD_3," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xC4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_WR_0," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x21C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_WR_1," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x374++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_WR_2," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x4CC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_WR_3," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xC8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_MSTADDR_0," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK0_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x220++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_MSTADDR_1," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK0_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x378++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_MSTADDR_2," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK0_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x4D0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_MSTADDR_3," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK0_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xCC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_SLVADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK0_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x224++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_SLVADDR_1," hexmask.long 0x00 7.--31. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK0_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x37C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_SLVADDR_2," hexmask.long 0x00 7.--31. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK0_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x4D4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_SLVADDR_3," hexmask.long 0x00 7.--31. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK0_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0xD0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_ERR_0," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x228++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_ERR_1," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x380++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_ERR_2," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x4D8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_ERR_3," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MASK0_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xD4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_REQUSERINFO_0," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK0_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0x22C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_REQUSERINFO_1," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK0_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0x384++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_REQUSERINFO_2," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK0_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0x4DC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_REQUSERINFO_3," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK0_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0xD8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_RSPUSERINFO_0," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "FILTER_i_MASK0_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x230++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_RSPUSERINFO_1," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "FILTER_i_MASK0_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x388++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_RSPUSERINFO_2," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "FILTER_i_MASK0_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x4E0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK0_RSPUSERINFO_3," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "FILTER_i_MASK0_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xE0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_RD_0," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x238++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_RD_1," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x390++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_RD_2," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x4E8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_RD_3," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xE4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_WR_0," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x23C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_WR_1," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x394++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_WR_2," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x4EC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_WR_3," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xE8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_MSTADDR_0," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH0_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x240++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_MSTADDR_1," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH0_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x398++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_MSTADDR_2," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH0_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x4F0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_MSTADDR_3," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH0_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xEC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_SLVADDR_0," hexmask.long 0x00 5.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x244++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_SLVADDR_1," hexmask.long 0x00 5.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x39C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_SLVADDR_2," hexmask.long 0x00 5.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4F4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_SLVADDR_3," hexmask.long 0x00 5.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xF0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_ERR_0," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x248++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_ERR_1," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x3A0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_ERR_2," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x4F8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_ERR_3," hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "FILTER_i_MATCH0_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xF4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_REQUSERINFO_0," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK0_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0x24C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_REQUSERINFO_1," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK0_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0x3A4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_REQUSERINFO_2," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK0_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0x4FC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_REQUSERINFO_3," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK0_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0xF8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_RSPUSERINFO_0," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "FILTER_i_MASK0_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x250++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_RSPUSERINFO_1," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "FILTER_i_MASK0_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x3A8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_RSPUSERINFO_2," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "FILTER_i_MASK0_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x500++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH0_RSPUSERINFO_3," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "FILTER_i_MASK0_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x1F0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0," hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" group.long 0x348++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_1," hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" group.long 0x4A0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_2," hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" group.long 0x5F8++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_3," hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" group.long 0x1F4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0," hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x34C++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_1," hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x4A4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_2," hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x5FC++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_3," hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x1F8++0x03 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_0," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" group.long 0x350++0x03 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_1," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" group.long 0x4A8++0x03 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_2," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" group.long 0x600++0x03 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_3," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" group.long 0x1FC++0x03 line.long 0x00 "L3_STCOL_OP_i_SEL_0," hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x354++0x03 line.long 0x00 "L3_STCOL_OP_i_SEL_1," hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x4AC++0x03 line.long 0x00 "L3_STCOL_OP_i_SEL_2," hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x604++0x03 line.long 0x00 "L3_STCOL_OP_i_SEL_3," hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C ) rgroup.long ($2+0x8C)++0x03 line.long 0x00 "L3_STCOL_DUMP_CNT$1," repeat.end width 0x0B tree.end repeat.end tree "CM_CORE_AON_TARG" base ad:0x4A006000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CM_CORE_TARG" base ad:0x4A00A000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CORE_CM_CORE" base ad:0x4A008700 group.long 0x00++0x03 line.long 0x00 "CM_L3MAIN1_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline rbitfld.long 0x00 9. "CLKACTIVITY_L3MAIN1_L4_GICLK,This field indicates the state of the L3MAIN1_L4_GICLK clock in the domain" "CLKACTIVITY_L3MAIN1_L4_GICLK_0,CLKACTIVITY_L3MAIN1_L4_GICLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_L3MAIN1_L3_GICLK,This field indicates the state of the L3MAIN1_L3_GICLK clock in the domain" "CLKACTIVITY_L3MAIN1_L3_GICLK_0,CLKACTIVITY_L3MAIN1_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L3MAIN1 clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x08++0x03 line.long 0x00 "CM_L3MAIN1_DYNAMICDEP,This register controls the dynamic domain depedencies from L3MAIN1 domain towards 'target' domains" rbitfld.long 0x00 31. "EVE4_DYNDEP,Dynamic dependency towards EVE4 clock domain" "?,EVE4_DYNDEP_1" newline rbitfld.long 0x00 30. "EVE3_DYNDEP,Dynamic dependency towards EVE3 clock domain" "?,EVE3_DYNDEP_1" newline rbitfld.long 0x00 29. "EVE2_DYNDEP,Dynamic dependency towards EVE2 clock domain" "?,EVE2_DYNDEP_1" newline rbitfld.long 0x00 28. "EVE1_DYNDEP,Dynamic dependency towards EVE1 clock domain" "?,EVE1_DYNDEP_1" newline bitfld.long 0x00 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 23. "L4PER3_DYNDEP,Dynamic dependency towards L4PER3 clock domain" "?,L4PER3_DYNDEP_1" newline rbitfld.long 0x00 22. "L4PER2_DYNDEP,Dynamic dependency towards L4PER2 clock domain" "?,L4PER2_DYNDEP_1" newline rbitfld.long 0x00 21. "PCIE_DYNDEP,Dynamic dependency towards PCIE clock domain" "?,PCIE_DYNDEP_1" newline rbitfld.long 0x00 20. "DSP2_DYNDEP,Dynamic dependency towards DSP2 clock domain" "?,DSP2_DYNDEP_1" newline rbitfld.long 0x00 19. "RESERVED," "0,1" newline rbitfld.long 0x00 18. "IPU1_DYNDEP,Dynamic dependency towards IPU1 clock domain" "?,IPU1_DYNDEP_1" newline rbitfld.long 0x00 16.--17. "RESERVED," "0,1,2,3" newline rbitfld.long 0x00 15. "WKUPAON_DYNDEP,Dynamic dependency towards WKUPAON clock domain" "?,WKUPAON_DYNDEP_1" newline rbitfld.long 0x00 14. "L4SEC_DYNDEP,Dynamic dependency towards L4SEC clock domain" "?,L4SEC_DYNDEP_1" newline rbitfld.long 0x00 13. "L4PER_DYNDEP,Dynamic dependency towards L4PER1 clock domain" "?,L4PER_DYNDEP_1" newline rbitfld.long 0x00 12. "L4CFG_DYNDEP,Dynamic dependency towards L4CFG clock domain" "?,L4CFG_DYNDEP_1" newline rbitfld.long 0x00 11. "RESERVED," "0,1" newline rbitfld.long 0x00 10. "GPU_DYNDEP,Dynamic dependency towards GPU clock domain" "?,GPU_DYNDEP_1" newline rbitfld.long 0x00 9. "RESERVED," "0,1" newline rbitfld.long 0x00 8. "DSS_DYNDEP,Dynamic dependency towards DSS clock domain" "?,DSS_DYNDEP_1" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4. "EMIF_DYNDEP,Dynamic dependency towards EMIF clock domain" "?,EMIF_DYNDEP_1" newline rbitfld.long 0x00 3. "IPU_DYNDEP,Dynamic dependency towards IPU clock domain" "?,IPU_DYNDEP_1" newline rbitfld.long 0x00 2. "IVA_DYNDEP,Dynamic dependency towards IVA clock domain" "?,IVA_DYNDEP_1" newline rbitfld.long 0x00 1. "DSP1_DYNDEP,Dynamic dependency towards DSP1 clock domain" "?,DSP1_DYNDEP_1" newline rbitfld.long 0x00 0. "IPU2_DYNDEP,Dynamic dependency towards IPU2 clock domain" "?,IPU2_DYNDEP_1" rgroup.long 0x20++0x03 line.long 0x00 "CM_L3MAIN1_L3_MAIN_1_CLKCTRL,This register manages the L3_MAIN_1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x28++0x03 line.long 0x00 "CM_L3MAIN1_GPMC_CLKCTRL,This register manages the GPMC clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x30++0x03 line.long 0x00 "CM_L3MAIN1_MMU_EDMA_CLKCTRL,This register manages the MMU_L4_EDMA clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x48++0x03 line.long 0x00 "CM_L3MAIN1_MMU_PCIESS_CLKCTRL,This register manages the MMU_L4_PCIESS clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x50++0x03 line.long 0x00 "CM_L3MAIN1_OCMC_RAM1_CLKCTRL,This register manages the OCMC_RAM1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x58++0x03 line.long 0x00 "CM_L3MAIN1_TESOC_CLKCTRL,This register manages the TESOC clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x60++0x03 line.long 0x00 "CM_L3MAIN1_OCMC_RAM3_CLKCTRL,This register manages the OCMC_RAM3 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x68++0x03 line.long 0x00 "CM_L3MAIN1_OCMC_ROM_CLKCTRL,This register manages the OCMC_RAM clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x70++0x03 line.long 0x00 "CM_L3MAIN1_TPCC_CLKCTRL,This register manages the TPCC clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x78++0x03 line.long 0x00 "CM_L3MAIN1_TPTC1_CLKCTRL,This register manages the TPTC1 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x80++0x03 line.long 0x00 "CM_L3MAIN1_TPTC2_CLKCTRL,This register manages the TPTC2 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x88++0x03 line.long 0x00 "CM_L3MAIN1_VCP1_CLKCTRL,This register manages the VCP1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x90++0x03 line.long 0x00 "CM_L3MAIN1_VCP2_CLKCTRL,This register manages the VCP2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x98++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_CME_CLKCTRL,This register manages the SPARE_CME clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xA0++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_HDMI_CLKCTRL,This register manages the SPARE_HDMI clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xA8++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_ICM_CLKCTRL,This register manages the SPARE_ICM clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xB0++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_IVA2_CLKCTRL,This register manages the SPARE_IVA2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xB8++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_SATA2_CLKCTRL,This register manages the SPARE_SATA2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xC0++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL,This register manages the SPARE_UNKNOWN4 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xC8++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL,This register manages the SPARE_UNKNOWN5 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xD0++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL,This register manages the SPARE_UNKNOWN6 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xD8++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL,This register manages the SPARE_VIDEOPLL1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xF0++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL,This register manages the SPARE_VIDEOPLL2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xF8++0x03 line.long 0x00 "CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL,This register manages the SPARE_VIDEOPLL3 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x200++0x0B line.long 0x00 "CM_IPU2_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline rbitfld.long 0x00 8. "CLKACTIVITY_IPU2_GFCLK,This field indicates the state of the IPU2_GCLK clock in the domain" "CLKACTIVITY_IPU2_GFCLK_0,CLKACTIVITY_IPU2_GFCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the IPU2 clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_IPU2_STATICDEP,This register controls the static domain depedencies from IPU domain towards 'target' domains" rbitfld.long 0x04 31. "RESERVED," "0,1" newline bitfld.long 0x04 30. "CRC_STATDEP,Static dependency towards CRC clock domain" "CRC_STATDEP_0,CRC_STATDEP_1" newline bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE clock domain" "PCIE_STATDEP_0,PCIE_STATDEP_1" newline bitfld.long 0x04 28. "ISS_STATDEP,Static dependency towards ISS clock domain" "ISS_STATDEP_0,ISS_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain" "GMAC_STATDEP_0,GMAC_STATDEP_1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" newline bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain" "EVE1_STATDEP_0,EVE1_STATDEP_1" newline bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain" "CUSTEFUSE_STATDEP_0,?" newline rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 11. "SDMA_STATDEP,Static dependency towards DMA clock domain" "SDMA_STATDEP_0,?" newline bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU clock domain" "GPU_STATDEP_0,GPU_STATDEP_1" newline rbitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain" "CAM_STATDEP_0,?" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline rbitfld.long 0x04 6. "RESERVED," "0,1" newline bitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "L3MAIN1_STATDEP_0,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP clock domain" "DSP1_STATDEP_0,DSP1_STATDEP_1" newline rbitfld.long 0x04 0. "RESERVED," "0,1" line.long 0x08 "CM_IPU2_DYNAMICDEP,This register controls the dynamic domain depedencies from IPU domain towards 'target' domains" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 10.--23. 1. "RESERVED," newline rbitfld.long 0x08 9. "CAM_DYNDEP,Dynamic dependency towards CAM clock domain" "CAM_DYNDEP_0,?" newline rbitfld.long 0x08 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x220++0x03 line.long 0x00 "CM_IPU2_IPU2_CLKCTRL,This register manages the IPU2 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x300++0x0B line.long 0x00 "CM_DMA_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline rbitfld.long 0x00 8. "CLKACTIVITY_DMA_L3_GICLK,This field indicates the state of the DMA_L3_GICLK clock in the domain" "CLKACTIVITY_DMA_L3_GICLK_0,CLKACTIVITY_DMA_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DMA clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_DMA_STATICDEP,This register controls the static domain depedencies from DMA domain towards 'target' domains" rbitfld.long 0x04 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE clock domain" "PCIE_STATDEP_0,PCIE_STATDEP_1" newline rbitfld.long 0x04 28. "RESERVED," "0,1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline rbitfld.long 0x04 25. "RESERVED," "0,1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline hexmask.long.byte 0x04 16.--22. 1. "RESERVED," newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 10.--11. "RESERVED," "0,1,2,3" newline rbitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain" "CAM_STATDEP_0,?" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline rbitfld.long 0x04 6. "RESERVED," "0,1" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline rbitfld.long 0x04 1. "RESERVED," "0,1" newline bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_DMA_DYNAMICDEP,This register controls the dynamic domain depedencies from SDMA domain towards 'target' domains" hexmask.long 0x08 6.--31. 1. "RESERVED," newline bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "L3MAIN1_DYNDEP_0,?" newline bitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x320++0x03 line.long 0x00 "CM_DMA_DMA_SYSTEM_CLKCTRL,This register manages the DMA_SYSTEM clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x400++0x03 line.long 0x00 "CM_EMIF_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," newline rbitfld.long 0x00 10. "CLKACTIVITY_EMIF_PHY_GCLK,This field indicates the state of the EMIF_PHY_GCLK clock in the domain" "CLKACTIVITY_EMIF_PHY_GCLK_0,CLKACTIVITY_EMIF_PHY_GCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_EMIF_DLL_GCLK,This field indicates the state of the DLL_GCLK clock in the domain" "CLKACTIVITY_EMIF_DLL_GCLK_0,CLKACTIVITY_EMIF_DLL_GCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_EMIF_L3_GICLK,This field indicates the state of the EMIF_L3_GICLK clock in the domain" "CLKACTIVITY_EMIF_L3_GICLK_0,CLKACTIVITY_EMIF_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the EMIF clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" rgroup.long 0x420++0x03 line.long 0x00 "CM_EMIF_DMM_CLKCTRL,This register manages the DMM clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x428++0x03 line.long 0x00 "CM_EMIF_EMIF_OCP_FW_CLKCTRL,This register manages the EMIF_OCP_FW clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x430++0x03 line.long 0x00 "CM_EMIF_EMIF1_CLKCTRL,This register manages the EMIF1 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," newline rbitfld.long 0x00 24. "CLKSEL_LL,Source of EMIF1 External Low Latency interface clock EMIF_LL_GCLK Value is provided by LLI_C2C_SELECT input pin" "CLKSEL_LL_0,CLKSEL_LL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x438++0x03 line.long 0x00 "CM_EMIF_EMIF2_CLKCTRL,This register manages the EMIF2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x440++0x03 line.long 0x00 "CM_EMIF_EMIF_DLL_CLKCTRL,This register manages the DLL clock" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_DLL_CLK,Optional functional clock control" "OPTFCLKEN_DLL_CLK_0,OPTFCLKEN_DLL_CLK_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0x500++0x03 line.long 0x00 "CM_CRC_CRC_CLKCTRL,This register manages the CRC clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 26.--27. "CLKSEL_SOURCE2,Selects source for CRC clock" "CLKSEL_SOURCE2_0,CLKSEL_SOURCE2_1,CLKSEL_SOURCE2_2,CLKSEL_SOURCE2_3" newline bitfld.long 0x00 24.--25. "CLKSEL_SOURCE1,Selects source for CRC clock" "CLKSEL_SOURCE1_0,CLKSEL_SOURCE1_1,CLKSEL_SOURCE1_2,CLKSEL_SOURCE1_3" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x520++0x03 line.long 0x00 "CM_CRC_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline rbitfld.long 0x00 9. "CLKACTIVITY_CRC_GFCLK,This field indicates the state of the CRC_GFCLK clock in the domain" "CLKACTIVITY_CRC_GFCLK_0,CLKACTIVITY_CRC_GFCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_CRC_L3_GICLK,This field indicates the state of the CRC_L3_GICLK clock in the domain" "CLKACTIVITY_CRC_L3_GICLK_0,CLKACTIVITY_CRC_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the C2C clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x600++0x03 line.long 0x00 "CM_L4CFG_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline rbitfld.long 0x00 9. "CLKACTIVITY_L4CFG_L3_GICLK,This field indicates the state of the L4CFG_L3_GICLK clock in the domain" "CLKACTIVITY_L4CFG_L3_GICLK_0,CLKACTIVITY_L4CFG_L3_GICLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_L4CFG_L4_GICLK,This field indicates the state of the L4CFG_L4_GICLK clock in the domain" "CLKACTIVITY_L4CFG_L4_GICLK_0,CLKACTIVITY_L4CFG_L4_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4CFG clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x608++0x03 line.long 0x00 "CM_L4CFG_DYNAMICDEP,This register controls the dynamic domain depedencies from L4CFG domain towards 'target' domains" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 19. "MPU_DYNDEP,Dynamic dependency towards MPU clock domain" "?,MPU_DYNDEP_1" newline rbitfld.long 0x00 18. "RESERVED," "0,1" newline rbitfld.long 0x00 17. "CUSTEFUSE_DYNDEP,Dynamic dependency towards CUSTEFUSE clock domain" "?,CUSTEFUSE_DYNDEP_1" newline rbitfld.long 0x00 16. "COREAON_DYNDEP,Dynamic dependency towards COREAON clock domain" "?,COREAON_DYNDEP_1" newline rbitfld.long 0x00 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 11. "SDMA_DYNDEP,Dynamic dependency towards DMA clock domain" "?,SDMA_DYNDEP_1" newline rbitfld.long 0x00 8.--10. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "L3INIT_DYNDEP,Dynamic dependency towards L3INIT clock domain" "?,L3INIT_DYNDEP_1" newline rbitfld.long 0x00 6. "RESERVED," "0,1" newline rbitfld.long 0x00 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x00 4. "EMIF_DYNDEP,Dynamic dependency towards EMIF clock domain" "?,EMIF_DYNDEP_1" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x620++0x03 line.long 0x00 "CM_L4CFG_L4_CFG_CLKCTRL,This register manages the L4_CFG clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x628++0x03 line.long 0x00 "CM_L4CFG_SPINLOCK_CLKCTRL,This register manages the SPINLOCK clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x630++0x03 line.long 0x00 "CM_L4CFG_MAILBOX1_CLKCTRL,This register manages the MAILBOX1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x638++0x03 line.long 0x00 "CM_L4CFG_SAR_ROM_CLKCTRL,This register manages the SAR_ROM clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x640++0x03 line.long 0x00 "CM_L4CFG_OCP2SCP2_CLKCTRL,This register manages the OCP2SCP2 clocks and the optional clock of USB PHY" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x648++0x03 line.long 0x00 "CM_L4CFG_MAILBOX2_CLKCTRL,This register manages the MAILBOX2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x650++0x03 line.long 0x00 "CM_L4CFG_MAILBOX3_CLKCTRL,This register manages the MAILBOX3 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x658++0x03 line.long 0x00 "CM_L4CFG_MAILBOX4_CLKCTRL,This register manages the MAILBOX4 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x660++0x03 line.long 0x00 "CM_L4CFG_MAILBOX5_CLKCTRL,This register manages the MAILBOX5 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x668++0x03 line.long 0x00 "CM_L4CFG_MAILBOX6_CLKCTRL,This register manages the MAILBOX6 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x670++0x03 line.long 0x00 "CM_L4CFG_MAILBOX7_CLKCTRL,This register manages the MAILBOX7 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x678++0x03 line.long 0x00 "CM_L4CFG_MAILBOX8_CLKCTRL,This register manages the MAILBOX8 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x680++0x03 line.long 0x00 "CM_L4CFG_MAILBOX9_CLKCTRL,This register manages the MAILBOX9 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x688++0x03 line.long 0x00 "CM_L4CFG_MAILBOX10_CLKCTRL,This register manages the MAILBOX10 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x690++0x03 line.long 0x00 "CM_L4CFG_MAILBOX11_CLKCTRL,This register manages the MAILBOX11 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x698++0x03 line.long 0x00 "CM_L4CFG_MAILBOX12_CLKCTRL,This register manages the MAILBOX12 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x6A0++0x03 line.long 0x00 "CM_L4CFG_MAILBOX13_CLKCTRL,This register manages the MAILBOX13 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x6A8++0x03 line.long 0x00 "CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL,This register manages the SPARE_SMARTREFLEX_RTC clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x6B0++0x03 line.long 0x00 "CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL,This register manages the SPARE_SMARTREFLEX_SDRAM clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x6B8++0x03 line.long 0x00 "CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL,This register manages the SPARE_SMARTREFLEX_WKUP clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x6C0++0x03 line.long 0x00 "CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL,This register manages the IO_DELAY_BLOCK clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x700++0x03 line.long 0x00 "CM_L3INSTR_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," newline bitfld.long 0x00 10. "CLKACTIVITY_L3INSTR_TS_GCLK,This field indicates the state of the L3INSTR_TS_GCLK clock in the domain" "CLKACTIVITY_L3INSTR_TS_GCLK_0,CLKACTIVITY_L3INSTR_TS_GCLK_1" newline bitfld.long 0x00 9. "CLKACTIVITY_L3INSTR_DLL_AGING_GCLK,This field indicates the state of the L3INSTR_DLL_AGING_GCLK clock in the domain" "CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_0,CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_1" newline bitfld.long 0x00 8. "CLKACTIVITY_L3INSTR_L3_GICLK,This field indicates the state of the L3INSTR_L3_GICLK clock in the domain" "CLKACTIVITY_L3INSTR_L3_GICLK_0,CLKACTIVITY_L3INSTR_L3_GICLK_1" newline bitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L3INSTR clock domain" "?,?,?,CLKTRCTRL_3" group.long 0x720++0x03 line.long 0x00 "CM_L3INSTR_L3_MAIN_2_CLKCTRL,This register manages the L3_MAIN_2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x728++0x03 line.long 0x00 "CM_L3INSTR_L3_INSTR_CLKCTRL,This register manages the L3 INSTRUMENTATION clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x740++0x03 line.long 0x00 "CM_L3INSTR_OCP_WP_NOC_CLKCTRL,This register manages the OCP_WP_NOC clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x748++0x03 line.long 0x00 "CM_L3INSTR_DLL_AGING_CLKCTRL,This register manages the DLL_AGING clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x750++0x03 line.long 0x00 "CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,This register manages the CTRL_MODULE_BANDGAP clock" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 24.--25. "CLKSEL,Selects the divider value for generating the Thermal Sensor clock from WKUPAON_ICLK source" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline rbitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" width 0x0B tree.end tree "CORE_PRM" base ad:0x4AE06700 group.long 0x00++0x07 line.long 0x00 "PM_CORE_PWRSTCTRL,This register controls the CORE power state to reach upon a domain sleep transition" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 24.--25. "OCP_NRET_BANK_ONSTATE,OCP_WP bank and DMM bank2 state when domain is ON" "?,?,?,OCP_NRET_BANK_ONSTATE_3" newline rbitfld.long 0x00 22.--23. "IPU_UNICACHE_ONSTATE,IPU UNICACHE bank state when domain is ON" "?,?,?,IPU_UNICACHE_ONSTATE_3" rbitfld.long 0x00 20.--21. "IPU_L2RAM_ONSTATE,IPU L2 bank state when domain is ON" "?,?,?,IPU_L2RAM_ONSTATE_3" newline rbitfld.long 0x00 18.--19. "CORE_OCMRAM_ONSTATE,OCMRAM bank state when domain is ON" "?,?,?,CORE_OCMRAM_ONSTATE_3" rbitfld.long 0x00 16.--17. "CORE_OTHER_BANK_ONSTATE,DMA/ICR bank and DMM bank1 state when domain is ON" "?,?,?,CORE_OTHER_BANK_ONSTATE_3" newline rbitfld.long 0x00 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x00 12. "OCP_NRET_BANK_RETSTATE,OCP_WP bank and DMM bank2 state when domain is RETENTION" "OCP_NRET_BANK_RETSTATE_0,?" newline bitfld.long 0x00 11. "IPU_UNICACHE_RETSTATE,IPU UNICACHE bank state when domain is RETENTION" "IPU_UNICACHE_RETSTATE_0,IPU_UNICACHE_RETSTATE_1" bitfld.long 0x00 10. "IPU_L2RAM_RETSTATE,IPU L2 bank state when domain is RETENTION" "IPU_L2RAM_RETSTATE_0,IPU_L2RAM_RETSTATE_1" newline rbitfld.long 0x00 9. "CORE_OCMRAM_RETSTATE,OCMRAM bank state when domain is RETENTION" "?,CORE_OCMRAM_RETSTATE_1" rbitfld.long 0x00 8. "CORE_OTHER_BANK_RETSTATE,DMA/ICR bank and DMM bank1 state when domain is RETENTION" "?,CORE_OTHER_BANK_RETSTATE_1" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION" "LOGICRETSTATE_0,LOGICRETSTATE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_CORE_PWRSTST,This register provides a status on the current CORE power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 14.--19. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x04 12.--13. "OCP_NRET_BANK_STATEST,OCP_WP bank and DMM bank2 state status" "OCP_NRET_BANK_STATEST_0,OCP_NRET_BANK_STATEST_1,OCP_NRET_BANK_STATEST_2,OCP_NRET_BANK_STATEST_3" newline rbitfld.long 0x04 10.--11. "IPU_UNICACHE_STATEST,IPU UNICACHE bank state status" "IPU_UNICACHE_STATEST_0,IPU_UNICACHE_STATEST_1,IPU_UNICACHE_STATEST_2,IPU_UNICACHE_STATEST_3" rbitfld.long 0x04 8.--9. "IPU_L2RAM_STATEST,IPU L2 bank state status" "IPU_L2RAM_STATEST_0,IPU_L2RAM_STATEST_1,IPU_L2RAM_STATEST_2,IPU_L2RAM_STATEST_3" newline rbitfld.long 0x04 6.--7. "CORE_OCMRAM_STATEST,OCMRAM bank state status" "CORE_OCMRAM_STATEST_0,CORE_OCMRAM_STATEST_1,CORE_OCMRAM_STATEST_2,CORE_OCMRAM_STATEST_3" rbitfld.long 0x04 4.--5. "CORE_OTHER_BANK_STATEST,DMA/ICR bank and DMM bank1 state status" "CORE_OTHER_BANK_STATEST_0,CORE_OTHER_BANK_STATEST_1,CORE_OTHER_BANK_STATEST_2,CORE_OTHER_BANK_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_L3MAIN1_L3_MAIN_1_CONTEXT,This register contains dedicated L3_MAIN_1 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x2C++0x03 line.long 0x00 "RM_L3MAIN1_GPMC_CONTEXT,This register contains dedicated GPMC context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x34++0x03 line.long 0x00 "RM_L3MAIN1_MMU_EDMA_CONTEXT,This register contains dedicated MMU context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x4C++0x1B line.long 0x00 "RM_L3MAIN1_MMU_PCIESS_CONTEXT,This register contains dedicated MMU context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" line.long 0x04 "PM_L3MAIN1_OCMC_RAM1_WKDEP,This register controls wakeup dependency based on OCMC_RAM1 service requests" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "WKUPDEP_OCMC_RAM1_EVE4,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_EVE4_0,WKUPDEP_OCMC_RAM1_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_OCMC_RAM1_EVE3,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_EVE3_0,WKUPDEP_OCMC_RAM1_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_OCMC_RAM1_EVE2,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_EVE2_0,WKUPDEP_OCMC_RAM1_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_OCMC_RAM1_EVE1,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_EVE1_0,WKUPDEP_OCMC_RAM1_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_OCMC_RAM1_DSP2,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_DSP2_0,WKUPDEP_OCMC_RAM1_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_OCMC_RAM1_IPU1,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_IPU1_0,WKUPDEP_OCMC_RAM1_IPU1_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "WKUPDEP_OCMC_RAM1_DSP1,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_DSP1_0,WKUPDEP_OCMC_RAM1_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_OCMC_RAM1_IPU2,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_IPU2_0,WKUPDEP_OCMC_RAM1_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_OCMC_RAM1_MPU,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_MPU_0,WKUPDEP_OCMC_RAM1_MPU_1" line.long 0x08 "RM_L3MAIN1_OCMC_RAM1_CONTEXT,This register contains dedicated OCMC_RAM context statuses" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," bitfld.long 0x08 8. "LOSTMEM_CORE_OCMRAM,Specify if memory-based context in CORE_OCMRAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_CORE_OCMRAM_0,LOSTMEM_CORE_OCMRAM_1" newline hexmask.long.byte 0x08 1.--7. 1. "RESERVED," bitfld.long 0x08 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x0C "PM_L3MAIN1_TESOC_WKDEP,This register controls wakeup dependency based on TESOC service requests" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED," bitfld.long 0x0C 9. "WKUPDEP_TESOC_EVE4,Wakeup dependency from TESOC module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_EVE4_0,WKUPDEP_TESOC_EVE4_1" newline bitfld.long 0x0C 8. "WKUPDEP_TESOC_EVE3,Wakeup dependency from TESOC module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_EVE3_0,WKUPDEP_TESOC_EVE3_1" bitfld.long 0x0C 7. "WKUPDEP_TESOC_EVE2,Wakeup dependency from TESOC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_EVE2_0,WKUPDEP_TESOC_EVE2_1" newline bitfld.long 0x0C 6. "WKUPDEP_TESOC_EVE1,Wakeup dependency from TESOC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_EVE1_0,WKUPDEP_TESOC_EVE1_1" bitfld.long 0x0C 5. "WKUPDEP_TESOC_DSP2,Wakeup dependency from TESOC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_DSP2_0,WKUPDEP_TESOC_DSP2_1" newline bitfld.long 0x0C 4. "WKUPDEP_TESOC_IPU1,Wakeup dependency from TESOC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_IPU1_0,WKUPDEP_TESOC_IPU1_1" rbitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "WKUPDEP_TESOC_DSP1,Wakeup dependency from TESOC module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_DSP1_0,WKUPDEP_TESOC_DSP1_1" bitfld.long 0x0C 1. "WKUPDEP_TESOC_IPU2,Wakeup dependency from TESOC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_IPU2_0,WKUPDEP_TESOC_IPU2_1" newline bitfld.long 0x0C 0. "WKUPDEP_TESOC_MPU,Wakeup dependency from TESOC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TESOC_MPU_0,WKUPDEP_TESOC_MPU_1" line.long 0x10 "RM_L3MAIN1_TESOC_CONTEXT,This register contains dedicated TESOC context statuses" hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED," bitfld.long 0x10 8. "LOSTMEM_CORE_OCMRAM,Specify if memory-based context in CORE_OCMRAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_CORE_OCMRAM_0,LOSTMEM_CORE_OCMRAM_1" newline hexmask.long.byte 0x10 1.--7. 1. "RESERVED," bitfld.long 0x10 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x14 "PM_L3MAIN1_OCMC_RAM3_WKDEP,This register controls wakeup dependency based on OCMC_RAM3 service requests" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," bitfld.long 0x14 9. "WKUPDEP_OCMC_RAM3_EVE4,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_EVE4_0,WKUPDEP_OCMC_RAM3_EVE4_1" newline bitfld.long 0x14 8. "WKUPDEP_OCMC_RAM3_EVE3,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_EVE3_0,WKUPDEP_OCMC_RAM3_EVE3_1" bitfld.long 0x14 7. "WKUPDEP_OCMC_RAM3_EVE2,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_EVE2_0,WKUPDEP_OCMC_RAM3_EVE2_1" newline bitfld.long 0x14 6. "WKUPDEP_OCMC_RAM3_EVE1,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_EVE1_0,WKUPDEP_OCMC_RAM3_EVE1_1" bitfld.long 0x14 5. "WKUPDEP_OCMC_RAM3_DSP2,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_DSP2_0,WKUPDEP_OCMC_RAM3_DSP2_1" newline bitfld.long 0x14 4. "WKUPDEP_OCMC_RAM3_IPU1,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_IPU1_0,WKUPDEP_OCMC_RAM3_IPU1_1" rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 2. "WKUPDEP_OCMC_RAM3_DSP1,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_DSP1_0,WKUPDEP_OCMC_RAM3_DSP1_1" bitfld.long 0x14 1. "WKUPDEP_OCMC_RAM3_IPU2,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_IPU2_0,WKUPDEP_OCMC_RAM3_IPU2_1" newline bitfld.long 0x14 0. "WKUPDEP_OCMC_RAM3_MPU,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_MPU_0,WKUPDEP_OCMC_RAM3_MPU_1" line.long 0x18 "RM_L3MAIN1_OCMC_RAM3_CONTEXT,This register contains dedicated OCMC_RAM3 context statuses" hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED," bitfld.long 0x18 8. "LOSTMEM_CORE_OCMRAM,Specify if memory-based context in CORE_OCMRAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_CORE_OCMRAM_0,LOSTMEM_CORE_OCMRAM_1" newline hexmask.long.byte 0x18 1.--7. 1. "RESERVED," bitfld.long 0x18 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x6C++0x1B line.long 0x00 "RM_L3MAIN1_OCMC_ROM_CONTEXT,This register contains dedicated OCMC_ROM context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_CORE_OCMROM,Specify if memory-based context in CORE_OCMROM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_CORE_OCMROM_0,LOSTMEM_CORE_OCMROM_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_L3MAIN1_TPCC_WKDEP,This register controls wakeup dependency based on TPCC service requests" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "WKUPDEP_TPCC_EVE4,Wakeup dependency from TPCC module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_EVE4_0,WKUPDEP_TPCC_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_TPCC_EVE3,Wakeup dependency from TPCC module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_EVE3_0,WKUPDEP_TPCC_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_TPCC_EVE2,Wakeup dependency from TPCC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_EVE2_0,WKUPDEP_TPCC_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_TPCC_EVE1,Wakeup dependency from TPCC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_EVE1_0,WKUPDEP_TPCC_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_TPCC_DSP2,Wakeup dependency from TPCC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_DSP2_0,WKUPDEP_TPCC_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_TPCC_IPU1,Wakeup dependency from TPCC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_IPU1_0,WKUPDEP_TPCC_IPU1_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "WKUPDEP_TPCC_DSP1,Wakeup dependency from TPCC module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_DSP1_0,WKUPDEP_TPCC_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_TPCC_IPU2,Wakeup dependency from TPCC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_IPU2_0,WKUPDEP_TPCC_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_TPCC_MPU,Wakeup dependency from TPCC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_MPU_0,WKUPDEP_TPCC_MPU_1" line.long 0x08 "RM_L3MAIN1_TPCC_CONTEXT,This register contains dedicated TPCC context statuses" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," bitfld.long 0x08 8. "LOSTMEM_TPCC_BANK,Specify if memory-based context in TPCC_MEM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_TPCC_BANK_0,LOSTMEM_TPCC_BANK_1" newline rbitfld.long 0x08 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x08 0. "RESERVED," "0,1" line.long 0x0C "PM_L3MAIN1_TPTC1_WKDEP,This register controls wakeup dependency based on TPTC service requests" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED," bitfld.long 0x0C 9. "WKUPDEP_TPTC1_EVE4,Wakeup dependency from TPTC module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_EVE4_0,WKUPDEP_TPTC1_EVE4_1" newline bitfld.long 0x0C 8. "WKUPDEP_TPTC1_EVE3,Wakeup dependency from TPTC module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_EVE3_0,WKUPDEP_TPTC1_EVE3_1" bitfld.long 0x0C 7. "WKUPDEP_TPTC1_EVE2,Wakeup dependency from TPTC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_EVE2_0,WKUPDEP_TPTC1_EVE2_1" newline bitfld.long 0x0C 6. "WKUPDEP_TPTC1_EVE1,Wakeup dependency from TPTC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_EVE1_0,WKUPDEP_TPTC1_EVE1_1" bitfld.long 0x0C 5. "WKUPDEP_TPTC1_DSP2,Wakeup dependency from TPTC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_DSP2_0,WKUPDEP_TPTC1_DSP2_1" newline bitfld.long 0x0C 4. "WKUPDEP_TPTC1_IPU1,Wakeup dependency from TPTC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_IPU1_0,WKUPDEP_TPTC1_IPU1_1" rbitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "WKUPDEP_TPTC1_DSP1,Wakeup dependency from TPTC module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_DSP1_0,WKUPDEP_TPTC1_DSP1_1" bitfld.long 0x0C 1. "WKUPDEP_TPTC1_IPU2,Wakeup dependency from TPTC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_IPU2_0,WKUPDEP_TPTC1_IPU2_1" newline bitfld.long 0x0C 0. "WKUPDEP_TPTC1_MPU,Wakeup dependency from TPTC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_MPU_0,WKUPDEP_TPTC1_MPU_1" line.long 0x10 "RM_L3MAIN1_TPTC1_CONTEXT,This register contains dedicated TPTC1 context statuses" hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED," bitfld.long 0x10 8. "LOSTMEM_TPTC_BANK,Specify if memory-based context in TPTC_MEM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_TPTC_BANK_0,LOSTMEM_TPTC_BANK_1" newline rbitfld.long 0x10 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x10 0. "RESERVED," "0,1" line.long 0x14 "PM_L3MAIN1_TPTC2_WKDEP,This register controls wakeup dependency based on TPTC service requests" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," bitfld.long 0x14 9. "WKUPDEP_TPTC2_EVE4,Wakeup dependency from TPTC module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_EVE4_0,WKUPDEP_TPTC2_EVE4_1" newline bitfld.long 0x14 8. "WKUPDEP_TPTC2_EVE3,Wakeup dependency from TPTC module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_EVE3_0,WKUPDEP_TPTC2_EVE3_1" bitfld.long 0x14 7. "WKUPDEP_TPTC2_EVE2,Wakeup dependency from TPTC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_EVE2_0,WKUPDEP_TPTC2_EVE2_1" newline bitfld.long 0x14 6. "WKUPDEP_TPTC2_EVE1,Wakeup dependency from TPTC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_EVE1_0,WKUPDEP_TPTC2_EVE1_1" bitfld.long 0x14 5. "WKUPDEP_TPTC2_DSP2,Wakeup dependency from TPTC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_DSP2_0,WKUPDEP_TPTC2_DSP2_1" newline bitfld.long 0x14 4. "WKUPDEP_TPTC2_IPU1,Wakeup dependency from TPTC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_IPU1_0,WKUPDEP_TPTC2_IPU1_1" rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 2. "WKUPDEP_TPTC2_DSP1,Wakeup dependency from TPTC module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_DSP1_0,WKUPDEP_TPTC2_DSP1_1" bitfld.long 0x14 1. "WKUPDEP_TPTC2_IPU2,Wakeup dependency from TPTC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_IPU2_0,WKUPDEP_TPTC2_IPU2_1" newline bitfld.long 0x14 0. "WKUPDEP_TPTC2_MPU,Wakeup dependency from TPTC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_MPU_0,WKUPDEP_TPTC2_MPU_1" line.long 0x18 "RM_L3MAIN1_TPTC2_CONTEXT,This register contains dedicated TPTC2 context statuses" hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED," bitfld.long 0x18 8. "LOSTMEM_TPTC_BANK,Specify if memory-based context in TPTC_MEM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_TPTC_BANK_0,LOSTMEM_TPTC_BANK_1" newline rbitfld.long 0x18 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x18 0. "RESERVED," "0,1" group.long 0x8C++0x03 line.long 0x00 "RM_L3MAIN1_VCP1_CONTEXT,This register contains dedicated VCP1 context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_VCP_BANK,Specify if memory-based context in VCP memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VCP_BANK_0,LOSTMEM_VCP_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x94++0x03 line.long 0x00 "RM_L3MAIN1_VCP2_CONTEXT,This register contains dedicated VCP2 context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_VCP_BANK,Specify if memory-based context in VCP memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VCP_BANK_0,LOSTMEM_VCP_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x9C++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_CME_CONTEXT,This register contains dedicated SPARE_CME context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xA4++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_HDMI_CONTEXT,This register contains dedicated SPARE_HDMI context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xAC++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_ICM_CONTEXT,This register contains dedicated SPARE_ICM context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xB4++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_IVA2_CONTEXT,This register contains dedicated SPARE_IVA2 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xBC++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_SATA2_CONTEXT,This register contains dedicated SPARE_SATA2 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xC4++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT,This register contains dedicated SPARE_UNKNOWN4 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xCC++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT,This register contains dedicated SPARE_UNKNOWN5 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xD4++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT,This register contains dedicated SPARE_UNKNOWN6 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xDC++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT,This register contains dedicated SPARE_VIDEOPLL1 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xF4++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT,This register contains dedicated SPARE_VIDEOPLL2 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xFC++0x03 line.long 0x00 "RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT,This register contains dedicated SPARE_VIDEOPLL3 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x210++0x07 line.long 0x00 "RM_IPU2_RSTCTRL,This register controls the release of the IPU2 sub-system resets" hexmask.long 0x00 3.--31. 1. "RESERVED," bitfld.long 0x00 2. "RST_IPU,IPU system reset control" "RST_IPU_0,RST_IPU_1" newline bitfld.long 0x00 1. "RST_CPU1,IPU Cortex M3 CPU1 reset control" "RST_CPU1_0,RST_CPU1_1" bitfld.long 0x00 0. "RST_CPU0,IPU Cortex M3 CPU0 reset control" "RST_CPU0_0,RST_CPU0_1" line.long 0x04 "RM_IPU2_RSTST,This register logs the different reset sources of the IPU2 SS" hexmask.long 0x04 7.--31. 1. "RESERVED," bitfld.long 0x04 6. "RST_ICECRUSHER_CPU1,Cortex M3 CPU1 has been reset due to IPU ICECRUSHER1 reset source" "RST_ICECRUSHER_CPU1_0,RST_ICECRUSHER_CPU1_1" newline bitfld.long 0x04 5. "RST_ICECRUSHER_CPU0,Cortex M3 CPU0 has been reset due to IPU ICECRUSHER0 reset source" "RST_ICECRUSHER_CPU0_0,RST_ICECRUSHER_CPU0_1" bitfld.long 0x04 4. "RST_EMULATION_CPU1,Cortex M3 CPU1 has been reset due to emulation reset source e.g" "RST_EMULATION_CPU1_0,RST_EMULATION_CPU1_1" newline bitfld.long 0x04 3. "RST_EMULATION_CPU0,Cortex M3 CPU0 has been reset due to emulation reset source e.g" "RST_EMULATION_CPU0_0,RST_EMULATION_CPU0_1" bitfld.long 0x04 2. "RST_IPU,IPU system SW reset status" "RST_IPU_0,RST_IPU_1" newline bitfld.long 0x04 1. "RST_CPU1,IPU Cortex-M3 CPU1 SW reset status" "RST_CPU1_0,RST_CPU1_1" bitfld.long 0x04 0. "RST_CPU0,IPU Cortex-M3 CPU0 SW reset status" "RST_CPU0_0,RST_CPU0_1" group.long 0x224++0x03 line.long 0x00 "RM_IPU2_IPU2_CONTEXT,This register contains dedicated BELLINI1 context statuses" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "LOSTMEM_IPU_L2RAM,Specify if memory-based context in IPU_L2RAM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_IPU_L2RAM_0,LOSTMEM_IPU_L2RAM_1" newline bitfld.long 0x00 8. "LOSTMEM_IPU_UNICACHE,Specify if memory-based context in IPU_UNICACHE memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_IPU_UNICACHE_0,LOSTMEM_IPU_UNICACHE_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x324++0x03 line.long 0x00 "RM_DMA_DMA_SYSTEM_CONTEXT,This register contains dedicated SDMA context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_CORE_OTHER_BANK,Specify if memory-based context in CORE_OTHER_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_CORE_OTHER_BANK_0,LOSTMEM_CORE_OTHER_BANK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x424++0x03 line.long 0x00 "RM_EMIF_DMM_CONTEXT,This register contains dedicated DMM context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x42C++0x03 line.long 0x00 "RM_EMIF_EMIF_OCP_FW_CONTEXT,This register contains dedicated EMIF_OCP_FW context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x434++0x03 line.long 0x00 "RM_EMIF_EMIF1_CONTEXT,This register contains dedicated EMIF_1 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x43C++0x03 line.long 0x00 "RM_EMIF_EMIF2_CONTEXT,This register contains dedicated EMIF_2 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x444++0x03 line.long 0x00 "RM_EMIF_EMIF_DLL_CONTEXT,This register contains dedicated DLL context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x524++0x03 line.long 0x00 "RM_CRC_CRC_CONTEXT,This register contains dedicated CRC context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_CRC_BANK,Specify if memory-based context in CRC_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_CRC_BANK_0,LOSTMEM_CRC_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x624++0x03 line.long 0x00 "RM_L4CFG_L4_CFG_CONTEXT,This register contains dedicated L4_CFG context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x62C++0x03 line.long 0x00 "RM_L4CFG_SPINLOCK_CONTEXT,This register contains dedicated HW_SEM context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x634++0x03 line.long 0x00 "RM_L4CFG_MAILBOX1_CONTEXT,This register contains dedicated MAILBOX1 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x63C++0x03 line.long 0x00 "RM_L4CFG_SAR_ROM_CONTEXT,This register contains dedicated SAR_ROM context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x644++0x03 line.long 0x00 "RM_L4CFG_OCP2SCP2_CONTEXT,This register contains dedicated OCP2SCP2 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x64C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX2_CONTEXT,This register contains dedicated MAILBOX2 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x654++0x03 line.long 0x00 "RM_L4CFG_MAILBOX3_CONTEXT,This register contains dedicated MAILBOX3 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x65C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX4_CONTEXT,This register contains dedicated MAILBOX4 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x664++0x03 line.long 0x00 "RM_L4CFG_MAILBOX5_CONTEXT,This register contains dedicated MAILBOX5 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x66C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX6_CONTEXT,This register contains dedicated MAILBOX6 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x674++0x03 line.long 0x00 "RM_L4CFG_MAILBOX7_CONTEXT,This register contains dedicated MAILBOX7 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x67C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX8_CONTEXT,This register contains dedicated MAILBOX8 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x684++0x03 line.long 0x00 "RM_L4CFG_MAILBOX9_CONTEXT,This register contains dedicated MAILBOX9 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x68C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX10_CONTEXT,This register contains dedicated MAILBOX10 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x694++0x03 line.long 0x00 "RM_L4CFG_MAILBOX11_CONTEXT,This register contains dedicated MAILBOX11 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x69C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX12_CONTEXT,This register contains dedicated MAILBOX12 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x6A4++0x03 line.long 0x00 "RM_L4CFG_MAILBOX13_CONTEXT,This register contains dedicated MAILBOX13 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x6AC++0x03 line.long 0x00 "RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT,This register contains dedicated SPARE_SMARTREFLEX_RTC context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x6B4++0x03 line.long 0x00 "RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT,This register contains dedicated SPARE_SMARTREFLEX_SDRAM context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x6BC++0x03 line.long 0x00 "RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT,This register contains dedicated SPARE_SMARTREFLEX_WKUP context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x6C4++0x03 line.long 0x00 "RM_L4CFG_IO_DELAY_BLOCK_CONTEXT,This register contains dedicated IO_DELAY_BLOCK context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x724++0x03 line.long 0x00 "RM_L3INSTR_L3_MAIN_2_CONTEXT,This register contains dedicated L3_3 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x72C++0x03 line.long 0x00 "RM_L3INSTR_L3_INSTR_CONTEXT,This register contains dedicated L3_INSTR context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x744++0x03 line.long 0x00 "RM_L3INSTR_OCP_WP_NOC_CONTEXT,This register contains dedicated OCP_WP1 context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_CORE_NRET_BANK,Specify if memory-based context in CORE_NRET_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_CORE_NRET_BANK_0,LOSTMEM_CORE_NRET_BANK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "COREAON_CM_CORE" base ad:0x4A008600 group.long 0x00++0x03 line.long 0x00 "CM_COREAON_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.word 0x00 17.--31. 1. "RESERVED," newline rbitfld.long 0x00 16. "CLKACTIVITY_ABE_GICLK,This field indicates the state of the ABE_GICLK clock input of the domain" "CLKACTIVITY_ABE_GICLK_0,CLKACTIVITY_ABE_GICLK_1" newline rbitfld.long 0x00 15. "CLKACTIVITY_SR_IVAHD_SYS_GFCLK,This field indicates the state of the SR_IVAHD_SYS_GFCLK clock input of the domain" "CLKACTIVITY_SR_IVAHD_SYS_GFCLK_0,CLKACTIVITY_SR_IVAHD_SYS_GFCLK_1" newline rbitfld.long 0x00 14. "CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK,This field indicates the state of the COREAON_IO_SRCOMP_GFCLK clock in the domain" "CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_0,CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_1" newline rbitfld.long 0x00 13. "CLKACTIVITY_SR_DSPEVE_SYS_GFCLK,This field indicates the state of the SR_DSPEVE_SYS_GFCLK clock input of the domain" "CLKACTIVITY_SR_DSPEVE_SYS_GFCLK_0,CLKACTIVITY_SR_DSPEVE_SYS_GFCLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_COREAON_32K_GFCLK,This field indicates the state of the COREAON_32K_GFCLK clock in the domain" "CLKACTIVITY_COREAON_32K_GFCLK_0,CLKACTIVITY_COREAON_32K_GFCLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_SR_CORE_SYS_GFCLK,This field indicates the state of the SR_CORE_SYS_GFCLK clock input of the domain" "CLKACTIVITY_SR_CORE_SYS_GFCLK_0,CLKACTIVITY_SR_CORE_SYS_GFCLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_SR_GPU_SYS_GFCLK,This field indicates the state of the SR_GPU_SYS_GFCLK clock input of the domain" "CLKACTIVITY_SR_GPU_SYS_GFCLK_0,CLKACTIVITY_SR_GPU_SYS_GFCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_SR_MPU_SYS_GFCLK,This field indicates the state of the SR_MPU_SYS_GFCLK clock input of the domain" "CLKACTIVITY_SR_MPU_SYS_GFCLK_0,CLKACTIVITY_SR_MPU_SYS_GFCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_COREAON_L4_GICLK,This field indicates the state of the COREAON_L4_GICLK clock of the domain" "CLKACTIVITY_COREAON_L4_GICLK_0,CLKACTIVITY_COREAON_L4_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the COREAON clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x28++0x03 line.long 0x00 "CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,This register manages the SR_MPU clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x38++0x03 line.long 0x00 "CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,This register manages the SR_CORE clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_COREAON_USB_PHY1_CORE_CLKCTRL,This register manages the USB PHY 32KHz clock" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,Optional functional clock control" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0x50++0x03 line.long 0x00 "CM_COREAON_IO_SRCOMP_CLKCTRL,This register manages the clock delivered to the IO Slew rate compensation cells" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "CLKEN_SRCOMP_FCLK,Functional clock control" "CLKEN_SRCOMP_FCLK_0,CLKEN_SRCOMP_FCLK_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0x58++0x03 line.long 0x00 "CM_COREAON_SMARTREFLEX_GPU_CLKCTRL,This register manages the SR_GPU clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x68++0x03 line.long 0x00 "CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL,This register manages the SR_DSPEVE clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x78++0x03 line.long 0x00 "CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL,This register manages the SR_IVAHD clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x88++0x03 line.long 0x00 "CM_COREAON_USB_PHY2_CORE_CLKCTRL,This register manages the USB PHY 32KHz clock" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,Optional functional clock control" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0x98++0x03 line.long 0x00 "CM_COREAON_USB_PHY3_CORE_CLKCTRL,This register manages the USB PHY 32KHz clock" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,Optional functional clock control" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0xA0++0x03 line.long 0x00 "CM_COREAON_DUMMY_MODULE1_CLKCTRL,Used for controlling the CLKOUTMUX1 gate" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLKOUTMUX1_CLK,Optional functional clock control" "OPTFCLKEN_CLKOUTMUX1_CLK_0,OPTFCLKEN_CLKOUTMUX1_CLK_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0xB0++0x03 line.long 0x00 "CM_COREAON_DUMMY_MODULE2_CLKCTRL,Used for controlling CLKOUTMUX2 gate" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLKOUTMUX2_CLK,Optional functional clock control" "OPTFCLKEN_CLKOUTMUX2_CLK_0,OPTFCLKEN_CLKOUTMUX2_CLK_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0xC0++0x03 line.long 0x00 "CM_COREAON_DUMMY_MODULE3_CLKCTRL,Used for controlling the L3INIT_60M_GFCLK gate" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_L3INIT_60M_GFCLK,Optional functional clock control" "OPTFCLKEN_L3INIT_60M_GFCLK_0,OPTFCLKEN_L3INIT_60M_GFCLK_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0xD0++0x03 line.long 0x00 "CM_COREAON_DUMMY_MODULE4_CLKCTRL,Used for controlling ABE_GICLK gate" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_ABE_GICLK,Optional functional clock control" "OPTFCLKEN_ABE_GICLK_0,OPTFCLKEN_ABE_GICLK_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," width 0x0B tree.end tree "COREAON_PRM" base ad:0x4AE06628 group.long 0x00++0x07 line.long 0x00 "PM_COREAON_SMARTREFLEX_MPU_WKDEP,This register controls wakeup dependency based on SR_MPU service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline bitfld.long 0x00 9. "WKUPDEP_SMARTREFLEX_MPU_EVE4,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_EVE4_0,WKUPDEP_SMARTREFLEX_MPU_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_SMARTREFLEX_MPU_EVE3,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_EVE3_0,WKUPDEP_SMARTREFLEX_MPU_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_SMARTREFLEX_MPU_EVE2,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_EVE2_0,WKUPDEP_SMARTREFLEX_MPU_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SMARTREFLEX_MPU_EVE1,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_EVE1_0,WKUPDEP_SMARTREFLEX_MPU_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SMARTREFLEX_MPU_DSP2,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_DSP2_0,WKUPDEP_SMARTREFLEX_MPU_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SMARTREFLEX_MPU_IPU1,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_IPU1_0,WKUPDEP_SMARTREFLEX_MPU_IPU1_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_SMARTREFLEX_MPU_DSP1,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_DSP1_0,WKUPDEP_SMARTREFLEX_MPU_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_SMARTREFLEX_MPU_IPU2,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_IPU2_0,WKUPDEP_SMARTREFLEX_MPU_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SMARTREFLEX_MPU_MPU,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_MPU_MPU_0,WKUPDEP_SMARTREFLEX_MPU_MPU_1" line.long 0x04 "RM_COREAON_SMARTREFLEX_MPU_CONTEXT,This register contains dedicated SR_MPU context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," newline bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x10++0x07 line.long 0x00 "PM_COREAON_SMARTREFLEX_CORE_WKDEP,This register controls wakeup dependency based on SR_CORE service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline bitfld.long 0x00 9. "WKUPDEP_SMARTREFLEX_CORE_EVE4,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_EVE4_0,WKUPDEP_SMARTREFLEX_CORE_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_SMARTREFLEX_CORE_EVE3,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_EVE3_0,WKUPDEP_SMARTREFLEX_CORE_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_SMARTREFLEX_CORE_EVE2,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_EVE2_0,WKUPDEP_SMARTREFLEX_CORE_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SMARTREFLEX_CORE_EVE1,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_EVE1_0,WKUPDEP_SMARTREFLEX_CORE_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SMARTREFLEX_CORE_DSP2,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_DSP2_0,WKUPDEP_SMARTREFLEX_CORE_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SMARTREFLEX_CORE_IPU1,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_IPU1_0,WKUPDEP_SMARTREFLEX_CORE_IPU1_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_SMARTREFLEX_CORE_DSP1,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_DSP1_0,WKUPDEP_SMARTREFLEX_CORE_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_SMARTREFLEX_CORE_IPU2,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_IPU2_0,WKUPDEP_SMARTREFLEX_CORE_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SMARTREFLEX_CORE_MPU,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_CORE_MPU_0,WKUPDEP_SMARTREFLEX_CORE_MPU_1" line.long 0x04 "RM_COREAON_SMARTREFLEX_CORE_CONTEXT,This register contains dedicated SR_CORE context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," newline bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x30++0x07 line.long 0x00 "PM_COREAON_SMARTREFLEX_GPU_WKDEP,This register controls wakeup dependency based on SMARTREFLEX_GPU service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline bitfld.long 0x00 9. "WKUPDEP_SMARTREFLEX_GPU_EVE4,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_EVE4_0,WKUPDEP_SMARTREFLEX_GPU_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_SMARTREFLEX_GPU_EVE3,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_EVE3_0,WKUPDEP_SMARTREFLEX_GPU_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_SMARTREFLEX_GPU_EVE2,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_EVE2_0,WKUPDEP_SMARTREFLEX_GPU_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SMARTREFLEX_GPU_EVE1,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_EVE1_0,WKUPDEP_SMARTREFLEX_GPU_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SMARTREFLEX_GPU_DSP2,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_DSP2_0,WKUPDEP_SMARTREFLEX_GPU_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SMARTREFLEX_GPU_IPU1,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_IPU1_0,WKUPDEP_SMARTREFLEX_GPU_IPU1_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_SMARTREFLEX_GPU_DSP1,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_DSP1_0,WKUPDEP_SMARTREFLEX_GPU_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_SMARTREFLEX_GPU_IPU2,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_IPU2_0,WKUPDEP_SMARTREFLEX_GPU_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SMARTREFLEX_GPU_MPU,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_GPU_MPU_0,WKUPDEP_SMARTREFLEX_GPU_MPU_1" line.long 0x04 "RM_COREAON_SMARTREFLEX_GPU_CONTEXT,This register contains dedicated SR_GPU context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," newline bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x40++0x07 line.long 0x00 "PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP,This register controls wakeup dependency based on SMARTREFLEX_DSPEVE service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline bitfld.long 0x00 9. "WKUPDEP_SMARTREFLEX_DSPEVE_EVE4,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_EVE4_0,WKUPDEP_SMARTREFLEX_DSPEVE_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_SMARTREFLEX_DSPEVE_EVE3,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_EVE3_0,WKUPDEP_SMARTREFLEX_DSPEVE_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_SMARTREFLEX_DSPEVE_EVE2,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_EVE2_0,WKUPDEP_SMARTREFLEX_DSPEVE_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SMARTREFLEX_DSPEVE_EVE1,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_EVE1_0,WKUPDEP_SMARTREFLEX_DSPEVE_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SMARTREFLEX_DSPEVE_DSP2,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_DSP2_0,WKUPDEP_SMARTREFLEX_DSPEVE_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SMARTREFLEX_DSPEVE_IPU1,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_IPU1_0,WKUPDEP_SMARTREFLEX_DSPEVE_IPU1_1" newline bitfld.long 0x00 3. "WKUPDEP_SMARTREFLEX_DSPEVE_SDMA,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_SDMA_0,WKUPDEP_SMARTREFLEX_DSPEVE_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_SMARTREFLEX_DSPEVE_DSP1,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_DSP1_0,WKUPDEP_SMARTREFLEX_DSPEVE_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_SMARTREFLEX_DSPEVE_IPU2,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_IPU2_0,WKUPDEP_SMARTREFLEX_DSPEVE_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SMARTREFLEX_DSPEVE_MPU,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_DSPEVE_MPU_0,WKUPDEP_SMARTREFLEX_DSPEVE_MPU_1" line.long 0x04 "RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT,This register contains dedicated SR_DSPEVE context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," newline bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x50++0x07 line.long 0x00 "PM_COREAON_SMARTREFLEX_IVAHD_WKDEP,This register controls wakeup dependency based on SMARTREFLEX_IVAHD service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline bitfld.long 0x00 9. "WKUPDEP_SMARTREFLEX_IVAHD_EVE4,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_EVE4_0,WKUPDEP_SMARTREFLEX_IVAHD_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_SMARTREFLEX_IVAHD_EVE3,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_EVE3_0,WKUPDEP_SMARTREFLEX_IVAHD_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_SMARTREFLEX_IVAHD_EVE2,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_EVE2_0,WKUPDEP_SMARTREFLEX_IVAHD_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SMARTREFLEX_IVAHD_EVE1,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_EVE1_0,WKUPDEP_SMARTREFLEX_IVAHD_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SMARTREFLEX_IVAHD_DSP2,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_DSP2_0,WKUPDEP_SMARTREFLEX_IVAHD_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SMARTREFLEX_IVAHD_IPU1,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_IPU1_0,WKUPDEP_SMARTREFLEX_IVAHD_IPU1_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_SMARTREFLEX_IVAHD_DSP1,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_DSP1_0,WKUPDEP_SMARTREFLEX_IVAHD_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_SMARTREFLEX_IVAHD_IPU2,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_IPU2_0,WKUPDEP_SMARTREFLEX_IVAHD_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SMARTREFLEX_IVAHD_MPU,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SMARTREFLEX_IVAHD_MPU_0,WKUPDEP_SMARTREFLEX_IVAHD_MPU_1" line.long 0x04 "RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT,This register contains dedicated SR_IVA context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," newline bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x84++0x03 line.long 0x00 "RM_COREAON_DUMMY_MODULE1_CONTEXT,This register contains dedicated DUMMY MODULE1 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x94++0x03 line.long 0x00 "RM_COREAON_DUMMY_MODULE2_CONTEXT,This register contains dedicated DUMMY MODULE2 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xA4++0x03 line.long 0x00 "RM_COREAON_DUMMY_MODULE3_CONTEXT,This register contains DUMMY MODULE USBSTUB context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xB4++0x03 line.long 0x00 "RM_COREAON_DUMMY_MODULE4_CONTEXT,This register contains dedicated DUMMY MODULE context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "COUNTER_32K_TARG" base ad:0x4AE05000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CPDMA" base ad:0x48484800 rgroup.long 0x00++0x0B line.long 0x00 "CPDMA_TX_IDVER,CPDMA_REGS TX revision register" line.long 0x04 "CPDMA_TX_CONTROL,CPDMA_REGS TX control register" hexmask.long 0x04 1.--31. 1. "RESERVED," newline bitfld.long 0x04 0. "TX_EN,TX Enable" "Disabled,Enabled" line.long 0x08 "CPDMA_TX_TEARDOWN,CPDMA_REGS TX teardown register" rbitfld.long 0x08 31. "TX_TDN_RDY,Tx Teardown Ready - read as zero but is always assumed to be one (unused)" "0,1" newline hexmask.long 0x08 3.--30. 1. "RESERVED," newline bitfld.long 0x08 0.--2. "TX_TDN_CH,Tx Teardown" "0,1,2,3,4,5,6,7" rgroup.long 0x10++0x3F line.long 0x00 "CPDMA_RX_IDVER,CPDMA_REGS RX revision register" line.long 0x04 "CPDMA_RX_CONTROL,CPDMA_REGS RX control register" hexmask.long 0x04 1.--31. 1. "RESERVED," newline bitfld.long 0x04 0. "RX_EN,RX DMA Enable" "Disabled,Enabled" line.long 0x08 "CPDMA_RX_TEARDOWN,CPDMA_REGS RX teardown register" rbitfld.long 0x08 31. "RX_TDN_RDY,Teardown Ready - read as zero but is always assumed to be one (unused)" "0,1" newline hexmask.long 0x08 3.--30. 1. "RESERVED," newline bitfld.long 0x08 0.--2. "RX_TDN_CH,Rx Teardown Channel -Receive channel teardown is commanded by writing the encoded value of the receive channel to be torn down" "0,1,2,3,4,5,6,7" line.long 0x0C "CPDMA_SOFT_RESET,CPDMA_REGS soft reset register" hexmask.long 0x0C 1.--31. 1. "RESERVED," newline bitfld.long 0x0C 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the CPDMA logic to be reset" "0,1" line.long 0x10 "CPDMA_DMACONTROL,CPDMA_REGS CPDMA control register" hexmask.long.word 0x10 16.--31. 1. "RESERVED," newline abitfld.long 0x10 8.--15. "TX_RLIM,Transmit Rate Limit Channel Bus" "0x00=no rate-limited channels,0x80=channel 7 is rate-limited,0xC0=channels 7 downto 6 are rate-limited,0xE0=channels 7 downto 5 are rate-limited,0xF0=channels 7 downto 4 are rate-limited,0xF8=channels 7 downto 3 are rate-limited,0xFC=channels 7 downto 2 are rate-limited,0xFE=channels 7 downto 1 are rate-limited,0xFF=channels 7 downto 0 are rate-limited all.." newline rbitfld.long 0x10 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 4. "RX_CEF,RX Copy Error Frames Enable - Enables DMA overrun frames to be transferred to memory (up to the point of overrun)" "Frames containing overrun errors are filtered,Frames containing overrun errors are transferred.." newline bitfld.long 0x10 3. "CMD_IDLE,Command Idle" "Idle not commanded,Idle Commanded (read IDLE in CPDMA_DMASTATUS)" newline bitfld.long 0x10 2. "RX_OFFLEN_BLOCK,Receive Offset/Length word write block" "Do not block the DMA writes to the receive..,Block all CPDMA DMA controller writes to the.." newline bitfld.long 0x10 1. "RX_OWNERSHIP,Receive Ownership Write Bit Value" "The CPDMA writes the receive ownership bit to..,The CPDMA writes the receive ownership bit to.." newline bitfld.long 0x10 0. "TX_PTYPE,Transmit Queue Priority Type" "The queue uses a round robin scheme to select..,The queue uses a fixed (channel 7 highest.." line.long 0x14 "CPDMA_DMASTATUS,CPDMA_REGS CPDMA status register" bitfld.long 0x14 31. "IDLE,Idle Status Bit - Indicates when set that the CPDMA is not transferring a packet on transmit or receive" "0,1" newline hexmask.long.byte 0x14 24.--30. 1. "RESERVED," newline bitfld.long 0x14 20.--23. "TX_HOST_ERR_CODE,TX Host Error Code - This field is set to indicate CPDMA detected TX DMA related host errors" "No error,SOP error,Ownership bit not set in SOP buffer,Zero Next Buffer Descriptor Pointer Without EOP,Zero Buffer Pointer,Zero Buffer Length,Packet Length Error (sum of buffers is less than..,?..." newline bitfld.long 0x14 19. "RESERVED," "0,1" newline bitfld.long 0x14 16.--18. "TX_ERR_CH,TX Host Error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--15. "RX_HOST_ERR_CODE,RX Host Error Code - This field is set to indicate CPDMA detected RX DMA related host errors" "No error,reserved,Ownership bit not set in input buffer,reserved,Zero Buffer Pointer,Zero buffer length on non-SOP descriptor,SOP buffer length not greater than offset 0x7 -..,?..." newline bitfld.long 0x14 11. "RESERVED," "0,1" newline bitfld.long 0x14 8.--10. "RX_ERR_CH,RX Host Error" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "RESERVED," line.long 0x18 "CPDMA_RX_BUFFER_OFFSET,CPDMA_REGS receive buffer offset" hexmask.long.word 0x18 16.--31. 1. "RESERVED," newline hexmask.long.word 0x18 0.--15. 1. "RX_BUFFER_OFFSET,Receive Buffer Offset Value - The RX_BUFFER_OFFSET will be written by the port into each frame SOP buffer descriptor buffer_offset field" line.long 0x1C "CPDMA_EMCONTROL,CPDMA_REGS emulation control" hexmask.long 0x1C 2.--31. 1. "RESERVED," newline bitfld.long 0x1C 1. "SOFT,Emulation Soft Bit" "0,1" newline bitfld.long 0x1C 0. "FREE,Emulation Free Bit" "0,1" line.long 0x20 "CPDMA_TX_PRI0_RATE,CPDMA_REGS transmit (ingress) priority 0 rate" rbitfld.long 0x20 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x20 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline rbitfld.long 0x20 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x20 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x24 "CPDMA_TX_PRI1_RATE,CPDMA_REGS transmit (ingress) priority 1 rate" rbitfld.long 0x24 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x24 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline rbitfld.long 0x24 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x24 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x28 "CPDMA_TX_PRI2_RATE,CPDMA_REGS transmit (ingress) priority 2 rate" rbitfld.long 0x28 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x28 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline rbitfld.long 0x28 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x28 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x2C "CPDMA_TX_PRI3_RATE,CPDMA_REGS transmit (ingress) priority 3 rate" rbitfld.long 0x2C 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x2C 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline rbitfld.long 0x2C 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x2C 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x30 "CPDMA_TX_PRI4_RATE,CPDMA_REGS transmit (ingress) priority 4 rate" rbitfld.long 0x30 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x30 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline rbitfld.long 0x30 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x30 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x34 "CPDMA_TX_PRI5_RATE,CPDMA_REGS transmit (ingress) priority 5 rate" rbitfld.long 0x34 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x34 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline rbitfld.long 0x34 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x34 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x38 "CPDMA_TX_PRI6_RATE,CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 6 RATE" rbitfld.long 0x38 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x38 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline rbitfld.long 0x38 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x38 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x3C "CPDMA_TX_PRI7_RATE,CPDMA_REGS transmit (ingress) priority 7 rate" rbitfld.long 0x3C 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x3C 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline rbitfld.long 0x3C 14.--15. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x3C 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" rgroup.long 0x80++0x17 line.long 0x00 "CPDMA_TX_INTSTAT_RAW,CPDMA_INT TX interrupt status register (raw value)" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," newline bitfld.long 0x00 7. "TX7_PEND,TX7_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 6. "TX6_PEND,TX6_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 5. "TX5_PEND,TX5_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 4. "TX4_PEND,TX4_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 3. "TX3_PEND,TX3_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 2. "TX2_PEND,TX2_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 1. "TX1_PEND,TX1_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 0. "TX0_PEND,TX0_PEND raw int read (before mask)" "0,1" line.long 0x04 "CPDMA_TX_INTSTAT_MASKED,CPDMA_INT TX interrupt status register (masked value)" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," newline bitfld.long 0x04 7. "TX7_PEND,TX7_PEND masked interrupt" "0,1" newline bitfld.long 0x04 6. "TX6_PEND,TX6_PEND masked interrupt" "0,1" newline bitfld.long 0x04 5. "TX5_PEND,TX5_PEND masked interrupt" "0,1" newline bitfld.long 0x04 4. "TX4_PEND,TX4_PEND masked interrupt" "0,1" newline bitfld.long 0x04 3. "TX3_PEND,TX3_PEND masked interrupt" "0,1" newline bitfld.long 0x04 2. "TX2_PEND,TX2_PEND masked interrupt" "0,1" newline bitfld.long 0x04 1. "TX1_PEND,TX1_PEND masked interrupt" "0,1" newline bitfld.long 0x04 0. "TX0_PEND,TX0_PEND masked interrupt" "0,1" line.long 0x08 "CPDMA_TX_INTMASK_SET,CPDMA_INT TX interrupt mask set register" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED," newline bitfld.long 0x08 7. "TX7_MASK,TX Channel 7 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 6. "TX6_MASK,TX Channel 6 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 5. "TX5_MASK,TX Channel 5 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 4. "TX4_MASK,TX Channel 4 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 3. "TX3_MASK,TX Channel 3 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 2. "TX2_MASK,TX Channel 2 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 1. "TX1_MASK,TX Channel 1 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 0. "TX0_MASK,TX Channel 0 Mask - Write one to enable interrupt" "0,1" line.long 0x0C "CPDMA_TX_INTMASK_CLEAR,CPDMA_INT TX Interrupt mask clear register" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED," newline bitfld.long 0x0C 7. "TX7_MASK,TX Channel 7 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 6. "TX6_MASK,TX Channel 6 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 5. "TX5_MASK,TX Channel 5 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 4. "TX4_MASK,TX Channel 4 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 3. "TX3_MASK,TX Channel 3 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 2. "TX2_MASK,TX Channel 2 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 1. "TX1_MASK,TX Channel 1 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 0. "TX0_MASK,TX Channel 0 Mask - Write one to disable interrupt" "0,1" line.long 0x10 "CPDMA_IN_VECTOR,CPDMA_INT input vector (read only)" line.long 0x14 "CPDMA_EOI_VECTOR,CPDMA_INT end of interrupt vector" hexmask.long 0x14 5.--31. 1. "RESERVED," newline bitfld.long 0x14 0.--4. "DMA_EOI_VECTOR,DMA End of Interrupt Vector - The EOI_VECTOR( 4:0) pins reflect the value written to this location one MAIN_CLK cycle after a write to this location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA0++0x5F line.long 0x00 "CPDMA_RX_INTSTAT_RAW,CPDMA_INT RX Interrupt status register (raw value)" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline bitfld.long 0x00 15. "RX7_THRESH_PEND,RX7_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 14. "RX6_THRESH_PEND,RX6_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 13. "RX5_THRESH_PEND,RX5_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 12. "RX4_THRESH_PEND,RX4_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 11. "RX3_THRESH_PEND,RX3_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 10. "RX2_THRESH_PEND,RX2_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 9. "RX1_THRESH_PEND,RX1_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 8. "RX0_THRESH_PEND,RX0_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 7. "RX7_PEND,RX7_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 6. "RX6_PEND,RX6_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 5. "RX5_PEND,RX5_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 4. "RX4_PEND,RX4_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 3. "RX3_PEND,RX3_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 2. "RX2_PEND,RX2_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 1. "RX1_PEND,RX1_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 0. "RX0_PEND,RX0_PEND raw int read (before mask)" "0,1" line.long 0x04 "CPDMA_RX_INTSTAT_MASKED,CPDMA_INT RX interrupt status register (masked value)" hexmask.long.word 0x04 16.--31. 1. "RESERVED," newline bitfld.long 0x04 15. "RX7_THRESH_PEND,RX7_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 14. "RX6_THRESH_PEND,RX6_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 13. "RX5_THRESH_PEND,RX5_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 12. "RX4_THRESH_PEND,RX4_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 11. "RX3_THRESH_PEND,RX3_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 10. "RX2_THRESH_PEND,RX2_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 9. "RX1_THRESH_PEND,RX1_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 8. "RX0_THRESH_PEND,RX0_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 7. "RX7_PEND,RX7_PEND masked int" "0,1" newline bitfld.long 0x04 6. "RX6_PEND,RX6_PEND masked int" "0,1" newline bitfld.long 0x04 5. "RX5_PEND,RX5_PEND masked int" "0,1" newline bitfld.long 0x04 4. "RX4_PEND,RX4_PEND masked int" "0,1" newline bitfld.long 0x04 3. "RX3_PEND,RX3_PEND masked int" "0,1" newline bitfld.long 0x04 2. "RX2_PEND,RX2_PEND masked int" "0,1" newline bitfld.long 0x04 1. "RX1_PEND,RX1_PEND masked int" "0,1" newline bitfld.long 0x04 0. "RX0_PEND,RX0_PEND masked int" "0,1" line.long 0x08 "CPDMA_RX_INTMASK_SET,CPDMA_INT RX interrupt mask set register" hexmask.long.word 0x08 16.--31. 1. "RESERVED," newline bitfld.long 0x08 15. "RX7_THRESH_PEND_MASK,RX Channel 7 Threshold Pending Int" "0,1" newline bitfld.long 0x08 14. "RX6_THRESH_PEND_MASK,RX Channel 6 Threshold Pending Int" "0,1" newline bitfld.long 0x08 13. "RX5_THRESH_PEND_MASK,RX Channel 5 Threshold Pending Int" "0,1" newline bitfld.long 0x08 12. "RX4_THRESH_PEND_MASK,RX Channel 4 Threshold Pending Int" "0,1" newline bitfld.long 0x08 11. "RX3_THRESH_PEND_MASK,RX Channel 3 Threshold Pending Int" "0,1" newline bitfld.long 0x08 10. "RX2_THRESH_PEND_MASK,RX Channel 2 Threshold Pending Int" "0,1" newline bitfld.long 0x08 9. "RX1_THRESH_PEND_MASK,RX Channel 1 Threshold Pending Int" "0,1" newline bitfld.long 0x08 8. "RX0_THRESH_PEND_MASK,RX Channel 0 Threshold Pending Int" "0,1" newline bitfld.long 0x08 7. "RX7_PEND_MASK,RX Channel 7 Pending Int" "0,1" newline bitfld.long 0x08 6. "RX6_PEND_MASK,RX Channel 6 Pending Int" "0,1" newline bitfld.long 0x08 5. "RX5_PEND_MASK,RX Channel 5 Pending Int" "0,1" newline bitfld.long 0x08 4. "RX4_PEND_MASK,RX Channel 4 Pending Int" "0,1" newline bitfld.long 0x08 3. "RX3_PEND_MASK,RX Channel 3 Pending Int" "0,1" newline bitfld.long 0x08 2. "RX2_PEND_MASK,RX Channel 2 Pending Int" "0,1" newline bitfld.long 0x08 1. "RX1_PEND_MASK,RX Channel 1 Pending Int" "0,1" newline bitfld.long 0x08 0. "RX0_PEND_MASK,RX Channel 0 Pending Int" "0,1" line.long 0x0C "CPDMA_RX_INTMASK_CLEAR,CPDMA_INT RX interrupt mask clear register" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," newline bitfld.long 0x0C 15. "RX7_THRESH_PEND_MASK,RX Channel 7 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 14. "RX6_THRESH_PEND_MASK,RX Channel 6 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 13. "RX5_THRESH_PEND_MASK,RX Channel 5 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 12. "RX4_THRESH_PEND_MASK,RX Channel 4 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 11. "RX3_THRESH_PEND_MASK,RX Channel 3 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 10. "RX2_THRESH_PEND_MASK,RX Channel 2 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 9. "RX1_THRESH_PEND_MASK,RX Channel 1 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 8. "RX0_THRESH_PEND_MASK,RX Channel 0 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 7. "RX7_PEND_MASK,RX Channel 7 Pending Int" "0,1" newline bitfld.long 0x0C 6. "RX6_PEND_MASK,RX Channel 6 Pending Int" "0,1" newline bitfld.long 0x0C 5. "RX5_PEND_MASK,RX Channel 5 Pending Int" "0,1" newline bitfld.long 0x0C 4. "RX4_PEND_MASK,RX Channel 4 Pending Int" "0,1" newline bitfld.long 0x0C 3. "RX3_PEND_MASK,RX Channel 3 Pending Int" "0,1" newline bitfld.long 0x0C 2. "RX2_PEND_MASK,RX Channel 2 Pending Int" "0,1" newline bitfld.long 0x0C 1. "RX1_PEND_MASK,RX Channel 1 Pending Int" "0,1" newline bitfld.long 0x0C 0. "RX0_PEND_MASK,RX Channel 0 Pending Int" "0,1" line.long 0x10 "CPDMA_DMA_INTSTAT_RAW,CPDMA_INT DMA interrupt status register (raw value)" hexmask.long 0x10 2.--31. 1. "RESERVED," newline bitfld.long 0x10 1. "HOST_PEND,Host Pending Interrupt - raw int read (before mask)" "0,1" newline bitfld.long 0x10 0. "STAT_PEND,Statistics Pending Interrupt - raw int read (before mask)" "0,1" line.long 0x14 "CPDMA_DMA_INTSTAT_MASKED,CPDMA_INT DMA interrupt status register (masked value)" hexmask.long 0x14 2.--31. 1. "RESERVED," newline bitfld.long 0x14 1. "HOST_PEND,Host Pending Interrupt - masked interrupt" "0,1" newline bitfld.long 0x14 0. "STAT_PEND,Statistics Pending Interrupt - masked interrupt" "0,1" line.long 0x18 "CPDMA_DMA_INTMASK_SET,CPDMA_INT DMA interrupt mask set register" hexmask.long 0x18 2.--31. 1. "RESERVED," newline bitfld.long 0x18 1. "HOST_ERR_INT_MASK,Host Error Interrupt Mask - Write one to enable interrupt" "0,1" newline rbitfld.long 0x18 0. "STAT_INT_MASK,Statistics Interrupt Mask - Write one to enable interrupt" "0,1" line.long 0x1C "CPDMA_DMA_INTMASK_CLEAR,CPDMA_INT DMA interrupt mask clear register" hexmask.long 0x1C 2.--31. 1. "RESERVED," newline bitfld.long 0x1C 1. "HOST_ERR_INT_MASK,Host Error Interrupt Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x1C 0. "STAT_INT_MASK,Statistics Interrupt Mask - Write one to disable interrupt" "0,1" line.long 0x20 "CPDMA_RX0_PENDTHRESH,CPDMA_INT receive threshold pending register channel 0" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x20 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x24 "CPDMA_RX1_PENDTHRESH,CPDMA_INT receive threshold pending register channel 1" hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x24 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x28 "CPDMA_RX2_PENDTHRESH,CPDMA_INT receive threshold pending register channel 2" hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x28 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x2C "CPDMA_RX3_PENDTHRESH,CPDMA_INT receive threshold pending register channel 3" hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x2C 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x30 "CPDMA_RX4_PENDTHRESH,CPDMA_INT receive threshold pending register channel 4" hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x30 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x34 "CPDMA_RX5_PENDTHRESH,CPDMA_INT receive threshold pending register channel 5" hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x34 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x38 "CPDMA_RX6_PENDTHRESH,CPDMA_INT receive threshold pending register channel 6" hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x38 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x3C "CPDMA_RX7_PENDTHRESH,CPDMA_INT receive threshold pending register channel 7" hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x3C 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x40 "CPDMA_RX0_FREEBUFFER,CPDMA_INT receive free buffer register channel 0" hexmask.long.word 0x40 16.--31. 1. "RESERVED," newline hexmask.long.word 0x40 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x44 "CPDMA_RX1_FREEBUFFER,CPDMA_INT receive free buffer register channel 1" hexmask.long.word 0x44 16.--31. 1. "RESERVED," newline hexmask.long.word 0x44 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x48 "CPDMA_RX2_FREEBUFFER,CPDMA_INT receive free buffer register channel 2" hexmask.long.word 0x48 16.--31. 1. "RESERVED," newline hexmask.long.word 0x48 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x4C "CPDMA_RX3_FREEBUFFER,CPDMA_INT receive free buffer register channel 3" hexmask.long.word 0x4C 16.--31. 1. "RESERVED," newline hexmask.long.word 0x4C 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x50 "CPDMA_RX4_FREEBUFFER,CPDMA_INT receive free buffer register channel 4" hexmask.long.word 0x50 16.--31. 1. "RESERVED," newline hexmask.long.word 0x50 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x54 "CPDMA_RX5_FREEBUFFER,CPDMA_INT receive free buffer register channel 5" hexmask.long.word 0x54 16.--31. 1. "RESERVED," newline hexmask.long.word 0x54 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x58 "CPDMA_RX6_FREEBUFFER,CPDMA_INT receive free buffer register channel 6" hexmask.long.word 0x58 16.--31. 1. "RESERVED," newline hexmask.long.word 0x58 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x5C "CPDMA_RX7_FREEBUFFER,CPDMA_INT receive free buffer register channel 7" hexmask.long.word 0x5C 16.--31. 1. "RESERVED," newline hexmask.long.word 0x5C 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" width 0x0B tree.end tree "CPTS" base ad:0x48484C00 rgroup.long 0x00++0x07 line.long 0x00 "CPTS_IDVER,CPTS revision" line.long 0x04 "CPTS_CONTROL,Time sync control register" hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED," bitfld.long 0x04 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" bitfld.long 0x04 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x04 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x04 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" rbitfld.long 0x04 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 1. "INT_TEST,Interrupt Test - When set this bit allows the raw interrupt to be written to facilitate interrupt test" "0,1" bitfld.long 0x04 0. "CPTS_EN,Time Sync Enable - When disabled (cleared to zero) the RCLK domain is held in reset" "Time Sync Disabled,Time Sync Enabled" group.long 0x0C++0x0B line.long 0x00 "CPTS_TS_PUSH,Time stamp event push register" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "TS_PUSH,Time stamp event push - When a logic high is written to this bit a time stamp event is pushed onto the event FIFO" "0,1" line.long 0x04 "CPTS_TS_LOAD_VAL,Time stamp load value register" line.long 0x08 "CPTS_TS_LOAD_EN,Time stamp load enable register" hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "TS_LOAD_EN,Time Stamp Load - Writing a one to this bit enables the time stamp value to be written via theCPTS_TS_LOAD_VAL register" "0,1" group.long 0x20++0x0B line.long 0x00 "CPTS_INTSTAT_RAW,Time sync interrupt status raw register" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" line.long 0x04 "CPTS_INTSTAT_MASKED,Time sync interrupt status masked register" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" line.long 0x08 "CPTS_INT_ENABLE,Time sync interrupt enable register" hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" group.long 0x30++0x0B line.long 0x00 "CPTS_EVENT_POP,Event interrupt pop register" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "EVENT_POP,Event Pop - When a logic high is written to this bit an event is popped off the event FIFO" "0,1" line.long 0x04 "CPTS_EVENT_LOW,Lower 32-bits of the event value" line.long 0x08 "CPTS_EVENT_HIGH,Upper 32-bits of the event value" bitfld.long 0x08 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x08 24.--28. "PORT_NUMBER,Port Number - indicates the port number of an ethernet event or the hardware push pin number (1 to 4)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 20.--23. "EVENT_TYPE,Time Sync Event Type" "Time Stamp Push Event,Time Stamp Rollover Event,Time Stamp Half Rollover Event,Hardware Time Stamp Push Event,Ethernet Receive Event,Ethernet Transmit Event,?..." bitfld.long 0x08 16.--19. "MESSAGE_TYPE,Message type - The message type value that was contained in an ethernet transmit or receive time sync packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 0.--15. 1. "SEQUENCE_ID,Sequence ID - The 16-bit sequence id is the value that was contained in an ethernet transmit or receivetime sync packet" width 0x0B tree.end tree "CRC_CFG_TARG" base ad:0x4A261000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CRC_FW" base ad:0x4A244000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" newline rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "CRC_FW_CFG_TARG" base ad:0x4A245000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CRC_TARG" base ad:0x44000700 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "CTRL_MODULE_CORE" base ad:0x4A002000 group.long 0x114++0x0F line.long 0x00 "CTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1," rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 26. "MCASP1_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 23.--25. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 22. "IPU1_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 17.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16. "EVE1_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 13. "CT_TBR_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x00 12. "DEBUGSS_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x00 11. "EMIF_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 6.--10. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5. "ISS_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x00 4. "DSS_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x00 3. "L3RAM1_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 1.--2. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 0. "GPMC_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 different values can be exported to the corresponding L3 firewall" "0,1" line.long 0x04 "CTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1," rbitfld.long 0x04 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 26. "MCASP1_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 23.--25. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 22. "IPU1_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 17.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 16. "EVE1_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 13. "CT_TBR_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x04 12. "DEBUGSS_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x04 11. "EMIF_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 6.--10. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 5. "ISS_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x04 4. "DSS_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x04 3. "L3RAM1_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 1.--2. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 0. "GPMC_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 different values can be exported to the corresponding L3 firewall" "0,1" line.long 0x08 "CTRL_CORE_L4_HW_FW_EXPORTED_VALUES_CONF," rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 27. "L4PER3_AP_SECDBG_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 26. "RESERVED," "0,1" newline bitfld.long 0x08 25. "L4PER2_AP_SECDBG_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 24. "RESERVED," "0,1" newline bitfld.long 0x08 23. "L4WAKEUP_AP_SECDBG_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 21.--22. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 20. "L4CONFIG_AP_SECDBG_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 16. "L4PER1_AP_SECDBG_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 11. "L4PER3_AP_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 10. "RESERVED," "0,1" newline bitfld.long 0x08 9. "L4PER2_AP_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 8. "RESERVED," "0,1" newline bitfld.long 0x08 7. "L4WAKEUP_AP_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 5.--6. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 4. "L4CONFIG_AP_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" newline rbitfld.long 0x08 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 0. "L4PER1_AP_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit different values can be exported to the corresponding L4 firewall" "0,1" line.long 0x0C "CTRL_CORE_SEC_LOAD_FW_EXPORTED_VALUE," hexmask.long 0x0C 6.--31. 1. "RESERVED," newline bitfld.long 0x0C 5. "L4_PER3_LOAD_FW_EXPORTED_VALUE_REQN,LOAD FW exported values" "L4_PER3_LOAD_FW_EXPORTED_VALUE_REQN_0,L4_PER3_LOAD_FW_EXPORTED_VALUE_REQN_1" newline bitfld.long 0x0C 4. "L4_PER2_LOAD_FW_EXPORTED_VALUE_REQN,LOAD FW exported values" "L4_PER2_LOAD_FW_EXPORTED_VALUE_REQN_0,L4_PER2_LOAD_FW_EXPORTED_VALUE_REQN_1" newline bitfld.long 0x0C 3. "L4_PER1_LOAD_FW_EXPORTED_VALUE_REQN,LOAD FW exported values" "L4_PER1_LOAD_FW_EXPORTED_VALUE_REQN_0,L4_PER1_LOAD_FW_EXPORTED_VALUE_REQN_1" newline bitfld.long 0x0C 2. "L4_CONFIG_LOAD_FW_EXPORTED_VALUE_REQN,LOAD FW exported values" "L4_CONFIG_LOAD_FW_EXPORTED_VALUE_REQN_0,L4_CONFIG_LOAD_FW_EXPORTED_VALUE_REQN_1" newline bitfld.long 0x0C 1. "L4_WAKEUP_LOAD_FW_EXPORTED_VALUE_REQN,LOAD FW exported values" "L4_WAKEUP_LOAD_FW_EXPORTED_VALUE_REQN_0,L4_WAKEUP_LOAD_FW_EXPORTED_VALUE_REQN_1" newline rbitfld.long 0x0C 0. "RESERVED," "0,1" rgroup.long 0x134++0x03 line.long 0x00 "CTRL_CORE_STATUS,Control Module Status Register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 6.--8. "DEVICE_TYPE,Device type captured at reset time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--5. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x148++0x03 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_FUNC_1,Firewall Error Status functional Register 1" rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 28. "EVE1_FW_ERROR,EVE1 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 23.--27. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 22. "L4_WAKEUP_FW_ERROR,L4 wakeup firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18. "DEBUGSS_FW_ERROR,DebugSS firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 17. "L4_CONFIG_FW_ERROR,L4 config firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 16. "L4_PERIPH1_FW_ERROR,L4 periph1 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "DSS_FW_ERROR,DSS firewall" "No error from firewall,Error from firewall" newline hexmask.long.byte 0x00 6.--13. 1. "RESERVED," newline bitfld.long 0x00 5. "IPU1_FW_ERROR,IPU1 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 4. "RESERVED," "0,1" newline bitfld.long 0x00 3. "EMIF_FW_ERROR,EMIF firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 2. "GPMC_FW_ERROR,GPMC firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 1. "L3RAM1_FW_ERROR,L3RAM1 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x150++0x03 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_DEBUG_1,Firewall Error Status Debug Register 1" rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 28. "EVE1_DBGFW_ERROR,EVE1 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 23.--27. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 22. "L4_WAKEUP_DBGFW_ERROR,L4 wakeup firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18. "DEBUGSS_DBGFW_ERROR,DebugSS firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 17. "L4_CONFIG_DBGFW_ERROR,L4 config firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 16. "L4_PERIPH1_DBGFW_ERROR,L4 periph1 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 14. "DSS_DBGFW_ERROR,DSS debug firewall" "No error from firewall,Error from firewall" newline hexmask.long.byte 0x00 6.--13. 1. "RESERVED," newline bitfld.long 0x00 5. "IPU1_DBGFW_ERROR,IPU1 debug firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 4. "RESERVED," "0,1" newline bitfld.long 0x00 3. "EMIF_DBGFW_ERROR,EMIF debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 2. "GPMC_DBGFW_ERROR,GPMC debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 1. "L3RAM1_DBGFW_ERROR,L3RAM1 debug firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 0. "RESERVED," "0,1" rgroup.long 0x1CC++0x13 line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_0,Standard Fuse OPP VDD_CORE [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_1,Standard Fuse OPP VDD_CORE [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_2,Standard Fuse OPP VDD_CORE [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_3,Standard Fuse OPP VDD_CORE [127:96]" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_4,Standard Fuse OPP VDD_CORE [159:128]" rgroup.long 0x1E8++0x03 line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_BGAP_CORE,Trim values for CORE associated temperature sensor and bandgap" hexmask.long.byte 0x00 24.--31. 1. "STD_FUSE_OPP_BGAP_CORE_0,Trim values for CORE associated temperature sensor and bandgap" newline hexmask.long.byte 0x00 16.--23. 1. "STD_FUSE_OPP_BGAP_CORE_1,Trim values for CORE associated temperature sensor and bandgap" newline hexmask.long.byte 0x00 8.--15. 1. "STD_FUSE_OPP_BGAP_CORE_2,Trim values for CORE associated temperature sensor and bandgap" newline hexmask.long.byte 0x00 0.--7. 1. "STD_FUSE_OPP_BGAP_CORE_3,Trim values for CORE associated temperature sensor and bandgap" rgroup.long 0x220++0x1F line.long 0x00 "CTRL_CORE_STD_FUSE_MPK_0,Standard Fuse keys" line.long 0x04 "CTRL_CORE_STD_FUSE_MPK_1,Standard Fuse keys" line.long 0x08 "CTRL_CORE_STD_FUSE_MPK_2,Standard Fuse keys" line.long 0x0C "CTRL_CORE_STD_FUSE_MPK_3,Standard Fuse keys" line.long 0x10 "CTRL_CORE_STD_FUSE_MPK_4,Standard Fuse keys" line.long 0x14 "CTRL_CORE_STD_FUSE_MPK_5,Standard Fuse keys" line.long 0x18 "CTRL_CORE_STD_FUSE_MPK_6,Standard Fuse keys" line.long 0x1C "CTRL_CORE_STD_FUSE_MPK_7,Standard Fuse keys" rgroup.long 0x2BC++0x1B line.long 0x00 "CTRL_CORE_CUST_FUSE_SWRV_0,Customer Fuse keys" line.long 0x04 "CTRL_CORE_CUST_FUSE_SWRV_1,Customer Fuse keys" line.long 0x08 "CTRL_CORE_CUST_FUSE_SWRV_2,Customer Fuse keys" line.long 0x0C "CTRL_CORE_CUST_FUSE_SWRV_3,Customer Fuse keys" line.long 0x10 "CTRL_CORE_CUST_FUSE_SWRV_4,Customer Fuse keys" line.long 0x14 "CTRL_CORE_CUST_FUSE_SWRV_5,Customer Fuse keys" line.long 0x18 "CTRL_CORE_CUST_FUSE_SWRV_6,Customer Fuse keys" group.long 0x2E0++0x0F line.long 0x00 "CTRL_CORE_BREG_SELECTION,DPLL selection" hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED," newline bitfld.long 0x00 14. "SEL_DDR,Selection ddr" "no dpll selected,rdpll selected" newline rbitfld.long 0x00 13. "RESERVED," "0,1" newline bitfld.long 0x00 12. "SEL_GMAC,Selection gmac" "no dpll selected,rdpll selected" newline bitfld.long 0x00 11. "SEL_DSP,Selection dsp" "no dpll selected,rdpll selected" newline bitfld.long 0x00 10. "SEL_EVE,Selection eve" "no dpll selected,rdpll selected" newline rbitfld.long 0x00 6.--9. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5. "SEL_PER,Selection per" "no dpll selected,rdpll selected" newline bitfld.long 0x00 4. "SEL_HDMI,Selection hdmi" "no dpll selected,rdpll selected" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 1. "SEL_CORE,Selection core" "no dpll selected,rdpll selected" newline bitfld.long 0x00 0. "SEL_IPU,Selection ipu" "no dpll selected,rdpll selected" line.long 0x04 "CTRL_CORE_DPLL_BCLK,DPPL obs" hexmask.long 0x04 2.--31. 1. "RESERVED," newline bitfld.long 0x04 1. "BRW,Reset" "no reset,reset" newline bitfld.long 0x04 0. "BCLK,clock" "0,1" line.long 0x08 "CTRL_CORE_DPLL_BADDR_BDATAW,DPLL addr and dataw" hexmask.long.word 0x08 20.--31. 1. "RESERVED," newline bitfld.long 0x08 16.--19. "BADDR,baddr" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 0.--15. 1. "BDATAW,bdataw" line.long 0x0C "CTRL_CORE_DPLL_BDATAR,DPLL datar" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--15. 1. "BDATAR,datar" rgroup.long 0x334++0x03 line.long 0x00 "CTRL_CORE_TEMP_SENSOR_CORE,Control VBGAPTS temperature sensor and thermal comparator shutdown register" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED," newline bitfld.long 0x00 11. "BGAP_TMPSOFF_CORE,This bit indicates the temperature sensor state" "0,1" newline bitfld.long 0x00 10. "BGAP_EOCZ_CORE,ADC End of Conversion" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "BGAP_DTEMP_CORE,Temperature data from the ADC" group.long 0x358++0x0B line.long 0x00 "CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR,Cortex M4 register" hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--19. 1. "CORTEX_M4_MMUADDRTRANSLTR,Used to save the mmu address boot" line.long 0x04 "CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR," hexmask.long.word 0x04 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x04 0.--19. 1. "CORTEX_M4_MMUADDRLOGICTR," line.long 0x08 "CTRL_CORE_HWOBS_CONTROL,HW observability control" hexmask.long.word 0x08 19.--31. 1. "RESERVED," newline bitfld.long 0x08 14.--18. "HWOBS_CLKDIV_SEL_2,Clock divider selection for obs2 line" "?,output is not divided,output is divided by 2,?,output is divided by 4,?,?,?,output is divided by 8,?,?,?,?,?,?,?,output is divided by 16,?..." newline bitfld.long 0x08 9.--13. "HWOBS_CLKDIV_SEL_1,Clock divider selection for obs1 line" "?,output is not divided,output is divided by 2,?,output is divided by 4,?,?,?,output is divided by 8,?,?,?,?,?,?,?,output is divided by 16,?..." newline rbitfld.long 0x08 8. "RESERVED," "0,1" newline bitfld.long 0x08 3.--7. "HWOBS_CLKDIV_SEL,Clock divider selection for obs0 line" "?,output is not divided,output is divided by 2,?,output is divided by 4,?,?,?,output is divided by 8,?,?,?,?,?,?,?,output is divided by 16,?..." newline bitfld.long 0x08 2. "HWOBS_ALL_ZERO_MODE,Used to gate observable signals" "hw observability ports are not gated,hw observability ports are all set to 0" newline bitfld.long 0x08 1. "HWOBS_ALL_ONE_MODE,Used to gate observable signals" "hw observability ports are not gated,hw observability ports are all set to 1" newline bitfld.long 0x08 0. "HWOBS_MACRO_ENABLE,Used to gate observable signals coming from macros using the 32-bit HWOBS bus definition" "hw observability ports from macros are gated and..,hw observability ports from macros are not gated" group.long 0x380++0x03 line.long 0x00 "CTRL_CORE_BANDGAP_MASK_1,bgap_mask" bitfld.long 0x00 30.--31. "SIDLEMODE,sidlemode for bandgap" "No Idle,Force Idle,Smart Idle,Reserved" newline bitfld.long 0x00 27.--29. "COUNTER_DELAY,Counter delay" "Imediat,Delay of 1ms,Delay of 10ms,Delay of 100ms,Delay of 250ms,Delay of 500ms,?..." newline rbitfld.long 0x00 24.--26. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 23. "FREEZE_CORE,Freeze the FIFO CORE" "No operation,Freeze the FIFO" newline rbitfld.long 0x00 21.--22. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 20. "CLEAR_CORE,Reset the FIFO CORE" "No operation,Reset the FIFO" newline hexmask.long.word 0x00 6.--19. 1. "RESERVED," newline bitfld.long 0x00 5. "MASK_HOT_CORE,Mask for hot event CORE" "hot event is masked,hot event is not masked" newline bitfld.long 0x00 4. "MASK_COLD_CORE,Mask for cold event CORE" "cold event is masked,cold event is not masked" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38C++0x03 line.long 0x00 "CTRL_CORE_BANDGAP_THRESHOLD_CORE,BGAP THRESHOLD CORE" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 16.--25. 1. "THOLD_HOT_CORE,Value for the high temperature threshold" newline rbitfld.long 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--9. 1. "THOLD_COLD_CORE,Value for the low temperature threshold" rgroup.long 0x398++0x03 line.long 0x00 "CTRL_CORE_BANDGAP_TSHUT_CORE,BGAP TSHUT THRESHOLD CORE" bitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 16.--25. 1. "TSHUT_HOT_CORE,tshut value hot" newline bitfld.long 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--9. 1. "TSHUT_COLD_CORE,tshut value cold" rgroup.long 0x3A8++0x03 line.long 0x00 "CTRL_CORE_BANDGAP_STATUS_1,BGAP STATUS" bitfld.long 0x00 31. "ALERT,Alert temperature when '1'" "0,1" newline hexmask.long 0x00 6.--30. 1. "RESERVED," newline bitfld.long 0x00 5. "HOT_CORE,Event for hot temperature mpu bandgap when '1'" "event not detected,event detected" newline bitfld.long 0x00 4. "COLD_CORE,Event for cold temperature mpu bandgap when '1'" "event not detected,event detected" newline bitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x3E8++0x17 line.long 0x00 "CTRL_CORE_DTEMP_CORE_0,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x00 10.--31. 1. "DTEMP_TAG_CORE_0,tag" newline hexmask.long.word 0x00 0.--9. 1. "DTEMP_TEMPERATURE_CORE_0,temperature" line.long 0x04 "CTRL_CORE_DTEMP_CORE_1,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x04 10.--31. 1. "DTEMP_TAG_CORE_1,tag" newline hexmask.long.word 0x04 0.--9. 1. "DTEMP_TEMPERATURE_CORE_1,temperature" line.long 0x08 "CTRL_CORE_DTEMP_CORE_2,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x08 10.--31. 1. "DTEMP_TAG_CORE_2,tag" newline hexmask.long.word 0x08 0.--9. 1. "DTEMP_TEMPERATURE_CORE_2,temperature" line.long 0x0C "CTRL_CORE_DTEMP_CORE_3,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x0C 10.--31. 1. "DTEMP_TAG_CORE_3,tag" newline hexmask.long.word 0x0C 0.--9. 1. "DTEMP_TEMPERATURE_CORE_3,temperature" line.long 0x10 "CTRL_CORE_DTEMP_CORE_4,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x10 10.--31. 1. "DTEMP_TAG_CORE_4,tag" newline hexmask.long.word 0x10 0.--9. 1. "DTEMP_TEMPERATURE_CORE_4,temperature" line.long 0x14 "CTRL_CORE_SMA_SW_0,Inversion control for SD_DAC input data - DIN[9:0]" hexmask.long 0x14 3.--31. 1. "RESERVED," newline bitfld.long 0x14 2. "INPUTINV,Inversion control for SD_DAC input data - DIN[9:0]" "This value should be used for inverted video..,This value should be used for non-inverted video.." newline rbitfld.long 0x14 1. "RESERVED," "0,1" newline bitfld.long 0x14 0. "CKE_ASSERTION,Forces the EMIF CKE pad to tri-state" "The CKE pad is not in tri-state and can be..,The CKE pad is in tri-state" group.long 0x408++0x07 line.long 0x00 "CTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline bitfld.long 0x00 19. "CRC_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 18. "RESERVED," "0,1" newline bitfld.long 0x00 17. "TESOC_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 16. "RESERVED," "0,1" newline bitfld.long 0x00 15. "MMU1_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11. "TSC_ADC_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x00 10. "EDMA_TPCC_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x00 9. "EDMA_TC_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x00 8. "QSPI_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 1. "DSP2_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x00 0. "DSP1_SECDBG_EN,Using a combination of x_SECDBG_EN and corresponding x_SECLOCK_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 different values can be exported to the corresponding L3 firewall" "0,1" line.long 0x04 "CTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2," hexmask.long.word 0x04 20.--31. 1. "RESERVED," newline bitfld.long 0x04 19. "CRC_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 18. "RESERVED," "0,1" newline bitfld.long 0x04 17. "TESOC_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 16. "RESERVED," "0,1" newline bitfld.long 0x04 15. "MMU1_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 11. "TSC_ADC_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x04 10. "EDMA_TPCC_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x04 9. "EDMA_TC_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x04 8. "QSPI_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" newline rbitfld.long 0x04 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 1. "DSP2_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" newline bitfld.long 0x04 0. "DSP1_SECLOCK_EN,Using a combination of x_SECLOCK_EN and corresponding x_SECDBG_EN bit from registerCTRL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 different values can be exported to the corresponding L3 firewall" "0,1" group.long 0x414++0x03 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_FUNC_2,Firewall Error Status functional Register 2" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 26. "TC1_EDMA_FW_ERROR,EDMA TC1 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 23.--25. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 22. "QSPI_FW_ERROR,QSPI firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 17. "TPCC_EDMA_FW_ERROR,EDMA TPCC firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 16. "TC0_EDMA_FW_ERROR,EDMA TC0 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 11. "MCASP1_FW_ERROR,McASP1 firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 6.--10. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5. "L4_PERIPH3_FW_ERROR,L4 periph3 init firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 4. "L4_PERIPH2_FW_ERROR,L4 periph2 init firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 1. "DSP2_FW_ERROR,DSP2 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 0. "DSP1_FW_ERROR,DSP1 firewall" "No error from firewall,Error from firewall" group.long 0x41C++0x1B line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_DEBUG_2,Firewall Error Status debug Register 2" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 26. "TC1_EDMA_DBGFW_ERROR,EDMA TC1 debug firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 23.--25. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 22. "QSPI_DBGFW_ERROR,QSPI debug firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 17. "TPCC_EDMA_DBGFW_ERROR,EDMA TPCC debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 16. "TC0_EDMA_DBGFW_ERROR,EDMA TC0 debug firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 11. "MCASP1_DBGFW_ERROR,McASP1 debug firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 6.--10. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5. "L4_PERIPH3_DBGFW_ERROR,L4 periph3 init firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 4. "L4_PERIPH2_DBGFW_ERROR,L4 periph2 init firewall" "No error from firewall,Error from firewall" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 1. "DSP2_DBGFW_ERROR,DSP2 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 0. "DSP1_DBGFW_ERROR,DSP1 firewall" "No error from firewall,Error from firewall" line.long 0x04 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_1,Register for priority settings for EMIF arbitration" hexmask.long.tbyte 0x04 15.--31. 1. "RESERVED," newline bitfld.long 0x04 12.--14. "DSP1_CFG_EMIF_PRIORITY,DSP1 CFG priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline rbitfld.long 0x04 11. "RESERVED," "0,1" newline bitfld.long 0x04 8.--10. "DSP1_EDMA_EMIF_PRIORITY,DSP1 EDMA priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline rbitfld.long 0x04 7. "RESERVED," "0,1" newline bitfld.long 0x04 4.--6. "DSP2_EDMA_EMIF_PRIORITY,DSP2 EDMA priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 0.--2. "DSP2_CFG_EMIF_PRIORITY,DSP2 CFG priority setting" "highest priority,?,?,?,?,?,?,lowest priority" line.long 0x08 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_2,Register for priority settings for EMIF arbitration" hexmask.long.word 0x08 19.--31. 1. "RESERVED," newline bitfld.long 0x08 16.--18. "EVE1_TC0_EMIF_PRIORITY,EVE1 TC0 priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline hexmask.long.word 0x08 0.--15. 1. "RESERVED," line.long 0x0C "CTRL_CORE_EMIF_INITIATOR_PRIORITY_3,Register for priority settings for EMIF arbitration" hexmask.long.word 0x0C 19.--31. 1. "RESERVED," newline bitfld.long 0x0C 16.--18. "IPU1_EMIF_PRIORITY,IPU1 priority setting" "highest prioroty,?,?,?,?,?,?,lowest priority" newline hexmask.long.word 0x0C 3.--15. 1. "RESERVED," newline bitfld.long 0x0C 0.--2. "EDMA_TC0_EMIF_PRIORITY,EDMA TC0 priority setting" "highest priority,?,?,?,?,?,?,lowest priority" line.long 0x10 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_4,Register for priority settings for EMIF arbitration" rbitfld.long 0x10 31. "RESERVED," "0,1" newline bitfld.long 0x10 28.--30. "EDMA_TC1_EMIF_PRIORITY,EDMA TC1 priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline rbitfld.long 0x10 27. "RESERVED," "0,1" newline bitfld.long 0x10 24.--26. "DSS_EMIF_PRIORITY,DSS priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline hexmask.long.word 0x10 11.--23. 1. "RESERVED," newline bitfld.long 0x10 8.--10. "VIP1_P1_P2_EMIF_PRIORITY,VIP1 priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline hexmask.long.byte 0x10 0.--7. 1. "RESERVED," line.long 0x14 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_5,Register for priority settings for EMIF arbitration" hexmask.long.tbyte 0x14 15.--31. 1. "RESERVED," newline bitfld.long 0x14 12.--14. "GMAC_SW_EMIF_PRIORITY,GMAC_SW priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline hexmask.long.word 0x14 0.--11. 1. "RESERVED," line.long 0x18 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_6,Register for priority settings for EMIF arbitration" hexmask.long.tbyte 0x18 11.--31. 1. "RESERVED," newline bitfld.long 0x18 8.--10. "EVE1_TC1_EMIF_PRIORITY,EVE1 TC1 priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline hexmask.long.byte 0x18 0.--7. 1. "RESERVED," group.long 0x43C++0x03 line.long 0x00 "CTRL_CORE_L3_INITIATOR_PRESSURE_1,Register for pressure settings for L3 arbitration" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline bitfld.long 0x00 17.--18. "DSP1_CFG_L3_PRESSURE,DSP1 CFG pressure setting" "lowest,?,?,highest" newline rbitfld.long 0x00 11.--16. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9.--10. "DSP2_CFG_L3_PRESSURE,DSP2 CFG pressure setting" "lowest,?,?,highest" newline hexmask.long.word 0x00 0.--8. 1. "RESERVED," rgroup.long 0x4E8++0x1B line.long 0x00 "CTRL_CORE_CUST_FUSE_UID_0,Customer Fuse keys" line.long 0x04 "CTRL_CORE_CUST_FUSE_UID_1,Customer Fuse keys" line.long 0x08 "CTRL_CORE_CUST_FUSE_UID_2,Customer Fuse keys" line.long 0x0C "CTRL_CORE_CUST_FUSE_UID_3,Customer Fuse keys" line.long 0x10 "CTRL_CORE_CUST_FUSE_UID_4,Customer Fuse keys" line.long 0x14 "CTRL_CORE_CUST_FUSE_UID_5,Customer Fuse keys" line.long 0x18 "CTRL_CORE_CUST_FUSE_UID_6,Customer Fuse keys" rgroup.long 0x514++0x0F line.long 0x00 "CTRL_CORE_MAC_ID_SW_0,Standard Fuse keys. MAC ID_1 [63:32]" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--23. 1. "STD_FUSE_MAC_ID_SW_0,This bit field contains the last three octets (NIC specific) of the MAC address of the GMAC_SW port 0" line.long 0x04 "CTRL_CORE_MAC_ID_SW_1,Standard Fuse keys. MAC ID_1 [31:0]" hexmask.long.byte 0x04 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x04 0.--23. 1. "STD_FUSE_MAC_ID_SW_1,This bit field contains the last three octets (the OUI) of the MAC address of the GMAC_SW port 0" line.long 0x08 "CTRL_CORE_MAC_ID_SW_2,Standard Fuse keys. MAC ID_2 [63:32]" hexmask.long.byte 0x08 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x08 0.--23. 1. "STD_FUSE_MAC_ID_SW_2,This bit field contains the last three octets (NIC specific) of the MAC address of the GMAC_SW port 1" line.long 0x0C "CTRL_CORE_MAC_ID_SW_3,Standard Fuse keys. MAC ID_2 [31:0]" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x0C 0.--23. 1. "STD_FUSE_MAC_ID_SW_3,This bit field contains the last three octets (the OUI) of the MAC address of the GMAC_SW port 1" group.long 0x534++0x03 line.long 0x00 "CTRL_CORE_SMA_SW_1,OCP Spare Register" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 26. "RGMII2_ID_MODE_N,Ethernet RGMII port 2 internal delay on transmit (SR2.0 Only)" "Internal delay enabled,Internal delay disabled" newline bitfld.long 0x00 25. "RGMII1_ID_MODE_N,Ethernet RGMII port 1 internal delay on transmit (SR2.0 Only)" "Internal delay enabled,Internal delay disabled" newline rbitfld.long 0x00 23.--24. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 22. "DSS_CH0_ON_OFF,DSS Channel 0 Pixel clock control On/Off" "HSYNC and VSYNC are driven on opposite edges of..,HSYNC and VSYNC are driven according to bit.." newline rbitfld.long 0x00 20.--21. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 19. "DSS_CH0_IPC,DSS Channel 0 IPC control" "Data is driven on the LCD data lines on the..,Data is driven on the LCD data lines on the.." newline rbitfld.long 0x00 17.--18. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 16. "DSS_CH0_RF,DSS Channel 0 Rise/Fall control" "HSYNC and VSYNC are driven on falling edge of..,HSYNC and VSYNC are driven on rising edge of.." newline hexmask.long.word 0x00 4.--15. 1. "RESERVED," newline bitfld.long 0x00 3. "VIP1_CLK_INV_PORT_2B,VIP1 Slice 1 Clock inversion for Port B enable" "Clock inversion is disabled,Clock inversion is enabled" newline bitfld.long 0x00 2. "VIP1_CLK_INV_PORT_1B,VIP1 Slice 0 Clock inversion for Port B enable" "Clock inversion is disabled,Clock inversion is enabled" newline bitfld.long 0x00 1. "VIP1_CLK_INV_PORT_2A,VIP1 Slice 1 Clock inversion for Port A enable" "Clock inversion is disabled,Clock inversion is enabled" newline bitfld.long 0x00 0. "VIP1_CLK_INV_PORT_1A,VIP1 Slice 0 Clock inversion for Port A enable" "Clock inversion is disabled,Clock inversion is enabled" group.long 0x53C++0x2B line.long 0x00 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_8,Register for priority settings for EMIF arbitration" hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED," newline bitfld.long 0x00 12.--14. "ISS_NRT_EMIF_PRIORITY,ISS NRT ports priority setting" "ISS_NRT_EMIF_PRIORITY_0,?,?,?,?,?,?,ISS_NRT_EMIF_PRIORITY_7" newline rbitfld.long 0x00 11. "RESERVED," "0,1" newline bitfld.long 0x00 8.--10. "ISS_RT_EMIF_PRIORITY,ISS RT port priority setting" "ISS_RT_EMIF_PRIORITY_0,?,?,?,?,?,?,ISS_RT_EMIF_PRIORITY_7" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," line.long 0x04 "CTRL_CORE_MMR_LOCK_1,Register to lock memory regions from 0x0000 0100 to 0x0000 079F and from 0x0000 1A00 to 0x0000 1FFF" line.long 0x08 "CTRL_CORE_MMR_LOCK_2,Register to lock memory region starting at address offset 0x0000 07A0 and ending at address offset 0x0000 0D9F" line.long 0x0C "CTRL_CORE_MMR_LOCK_3,Register to lock memory region starting at address offset 0x0000 0DA0 and ending at address offset 0x0000 0FFF" line.long 0x10 "CTRL_CORE_MMR_LOCK_4,Register to lock memory region starting at address offset 0x0000 1000 and ending at address offset 0x0000 13FF" line.long 0x14 "CTRL_CORE_MMR_LOCK_5,Register to lock memory region starting at address offset 0x0000 1400 and ending at address offset 0x0000 19FF" line.long 0x18 "CTRL_CORE_CONTROL_IO_1,Register to configure some IP level signals" hexmask.long.word 0x18 17.--31. 1. "RESERVED," newline bitfld.long 0x18 16. "MMU1_DISABLE,MMU1 DISABLE setting" "0,1" newline rbitfld.long 0x18 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x18 12.--13. "TC1_DEFAULT_BURST_SIZE,EDMA TC1 DEFAULT BURST SIZE setting" "0,1,2,3" newline rbitfld.long 0x18 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x18 8.--9. "TC0_DEFAULT_BURST_SIZE,EDMA TC0 DEFAULT BURST SIZE setting" "0,1,2,3" newline rbitfld.long 0x18 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x18 4.--5. "GMII2_SEL,GMII2 selection setting" "GMII/MII,RMII,RGMII,Reserved" newline rbitfld.long 0x18 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x18 0.--1. "GMII1_SEL,GMII1 selection setting" "GMII/MII,RMII,RGMII,Reserved" line.long 0x1C "CTRL_CORE_CONTROL_IO_2,Register to configure some IP level signals" rbitfld.long 0x1C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 24.--26. "RTI_RESET_SELECTION_TO_PRCM,RTI reset mux select value" "RTI1,RTI2,RTI3,RTI4,RTI5,?..." newline bitfld.long 0x1C 23. "GMAC_RESET_ISOLATION_ENABLE,Reset isolation enable setting" "Reset is not isolated,Reset is isolated" newline rbitfld.long 0x1C 21.--22. "RESERVED," "0,1,2,3" newline bitfld.long 0x1C 20. "PWMSS1_TBCLKEN,PWMSS1 CLOCK ENABLE setting" "0,1" newline rbitfld.long 0x1C 16.--19. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 15. "VIP1_VIN2_INPUT_SELECTION,VIP1 vin2 input selection setting" "Input from pins selected,Input from LVDSRX port2 selected" newline bitfld.long 0x1C 14. "VIP1_VIN1_INPUT_SELECTION,VIP1 vin1 input selection setting" "Input from pins selected,Input from LVDSRX port1 selected" newline rbitfld.long 0x1C 11.--13. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8.--10. "QSPI_MEMMAPPED_CS,QSPI CS MAPPING setting" "The QSPI configuration registers are accessed,An external device connected to CS0 is accessed,An external device connected to CS1 is accessed,An external device connected to CS2 is accessed..,?..." newline rbitfld.long 0x1C 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x1C 5. "DCAN2_RAMINIT_START,DCAN2 RAM INIT START setting (SR1.0 Only)" "0,1" newline bitfld.long 0x1C 4. "DSS_DESHDCP_DISABLE,DSS DESHDCP DISABLE setting" "0,1" newline bitfld.long 0x1C 3. "DCAN_RAMINIT_START,DCAN RAM INIT START setting To initialize DCAN RAM the bit should be set to 0x1" "0,1" newline bitfld.long 0x1C 2. "DCAN2_RAMINIT_DONE,DCAN2 RAM INIT DONE status (SR1.0 Only)" "0,1" newline bitfld.long 0x1C 1. "DCAN_RAMINIT_DONE,DCAN RAM INIT DONE status: is called on SR1.0 devices" "0,1" newline bitfld.long 0x1C 0. "DSS_DESHDCP_CLKEN,DSS DESHDCP CLOCK ENABLE setting" "0,1" line.long 0x20 "CTRL_CORE_CONTROL_DSP1_RST_VECT,Register for storing DSP1 reset vector" bitfld.long 0x20 27.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x20 24.--26. "DSP1_NUM_MM,Number of DSP instances in the SoC" "?,1,2,?..." newline rbitfld.long 0x20 22.--23. "RESERVED," "0,1,2,3" newline hexmask.long.tbyte 0x20 0.--21. 1. "DSP1_RST_VECT,DSP1 reset vector address" line.long 0x24 "CTRL_CORE_CONTROL_DSP2_RST_VECT,Register for storing DSP2 reset vector" bitfld.long 0x24 27.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x24 24.--26. "DSP2_NUM_MM,Number of DSP instances in the SoC" "?,1,2,?..." newline rbitfld.long 0x24 22.--23. "RESERVED," "0,1,2,3" newline hexmask.long.tbyte 0x24 0.--21. 1. "DSP2_RST_VECT,DSP2 reset vector address" line.long 0x28 "CTRL_CORE_STD_FUSE_OPP_BGAP_DSPEVE,Trim values for DSPEVE associated bandgap" hexmask.long.word 0x28 16.--31. 1. "RESERVED," newline hexmask.long.byte 0x28 8.--15. 1. "STD_FUSE_OPP_BGAP_DSPEVE_0,Trim values for DSPEVE associated bandgap" newline hexmask.long.byte 0x28 0.--7. 1. "STD_FUSE_OPP_BGAP_DSPEVE_1,Trim values for DSPEVE associated bandgap" group.long 0x56C++0x03 line.long 0x00 "CTRL_CORE_LDOSRAM_DSPEVE_VOLTAGE_CTRL,DSPEVE SRAM LDO Control register" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 26. "LDOSRAMDSPEVE_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value" "LDOSRAMDSPEVE_RETMODE_MUX_CTRL_0,LDOSRAMDSPEVE_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x00 21.--25. "LDOSRAMDSPEVE_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "LDOSRAMDSPEVE_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10. "LDOSRAMDSPEVE_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value" "LDOSRAMDSPEVE_ACTMODE_MUX_CTRL_0,LDOSRAMDSPEVE_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x00 5.--9. "LDOSRAMDSPEVE_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "LDOSRAMDSPEVE_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x5E0++0x0F line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_2,This register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_NOM" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--11. 1. "STD_FUSE_OPP_VMIN_DSPEVE_2,AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_NOM" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_3,This register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_OD" hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x04 0.--11. 1. "STD_FUSE_OPP_VMIN_DSPEVE_3,AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_OD" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_4,This register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_HIGH" hexmask.long.tbyte 0x08 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x08 0.--11. 1. "STD_FUSE_OPP_VMIN_DSPEVE_4,AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_HIGH" line.long 0x0C "CTRL_CORE_RC_OSC_FREQUENCY,This register is used only on SR2.0 devices" bitfld.long 0x0C 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long 0x0C 0.--25. 1. "RC_OSC_CALIBRATION_VALUE,Used only on SR2.0 devices" rgroup.long 0x5F4++0x03 line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_2,This register contains the AVS Class 0 voltage value for the vdd voltage rail when running at OPP_NOM" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--11. 1. "STD_FUSE_OPP_VMIN_CORE_2,AVS Class 0 voltage value for the vdd voltage rail when running at OPP_NOM" group.long 0x680++0x07 line.long 0x00 "CTRL_CORE_LDOSRAM_CORE_2_VOLTAGE_CTRL,CORE 2nd SRAM LDO Control register" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 26. "LDOSRAMCORE_2_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value" "LDOSRAMCORE_2_RETMODE_MUX_CTRL_0,LDOSRAMCORE_2_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x00 21.--25. "LDOSRAMCORE_2_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "LDOSRAMCORE_2_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10. "LDOSRAMCORE_2_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value" "LDOSRAMCORE_2_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_2_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x00 5.--9. "LDOSRAMCORE_2_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "LDOSRAMCORE_2_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "CTRL_CORE_LDOSRAM_CORE_3_VOLTAGE_CTRL,CORE 3rd SRAM LDO Control register" rbitfld.long 0x04 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 26. "LDOSRAMCORE_3_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value" "LDOSRAMCORE_3_RETMODE_MUX_CTRL_0,LDOSRAMCORE_3_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x04 21.--25. "LDOSRAMCORE_3_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 16.--20. "LDOSRAMCORE_3_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 10. "LDOSRAMCORE_3_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value" "LDOSRAMCORE_3_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_3_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x04 5.--9. "LDOSRAMCORE_3_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. "LDOSRAMCORE_3_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x68C++0x07 line.long 0x00 "CTRL_CORE_NMI_DESTINATION_1,Register for routing NMI interrupt to respective cores" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" newline abitfld.long 0x00 0.--7. "IPU1_C1,Enable IPU1 CORE1 to receive the NMI interrupt" "0x00=NMI disabled,0x01=NMI enabled" line.long 0x04 "CTRL_CORE_NMI_DESTINATION_2,Register for routing NMI interrupt to respective cores" abitfld.long 0x04 24.--31. "IPU1_C0,Enable IPU1 CORE0 to receive the NMI interrupt" "0x00=NMI disabled,0x01=NMI enabled" newline abitfld.long 0x04 16.--23. "DSP2,Enable DSP2 to receive the NMI interrupt" "0x00=NMI disabled,0x01=NMI enabled" newline abitfld.long 0x04 8.--15. "DSP1,Enable DSP1 to receive the NMI interrupt" "0x00=NMI disabled,0x01=NMI enabled" newline hexmask.long.byte 0x04 0.--7. 1. "RESERVED," rgroup.long 0x6A0++0x1F line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_0,Standard Fuse OPP VDD_DSPEVE [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_1,Standard Fuse OPP VDD_DSPEVE [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_2,Standard Fuse OPP VDD_DSPEVE [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_3,Standard Fuse OPP VDD_DSPEVE [127:96]" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_4,Standard Fuse OPP VDD_DSPEVE [159:128]" line.long 0x14 "CTRL_CORE_CUST_FUSE_SWRV_7,Customer Fuse keys" line.long 0x18 "CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0,Standard Fuse Calibration override value [31:0]" line.long 0x1C "CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1,Standard Fuse Calibration override value [63:32]" rgroup.long 0x6C4++0x03 line.long 0x00 "CTRL_CORE_BOOTSTRAP,Register to view all the sysboot settings" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline bitfld.long 0x00 15. "DSP_CLOCK_DIVIDER,Divide factor for DSP clock" "0,1" newline bitfld.long 0x00 14. "RESERVED," "0,1" newline bitfld.long 0x00 13. "BOOTDEVICESIZE,Select the size of the flash device on CS0" "8-bit,16-bit" newline bitfld.long 0x00 11.--12. "MUXCS0DEVICE,Select IC boot sequence to be executed from a multiplexed address and data device attached to CS0" "Non-muxed device attached,Addr-Data Mux device attached,Reserved,Reserved" newline bitfld.long 0x00 10. "BOOTWAITEN,Enable the monitoring on CS0 of the wait pin at IC reset release time for read accesses" "Wait pin is not monitored for read accesses,Wait pin is monitored for read accesses" newline bitfld.long 0x00 8.--9. "SPEEDSELECT,Indicates the SYS_CLK1 frequency (from osc0)" "Reserved,20 MHz,27 MHz,19.2 MHz" newline bitfld.long 0x00 7. "RESERVED," "0,1" newline bitfld.long 0x00 6. "HWOBS_IO_SELECTION," "0,1" newline bitfld.long 0x00 5. "ADC_CLOCK_DIVIDER," "0,1" newline bitfld.long 0x00 0.--4. "BOOTMODE,SYSBOOT mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x794++0x03 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_FUNC_3," hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "CRC_FW_ERROR,CRC firewall" "CRC_FW_ERROR_0,CRC_FW_ERROR_1" group.long 0x79C++0x13 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_DEBUG_3,Security Error Status functional Register" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "CRC_DBGFW_ERROR,CRC debug firewall" "CRC_DBGFW_ERROR_0,CRC_DBGFW_ERROR_1" line.long 0x04 "CTRL_CORE_EVE_IRQ_0_1," hexmask.long.byte 0x04 25.--31. 1. "RESERVED," newline hexmask.long.word 0x04 16.--24. 1. "EVE1_IRQ_1," newline hexmask.long.byte 0x04 9.--15. 1. "RESERVED," newline hexmask.long.word 0x04 0.--8. 1. "EVE1_IRQ_0," line.long 0x08 "CTRL_CORE_EVE_IRQ_2_3," hexmask.long.byte 0x08 25.--31. 1. "RESERVED," newline hexmask.long.word 0x08 16.--24. 1. "EVE1_IRQ_3," newline hexmask.long.byte 0x08 9.--15. 1. "RESERVED," newline hexmask.long.word 0x08 0.--8. 1. "EVE1_IRQ_2," line.long 0x0C "CTRL_CORE_EVE_IRQ_4_5," hexmask.long.byte 0x0C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x0C 16.--24. 1. "EVE1_IRQ_5," newline hexmask.long.byte 0x0C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--8. 1. "EVE1_IRQ_4," line.long 0x10 "CTRL_CORE_EVE_IRQ_6_7," hexmask.long.byte 0x10 25.--31. 1. "RESERVED," newline hexmask.long.word 0x10 16.--24. 1. "EVE1_IRQ_7," newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED," newline hexmask.long.word 0x10 0.--8. 1. "EVE1_IRQ_6," group.long 0x7E0++0x73 line.long 0x00 "CTRL_CORE_IPU_IRQ_23_24," hexmask.long.byte 0x00 25.--31. 1. "RESERVED," newline hexmask.long.word 0x00 16.--24. 1. "IPU1_IRQ_24," newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline hexmask.long.word 0x00 0.--8. 1. "IPU1_IRQ_23," line.long 0x04 "CTRL_CORE_IPU_IRQ_25_26," hexmask.long.byte 0x04 25.--31. 1. "RESERVED," newline hexmask.long.word 0x04 16.--24. 1. "IPU1_IRQ_26," newline hexmask.long.byte 0x04 9.--15. 1. "RESERVED," newline hexmask.long.word 0x04 0.--8. 1. "IPU1_IRQ_25," line.long 0x08 "CTRL_CORE_IPU_IRQ_27_28," hexmask.long.byte 0x08 25.--31. 1. "RESERVED," newline hexmask.long.word 0x08 16.--24. 1. "IPU1_IRQ_28," newline hexmask.long.byte 0x08 9.--15. 1. "RESERVED," newline hexmask.long.word 0x08 0.--8. 1. "IPU1_IRQ_27," line.long 0x0C "CTRL_CORE_IPU_IRQ_29_30," hexmask.long.byte 0x0C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x0C 16.--24. 1. "IPU1_IRQ_30," newline hexmask.long.byte 0x0C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--8. 1. "IPU1_IRQ_29," line.long 0x10 "CTRL_CORE_IPU_IRQ_31_32," hexmask.long.byte 0x10 25.--31. 1. "RESERVED," newline hexmask.long.word 0x10 16.--24. 1. "IPU1_IRQ_32," newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED," newline hexmask.long.word 0x10 0.--8. 1. "IPU1_IRQ_31," line.long 0x14 "CTRL_CORE_IPU_IRQ_33_34," hexmask.long.byte 0x14 25.--31. 1. "RESERVED," newline hexmask.long.word 0x14 16.--24. 1. "IPU1_IRQ_34," newline hexmask.long.byte 0x14 9.--15. 1. "RESERVED," newline hexmask.long.word 0x14 0.--8. 1. "IPU1_IRQ_33," line.long 0x18 "CTRL_CORE_IPU_IRQ_35_36," hexmask.long.byte 0x18 25.--31. 1. "RESERVED," newline hexmask.long.word 0x18 16.--24. 1. "IPU1_IRQ_36," newline hexmask.long.byte 0x18 9.--15. 1. "RESERVED," newline hexmask.long.word 0x18 0.--8. 1. "IPU1_IRQ_35," line.long 0x1C "CTRL_CORE_IPU_IRQ_37_38," hexmask.long.byte 0x1C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x1C 16.--24. 1. "IPU1_IRQ_38," newline hexmask.long.byte 0x1C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x1C 0.--8. 1. "IPU1_IRQ_37," line.long 0x20 "CTRL_CORE_IPU_IRQ_39_40," hexmask.long.byte 0x20 25.--31. 1. "RESERVED," newline hexmask.long.word 0x20 16.--24. 1. "IPU1_IRQ_40," newline hexmask.long.byte 0x20 9.--15. 1. "RESERVED," newline hexmask.long.word 0x20 0.--8. 1. "IPU1_IRQ_39," line.long 0x24 "CTRL_CORE_IPU_IRQ_41_42," hexmask.long.byte 0x24 25.--31. 1. "RESERVED," newline hexmask.long.word 0x24 16.--24. 1. "IPU1_IRQ_42," newline hexmask.long.byte 0x24 9.--15. 1. "RESERVED," newline hexmask.long.word 0x24 0.--8. 1. "IPU1_IRQ_41," line.long 0x28 "CTRL_CORE_IPU_IRQ_43_44," hexmask.long.byte 0x28 25.--31. 1. "RESERVED," newline hexmask.long.word 0x28 16.--24. 1. "IPU1_IRQ_44," newline hexmask.long.byte 0x28 9.--15. 1. "RESERVED," newline hexmask.long.word 0x28 0.--8. 1. "IPU1_IRQ_43," line.long 0x2C "CTRL_CORE_IPU_IRQ_45_46," hexmask.long.byte 0x2C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x2C 16.--24. 1. "IPU1_IRQ_46," newline hexmask.long.byte 0x2C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x2C 0.--8. 1. "IPU1_IRQ_45," line.long 0x30 "CTRL_CORE_IPU_IRQ_47_48," hexmask.long.byte 0x30 25.--31. 1. "RESERVED," newline hexmask.long.word 0x30 16.--24. 1. "IPU1_IRQ_48," newline hexmask.long.byte 0x30 9.--15. 1. "RESERVED," newline hexmask.long.word 0x30 0.--8. 1. "IPU1_IRQ_47," line.long 0x34 "CTRL_CORE_IPU_IRQ_49_50," hexmask.long.byte 0x34 25.--31. 1. "RESERVED," newline hexmask.long.word 0x34 16.--24. 1. "IPU1_IRQ_50," newline hexmask.long.byte 0x34 9.--15. 1. "RESERVED," newline hexmask.long.word 0x34 0.--8. 1. "IPU1_IRQ_49," line.long 0x38 "CTRL_CORE_IPU_IRQ_51_52," hexmask.long.byte 0x38 25.--31. 1. "RESERVED," newline hexmask.long.word 0x38 16.--24. 1. "IPU1_IRQ_52," newline hexmask.long.byte 0x38 9.--15. 1. "RESERVED," newline hexmask.long.word 0x38 0.--8. 1. "IPU1_IRQ_51," line.long 0x3C "CTRL_CORE_IPU_IRQ_53_54," hexmask.long.byte 0x3C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x3C 16.--24. 1. "IPU1_IRQ_54," newline hexmask.long.byte 0x3C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x3C 0.--8. 1. "IPU1_IRQ_53," line.long 0x40 "CTRL_CORE_IPU_IRQ_55_56," hexmask.long.byte 0x40 25.--31. 1. "RESERVED," newline hexmask.long.word 0x40 16.--24. 1. "IPU1_IRQ_56," newline hexmask.long.byte 0x40 9.--15. 1. "RESERVED," newline hexmask.long.word 0x40 0.--8. 1. "IPU1_IRQ_55," line.long 0x44 "CTRL_CORE_IPU_IRQ_57_58," hexmask.long.byte 0x44 25.--31. 1. "RESERVED," newline hexmask.long.word 0x44 16.--24. 1. "IPU1_IRQ_58," newline hexmask.long.byte 0x44 9.--15. 1. "RESERVED," newline hexmask.long.word 0x44 0.--8. 1. "IPU1_IRQ_57," line.long 0x48 "CTRL_CORE_IPU_IRQ_59_60," hexmask.long.byte 0x48 25.--31. 1. "RESERVED," newline hexmask.long.word 0x48 16.--24. 1. "IPU1_IRQ_60," newline hexmask.long.byte 0x48 9.--15. 1. "RESERVED," newline hexmask.long.word 0x48 0.--8. 1. "IPU1_IRQ_59," line.long 0x4C "CTRL_CORE_IPU_IRQ_61_62," hexmask.long.byte 0x4C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x4C 16.--24. 1. "IPU1_IRQ_62," newline hexmask.long.byte 0x4C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x4C 0.--8. 1. "IPU1_IRQ_61," line.long 0x50 "CTRL_CORE_IPU_IRQ_63_64," hexmask.long.byte 0x50 25.--31. 1. "RESERVED," newline hexmask.long.word 0x50 16.--24. 1. "IPU1_IRQ_64," newline hexmask.long.byte 0x50 9.--15. 1. "RESERVED," newline hexmask.long.word 0x50 0.--8. 1. "IPU1_IRQ_63," line.long 0x54 "CTRL_CORE_IPU_IRQ_65_66," hexmask.long.byte 0x54 25.--31. 1. "RESERVED," newline hexmask.long.word 0x54 16.--24. 1. "IPU1_IRQ_66," newline hexmask.long.byte 0x54 9.--15. 1. "RESERVED," newline hexmask.long.word 0x54 0.--8. 1. "IPU1_IRQ_65," line.long 0x58 "CTRL_CORE_IPU_IRQ_67_68," hexmask.long.byte 0x58 25.--31. 1. "RESERVED," newline hexmask.long.word 0x58 16.--24. 1. "IPU1_IRQ_68," newline hexmask.long.byte 0x58 9.--15. 1. "RESERVED," newline hexmask.long.word 0x58 0.--8. 1. "IPU1_IRQ_67," line.long 0x5C "CTRL_CORE_IPU_IRQ_69_70," hexmask.long.byte 0x5C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x5C 16.--24. 1. "IPU1_IRQ_70," newline hexmask.long.byte 0x5C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x5C 0.--8. 1. "IPU1_IRQ_69," line.long 0x60 "CTRL_CORE_IPU_IRQ_71_72," hexmask.long.byte 0x60 25.--31. 1. "RESERVED," newline hexmask.long.word 0x60 16.--24. 1. "IPU1_IRQ_72," newline hexmask.long.byte 0x60 9.--15. 1. "RESERVED," newline hexmask.long.word 0x60 0.--8. 1. "IPU1_IRQ_71," line.long 0x64 "CTRL_CORE_IPU_IRQ_73_74," hexmask.long.byte 0x64 25.--31. 1. "RESERVED," newline hexmask.long.word 0x64 16.--24. 1. "IPU1_IRQ_74," newline hexmask.long.byte 0x64 9.--15. 1. "RESERVED," newline hexmask.long.word 0x64 0.--8. 1. "IPU1_IRQ_73," line.long 0x68 "CTRL_CORE_IPU_IRQ_75_76," hexmask.long.byte 0x68 25.--31. 1. "RESERVED," newline hexmask.long.word 0x68 16.--24. 1. "IPU1_IRQ_76," newline hexmask.long.byte 0x68 9.--15. 1. "RESERVED," newline hexmask.long.word 0x68 0.--8. 1. "IPU1_IRQ_75," line.long 0x6C "CTRL_CORE_IPU_IRQ_77_78," hexmask.long.byte 0x6C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x6C 16.--24. 1. "IPU1_IRQ_78," newline hexmask.long.byte 0x6C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x6C 0.--8. 1. "IPU1_IRQ_77," line.long 0x70 "CTRL_CORE_IPU_IRQ_79_80," hexmask.long.tbyte 0x70 9.--31. 1. "RESERVED," newline hexmask.long.word 0x70 0.--8. 1. "IPU1_IRQ_79," group.long 0x948++0xFF line.long 0x00 "CTRL_CORE_DSP1_IRQ_32_33," hexmask.long.byte 0x00 25.--31. 1. "RESERVED," newline hexmask.long.word 0x00 16.--24. 1. "DSP1_IRQ_33," newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline hexmask.long.word 0x00 0.--8. 1. "DSP1_IRQ_32," line.long 0x04 "CTRL_CORE_DSP1_IRQ_34_35," hexmask.long.byte 0x04 25.--31. 1. "RESERVED," newline hexmask.long.word 0x04 16.--24. 1. "DSP1_IRQ_35," newline hexmask.long.byte 0x04 9.--15. 1. "RESERVED," newline hexmask.long.word 0x04 0.--8. 1. "DSP1_IRQ_34," line.long 0x08 "CTRL_CORE_DSP1_IRQ_36_37," hexmask.long.byte 0x08 25.--31. 1. "RESERVED," newline hexmask.long.word 0x08 16.--24. 1. "DSP1_IRQ_37," newline hexmask.long.byte 0x08 9.--15. 1. "RESERVED," newline hexmask.long.word 0x08 0.--8. 1. "DSP1_IRQ_36," line.long 0x0C "CTRL_CORE_DSP1_IRQ_38_39," hexmask.long.byte 0x0C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x0C 16.--24. 1. "DSP1_IRQ_39," newline hexmask.long.byte 0x0C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--8. 1. "DSP1_IRQ_38," line.long 0x10 "CTRL_CORE_DSP1_IRQ_40_41," hexmask.long.byte 0x10 25.--31. 1. "RESERVED," newline hexmask.long.word 0x10 16.--24. 1. "DSP1_IRQ_41," newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED," newline hexmask.long.word 0x10 0.--8. 1. "DSP1_IRQ_40," line.long 0x14 "CTRL_CORE_DSP1_IRQ_42_43," hexmask.long.byte 0x14 25.--31. 1. "RESERVED," newline hexmask.long.word 0x14 16.--24. 1. "DSP1_IRQ_43," newline hexmask.long.byte 0x14 9.--15. 1. "RESERVED," newline hexmask.long.word 0x14 0.--8. 1. "DSP1_IRQ_42," line.long 0x18 "CTRL_CORE_DSP1_IRQ_44_45," hexmask.long.byte 0x18 25.--31. 1. "RESERVED," newline hexmask.long.word 0x18 16.--24. 1. "DSP1_IRQ_45," newline hexmask.long.byte 0x18 9.--15. 1. "RESERVED," newline hexmask.long.word 0x18 0.--8. 1. "DSP1_IRQ_44," line.long 0x1C "CTRL_CORE_DSP1_IRQ_46_47," hexmask.long.byte 0x1C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x1C 16.--24. 1. "DSP1_IRQ_47," newline hexmask.long.byte 0x1C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x1C 0.--8. 1. "DSP1_IRQ_46," line.long 0x20 "CTRL_CORE_DSP1_IRQ_48_49," hexmask.long.byte 0x20 25.--31. 1. "RESERVED," newline hexmask.long.word 0x20 16.--24. 1. "DSP1_IRQ_49," newline hexmask.long.byte 0x20 9.--15. 1. "RESERVED," newline hexmask.long.word 0x20 0.--8. 1. "DSP1_IRQ_48," line.long 0x24 "CTRL_CORE_DSP1_IRQ_50_51," hexmask.long.byte 0x24 25.--31. 1. "RESERVED," newline hexmask.long.word 0x24 16.--24. 1. "DSP1_IRQ_51," newline hexmask.long.byte 0x24 9.--15. 1. "RESERVED," newline hexmask.long.word 0x24 0.--8. 1. "DSP1_IRQ_50," line.long 0x28 "CTRL_CORE_DSP1_IRQ_52_53," hexmask.long.byte 0x28 25.--31. 1. "RESERVED," newline hexmask.long.word 0x28 16.--24. 1. "DSP1_IRQ_53," newline hexmask.long.byte 0x28 9.--15. 1. "RESERVED," newline hexmask.long.word 0x28 0.--8. 1. "DSP1_IRQ_52," line.long 0x2C "CTRL_CORE_DSP1_IRQ_54_55," hexmask.long.byte 0x2C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x2C 16.--24. 1. "DSP1_IRQ_55," newline hexmask.long.byte 0x2C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x2C 0.--8. 1. "DSP1_IRQ_54," line.long 0x30 "CTRL_CORE_DSP1_IRQ_56_57," hexmask.long.byte 0x30 25.--31. 1. "RESERVED," newline hexmask.long.word 0x30 16.--24. 1. "DSP1_IRQ_57," newline hexmask.long.byte 0x30 9.--15. 1. "RESERVED," newline hexmask.long.word 0x30 0.--8. 1. "DSP1_IRQ_56," line.long 0x34 "CTRL_CORE_DSP1_IRQ_58_59," hexmask.long.byte 0x34 25.--31. 1. "RESERVED," newline hexmask.long.word 0x34 16.--24. 1. "DSP1_IRQ_59," newline hexmask.long.byte 0x34 9.--15. 1. "RESERVED," newline hexmask.long.word 0x34 0.--8. 1. "DSP1_IRQ_58," line.long 0x38 "CTRL_CORE_DSP1_IRQ_60_61," hexmask.long.byte 0x38 25.--31. 1. "RESERVED," newline hexmask.long.word 0x38 16.--24. 1. "DSP1_IRQ_61," newline hexmask.long.byte 0x38 9.--15. 1. "RESERVED," newline hexmask.long.word 0x38 0.--8. 1. "DSP1_IRQ_60," line.long 0x3C "CTRL_CORE_DSP1_IRQ_62_63," hexmask.long.byte 0x3C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x3C 16.--24. 1. "DSP1_IRQ_63," newline hexmask.long.byte 0x3C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x3C 0.--8. 1. "DSP1_IRQ_62," line.long 0x40 "CTRL_CORE_DSP1_IRQ_64_65," hexmask.long.byte 0x40 25.--31. 1. "RESERVED," newline hexmask.long.word 0x40 16.--24. 1. "DSP1_IRQ_65," newline hexmask.long.byte 0x40 9.--15. 1. "RESERVED," newline hexmask.long.word 0x40 0.--8. 1. "DSP1_IRQ_64," line.long 0x44 "CTRL_CORE_DSP1_IRQ_66_67," hexmask.long.byte 0x44 25.--31. 1. "RESERVED," newline hexmask.long.word 0x44 16.--24. 1. "DSP1_IRQ_67," newline hexmask.long.byte 0x44 9.--15. 1. "RESERVED," newline hexmask.long.word 0x44 0.--8. 1. "DSP1_IRQ_66," line.long 0x48 "CTRL_CORE_DSP1_IRQ_68_69," hexmask.long.byte 0x48 25.--31. 1. "RESERVED," newline hexmask.long.word 0x48 16.--24. 1. "DSP1_IRQ_69," newline hexmask.long.byte 0x48 9.--15. 1. "RESERVED," newline hexmask.long.word 0x48 0.--8. 1. "DSP1_IRQ_68," line.long 0x4C "CTRL_CORE_DSP1_IRQ_70_71," hexmask.long.byte 0x4C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x4C 16.--24. 1. "DSP1_IRQ_71," newline hexmask.long.byte 0x4C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x4C 0.--8. 1. "DSP1_IRQ_70," line.long 0x50 "CTRL_CORE_DSP1_IRQ_72_73," hexmask.long.byte 0x50 25.--31. 1. "RESERVED," newline hexmask.long.word 0x50 16.--24. 1. "DSP1_IRQ_73," newline hexmask.long.byte 0x50 9.--15. 1. "RESERVED," newline hexmask.long.word 0x50 0.--8. 1. "DSP1_IRQ_72," line.long 0x54 "CTRL_CORE_DSP1_IRQ_74_75," hexmask.long.byte 0x54 25.--31. 1. "RESERVED," newline hexmask.long.word 0x54 16.--24. 1. "DSP1_IRQ_75," newline hexmask.long.byte 0x54 9.--15. 1. "RESERVED," newline hexmask.long.word 0x54 0.--8. 1. "DSP1_IRQ_74," line.long 0x58 "CTRL_CORE_DSP1_IRQ_76_77," hexmask.long.byte 0x58 25.--31. 1. "RESERVED," newline hexmask.long.word 0x58 16.--24. 1. "DSP1_IRQ_77," newline hexmask.long.byte 0x58 9.--15. 1. "RESERVED," newline hexmask.long.word 0x58 0.--8. 1. "DSP1_IRQ_76," line.long 0x5C "CTRL_CORE_DSP1_IRQ_78_79," hexmask.long.byte 0x5C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x5C 16.--24. 1. "DSP1_IRQ_79," newline hexmask.long.byte 0x5C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x5C 0.--8. 1. "DSP1_IRQ_78," line.long 0x60 "CTRL_CORE_DSP1_IRQ_80_81," hexmask.long.byte 0x60 25.--31. 1. "RESERVED," newline hexmask.long.word 0x60 16.--24. 1. "DSP1_IRQ_81," newline hexmask.long.byte 0x60 9.--15. 1. "RESERVED," newline hexmask.long.word 0x60 0.--8. 1. "DSP1_IRQ_80," line.long 0x64 "CTRL_CORE_DSP1_IRQ_82_83," hexmask.long.byte 0x64 25.--31. 1. "RESERVED," newline hexmask.long.word 0x64 16.--24. 1. "DSP1_IRQ_83," newline hexmask.long.byte 0x64 9.--15. 1. "RESERVED," newline hexmask.long.word 0x64 0.--8. 1. "DSP1_IRQ_82," line.long 0x68 "CTRL_CORE_DSP1_IRQ_84_85," hexmask.long.byte 0x68 25.--31. 1. "RESERVED," newline hexmask.long.word 0x68 16.--24. 1. "DSP1_IRQ_85," newline hexmask.long.byte 0x68 9.--15. 1. "RESERVED," newline hexmask.long.word 0x68 0.--8. 1. "DSP1_IRQ_84," line.long 0x6C "CTRL_CORE_DSP1_IRQ_86_87," hexmask.long.byte 0x6C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x6C 16.--24. 1. "DSP1_IRQ_87," newline hexmask.long.byte 0x6C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x6C 0.--8. 1. "DSP1_IRQ_86," line.long 0x70 "CTRL_CORE_DSP1_IRQ_88_89," hexmask.long.byte 0x70 25.--31. 1. "RESERVED," newline hexmask.long.word 0x70 16.--24. 1. "DSP1_IRQ_89," newline hexmask.long.byte 0x70 9.--15. 1. "RESERVED," newline hexmask.long.word 0x70 0.--8. 1. "DSP1_IRQ_88," line.long 0x74 "CTRL_CORE_DSP1_IRQ_90_91," hexmask.long.byte 0x74 25.--31. 1. "RESERVED," newline hexmask.long.word 0x74 16.--24. 1. "DSP1_IRQ_91," newline hexmask.long.byte 0x74 9.--15. 1. "RESERVED," newline hexmask.long.word 0x74 0.--8. 1. "DSP1_IRQ_90," line.long 0x78 "CTRL_CORE_DSP1_IRQ_92_93," hexmask.long.byte 0x78 25.--31. 1. "RESERVED," newline hexmask.long.word 0x78 16.--24. 1. "DSP1_IRQ_93," newline hexmask.long.byte 0x78 9.--15. 1. "RESERVED," newline hexmask.long.word 0x78 0.--8. 1. "DSP1_IRQ_92," line.long 0x7C "CTRL_CORE_DSP1_IRQ_94_95," hexmask.long.byte 0x7C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x7C 16.--24. 1. "DSP1_IRQ_95," newline hexmask.long.byte 0x7C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x7C 0.--8. 1. "DSP1_IRQ_94," line.long 0x80 "CTRL_CORE_DSP2_IRQ_32_33," hexmask.long.byte 0x80 25.--31. 1. "RESERVED," newline hexmask.long.word 0x80 16.--24. 1. "DSP2_IRQ_33," newline hexmask.long.byte 0x80 9.--15. 1. "RESERVED," newline hexmask.long.word 0x80 0.--8. 1. "DSP2_IRQ_32," line.long 0x84 "CTRL_CORE_DSP2_IRQ_34_35," hexmask.long.byte 0x84 25.--31. 1. "RESERVED," newline hexmask.long.word 0x84 16.--24. 1. "DSP2_IRQ_35," newline hexmask.long.byte 0x84 9.--15. 1. "RESERVED," newline hexmask.long.word 0x84 0.--8. 1. "DSP2_IRQ_34," line.long 0x88 "CTRL_CORE_DSP2_IRQ_36_37," hexmask.long.byte 0x88 25.--31. 1. "RESERVED," newline hexmask.long.word 0x88 16.--24. 1. "DSP2_IRQ_37," newline hexmask.long.byte 0x88 9.--15. 1. "RESERVED," newline hexmask.long.word 0x88 0.--8. 1. "DSP2_IRQ_36," line.long 0x8C "CTRL_CORE_DSP2_IRQ_38_39," hexmask.long.byte 0x8C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x8C 16.--24. 1. "DSP2_IRQ_39," newline hexmask.long.byte 0x8C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x8C 0.--8. 1. "DSP2_IRQ_38," line.long 0x90 "CTRL_CORE_DSP2_IRQ_40_41," hexmask.long.byte 0x90 25.--31. 1. "RESERVED," newline hexmask.long.word 0x90 16.--24. 1. "DSP2_IRQ_41," newline hexmask.long.byte 0x90 9.--15. 1. "RESERVED," newline hexmask.long.word 0x90 0.--8. 1. "DSP2_IRQ_40," line.long 0x94 "CTRL_CORE_DSP2_IRQ_42_43," hexmask.long.byte 0x94 25.--31. 1. "RESERVED," newline hexmask.long.word 0x94 16.--24. 1. "DSP2_IRQ_43," newline hexmask.long.byte 0x94 9.--15. 1. "RESERVED," newline hexmask.long.word 0x94 0.--8. 1. "DSP2_IRQ_42," line.long 0x98 "CTRL_CORE_DSP2_IRQ_44_45," hexmask.long.byte 0x98 25.--31. 1. "RESERVED," newline hexmask.long.word 0x98 16.--24. 1. "DSP2_IRQ_45," newline hexmask.long.byte 0x98 9.--15. 1. "RESERVED," newline hexmask.long.word 0x98 0.--8. 1. "DSP2_IRQ_44," line.long 0x9C "CTRL_CORE_DSP2_IRQ_46_47," hexmask.long.byte 0x9C 25.--31. 1. "RESERVED," newline hexmask.long.word 0x9C 16.--24. 1. "DSP2_IRQ_47," newline hexmask.long.byte 0x9C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x9C 0.--8. 1. "DSP2_IRQ_46," line.long 0xA0 "CTRL_CORE_DSP2_IRQ_48_49," hexmask.long.byte 0xA0 25.--31. 1. "RESERVED," newline hexmask.long.word 0xA0 16.--24. 1. "DSP2_IRQ_49," newline hexmask.long.byte 0xA0 9.--15. 1. "RESERVED," newline hexmask.long.word 0xA0 0.--8. 1. "DSP2_IRQ_48," line.long 0xA4 "CTRL_CORE_DSP2_IRQ_50_51," hexmask.long.byte 0xA4 25.--31. 1. "RESERVED," newline hexmask.long.word 0xA4 16.--24. 1. "DSP2_IRQ_51," newline hexmask.long.byte 0xA4 9.--15. 1. "RESERVED," newline hexmask.long.word 0xA4 0.--8. 1. "DSP2_IRQ_50," line.long 0xA8 "CTRL_CORE_DSP2_IRQ_52_53," hexmask.long.byte 0xA8 25.--31. 1. "RESERVED," newline hexmask.long.word 0xA8 16.--24. 1. "DSP2_IRQ_53," newline hexmask.long.byte 0xA8 9.--15. 1. "RESERVED," newline hexmask.long.word 0xA8 0.--8. 1. "DSP2_IRQ_52," line.long 0xAC "CTRL_CORE_DSP2_IRQ_54_55," hexmask.long.byte 0xAC 25.--31. 1. "RESERVED," newline hexmask.long.word 0xAC 16.--24. 1. "DSP2_IRQ_55," newline hexmask.long.byte 0xAC 9.--15. 1. "RESERVED," newline hexmask.long.word 0xAC 0.--8. 1. "DSP2_IRQ_54," line.long 0xB0 "CTRL_CORE_DSP2_IRQ_56_57," hexmask.long.byte 0xB0 25.--31. 1. "RESERVED," newline hexmask.long.word 0xB0 16.--24. 1. "DSP2_IRQ_57," newline hexmask.long.byte 0xB0 9.--15. 1. "RESERVED," newline hexmask.long.word 0xB0 0.--8. 1. "DSP2_IRQ_56," line.long 0xB4 "CTRL_CORE_DSP2_IRQ_58_59," hexmask.long.byte 0xB4 25.--31. 1. "RESERVED," newline hexmask.long.word 0xB4 16.--24. 1. "DSP2_IRQ_59," newline hexmask.long.byte 0xB4 9.--15. 1. "RESERVED," newline hexmask.long.word 0xB4 0.--8. 1. "DSP2_IRQ_58," line.long 0xB8 "CTRL_CORE_DSP2_IRQ_60_61," hexmask.long.byte 0xB8 25.--31. 1. "RESERVED," newline hexmask.long.word 0xB8 16.--24. 1. "DSP2_IRQ_61," newline hexmask.long.byte 0xB8 9.--15. 1. "RESERVED," newline hexmask.long.word 0xB8 0.--8. 1. "DSP2_IRQ_60," line.long 0xBC "CTRL_CORE_DSP2_IRQ_62_63," hexmask.long.byte 0xBC 25.--31. 1. "RESERVED," newline hexmask.long.word 0xBC 16.--24. 1. "DSP2_IRQ_63," newline hexmask.long.byte 0xBC 9.--15. 1. "RESERVED," newline hexmask.long.word 0xBC 0.--8. 1. "DSP2_IRQ_62," line.long 0xC0 "CTRL_CORE_DSP2_IRQ_64_65," hexmask.long.byte 0xC0 25.--31. 1. "RESERVED," newline hexmask.long.word 0xC0 16.--24. 1. "DSP2_IRQ_65," newline hexmask.long.byte 0xC0 9.--15. 1. "RESERVED," newline hexmask.long.word 0xC0 0.--8. 1. "DSP2_IRQ_64," line.long 0xC4 "CTRL_CORE_DSP2_IRQ_66_67," hexmask.long.byte 0xC4 25.--31. 1. "RESERVED," newline hexmask.long.word 0xC4 16.--24. 1. "DSP2_IRQ_67," newline hexmask.long.byte 0xC4 9.--15. 1. "RESERVED," newline hexmask.long.word 0xC4 0.--8. 1. "DSP2_IRQ_66," line.long 0xC8 "CTRL_CORE_DSP2_IRQ_68_69," hexmask.long.byte 0xC8 25.--31. 1. "RESERVED," newline hexmask.long.word 0xC8 16.--24. 1. "DSP2_IRQ_69," newline hexmask.long.byte 0xC8 9.--15. 1. "RESERVED," newline hexmask.long.word 0xC8 0.--8. 1. "DSP2_IRQ_68," line.long 0xCC "CTRL_CORE_DSP2_IRQ_70_71," hexmask.long.byte 0xCC 25.--31. 1. "RESERVED," newline hexmask.long.word 0xCC 16.--24. 1. "DSP2_IRQ_71," newline hexmask.long.byte 0xCC 9.--15. 1. "RESERVED," newline hexmask.long.word 0xCC 0.--8. 1. "DSP2_IRQ_70," line.long 0xD0 "CTRL_CORE_DSP2_IRQ_72_73," hexmask.long.byte 0xD0 25.--31. 1. "RESERVED," newline hexmask.long.word 0xD0 16.--24. 1. "DSP2_IRQ_73," newline hexmask.long.byte 0xD0 9.--15. 1. "RESERVED," newline hexmask.long.word 0xD0 0.--8. 1. "DSP2_IRQ_72," line.long 0xD4 "CTRL_CORE_DSP2_IRQ_74_75," hexmask.long.byte 0xD4 25.--31. 1. "RESERVED," newline hexmask.long.word 0xD4 16.--24. 1. "DSP2_IRQ_75," newline hexmask.long.byte 0xD4 9.--15. 1. "RESERVED," newline hexmask.long.word 0xD4 0.--8. 1. "DSP2_IRQ_74," line.long 0xD8 "CTRL_CORE_DSP2_IRQ_76_77," hexmask.long.byte 0xD8 25.--31. 1. "RESERVED," newline hexmask.long.word 0xD8 16.--24. 1. "DSP2_IRQ_77," newline hexmask.long.byte 0xD8 9.--15. 1. "RESERVED," newline hexmask.long.word 0xD8 0.--8. 1. "DSP2_IRQ_76," line.long 0xDC "CTRL_CORE_DSP2_IRQ_78_79," hexmask.long.byte 0xDC 25.--31. 1. "RESERVED," newline hexmask.long.word 0xDC 16.--24. 1. "DSP2_IRQ_79," newline hexmask.long.byte 0xDC 9.--15. 1. "RESERVED," newline hexmask.long.word 0xDC 0.--8. 1. "DSP2_IRQ_78," line.long 0xE0 "CTRL_CORE_DSP2_IRQ_80_81," hexmask.long.byte 0xE0 25.--31. 1. "RESERVED," newline hexmask.long.word 0xE0 16.--24. 1. "DSP2_IRQ_81," newline hexmask.long.byte 0xE0 9.--15. 1. "RESERVED," newline hexmask.long.word 0xE0 0.--8. 1. "DSP2_IRQ_80," line.long 0xE4 "CTRL_CORE_DSP2_IRQ_82_83," hexmask.long.byte 0xE4 25.--31. 1. "RESERVED," newline hexmask.long.word 0xE4 16.--24. 1. "DSP2_IRQ_83," newline hexmask.long.byte 0xE4 9.--15. 1. "RESERVED," newline hexmask.long.word 0xE4 0.--8. 1. "DSP2_IRQ_82," line.long 0xE8 "CTRL_CORE_DSP2_IRQ_84_85," hexmask.long.byte 0xE8 25.--31. 1. "RESERVED," newline hexmask.long.word 0xE8 16.--24. 1. "DSP2_IRQ_85," newline hexmask.long.byte 0xE8 9.--15. 1. "RESERVED," newline hexmask.long.word 0xE8 0.--8. 1. "DSP2_IRQ_84," line.long 0xEC "CTRL_CORE_DSP2_IRQ_86_87," hexmask.long.byte 0xEC 25.--31. 1. "RESERVED," newline hexmask.long.word 0xEC 16.--24. 1. "DSP2_IRQ_87," newline hexmask.long.byte 0xEC 9.--15. 1. "RESERVED," newline hexmask.long.word 0xEC 0.--8. 1. "DSP2_IRQ_86," line.long 0xF0 "CTRL_CORE_DSP2_IRQ_88_89," hexmask.long.byte 0xF0 25.--31. 1. "RESERVED," newline hexmask.long.word 0xF0 16.--24. 1. "DSP2_IRQ_89," newline hexmask.long.byte 0xF0 9.--15. 1. "RESERVED," newline hexmask.long.word 0xF0 0.--8. 1. "DSP2_IRQ_88," line.long 0xF4 "CTRL_CORE_DSP2_IRQ_90_91," hexmask.long.byte 0xF4 25.--31. 1. "RESERVED," newline hexmask.long.word 0xF4 16.--24. 1. "DSP2_IRQ_91," newline hexmask.long.byte 0xF4 9.--15. 1. "RESERVED," newline hexmask.long.word 0xF4 0.--8. 1. "DSP2_IRQ_90," line.long 0xF8 "CTRL_CORE_DSP2_IRQ_92_93," hexmask.long.byte 0xF8 25.--31. 1. "RESERVED," newline hexmask.long.word 0xF8 16.--24. 1. "DSP2_IRQ_93," newline hexmask.long.byte 0xF8 9.--15. 1. "RESERVED," newline hexmask.long.word 0xF8 0.--8. 1. "DSP2_IRQ_92," line.long 0xFC "CTRL_CORE_DSP2_IRQ_94_95," hexmask.long.byte 0xFC 25.--31. 1. "RESERVED," newline hexmask.long.word 0xFC 16.--24. 1. "DSP2_IRQ_95," newline hexmask.long.byte 0xFC 9.--15. 1. "RESERVED," newline hexmask.long.word 0xFC 0.--8. 1. "DSP2_IRQ_94," group.long 0xC78++0xCF line.long 0x00 "CTRL_CORE_DMA_EDMA_DREQ_0_1," hexmask.long.byte 0x00 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x00 16.--23. 1. "DMA_EDMA_DREQ_1_IRQ_1," newline hexmask.long.byte 0x00 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--7. 1. "DMA_EDMA_DREQ_0_IRQ_0," line.long 0x04 "CTRL_CORE_DMA_EDMA_DREQ_2_3," hexmask.long.byte 0x04 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x04 16.--23. 1. "DMA_EDMA_DREQ_3_IRQ_3," newline hexmask.long.byte 0x04 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x04 0.--7. 1. "DMA_EDMA_DREQ_2_IRQ_2," line.long 0x08 "CTRL_CORE_DMA_EDMA_DREQ_4_5," hexmask.long.byte 0x08 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x08 16.--23. 1. "DMA_EDMA_DREQ_5_IRQ_5," newline hexmask.long.byte 0x08 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x08 0.--7. 1. "DMA_EDMA_DREQ_4_IRQ_4," line.long 0x0C "CTRL_CORE_DMA_EDMA_DREQ_6_7," hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x0C 16.--23. 1. "DMA_EDMA_DREQ_7_IRQ_7," newline hexmask.long.byte 0x0C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x0C 0.--7. 1. "DMA_EDMA_DREQ_6_IRQ_6," line.long 0x10 "CTRL_CORE_DMA_EDMA_DREQ_8_9," hexmask.long.byte 0x10 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x10 16.--23. 1. "DMA_EDMA_DREQ_9_IRQ_9," newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x10 0.--7. 1. "DMA_EDMA_DREQ_8_IRQ_8," line.long 0x14 "CTRL_CORE_DMA_EDMA_DREQ_10_11," hexmask.long.byte 0x14 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x14 16.--23. 1. "DMA_EDMA_DREQ_11_IRQ_11," newline hexmask.long.byte 0x14 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x14 0.--7. 1. "DMA_EDMA_DREQ_10_IRQ_10," line.long 0x18 "CTRL_CORE_DMA_EDMA_DREQ_12_13," hexmask.long.byte 0x18 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 16.--23. 1. "DMA_EDMA_DREQ_13_IRQ_13," newline hexmask.long.byte 0x18 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x18 0.--7. 1. "DMA_EDMA_DREQ_12_IRQ_12," line.long 0x1C "CTRL_CORE_DMA_EDMA_DREQ_14_15," hexmask.long.byte 0x1C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x1C 16.--23. 1. "DMA_EDMA_DREQ_15_IRQ_15," newline hexmask.long.byte 0x1C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x1C 0.--7. 1. "DMA_EDMA_DREQ_14_IRQ_14," line.long 0x20 "CTRL_CORE_DMA_EDMA_DREQ_16_17," hexmask.long.byte 0x20 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x20 16.--23. 1. "DMA_EDMA_DREQ_17_IRQ_17," newline hexmask.long.byte 0x20 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x20 0.--7. 1. "DMA_EDMA_DREQ_16_IRQ_16," line.long 0x24 "CTRL_CORE_DMA_EDMA_DREQ_18_19," hexmask.long.byte 0x24 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x24 16.--23. 1. "DMA_EDMA_DREQ_19_IRQ_19," newline hexmask.long.byte 0x24 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x24 0.--7. 1. "DMA_EDMA_DREQ_18_IRQ_18," line.long 0x28 "CTRL_CORE_DMA_EDMA_DREQ_20_21," hexmask.long.byte 0x28 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x28 16.--23. 1. "DMA_EDMA_DREQ_21_IRQ_21," newline hexmask.long.byte 0x28 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x28 0.--7. 1. "DMA_EDMA_DREQ_20_IRQ_20," line.long 0x2C "CTRL_CORE_DMA_EDMA_DREQ_22_23," hexmask.long.byte 0x2C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x2C 16.--23. 1. "DMA_EDMA_DREQ_23_IRQ_23," newline hexmask.long.byte 0x2C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x2C 0.--7. 1. "DMA_EDMA_DREQ_22_IRQ_22," line.long 0x30 "CTRL_CORE_DMA_EDMA_DREQ_24_25," hexmask.long.byte 0x30 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x30 16.--23. 1. "DMA_EDMA_DREQ_25_IRQ_25," newline hexmask.long.byte 0x30 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x30 0.--7. 1. "DMA_EDMA_DREQ_24_IRQ_24," line.long 0x34 "CTRL_CORE_DMA_EDMA_DREQ_26_27," hexmask.long.byte 0x34 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x34 16.--23. 1. "DMA_EDMA_DREQ_27_IRQ_27," newline hexmask.long.byte 0x34 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x34 0.--7. 1. "DMA_EDMA_DREQ_26_IRQ_26," line.long 0x38 "CTRL_CORE_DMA_EDMA_DREQ_28_29," hexmask.long.byte 0x38 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x38 16.--23. 1. "DMA_EDMA_DREQ_29_IRQ_29," newline hexmask.long.byte 0x38 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x38 0.--7. 1. "DMA_EDMA_DREQ_28_IRQ_28," line.long 0x3C "CTRL_CORE_DMA_EDMA_DREQ_30_31," hexmask.long.byte 0x3C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x3C 16.--23. 1. "DMA_EDMA_DREQ_31_IRQ_31," newline hexmask.long.byte 0x3C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x3C 0.--7. 1. "DMA_EDMA_DREQ_30_IRQ_30," line.long 0x40 "CTRL_CORE_DMA_EDMA_DREQ_32_33," hexmask.long.byte 0x40 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x40 16.--23. 1. "DMA_EDMA_DREQ_33_IRQ_33," newline hexmask.long.byte 0x40 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x40 0.--7. 1. "DMA_EDMA_DREQ_32_IRQ_32," line.long 0x44 "CTRL_CORE_DMA_EDMA_DREQ_34_35," hexmask.long.byte 0x44 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x44 16.--23. 1. "DMA_EDMA_DREQ_35_IRQ_35," newline hexmask.long.byte 0x44 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x44 0.--7. 1. "DMA_EDMA_DREQ_34_IRQ_34," line.long 0x48 "CTRL_CORE_DMA_EDMA_DREQ_36_37," hexmask.long.byte 0x48 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x48 16.--23. 1. "DMA_EDMA_DREQ_37_IRQ_37," newline hexmask.long.byte 0x48 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x48 0.--7. 1. "DMA_EDMA_DREQ_36_IRQ_36," line.long 0x4C "CTRL_CORE_DMA_EDMA_DREQ_38_39," hexmask.long.byte 0x4C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x4C 16.--23. 1. "DMA_EDMA_DREQ_39_IRQ_39," newline hexmask.long.byte 0x4C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x4C 0.--7. 1. "DMA_EDMA_DREQ_38_IRQ_38," line.long 0x50 "CTRL_CORE_DMA_EDMA_DREQ_40_41," hexmask.long.byte 0x50 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x50 16.--23. 1. "DMA_EDMA_DREQ_41_IRQ_41," newline hexmask.long.byte 0x50 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x50 0.--7. 1. "DMA_EDMA_DREQ_40_IRQ_40," line.long 0x54 "CTRL_CORE_DMA_EDMA_DREQ_42_43," hexmask.long.byte 0x54 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x54 16.--23. 1. "DMA_EDMA_DREQ_43_IRQ_43," newline hexmask.long.byte 0x54 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x54 0.--7. 1. "DMA_EDMA_DREQ_42_IRQ_42," line.long 0x58 "CTRL_CORE_DMA_EDMA_DREQ_44_45," hexmask.long.byte 0x58 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x58 16.--23. 1. "DMA_EDMA_DREQ_45_IRQ_45," newline hexmask.long.byte 0x58 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x58 0.--7. 1. "DMA_EDMA_DREQ_44_IRQ_44," line.long 0x5C "CTRL_CORE_DMA_EDMA_DREQ_46_47," hexmask.long.byte 0x5C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x5C 16.--23. 1. "DMA_EDMA_DREQ_47_IRQ_47," newline hexmask.long.byte 0x5C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x5C 0.--7. 1. "DMA_EDMA_DREQ_46_IRQ_46," line.long 0x60 "CTRL_CORE_DMA_EDMA_DREQ_48_49," hexmask.long.byte 0x60 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x60 16.--23. 1. "DMA_EDMA_DREQ_49_IRQ_49," newline hexmask.long.byte 0x60 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x60 0.--7. 1. "DMA_EDMA_DREQ_48_IRQ_48," line.long 0x64 "CTRL_CORE_DMA_EDMA_DREQ_50_51," hexmask.long.byte 0x64 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x64 16.--23. 1. "DMA_EDMA_DREQ_51_IRQ_51," newline hexmask.long.byte 0x64 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x64 0.--7. 1. "DMA_EDMA_DREQ_50_IRQ_50," line.long 0x68 "CTRL_CORE_DMA_EDMA_DREQ_52_53," hexmask.long.byte 0x68 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x68 16.--23. 1. "DMA_EDMA_DREQ_53_IRQ_53," newline hexmask.long.byte 0x68 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x68 0.--7. 1. "DMA_EDMA_DREQ_52_IRQ_52," line.long 0x6C "CTRL_CORE_DMA_EDMA_DREQ_54_55," hexmask.long.byte 0x6C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x6C 16.--23. 1. "DMA_EDMA_DREQ_55_IRQ_55," newline hexmask.long.byte 0x6C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x6C 0.--7. 1. "DMA_EDMA_DREQ_54_IRQ_54," line.long 0x70 "CTRL_CORE_DMA_EDMA_DREQ_56_57," hexmask.long.byte 0x70 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x70 16.--23. 1. "DMA_EDMA_DREQ_57_IRQ_57," newline hexmask.long.byte 0x70 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x70 0.--7. 1. "DMA_EDMA_DREQ_56_IRQ_56," line.long 0x74 "CTRL_CORE_DMA_EDMA_DREQ_58_59," hexmask.long.byte 0x74 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x74 16.--23. 1. "DMA_EDMA_DREQ_59_IRQ_59," newline hexmask.long.byte 0x74 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x74 0.--7. 1. "DMA_EDMA_DREQ_58_IRQ_58," line.long 0x78 "CTRL_CORE_DMA_EDMA_DREQ_60_61," hexmask.long.byte 0x78 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x78 16.--23. 1. "DMA_EDMA_DREQ_61_IRQ_61," newline hexmask.long.byte 0x78 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x78 0.--7. 1. "DMA_EDMA_DREQ_60_IRQ_60," line.long 0x7C "CTRL_CORE_DMA_EDMA_DREQ_62_63," hexmask.long.byte 0x7C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x7C 16.--23. 1. "DMA_EDMA_DREQ_63_IRQ_63," newline hexmask.long.byte 0x7C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x7C 0.--7. 1. "DMA_EDMA_DREQ_62_IRQ_62," line.long 0x80 "CTRL_CORE_DMA_DSP1_DREQ_0_1," hexmask.long.byte 0x80 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x80 16.--23. 1. "DMA_DSP1_DREQ_1_IRQ_1," newline hexmask.long.byte 0x80 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x80 0.--7. 1. "DMA_DSP1_DREQ_0_IRQ_0," line.long 0x84 "CTRL_CORE_DMA_DSP1_DREQ_2_3," hexmask.long.byte 0x84 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x84 16.--23. 1. "DMA_DSP1_DREQ_3_IRQ_3," newline hexmask.long.byte 0x84 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x84 0.--7. 1. "DMA_DSP1_DREQ_2_IRQ_2," line.long 0x88 "CTRL_CORE_DMA_DSP1_DREQ_4_5," hexmask.long.byte 0x88 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x88 16.--23. 1. "DMA_DSP1_DREQ_5_IRQ_5," newline hexmask.long.byte 0x88 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x88 0.--7. 1. "DMA_DSP1_DREQ_4_IRQ_4," line.long 0x8C "CTRL_CORE_DMA_DSP1_DREQ_6_7," hexmask.long.byte 0x8C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x8C 16.--23. 1. "DMA_DSP1_DREQ_7_IRQ_7," newline hexmask.long.byte 0x8C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x8C 0.--7. 1. "DMA_DSP1_DREQ_6_IRQ_6," line.long 0x90 "CTRL_CORE_DMA_DSP1_DREQ_8_9," hexmask.long.byte 0x90 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x90 16.--23. 1. "DMA_DSP1_DREQ_9_IRQ_9," newline hexmask.long.byte 0x90 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x90 0.--7. 1. "DMA_DSP1_DREQ_8_IRQ_8," line.long 0x94 "CTRL_CORE_DMA_DSP1_DREQ_10_11," hexmask.long.byte 0x94 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x94 16.--23. 1. "DMA_DSP1_DREQ_11_IRQ_11," newline hexmask.long.byte 0x94 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x94 0.--7. 1. "DMA_DSP1_DREQ_10_IRQ_10," line.long 0x98 "CTRL_CORE_DMA_DSP1_DREQ_12_13," hexmask.long.byte 0x98 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x98 16.--23. 1. "DMA_DSP1_DREQ_13_IRQ_13," newline hexmask.long.byte 0x98 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x98 0.--7. 1. "DMA_DSP1_DREQ_12_IRQ_12," line.long 0x9C "CTRL_CORE_DMA_DSP1_DREQ_14_15," hexmask.long.byte 0x9C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x9C 16.--23. 1. "DMA_DSP1_DREQ_15_IRQ_15," newline hexmask.long.byte 0x9C 8.--15. 1. "RESERVED," newline hexmask.long.byte 0x9C 0.--7. 1. "DMA_DSP1_DREQ_14_IRQ_14," line.long 0xA0 "CTRL_CORE_DMA_DSP1_DREQ_16_17," hexmask.long.byte 0xA0 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xA0 16.--23. 1. "DMA_DSP1_DREQ_17_IRQ_17," newline hexmask.long.byte 0xA0 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xA0 0.--7. 1. "DMA_DSP1_DREQ_16_IRQ_16," line.long 0xA4 "CTRL_CORE_DMA_DSP1_DREQ_18_19," hexmask.long.byte 0xA4 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xA4 16.--23. 1. "DMA_DSP1_DREQ_19_IRQ_19," newline hexmask.long.byte 0xA4 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xA4 0.--7. 1. "DMA_DSP1_DREQ_18_IRQ_18," line.long 0xA8 "CTRL_CORE_DMA_DSP2_DREQ_0_1," hexmask.long.byte 0xA8 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xA8 16.--23. 1. "DMA_DSP2_DREQ_1_IRQ_1," newline hexmask.long.byte 0xA8 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xA8 0.--7. 1. "DMA_DSP2_DREQ_0_IRQ_0," line.long 0xAC "CTRL_CORE_DMA_DSP2_DREQ_2_3," hexmask.long.byte 0xAC 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xAC 16.--23. 1. "DMA_DSP2_DREQ_3_IRQ_3," newline hexmask.long.byte 0xAC 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xAC 0.--7. 1. "DMA_DSP2_DREQ_2_IRQ_2," line.long 0xB0 "CTRL_CORE_DMA_DSP2_DREQ_4_5," hexmask.long.byte 0xB0 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xB0 16.--23. 1. "DMA_DSP2_DREQ_5_IRQ_5," newline hexmask.long.byte 0xB0 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xB0 0.--7. 1. "DMA_DSP2_DREQ_4_IRQ_4," line.long 0xB4 "CTRL_CORE_DMA_DSP2_DREQ_6_7," hexmask.long.byte 0xB4 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xB4 16.--23. 1. "DMA_DSP2_DREQ_7_IRQ_7," newline hexmask.long.byte 0xB4 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xB4 0.--7. 1. "DMA_DSP2_DREQ_6_IRQ_6," line.long 0xB8 "CTRL_CORE_DMA_DSP2_DREQ_8_9," hexmask.long.byte 0xB8 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xB8 16.--23. 1. "DMA_DSP2_DREQ_9_IRQ_9," newline hexmask.long.byte 0xB8 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xB8 0.--7. 1. "DMA_DSP2_DREQ_8_IRQ_8," line.long 0xBC "CTRL_CORE_DMA_DSP2_DREQ_10_11," hexmask.long.byte 0xBC 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xBC 16.--23. 1. "DMA_DSP2_DREQ_11_IRQ_11," newline hexmask.long.byte 0xBC 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xBC 0.--7. 1. "DMA_DSP2_DREQ_10_IRQ_10," line.long 0xC0 "CTRL_CORE_DMA_DSP2_DREQ_12_13," hexmask.long.byte 0xC0 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xC0 16.--23. 1. "DMA_DSP2_DREQ_13_IRQ_13," newline hexmask.long.byte 0xC0 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xC0 0.--7. 1. "DMA_DSP2_DREQ_12_IRQ_12," line.long 0xC4 "CTRL_CORE_DMA_DSP2_DREQ_14_15," hexmask.long.byte 0xC4 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xC4 16.--23. 1. "DMA_DSP2_DREQ_15_IRQ_15," newline hexmask.long.byte 0xC4 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xC4 0.--7. 1. "DMA_DSP2_DREQ_14_IRQ_14," line.long 0xC8 "CTRL_CORE_DMA_DSP2_DREQ_16_17," hexmask.long.byte 0xC8 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xC8 16.--23. 1. "DMA_DSP2_DREQ_17_IRQ_17," newline hexmask.long.byte 0xC8 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xC8 0.--7. 1. "DMA_DSP2_DREQ_16_IRQ_16," line.long 0xCC "CTRL_CORE_DMA_DSP2_DREQ_18_19," hexmask.long.byte 0xCC 24.--31. 1. "RESERVED," newline hexmask.long.byte 0xCC 16.--23. 1. "DMA_DSP2_DREQ_19_IRQ_19," newline hexmask.long.byte 0xCC 8.--15. 1. "RESERVED," newline hexmask.long.byte 0xCC 0.--7. 1. "DMA_DSP2_DREQ_18_IRQ_18," group.long 0xD54++0x0F line.long 0x00 "CTRL_CORE_ESM_GROUP1_0," hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--8. 1. "ESM_GROUP1_0_IRQ_0," line.long 0x04 "CTRL_CORE_ESM_GROUP1_1," hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," newline hexmask.long.word 0x04 0.--8. 1. "ESM_GROUP1_1_IRQ_1," line.long 0x08 "CTRL_CORE_ESM_GROUP1_2," hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," newline hexmask.long.word 0x08 0.--8. 1. "ESM_GROUP1_2_IRQ_2," line.long 0x0C "CTRL_CORE_ESM_GROUP1_3," hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x0C 0.--7. 1. "ESM_GROUP1_3_DMA_3," group.long 0xE30++0x03 line.long 0x00 "CTRL_CORE_CONTROL_DDRCACH1_0,ddrcaCH1 control" bitfld.long 0x00 29.--31. "DDRCH1_PART0_I,PART0 Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 26.--28. "DDRCH1_PART0_SR,PART0 Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 24.--25. "DDRCH1_PART0_WD,PART0 Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 21.--23. "DDRCH1_PART5A_I,PART5A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 18.--20. "DDRCH1_PART5A_SR,PART5A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 16.--17. "DDRCH1_PART5A_WD,PART5A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 13.--15. "DDRCH1_PART5B_I,PART5B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 10.--12. "DDRCH1_PART5B_SR,PART5B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 8.--9. "DDRCH1_PART5B_WD,PART5B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 5.--7. "DDRCH1_PART6_I,PART6 Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 2.--4. "DDRCH1_PART6_SR,PART6 Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 0.--1. "DDRCH1_PART6_WD,PART6 Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" group.long 0xE38++0x07 line.long 0x00 "CTRL_CORE_CONTROL_DDRCH1_0,DDRCH1 control 0" bitfld.long 0x00 29.--31. "DDRCH1_PART1A_I,PART1A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 26.--28. "DDRCH1_PART1A_SR,PART1A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 24.--25. "DDRCH1_PART1A_WD,PART1A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 21.--23. "DDRCH1_PART1B_I,PART1B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 18.--20. "DDRCH1_PART1B_SR,PART1B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 16.--17. "DDRCH1_PART1B_WD,PART1B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 13.--15. "DDRCH1_PART2A_I,PART2A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 10.--12. "DDRCH1_PART2A_SR,PART2A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 8.--9. "DDRCH1_PART2A_WD,PART2A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 5.--7. "DDRCH1_PART2B_I,PART2B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 2.--4. "DDRCH1_PART2B_SR,PART2B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 0.--1. "DDRCH1_PART2B_WD,PART2B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" line.long 0x04 "CTRL_CORE_CONTROL_DDRCH1_1,DDRCH1 control 1" bitfld.long 0x04 29.--31. "DDRCH1_PART3A_I,PART3A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x04 26.--28. "DDRCH1_PART3A_SR,PART3A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x04 24.--25. "DDRCH1_PART3A_WD,PART3A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x04 21.--23. "DDRCH1_PART3B_I,PART3B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x04 18.--20. "DDRCH1_PART3B_SR,PART3B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x04 16.--17. "DDRCH1_PART3B_WD,PART3B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x04 13.--15. "DDRCH1_PART4A_I,PART4A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x04 10.--12. "DDRCH1_PART4A_SR,PART4A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x04 8.--9. "DDRCH1_PART4A_WD,PART4A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x04 5.--7. "DDRCH1_PART4B_I,PART4B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x04 2.--4. "DDRCH1_PART4B_SR,PART4B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x04 0.--1. "DDRCH1_PART4B_WD,PART4B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" group.long 0xE48++0x03 line.long 0x00 "CTRL_CORE_CONTROL_DDRCH1_2," hexmask.long.byte 0x00 24.--31. 1. "RESERVED," newline bitfld.long 0x00 21.--23. "DDRCH1_PART7A_I,PART7A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 18.--20. "DDRCH1_PART7A_SR,PART7A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 16.--17. "DDRCH1_PART7A_WD,PART7A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 13.--15. "DDRCH1_PART7B_I,PART7B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 10.--12. "DDRCH1_PART7B_SR,PART7B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 8.--9. "DDRCH1_PART7B_WD,PART7B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0xE50++0x03 line.long 0x00 "CTRL_CORE_CONTROL_DDRIO_0," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline bitfld.long 0x00 19. "DDRCH1_VREF_DQ0_INT_CCAP0,Selection for coupling cap connection" "DDRCH1_VREF_DQ0_INT_CCAP0_0,DDRCH1_VREF_DQ0_INT_CCAP0_1" newline bitfld.long 0x00 18. "DDRCH1_VREF_DQ0_INT_CCAP1,Selection for coupling cap connection" "DDRCH1_VREF_DQ0_INT_CCAP1_0,DDRCH1_VREF_DQ0_INT_CCAP1_1" newline bitfld.long 0x00 17. "DDRCH1_VREF_DQ0_INT_TAP0,Selection for internal reference voltage drive" "DDRCH1_VREF_DQ0_INT_TAP0_0,DDRCH1_VREF_DQ0_INT_TAP0_1" newline bitfld.long 0x00 16. "DDRCH1_VREF_DQ0_INT_TAP1,Selection for internal reference voltage drive" "DDRCH1_VREF_DQ0_INT_TAP1_0,DDRCH1_VREF_DQ0_INT_TAP1_1" newline bitfld.long 0x00 15. "DDRCH1_VREF_DQ0_INT_EN,Enable" "DDRCH1_VREF_DQ0_INT_EN_0,DDRCH1_VREF_DQ0_INT_EN_1" newline bitfld.long 0x00 14. "DDRCH1_VREF_DQ1_INT_CCAP0,Selection for coupling cap connection" "DDRCH1_VREF_DQ1_INT_CCAP0_0,DDRCH1_VREF_DQ1_INT_CCAP0_1" newline bitfld.long 0x00 13. "DDRCH1_VREF_DQ1_INT_CCAP1,Selection for coupling cap connection" "DDRCH1_VREF_DQ1_INT_CCAP1_0,DDRCH1_VREF_DQ1_INT_CCAP1_1" newline bitfld.long 0x00 12. "DDRCH1_VREF_DQ1_INT_TAP0,Selection for internal reference voltage drive" "DDRCH1_VREF_DQ1_INT_TAP0_0,DDRCH1_VREF_DQ1_INT_TAP0_1" newline bitfld.long 0x00 11. "DDRCH1_VREF_DQ1_INT_TAP1,Selection for internal reference voltage drive" "DDRCH1_VREF_DQ1_INT_TAP1_0,DDRCH1_VREF_DQ1_INT_TAP1_1" newline bitfld.long 0x00 10. "DDRCH1_VREF_DQ1_INT_EN,Enable" "DDRCH1_VREF_DQ1_INT_EN_0,DDRCH1_VREF_DQ1_INT_EN_1" newline hexmask.long.word 0x00 0.--9. 1. "RESERVED," group.long 0x1000++0x03 line.long 0x00 "CTRL_CORE_HWOBS_FINAL_MUX_SEL,This register controls the final multiplexor which selects whether CORE or WKUP observable signals are mapped to the final observability bus. that is obs[31:0] bus" group.long 0x100C++0xBF line.long 0x00 "CTRL_CORE_CONF_DEBUG_SEL_TST_0,This register is used to select an observable signal for CORE observability line 0" hexmask.long 0x00 6.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 0" "?,?,?,?,?,?,?,MODE_7,?,?,?,MODE_11,?,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "CTRL_CORE_CONF_DEBUG_SEL_TST_1,This register is used to select an observable signal for CORE observability line 1" hexmask.long 0x04 6.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 1" "?,?,?,?,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x08 "CTRL_CORE_CONF_DEBUG_SEL_TST_2,This register is used to select an observable signal for CORE observability line 2" hexmask.long 0x08 6.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 2" "?,?,?,?,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x0C "CTRL_CORE_CONF_DEBUG_SEL_TST_3,This register is used to select an observable signal for CORE observability line 3" hexmask.long 0x0C 6.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 3" "?,MODE_1,?,MODE_3,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x10 "CTRL_CORE_CONF_DEBUG_SEL_TST_4,This register is used to select an observable signal for CORE observability line 4" hexmask.long 0x10 6.--31. 1. "RESERVED," newline bitfld.long 0x10 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 4" "?,MODE_1,?,MODE_3,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "CTRL_CORE_CONF_DEBUG_SEL_TST_5,This register is used to select an observable signal for CORE observability line 5" hexmask.long 0x14 6.--31. 1. "RESERVED," newline bitfld.long 0x14 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 5" "?,MODE_1,?,MODE_3,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x18 "CTRL_CORE_CONF_DEBUG_SEL_TST_6,This register is used to select an observable signal for CORE observability line 6" hexmask.long 0x18 6.--31. 1. "RESERVED," newline bitfld.long 0x18 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 6" "?,MODE_1,?,MODE_3,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x1C "CTRL_CORE_CONF_DEBUG_SEL_TST_7,This register is used to select an observable signal for CORE observability line 7" hexmask.long 0x1C 6.--31. 1. "RESERVED," newline bitfld.long 0x1C 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 7" "?,MODE_1,?,MODE_3,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x20 "CTRL_CORE_CONF_DEBUG_SEL_TST_8,This register is used to select an observable signal for CORE observability line 8" hexmask.long 0x20 6.--31. 1. "RESERVED," newline bitfld.long 0x20 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 8" "?,MODE_1,?,MODE_3,?,?,?,MODE_7,?,?,?,MODE_11,MODE_12,?,MODE_14,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x24 "CTRL_CORE_CONF_DEBUG_SEL_TST_9,This register is used to select an observable signal for CORE observability line 9" hexmask.long 0x24 6.--31. 1. "RESERVED," newline bitfld.long 0x24 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 9" "?,MODE_1,?,MODE_3,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x28 "CTRL_CORE_CONF_DEBUG_SEL_TST_10,This register is used to select an observable signal for CORE observability line 10" hexmask.long 0x28 6.--31. 1. "RESERVED," newline bitfld.long 0x28 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 10" "?,MODE_1,?,?,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x2C "CTRL_CORE_CONF_DEBUG_SEL_TST_11,This register is used to select an observable signal for CORE observability line 11" hexmask.long 0x2C 6.--31. 1. "RESERVED," newline bitfld.long 0x2C 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 11" "?,MODE_1,?,?,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,MODE_14,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x30 "CTRL_CORE_CONF_DEBUG_SEL_TST_12,This register is used to select an observable signal for CORE observability line 12" hexmask.long 0x30 6.--31. 1. "RESERVED," newline bitfld.long 0x30 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 12" "?,MODE_1,MODE_2,?,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,?,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x34 "CTRL_CORE_CONF_DEBUG_SEL_TST_13,This register is used to select an observable signal for CORE observability line 13" hexmask.long 0x34 6.--31. 1. "RESERVED," newline bitfld.long 0x34 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 13" "?,MODE_1,MODE_2,?,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,?,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x38 "CTRL_CORE_CONF_DEBUG_SEL_TST_14,This register is used to select an observable signal for CORE observability line 14" hexmask.long 0x38 6.--31. 1. "RESERVED," newline bitfld.long 0x38 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 14" "?,MODE_1,?,?,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,?,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x3C "CTRL_CORE_CONF_DEBUG_SEL_TST_15,This register is used to select an observable signal for CORE observability line 15" hexmask.long 0x3C 6.--31. 1. "RESERVED," newline bitfld.long 0x3C 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 15" "?,MODE_1,?,?,?,?,?,MODE_7,?,MODE_9,?,MODE_11,MODE_12,?,?,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x40 "CTRL_CORE_CONF_DEBUG_SEL_TST_16,This register is used to select an observable signal for CORE observability line 16" hexmask.long 0x40 6.--31. 1. "RESERVED," newline bitfld.long 0x40 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 16" "?,MODE_1,?,?,?,?,?,MODE_7,?,?,?,MODE_11,MODE_12,?,?,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x44 "CTRL_CORE_CONF_DEBUG_SEL_TST_17,This register is used to select an observable signal for CORE observability line 17" hexmask.long 0x44 6.--31. 1. "RESERVED," newline bitfld.long 0x44 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 17" "?,MODE_1,?,?,?,?,?,MODE_7,?,?,?,MODE_11,MODE_12,?,?,?,?,MODE_17,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x48 "CTRL_CORE_CONF_DEBUG_SEL_TST_18,This register is used to select an observable signal for CORE observability line 18" hexmask.long 0x48 6.--31. 1. "RESERVED," newline bitfld.long 0x48 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 18" "?,MODE_1,?,?,?,?,?,MODE_7,?,?,?,MODE_11,MODE_12,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x4C "CTRL_CORE_CONF_DEBUG_SEL_TST_19,This register is used to select an observable signal for CORE observability line 19" hexmask.long 0x4C 6.--31. 1. "RESERVED," newline bitfld.long 0x4C 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 19" "?,MODE_1,MODE_2,?,?,?,?,MODE_7,?,?,?,MODE_11,MODE_12,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x50 "CTRL_CORE_CONF_DEBUG_SEL_TST_20,This register is used to select an observable signal for CORE observability line 20" hexmask.long 0x50 6.--31. 1. "RESERVED," newline bitfld.long 0x50 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 20" "?,MODE_1,MODE_2,?,?,?,?,MODE_7,?,?,?,MODE_11,MODE_12,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x54 "CTRL_CORE_CONF_DEBUG_SEL_TST_21,This register is used to select an observable signal for CORE observability line 21" hexmask.long 0x54 6.--31. 1. "RESERVED," newline bitfld.long 0x54 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 21" "?,?,MODE_2,?,?,?,?,MODE_7,?,?,?,MODE_11,MODE_12,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,MODE_24,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x58 "CTRL_CORE_CONF_DEBUG_SEL_TST_22,This register is used to select an observable signal for CORE observability line 22" hexmask.long 0x58 6.--31. 1. "RESERVED," newline bitfld.long 0x58 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 22" "?,?,MODE_2,?,?,?,?,MODE_7,?,?,?,MODE_11,MODE_12,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,?,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x5C "CTRL_CORE_CONF_DEBUG_SEL_TST_23,This register is used to select an observable signal for CORE observability line 23" hexmask.long 0x5C 6.--31. 1. "RESERVED," newline bitfld.long 0x5C 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 23" "?,?,MODE_2,?,?,?,?,MODE_7,?,?,?,MODE_11,?,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,?,?,?,?,?,?,MODE_30,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x60 "CTRL_CORE_CONF_DEBUG_SEL_TST_24,This register is used to select an observable signal for CORE observability line 24" hexmask.long 0x60 6.--31. 1. "RESERVED," newline bitfld.long 0x60 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 24" "?,?,MODE_2,?,?,?,?,MODE_7,?,?,?,MODE_11,?,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,?,?,?,?,?,?,?,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,MODE_45,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x64 "CTRL_CORE_CONF_DEBUG_SEL_TST_25,This register is used to select an observable signal for CORE observability line 25" hexmask.long 0x64 6.--31. 1. "RESERVED," newline bitfld.long 0x64 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 25" "?,?,MODE_2,?,?,?,?,MODE_7,?,?,?,MODE_11,?,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,?,?,?,?,?,?,?,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,?,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x68 "CTRL_CORE_CONF_DEBUG_SEL_TST_26,This register is used to select an observable signal for CORE observability line 26" hexmask.long 0x68 6.--31. 1. "RESERVED," newline bitfld.long 0x68 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 26" "?,?,?,?,?,?,?,MODE_7,?,?,?,?,?,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,?,?,?,?,?,?,?,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,?,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x6C "CTRL_CORE_CONF_DEBUG_SEL_TST_27,This register is used to select an observable signal for CORE observability line 27" hexmask.long 0x6C 6.--31. 1. "RESERVED," newline bitfld.long 0x6C 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 27" "?,?,?,?,?,?,?,MODE_7,?,?,?,?,?,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,?,?,?,?,?,?,?,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,?,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x70 "CTRL_CORE_CONF_DEBUG_SEL_TST_28,This register is used to select an observable signal for CORE observability line 28" hexmask.long 0x70 6.--31. 1. "RESERVED," newline bitfld.long 0x70 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 28" "?,?,?,?,?,?,?,MODE_7,?,?,?,?,?,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,?,?,?,?,?,?,?,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,?,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x74 "CTRL_CORE_CONF_DEBUG_SEL_TST_29,This register is used to select an observable signal for CORE observability line 29" hexmask.long 0x74 6.--31. 1. "RESERVED," newline bitfld.long 0x74 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 29" "?,?,?,?,?,?,?,MODE_7,?,?,?,?,?,?,?,?,?,?,MODE_18,?,?,MODE_21,MODE_22,MODE_23,?,?,?,?,?,?,?,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,?,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x78 "CTRL_CORE_CONF_DEBUG_SEL_TST_30,This register is used to select an observable signal for CORE observability line 30" hexmask.long 0x78 6.--31. 1. "RESERVED," newline bitfld.long 0x78 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 30" "?,?,MODE_2,?,?,?,?,MODE_7,?,?,?,?,?,?,?,?,?,?,MODE_18,?,?,?,MODE_22,MODE_23,?,?,?,?,?,?,?,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,?,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x7C "CTRL_CORE_CONF_DEBUG_SEL_TST_31,This register is used to select an observable signal for CORE observability line 31" hexmask.long 0x7C 6.--31. 1. "RESERVED," newline bitfld.long 0x7C 0.--5. "MODE,Selects one of the following signals to be available on CORE observability line 31" "?,?,?,?,?,?,?,MODE_7,?,?,?,?,?,?,?,?,?,?,MODE_18,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,MODE_34,MODE_35,?,?,MODE_38,?,?,?,MODE_42,MODE_43,MODE_44,?,MODE_46,MODE_47,MODE_48,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x80 "CTRL_CORE_CONF_DEBUG_SEL_TST_32,This register is used to select a signal for observation using line 0 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0x80 3.--31. 1. "RESERVED," newline bitfld.long 0x80 0.--2. "MODE,Selects one of the following signals to be available on line 0 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0x84 "CTRL_CORE_CONF_DEBUG_SEL_TST_33,This register is used to select a signal for observation using line 1 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0x84 3.--31. 1. "RESERVED," newline bitfld.long 0x84 0.--2. "MODE,Selects one of the following signals to be available on line 1 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0x88 "CTRL_CORE_CONF_DEBUG_SEL_TST_34,This register is used to select a signal for observation using line 2 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0x88 3.--31. 1. "RESERVED," newline bitfld.long 0x88 0.--2. "MODE,Selects one of the following signals to be available on line 2 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0x8C "CTRL_CORE_CONF_DEBUG_SEL_TST_35,This register is used to select a signal for observation using line 3 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0x8C 3.--31. 1. "RESERVED," newline bitfld.long 0x8C 0.--2. "MODE,Selects one of the following signals to be available on line 3 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0x90 "CTRL_CORE_CONF_DEBUG_SEL_TST_36,This register is used to select a signal for observation using line 4 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0x90 3.--31. 1. "RESERVED," newline bitfld.long 0x90 0.--2. "MODE,Selects one of the following signals to be available on line 4 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0x94 "CTRL_CORE_CONF_DEBUG_SEL_TST_37,This register is used to select a signal for observation using line 5 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0x94 3.--31. 1. "RESERVED," newline bitfld.long 0x94 0.--2. "MODE,Selects one of the following signals to be available on line 5 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0x98 "CTRL_CORE_CONF_DEBUG_SEL_TST_38,This register is used to select a signal for observation using line 6 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0x98 3.--31. 1. "RESERVED," newline bitfld.long 0x98 0.--2. "MODE,Selects one of the following signals to be available on line 6 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0x9C "CTRL_CORE_CONF_DEBUG_SEL_TST_39,This register is used to select a signal for observation using line 7 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0x9C 3.--31. 1. "RESERVED," newline bitfld.long 0x9C 0.--2. "MODE,Selects one of the following signals to be available on line 7 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0xA0 "CTRL_CORE_CONF_DEBUG_SEL_TST_40,This register is used to select a signal for observation using line 8 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0xA0 3.--31. 1. "RESERVED," newline bitfld.long 0xA0 0.--2. "MODE,Selects one of the following signals to be available on line 8 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0xA4 "CTRL_CORE_CONF_DEBUG_SEL_TST_41,This register is used to select a signal for observation using line 9 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0xA4 3.--31. 1. "RESERVED," newline bitfld.long 0xA4 0.--2. "MODE,Selects one of the following signals to be available on line 9 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0xA8 "CTRL_CORE_CONF_DEBUG_SEL_TST_42,This register is used to select a signal for observation using line 10 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0xA8 3.--31. 1. "RESERVED," newline bitfld.long 0xA8 0.--2. "MODE,Selects one of the following signals to be available on line 10 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0xAC "CTRL_CORE_CONF_DEBUG_SEL_TST_43,This register is used to select a signal for observation using line 11 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0xAC 3.--31. 1. "RESERVED," newline bitfld.long 0xAC 0.--2. "MODE,Selects one of the following signals to be available on line 11 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0xB0 "CTRL_CORE_CONF_DEBUG_SEL_TST_44,This register is used to select a signal for observation using line 12 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0xB0 3.--31. 1. "RESERVED," newline bitfld.long 0xB0 0.--2. "MODE,Selects one of the following signals to be available on line 12 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0xB4 "CTRL_CORE_CONF_DEBUG_SEL_TST_45,This register is used to select a signal for observation using line 13 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0xB4 3.--31. 1. "RESERVED," newline bitfld.long 0xB4 0.--2. "MODE,Selects one of the following signals to be available on line 13 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0xB8 "CTRL_CORE_CONF_DEBUG_SEL_TST_46,This register is used to select a signal for observation using line 14 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0xB8 3.--31. 1. "RESERVED," newline bitfld.long 0xB8 0.--2. "MODE,Selects one of the following signals to be available on line 14 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" line.long 0xBC "CTRL_CORE_CONF_DEBUG_SEL_TST_47,This register is used to select a signal for observation using line 15 of the system event detection bus which is part of the device OCP-WP" hexmask.long 0xBC 3.--31. 1. "RESERVED," newline bitfld.long 0xBC 0.--2. "MODE,Selects one of the following signals to be available on line 15 of the system event detection bus" "?,?,?,?,MODE_4,MODE_5,?,?" group.long 0x1400++0x14F line.long 0x00 "CTRL_CORE_PAD_GPMC_CLK," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline bitfld.long 0x00 19. "GPMC_CLK_SLEWCONTROL," "GPMC_CLK_SLEWCONTROL_0,GPMC_CLK_SLEWCONTROL_1" newline bitfld.long 0x00 18. "GPMC_CLK_INPUTENABLE," "GPMC_CLK_INPUTENABLE_0,GPMC_CLK_INPUTENABLE_1" newline bitfld.long 0x00 17. "GPMC_CLK_PULLTYPESELECT," "GPMC_CLK_PULLTYPESELECT_0,GPMC_CLK_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "GPMC_CLK_PULLUDENABLE," "GPMC_CLK_PULLUDENABLE_0,GPMC_CLK_PULLUDENABLE_1" newline hexmask.long.word 0x00 4.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "GPMC_CLK_MUXMODE," "GPMC_CLK_MUXMODE_0,GPMC_CLK_MUXMODE_1,?,?,?,GPMC_CLK_MUXMODE_5,GPMC_CLK_MUXMODE_6,?,?,?,?,?,?,?,GPMC_CLK_MUXMODE_14,GPMC_CLK_MUXMODE_15" line.long 0x04 "CTRL_CORE_PAD_GPMC_BEN0," hexmask.long.word 0x04 20.--31. 1. "RESERVED," newline bitfld.long 0x04 19. "GPMC_BEN0_SLEWCONTROL," "GPMC_BEN0_SLEWCONTROL_0,GPMC_BEN0_SLEWCONTROL_1" newline bitfld.long 0x04 18. "GPMC_BEN0_INPUTENABLE," "GPMC_BEN0_INPUTENABLE_0,GPMC_BEN0_INPUTENABLE_1" newline bitfld.long 0x04 17. "GPMC_BEN0_PULLTYPESELECT," "GPMC_BEN0_PULLTYPESELECT_0,GPMC_BEN0_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "GPMC_BEN0_PULLUDENABLE," "GPMC_BEN0_PULLUDENABLE_0,GPMC_BEN0_PULLUDENABLE_1" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 0.--3. "GPMC_BEN0_MUXMODE," "GPMC_BEN0_MUXMODE_0,GPMC_BEN0_MUXMODE_1,?,?,GPMC_BEN0_MUXMODE_4,?,GPMC_BEN0_MUXMODE_6,?,?,?,?,?,?,?,GPMC_BEN0_MUXMODE_14,GPMC_BEN0_MUXMODE_15" line.long 0x08 "CTRL_CORE_PAD_GPMC_BEN1," hexmask.long.word 0x08 20.--31. 1. "RESERVED," newline bitfld.long 0x08 19. "GPMC_BEN1_SLEWCONTROL," "GPMC_BEN1_SLEWCONTROL_0,GPMC_BEN1_SLEWCONTROL_1" newline bitfld.long 0x08 18. "GPMC_BEN1_INPUTENABLE," "GPMC_BEN1_INPUTENABLE_0,GPMC_BEN1_INPUTENABLE_1" newline bitfld.long 0x08 17. "GPMC_BEN1_PULLTYPESELECT," "GPMC_BEN1_PULLTYPESELECT_0,GPMC_BEN1_PULLTYPESELECT_1" newline bitfld.long 0x08 16. "GPMC_BEN1_PULLUDENABLE," "GPMC_BEN1_PULLUDENABLE_0,GPMC_BEN1_PULLUDENABLE_1" newline hexmask.long.word 0x08 4.--15. 1. "RESERVED," newline bitfld.long 0x08 0.--3. "GPMC_BEN1_MUXMODE," "GPMC_BEN1_MUXMODE_0,GPMC_BEN1_MUXMODE_1,?,?,GPMC_BEN1_MUXMODE_4,?,GPMC_BEN1_MUXMODE_6,?,?,?,?,?,?,?,GPMC_BEN1_MUXMODE_14,GPMC_BEN1_MUXMODE_15" line.long 0x0C "CTRL_CORE_PAD_GPMC_ADVN_ALE," hexmask.long.word 0x0C 20.--31. 1. "RESERVED," newline bitfld.long 0x0C 19. "GPMC_ADVN_ALE_SLEWCONTROL," "GPMC_ADVN_ALE_SLEWCONTROL_0,GPMC_ADVN_ALE_SLEWCONTROL_1" newline bitfld.long 0x0C 18. "GPMC_ADVN_ALE_INPUTENABLE," "GPMC_ADVN_ALE_INPUTENABLE_0,GPMC_ADVN_ALE_INPUTENABLE_1" newline bitfld.long 0x0C 17. "GPMC_ADVN_ALE_PULLTYPESELECT," "GPMC_ADVN_ALE_PULLTYPESELECT_0,GPMC_ADVN_ALE_PULLTYPESELECT_1" newline bitfld.long 0x0C 16. "GPMC_ADVN_ALE_PULLUDENABLE," "GPMC_ADVN_ALE_PULLUDENABLE_0,GPMC_ADVN_ALE_PULLUDENABLE_1" newline hexmask.long.word 0x0C 4.--15. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "GPMC_ADVN_ALE_MUXMODE," "GPMC_ADVN_ALE_MUXMODE_0,GPMC_ADVN_ALE_MUXMODE_1,?,?,GPMC_ADVN_ALE_MUXMODE_4,GPMC_ADVN_ALE_MUXMODE_5,GPMC_ADVN_ALE_MUXMODE_6,?,?,?,?,?,?,?,GPMC_ADVN_ALE_MUXMODE_14,GPMC_ADVN_ALE_MUXMODE_15" line.long 0x10 "CTRL_CORE_PAD_GPMC_OEN_REN," hexmask.long.word 0x10 20.--31. 1. "RESERVED," newline bitfld.long 0x10 19. "GPMC_OEN_REN_SLEWCONTROL," "GPMC_OEN_REN_SLEWCONTROL_0,GPMC_OEN_REN_SLEWCONTROL_1" newline bitfld.long 0x10 18. "GPMC_OEN_REN_INPUTENABLE," "GPMC_OEN_REN_INPUTENABLE_0,GPMC_OEN_REN_INPUTENABLE_1" newline bitfld.long 0x10 17. "GPMC_OEN_REN_PULLTYPESELECT," "GPMC_OEN_REN_PULLTYPESELECT_0,GPMC_OEN_REN_PULLTYPESELECT_1" newline bitfld.long 0x10 16. "GPMC_OEN_REN_PULLUDENABLE," "GPMC_OEN_REN_PULLUDENABLE_0,GPMC_OEN_REN_PULLUDENABLE_1" newline hexmask.long.word 0x10 4.--15. 1. "RESERVED," newline bitfld.long 0x10 0.--3. "GPMC_OEN_REN_MUXMODE," "GPMC_OEN_REN_MUXMODE_0,GPMC_OEN_REN_MUXMODE_1,?,?,GPMC_OEN_REN_MUXMODE_4,GPMC_OEN_REN_MUXMODE_5,?,?,?,?,?,?,?,?,GPMC_OEN_REN_MUXMODE_14,GPMC_OEN_REN_MUXMODE_15" line.long 0x14 "CTRL_CORE_PAD_GPMC_WEN," hexmask.long.word 0x14 20.--31. 1. "RESERVED," newline bitfld.long 0x14 19. "GPMC_WEN_SLEWCONTROL," "GPMC_WEN_SLEWCONTROL_0,GPMC_WEN_SLEWCONTROL_1" newline bitfld.long 0x14 18. "GPMC_WEN_INPUTENABLE," "GPMC_WEN_INPUTENABLE_0,GPMC_WEN_INPUTENABLE_1" newline bitfld.long 0x14 17. "GPMC_WEN_PULLTYPESELECT," "GPMC_WEN_PULLTYPESELECT_0,GPMC_WEN_PULLTYPESELECT_1" newline bitfld.long 0x14 16. "GPMC_WEN_PULLUDENABLE," "GPMC_WEN_PULLUDENABLE_0,GPMC_WEN_PULLUDENABLE_1" newline hexmask.long.word 0x14 4.--15. 1. "RESERVED," newline bitfld.long 0x14 0.--3. "GPMC_WEN_MUXMODE," "GPMC_WEN_MUXMODE_0,GPMC_WEN_MUXMODE_1,?,?,GPMC_WEN_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_WEN_MUXMODE_14,GPMC_WEN_MUXMODE_15" line.long 0x18 "CTRL_CORE_PAD_GPMC_CS0," hexmask.long.word 0x18 20.--31. 1. "RESERVED," newline bitfld.long 0x18 19. "GPMC_CS0_SLEWCONTROL," "GPMC_CS0_SLEWCONTROL_0,GPMC_CS0_SLEWCONTROL_1" newline bitfld.long 0x18 18. "GPMC_CS0_INPUTENABLE," "GPMC_CS0_INPUTENABLE_0,GPMC_CS0_INPUTENABLE_1" newline bitfld.long 0x18 17. "GPMC_CS0_PULLTYPESELECT," "GPMC_CS0_PULLTYPESELECT_0,GPMC_CS0_PULLTYPESELECT_1" newline bitfld.long 0x18 16. "GPMC_CS0_PULLUDENABLE," "GPMC_CS0_PULLUDENABLE_0,GPMC_CS0_PULLUDENABLE_1" newline hexmask.long.word 0x18 4.--15. 1. "RESERVED," newline bitfld.long 0x18 0.--3. "GPMC_CS0_MUXMODE," "GPMC_CS0_MUXMODE_0,GPMC_CS0_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS0_MUXMODE_14,GPMC_CS0_MUXMODE_15" line.long 0x1C "CTRL_CORE_PAD_GPMC_CS1," hexmask.long.word 0x1C 20.--31. 1. "RESERVED," newline bitfld.long 0x1C 19. "GPMC_CS1_SLEWCONTROL," "GPMC_CS1_SLEWCONTROL_0,GPMC_CS1_SLEWCONTROL_1" newline bitfld.long 0x1C 18. "GPMC_CS1_INPUTENABLE," "GPMC_CS1_INPUTENABLE_0,GPMC_CS1_INPUTENABLE_1" newline bitfld.long 0x1C 17. "GPMC_CS1_PULLTYPESELECT," "GPMC_CS1_PULLTYPESELECT_0,GPMC_CS1_PULLTYPESELECT_1" newline bitfld.long 0x1C 16. "GPMC_CS1_PULLUDENABLE," "GPMC_CS1_PULLUDENABLE_0,GPMC_CS1_PULLUDENABLE_1" newline hexmask.long.word 0x1C 4.--15. 1. "RESERVED," newline bitfld.long 0x1C 0.--3. "GPMC_CS1_MUXMODE," "GPMC_CS1_MUXMODE_0,GPMC_CS1_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS1_MUXMODE_14,GPMC_CS1_MUXMODE_15" line.long 0x20 "CTRL_CORE_PAD_GPMC_CS2," hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline bitfld.long 0x20 19. "GPMC_CS2_SLEWCONTROL," "GPMC_CS2_SLEWCONTROL_0,GPMC_CS2_SLEWCONTROL_1" newline bitfld.long 0x20 18. "GPMC_CS2_INPUTENABLE," "GPMC_CS2_INPUTENABLE_0,GPMC_CS2_INPUTENABLE_1" newline bitfld.long 0x20 17. "GPMC_CS2_PULLTYPESELECT," "GPMC_CS2_PULLTYPESELECT_0,GPMC_CS2_PULLTYPESELECT_1" newline bitfld.long 0x20 16. "GPMC_CS2_PULLUDENABLE," "GPMC_CS2_PULLUDENABLE_0,GPMC_CS2_PULLUDENABLE_1" newline hexmask.long.word 0x20 4.--15. 1. "RESERVED," newline bitfld.long 0x20 0.--3. "GPMC_CS2_MUXMODE," "GPMC_CS2_MUXMODE_0,GPMC_CS2_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS2_MUXMODE_14,GPMC_CS2_MUXMODE_15" line.long 0x24 "CTRL_CORE_PAD_GPMC_CS3," hexmask.long.word 0x24 20.--31. 1. "RESERVED," newline bitfld.long 0x24 19. "GPMC_CS3_SLEWCONTROL," "GPMC_CS3_SLEWCONTROL_0,GPMC_CS3_SLEWCONTROL_1" newline bitfld.long 0x24 18. "GPMC_CS3_INPUTENABLE," "GPMC_CS3_INPUTENABLE_0,GPMC_CS3_INPUTENABLE_1" newline bitfld.long 0x24 17. "GPMC_CS3_PULLTYPESELECT," "GPMC_CS3_PULLTYPESELECT_0,GPMC_CS3_PULLTYPESELECT_1" newline bitfld.long 0x24 16. "GPMC_CS3_PULLUDENABLE," "GPMC_CS3_PULLUDENABLE_0,GPMC_CS3_PULLUDENABLE_1" newline hexmask.long.word 0x24 4.--15. 1. "RESERVED," newline bitfld.long 0x24 0.--3. "GPMC_CS3_MUXMODE," "GPMC_CS3_MUXMODE_0,GPMC_CS3_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS3_MUXMODE_14,GPMC_CS3_MUXMODE_15" line.long 0x28 "CTRL_CORE_PAD_GPMC_CS4," hexmask.long.word 0x28 20.--31. 1. "RESERVED," newline bitfld.long 0x28 19. "GPMC_CS4_SLEWCONTROL," "GPMC_CS4_SLEWCONTROL_0,GPMC_CS4_SLEWCONTROL_1" newline bitfld.long 0x28 18. "GPMC_CS4_INPUTENABLE," "GPMC_CS4_INPUTENABLE_0,GPMC_CS4_INPUTENABLE_1" newline bitfld.long 0x28 17. "GPMC_CS4_PULLTYPESELECT," "GPMC_CS4_PULLTYPESELECT_0,GPMC_CS4_PULLTYPESELECT_1" newline bitfld.long 0x28 16. "GPMC_CS4_PULLUDENABLE," "GPMC_CS4_PULLUDENABLE_0,GPMC_CS4_PULLUDENABLE_1" newline hexmask.long.word 0x28 4.--15. 1. "RESERVED," newline bitfld.long 0x28 0.--3. "GPMC_CS4_MUXMODE," "GPMC_CS4_MUXMODE_0,GPMC_CS4_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS4_MUXMODE_14,GPMC_CS4_MUXMODE_15" line.long 0x2C "CTRL_CORE_PAD_GPMC_CS5," hexmask.long.word 0x2C 20.--31. 1. "RESERVED," newline bitfld.long 0x2C 19. "GPMC_CS5_SLEWCONTROL," "GPMC_CS5_SLEWCONTROL_0,GPMC_CS5_SLEWCONTROL_1" newline bitfld.long 0x2C 18. "GPMC_CS5_INPUTENABLE," "GPMC_CS5_INPUTENABLE_0,GPMC_CS5_INPUTENABLE_1" newline bitfld.long 0x2C 17. "GPMC_CS5_PULLTYPESELECT," "GPMC_CS5_PULLTYPESELECT_0,GPMC_CS5_PULLTYPESELECT_1" newline bitfld.long 0x2C 16. "GPMC_CS5_PULLUDENABLE," "GPMC_CS5_PULLUDENABLE_0,GPMC_CS5_PULLUDENABLE_1" newline hexmask.long.word 0x2C 4.--15. 1. "RESERVED," newline bitfld.long 0x2C 0.--3. "GPMC_CS5_MUXMODE," "GPMC_CS5_MUXMODE_0,GPMC_CS5_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS5_MUXMODE_14,GPMC_CS5_MUXMODE_15" line.long 0x30 "CTRL_CORE_PAD_GPMC_CS6," hexmask.long.word 0x30 20.--31. 1. "RESERVED," newline bitfld.long 0x30 19. "GPMC_CS6_SLEWCONTROL," "GPMC_CS6_SLEWCONTROL_0,GPMC_CS6_SLEWCONTROL_1" newline bitfld.long 0x30 18. "GPMC_CS6_INPUTENABLE," "GPMC_CS6_INPUTENABLE_0,GPMC_CS6_INPUTENABLE_1" newline bitfld.long 0x30 17. "GPMC_CS6_PULLTYPESELECT," "GPMC_CS6_PULLTYPESELECT_0,GPMC_CS6_PULLTYPESELECT_1" newline bitfld.long 0x30 16. "GPMC_CS6_PULLUDENABLE," "GPMC_CS6_PULLUDENABLE_0,GPMC_CS6_PULLUDENABLE_1" newline hexmask.long.word 0x30 4.--15. 1. "RESERVED," newline bitfld.long 0x30 0.--3. "GPMC_CS6_MUXMODE," "GPMC_CS6_MUXMODE_0,GPMC_CS6_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS6_MUXMODE_14,GPMC_CS6_MUXMODE_15" line.long 0x34 "CTRL_CORE_PAD_GPMC_WAIT0," hexmask.long.word 0x34 20.--31. 1. "RESERVED," newline bitfld.long 0x34 19. "GPMC_WAIT0_SLEWCONTROL," "GPMC_WAIT0_SLEWCONTROL_0,GPMC_WAIT0_SLEWCONTROL_1" newline bitfld.long 0x34 18. "GPMC_WAIT0_INPUTENABLE," "GPMC_WAIT0_INPUTENABLE_0,GPMC_WAIT0_INPUTENABLE_1" newline bitfld.long 0x34 17. "GPMC_WAIT0_PULLTYPESELECT," "GPMC_WAIT0_PULLTYPESELECT_0,GPMC_WAIT0_PULLTYPESELECT_1" newline bitfld.long 0x34 16. "GPMC_WAIT0_PULLUDENABLE," "GPMC_WAIT0_PULLUDENABLE_0,GPMC_WAIT0_PULLUDENABLE_1" newline hexmask.long.word 0x34 4.--15. 1. "RESERVED," newline bitfld.long 0x34 0.--3. "GPMC_WAIT0_MUXMODE," "GPMC_WAIT0_MUXMODE_0,GPMC_WAIT0_MUXMODE_1,GPMC_WAIT0_MUXMODE_2,?,?,?,GPMC_WAIT0_MUXMODE_6,?,?,?,?,?,?,?,GPMC_WAIT0_MUXMODE_14,GPMC_WAIT0_MUXMODE_15" line.long 0x38 "CTRL_CORE_PAD_GPMC_AD0," hexmask.long.word 0x38 20.--31. 1. "RESERVED," newline bitfld.long 0x38 19. "GPMC_AD0_SLEWCONTROL," "GPMC_AD0_SLEWCONTROL_0,GPMC_AD0_SLEWCONTROL_1" newline bitfld.long 0x38 18. "GPMC_AD0_INPUTENABLE," "GPMC_AD0_INPUTENABLE_0,GPMC_AD0_INPUTENABLE_1" newline bitfld.long 0x38 17. "GPMC_AD0_PULLTYPESELECT," "GPMC_AD0_PULLTYPESELECT_0,GPMC_AD0_PULLTYPESELECT_1" newline bitfld.long 0x38 16. "GPMC_AD0_PULLUDENABLE," "GPMC_AD0_PULLUDENABLE_0,GPMC_AD0_PULLUDENABLE_1" newline hexmask.long.word 0x38 4.--15. 1. "RESERVED," newline bitfld.long 0x38 0.--3. "GPMC_AD0_MUXMODE," "GPMC_AD0_MUXMODE_0,GPMC_AD0_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_AD0_MUXMODE_14,GPMC_AD0_MUXMODE_15" line.long 0x3C "CTRL_CORE_PAD_GPMC_AD1," hexmask.long.word 0x3C 20.--31. 1. "RESERVED," newline bitfld.long 0x3C 19. "GPMC_AD1_SLEWCONTROL," "GPMC_AD1_SLEWCONTROL_0,GPMC_AD1_SLEWCONTROL_1" newline bitfld.long 0x3C 18. "GPMC_AD1_INPUTENABLE," "GPMC_AD1_INPUTENABLE_0,GPMC_AD1_INPUTENABLE_1" newline bitfld.long 0x3C 17. "GPMC_AD1_PULLTYPESELECT," "GPMC_AD1_PULLTYPESELECT_0,GPMC_AD1_PULLTYPESELECT_1" newline bitfld.long 0x3C 16. "GPMC_AD1_PULLUDENABLE," "GPMC_AD1_PULLUDENABLE_0,GPMC_AD1_PULLUDENABLE_1" newline hexmask.long.word 0x3C 4.--15. 1. "RESERVED," newline bitfld.long 0x3C 0.--3. "GPMC_AD1_MUXMODE," "GPMC_AD1_MUXMODE_0,GPMC_AD1_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_AD1_MUXMODE_14,GPMC_AD1_MUXMODE_15" line.long 0x40 "CTRL_CORE_PAD_GPMC_AD2," hexmask.long.word 0x40 20.--31. 1. "RESERVED," newline bitfld.long 0x40 19. "GPMC_AD2_SLEWCONTROL," "GPMC_AD2_SLEWCONTROL_0,GPMC_AD2_SLEWCONTROL_1" newline bitfld.long 0x40 18. "GPMC_AD2_INPUTENABLE," "GPMC_AD2_INPUTENABLE_0,GPMC_AD2_INPUTENABLE_1" newline bitfld.long 0x40 17. "GPMC_AD2_PULLTYPESELECT," "GPMC_AD2_PULLTYPESELECT_0,GPMC_AD2_PULLTYPESELECT_1" newline bitfld.long 0x40 16. "GPMC_AD2_PULLUDENABLE," "GPMC_AD2_PULLUDENABLE_0,GPMC_AD2_PULLUDENABLE_1" newline hexmask.long.word 0x40 4.--15. 1. "RESERVED," newline bitfld.long 0x40 0.--3. "GPMC_AD2_MUXMODE," "GPMC_AD2_MUXMODE_0,GPMC_AD2_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_AD2_MUXMODE_14,GPMC_AD2_MUXMODE_15" line.long 0x44 "CTRL_CORE_PAD_GPMC_AD3," hexmask.long.word 0x44 20.--31. 1. "RESERVED," newline bitfld.long 0x44 19. "GPMC_AD3_SLEWCONTROL," "GPMC_AD3_SLEWCONTROL_0,GPMC_AD3_SLEWCONTROL_1" newline bitfld.long 0x44 18. "GPMC_AD3_INPUTENABLE," "GPMC_AD3_INPUTENABLE_0,GPMC_AD3_INPUTENABLE_1" newline bitfld.long 0x44 17. "GPMC_AD3_PULLTYPESELECT," "GPMC_AD3_PULLTYPESELECT_0,GPMC_AD3_PULLTYPESELECT_1" newline bitfld.long 0x44 16. "GPMC_AD3_PULLUDENABLE," "GPMC_AD3_PULLUDENABLE_0,GPMC_AD3_PULLUDENABLE_1" newline hexmask.long.word 0x44 4.--15. 1. "RESERVED," newline bitfld.long 0x44 0.--3. "GPMC_AD3_MUXMODE," "GPMC_AD3_MUXMODE_0,GPMC_AD3_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_AD3_MUXMODE_14,GPMC_AD3_MUXMODE_15" line.long 0x48 "CTRL_CORE_PAD_GPMC_AD4," hexmask.long.word 0x48 20.--31. 1. "RESERVED," newline bitfld.long 0x48 19. "GPMC_AD4_SLEWCONTROL," "GPMC_AD4_SLEWCONTROL_0,GPMC_AD4_SLEWCONTROL_1" newline bitfld.long 0x48 18. "GPMC_AD4_INPUTENABLE," "GPMC_AD4_INPUTENABLE_0,GPMC_AD4_INPUTENABLE_1" newline bitfld.long 0x48 17. "GPMC_AD4_PULLTYPESELECT," "GPMC_AD4_PULLTYPESELECT_0,GPMC_AD4_PULLTYPESELECT_1" newline bitfld.long 0x48 16. "GPMC_AD4_PULLUDENABLE," "GPMC_AD4_PULLUDENABLE_0,GPMC_AD4_PULLUDENABLE_1" newline hexmask.long.word 0x48 4.--15. 1. "RESERVED," newline bitfld.long 0x48 0.--3. "GPMC_AD4_MUXMODE," "GPMC_AD4_MUXMODE_0,GPMC_AD4_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_AD4_MUXMODE_14,GPMC_AD4_MUXMODE_15" line.long 0x4C "CTRL_CORE_PAD_GPMC_AD5," hexmask.long.word 0x4C 20.--31. 1. "RESERVED," newline bitfld.long 0x4C 19. "GPMC_AD5_SLEWCONTROL," "GPMC_AD5_SLEWCONTROL_0,GPMC_AD5_SLEWCONTROL_1" newline bitfld.long 0x4C 18. "GPMC_AD5_INPUTENABLE," "GPMC_AD5_INPUTENABLE_0,GPMC_AD5_INPUTENABLE_1" newline bitfld.long 0x4C 17. "GPMC_AD5_PULLTYPESELECT," "GPMC_AD5_PULLTYPESELECT_0,GPMC_AD5_PULLTYPESELECT_1" newline bitfld.long 0x4C 16. "GPMC_AD5_PULLUDENABLE," "GPMC_AD5_PULLUDENABLE_0,GPMC_AD5_PULLUDENABLE_1" newline hexmask.long.word 0x4C 4.--15. 1. "RESERVED," newline bitfld.long 0x4C 0.--3. "GPMC_AD5_MUXMODE," "GPMC_AD5_MUXMODE_0,?,GPMC_AD5_MUXMODE_2,GPMC_AD5_MUXMODE_3,GPMC_AD5_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_AD5_MUXMODE_14,GPMC_AD5_MUXMODE_15" line.long 0x50 "CTRL_CORE_PAD_GPMC_AD6," hexmask.long.word 0x50 20.--31. 1. "RESERVED," newline bitfld.long 0x50 19. "GPMC_AD6_SLEWCONTROL," "GPMC_AD6_SLEWCONTROL_0,GPMC_AD6_SLEWCONTROL_1" newline bitfld.long 0x50 18. "GPMC_AD6_INPUTENABLE," "GPMC_AD6_INPUTENABLE_0,GPMC_AD6_INPUTENABLE_1" newline bitfld.long 0x50 17. "GPMC_AD6_PULLTYPESELECT," "GPMC_AD6_PULLTYPESELECT_0,GPMC_AD6_PULLTYPESELECT_1" newline bitfld.long 0x50 16. "GPMC_AD6_PULLUDENABLE," "GPMC_AD6_PULLUDENABLE_0,GPMC_AD6_PULLUDENABLE_1" newline hexmask.long.word 0x50 4.--15. 1. "RESERVED," newline bitfld.long 0x50 0.--3. "GPMC_AD6_MUXMODE," "GPMC_AD6_MUXMODE_0,?,GPMC_AD6_MUXMODE_2,GPMC_AD6_MUXMODE_3,GPMC_AD6_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_AD6_MUXMODE_14,GPMC_AD6_MUXMODE_15" line.long 0x54 "CTRL_CORE_PAD_GPMC_AD7," hexmask.long.word 0x54 20.--31. 1. "RESERVED," newline bitfld.long 0x54 19. "GPMC_AD7_SLEWCONTROL," "GPMC_AD7_SLEWCONTROL_0,GPMC_AD7_SLEWCONTROL_1" newline bitfld.long 0x54 18. "GPMC_AD7_INPUTENABLE," "GPMC_AD7_INPUTENABLE_0,GPMC_AD7_INPUTENABLE_1" newline bitfld.long 0x54 17. "GPMC_AD7_PULLTYPESELECT," "GPMC_AD7_PULLTYPESELECT_0,GPMC_AD7_PULLTYPESELECT_1" newline bitfld.long 0x54 16. "GPMC_AD7_PULLUDENABLE," "GPMC_AD7_PULLUDENABLE_0,GPMC_AD7_PULLUDENABLE_1" newline hexmask.long.word 0x54 4.--15. 1. "RESERVED," newline bitfld.long 0x54 0.--3. "GPMC_AD7_MUXMODE," "GPMC_AD7_MUXMODE_0,GPMC_AD7_MUXMODE_1,?,GPMC_AD7_MUXMODE_3,GPMC_AD7_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_AD7_MUXMODE_14,GPMC_AD7_MUXMODE_15" line.long 0x58 "CTRL_CORE_PAD_GPMC_AD8," hexmask.long.word 0x58 20.--31. 1. "RESERVED," newline bitfld.long 0x58 19. "GPMC_AD8_SLEWCONTROL," "GPMC_AD8_SLEWCONTROL_0,GPMC_AD8_SLEWCONTROL_1" newline bitfld.long 0x58 18. "GPMC_AD8_INPUTENABLE," "GPMC_AD8_INPUTENABLE_0,GPMC_AD8_INPUTENABLE_1" newline bitfld.long 0x58 17. "GPMC_AD8_PULLTYPESELECT," "GPMC_AD8_PULLTYPESELECT_0,GPMC_AD8_PULLTYPESELECT_1" newline bitfld.long 0x58 16. "GPMC_AD8_PULLUDENABLE," "GPMC_AD8_PULLUDENABLE_0,GPMC_AD8_PULLUDENABLE_1" newline hexmask.long.word 0x58 4.--15. 1. "RESERVED," newline bitfld.long 0x58 0.--3. "GPMC_AD8_MUXMODE," "GPMC_AD8_MUXMODE_0,?,?,GPMC_AD8_MUXMODE_3,GPMC_AD8_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_AD8_MUXMODE_14,GPMC_AD8_MUXMODE_15" line.long 0x5C "CTRL_CORE_PAD_GPMC_AD9," hexmask.long.word 0x5C 20.--31. 1. "RESERVED," newline bitfld.long 0x5C 19. "GPMC_AD9_SLEWCONTROL," "GPMC_AD9_SLEWCONTROL_0,GPMC_AD9_SLEWCONTROL_1" newline bitfld.long 0x5C 18. "GPMC_AD9_INPUTENABLE," "GPMC_AD9_INPUTENABLE_0,GPMC_AD9_INPUTENABLE_1" newline bitfld.long 0x5C 17. "GPMC_AD9_PULLTYPESELECT," "GPMC_AD9_PULLTYPESELECT_0,GPMC_AD9_PULLTYPESELECT_1" newline bitfld.long 0x5C 16. "GPMC_AD9_PULLUDENABLE," "GPMC_AD9_PULLUDENABLE_0,GPMC_AD9_PULLUDENABLE_1" newline hexmask.long.word 0x5C 4.--15. 1. "RESERVED," newline bitfld.long 0x5C 0.--3. "GPMC_AD9_MUXMODE," "GPMC_AD9_MUXMODE_0,?,?,GPMC_AD9_MUXMODE_3,GPMC_AD9_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_AD9_MUXMODE_14,GPMC_AD9_MUXMODE_15" line.long 0x60 "CTRL_CORE_PAD_GPMC_AD10," hexmask.long.word 0x60 20.--31. 1. "RESERVED," newline bitfld.long 0x60 19. "GPMC_AD10_SLEWCONTROL," "GPMC_AD10_SLEWCONTROL_0,GPMC_AD10_SLEWCONTROL_1" newline bitfld.long 0x60 18. "GPMC_AD10_INPUTENABLE," "GPMC_AD10_INPUTENABLE_0,GPMC_AD10_INPUTENABLE_1" newline bitfld.long 0x60 17. "GPMC_AD10_PULLTYPESELECT," "GPMC_AD10_PULLTYPESELECT_0,GPMC_AD10_PULLTYPESELECT_1" newline bitfld.long 0x60 16. "GPMC_AD10_PULLUDENABLE," "GPMC_AD10_PULLUDENABLE_0,GPMC_AD10_PULLUDENABLE_1" newline hexmask.long.word 0x60 4.--15. 1. "RESERVED," newline bitfld.long 0x60 0.--3. "GPMC_AD10_MUXMODE," "GPMC_AD10_MUXMODE_0,?,?,GPMC_AD10_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD10_MUXMODE_14,GPMC_AD10_MUXMODE_15" line.long 0x64 "CTRL_CORE_PAD_GPMC_AD11," hexmask.long.word 0x64 20.--31. 1. "RESERVED," newline bitfld.long 0x64 19. "GPMC_AD11_SLEWCONTROL," "GPMC_AD11_SLEWCONTROL_0,GPMC_AD11_SLEWCONTROL_1" newline bitfld.long 0x64 18. "GPMC_AD11_INPUTENABLE," "GPMC_AD11_INPUTENABLE_0,GPMC_AD11_INPUTENABLE_1" newline bitfld.long 0x64 17. "GPMC_AD11_PULLTYPESELECT," "GPMC_AD11_PULLTYPESELECT_0,GPMC_AD11_PULLTYPESELECT_1" newline bitfld.long 0x64 16. "GPMC_AD11_PULLUDENABLE," "GPMC_AD11_PULLUDENABLE_0,GPMC_AD11_PULLUDENABLE_1" newline hexmask.long.word 0x64 4.--15. 1. "RESERVED," newline bitfld.long 0x64 0.--3. "GPMC_AD11_MUXMODE," "GPMC_AD11_MUXMODE_0,?,?,GPMC_AD11_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD11_MUXMODE_14,GPMC_AD11_MUXMODE_15" line.long 0x68 "CTRL_CORE_PAD_GPMC_AD12," hexmask.long.word 0x68 20.--31. 1. "RESERVED," newline bitfld.long 0x68 19. "GPMC_AD12_SLEWCONTROL," "GPMC_AD12_SLEWCONTROL_0,GPMC_AD12_SLEWCONTROL_1" newline bitfld.long 0x68 18. "GPMC_AD12_INPUTENABLE," "GPMC_AD12_INPUTENABLE_0,GPMC_AD12_INPUTENABLE_1" newline bitfld.long 0x68 17. "GPMC_AD12_PULLTYPESELECT," "GPMC_AD12_PULLTYPESELECT_0,GPMC_AD12_PULLTYPESELECT_1" newline bitfld.long 0x68 16. "GPMC_AD12_PULLUDENABLE," "GPMC_AD12_PULLUDENABLE_0,GPMC_AD12_PULLUDENABLE_1" newline hexmask.long.word 0x68 4.--15. 1. "RESERVED," newline bitfld.long 0x68 0.--3. "GPMC_AD12_MUXMODE," "GPMC_AD12_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_AD12_MUXMODE_14,GPMC_AD12_MUXMODE_15" line.long 0x6C "CTRL_CORE_PAD_GPMC_AD13," hexmask.long.word 0x6C 20.--31. 1. "RESERVED," newline bitfld.long 0x6C 19. "GPMC_AD13_SLEWCONTROL," "GPMC_AD13_SLEWCONTROL_0,GPMC_AD13_SLEWCONTROL_1" newline bitfld.long 0x6C 18. "GPMC_AD13_INPUTENABLE," "GPMC_AD13_INPUTENABLE_0,GPMC_AD13_INPUTENABLE_1" newline bitfld.long 0x6C 17. "GPMC_AD13_PULLTYPESELECT," "GPMC_AD13_PULLTYPESELECT_0,GPMC_AD13_PULLTYPESELECT_1" newline bitfld.long 0x6C 16. "GPMC_AD13_PULLUDENABLE," "GPMC_AD13_PULLUDENABLE_0,GPMC_AD13_PULLUDENABLE_1" newline hexmask.long.word 0x6C 4.--15. 1. "RESERVED," newline bitfld.long 0x6C 0.--3. "GPMC_AD13_MUXMODE," "GPMC_AD13_MUXMODE_0,GPMC_AD13_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_AD13_MUXMODE_14,GPMC_AD13_MUXMODE_15" line.long 0x70 "CTRL_CORE_PAD_GPMC_AD14," hexmask.long.word 0x70 20.--31. 1. "RESERVED," newline bitfld.long 0x70 19. "GPMC_AD14_SLEWCONTROL," "GPMC_AD14_SLEWCONTROL_0,GPMC_AD14_SLEWCONTROL_1" newline bitfld.long 0x70 18. "GPMC_AD14_INPUTENABLE," "GPMC_AD14_INPUTENABLE_0,GPMC_AD14_INPUTENABLE_1" newline bitfld.long 0x70 17. "GPMC_AD14_PULLTYPESELECT," "GPMC_AD14_PULLTYPESELECT_0,GPMC_AD14_PULLTYPESELECT_1" newline bitfld.long 0x70 16. "GPMC_AD14_PULLUDENABLE," "GPMC_AD14_PULLUDENABLE_0,GPMC_AD14_PULLUDENABLE_1" newline hexmask.long.word 0x70 4.--15. 1. "RESERVED," newline bitfld.long 0x70 0.--3. "GPMC_AD14_MUXMODE," "GPMC_AD14_MUXMODE_0,?,?,?,GPMC_AD14_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_AD14_MUXMODE_14,GPMC_AD14_MUXMODE_15" line.long 0x74 "CTRL_CORE_PAD_GPMC_AD15," hexmask.long.word 0x74 20.--31. 1. "RESERVED," newline bitfld.long 0x74 19. "GPMC_AD15_SLEWCONTROL," "GPMC_AD15_SLEWCONTROL_0,GPMC_AD15_SLEWCONTROL_1" newline bitfld.long 0x74 18. "GPMC_AD15_INPUTENABLE," "GPMC_AD15_INPUTENABLE_0,GPMC_AD15_INPUTENABLE_1" newline bitfld.long 0x74 17. "GPMC_AD15_PULLTYPESELECT," "GPMC_AD15_PULLTYPESELECT_0,GPMC_AD15_PULLTYPESELECT_1" newline bitfld.long 0x74 16. "GPMC_AD15_PULLUDENABLE," "GPMC_AD15_PULLUDENABLE_0,GPMC_AD15_PULLUDENABLE_1" newline hexmask.long.word 0x74 4.--15. 1. "RESERVED," newline bitfld.long 0x74 0.--3. "GPMC_AD15_MUXMODE," "GPMC_AD15_MUXMODE_0,?,?,?,GPMC_AD15_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_AD15_MUXMODE_14,GPMC_AD15_MUXMODE_15" line.long 0x78 "CTRL_CORE_PAD_VIN1A_CLK0," hexmask.long.word 0x78 20.--31. 1. "RESERVED," newline bitfld.long 0x78 19. "VIN1A_CLK0_SLEWCONTROL," "VIN1A_CLK0_SLEWCONTROL_0,VIN1A_CLK0_SLEWCONTROL_1" newline bitfld.long 0x78 18. "VIN1A_CLK0_INPUTENABLE," "VIN1A_CLK0_INPUTENABLE_0,VIN1A_CLK0_INPUTENABLE_1" newline bitfld.long 0x78 17. "VIN1A_CLK0_PULLTYPESELECT," "VIN1A_CLK0_PULLTYPESELECT_0,VIN1A_CLK0_PULLTYPESELECT_1" newline bitfld.long 0x78 16. "VIN1A_CLK0_PULLUDENABLE," "VIN1A_CLK0_PULLUDENABLE_0,VIN1A_CLK0_PULLUDENABLE_1" newline hexmask.long.word 0x78 4.--15. 1. "RESERVED," newline bitfld.long 0x78 0.--3. "VIN1A_CLK0_MUXMODE," "VIN1A_CLK0_MUXMODE_0,VIN1A_CLK0_MUXMODE_1,?,?,VIN1A_CLK0_MUXMODE_4,?,?,?,?,?,?,?,?,?,VIN1A_CLK0_MUXMODE_14,VIN1A_CLK0_MUXMODE_15" line.long 0x7C "CTRL_CORE_PAD_VIN1A_DE0," hexmask.long.word 0x7C 20.--31. 1. "RESERVED," newline bitfld.long 0x7C 19. "VIN1A_DE0_SLEWCONTROL," "VIN1A_DE0_SLEWCONTROL_0,VIN1A_DE0_SLEWCONTROL_1" newline bitfld.long 0x7C 18. "VIN1A_DE0_INPUTENABLE," "VIN1A_DE0_INPUTENABLE_0,VIN1A_DE0_INPUTENABLE_1" newline bitfld.long 0x7C 17. "VIN1A_DE0_PULLTYPESELECT," "VIN1A_DE0_PULLTYPESELECT_0,VIN1A_DE0_PULLTYPESELECT_1" newline bitfld.long 0x7C 16. "VIN1A_DE0_PULLUDENABLE," "VIN1A_DE0_PULLUDENABLE_0,VIN1A_DE0_PULLUDENABLE_1" newline hexmask.long.word 0x7C 4.--15. 1. "RESERVED," newline bitfld.long 0x7C 0.--3. "VIN1A_DE0_MUXMODE," "VIN1A_DE0_MUXMODE_0,VIN1A_DE0_MUXMODE_1,VIN1A_DE0_MUXMODE_2,?,VIN1A_DE0_MUXMODE_4,?,?,?,?,?,?,?,?,?,VIN1A_DE0_MUXMODE_14,VIN1A_DE0_MUXMODE_15" line.long 0x80 "CTRL_CORE_PAD_VIN1A_FLD0," hexmask.long.word 0x80 20.--31. 1. "RESERVED," newline bitfld.long 0x80 19. "VIN1A_FLD0_SLEWCONTROL," "VIN1A_FLD0_SLEWCONTROL_0,VIN1A_FLD0_SLEWCONTROL_1" newline bitfld.long 0x80 18. "VIN1A_FLD0_INPUTENABLE," "VIN1A_FLD0_INPUTENABLE_0,VIN1A_FLD0_INPUTENABLE_1" newline bitfld.long 0x80 17. "VIN1A_FLD0_PULLTYPESELECT," "VIN1A_FLD0_PULLTYPESELECT_0,VIN1A_FLD0_PULLTYPESELECT_1" newline bitfld.long 0x80 16. "VIN1A_FLD0_PULLUDENABLE," "VIN1A_FLD0_PULLUDENABLE_0,VIN1A_FLD0_PULLUDENABLE_1" newline hexmask.long.word 0x80 4.--15. 1. "RESERVED," newline bitfld.long 0x80 0.--3. "VIN1A_FLD0_MUXMODE," "VIN1A_FLD0_MUXMODE_0,VIN1A_FLD0_MUXMODE_1,VIN1A_FLD0_MUXMODE_2,?,VIN1A_FLD0_MUXMODE_4,?,?,?,?,?,?,?,?,?,VIN1A_FLD0_MUXMODE_14,VIN1A_FLD0_MUXMODE_15" line.long 0x84 "CTRL_CORE_PAD_VIN1A_HSYNC0," hexmask.long.word 0x84 20.--31. 1. "RESERVED," newline bitfld.long 0x84 19. "VIN1A_HSYNC0_SLEWCONTROL," "VIN1A_HSYNC0_SLEWCONTROL_0,VIN1A_HSYNC0_SLEWCONTROL_1" newline bitfld.long 0x84 18. "VIN1A_HSYNC0_INPUTENABLE," "VIN1A_HSYNC0_INPUTENABLE_0,VIN1A_HSYNC0_INPUTENABLE_1" newline bitfld.long 0x84 17. "VIN1A_HSYNC0_PULLTYPESELECT," "VIN1A_HSYNC0_PULLTYPESELECT_0,VIN1A_HSYNC0_PULLTYPESELECT_1" newline bitfld.long 0x84 16. "VIN1A_HSYNC0_PULLUDENABLE," "VIN1A_HSYNC0_PULLUDENABLE_0,VIN1A_HSYNC0_PULLUDENABLE_1" newline hexmask.long.word 0x84 4.--15. 1. "RESERVED," newline bitfld.long 0x84 0.--3. "VIN1A_HSYNC0_MUXMODE," "VIN1A_HSYNC0_MUXMODE_0,VIN1A_HSYNC0_MUXMODE_1,VIN1A_HSYNC0_MUXMODE_2,?,?,?,?,?,?,?,?,?,?,?,VIN1A_HSYNC0_MUXMODE_14,VIN1A_HSYNC0_MUXMODE_15" line.long 0x88 "CTRL_CORE_PAD_VIN1A_VSYNC0," hexmask.long.word 0x88 20.--31. 1. "RESERVED," newline bitfld.long 0x88 19. "VIN1A_VSYNC0_SLEWCONTROL," "VIN1A_VSYNC0_SLEWCONTROL_0,VIN1A_VSYNC0_SLEWCONTROL_1" newline bitfld.long 0x88 18. "VIN1A_VSYNC0_INPUTENABLE," "VIN1A_VSYNC0_INPUTENABLE_0,VIN1A_VSYNC0_INPUTENABLE_1" newline bitfld.long 0x88 17. "VIN1A_VSYNC0_PULLTYPESELECT," "VIN1A_VSYNC0_PULLTYPESELECT_0,VIN1A_VSYNC0_PULLTYPESELECT_1" newline bitfld.long 0x88 16. "VIN1A_VSYNC0_PULLUDENABLE," "VIN1A_VSYNC0_PULLUDENABLE_0,VIN1A_VSYNC0_PULLUDENABLE_1" newline hexmask.long.word 0x88 4.--15. 1. "RESERVED," newline bitfld.long 0x88 0.--3. "VIN1A_VSYNC0_MUXMODE," "VIN1A_VSYNC0_MUXMODE_0,VIN1A_VSYNC0_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_VSYNC0_MUXMODE_14,VIN1A_VSYNC0_MUXMODE_15" line.long 0x8C "CTRL_CORE_PAD_VIN1A_D0," hexmask.long.word 0x8C 20.--31. 1. "RESERVED," newline bitfld.long 0x8C 19. "VIN1A_D0_SLEWCONTROL," "VIN1A_D0_SLEWCONTROL_0,VIN1A_D0_SLEWCONTROL_1" newline bitfld.long 0x8C 18. "VIN1A_D0_INPUTENABLE," "VIN1A_D0_INPUTENABLE_0,VIN1A_D0_INPUTENABLE_1" newline bitfld.long 0x8C 17. "VIN1A_D0_PULLTYPESELECT," "VIN1A_D0_PULLTYPESELECT_0,VIN1A_D0_PULLTYPESELECT_1" newline bitfld.long 0x8C 16. "VIN1A_D0_PULLUDENABLE," "VIN1A_D0_PULLUDENABLE_0,VIN1A_D0_PULLUDENABLE_1" newline hexmask.long.word 0x8C 4.--15. 1. "RESERVED," newline bitfld.long 0x8C 0.--3. "VIN1A_D0_MUXMODE," "VIN1A_D0_MUXMODE_0,VIN1A_D0_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_D0_MUXMODE_14,VIN1A_D0_MUXMODE_15" line.long 0x90 "CTRL_CORE_PAD_VIN1A_D1," hexmask.long.word 0x90 20.--31. 1. "RESERVED," newline bitfld.long 0x90 19. "VIN1A_D1_SLEWCONTROL," "VIN1A_D1_SLEWCONTROL_0,VIN1A_D1_SLEWCONTROL_1" newline bitfld.long 0x90 18. "VIN1A_D1_INPUTENABLE," "VIN1A_D1_INPUTENABLE_0,VIN1A_D1_INPUTENABLE_1" newline bitfld.long 0x90 17. "VIN1A_D1_PULLTYPESELECT," "VIN1A_D1_PULLTYPESELECT_0,VIN1A_D1_PULLTYPESELECT_1" newline bitfld.long 0x90 16. "VIN1A_D1_PULLUDENABLE," "VIN1A_D1_PULLUDENABLE_0,VIN1A_D1_PULLUDENABLE_1" newline hexmask.long.word 0x90 4.--15. 1. "RESERVED," newline bitfld.long 0x90 0.--3. "VIN1A_D1_MUXMODE," "VIN1A_D1_MUXMODE_0,VIN1A_D1_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_D1_MUXMODE_14,VIN1A_D1_MUXMODE_15" line.long 0x94 "CTRL_CORE_PAD_VIN1A_D2," hexmask.long.word 0x94 20.--31. 1. "RESERVED," newline bitfld.long 0x94 19. "VIN1A_D2_SLEWCONTROL," "VIN1A_D2_SLEWCONTROL_0,VIN1A_D2_SLEWCONTROL_1" newline bitfld.long 0x94 18. "VIN1A_D2_INPUTENABLE," "VIN1A_D2_INPUTENABLE_0,VIN1A_D2_INPUTENABLE_1" newline bitfld.long 0x94 17. "VIN1A_D2_PULLTYPESELECT," "VIN1A_D2_PULLTYPESELECT_0,VIN1A_D2_PULLTYPESELECT_1" newline bitfld.long 0x94 16. "VIN1A_D2_PULLUDENABLE," "VIN1A_D2_PULLUDENABLE_0,VIN1A_D2_PULLUDENABLE_1" newline hexmask.long.word 0x94 4.--15. 1. "RESERVED," newline bitfld.long 0x94 0.--3. "VIN1A_D2_MUXMODE," "VIN1A_D2_MUXMODE_0,VIN1A_D2_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_D2_MUXMODE_14,VIN1A_D2_MUXMODE_15" line.long 0x98 "CTRL_CORE_PAD_VIN1A_D3," hexmask.long.word 0x98 20.--31. 1. "RESERVED," newline bitfld.long 0x98 19. "VIN1A_D3_SLEWCONTROL," "VIN1A_D3_SLEWCONTROL_0,VIN1A_D3_SLEWCONTROL_1" newline bitfld.long 0x98 18. "VIN1A_D3_INPUTENABLE," "VIN1A_D3_INPUTENABLE_0,VIN1A_D3_INPUTENABLE_1" newline bitfld.long 0x98 17. "VIN1A_D3_PULLTYPESELECT," "VIN1A_D3_PULLTYPESELECT_0,VIN1A_D3_PULLTYPESELECT_1" newline bitfld.long 0x98 16. "VIN1A_D3_PULLUDENABLE," "VIN1A_D3_PULLUDENABLE_0,VIN1A_D3_PULLUDENABLE_1" newline hexmask.long.word 0x98 4.--15. 1. "RESERVED," newline bitfld.long 0x98 0.--3. "VIN1A_D3_MUXMODE," "VIN1A_D3_MUXMODE_0,VIN1A_D3_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_D3_MUXMODE_14,VIN1A_D3_MUXMODE_15" line.long 0x9C "CTRL_CORE_PAD_VIN1A_D4," hexmask.long.word 0x9C 20.--31. 1. "RESERVED," newline bitfld.long 0x9C 19. "VIN1A_D4_SLEWCONTROL," "VIN1A_D4_SLEWCONTROL_0,VIN1A_D4_SLEWCONTROL_1" newline bitfld.long 0x9C 18. "VIN1A_D4_INPUTENABLE," "VIN1A_D4_INPUTENABLE_0,VIN1A_D4_INPUTENABLE_1" newline bitfld.long 0x9C 17. "VIN1A_D4_PULLTYPESELECT," "VIN1A_D4_PULLTYPESELECT_0,VIN1A_D4_PULLTYPESELECT_1" newline bitfld.long 0x9C 16. "VIN1A_D4_PULLUDENABLE," "VIN1A_D4_PULLUDENABLE_0,VIN1A_D4_PULLUDENABLE_1" newline hexmask.long.word 0x9C 4.--15. 1. "RESERVED," newline bitfld.long 0x9C 0.--3. "VIN1A_D4_MUXMODE," "VIN1A_D4_MUXMODE_0,VIN1A_D4_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_D4_MUXMODE_14,VIN1A_D4_MUXMODE_15" line.long 0xA0 "CTRL_CORE_PAD_VIN1A_D5," hexmask.long.word 0xA0 20.--31. 1. "RESERVED," newline bitfld.long 0xA0 19. "VIN1A_D5_SLEWCONTROL," "VIN1A_D5_SLEWCONTROL_0,VIN1A_D5_SLEWCONTROL_1" newline bitfld.long 0xA0 18. "VIN1A_D5_INPUTENABLE," "VIN1A_D5_INPUTENABLE_0,VIN1A_D5_INPUTENABLE_1" newline bitfld.long 0xA0 17. "VIN1A_D5_PULLTYPESELECT," "VIN1A_D5_PULLTYPESELECT_0,VIN1A_D5_PULLTYPESELECT_1" newline bitfld.long 0xA0 16. "VIN1A_D5_PULLUDENABLE," "VIN1A_D5_PULLUDENABLE_0,VIN1A_D5_PULLUDENABLE_1" newline hexmask.long.word 0xA0 4.--15. 1. "RESERVED," newline bitfld.long 0xA0 0.--3. "VIN1A_D5_MUXMODE," "VIN1A_D5_MUXMODE_0,VIN1A_D5_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_D5_MUXMODE_14,VIN1A_D5_MUXMODE_15" line.long 0xA4 "CTRL_CORE_PAD_VIN1A_D6," hexmask.long.word 0xA4 20.--31. 1. "RESERVED," newline bitfld.long 0xA4 19. "VIN1A_D6_SLEWCONTROL," "VIN1A_D6_SLEWCONTROL_0,VIN1A_D6_SLEWCONTROL_1" newline bitfld.long 0xA4 18. "VIN1A_D6_INPUTENABLE," "VIN1A_D6_INPUTENABLE_0,VIN1A_D6_INPUTENABLE_1" newline bitfld.long 0xA4 17. "VIN1A_D6_PULLTYPESELECT," "VIN1A_D6_PULLTYPESELECT_0,VIN1A_D6_PULLTYPESELECT_1" newline bitfld.long 0xA4 16. "VIN1A_D6_PULLUDENABLE," "VIN1A_D6_PULLUDENABLE_0,VIN1A_D6_PULLUDENABLE_1" newline hexmask.long.word 0xA4 4.--15. 1. "RESERVED," newline bitfld.long 0xA4 0.--3. "VIN1A_D6_MUXMODE," "VIN1A_D6_MUXMODE_0,VIN1A_D6_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_D6_MUXMODE_14,VIN1A_D6_MUXMODE_15" line.long 0xA8 "CTRL_CORE_PAD_VIN1A_D7," hexmask.long.word 0xA8 20.--31. 1. "RESERVED," newline bitfld.long 0xA8 19. "VIN1A_D7_SLEWCONTROL," "VIN1A_D7_SLEWCONTROL_0,VIN1A_D7_SLEWCONTROL_1" newline bitfld.long 0xA8 18. "VIN1A_D7_INPUTENABLE," "VIN1A_D7_INPUTENABLE_0,VIN1A_D7_INPUTENABLE_1" newline bitfld.long 0xA8 17. "VIN1A_D7_PULLTYPESELECT," "VIN1A_D7_PULLTYPESELECT_0,VIN1A_D7_PULLTYPESELECT_1" newline bitfld.long 0xA8 16. "VIN1A_D7_PULLUDENABLE," "VIN1A_D7_PULLUDENABLE_0,VIN1A_D7_PULLUDENABLE_1" newline hexmask.long.word 0xA8 4.--15. 1. "RESERVED," newline bitfld.long 0xA8 0.--3. "VIN1A_D7_MUXMODE," "VIN1A_D7_MUXMODE_0,VIN1A_D7_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,VIN1A_D7_MUXMODE_14,VIN1A_D7_MUXMODE_15" line.long 0xAC "CTRL_CORE_PAD_VIN1A_D8," hexmask.long.word 0xAC 20.--31. 1. "RESERVED," newline bitfld.long 0xAC 19. "VIN1A_D8_SLEWCONTROL," "VIN1A_D8_SLEWCONTROL_0,VIN1A_D8_SLEWCONTROL_1" newline bitfld.long 0xAC 18. "VIN1A_D8_INPUTENABLE," "VIN1A_D8_INPUTENABLE_0,VIN1A_D8_INPUTENABLE_1" newline bitfld.long 0xAC 17. "VIN1A_D8_PULLTYPESELECT," "VIN1A_D8_PULLTYPESELECT_0,VIN1A_D8_PULLTYPESELECT_1" newline bitfld.long 0xAC 16. "VIN1A_D8_PULLUDENABLE," "VIN1A_D8_PULLUDENABLE_0,VIN1A_D8_PULLUDENABLE_1" newline hexmask.long.word 0xAC 4.--15. 1. "RESERVED," newline bitfld.long 0xAC 0.--3. "VIN1A_D8_MUXMODE," "VIN1A_D8_MUXMODE_0,VIN1A_D8_MUXMODE_1,VIN1A_D8_MUXMODE_2,VIN1A_D8_MUXMODE_3,?,?,?,VIN1A_D8_MUXMODE_7,?,?,?,?,?,?,VIN1A_D8_MUXMODE_14,VIN1A_D8_MUXMODE_15" line.long 0xB0 "CTRL_CORE_PAD_VIN1A_D9," hexmask.long.word 0xB0 20.--31. 1. "RESERVED," newline bitfld.long 0xB0 19. "VIN1A_D9_SLEWCONTROL," "VIN1A_D9_SLEWCONTROL_0,VIN1A_D9_SLEWCONTROL_1" newline bitfld.long 0xB0 18. "VIN1A_D9_INPUTENABLE," "VIN1A_D9_INPUTENABLE_0,VIN1A_D9_INPUTENABLE_1" newline bitfld.long 0xB0 17. "VIN1A_D9_PULLTYPESELECT," "VIN1A_D9_PULLTYPESELECT_0,VIN1A_D9_PULLTYPESELECT_1" newline bitfld.long 0xB0 16. "VIN1A_D9_PULLUDENABLE," "VIN1A_D9_PULLUDENABLE_0,VIN1A_D9_PULLUDENABLE_1" newline hexmask.long.word 0xB0 4.--15. 1. "RESERVED," newline bitfld.long 0xB0 0.--3. "VIN1A_D9_MUXMODE," "VIN1A_D9_MUXMODE_0,VIN1A_D9_MUXMODE_1,VIN1A_D9_MUXMODE_2,VIN1A_D9_MUXMODE_3,?,?,?,VIN1A_D9_MUXMODE_7,?,?,?,?,?,?,VIN1A_D9_MUXMODE_14,VIN1A_D9_MUXMODE_15" line.long 0xB4 "CTRL_CORE_PAD_VIN1A_D10," hexmask.long.word 0xB4 20.--31. 1. "RESERVED," newline bitfld.long 0xB4 19. "VIN1A_D10_SLEWCONTROL," "VIN1A_D10_SLEWCONTROL_0,VIN1A_D10_SLEWCONTROL_1" newline bitfld.long 0xB4 18. "VIN1A_D10_INPUTENABLE," "VIN1A_D10_INPUTENABLE_0,VIN1A_D10_INPUTENABLE_1" newline bitfld.long 0xB4 17. "VIN1A_D10_PULLTYPESELECT," "VIN1A_D10_PULLTYPESELECT_0,VIN1A_D10_PULLTYPESELECT_1" newline bitfld.long 0xB4 16. "VIN1A_D10_PULLUDENABLE," "VIN1A_D10_PULLUDENABLE_0,VIN1A_D10_PULLUDENABLE_1" newline hexmask.long.word 0xB4 4.--15. 1. "RESERVED," newline bitfld.long 0xB4 0.--3. "VIN1A_D10_MUXMODE," "VIN1A_D10_MUXMODE_0,VIN1A_D10_MUXMODE_1,VIN1A_D10_MUXMODE_2,VIN1A_D10_MUXMODE_3,?,?,?,VIN1A_D10_MUXMODE_7,?,?,?,?,?,?,VIN1A_D10_MUXMODE_14,VIN1A_D10_MUXMODE_15" line.long 0xB8 "CTRL_CORE_PAD_VIN1A_D11," hexmask.long.word 0xB8 20.--31. 1. "RESERVED," newline bitfld.long 0xB8 19. "VIN1A_D11_SLEWCONTROL," "VIN1A_D11_SLEWCONTROL_0,VIN1A_D11_SLEWCONTROL_1" newline bitfld.long 0xB8 18. "VIN1A_D11_INPUTENABLE," "VIN1A_D11_INPUTENABLE_0,VIN1A_D11_INPUTENABLE_1" newline bitfld.long 0xB8 17. "VIN1A_D11_PULLTYPESELECT," "VIN1A_D11_PULLTYPESELECT_0,VIN1A_D11_PULLTYPESELECT_1" newline bitfld.long 0xB8 16. "VIN1A_D11_PULLUDENABLE," "VIN1A_D11_PULLUDENABLE_0,VIN1A_D11_PULLUDENABLE_1" newline hexmask.long.word 0xB8 4.--15. 1. "RESERVED," newline bitfld.long 0xB8 0.--3. "VIN1A_D11_MUXMODE," "VIN1A_D11_MUXMODE_0,VIN1A_D11_MUXMODE_1,VIN1A_D11_MUXMODE_2,VIN1A_D11_MUXMODE_3,?,?,?,VIN1A_D11_MUXMODE_7,?,?,?,?,?,?,VIN1A_D11_MUXMODE_14,VIN1A_D11_MUXMODE_15" line.long 0xBC "CTRL_CORE_PAD_VIN1A_D12," hexmask.long.word 0xBC 20.--31. 1. "RESERVED," newline bitfld.long 0xBC 19. "VIN1A_D12_SLEWCONTROL," "VIN1A_D12_SLEWCONTROL_0,VIN1A_D12_SLEWCONTROL_1" newline bitfld.long 0xBC 18. "VIN1A_D12_INPUTENABLE," "VIN1A_D12_INPUTENABLE_0,VIN1A_D12_INPUTENABLE_1" newline bitfld.long 0xBC 17. "VIN1A_D12_PULLTYPESELECT," "VIN1A_D12_PULLTYPESELECT_0,VIN1A_D12_PULLTYPESELECT_1" newline bitfld.long 0xBC 16. "VIN1A_D12_PULLUDENABLE," "VIN1A_D12_PULLUDENABLE_0,VIN1A_D12_PULLUDENABLE_1" newline hexmask.long.word 0xBC 4.--15. 1. "RESERVED," newline bitfld.long 0xBC 0.--3. "VIN1A_D12_MUXMODE," "VIN1A_D12_MUXMODE_0,VIN1A_D12_MUXMODE_1,VIN1A_D12_MUXMODE_2,VIN1A_D12_MUXMODE_3,?,?,VIN1A_D12_MUXMODE_6,?,?,?,?,?,?,?,VIN1A_D12_MUXMODE_14,VIN1A_D12_MUXMODE_15" line.long 0xC0 "CTRL_CORE_PAD_VIN1A_D13," hexmask.long.word 0xC0 20.--31. 1. "RESERVED," newline bitfld.long 0xC0 19. "VIN1A_D13_SLEWCONTROL," "VIN1A_D13_SLEWCONTROL_0,VIN1A_D13_SLEWCONTROL_1" newline bitfld.long 0xC0 18. "VIN1A_D13_INPUTENABLE," "VIN1A_D13_INPUTENABLE_0,VIN1A_D13_INPUTENABLE_1" newline bitfld.long 0xC0 17. "VIN1A_D13_PULLTYPESELECT," "VIN1A_D13_PULLTYPESELECT_0,VIN1A_D13_PULLTYPESELECT_1" newline bitfld.long 0xC0 16. "VIN1A_D13_PULLUDENABLE," "VIN1A_D13_PULLUDENABLE_0,VIN1A_D13_PULLUDENABLE_1" newline hexmask.long.word 0xC0 4.--15. 1. "RESERVED," newline bitfld.long 0xC0 0.--3. "VIN1A_D13_MUXMODE," "VIN1A_D13_MUXMODE_0,VIN1A_D13_MUXMODE_1,VIN1A_D13_MUXMODE_2,VIN1A_D13_MUXMODE_3,?,?,VIN1A_D13_MUXMODE_6,?,?,?,?,?,?,?,VIN1A_D13_MUXMODE_14,VIN1A_D13_MUXMODE_15" line.long 0xC4 "CTRL_CORE_PAD_VIN1A_D14," hexmask.long.word 0xC4 20.--31. 1. "RESERVED," newline bitfld.long 0xC4 19. "VIN1A_D14_SLEWCONTROL," "VIN1A_D14_SLEWCONTROL_0,VIN1A_D14_SLEWCONTROL_1" newline bitfld.long 0xC4 18. "VIN1A_D14_INPUTENABLE," "VIN1A_D14_INPUTENABLE_0,VIN1A_D14_INPUTENABLE_1" newline bitfld.long 0xC4 17. "VIN1A_D14_PULLTYPESELECT," "VIN1A_D14_PULLTYPESELECT_0,VIN1A_D14_PULLTYPESELECT_1" newline bitfld.long 0xC4 16. "VIN1A_D14_PULLUDENABLE," "VIN1A_D14_PULLUDENABLE_0,VIN1A_D14_PULLUDENABLE_1" newline hexmask.long.word 0xC4 4.--15. 1. "RESERVED," newline bitfld.long 0xC4 0.--3. "VIN1A_D14_MUXMODE," "VIN1A_D14_MUXMODE_0,VIN1A_D14_MUXMODE_1,VIN1A_D14_MUXMODE_2,VIN1A_D14_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,VIN1A_D14_MUXMODE_14,VIN1A_D14_MUXMODE_15" line.long 0xC8 "CTRL_CORE_PAD_VIN1A_D15," hexmask.long.word 0xC8 20.--31. 1. "RESERVED," newline bitfld.long 0xC8 19. "VIN1A_D15_SLEWCONTROL," "VIN1A_D15_SLEWCONTROL_0,VIN1A_D15_SLEWCONTROL_1" newline bitfld.long 0xC8 18. "VIN1A_D15_INPUTENABLE," "VIN1A_D15_INPUTENABLE_0,VIN1A_D15_INPUTENABLE_1" newline bitfld.long 0xC8 17. "VIN1A_D15_PULLTYPESELECT," "VIN1A_D15_PULLTYPESELECT_0,VIN1A_D15_PULLTYPESELECT_1" newline bitfld.long 0xC8 16. "VIN1A_D15_PULLUDENABLE," "VIN1A_D15_PULLUDENABLE_0,VIN1A_D15_PULLUDENABLE_1" newline hexmask.long.word 0xC8 4.--15. 1. "RESERVED," newline bitfld.long 0xC8 0.--3. "VIN1A_D15_MUXMODE," "VIN1A_D15_MUXMODE_0,VIN1A_D15_MUXMODE_1,VIN1A_D15_MUXMODE_2,VIN1A_D15_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,VIN1A_D15_MUXMODE_14,VIN1A_D15_MUXMODE_15" line.long 0xCC "CTRL_CORE_PAD_VIN2A_CLK0," hexmask.long.word 0xCC 20.--31. 1. "RESERVED," newline bitfld.long 0xCC 19. "VIN2A_CLK0_SLEWCONTROL," "VIN2A_CLK0_SLEWCONTROL_0,VIN2A_CLK0_SLEWCONTROL_1" newline bitfld.long 0xCC 18. "VIN2A_CLK0_INPUTENABLE," "VIN2A_CLK0_INPUTENABLE_0,VIN2A_CLK0_INPUTENABLE_1" newline bitfld.long 0xCC 17. "VIN2A_CLK0_PULLTYPESELECT," "VIN2A_CLK0_PULLTYPESELECT_0,VIN2A_CLK0_PULLTYPESELECT_1" newline bitfld.long 0xCC 16. "VIN2A_CLK0_PULLUDENABLE," "VIN2A_CLK0_PULLUDENABLE_0,VIN2A_CLK0_PULLUDENABLE_1" newline hexmask.long.word 0xCC 4.--15. 1. "RESERVED," newline bitfld.long 0xCC 0.--3. "VIN2A_CLK0_MUXMODE," "VIN2A_CLK0_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,VIN2A_CLK0_MUXMODE_14,VIN2A_CLK0_MUXMODE_15" line.long 0xD0 "CTRL_CORE_PAD_VIN2A_DE0," hexmask.long.word 0xD0 20.--31. 1. "RESERVED," newline bitfld.long 0xD0 19. "VIN2A_DE0_SLEWCONTROL," "VIN2A_DE0_SLEWCONTROL_0,VIN2A_DE0_SLEWCONTROL_1" newline bitfld.long 0xD0 18. "VIN2A_DE0_INPUTENABLE," "VIN2A_DE0_INPUTENABLE_0,VIN2A_DE0_INPUTENABLE_1" newline bitfld.long 0xD0 17. "VIN2A_DE0_PULLTYPESELECT," "VIN2A_DE0_PULLTYPESELECT_0,VIN2A_DE0_PULLTYPESELECT_1" newline bitfld.long 0xD0 16. "VIN2A_DE0_PULLUDENABLE," "VIN2A_DE0_PULLUDENABLE_0,VIN2A_DE0_PULLUDENABLE_1" newline hexmask.long.word 0xD0 4.--15. 1. "RESERVED," newline bitfld.long 0xD0 0.--3. "VIN2A_DE0_MUXMODE," "VIN2A_DE0_MUXMODE_0,VIN2A_DE0_MUXMODE_1,VIN2A_DE0_MUXMODE_2,?,?,VIN2A_DE0_MUXMODE_5,?,?,?,?,?,?,?,?,VIN2A_DE0_MUXMODE_14,VIN2A_DE0_MUXMODE_15" line.long 0xD4 "CTRL_CORE_PAD_VIN2A_FLD0," hexmask.long.word 0xD4 20.--31. 1. "RESERVED," newline bitfld.long 0xD4 19. "VIN2A_FLD0_SLEWCONTROL," "VIN2A_FLD0_SLEWCONTROL_0,VIN2A_FLD0_SLEWCONTROL_1" newline bitfld.long 0xD4 18. "VIN2A_FLD0_INPUTENABLE," "VIN2A_FLD0_INPUTENABLE_0,VIN2A_FLD0_INPUTENABLE_1" newline bitfld.long 0xD4 17. "VIN2A_FLD0_PULLTYPESELECT," "VIN2A_FLD0_PULLTYPESELECT_0,VIN2A_FLD0_PULLTYPESELECT_1" newline bitfld.long 0xD4 16. "VIN2A_FLD0_PULLUDENABLE," "VIN2A_FLD0_PULLUDENABLE_0,VIN2A_FLD0_PULLUDENABLE_1" newline hexmask.long.word 0xD4 4.--15. 1. "RESERVED," newline bitfld.long 0xD4 0.--3. "VIN2A_FLD0_MUXMODE," "VIN2A_FLD0_MUXMODE_0,VIN2A_FLD0_MUXMODE_1,VIN2A_FLD0_MUXMODE_2,?,?,?,?,?,?,?,?,?,?,?,VIN2A_FLD0_MUXMODE_14,VIN2A_FLD0_MUXMODE_15" line.long 0xD8 "CTRL_CORE_PAD_VOUT1_CLK," hexmask.long.word 0xD8 20.--31. 1. "RESERVED," newline bitfld.long 0xD8 19. "VOUT1_CLK_SLEWCONTROL," "VOUT1_CLK_SLEWCONTROL_0,VOUT1_CLK_SLEWCONTROL_1" newline bitfld.long 0xD8 18. "VOUT1_CLK_INPUTENABLE," "VOUT1_CLK_INPUTENABLE_0,VOUT1_CLK_INPUTENABLE_1" newline bitfld.long 0xD8 17. "VOUT1_CLK_PULLTYPESELECT," "VOUT1_CLK_PULLTYPESELECT_0,VOUT1_CLK_PULLTYPESELECT_1" newline bitfld.long 0xD8 16. "VOUT1_CLK_PULLUDENABLE," "VOUT1_CLK_PULLUDENABLE_0,VOUT1_CLK_PULLUDENABLE_1" newline hexmask.long.word 0xD8 4.--15. 1. "RESERVED," newline bitfld.long 0xD8 0.--3. "VOUT1_CLK_MUXMODE," "VOUT1_CLK_MUXMODE_0,?,VOUT1_CLK_MUXMODE_2,?,VOUT1_CLK_MUXMODE_4,?,?,?,?,VOUT1_CLK_MUXMODE_9,?,?,?,?,VOUT1_CLK_MUXMODE_14,VOUT1_CLK_MUXMODE_15" line.long 0xDC "CTRL_CORE_PAD_VOUT1_DE," hexmask.long.word 0xDC 20.--31. 1. "RESERVED," newline bitfld.long 0xDC 19. "VOUT1_DE_SLEWCONTROL," "VOUT1_DE_SLEWCONTROL_0,VOUT1_DE_SLEWCONTROL_1" newline bitfld.long 0xDC 18. "VOUT1_DE_INPUTENABLE," "VOUT1_DE_INPUTENABLE_0,VOUT1_DE_INPUTENABLE_1" newline bitfld.long 0xDC 17. "VOUT1_DE_PULLTYPESELECT," "VOUT1_DE_PULLTYPESELECT_0,VOUT1_DE_PULLTYPESELECT_1" newline bitfld.long 0xDC 16. "VOUT1_DE_PULLUDENABLE," "VOUT1_DE_PULLUDENABLE_0,VOUT1_DE_PULLUDENABLE_1" newline hexmask.long.word 0xDC 4.--15. 1. "RESERVED," newline bitfld.long 0xDC 0.--3. "VOUT1_DE_MUXMODE," "VOUT1_DE_MUXMODE_0,VOUT1_DE_MUXMODE_1,VOUT1_DE_MUXMODE_2,?,VOUT1_DE_MUXMODE_4,?,?,?,?,?,?,?,?,?,VOUT1_DE_MUXMODE_14,VOUT1_DE_MUXMODE_15" line.long 0xE0 "CTRL_CORE_PAD_VOUT1_FLD," hexmask.long.word 0xE0 20.--31. 1. "RESERVED," newline bitfld.long 0xE0 19. "VOUT1_FLD_SLEWCONTROL," "VOUT1_FLD_SLEWCONTROL_0,VOUT1_FLD_SLEWCONTROL_1" newline bitfld.long 0xE0 18. "VOUT1_FLD_INPUTENABLE," "VOUT1_FLD_INPUTENABLE_0,VOUT1_FLD_INPUTENABLE_1" newline bitfld.long 0xE0 17. "VOUT1_FLD_PULLTYPESELECT," "VOUT1_FLD_PULLTYPESELECT_0,VOUT1_FLD_PULLTYPESELECT_1" newline bitfld.long 0xE0 16. "VOUT1_FLD_PULLUDENABLE," "VOUT1_FLD_PULLUDENABLE_0,VOUT1_FLD_PULLUDENABLE_1" newline hexmask.long.word 0xE0 4.--15. 1. "RESERVED," newline bitfld.long 0xE0 0.--3. "VOUT1_FLD_MUXMODE," "VOUT1_FLD_MUXMODE_0,VOUT1_FLD_MUXMODE_1,VOUT1_FLD_MUXMODE_2,?,VOUT1_FLD_MUXMODE_4,?,?,?,?,?,?,?,?,?,VOUT1_FLD_MUXMODE_14,VOUT1_FLD_MUXMODE_15" line.long 0xE4 "CTRL_CORE_PAD_VOUT1_HSYNC," hexmask.long.word 0xE4 20.--31. 1. "RESERVED," newline bitfld.long 0xE4 19. "VOUT1_HSYNC_SLEWCONTROL," "VOUT1_HSYNC_SLEWCONTROL_0,VOUT1_HSYNC_SLEWCONTROL_1" newline bitfld.long 0xE4 18. "VOUT1_HSYNC_INPUTENABLE," "VOUT1_HSYNC_INPUTENABLE_0,VOUT1_HSYNC_INPUTENABLE_1" newline bitfld.long 0xE4 17. "VOUT1_HSYNC_PULLTYPESELECT," "VOUT1_HSYNC_PULLTYPESELECT_0,VOUT1_HSYNC_PULLTYPESELECT_1" newline bitfld.long 0xE4 16. "VOUT1_HSYNC_PULLUDENABLE," "VOUT1_HSYNC_PULLUDENABLE_0,VOUT1_HSYNC_PULLUDENABLE_1" newline hexmask.long.word 0xE4 4.--15. 1. "RESERVED," newline bitfld.long 0xE4 0.--3. "VOUT1_HSYNC_MUXMODE," "VOUT1_HSYNC_MUXMODE_0,VOUT1_HSYNC_MUXMODE_1,VOUT1_HSYNC_MUXMODE_2,?,?,?,?,?,?,VOUT1_HSYNC_MUXMODE_9,?,?,?,?,VOUT1_HSYNC_MUXMODE_14,VOUT1_HSYNC_MUXMODE_15" line.long 0xE8 "CTRL_CORE_PAD_VOUT1_VSYNC," hexmask.long.word 0xE8 20.--31. 1. "RESERVED," newline bitfld.long 0xE8 19. "VOUT1_VSYNC_SLEWCONTROL," "VOUT1_VSYNC_SLEWCONTROL_0,VOUT1_VSYNC_SLEWCONTROL_1" newline bitfld.long 0xE8 18. "VOUT1_VSYNC_INPUTENABLE," "VOUT1_VSYNC_INPUTENABLE_0,VOUT1_VSYNC_INPUTENABLE_1" newline bitfld.long 0xE8 17. "VOUT1_VSYNC_PULLTYPESELECT," "VOUT1_VSYNC_PULLTYPESELECT_0,VOUT1_VSYNC_PULLTYPESELECT_1" newline bitfld.long 0xE8 16. "VOUT1_VSYNC_PULLUDENABLE," "VOUT1_VSYNC_PULLUDENABLE_0,VOUT1_VSYNC_PULLUDENABLE_1" newline hexmask.long.word 0xE8 4.--15. 1. "RESERVED," newline bitfld.long 0xE8 0.--3. "VOUT1_VSYNC_MUXMODE," "VOUT1_VSYNC_MUXMODE_0,VOUT1_VSYNC_MUXMODE_1,VOUT1_VSYNC_MUXMODE_2,?,?,?,?,?,?,VOUT1_VSYNC_MUXMODE_9,?,?,?,?,VOUT1_VSYNC_MUXMODE_14,VOUT1_VSYNC_MUXMODE_15" line.long 0xEC "CTRL_CORE_PAD_VOUT1_D0," hexmask.long.word 0xEC 20.--31. 1. "RESERVED," newline bitfld.long 0xEC 19. "VOUT1_D0_SLEWCONTROL," "VOUT1_D0_SLEWCONTROL_0,VOUT1_D0_SLEWCONTROL_1" newline bitfld.long 0xEC 18. "VOUT1_D0_INPUTENABLE," "VOUT1_D0_INPUTENABLE_0,VOUT1_D0_INPUTENABLE_1" newline bitfld.long 0xEC 17. "VOUT1_D0_PULLTYPESELECT," "VOUT1_D0_PULLTYPESELECT_0,VOUT1_D0_PULLTYPESELECT_1" newline bitfld.long 0xEC 16. "VOUT1_D0_PULLUDENABLE," "VOUT1_D0_PULLUDENABLE_0,VOUT1_D0_PULLUDENABLE_1" newline hexmask.long.word 0xEC 4.--15. 1. "RESERVED," newline bitfld.long 0xEC 0.--3. "VOUT1_D0_MUXMODE," "VOUT1_D0_MUXMODE_0,VOUT1_D0_MUXMODE_1,?,?,?,VOUT1_D0_MUXMODE_5,?,?,?,?,?,?,?,?,VOUT1_D0_MUXMODE_14,VOUT1_D0_MUXMODE_15" line.long 0xF0 "CTRL_CORE_PAD_VOUT1_D1," hexmask.long.word 0xF0 20.--31. 1. "RESERVED," newline bitfld.long 0xF0 19. "VOUT1_D1_SLEWCONTROL," "VOUT1_D1_SLEWCONTROL_0,VOUT1_D1_SLEWCONTROL_1" newline bitfld.long 0xF0 18. "VOUT1_D1_INPUTENABLE," "VOUT1_D1_INPUTENABLE_0,VOUT1_D1_INPUTENABLE_1" newline bitfld.long 0xF0 17. "VOUT1_D1_PULLTYPESELECT," "VOUT1_D1_PULLTYPESELECT_0,VOUT1_D1_PULLTYPESELECT_1" newline bitfld.long 0xF0 16. "VOUT1_D1_PULLUDENABLE," "VOUT1_D1_PULLUDENABLE_0,VOUT1_D1_PULLUDENABLE_1" newline hexmask.long.word 0xF0 4.--15. 1. "RESERVED," newline bitfld.long 0xF0 0.--3. "VOUT1_D1_MUXMODE," "VOUT1_D1_MUXMODE_0,VOUT1_D1_MUXMODE_1,?,?,?,VOUT1_D1_MUXMODE_5,?,?,?,?,?,?,?,?,VOUT1_D1_MUXMODE_14,VOUT1_D1_MUXMODE_15" line.long 0xF4 "CTRL_CORE_PAD_VOUT1_D2," hexmask.long.word 0xF4 20.--31. 1. "RESERVED," newline bitfld.long 0xF4 19. "VOUT1_D2_SLEWCONTROL," "VOUT1_D2_SLEWCONTROL_0,VOUT1_D2_SLEWCONTROL_1" newline bitfld.long 0xF4 18. "VOUT1_D2_INPUTENABLE," "VOUT1_D2_INPUTENABLE_0,VOUT1_D2_INPUTENABLE_1" newline bitfld.long 0xF4 17. "VOUT1_D2_PULLTYPESELECT," "VOUT1_D2_PULLTYPESELECT_0,VOUT1_D2_PULLTYPESELECT_1" newline bitfld.long 0xF4 16. "VOUT1_D2_PULLUDENABLE," "VOUT1_D2_PULLUDENABLE_0,VOUT1_D2_PULLUDENABLE_1" newline hexmask.long.word 0xF4 4.--15. 1. "RESERVED," newline bitfld.long 0xF4 0.--3. "VOUT1_D2_MUXMODE," "VOUT1_D2_MUXMODE_0,VOUT1_D2_MUXMODE_1,?,?,VOUT1_D2_MUXMODE_4,VOUT1_D2_MUXMODE_5,?,?,?,?,?,?,?,?,VOUT1_D2_MUXMODE_14,VOUT1_D2_MUXMODE_15" line.long 0xF8 "CTRL_CORE_PAD_VOUT1_D3," hexmask.long.word 0xF8 20.--31. 1. "RESERVED," newline bitfld.long 0xF8 19. "VOUT1_D3_SLEWCONTROL," "VOUT1_D3_SLEWCONTROL_0,VOUT1_D3_SLEWCONTROL_1" newline bitfld.long 0xF8 18. "VOUT1_D3_INPUTENABLE," "VOUT1_D3_INPUTENABLE_0,VOUT1_D3_INPUTENABLE_1" newline bitfld.long 0xF8 17. "VOUT1_D3_PULLTYPESELECT," "VOUT1_D3_PULLTYPESELECT_0,VOUT1_D3_PULLTYPESELECT_1" newline bitfld.long 0xF8 16. "VOUT1_D3_PULLUDENABLE," "VOUT1_D3_PULLUDENABLE_0,VOUT1_D3_PULLUDENABLE_1" newline hexmask.long.word 0xF8 4.--15. 1. "RESERVED," newline bitfld.long 0xF8 0.--3. "VOUT1_D3_MUXMODE," "VOUT1_D3_MUXMODE_0,VOUT1_D3_MUXMODE_1,?,?,VOUT1_D3_MUXMODE_4,VOUT1_D3_MUXMODE_5,?,?,?,?,?,?,?,?,VOUT1_D3_MUXMODE_14,VOUT1_D3_MUXMODE_15" line.long 0xFC "CTRL_CORE_PAD_VOUT1_D4," hexmask.long.word 0xFC 20.--31. 1. "RESERVED," newline bitfld.long 0xFC 19. "VOUT1_D4_SLEWCONTROL," "VOUT1_D4_SLEWCONTROL_0,VOUT1_D4_SLEWCONTROL_1" newline bitfld.long 0xFC 18. "VOUT1_D4_INPUTENABLE," "VOUT1_D4_INPUTENABLE_0,VOUT1_D4_INPUTENABLE_1" newline bitfld.long 0xFC 17. "VOUT1_D4_PULLTYPESELECT," "VOUT1_D4_PULLTYPESELECT_0,VOUT1_D4_PULLTYPESELECT_1" newline bitfld.long 0xFC 16. "VOUT1_D4_PULLUDENABLE," "VOUT1_D4_PULLUDENABLE_0,VOUT1_D4_PULLUDENABLE_1" newline hexmask.long.word 0xFC 4.--15. 1. "RESERVED," newline bitfld.long 0xFC 0.--3. "VOUT1_D4_MUXMODE," "VOUT1_D4_MUXMODE_0,VOUT1_D4_MUXMODE_1,?,?,VOUT1_D4_MUXMODE_4,VOUT1_D4_MUXMODE_5,?,?,?,?,?,?,?,?,VOUT1_D4_MUXMODE_14,VOUT1_D4_MUXMODE_15" line.long 0x100 "CTRL_CORE_PAD_VOUT1_D5," hexmask.long.word 0x100 20.--31. 1. "RESERVED," newline bitfld.long 0x100 19. "VOUT1_D5_SLEWCONTROL," "VOUT1_D5_SLEWCONTROL_0,VOUT1_D5_SLEWCONTROL_1" newline bitfld.long 0x100 18. "VOUT1_D5_INPUTENABLE," "VOUT1_D5_INPUTENABLE_0,VOUT1_D5_INPUTENABLE_1" newline bitfld.long 0x100 17. "VOUT1_D5_PULLTYPESELECT," "VOUT1_D5_PULLTYPESELECT_0,VOUT1_D5_PULLTYPESELECT_1" newline bitfld.long 0x100 16. "VOUT1_D5_PULLUDENABLE," "VOUT1_D5_PULLUDENABLE_0,VOUT1_D5_PULLUDENABLE_1" newline hexmask.long.word 0x100 4.--15. 1. "RESERVED," newline bitfld.long 0x100 0.--3. "VOUT1_D5_MUXMODE," "VOUT1_D5_MUXMODE_0,VOUT1_D5_MUXMODE_1,?,?,VOUT1_D5_MUXMODE_4,VOUT1_D5_MUXMODE_5,?,?,?,VOUT1_D5_MUXMODE_9,?,?,?,?,VOUT1_D5_MUXMODE_14,VOUT1_D5_MUXMODE_15" line.long 0x104 "CTRL_CORE_PAD_VOUT1_D6," hexmask.long.word 0x104 20.--31. 1. "RESERVED," newline bitfld.long 0x104 19. "VOUT1_D6_SLEWCONTROL," "VOUT1_D6_SLEWCONTROL_0,VOUT1_D6_SLEWCONTROL_1" newline bitfld.long 0x104 18. "VOUT1_D6_INPUTENABLE," "VOUT1_D6_INPUTENABLE_0,VOUT1_D6_INPUTENABLE_1" newline bitfld.long 0x104 17. "VOUT1_D6_PULLTYPESELECT," "VOUT1_D6_PULLTYPESELECT_0,VOUT1_D6_PULLTYPESELECT_1" newline bitfld.long 0x104 16. "VOUT1_D6_PULLUDENABLE," "VOUT1_D6_PULLUDENABLE_0,VOUT1_D6_PULLUDENABLE_1" newline hexmask.long.word 0x104 4.--15. 1. "RESERVED," newline bitfld.long 0x104 0.--3. "VOUT1_D6_MUXMODE," "VOUT1_D6_MUXMODE_0,VOUT1_D6_MUXMODE_1,?,?,VOUT1_D6_MUXMODE_4,VOUT1_D6_MUXMODE_5,VOUT1_D6_MUXMODE_6,?,?,VOUT1_D6_MUXMODE_9,?,?,?,?,VOUT1_D6_MUXMODE_14,VOUT1_D6_MUXMODE_15" line.long 0x108 "CTRL_CORE_PAD_VOUT1_D7," hexmask.long.word 0x108 20.--31. 1. "RESERVED," newline bitfld.long 0x108 19. "VOUT1_D7_SLEWCONTROL," "VOUT1_D7_SLEWCONTROL_0,VOUT1_D7_SLEWCONTROL_1" newline bitfld.long 0x108 18. "VOUT1_D7_INPUTENABLE," "VOUT1_D7_INPUTENABLE_0,VOUT1_D7_INPUTENABLE_1" newline bitfld.long 0x108 17. "VOUT1_D7_PULLTYPESELECT," "VOUT1_D7_PULLTYPESELECT_0,VOUT1_D7_PULLTYPESELECT_1" newline bitfld.long 0x108 16. "VOUT1_D7_PULLUDENABLE," "VOUT1_D7_PULLUDENABLE_0,VOUT1_D7_PULLUDENABLE_1" newline hexmask.long.word 0x108 4.--15. 1. "RESERVED," newline bitfld.long 0x108 0.--3. "VOUT1_D7_MUXMODE," "VOUT1_D7_MUXMODE_0,VOUT1_D7_MUXMODE_1,?,VOUT1_D7_MUXMODE_3,VOUT1_D7_MUXMODE_4,?,VOUT1_D7_MUXMODE_6,?,?,VOUT1_D7_MUXMODE_9,?,?,?,?,VOUT1_D7_MUXMODE_14,VOUT1_D7_MUXMODE_15" line.long 0x10C "CTRL_CORE_PAD_VOUT1_D8," hexmask.long.word 0x10C 20.--31. 1. "RESERVED," newline bitfld.long 0x10C 19. "VOUT1_D8_SLEWCONTROL," "VOUT1_D8_SLEWCONTROL_0,VOUT1_D8_SLEWCONTROL_1" newline bitfld.long 0x10C 18. "VOUT1_D8_INPUTENABLE," "VOUT1_D8_INPUTENABLE_0,VOUT1_D8_INPUTENABLE_1" newline bitfld.long 0x10C 17. "VOUT1_D8_PULLTYPESELECT," "VOUT1_D8_PULLTYPESELECT_0,VOUT1_D8_PULLTYPESELECT_1" newline bitfld.long 0x10C 16. "VOUT1_D8_PULLUDENABLE," "VOUT1_D8_PULLUDENABLE_0,VOUT1_D8_PULLUDENABLE_1" newline hexmask.long.word 0x10C 4.--15. 1. "RESERVED," newline bitfld.long 0x10C 0.--3. "VOUT1_D8_MUXMODE," "VOUT1_D8_MUXMODE_0,VOUT1_D8_MUXMODE_1,VOUT1_D8_MUXMODE_2,VOUT1_D8_MUXMODE_3,?,?,VOUT1_D8_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D8_MUXMODE_14,VOUT1_D8_MUXMODE_15" line.long 0x110 "CTRL_CORE_PAD_VOUT1_D9," hexmask.long.word 0x110 20.--31. 1. "RESERVED," newline bitfld.long 0x110 19. "VOUT1_D9_SLEWCONTROL," "VOUT1_D9_SLEWCONTROL_0,VOUT1_D9_SLEWCONTROL_1" newline bitfld.long 0x110 18. "VOUT1_D9_INPUTENABLE," "VOUT1_D9_INPUTENABLE_0,VOUT1_D9_INPUTENABLE_1" newline bitfld.long 0x110 17. "VOUT1_D9_PULLTYPESELECT," "VOUT1_D9_PULLTYPESELECT_0,VOUT1_D9_PULLTYPESELECT_1" newline bitfld.long 0x110 16. "VOUT1_D9_PULLUDENABLE," "VOUT1_D9_PULLUDENABLE_0,VOUT1_D9_PULLUDENABLE_1" newline hexmask.long.word 0x110 4.--15. 1. "RESERVED," newline bitfld.long 0x110 0.--3. "VOUT1_D9_MUXMODE," "VOUT1_D9_MUXMODE_0,VOUT1_D9_MUXMODE_1,VOUT1_D9_MUXMODE_2,VOUT1_D9_MUXMODE_3,?,?,VOUT1_D9_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D9_MUXMODE_14,VOUT1_D9_MUXMODE_15" line.long 0x114 "CTRL_CORE_PAD_VOUT1_D10," hexmask.long.word 0x114 20.--31. 1. "RESERVED," newline bitfld.long 0x114 19. "VOUT1_D10_SLEWCONTROL," "VOUT1_D10_SLEWCONTROL_0,VOUT1_D10_SLEWCONTROL_1" newline bitfld.long 0x114 18. "VOUT1_D10_INPUTENABLE," "VOUT1_D10_INPUTENABLE_0,VOUT1_D10_INPUTENABLE_1" newline bitfld.long 0x114 17. "VOUT1_D10_PULLTYPESELECT," "VOUT1_D10_PULLTYPESELECT_0,VOUT1_D10_PULLTYPESELECT_1" newline bitfld.long 0x114 16. "VOUT1_D10_PULLUDENABLE," "VOUT1_D10_PULLUDENABLE_0,VOUT1_D10_PULLUDENABLE_1" newline hexmask.long.word 0x114 4.--15. 1. "RESERVED," newline bitfld.long 0x114 0.--3. "VOUT1_D10_MUXMODE," "VOUT1_D10_MUXMODE_0,VOUT1_D10_MUXMODE_1,VOUT1_D10_MUXMODE_2,VOUT1_D10_MUXMODE_3,?,?,VOUT1_D10_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D10_MUXMODE_14,VOUT1_D10_MUXMODE_15" line.long 0x118 "CTRL_CORE_PAD_VOUT1_D11," hexmask.long.word 0x118 20.--31. 1. "RESERVED," newline bitfld.long 0x118 19. "VOUT1_D11_SLEWCONTROL," "VOUT1_D11_SLEWCONTROL_0,VOUT1_D11_SLEWCONTROL_1" newline bitfld.long 0x118 18. "VOUT1_D11_INPUTENABLE," "VOUT1_D11_INPUTENABLE_0,VOUT1_D11_INPUTENABLE_1" newline bitfld.long 0x118 17. "VOUT1_D11_PULLTYPESELECT," "VOUT1_D11_PULLTYPESELECT_0,VOUT1_D11_PULLTYPESELECT_1" newline bitfld.long 0x118 16. "VOUT1_D11_PULLUDENABLE," "VOUT1_D11_PULLUDENABLE_0,VOUT1_D11_PULLUDENABLE_1" newline hexmask.long.word 0x118 4.--15. 1. "RESERVED," newline bitfld.long 0x118 0.--3. "VOUT1_D11_MUXMODE," "VOUT1_D11_MUXMODE_0,VOUT1_D11_MUXMODE_1,VOUT1_D11_MUXMODE_2,VOUT1_D11_MUXMODE_3,?,?,VOUT1_D11_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D11_MUXMODE_14,VOUT1_D11_MUXMODE_15" line.long 0x11C "CTRL_CORE_PAD_VOUT1_D12," hexmask.long.word 0x11C 20.--31. 1. "RESERVED," newline bitfld.long 0x11C 19. "VOUT1_D12_SLEWCONTROL," "VOUT1_D12_SLEWCONTROL_0,VOUT1_D12_SLEWCONTROL_1" newline bitfld.long 0x11C 18. "VOUT1_D12_INPUTENABLE," "VOUT1_D12_INPUTENABLE_0,VOUT1_D12_INPUTENABLE_1" newline bitfld.long 0x11C 17. "VOUT1_D12_PULLTYPESELECT," "VOUT1_D12_PULLTYPESELECT_0,VOUT1_D12_PULLTYPESELECT_1" newline bitfld.long 0x11C 16. "VOUT1_D12_PULLUDENABLE," "VOUT1_D12_PULLUDENABLE_0,VOUT1_D12_PULLUDENABLE_1" newline hexmask.long.word 0x11C 4.--15. 1. "RESERVED," newline bitfld.long 0x11C 0.--3. "VOUT1_D12_MUXMODE," "VOUT1_D12_MUXMODE_0,VOUT1_D12_MUXMODE_1,VOUT1_D12_MUXMODE_2,VOUT1_D12_MUXMODE_3,?,?,VOUT1_D12_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D12_MUXMODE_14,VOUT1_D12_MUXMODE_15" line.long 0x120 "CTRL_CORE_PAD_VOUT1_D13," hexmask.long.word 0x120 20.--31. 1. "RESERVED," newline bitfld.long 0x120 19. "VOUT1_D13_SLEWCONTROL," "VOUT1_D13_SLEWCONTROL_0,VOUT1_D13_SLEWCONTROL_1" newline bitfld.long 0x120 18. "VOUT1_D13_INPUTENABLE," "VOUT1_D13_INPUTENABLE_0,VOUT1_D13_INPUTENABLE_1" newline bitfld.long 0x120 17. "VOUT1_D13_PULLTYPESELECT," "VOUT1_D13_PULLTYPESELECT_0,VOUT1_D13_PULLTYPESELECT_1" newline bitfld.long 0x120 16. "VOUT1_D13_PULLUDENABLE," "VOUT1_D13_PULLUDENABLE_0,VOUT1_D13_PULLUDENABLE_1" newline hexmask.long.word 0x120 4.--15. 1. "RESERVED," newline bitfld.long 0x120 0.--3. "VOUT1_D13_MUXMODE," "VOUT1_D13_MUXMODE_0,VOUT1_D13_MUXMODE_1,VOUT1_D13_MUXMODE_2,VOUT1_D13_MUXMODE_3,?,?,VOUT1_D13_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D13_MUXMODE_14,VOUT1_D13_MUXMODE_15" line.long 0x124 "CTRL_CORE_PAD_VOUT1_D14," hexmask.long.word 0x124 20.--31. 1. "RESERVED," newline bitfld.long 0x124 19. "VOUT1_D14_SLEWCONTROL," "VOUT1_D14_SLEWCONTROL_0,VOUT1_D14_SLEWCONTROL_1" newline bitfld.long 0x124 18. "VOUT1_D14_INPUTENABLE," "VOUT1_D14_INPUTENABLE_0,VOUT1_D14_INPUTENABLE_1" newline bitfld.long 0x124 17. "VOUT1_D14_PULLTYPESELECT," "VOUT1_D14_PULLTYPESELECT_0,VOUT1_D14_PULLTYPESELECT_1" newline bitfld.long 0x124 16. "VOUT1_D14_PULLUDENABLE," "VOUT1_D14_PULLUDENABLE_0,VOUT1_D14_PULLUDENABLE_1" newline hexmask.long.word 0x124 4.--15. 1. "RESERVED," newline bitfld.long 0x124 0.--3. "VOUT1_D14_MUXMODE," "VOUT1_D14_MUXMODE_0,VOUT1_D14_MUXMODE_1,VOUT1_D14_MUXMODE_2,VOUT1_D14_MUXMODE_3,?,?,VOUT1_D14_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D14_MUXMODE_14,VOUT1_D14_MUXMODE_15" line.long 0x128 "CTRL_CORE_PAD_VOUT1_D15," hexmask.long.word 0x128 20.--31. 1. "RESERVED," newline bitfld.long 0x128 19. "VOUT1_D15_SLEWCONTROL," "VOUT1_D15_SLEWCONTROL_0,VOUT1_D15_SLEWCONTROL_1" newline bitfld.long 0x128 18. "VOUT1_D15_INPUTENABLE," "VOUT1_D15_INPUTENABLE_0,VOUT1_D15_INPUTENABLE_1" newline bitfld.long 0x128 17. "VOUT1_D15_PULLTYPESELECT," "VOUT1_D15_PULLTYPESELECT_0,VOUT1_D15_PULLTYPESELECT_1" newline bitfld.long 0x128 16. "VOUT1_D15_PULLUDENABLE," "VOUT1_D15_PULLUDENABLE_0,VOUT1_D15_PULLUDENABLE_1" newline hexmask.long.word 0x128 4.--15. 1. "RESERVED," newline bitfld.long 0x128 0.--3. "VOUT1_D15_MUXMODE," "VOUT1_D15_MUXMODE_0,VOUT1_D15_MUXMODE_1,VOUT1_D15_MUXMODE_2,VOUT1_D15_MUXMODE_3,?,?,VOUT1_D15_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D15_MUXMODE_14,VOUT1_D15_MUXMODE_15" line.long 0x12C "CTRL_CORE_PAD_VOUT1_D16," hexmask.long.word 0x12C 20.--31. 1. "RESERVED," newline bitfld.long 0x12C 19. "VOUT1_D16_SLEWCONTROL," "VOUT1_D16_SLEWCONTROL_0,VOUT1_D16_SLEWCONTROL_1" newline bitfld.long 0x12C 18. "VOUT1_D16_INPUTENABLE," "VOUT1_D16_INPUTENABLE_0,VOUT1_D16_INPUTENABLE_1" newline bitfld.long 0x12C 17. "VOUT1_D16_PULLTYPESELECT," "VOUT1_D16_PULLTYPESELECT_0,VOUT1_D16_PULLTYPESELECT_1" newline bitfld.long 0x12C 16. "VOUT1_D16_PULLUDENABLE," "VOUT1_D16_PULLUDENABLE_0,VOUT1_D16_PULLUDENABLE_1" newline hexmask.long.word 0x12C 4.--15. 1. "RESERVED," newline bitfld.long 0x12C 0.--3. "VOUT1_D16_MUXMODE," "VOUT1_D16_MUXMODE_0,VOUT1_D16_MUXMODE_1,VOUT1_D16_MUXMODE_2,VOUT1_D16_MUXMODE_3,VOUT1_D16_MUXMODE_4,VOUT1_D16_MUXMODE_5,VOUT1_D16_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D16_MUXMODE_14,VOUT1_D16_MUXMODE_15" line.long 0x130 "CTRL_CORE_PAD_VOUT1_D17," hexmask.long.word 0x130 20.--31. 1. "RESERVED," newline bitfld.long 0x130 19. "VOUT1_D17_SLEWCONTROL," "VOUT1_D17_SLEWCONTROL_0,VOUT1_D17_SLEWCONTROL_1" newline bitfld.long 0x130 18. "VOUT1_D17_INPUTENABLE," "VOUT1_D17_INPUTENABLE_0,VOUT1_D17_INPUTENABLE_1" newline bitfld.long 0x130 17. "VOUT1_D17_PULLTYPESELECT," "VOUT1_D17_PULLTYPESELECT_0,VOUT1_D17_PULLTYPESELECT_1" newline bitfld.long 0x130 16. "VOUT1_D17_PULLUDENABLE," "VOUT1_D17_PULLUDENABLE_0,VOUT1_D17_PULLUDENABLE_1" newline hexmask.long.word 0x130 4.--15. 1. "RESERVED," newline bitfld.long 0x130 0.--3. "VOUT1_D17_MUXMODE," "VOUT1_D17_MUXMODE_0,?,VOUT1_D17_MUXMODE_2,VOUT1_D17_MUXMODE_3,VOUT1_D17_MUXMODE_4,VOUT1_D17_MUXMODE_5,VOUT1_D17_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D17_MUXMODE_14,VOUT1_D17_MUXMODE_15" line.long 0x134 "CTRL_CORE_PAD_VOUT1_D18," hexmask.long.word 0x134 20.--31. 1. "RESERVED," newline bitfld.long 0x134 19. "VOUT1_D18_SLEWCONTROL," "VOUT1_D18_SLEWCONTROL_0,VOUT1_D18_SLEWCONTROL_1" newline bitfld.long 0x134 18. "VOUT1_D18_INPUTENABLE," "VOUT1_D18_INPUTENABLE_0,VOUT1_D18_INPUTENABLE_1" newline bitfld.long 0x134 17. "VOUT1_D18_PULLTYPESELECT," "VOUT1_D18_PULLTYPESELECT_0,VOUT1_D18_PULLTYPESELECT_1" newline bitfld.long 0x134 16. "VOUT1_D18_PULLUDENABLE," "VOUT1_D18_PULLUDENABLE_0,VOUT1_D18_PULLUDENABLE_1" newline hexmask.long.word 0x134 4.--15. 1. "RESERVED," newline bitfld.long 0x134 0.--3. "VOUT1_D18_MUXMODE," "VOUT1_D18_MUXMODE_0,?,VOUT1_D18_MUXMODE_2,VOUT1_D18_MUXMODE_3,VOUT1_D18_MUXMODE_4,VOUT1_D18_MUXMODE_5,VOUT1_D18_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D18_MUXMODE_14,VOUT1_D18_MUXMODE_15" line.long 0x138 "CTRL_CORE_PAD_VOUT1_D19," hexmask.long.word 0x138 20.--31. 1. "RESERVED," newline bitfld.long 0x138 19. "VOUT1_D19_SLEWCONTROL," "VOUT1_D19_SLEWCONTROL_0,VOUT1_D19_SLEWCONTROL_1" newline bitfld.long 0x138 18. "VOUT1_D19_INPUTENABLE," "VOUT1_D19_INPUTENABLE_0,VOUT1_D19_INPUTENABLE_1" newline bitfld.long 0x138 17. "VOUT1_D19_PULLTYPESELECT," "VOUT1_D19_PULLTYPESELECT_0,VOUT1_D19_PULLTYPESELECT_1" newline bitfld.long 0x138 16. "VOUT1_D19_PULLUDENABLE," "VOUT1_D19_PULLUDENABLE_0,VOUT1_D19_PULLUDENABLE_1" newline hexmask.long.word 0x138 4.--15. 1. "RESERVED," newline bitfld.long 0x138 0.--3. "VOUT1_D19_MUXMODE," "VOUT1_D19_MUXMODE_0,?,VOUT1_D19_MUXMODE_2,VOUT1_D19_MUXMODE_3,VOUT1_D19_MUXMODE_4,VOUT1_D19_MUXMODE_5,VOUT1_D19_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D19_MUXMODE_14,VOUT1_D19_MUXMODE_15" line.long 0x13C "CTRL_CORE_PAD_VOUT1_D20," hexmask.long.word 0x13C 20.--31. 1. "RESERVED," newline bitfld.long 0x13C 19. "VOUT1_D20_SLEWCONTROL," "VOUT1_D20_SLEWCONTROL_0,VOUT1_D20_SLEWCONTROL_1" newline bitfld.long 0x13C 18. "VOUT1_D20_INPUTENABLE," "VOUT1_D20_INPUTENABLE_0,VOUT1_D20_INPUTENABLE_1" newline bitfld.long 0x13C 17. "VOUT1_D20_PULLTYPESELECT," "VOUT1_D20_PULLTYPESELECT_0,VOUT1_D20_PULLTYPESELECT_1" newline bitfld.long 0x13C 16. "VOUT1_D20_PULLUDENABLE," "VOUT1_D20_PULLUDENABLE_0,VOUT1_D20_PULLUDENABLE_1" newline hexmask.long.word 0x13C 4.--15. 1. "RESERVED," newline bitfld.long 0x13C 0.--3. "VOUT1_D20_MUXMODE," "VOUT1_D20_MUXMODE_0,?,VOUT1_D20_MUXMODE_2,VOUT1_D20_MUXMODE_3,VOUT1_D20_MUXMODE_4,VOUT1_D20_MUXMODE_5,VOUT1_D20_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D20_MUXMODE_14,VOUT1_D20_MUXMODE_15" line.long 0x140 "CTRL_CORE_PAD_VOUT1_D21," hexmask.long.word 0x140 20.--31. 1. "RESERVED," newline bitfld.long 0x140 19. "VOUT1_D21_SLEWCONTROL," "VOUT1_D21_SLEWCONTROL_0,VOUT1_D21_SLEWCONTROL_1" newline bitfld.long 0x140 18. "VOUT1_D21_INPUTENABLE," "VOUT1_D21_INPUTENABLE_0,VOUT1_D21_INPUTENABLE_1" newline bitfld.long 0x140 17. "VOUT1_D21_PULLTYPESELECT," "VOUT1_D21_PULLTYPESELECT_0,VOUT1_D21_PULLTYPESELECT_1" newline bitfld.long 0x140 16. "VOUT1_D21_PULLUDENABLE," "VOUT1_D21_PULLUDENABLE_0,VOUT1_D21_PULLUDENABLE_1" newline hexmask.long.word 0x140 4.--15. 1. "RESERVED," newline bitfld.long 0x140 0.--3. "VOUT1_D21_MUXMODE," "VOUT1_D21_MUXMODE_0,?,VOUT1_D21_MUXMODE_2,VOUT1_D21_MUXMODE_3,VOUT1_D21_MUXMODE_4,VOUT1_D21_MUXMODE_5,VOUT1_D21_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D21_MUXMODE_14,VOUT1_D21_MUXMODE_15" line.long 0x144 "CTRL_CORE_PAD_VOUT1_D22," hexmask.long.word 0x144 20.--31. 1. "RESERVED," newline bitfld.long 0x144 19. "VOUT1_D22_SLEWCONTROL," "VOUT1_D22_SLEWCONTROL_0,VOUT1_D22_SLEWCONTROL_1" newline bitfld.long 0x144 18. "VOUT1_D22_INPUTENABLE," "VOUT1_D22_INPUTENABLE_0,VOUT1_D22_INPUTENABLE_1" newline bitfld.long 0x144 17. "VOUT1_D22_PULLTYPESELECT," "VOUT1_D22_PULLTYPESELECT_0,VOUT1_D22_PULLTYPESELECT_1" newline bitfld.long 0x144 16. "VOUT1_D22_PULLUDENABLE," "VOUT1_D22_PULLUDENABLE_0,VOUT1_D22_PULLUDENABLE_1" newline hexmask.long.word 0x144 4.--15. 1. "RESERVED," newline bitfld.long 0x144 0.--3. "VOUT1_D22_MUXMODE," "VOUT1_D22_MUXMODE_0,?,VOUT1_D22_MUXMODE_2,VOUT1_D22_MUXMODE_3,VOUT1_D22_MUXMODE_4,VOUT1_D22_MUXMODE_5,VOUT1_D22_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D22_MUXMODE_14,VOUT1_D22_MUXMODE_15" line.long 0x148 "CTRL_CORE_PAD_VOUT1_D23," hexmask.long.word 0x148 20.--31. 1. "RESERVED," newline bitfld.long 0x148 19. "VOUT1_D23_SLEWCONTROL," "VOUT1_D23_SLEWCONTROL_0,VOUT1_D23_SLEWCONTROL_1" newline bitfld.long 0x148 18. "VOUT1_D23_INPUTENABLE," "VOUT1_D23_INPUTENABLE_0,VOUT1_D23_INPUTENABLE_1" newline bitfld.long 0x148 17. "VOUT1_D23_PULLTYPESELECT," "VOUT1_D23_PULLTYPESELECT_0,VOUT1_D23_PULLTYPESELECT_1" newline bitfld.long 0x148 16. "VOUT1_D23_PULLUDENABLE," "VOUT1_D23_PULLUDENABLE_0,VOUT1_D23_PULLUDENABLE_1" newline hexmask.long.word 0x148 4.--15. 1. "RESERVED," newline bitfld.long 0x148 0.--3. "VOUT1_D23_MUXMODE," "VOUT1_D23_MUXMODE_0,?,VOUT1_D23_MUXMODE_2,VOUT1_D23_MUXMODE_3,VOUT1_D23_MUXMODE_4,VOUT1_D23_MUXMODE_5,VOUT1_D23_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D23_MUXMODE_14,VOUT1_D23_MUXMODE_15" line.long 0x14C "CTRL_CORE_PAD_DCAN2_TX,SR1.0 Only" hexmask.long.word 0x14C 20.--31. 1. "RESERVED," newline bitfld.long 0x14C 19. "DCAN2_TX_SLEWCONTROL," "DCAN2_TX_SLEWCONTROL_0,DCAN2_TX_SLEWCONTROL_1" newline bitfld.long 0x14C 18. "DCAN2_TX_INPUTENABLE," "DCAN2_TX_INPUTENABLE_0,DCAN2_TX_INPUTENABLE_1" newline bitfld.long 0x14C 17. "DCAN2_TX_PULLTYPESELECT," "DCAN2_TX_PULLTYPESELECT_0,DCAN2_TX_PULLTYPESELECT_1" newline bitfld.long 0x14C 16. "DCAN2_TX_PULLUDENABLE," "DCAN2_TX_PULLUDENABLE_0,DCAN2_TX_PULLUDENABLE_1" newline hexmask.long.word 0x14C 4.--15. 1. "RESERVED," newline bitfld.long 0x14C 0.--3. "DCAN2_TX_MUXMODE," "DCAN2_TX_MUXMODE_0,DCAN2_TX_MUXMODE_1,DCAN2_TX_MUXMODE_2,DCAN2_TX_MUXMODE_3,DCAN2_TX_MUXMODE_4,DCAN2_TX_MUXMODE_5,DCAN2_TX_MUXMODE_6,DCAN2_TX_MUXMODE_7,DCAN2_TX_MUXMODE_8,?,?,?,?,?,DCAN2_TX_MUXMODE_14,DCAN2_TX_MUXMODE_15" group.long 0x154C++0x07 line.long 0x00 "CTRL_CORE_PAD_MCAN_TX,SR2.0 Only" hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline bitfld.long 0x00 19. "MCAN_TX_SLEWCONTROL," "MCAN_TX_SLEWCONTROL_0,MCAN_TX_SLEWCONTROL_1" newline bitfld.long 0x00 18. "MCAN_TX_INPUTENABLE," "MCAN_TX_INPUTENABLE_0,MCAN_TX_INPUTENABLE_1" newline bitfld.long 0x00 17. "MCAN_TX_PULLTYPESELECT," "MCAN_TX_PULLTYPESELECT_0,MCAN_TX_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "MCAN_TX_PULLUDENABLE," "MCAN_TX_PULLUDENABLE_0,MCAN_TX_PULLUDENABLE_1" newline hexmask.long.word 0x00 4.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "MCAN_TX_MUXMODE," "MCAN_TX_MUXMODE_0,MCAN_TX_MUXMODE_1,MCAN_TX_MUXMODE_2,MCAN_TX_MUXMODE_3,MCAN_TX_MUXMODE_4,MCAN_TX_MUXMODE_5,MCAN_TX_MUXMODE_6,MCAN_TX_MUXMODE_7,MCAN_TX_MUXMODE_8,?,?,?,?,?,MCAN_TX_MUXMODE_14,MCAN_TX_MUXMODE_15" line.long 0x04 "CTRL_CORE_PAD_DCAN2_RX,SR1.0 Only" hexmask.long.word 0x04 20.--31. 1. "RESERVED," newline bitfld.long 0x04 19. "DCAN2_RX_SLEWCONTROL," "DCAN2_RX_SLEWCONTROL_0,DCAN2_RX_SLEWCONTROL_1" newline bitfld.long 0x04 18. "DCAN2_RX_INPUTENABLE," "DCAN2_RX_INPUTENABLE_0,DCAN2_RX_INPUTENABLE_1" newline bitfld.long 0x04 17. "DCAN2_RX_PULLTYPESELECT," "DCAN2_RX_PULLTYPESELECT_0,DCAN2_RX_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "DCAN2_RX_PULLUDENABLE," "DCAN2_RX_PULLUDENABLE_0,DCAN2_RX_PULLUDENABLE_1" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 0.--3. "DCAN2_RX_MUXMODE," "DCAN2_RX_MUXMODE_0,DCAN2_RX_MUXMODE_1,DCAN2_RX_MUXMODE_2,DCAN2_RX_MUXMODE_3,DCAN2_RX_MUXMODE_4,DCAN2_RX_MUXMODE_5,?,DCAN2_RX_MUXMODE_7,?,?,?,?,?,?,DCAN2_RX_MUXMODE_14,DCAN2_RX_MUXMODE_15" group.long 0x1550++0x67 line.long 0x00 "CTRL_CORE_PAD_MCAN_RX,SR2.0 Only" hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline bitfld.long 0x00 19. "MCAN_RX_SLEWCONTROL," "MCAN_RX_SLEWCONTROL_0,MCAN_RX_SLEWCONTROL_1" newline bitfld.long 0x00 18. "MCAN_RX_INPUTENABLE," "MCAN_RX_INPUTENABLE_0,MCAN_RX_INPUTENABLE_1" newline bitfld.long 0x00 17. "MCAN_RX_PULLTYPESELECT," "MCAN_RX_PULLTYPESELECT_0,MCAN_RX_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "MCAN_RX_PULLUDENABLE," "MCAN_RX_PULLUDENABLE_0,MCAN_RX_PULLUDENABLE_1" newline hexmask.long.word 0x00 4.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "MCAN_RX_MUXMODE," "MCAN_RX_MUXMODE_0,MCAN_RX_MUXMODE_1,MCAN_RX_MUXMODE_2,MCAN_RX_MUXMODE_3,MCAN_RX_MUXMODE_4,MCAN_RX_MUXMODE_5,?,MCAN_RX_MUXMODE_7,?,?,?,?,?,?,MCAN_RX_MUXMODE_14,MCAN_RX_MUXMODE_15" line.long 0x04 "CTRL_CORE_PAD_MDIO_MCLK," hexmask.long.word 0x04 20.--31. 1. "RESERVED," newline bitfld.long 0x04 19. "MDIO_MCLK_SLEWCONTROL," "MDIO_MCLK_SLEWCONTROL_0,MDIO_MCLK_SLEWCONTROL_1" newline bitfld.long 0x04 18. "MDIO_MCLK_INPUTENABLE," "MDIO_MCLK_INPUTENABLE_0,MDIO_MCLK_INPUTENABLE_1" newline bitfld.long 0x04 17. "MDIO_MCLK_PULLTYPESELECT," "MDIO_MCLK_PULLTYPESELECT_0,MDIO_MCLK_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "MDIO_MCLK_PULLUDENABLE," "MDIO_MCLK_PULLUDENABLE_0,MDIO_MCLK_PULLUDENABLE_1" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 0.--3. "MDIO_MCLK_MUXMODE," "MDIO_MCLK_MUXMODE_0,?,?,?,MDIO_MCLK_MUXMODE_4,?,?,?,?,?,?,?,?,?,MDIO_MCLK_MUXMODE_14,MDIO_MCLK_MUXMODE_15" line.long 0x08 "CTRL_CORE_PAD_MDIO_D," hexmask.long.word 0x08 20.--31. 1. "RESERVED," newline bitfld.long 0x08 19. "MDIO_D_SLEWCONTROL," "MDIO_D_SLEWCONTROL_0,MDIO_D_SLEWCONTROL_1" newline bitfld.long 0x08 18. "MDIO_D_INPUTENABLE," "MDIO_D_INPUTENABLE_0,MDIO_D_INPUTENABLE_1" newline bitfld.long 0x08 17. "MDIO_D_PULLTYPESELECT," "MDIO_D_PULLTYPESELECT_0,MDIO_D_PULLTYPESELECT_1" newline bitfld.long 0x08 16. "MDIO_D_PULLUDENABLE," "MDIO_D_PULLUDENABLE_0,MDIO_D_PULLUDENABLE_1" newline hexmask.long.word 0x08 4.--15. 1. "RESERVED," newline bitfld.long 0x08 0.--3. "MDIO_D_MUXMODE," "MDIO_D_MUXMODE_0,?,?,?,MDIO_D_MUXMODE_4,MDIO_D_MUXMODE_5,?,?,?,?,?,?,?,?,MDIO_D_MUXMODE_14,MDIO_D_MUXMODE_15" line.long 0x0C "CTRL_CORE_PAD_RGMII0_TXC," hexmask.long.word 0x0C 20.--31. 1. "RESERVED," newline bitfld.long 0x0C 19. "RGMII0_TXC_SLEWCONTROL," "RGMII0_TXC_SLEWCONTROL_0,RGMII0_TXC_SLEWCONTROL_1" newline bitfld.long 0x0C 18. "RGMII0_TXC_INPUTENABLE," "RGMII0_TXC_INPUTENABLE_0,RGMII0_TXC_INPUTENABLE_1" newline bitfld.long 0x0C 17. "RGMII0_TXC_PULLTYPESELECT," "RGMII0_TXC_PULLTYPESELECT_0,RGMII0_TXC_PULLTYPESELECT_1" newline bitfld.long 0x0C 16. "RGMII0_TXC_PULLUDENABLE," "RGMII0_TXC_PULLUDENABLE_0,RGMII0_TXC_PULLUDENABLE_1" newline hexmask.long.word 0x0C 4.--15. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "RGMII0_TXC_MUXMODE," "RGMII0_TXC_MUXMODE_0,?,?,RGMII0_TXC_MUXMODE_3,RGMII0_TXC_MUXMODE_4,RGMII0_TXC_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_TXC_MUXMODE_14,RGMII0_TXC_MUXMODE_15" line.long 0x10 "CTRL_CORE_PAD_RGMII0_TXCTL," hexmask.long.word 0x10 20.--31. 1. "RESERVED," newline bitfld.long 0x10 19. "RGMII0_TXCTL_SLEWCONTROL," "RGMII0_TXCTL_SLEWCONTROL_0,RGMII0_TXCTL_SLEWCONTROL_1" newline bitfld.long 0x10 18. "RGMII0_TXCTL_INPUTENABLE," "RGMII0_TXCTL_INPUTENABLE_0,RGMII0_TXCTL_INPUTENABLE_1" newline bitfld.long 0x10 17. "RGMII0_TXCTL_PULLTYPESELECT," "RGMII0_TXCTL_PULLTYPESELECT_0,RGMII0_TXCTL_PULLTYPESELECT_1" newline bitfld.long 0x10 16. "RGMII0_TXCTL_PULLUDENABLE," "RGMII0_TXCTL_PULLUDENABLE_0,RGMII0_TXCTL_PULLUDENABLE_1" newline hexmask.long.word 0x10 4.--15. 1. "RESERVED," newline bitfld.long 0x10 0.--3. "RGMII0_TXCTL_MUXMODE," "RGMII0_TXCTL_MUXMODE_0,?,?,RGMII0_TXCTL_MUXMODE_3,RGMII0_TXCTL_MUXMODE_4,RGMII0_TXCTL_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_TXCTL_MUXMODE_14,RGMII0_TXCTL_MUXMODE_15" line.long 0x14 "CTRL_CORE_PAD_RGMII0_TXD3," hexmask.long.word 0x14 20.--31. 1. "RESERVED," newline bitfld.long 0x14 19. "RGMII0_TXD3_SLEWCONTROL," "RGMII0_TXD3_SLEWCONTROL_0,RGMII0_TXD3_SLEWCONTROL_1" newline bitfld.long 0x14 18. "RGMII0_TXD3_INPUTENABLE," "RGMII0_TXD3_INPUTENABLE_0,RGMII0_TXD3_INPUTENABLE_1" newline bitfld.long 0x14 17. "RGMII0_TXD3_PULLTYPESELECT," "RGMII0_TXD3_PULLTYPESELECT_0,RGMII0_TXD3_PULLTYPESELECT_1" newline bitfld.long 0x14 16. "RGMII0_TXD3_PULLUDENABLE," "RGMII0_TXD3_PULLUDENABLE_0,RGMII0_TXD3_PULLUDENABLE_1" newline hexmask.long.word 0x14 4.--15. 1. "RESERVED," newline bitfld.long 0x14 0.--3. "RGMII0_TXD3_MUXMODE," "RGMII0_TXD3_MUXMODE_0,?,?,?,?,RGMII0_TXD3_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_TXD3_MUXMODE_14,RGMII0_TXD3_MUXMODE_15" line.long 0x18 "CTRL_CORE_PAD_RGMII0_TXD2," hexmask.long.word 0x18 20.--31. 1. "RESERVED," newline bitfld.long 0x18 19. "RGMII0_TXD2_SLEWCONTROL," "RGMII0_TXD2_SLEWCONTROL_0,RGMII0_TXD2_SLEWCONTROL_1" newline bitfld.long 0x18 18. "RGMII0_TXD2_INPUTENABLE," "RGMII0_TXD2_INPUTENABLE_0,RGMII0_TXD2_INPUTENABLE_1" newline bitfld.long 0x18 17. "RGMII0_TXD2_PULLTYPESELECT," "RGMII0_TXD2_PULLTYPESELECT_0,RGMII0_TXD2_PULLTYPESELECT_1" newline bitfld.long 0x18 16. "RGMII0_TXD2_PULLUDENABLE," "RGMII0_TXD2_PULLUDENABLE_0,RGMII0_TXD2_PULLUDENABLE_1" newline hexmask.long.word 0x18 4.--15. 1. "RESERVED," newline bitfld.long 0x18 0.--3. "RGMII0_TXD2_MUXMODE," "RGMII0_TXD2_MUXMODE_0,?,?,RGMII0_TXD2_MUXMODE_3,?,RGMII0_TXD2_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_TXD2_MUXMODE_14,RGMII0_TXD2_MUXMODE_15" line.long 0x1C "CTRL_CORE_PAD_RGMII0_TXD1," hexmask.long.word 0x1C 20.--31. 1. "RESERVED," newline bitfld.long 0x1C 19. "RGMII0_TXD1_SLEWCONTROL," "RGMII0_TXD1_SLEWCONTROL_0,RGMII0_TXD1_SLEWCONTROL_1" newline bitfld.long 0x1C 18. "RGMII0_TXD1_INPUTENABLE," "RGMII0_TXD1_INPUTENABLE_0,RGMII0_TXD1_INPUTENABLE_1" newline bitfld.long 0x1C 17. "RGMII0_TXD1_PULLTYPESELECT," "RGMII0_TXD1_PULLTYPESELECT_0,RGMII0_TXD1_PULLTYPESELECT_1" newline bitfld.long 0x1C 16. "RGMII0_TXD1_PULLUDENABLE," "RGMII0_TXD1_PULLUDENABLE_0,RGMII0_TXD1_PULLUDENABLE_1" newline hexmask.long.word 0x1C 4.--15. 1. "RESERVED," newline bitfld.long 0x1C 0.--3. "RGMII0_TXD1_MUXMODE," "RGMII0_TXD1_MUXMODE_0,?,?,?,?,RGMII0_TXD1_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_TXD1_MUXMODE_14,RGMII0_TXD1_MUXMODE_15" line.long 0x20 "CTRL_CORE_PAD_RGMII0_TXD0," hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline bitfld.long 0x20 19. "RGMII0_TXD0_SLEWCONTROL," "RGMII0_TXD0_SLEWCONTROL_0,RGMII0_TXD0_SLEWCONTROL_1" newline bitfld.long 0x20 18. "RGMII0_TXD0_INPUTENABLE," "RGMII0_TXD0_INPUTENABLE_0,RGMII0_TXD0_INPUTENABLE_1" newline bitfld.long 0x20 17. "RGMII0_TXD0_PULLTYPESELECT," "RGMII0_TXD0_PULLTYPESELECT_0,RGMII0_TXD0_PULLTYPESELECT_1" newline bitfld.long 0x20 16. "RGMII0_TXD0_PULLUDENABLE," "RGMII0_TXD0_PULLUDENABLE_0,RGMII0_TXD0_PULLUDENABLE_1" newline hexmask.long.word 0x20 4.--15. 1. "RESERVED," newline bitfld.long 0x20 0.--3. "RGMII0_TXD0_MUXMODE," "RGMII0_TXD0_MUXMODE_0,?,?,?,?,RGMII0_TXD0_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_TXD0_MUXMODE_14,RGMII0_TXD0_MUXMODE_15" line.long 0x24 "CTRL_CORE_PAD_RGMII0_RXC," hexmask.long.word 0x24 20.--31. 1. "RESERVED," newline bitfld.long 0x24 19. "RGMII0_RXC_SLEWCONTROL," "RGMII0_RXC_SLEWCONTROL_0,RGMII0_RXC_SLEWCONTROL_1" newline bitfld.long 0x24 18. "RGMII0_RXC_INPUTENABLE," "RGMII0_RXC_INPUTENABLE_0,RGMII0_RXC_INPUTENABLE_1" newline bitfld.long 0x24 17. "RGMII0_RXC_PULLTYPESELECT," "RGMII0_RXC_PULLTYPESELECT_0,RGMII0_RXC_PULLTYPESELECT_1" newline bitfld.long 0x24 16. "RGMII0_RXC_PULLUDENABLE," "RGMII0_RXC_PULLUDENABLE_0,RGMII0_RXC_PULLUDENABLE_1" newline hexmask.long.word 0x24 4.--15. 1. "RESERVED," newline bitfld.long 0x24 0.--3. "RGMII0_RXC_MUXMODE," "RGMII0_RXC_MUXMODE_0,?,?,RGMII0_RXC_MUXMODE_3,?,RGMII0_RXC_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_RXC_MUXMODE_14,RGMII0_RXC_MUXMODE_15" line.long 0x28 "CTRL_CORE_PAD_RGMII0_RXCTL," hexmask.long.word 0x28 20.--31. 1. "RESERVED," newline bitfld.long 0x28 19. "RGMII0_RXCTL_SLEWCONTROL," "RGMII0_RXCTL_SLEWCONTROL_0,RGMII0_RXCTL_SLEWCONTROL_1" newline bitfld.long 0x28 18. "RGMII0_RXCTL_INPUTENABLE," "RGMII0_RXCTL_INPUTENABLE_0,RGMII0_RXCTL_INPUTENABLE_1" newline bitfld.long 0x28 17. "RGMII0_RXCTL_PULLTYPESELECT," "RGMII0_RXCTL_PULLTYPESELECT_0,RGMII0_RXCTL_PULLTYPESELECT_1" newline bitfld.long 0x28 16. "RGMII0_RXCTL_PULLUDENABLE," "RGMII0_RXCTL_PULLUDENABLE_0,RGMII0_RXCTL_PULLUDENABLE_1" newline hexmask.long.word 0x28 4.--15. 1. "RESERVED," newline bitfld.long 0x28 0.--3. "RGMII0_RXCTL_MUXMODE," "RGMII0_RXCTL_MUXMODE_0,?,?,RGMII0_RXCTL_MUXMODE_3,?,RGMII0_RXCTL_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_RXCTL_MUXMODE_14,RGMII0_RXCTL_MUXMODE_15" line.long 0x2C "CTRL_CORE_PAD_RGMII0_RXD3," hexmask.long.word 0x2C 20.--31. 1. "RESERVED," newline bitfld.long 0x2C 19. "RGMII0_RXD3_SLEWCONTROL," "RGMII0_RXD3_SLEWCONTROL_0,RGMII0_RXD3_SLEWCONTROL_1" newline bitfld.long 0x2C 18. "RGMII0_RXD3_INPUTENABLE," "RGMII0_RXD3_INPUTENABLE_0,RGMII0_RXD3_INPUTENABLE_1" newline bitfld.long 0x2C 17. "RGMII0_RXD3_PULLTYPESELECT," "RGMII0_RXD3_PULLTYPESELECT_0,RGMII0_RXD3_PULLTYPESELECT_1" newline bitfld.long 0x2C 16. "RGMII0_RXD3_PULLUDENABLE," "RGMII0_RXD3_PULLUDENABLE_0,RGMII0_RXD3_PULLUDENABLE_1" newline hexmask.long.word 0x2C 4.--15. 1. "RESERVED," newline bitfld.long 0x2C 0.--3. "RGMII0_RXD3_MUXMODE," "RGMII0_RXD3_MUXMODE_0,?,?,?,?,RGMII0_RXD3_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_RXD3_MUXMODE_14,RGMII0_RXD3_MUXMODE_15" line.long 0x30 "CTRL_CORE_PAD_RGMII0_RXD2," hexmask.long.word 0x30 20.--31. 1. "RESERVED," newline bitfld.long 0x30 19. "RGMII0_RXD2_SLEWCONTROL," "RGMII0_RXD2_SLEWCONTROL_0,RGMII0_RXD2_SLEWCONTROL_1" newline bitfld.long 0x30 18. "RGMII0_RXD2_INPUTENABLE," "RGMII0_RXD2_INPUTENABLE_0,RGMII0_RXD2_INPUTENABLE_1" newline bitfld.long 0x30 17. "RGMII0_RXD2_PULLTYPESELECT," "RGMII0_RXD2_PULLTYPESELECT_0,RGMII0_RXD2_PULLTYPESELECT_1" newline bitfld.long 0x30 16. "RGMII0_RXD2_PULLUDENABLE," "RGMII0_RXD2_PULLUDENABLE_0,RGMII0_RXD2_PULLUDENABLE_1" newline hexmask.long.word 0x30 4.--15. 1. "RESERVED," newline bitfld.long 0x30 0.--3. "RGMII0_RXD2_MUXMODE," "RGMII0_RXD2_MUXMODE_0,?,?,?,?,RGMII0_RXD2_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_RXD2_MUXMODE_14,RGMII0_RXD2_MUXMODE_15" line.long 0x34 "CTRL_CORE_PAD_RGMII0_RXD1," hexmask.long.word 0x34 20.--31. 1. "RESERVED," newline bitfld.long 0x34 19. "RGMII0_RXD1_SLEWCONTROL," "RGMII0_RXD1_SLEWCONTROL_0,RGMII0_RXD1_SLEWCONTROL_1" newline bitfld.long 0x34 18. "RGMII0_RXD1_INPUTENABLE," "RGMII0_RXD1_INPUTENABLE_0,RGMII0_RXD1_INPUTENABLE_1" newline bitfld.long 0x34 17. "RGMII0_RXD1_PULLTYPESELECT," "RGMII0_RXD1_PULLTYPESELECT_0,RGMII0_RXD1_PULLTYPESELECT_1" newline bitfld.long 0x34 16. "RGMII0_RXD1_PULLUDENABLE," "RGMII0_RXD1_PULLUDENABLE_0,RGMII0_RXD1_PULLUDENABLE_1" newline hexmask.long.word 0x34 4.--15. 1. "RESERVED," newline bitfld.long 0x34 0.--3. "RGMII0_RXD1_MUXMODE," "RGMII0_RXD1_MUXMODE_0,?,?,?,?,RGMII0_RXD1_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_RXD1_MUXMODE_14,RGMII0_RXD1_MUXMODE_15" line.long 0x38 "CTRL_CORE_PAD_RGMII0_RXD0," hexmask.long.word 0x38 20.--31. 1. "RESERVED," newline bitfld.long 0x38 19. "RGMII0_RXD0_SLEWCONTROL," "RGMII0_RXD0_SLEWCONTROL_0,RGMII0_RXD0_SLEWCONTROL_1" newline bitfld.long 0x38 18. "RGMII0_RXD0_INPUTENABLE," "RGMII0_RXD0_INPUTENABLE_0,RGMII0_RXD0_INPUTENABLE_1" newline bitfld.long 0x38 17. "RGMII0_RXD0_PULLTYPESELECT," "RGMII0_RXD0_PULLTYPESELECT_0,RGMII0_RXD0_PULLTYPESELECT_1" newline bitfld.long 0x38 16. "RGMII0_RXD0_PULLUDENABLE," "RGMII0_RXD0_PULLUDENABLE_0,RGMII0_RXD0_PULLUDENABLE_1" newline hexmask.long.word 0x38 4.--15. 1. "RESERVED," newline bitfld.long 0x38 0.--3. "RGMII0_RXD0_MUXMODE," "RGMII0_RXD0_MUXMODE_0,?,?,?,?,RGMII0_RXD0_MUXMODE_5,?,?,?,?,?,?,?,?,RGMII0_RXD0_MUXMODE_14,RGMII0_RXD0_MUXMODE_15" line.long 0x3C "CTRL_CORE_PAD_XREF_CLK0," hexmask.long.word 0x3C 20.--31. 1. "RESERVED," newline bitfld.long 0x3C 19. "XREF_CLK0_SLEWCONTROL," "XREF_CLK0_SLEWCONTROL_0,XREF_CLK0_SLEWCONTROL_1" newline bitfld.long 0x3C 18. "XREF_CLK0_INPUTENABLE," "XREF_CLK0_INPUTENABLE_0,XREF_CLK0_INPUTENABLE_1" newline bitfld.long 0x3C 17. "XREF_CLK0_PULLTYPESELECT," "XREF_CLK0_PULLTYPESELECT_0,XREF_CLK0_PULLTYPESELECT_1" newline bitfld.long 0x3C 16. "XREF_CLK0_PULLUDENABLE," "XREF_CLK0_PULLUDENABLE_0,XREF_CLK0_PULLUDENABLE_1" newline hexmask.long.word 0x3C 4.--15. 1. "RESERVED," newline bitfld.long 0x3C 0.--3. "XREF_CLK0_MUXMODE," "XREF_CLK0_MUXMODE_0,XREF_CLK0_MUXMODE_1,?,?,XREF_CLK0_MUXMODE_4,XREF_CLK0_MUXMODE_5,XREF_CLK0_MUXMODE_6,XREF_CLK0_MUXMODE_7,?,?,?,?,?,?,XREF_CLK0_MUXMODE_14,XREF_CLK0_MUXMODE_15" line.long 0x40 "CTRL_CORE_PAD_SPI1_SCLK," hexmask.long.word 0x40 20.--31. 1. "RESERVED," newline bitfld.long 0x40 19. "SPI1_SCLK_SLEWCONTROL," "SPI1_SCLK_SLEWCONTROL_0,SPI1_SCLK_SLEWCONTROL_1" newline bitfld.long 0x40 18. "SPI1_SCLK_INPUTENABLE," "SPI1_SCLK_INPUTENABLE_0,SPI1_SCLK_INPUTENABLE_1" newline bitfld.long 0x40 17. "SPI1_SCLK_PULLTYPESELECT," "SPI1_SCLK_PULLTYPESELECT_0,SPI1_SCLK_PULLTYPESELECT_1" newline bitfld.long 0x40 16. "SPI1_SCLK_PULLUDENABLE," "SPI1_SCLK_PULLUDENABLE_0,SPI1_SCLK_PULLUDENABLE_1" newline hexmask.long.word 0x40 4.--15. 1. "RESERVED," newline bitfld.long 0x40 0.--3. "SPI1_SCLK_MUXMODE," "SPI1_SCLK_MUXMODE_0,SPI1_SCLK_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,SPI1_SCLK_MUXMODE_14,SPI1_SCLK_MUXMODE_15" line.long 0x44 "CTRL_CORE_PAD_SPI1_D1," hexmask.long.word 0x44 20.--31. 1. "RESERVED," newline bitfld.long 0x44 19. "SPI1_D1_SLEWCONTROL," "SPI1_D1_SLEWCONTROL_0,SPI1_D1_SLEWCONTROL_1" newline bitfld.long 0x44 18. "SPI1_D1_INPUTENABLE," "SPI1_D1_INPUTENABLE_0,SPI1_D1_INPUTENABLE_1" newline bitfld.long 0x44 17. "SPI1_D1_PULLTYPESELECT," "SPI1_D1_PULLTYPESELECT_0,SPI1_D1_PULLTYPESELECT_1" newline bitfld.long 0x44 16. "SPI1_D1_PULLUDENABLE," "SPI1_D1_PULLUDENABLE_0,SPI1_D1_PULLUDENABLE_1" newline hexmask.long.word 0x44 4.--15. 1. "RESERVED," newline bitfld.long 0x44 0.--3. "SPI1_D1_MUXMODE," "SPI1_D1_MUXMODE_0,SPI1_D1_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,SPI1_D1_MUXMODE_14,SPI1_D1_MUXMODE_15" line.long 0x48 "CTRL_CORE_PAD_SPI1_D0," hexmask.long.word 0x48 20.--31. 1. "RESERVED," newline bitfld.long 0x48 19. "SPI1_D0_SLEWCONTROL," "SPI1_D0_SLEWCONTROL_0,SPI1_D0_SLEWCONTROL_1" newline bitfld.long 0x48 18. "SPI1_D0_INPUTENABLE," "SPI1_D0_INPUTENABLE_0,SPI1_D0_INPUTENABLE_1" newline bitfld.long 0x48 17. "SPI1_D0_PULLTYPESELECT," "SPI1_D0_PULLTYPESELECT_0,SPI1_D0_PULLTYPESELECT_1" newline bitfld.long 0x48 16. "SPI1_D0_PULLUDENABLE," "SPI1_D0_PULLUDENABLE_0,SPI1_D0_PULLUDENABLE_1" newline hexmask.long.word 0x48 4.--15. 1. "RESERVED," newline bitfld.long 0x48 0.--3. "SPI1_D0_MUXMODE," "SPI1_D0_MUXMODE_0,SPI1_D0_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,SPI1_D0_MUXMODE_14,SPI1_D0_MUXMODE_15" line.long 0x4C "CTRL_CORE_PAD_SPI1_CS0," hexmask.long.word 0x4C 20.--31. 1. "RESERVED," newline bitfld.long 0x4C 19. "SPI1_CS0_SLEWCONTROL," "SPI1_CS0_SLEWCONTROL_0,SPI1_CS0_SLEWCONTROL_1" newline bitfld.long 0x4C 18. "SPI1_CS0_INPUTENABLE," "SPI1_CS0_INPUTENABLE_0,SPI1_CS0_INPUTENABLE_1" newline bitfld.long 0x4C 17. "SPI1_CS0_PULLTYPESELECT," "SPI1_CS0_PULLTYPESELECT_0,SPI1_CS0_PULLTYPESELECT_1" newline bitfld.long 0x4C 16. "SPI1_CS0_PULLUDENABLE," "SPI1_CS0_PULLUDENABLE_0,SPI1_CS0_PULLUDENABLE_1" newline hexmask.long.word 0x4C 4.--15. 1. "RESERVED," newline bitfld.long 0x4C 0.--3. "SPI1_CS0_MUXMODE," "SPI1_CS0_MUXMODE_0,SPI1_CS0_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,SPI1_CS0_MUXMODE_14,SPI1_CS0_MUXMODE_15" line.long 0x50 "CTRL_CORE_PAD_SPI1_CS1," hexmask.long.word 0x50 20.--31. 1. "RESERVED," newline bitfld.long 0x50 19. "SPI1_CS1_SLEWCONTROL," "SPI1_CS1_SLEWCONTROL_0,SPI1_CS1_SLEWCONTROL_1" newline bitfld.long 0x50 18. "SPI1_CS1_INPUTENABLE," "SPI1_CS1_INPUTENABLE_0,SPI1_CS1_INPUTENABLE_1" newline bitfld.long 0x50 17. "SPI1_CS1_PULLTYPESELECT," "SPI1_CS1_PULLTYPESELECT_0,SPI1_CS1_PULLTYPESELECT_1" newline bitfld.long 0x50 16. "SPI1_CS1_PULLUDENABLE," "SPI1_CS1_PULLUDENABLE_0,SPI1_CS1_PULLUDENABLE_1" newline hexmask.long.word 0x50 4.--15. 1. "RESERVED," newline bitfld.long 0x50 0.--3. "SPI1_CS1_MUXMODE," "SPI1_CS1_MUXMODE_0,SPI1_CS1_MUXMODE_1,?,?,SPI1_CS1_MUXMODE_4,?,?,SPI1_CS1_MUXMODE_7,?,?,?,?,?,?,SPI1_CS1_MUXMODE_14,SPI1_CS1_MUXMODE_15" line.long 0x54 "CTRL_CORE_PAD_SPI2_SCLK," hexmask.long.word 0x54 20.--31. 1. "RESERVED," newline bitfld.long 0x54 19. "SPI2_SCLK_SLEWCONTROL," "SPI2_SCLK_SLEWCONTROL_0,SPI2_SCLK_SLEWCONTROL_1" newline bitfld.long 0x54 18. "SPI2_SCLK_INPUTENABLE," "SPI2_SCLK_INPUTENABLE_0,SPI2_SCLK_INPUTENABLE_1" newline bitfld.long 0x54 17. "SPI2_SCLK_PULLTYPESELECT," "SPI2_SCLK_PULLTYPESELECT_0,SPI2_SCLK_PULLTYPESELECT_1" newline bitfld.long 0x54 16. "SPI2_SCLK_PULLUDENABLE," "SPI2_SCLK_PULLUDENABLE_0,SPI2_SCLK_PULLUDENABLE_1" newline hexmask.long.word 0x54 4.--15. 1. "RESERVED," newline bitfld.long 0x54 0.--3. "SPI2_SCLK_MUXMODE," "SPI2_SCLK_MUXMODE_0,SPI2_SCLK_MUXMODE_1,SPI2_SCLK_MUXMODE_2,SPI2_SCLK_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,SPI2_SCLK_MUXMODE_14,SPI2_SCLK_MUXMODE_15" line.long 0x58 "CTRL_CORE_PAD_SPI2_D1," hexmask.long.word 0x58 20.--31. 1. "RESERVED," newline bitfld.long 0x58 19. "SPI2_D1_SLEWCONTROL," "SPI2_D1_SLEWCONTROL_0,SPI2_D1_SLEWCONTROL_1" newline bitfld.long 0x58 18. "SPI2_D1_INPUTENABLE," "SPI2_D1_INPUTENABLE_0,SPI2_D1_INPUTENABLE_1" newline bitfld.long 0x58 17. "SPI2_D1_PULLTYPESELECT," "SPI2_D1_PULLTYPESELECT_0,SPI2_D1_PULLTYPESELECT_1" newline bitfld.long 0x58 16. "SPI2_D1_PULLUDENABLE," "SPI2_D1_PULLUDENABLE_0,SPI2_D1_PULLUDENABLE_1" newline hexmask.long.word 0x58 4.--15. 1. "RESERVED," newline bitfld.long 0x58 0.--3. "SPI2_D1_MUXMODE," "SPI2_D1_MUXMODE_0,SPI2_D1_MUXMODE_1,?,SPI2_D1_MUXMODE_3,?,?,?,SPI2_D1_MUXMODE_7,?,?,?,?,?,?,SPI2_D1_MUXMODE_14,SPI2_D1_MUXMODE_15" line.long 0x5C "CTRL_CORE_PAD_SPI2_D0," hexmask.long.word 0x5C 20.--31. 1. "RESERVED," newline bitfld.long 0x5C 19. "SPI2_D0_SLEWCONTROL," "SPI2_D0_SLEWCONTROL_0,SPI2_D0_SLEWCONTROL_1" newline bitfld.long 0x5C 18. "SPI2_D0_INPUTENABLE," "SPI2_D0_INPUTENABLE_0,SPI2_D0_INPUTENABLE_1" newline bitfld.long 0x5C 17. "SPI2_D0_PULLTYPESELECT," "SPI2_D0_PULLTYPESELECT_0,SPI2_D0_PULLTYPESELECT_1" newline bitfld.long 0x5C 16. "SPI2_D0_PULLUDENABLE," "SPI2_D0_PULLUDENABLE_0,SPI2_D0_PULLUDENABLE_1" newline hexmask.long.word 0x5C 4.--15. 1. "RESERVED," newline bitfld.long 0x5C 0.--3. "SPI2_D0_MUXMODE," "SPI2_D0_MUXMODE_0,SPI2_D0_MUXMODE_1,?,SPI2_D0_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,SPI2_D0_MUXMODE_14,SPI2_D0_MUXMODE_15" line.long 0x60 "CTRL_CORE_PAD_SPI2_CS0," hexmask.long.word 0x60 20.--31. 1. "RESERVED," newline bitfld.long 0x60 19. "SPI2_CS0_SLEWCONTROL," "SPI2_CS0_SLEWCONTROL_0,SPI2_CS0_SLEWCONTROL_1" newline bitfld.long 0x60 18. "SPI2_CS0_INPUTENABLE," "SPI2_CS0_INPUTENABLE_0,SPI2_CS0_INPUTENABLE_1" newline bitfld.long 0x60 17. "SPI2_CS0_PULLTYPESELECT," "SPI2_CS0_PULLTYPESELECT_0,SPI2_CS0_PULLTYPESELECT_1" newline bitfld.long 0x60 16. "SPI2_CS0_PULLUDENABLE," "SPI2_CS0_PULLUDENABLE_0,SPI2_CS0_PULLUDENABLE_1" newline hexmask.long.word 0x60 4.--15. 1. "RESERVED," newline bitfld.long 0x60 0.--3. "SPI2_CS0_MUXMODE," "SPI2_CS0_MUXMODE_0,SPI2_CS0_MUXMODE_1,SPI2_CS0_MUXMODE_2,SPI2_CS0_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,SPI2_CS0_MUXMODE_14,SPI2_CS0_MUXMODE_15" line.long 0x64 "CTRL_CORE_PAD_DCAN1_TX,SR1.0 Only" hexmask.long.word 0x64 20.--31. 1. "RESERVED," newline bitfld.long 0x64 19. "DCAN1_TX_SLEWCONTROL," "DCAN1_TX_SLEWCONTROL_0,DCAN1_TX_SLEWCONTROL_1" newline bitfld.long 0x64 18. "DCAN1_TX_INPUTENABLE," "DCAN1_TX_INPUTENABLE_0,DCAN1_TX_INPUTENABLE_1" newline bitfld.long 0x64 17. "DCAN1_TX_PULLTYPESELECT," "DCAN1_TX_PULLTYPESELECT_0,DCAN1_TX_PULLTYPESELECT_1" newline bitfld.long 0x64 16. "DCAN1_TX_PULLUDENABLE," "DCAN1_TX_PULLUDENABLE_0,DCAN1_TX_PULLUDENABLE_1" newline hexmask.long.word 0x64 4.--15. 1. "RESERVED," newline bitfld.long 0x64 0.--3. "DCAN1_TX_MUXMODE," "DCAN1_TX_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,DCAN1_TX_MUXMODE_14,DCAN1_TX_MUXMODE_15" group.long 0x15B4++0x07 line.long 0x00 "CTRL_CORE_PAD_DCAN_TX,SR2.0 Only" hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline bitfld.long 0x00 19. "DCAN_TX_SLEWCONTROL," "DCAN_TX_SLEWCONTROL_0,DCAN_TX_SLEWCONTROL_1" newline bitfld.long 0x00 18. "DCAN_TX_INPUTENABLE," "DCAN_TX_INPUTENABLE_0,DCAN_TX_INPUTENABLE_1" newline bitfld.long 0x00 17. "DCAN_TX_PULLTYPESELECT," "DCAN_TX_PULLTYPESELECT_0,DCAN_TX_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "DCAN_TX_PULLUDENABLE," "DCAN_TX_PULLUDENABLE_0,DCAN_TX_PULLUDENABLE_1" newline hexmask.long.word 0x00 4.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "DCAN_TX_MUXMODE," "DCAN_TX_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,DCAN_TX_MUXMODE_14,DCAN_TX_MUXMODE_15" line.long 0x04 "CTRL_CORE_PAD_DCAN1_RX,SR1.0 Only" hexmask.long.word 0x04 20.--31. 1. "RESERVED," newline bitfld.long 0x04 19. "DCAN1_RX_SLEWCONTROL," "DCAN1_RX_SLEWCONTROL_0,DCAN1_RX_SLEWCONTROL_1" newline bitfld.long 0x04 18. "DCAN1_RX_INPUTENABLE," "DCAN1_RX_INPUTENABLE_0,DCAN1_RX_INPUTENABLE_1" newline bitfld.long 0x04 17. "DCAN1_RX_PULLTYPESELECT," "DCAN1_RX_PULLTYPESELECT_0,DCAN1_RX_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "DCAN1_RX_PULLUDENABLE," "DCAN1_RX_PULLUDENABLE_0,DCAN1_RX_PULLUDENABLE_1" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 0.--3. "DCAN1_RX_MUXMODE," "DCAN1_RX_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,DCAN1_RX_MUXMODE_14,DCAN1_RX_MUXMODE_15" group.long 0x15B8++0x5F line.long 0x00 "CTRL_CORE_PAD_DCAN_RX,SR2.0 Only" hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline bitfld.long 0x00 19. "DCAN_RX_SLEWCONTROL," "DCAN_RX_SLEWCONTROL_0,DCAN_RX_SLEWCONTROL_1" newline bitfld.long 0x00 18. "DCAN_RX_INPUTENABLE," "DCAN_RX_INPUTENABLE_0,DCAN_RX_INPUTENABLE_1" newline bitfld.long 0x00 17. "DCAN_RX_PULLTYPESELECT," "DCAN_RX_PULLTYPESELECT_0,DCAN_RX_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "DCAN_RX_PULLUDENABLE," "DCAN_RX_PULLUDENABLE_0,DCAN_RX_PULLUDENABLE_1" newline hexmask.long.word 0x00 4.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "DCAN_RX_MUXMODE," "DCAN_RX_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,DCAN_RX_MUXMODE_14,DCAN_RX_MUXMODE_15" line.long 0x04 "CTRL_CORE_PAD_UART1_RXD," hexmask.long.word 0x04 20.--31. 1. "RESERVED," newline bitfld.long 0x04 19. "UART1_RXD_SLEWCONTROL," "UART1_RXD_SLEWCONTROL_0,UART1_RXD_SLEWCONTROL_1" newline bitfld.long 0x04 18. "UART1_RXD_INPUTENABLE," "UART1_RXD_INPUTENABLE_0,UART1_RXD_INPUTENABLE_1" newline bitfld.long 0x04 17. "UART1_RXD_PULLTYPESELECT," "UART1_RXD_PULLTYPESELECT_0,UART1_RXD_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "UART1_RXD_PULLUDENABLE," "UART1_RXD_PULLUDENABLE_0,UART1_RXD_PULLUDENABLE_1" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 0.--3. "UART1_RXD_MUXMODE," "UART1_RXD_MUXMODE_0,?,?,?,UART1_RXD_MUXMODE_4,UART1_RXD_MUXMODE_5,?,?,?,?,UART1_RXD_MUXMODE_10,?,UART1_RXD_MUXMODE_12,?,UART1_RXD_MUXMODE_14,UART1_RXD_MUXMODE_15" line.long 0x08 "CTRL_CORE_PAD_UART1_TXD," hexmask.long.word 0x08 20.--31. 1. "RESERVED," newline bitfld.long 0x08 19. "UART1_TXD_SLEWCONTROL," "UART1_TXD_SLEWCONTROL_0,UART1_TXD_SLEWCONTROL_1" newline bitfld.long 0x08 18. "UART1_TXD_INPUTENABLE," "UART1_TXD_INPUTENABLE_0,UART1_TXD_INPUTENABLE_1" newline bitfld.long 0x08 17. "UART1_TXD_PULLTYPESELECT," "UART1_TXD_PULLTYPESELECT_0,UART1_TXD_PULLTYPESELECT_1" newline bitfld.long 0x08 16. "UART1_TXD_PULLUDENABLE," "UART1_TXD_PULLUDENABLE_0,UART1_TXD_PULLUDENABLE_1" newline hexmask.long.word 0x08 4.--15. 1. "RESERVED," newline bitfld.long 0x08 0.--3. "UART1_TXD_MUXMODE," "UART1_TXD_MUXMODE_0,?,?,?,UART1_TXD_MUXMODE_4,?,?,?,?,?,UART1_TXD_MUXMODE_10,?,UART1_TXD_MUXMODE_12,?,UART1_TXD_MUXMODE_14,UART1_TXD_MUXMODE_15" line.long 0x0C "CTRL_CORE_PAD_UART1_CTSN," hexmask.long.word 0x0C 20.--31. 1. "RESERVED," newline bitfld.long 0x0C 19. "UART1_CTSN_SLEWCONTROL," "UART1_CTSN_SLEWCONTROL_0,UART1_CTSN_SLEWCONTROL_1" newline bitfld.long 0x0C 18. "UART1_CTSN_INPUTENABLE," "UART1_CTSN_INPUTENABLE_0,UART1_CTSN_INPUTENABLE_1" newline bitfld.long 0x0C 17. "UART1_CTSN_PULLTYPESELECT," "UART1_CTSN_PULLTYPESELECT_0,UART1_CTSN_PULLTYPESELECT_1" newline bitfld.long 0x0C 16. "UART1_CTSN_PULLUDENABLE," "UART1_CTSN_PULLUDENABLE_0,UART1_CTSN_PULLUDENABLE_1" newline hexmask.long.word 0x0C 4.--15. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "UART1_CTSN_MUXMODE," "UART1_CTSN_MUXMODE_0,UART1_CTSN_MUXMODE_1,UART1_CTSN_MUXMODE_2,UART1_CTSN_MUXMODE_3,UART1_CTSN_MUXMODE_4,UART1_CTSN_MUXMODE_5,UART1_CTSN_MUXMODE_6,UART1_CTSN_MUXMODE_7,UART1_CTSN_MUXMODE_8,UART1_CTSN_MUXMODE_9,UART1_CTSN_MUXMODE_10,UART1_CTSN_MUXMODE_11,UART1_CTSN_MUXMODE_12,?,UART1_CTSN_MUXMODE_14,UART1_CTSN_MUXMODE_15" line.long 0x10 "CTRL_CORE_PAD_UART1_RTSN," hexmask.long.word 0x10 20.--31. 1. "RESERVED," newline bitfld.long 0x10 19. "UART1_RTSN_SLEWCONTROL," "UART1_RTSN_SLEWCONTROL_0,UART1_RTSN_SLEWCONTROL_1" newline bitfld.long 0x10 18. "UART1_RTSN_INPUTENABLE," "UART1_RTSN_INPUTENABLE_0,UART1_RTSN_INPUTENABLE_1" newline bitfld.long 0x10 17. "UART1_RTSN_PULLTYPESELECT," "UART1_RTSN_PULLTYPESELECT_0,UART1_RTSN_PULLTYPESELECT_1" newline bitfld.long 0x10 16. "UART1_RTSN_PULLUDENABLE," "UART1_RTSN_PULLUDENABLE_0,UART1_RTSN_PULLUDENABLE_1" newline hexmask.long.word 0x10 4.--15. 1. "RESERVED," newline bitfld.long 0x10 0.--3. "UART1_RTSN_MUXMODE," "UART1_RTSN_MUXMODE_0,?,UART1_RTSN_MUXMODE_2,UART1_RTSN_MUXMODE_3,UART1_RTSN_MUXMODE_4,UART1_RTSN_MUXMODE_5,UART1_RTSN_MUXMODE_6,UART1_RTSN_MUXMODE_7,UART1_RTSN_MUXMODE_8,UART1_RTSN_MUXMODE_9,UART1_RTSN_MUXMODE_10,?,UART1_RTSN_MUXMODE_12,?,UART1_RTSN_MUXMODE_14,UART1_RTSN_MUXMODE_15" line.long 0x14 "CTRL_CORE_PAD_UART2_RXD," hexmask.long.word 0x14 20.--31. 1. "RESERVED," newline bitfld.long 0x14 19. "UART2_RXD_SLEWCONTROL," "UART2_RXD_SLEWCONTROL_0,UART2_RXD_SLEWCONTROL_1" newline bitfld.long 0x14 18. "UART2_RXD_INPUTENABLE," "UART2_RXD_INPUTENABLE_0,UART2_RXD_INPUTENABLE_1" newline bitfld.long 0x14 17. "UART2_RXD_PULLTYPESELECT," "UART2_RXD_PULLTYPESELECT_0,UART2_RXD_PULLTYPESELECT_1" newline bitfld.long 0x14 16. "UART2_RXD_PULLUDENABLE," "UART2_RXD_PULLUDENABLE_0,UART2_RXD_PULLUDENABLE_1" newline hexmask.long.word 0x14 4.--15. 1. "RESERVED," newline bitfld.long 0x14 0.--3. "UART2_RXD_MUXMODE," "UART2_RXD_MUXMODE_0,?,?,?,UART2_RXD_MUXMODE_4,?,UART2_RXD_MUXMODE_6,UART2_RXD_MUXMODE_7,?,?,UART2_RXD_MUXMODE_10,UART2_RXD_MUXMODE_11,UART2_RXD_MUXMODE_12,?,UART2_RXD_MUXMODE_14,UART2_RXD_MUXMODE_15" line.long 0x18 "CTRL_CORE_PAD_UART2_TXD," hexmask.long.word 0x18 20.--31. 1. "RESERVED," newline bitfld.long 0x18 19. "UART2_TXD_SLEWCONTROL," "UART2_TXD_SLEWCONTROL_0,UART2_TXD_SLEWCONTROL_1" newline bitfld.long 0x18 18. "UART2_TXD_INPUTENABLE," "UART2_TXD_INPUTENABLE_0,UART2_TXD_INPUTENABLE_1" newline bitfld.long 0x18 17. "UART2_TXD_PULLTYPESELECT," "UART2_TXD_PULLTYPESELECT_0,UART2_TXD_PULLTYPESELECT_1" newline bitfld.long 0x18 16. "UART2_TXD_PULLUDENABLE," "UART2_TXD_PULLUDENABLE_0,UART2_TXD_PULLUDENABLE_1" newline hexmask.long.word 0x18 4.--15. 1. "RESERVED," newline bitfld.long 0x18 0.--3. "UART2_TXD_MUXMODE," "UART2_TXD_MUXMODE_0,?,?,?,UART2_TXD_MUXMODE_4,?,UART2_TXD_MUXMODE_6,UART2_TXD_MUXMODE_7,?,?,?,UART2_TXD_MUXMODE_11,UART2_TXD_MUXMODE_12,?,UART2_TXD_MUXMODE_14,UART2_TXD_MUXMODE_15" line.long 0x1C "CTRL_CORE_PAD_UART2_CTSN," hexmask.long.word 0x1C 20.--31. 1. "RESERVED," newline bitfld.long 0x1C 19. "UART2_CTSN_SLEWCONTROL," "UART2_CTSN_SLEWCONTROL_0,UART2_CTSN_SLEWCONTROL_1" newline bitfld.long 0x1C 18. "UART2_CTSN_INPUTENABLE," "UART2_CTSN_INPUTENABLE_0,UART2_CTSN_INPUTENABLE_1" newline bitfld.long 0x1C 17. "UART2_CTSN_PULLTYPESELECT," "UART2_CTSN_PULLTYPESELECT_0,UART2_CTSN_PULLTYPESELECT_1" newline bitfld.long 0x1C 16. "UART2_CTSN_PULLUDENABLE," "UART2_CTSN_PULLUDENABLE_0,UART2_CTSN_PULLUDENABLE_1" newline hexmask.long.word 0x1C 4.--15. 1. "RESERVED," newline bitfld.long 0x1C 0.--3. "UART2_CTSN_MUXMODE," "UART2_CTSN_MUXMODE_0,?,UART2_CTSN_MUXMODE_2,UART2_CTSN_MUXMODE_3,UART2_CTSN_MUXMODE_4,UART2_CTSN_MUXMODE_5,UART2_CTSN_MUXMODE_6,?,?,UART2_CTSN_MUXMODE_9,UART2_CTSN_MUXMODE_10,?,UART2_CTSN_MUXMODE_12,?,UART2_CTSN_MUXMODE_14,UART2_CTSN_MUXMODE_15" line.long 0x20 "CTRL_CORE_PAD_UART2_RTSN," hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline bitfld.long 0x20 19. "UART2_RTSN_SLEWCONTROL," "UART2_RTSN_SLEWCONTROL_0,UART2_RTSN_SLEWCONTROL_1" newline bitfld.long 0x20 18. "UART2_RTSN_INPUTENABLE," "UART2_RTSN_INPUTENABLE_0,UART2_RTSN_INPUTENABLE_1" newline bitfld.long 0x20 17. "UART2_RTSN_PULLTYPESELECT," "UART2_RTSN_PULLTYPESELECT_0,UART2_RTSN_PULLTYPESELECT_1" newline bitfld.long 0x20 16. "UART2_RTSN_PULLUDENABLE," "UART2_RTSN_PULLUDENABLE_0,UART2_RTSN_PULLUDENABLE_1" newline hexmask.long.word 0x20 4.--15. 1. "RESERVED," newline bitfld.long 0x20 0.--3. "UART2_RTSN_MUXMODE," "UART2_RTSN_MUXMODE_0,UART2_RTSN_MUXMODE_1,?,UART2_RTSN_MUXMODE_3,UART2_RTSN_MUXMODE_4,?,UART2_RTSN_MUXMODE_6,?,?,UART2_RTSN_MUXMODE_9,?,?,UART2_RTSN_MUXMODE_12,?,UART2_RTSN_MUXMODE_14,UART2_RTSN_MUXMODE_15" line.long 0x24 "CTRL_CORE_PAD_I2C1_SDA," hexmask.long.word 0x24 19.--31. 1. "RESERVED," newline bitfld.long 0x24 18. "I2C1_SDA_INPUTENABLE," "I2C1_SDA_INPUTENABLE_0,I2C1_SDA_INPUTENABLE_1" newline hexmask.long.tbyte 0x24 0.--17. 1. "RESERVED," line.long 0x28 "CTRL_CORE_PAD_I2C1_SCL," hexmask.long.word 0x28 19.--31. 1. "RESERVED," newline bitfld.long 0x28 18. "I2C1_SCL_INPUTENABLE," "I2C1_SCL_INPUTENABLE_0,I2C1_SCL_INPUTENABLE_1" newline hexmask.long.tbyte 0x28 0.--17. 1. "RESERVED," line.long 0x2C "CTRL_CORE_PAD_I2C2_SDA," hexmask.long.word 0x2C 19.--31. 1. "RESERVED," newline bitfld.long 0x2C 18. "I2C2_SDA_INPUTENABLE," "I2C2_SDA_INPUTENABLE_0,I2C2_SDA_INPUTENABLE_1" newline hexmask.long.tbyte 0x2C 0.--17. 1. "RESERVED," line.long 0x30 "CTRL_CORE_PAD_I2C2_SCL," hexmask.long.word 0x30 19.--31. 1. "RESERVED," newline bitfld.long 0x30 18. "I2C2_SCL_INPUTENABLE," "I2C2_SCL_INPUTENABLE_0,I2C2_SCL_INPUTENABLE_1" newline hexmask.long.tbyte 0x30 0.--17. 1. "RESERVED," line.long 0x34 "CTRL_CORE_PAD_TMS," hexmask.long.word 0x34 20.--31. 1. "RESERVED," newline bitfld.long 0x34 19. "TMS_SLEWCONTROL," "TMS_SLEWCONTROL_0,TMS_SLEWCONTROL_1" newline bitfld.long 0x34 18. "TMS_INPUTENABLE," "TMS_INPUTENABLE_0,TMS_INPUTENABLE_1" newline hexmask.long.word 0x34 4.--17. 1. "RESERVED," newline bitfld.long 0x34 0.--3. "TMS_MUXMODE," "TMS_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x38 "CTRL_CORE_PAD_TDI," hexmask.long.word 0x38 20.--31. 1. "RESERVED," newline bitfld.long 0x38 19. "TDI_SLEWCONTROL," "TDI_SLEWCONTROL_0,TDI_SLEWCONTROL_1" newline bitfld.long 0x38 18. "TDI_INPUTENABLE," "TDI_INPUTENABLE_0,TDI_INPUTENABLE_1" newline bitfld.long 0x38 17. "TDI_PULLTYPESELECT," "TDI_PULLTYPESELECT_0,TDI_PULLTYPESELECT_1" newline bitfld.long 0x38 16. "TDI_PULLUDENABLE," "TDI_PULLUDENABLE_0,TDI_PULLUDENABLE_1" newline hexmask.long.word 0x38 4.--15. 1. "RESERVED," newline bitfld.long 0x38 0.--3. "TDI_MUXMODE," "TDI_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,TDI_MUXMODE_14,TDI_MUXMODE_15" line.long 0x3C "CTRL_CORE_PAD_TDO," hexmask.long.word 0x3C 20.--31. 1. "RESERVED," newline bitfld.long 0x3C 19. "TDO_SLEWCONTROL," "TDO_SLEWCONTROL_0,TDO_SLEWCONTROL_1" newline bitfld.long 0x3C 18. "TDO_INPUTENABLE," "TDO_INPUTENABLE_0,TDO_INPUTENABLE_1" newline bitfld.long 0x3C 17. "TDO_PULLTYPESELECT," "TDO_PULLTYPESELECT_0,TDO_PULLTYPESELECT_1" newline bitfld.long 0x3C 16. "TDO_PULLUDENABLE," "TDO_PULLUDENABLE_0,TDO_PULLUDENABLE_1" newline hexmask.long.word 0x3C 4.--15. 1. "RESERVED," newline bitfld.long 0x3C 0.--3. "TDO_MUXMODE," "TDO_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,TDO_MUXMODE_14,TDO_MUXMODE_15" line.long 0x40 "CTRL_CORE_PAD_TCLK," hexmask.long.word 0x40 19.--31. 1. "RESERVED," newline bitfld.long 0x40 18. "TCLK_INPUTENABLE," "TCLK_INPUTENABLE_0,TCLK_INPUTENABLE_1" newline bitfld.long 0x40 17. "TCLK_PULLTYPESELECT," "TCLK_PULLTYPESELECT_0,TCLK_PULLTYPESELECT_1" newline bitfld.long 0x40 16. "TCLK_PULLUDENABLE," "TCLK_PULLUDENABLE_0,TCLK_PULLUDENABLE_1" newline hexmask.long.word 0x40 4.--15. 1. "RESERVED," newline bitfld.long 0x40 0.--3. "TCLK_MUXMODE," "TCLK_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x44 "CTRL_CORE_PAD_TRSTN," hexmask.long.word 0x44 20.--31. 1. "RESERVED," newline bitfld.long 0x44 19. "TRSTN_SLEWCONTROL," "TRSTN_SLEWCONTROL_0,TRSTN_SLEWCONTROL_1" newline bitfld.long 0x44 18. "TRSTN_INPUTENABLE," "TRSTN_INPUTENABLE_0,TRSTN_INPUTENABLE_1" newline bitfld.long 0x44 17. "TRSTN_PULLTYPESELECT," "TRSTN_PULLTYPESELECT_0,TRSTN_PULLTYPESELECT_1" newline bitfld.long 0x44 16. "TRSTN_PULLUDENABLE," "TRSTN_PULLUDENABLE_0,TRSTN_PULLUDENABLE_1" newline hexmask.long.word 0x44 0.--15. 1. "RESERVED," line.long 0x48 "CTRL_CORE_PAD_RTCK," hexmask.long.word 0x48 20.--31. 1. "RESERVED," newline bitfld.long 0x48 19. "RTCK_SLEWCONTROL," "RTCK_SLEWCONTROL_0,RTCK_SLEWCONTROL_1" newline bitfld.long 0x48 18. "RTCK_INPUTENABLE," "RTCK_INPUTENABLE_0,RTCK_INPUTENABLE_1" newline bitfld.long 0x48 17. "RTCK_PULLTYPESELECT," "RTCK_PULLTYPESELECT_0,RTCK_PULLTYPESELECT_1" newline bitfld.long 0x48 16. "RTCK_PULLUDENABLE," "RTCK_PULLUDENABLE_0,RTCK_PULLUDENABLE_1" newline hexmask.long.word 0x48 4.--15. 1. "RESERVED," newline bitfld.long 0x48 0.--3. "RTCK_MUXMODE," "RTCK_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,RTCK_MUXMODE_14,RTCK_MUXMODE_15" line.long 0x4C "CTRL_CORE_PAD_EMU0," hexmask.long.word 0x4C 20.--31. 1. "RESERVED," newline bitfld.long 0x4C 19. "EMU0_SLEWCONTROL," "EMU0_SLEWCONTROL_0,EMU0_SLEWCONTROL_1" newline bitfld.long 0x4C 18. "EMU0_INPUTENABLE," "EMU0_INPUTENABLE_0,EMU0_INPUTENABLE_1" newline bitfld.long 0x4C 17. "EMU0_PULLTYPESELECT," "EMU0_PULLTYPESELECT_0,EMU0_PULLTYPESELECT_1" newline bitfld.long 0x4C 16. "EMU0_PULLUDENABLE," "EMU0_PULLUDENABLE_0,EMU0_PULLUDENABLE_1" newline hexmask.long.word 0x4C 4.--15. 1. "RESERVED," newline bitfld.long 0x4C 0.--3. "EMU0_MUXMODE," "EMU0_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,EMU0_MUXMODE_14,EMU0_MUXMODE_15" line.long 0x50 "CTRL_CORE_PAD_EMU1," hexmask.long.word 0x50 20.--31. 1. "RESERVED," newline bitfld.long 0x50 19. "EMU1_SLEWCONTROL," "EMU1_SLEWCONTROL_0,EMU1_SLEWCONTROL_1" newline bitfld.long 0x50 18. "EMU1_INPUTENABLE," "EMU1_INPUTENABLE_0,EMU1_INPUTENABLE_1" newline bitfld.long 0x50 17. "EMU1_PULLTYPESELECT," "EMU1_PULLTYPESELECT_0,EMU1_PULLTYPESELECT_1" newline bitfld.long 0x50 16. "EMU1_PULLUDENABLE," "EMU1_PULLUDENABLE_0,EMU1_PULLUDENABLE_1" newline hexmask.long.word 0x50 4.--15. 1. "RESERVED," newline bitfld.long 0x50 0.--3. "EMU1_MUXMODE," "EMU1_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,EMU1_MUXMODE_14,EMU1_MUXMODE_15" line.long 0x54 "CTRL_CORE_PAD_RESETN," hexmask.long.word 0x54 18.--31. 1. "RESERVED," newline bitfld.long 0x54 17. "RESETN_PULLTYPESELECT," "RESETN_PULLTYPESELECT_0,RESETN_PULLTYPESELECT_1" newline bitfld.long 0x54 16. "RESETN_PULLUDENABLE," "RESETN_PULLUDENABLE_0,RESETN_PULLUDENABLE_1" newline hexmask.long.word 0x54 0.--15. 1. "RESERVED," line.long 0x58 "CTRL_CORE_PAD_NMIN," hexmask.long.word 0x58 18.--31. 1. "RESERVED," newline bitfld.long 0x58 17. "NMIN_PULLTYPESELECT," "NMIN_PULLTYPESELECT_0,NMIN_PULLTYPESELECT_1" newline bitfld.long 0x58 16. "NMIN_PULLUDENABLE," "NMIN_PULLUDENABLE_0,NMIN_PULLUDENABLE_1" newline hexmask.long.word 0x58 0.--15. 1. "RESERVED," line.long 0x5C "CTRL_CORE_PAD_RSTOUTN," hexmask.long.word 0x5C 18.--31. 1. "RESERVED," newline bitfld.long 0x5C 17. "RSTOUTN_PULLTYPESELECT," "RSTOUTN_PULLTYPESELECT_0,RSTOUTN_PULLTYPESELECT_1" newline bitfld.long 0x5C 16. "RSTOUTN_PULLUDENABLE," "RSTOUTN_PULLUDENABLE_0,RSTOUTN_PULLUDENABLE_1" newline hexmask.long.word 0x5C 0.--15. 1. "RESERVED," group.long 0x1A10++0x0B line.long 0x00 "CTRL_CORE_L4_CFG_ROLES_0_LOWER,L4 Config Protection Group 0 Roles [31:0]" line.long 0x04 "CTRL_CORE_L4_CFG_ROLES_0_UPPER,L4 Config Protection Group 0 Roles [63:32]" line.long 0x08 "CTRL_CORE_L4_CFG_MEMBERS_0,L4 Config Protection Group 0 Members and lock" bitfld.long 0x08 31. "L4_CFG_DISABLE_0,L4 Config Protection Group 0 Lock" "0,1" newline hexmask.long.word 0x08 16.--30. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "L4_CFG_MEMBERS_0,L4 Config Protection Group 0 Members [15:0]" group.long 0x1A20++0x0B line.long 0x00 "CTRL_CORE_L4_CFG_ROLES_1_LOWER,L4 Config Protection Group 1 Roles [31:0]" line.long 0x04 "CTRL_CORE_L4_CFG_ROLES_1_UPPER,L4 Config Protection Group 1 Roles [63:32]" line.long 0x08 "CTRL_CORE_L4_CFG_MEMBERS_1,L4 Config Protection Group 1 Members and lock" bitfld.long 0x08 31. "L4_CFG_DISABLE_1,L4 Config Protection Group 1 Lock" "0,1" newline hexmask.long.word 0x08 16.--30. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "L4_CFG_MEMBERS_1,L4 Config Protection Group 1 Members [15:0]" group.long 0x1A40++0x0B line.long 0x00 "CTRL_CORE_L4_PER_1_ROLES_0_LOWER,L4 Per 1 Protection Group 0 Roles [31:0]" line.long 0x04 "CTRL_CORE_L4_PER_1_ROLES_0_UPPER,L4 Per 1 Protection Group 0 Roles [63:32]" line.long 0x08 "CTRL_CORE_L4_PER_1_MEMBERS_0,L4 Per 1 Protection Group 0 Members and lock" bitfld.long 0x08 31. "L4_PER_1_DISABLE_0,L4 Per 1 Protection Group 0 Lock" "0,1" newline hexmask.long.word 0x08 16.--30. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "L4_PER_1_MEMBERS_0,L4 Per 1 Protection Group 0 Members [15:0]" group.long 0x1A60++0x0B line.long 0x00 "CTRL_CORE_L4_PER_2_ROLES_0_LOWER,L4 Per 2 Protection Group 0 Roles [31:0]" line.long 0x04 "CTRL_CORE_L4_PER_2_ROLES_0_UPPER,L4 Per 2 Protection Group 0 Roles [63:32]" line.long 0x08 "CTRL_CORE_L4_PER_2_MEMBERS_0,L4 Per 2 Protection Group 0 Members and lock" bitfld.long 0x08 31. "L4_PER_2_DISABLE_0,L4 Per 2 Protection Group 0 Lock" "0,1" newline hexmask.long.word 0x08 16.--30. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "L4_PER_2_MEMBERS_0,L4 Per 2 Protection Group 0 Members [15:0]" group.long 0x1A70++0x0B line.long 0x00 "CTRL_CORE_L4_PER_3_ROLES_0_LOWER,L4 Per 3 Protection Group 0 Roles [31:0]" line.long 0x04 "CTRL_CORE_L4_PER_3_ROLES_0_UPPER,L4 Per 3 Protection Group 0 Roles [63:32]" line.long 0x08 "CTRL_CORE_L4_PER_3_MEMBERS_0,L4 Per 3 Protection Group 0 Members and lock" bitfld.long 0x08 31. "L4_PER_3_DISABLE_0,L4 Per 3 Protection Group 0 Lock" "0,1" newline hexmask.long.word 0x08 16.--30. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "L4_PER_3_MEMBERS_0,L4 Per 3 Protection Group 0 Members [15:0]" group.long 0x1A80++0x0B line.long 0x00 "CTRL_CORE_L4_WKUP_ROLES_0_LOWER,L4 Wakeup Protection Group 0 Roles [31:0]" line.long 0x04 "CTRL_CORE_L4_WKUP_ROLES_0_UPPER,L4 Wakeup Protection Group 0 Roles [63:32]" line.long 0x08 "CTRL_CORE_L4_WKUP_MEMBERS_0,L4 Wakeup Protection Group 0 Members and lock" bitfld.long 0x08 31. "L4_WKUP_DISABLE_0,L4 Wakeup Protection Group 0 Lock" "0,1" newline hexmask.long.word 0x08 16.--30. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "L4_WKUP_MEMBERS_0,L4 Wakeup Protection Group 0 Members [15:0]" group.long 0x1AA0++0x0B line.long 0x00 "CTRL_CORE_L4_WKUP_ROLES_3_LOWER,L4 Wakeup Protection Group 3 Roles [31:0]" line.long 0x04 "CTRL_CORE_L4_WKUP_ROLES_3_UPPER,L4 Wakeup Protection Group 3 Roles [63:32]" line.long 0x08 "CTRL_CORE_L4_WKUP_MEMBERS_3,L4 Wakeup Protection Group 3 Members and lock" bitfld.long 0x08 31. "L4_WKUP_DISABLE_3,L4 Wakeup Protection Group 3 Lock" "0,1" newline hexmask.long.word 0x08 16.--30. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "L4_WKUP_MEMBERS_3,L4 Wakeup Protection Group 3 Members [15:0]" group.long 0x1AB0++0x0B line.long 0x00 "CTRL_CORE_L4_WKUP_ROLES_4_LOWER,L4 Wakeup Protection Group 4 Roles [31:0]" line.long 0x04 "CTRL_CORE_L4_WKUP_ROLES_4_UPPER,L4 Wakeup Protection Group 4 Roles [63:32]" line.long 0x08 "CTRL_CORE_L4_WKUP_MEMBERS_4,L4 Wakeup Protection Group 4 Members and lock" bitfld.long 0x08 31. "L4_WKUP_DISABLE_4,L4 Wakeup Protection Group 4 Lock" "0,1" newline hexmask.long.word 0x08 16.--30. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "L4_WKUP_MEMBERS_4,L4 Wakeup Protection Group 4 Members [15:0]" rgroup.long 0x1B38++0x13 line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_0,Standard Fuse OPP VDD_GPU [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_1,Standard Fuse OPP VDD_GPU [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_2,Standard Fuse OPP VDD_GPU [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_3,Standard Fuse OPP VDD_GPU [127:96]" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_4,Standard Fuse OPP VDD_GPU [159:128]" rgroup.long 0x1B60++0x1F line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_0,Standard Fuse OPP VDD_CORE [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_1,Standard Fuse OPP VDD_CORE [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_2,Standard Fuse OPP VDD_CORE [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_3,Standard Fuse OPP VDD_CORE [127:96]" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_4,Standard Fuse OPP VDD_CORE [159:128]" line.long 0x14 "CTRL_CORE_LDOSRAM_CORE_4_VOLTAGE_CTRL,CORE 4th SRAM LDO Control register" rbitfld.long 0x14 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 26. "LDOSRAMCORE_4_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value" "LDOSRAMCORE_4_RETMODE_MUX_CTRL_0,LDOSRAMCORE_4_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x14 21.--25. "LDOSRAMCORE_4_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 16.--20. "LDOSRAMCORE_4_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x14 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 10. "LDOSRAMCORE_4_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value" "LDOSRAMCORE_4_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_4_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x14 5.--9. "LDOSRAMCORE_4_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 0.--4. "LDOSRAMCORE_4_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "CTRL_CORE_LDOSRAM_CORE_5_VOLTAGE_CTRL,CORE 5th SRAM LDO Control register" rbitfld.long 0x18 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 26. "LDOSRAMCORE_5_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value" "LDOSRAMCORE_5_RETMODE_MUX_CTRL_0,LDOSRAMCORE_5_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x18 21.--25. "LDOSRAMCORE_5_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 16.--20. "LDOSRAMCORE_5_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x18 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 10. "LDOSRAMCORE_5_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value" "LDOSRAMCORE_5_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_5_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x18 5.--9. "LDOSRAMCORE_5_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 0.--4. "LDOSRAMCORE_5_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "CTRL_CORE_LDOSRAM_DSPEVE_2_VOLTAGE_CTRL,DSPEVE 2nd SRAM LDO Control register" rbitfld.long 0x1C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 26. "LDOSRAMDSPEVE_2_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value" "LDOSRAMDSPEVE_2_RETMODE_MUX_CTRL_0,LDOSRAMDSPEVE_2_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x1C 21.--25. "LDOSRAMDSPEVE_2_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 16.--20. "LDOSRAMDSPEVE_2_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x1C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 10. "LDOSRAMDSPEVE_2_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value" "LDOSRAMDSPEVE_2_ACTMODE_MUX_CTRL_0,LDOSRAMDSPEVE_2_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x1C 5.--9. "LDOSRAMDSPEVE_2_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 0.--4. "LDOSRAMDSPEVE_2_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1C04++0x07 line.long 0x00 "CTRL_CORE_SMA_SW_2,OCP Spare Register" line.long 0x04 "CTRL_CORE_SMA_SW_3,OCP Spare Register" group.long 0x1C14++0x07 line.long 0x00 "CTRL_CORE_SMA_SW_6,OCP Spare Register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "RMII_CLK_SETTING,RMII CLK setting" "Internal clock from..,Reserved" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," newline bitfld.long 0x00 0. "MUXSEL_32K_CLKIN,Setting for mux to select 32KHz clock input to PRCM" "0,1" line.long 0x04 "CTRL_CORE_SMA_SW_7,OCP Spare Register" hexmask.long.word 0x04 17.--31. 1. "RESERVED," newline bitfld.long 0x04 16. "MMU1_ABORT_ENABLE,MMU1 abort enable" "0,1" newline rbitfld.long 0x04 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 11. "EDMA_TC0_RD_MMU_ROUTE_ENABLE,EDMA TC0 RD traffic MMU route enable" "0,1" newline bitfld.long 0x04 10. "EDMA_TC1_RD_MMU_ROUTE_ENABLE,EDMA TC1 RD traffic MMU route enable" "0,1" newline bitfld.long 0x04 9. "EDMA_TC0_WR_MMU_ROUTE_ENABLE,EDMA TC0 WR traffic MMU route enable" "0,1" newline bitfld.long 0x04 8. "EDMA_TC1_WR_MMU_ROUTE_ENABLE,EDMA TC1 WR traffic MMU route enable" "0,1" newline hexmask.long.byte 0x04 0.--7. 1. "RESERVED," group.long 0x1C48++0x5F line.long 0x00 "CTRL_CORE_FIREWALL_CONNID_CONTROL_0,Firewall ConnID control register" bitfld.long 0x00 28.--31. "MMU1_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "EDMA_TC0_RD_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "EDMA_TC0_WR_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "EDMA_TC1_RD_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "EDMA_TC1_WR_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "VIP1_P0_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "VIP1_P1_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "EVE1_TC0_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "CTRL_CORE_FIREWALL_CONNID_CONTROL_1,Firewall ConnID control register" bitfld.long 0x04 28.--31. "EVE1_TC1_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 24.--27. "DSP1_EDMA_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 20.--23. "DSP1_MDMA_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 16.--19. "DSP2_EDMA_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12.--15. "DSP2_MDMA_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. "DSS_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x04 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. "IPU1_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "CTRL_CORE_FIREWALL_CONNID_CONTROL_2,Firewall ConnID control register" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "DSP1_CFG_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 20.--23. "DSP2_CFG_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 16.--19. "GMAC_SW_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 0.--15. 1. "RESERVED," line.long 0x0C "CTRL_CORE_FIREWALL_CONNID_CONTROL_3,Firewall ConnID control register" rbitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 24.--27. "ISS_RT_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x0C 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 16.--19. "ISS_NRT1_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 12.--15. "ISS_NRT2_CONNID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 0.--11. 1. "RESERVED," line.long 0x10 "CTRL_CORE_EMIF_MPU_ROUTING,EMIF MPU traffic control register" hexmask.long 0x10 4.--31. 1. "RESERVED," newline bitfld.long 0x10 3. "EVE1_ROUTING_ENABLE," "0,1" newline bitfld.long 0x10 2. "DSP2_ROUTING_ENABLE," "0,1" newline bitfld.long 0x10 1. "DSP1_ROUTING_ENABLE," "0,1" newline bitfld.long 0x10 0. "IPU1_ROUTING_ENABLE," "0,1" line.long 0x14 "CTRL_CORE_PRCM_CLKSEL_CONTROL,PRCM Clock selection control register" rbitfld.long 0x14 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 28. "EVE_CLKSEL,EVE Clock selection control" "EVE_CLKSEL_0,EVE_CLKSEL_1" newline rbitfld.long 0x14 26.--27. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 24.--25. "DSP_CLKSEL,DSP Clock selection control" "DSP_CLKSEL_0,DSP_CLKSEL_1,DSP_CLKSEL_2,DSP_CLKSEL_3" newline rbitfld.long 0x14 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 20.--21. "ADC_CLKSEL,ADC Clock selection control" "ADC_CLKSEL_0,ADC_CLKSEL_1,ADC_CLKSEL_2,ADC_CLKSEL_3" newline rbitfld.long 0x14 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 16.--17. "RTI1_CLKSEL,RTI1 Clock selection control" "RTI1_CLKSEL_0,RTI1_CLKSEL_1,RTI1_CLKSEL_2,RTI1_CLKSEL_3" newline rbitfld.long 0x14 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 12.--13. "RTI2_CLKSEL,RTI2 Clock selection control" "RTI2_CLKSEL_0,RTI2_CLKSEL_1,RTI2_CLKSEL_2,RTI2_CLKSEL_3" newline rbitfld.long 0x14 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 8.--9. "RTI3_CLKSEL,RTI3 Clock selection control" "RTI3_CLKSEL_0,RTI3_CLKSEL_1,RTI3_CLKSEL_2,RTI3_CLKSEL_3" newline rbitfld.long 0x14 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 4.--5. "RTI4_CLKSEL,RTI4 Clock selection control" "RTI4_CLKSEL_0,RTI4_CLKSEL_1,RTI4_CLKSEL_2,RTI4_CLKSEL_3" newline rbitfld.long 0x14 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 0.--1. "RTI5_CLKSEL,RTI5 Clock selection control" "RTI5_CLKSEL_0,RTI5_CLKSEL_1,RTI5_CLKSEL_2,RTI5_CLKSEL_3" line.long 0x18 "CTRL_CORE_PRCM_CLKDIV_CONTROL1,PRCM Clock divider control1 register" rbitfld.long 0x18 30.--31. "RESERVED,Read returns 0" "0,1,2,3" newline rbitfld.long 0x18 29. "DBG_STM_EXPT_CLK_HSDIV_CHANGE_ACK,HSDIVIDER change ack" "0,1" newline rbitfld.long 0x18 28. "DBG_STM_EXPT_CLK_HSDIV_EN_ACK,EN_ACK from HSDIVIDER" "0,1" newline rbitfld.long 0x18 27. "DBG_TRC_EXPT_CLK_HSDIV_CHANGE_ACK,HSDIVIDER change ack" "0,1" newline rbitfld.long 0x18 26. "DBG_TRC_EXPT_CLK_HSDIV_EN_ACK,EN_ACK from HSDIVIDER" "0,1" newline rbitfld.long 0x18 25. "DBG_ATB_CLK_HSDIV_CHANGE_ACK,HSDIVIDER change ack" "0,1" newline rbitfld.long 0x18 24. "DBG_ATB_CLK_HSDIV_EN_ACK,EN_ACK from HSDIVIDER" "0,1" newline bitfld.long 0x18 23. "DBG_STM_EXPT_CLK_TENABLEDIV_SEL," "0,1" newline bitfld.long 0x18 22. "DBG_STM_EXPT_CLK_TENABLEDIV,Needs to be pulsed (LO->HI->LO) for latching the divider value in to the DPLL" "0,1" newline bitfld.long 0x18 16.--21. "DBG_STM_EXPT_CLK_DIV,DebugSS STM Clock divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x18 15. "DBG_TRC_EXPT_CLK_TENABLEDIV_SEL," "0,1" newline bitfld.long 0x18 14. "DBG_TRC_EXPT_CLK_TENABLEDIV,Needs to be pulsed (LO->HI->LO) for latching the divider value in to the DPLL" "0,1" newline bitfld.long 0x18 8.--13. "DBG_TRC_EXPT_CLK_DIV,DebugSS TRC Clock divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x18 7. "RESERVED," "0,1" newline bitfld.long 0x18 6. "DBG_ATB_CLK_TENABLEDIV,Needs to be pulsed (LO->HI->LO) for latching the divider value in to the DPLL" "0,1" newline bitfld.long 0x18 0.--5. "DBG_ATB_CLK_DIV,DebugSS ATB Clock divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "CTRL_CORE_PRCM_CLKDIV_CONTROL2,PRCM Clock divider control2 register" rbitfld.long 0x1C 29.--31. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 28. "VID_PIX_CLK_TENABLEDIV_SEL,VID_PIX_CLK_TENABLEDIV control select" "Control from PRCM,Control from Control Module -.." newline rbitfld.long 0x1C 27. "VID_PIX_CLK_HSDIV_CHANGE_ACK,HSDIVIDER change ack" "0,1" newline bitfld.long 0x1C 25.--26. "VID_PIX_CLK_EXT_CLK_DIV,Video Clock divider value" "VID_PIX_CLK_EXT_CLK_DIV_0,VID_PIX_CLK_EXT_CLK_DIV_1,VID_PIX_CLK_EXT_CLK_DIV_2,VID_PIX_CLK_EXT_CLK_DIV_3" newline rbitfld.long 0x1C 24. "VID_PIX_CLK_HSDIV_EN_ACK,EN_ACK from HSDIVIDER" "0,1" newline bitfld.long 0x1C 23. "VID_PIX_CLK_HSDIV_EN,Clock enable to the Video Clock HS divider" "0,1" newline bitfld.long 0x1C 22. "VID_PIX_CLK_HSDIV_LATCH_EN,Video Clock HS divider latch enable: To be toggled to latch DIV value in HSDIVIDER" "0,1" newline bitfld.long 0x1C 16.--21. "VID_PIX_CLK_HSDIV,Video Clock HS divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x1C 14.--15. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "TESOC_DBG_ATB_CLK_TENABLEDIV_SEL,Mux select for the TENABLE of Core DPLL HS divider" "PRCM,DBG_ATB_CLK,TESOC_EXT_CLK_HSDIV,Reserved" newline rbitfld.long 0x1C 11. "TESOC_HSDIV_CHANGE_ACK,HSDIVIDER change ack" "0,1" newline bitfld.long 0x1C 9.--10. "TESOC_EXT_CLK_DIV,TesOC clock divider value" "TESOC_EXT_CLK_DIV_0,TESOC_EXT_CLK_DIV_1,TESOC_EXT_CLK_DIV_2,TESOC_EXT_CLK_DIV_3" newline rbitfld.long 0x1C 8. "TESOC_HSDIV_EN_ACK,EN_ACK from HSDIVIDER" "0,1" newline bitfld.long 0x1C 7. "TESOC_HSDIV_EN,Clock enable to TesOC clock HS divider" "0,1" newline bitfld.long 0x1C 6. "TESOC_HSDIV_LATCH_EN,TesOC clock HS divider latch enable: To be toggled to latch DIV value in DPLL" "0,1" newline bitfld.long 0x1C 0.--5. "TESOC_HSDIV,TesOC clock HS divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "CTRL_CORE_SMA_SW_10,OCP Spare Register" rbitfld.long 0x20 30.--31. "SMA_SW_10,spare bits" "0,1,2,3" newline bitfld.long 0x20 29. "IE_CSI2_0_Y4," "0,1" newline bitfld.long 0x20 28. "IE_CSI2_0_X4," "0,1" newline bitfld.long 0x20 27. "IE_CSI2_0_Y3," "0,1" newline bitfld.long 0x20 25.--26. "IE_CSI2_0_X3," "0,1,2,3" newline bitfld.long 0x20 24. "IE_CSI2_0_Y2," "0,1" newline bitfld.long 0x20 23. "IE_CSI2_0_X2," "0,1" newline bitfld.long 0x20 22. "IE_CSI2_0_Y1," "0,1" newline bitfld.long 0x20 21. "IE_CSI2_0_X1," "0,1" newline bitfld.long 0x20 20. "IE_CSI2_0_Y0," "0,1" newline bitfld.long 0x20 19. "IE_CSI2_0_X0," "0,1" newline bitfld.long 0x20 18. "PIPD_CSI2_0_X4," "0,1" newline bitfld.long 0x20 17. "PIPD_CSI2_0_Y3," "0,1" newline bitfld.long 0x20 16. "PIPD_CSI2_0_X3," "0,1" newline bitfld.long 0x20 15. "PIPD_CSI2_0_Y2," "0,1" newline bitfld.long 0x20 14. "PIPD_CSI2_0_X2," "0,1" newline bitfld.long 0x20 13. "PIPD_CSI2_0_Y1," "0,1" newline bitfld.long 0x20 12. "PIPD_CSI2_0_X1," "0,1" newline bitfld.long 0x20 11. "PIPD_CSI2_0_Y0," "0,1" newline bitfld.long 0x20 10. "PIPD_CSI2_0_X0," "0,1" newline bitfld.long 0x20 9. "PIPU_CSI2_0_Y4," "0,1" newline bitfld.long 0x20 8. "PIPU_CSI2_0_X4," "0,1" newline bitfld.long 0x20 7. "PIPU_CSI2_0_Y3," "0,1" newline bitfld.long 0x20 6. "PIPU_CSI2_0_X3," "0,1" newline bitfld.long 0x20 5. "PIPU_CSI2_0_Y2," "0,1" newline bitfld.long 0x20 4. "PIPU_CSI2_0_X2," "0,1" newline bitfld.long 0x20 3. "PIPU_CSI2_0_Y1," "0,1" newline bitfld.long 0x20 2. "PIPU_CSI2_0_X1," "0,1" newline bitfld.long 0x20 1. "PIPU_CSI2_0_Y0," "0,1" newline bitfld.long 0x20 0. "PIPU_CSI2_0_X0," "0,1" line.long 0x24 "CTRL_CORE_SMA_SW_11,OCP Spare Register" line.long 0x28 "CTRL_CORE_SMA_SW_12,OCP Spare Register" line.long 0x2C "CTRL_CORE_SMA_SW_13,OCP Spare Register" line.long 0x30 "CTRL_CORE_TESOC_LAST_RESET_INDICATOR,TESOC last reset indicator register" rbitfld.long 0x30 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x30 24.--27. "IPU_LAST_RESET_INDICATOR,IPU resert indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x30 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x30 16.--19. "DSP1_LAST_RESET_INDICATOR,DSP1 resert indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x30 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x30 8.--11. "DSP2_LAST_RESET_INDICATOR,DSP2 resert indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x30 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x30 0.--3. "EVE_LAST_RESET_INDICATOR,EVE resert indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x34 "CTRL_CORE_SD_DAC_CONTROL,SD DAC control register" bitfld.long 0x34 31. "SD_DAC_CALSET," "0,1" newline hexmask.long.word 0x34 21.--30. 1. "SD_DAC_CAL,10-bit data for SD_DAC test or debug purposes" newline hexmask.long.word 0x34 6.--20. 1. "CTL,SD_DAC Control interface for reconfiguration of the module in functional mode through internal configuration registers" newline bitfld.long 0x34 5. "CTL_WR_ACK,Used only for synchronous mode of the CTL interface" "0,1" newline bitfld.long 0x34 4. "CTL_ASYNC_EN,Asynchronous mode enable for CTL interface" "Synchronous mode,Asynchronous mode" newline bitfld.long 0x34 3. "TVOUTBYPASS,TVOUT Bypass enable" "Normal mode,Bypass mode" newline bitfld.long 0x34 2. "ACEN,AC coupling enable" "DC coupling selected,AC coupling selected" newline rbitfld.long 0x34 0.--1. "RESERVED," "0,1,2,3" line.long 0x38 "CTRL_CORE_SD_DAC_TRIM_VALUE,SD DAC trim value" bitfld.long 0x38 31. "COMP_EN,Optional control for lower output swing" "High full-scale output swing,Low full-scale output swing" newline hexmask.long.byte 0x38 23.--30. 1. "RESERVED," newline hexmask.long.tbyte 0x38 0.--22. 1. "SD_DAC_TRIM,SD DAC trim value" line.long 0x3C "CTRL_CORE_ADC_ERROR_OFFSET,ADC Error offset register" hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x3C 0.--7. 1. "ERROR_OFFSET,Error offset value driven from efuse with optional override" line.long 0x40 "CTRL_CORE_IPU_WAKEUP,IPU wakeup enable" hexmask.long 0x40 1.--31. 1. "RESERVED," newline bitfld.long 0x40 0. "IPU_WKUP_EN,IPU wakeup enable" "0,1" line.long 0x44 "CTRL_CORE_ISS_EFUSE,ADC Error offset register" hexmask.long 0x44 7.--31. 1. "RESERVED," newline bitfld.long 0x44 6. "STD_FUSE_ISS_EFUSE1_EN,Error offset value driven from efuse with optional override" "0,1" newline bitfld.long 0x44 5. "STD_FUSE_ISS_EFUSE2_EN,Error offset value driven from efuse with optional override" "0,1" newline bitfld.long 0x44 4. "STD_FUSE_ISS_EFUSE3_EN,Error offset value driven from efuse with optional override" "0,1" newline bitfld.long 0x44 3. "STD_FUSE_ISS_EFUSE4_EN,Error offset value driven from efuse with optional override" "0,1" newline bitfld.long 0x44 2. "STD_FUSE_ISS_EFUSE5_EN,Error offset value driven from efuse with optional override" "0,1" newline bitfld.long 0x44 1. "STD_FUSE_ISS_EFUSE6_EN,Error offset value driven from efuse with optional override" "0,1" newline bitfld.long 0x44 0. "STD_FUSE_ISS_EFUSE7_EN,Error offset value driven from efuse with optional override" "0,1" line.long 0x48 "CTRL_CORE_SMA_SW_14,OCP Spare Register (SR1.0 Only)" bitfld.long 0x48 31. "MCASP_MODE_17_VOUT1_D22_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d22 not selected0x1: mcasp2_axr4 selected on pad vout1_d22 as function 17" "0,1" newline bitfld.long 0x48 30. "MCASP_MODE_17_VOUT1_D21_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d21 not selected0x1: mcasp2_axr3 selected on pad vout1_d21 as function 17" "0,1" newline bitfld.long 0x48 29. "MCASP_MODE_17_VOUT1_D20_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d20 not selected0x1: mcasp2_axr2 selected on pad vout1_d20 as function 17" "0,1" newline bitfld.long 0x48 28. "MCASP_MODE_17_VOUT1_D19_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d19 not selected0x1: mcasp2_axr1 selected on pad vout1_d19 as function 17" "0,1" newline bitfld.long 0x48 27. "MCASP_MODE_17_VOUT1_D18_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d18 not selected0x1: mcasp2_axr0 selected on pad vout1_d18 as function 17" "0,1" newline bitfld.long 0x48 26. "MCASP_MODE_17_VOUT1_D17_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d17 not selected0x1: mcasp2_fsr selected on pad vout1_d17 as function 17" "0,1" newline bitfld.long 0x48 25. "MCASP_MODE_17_VOUT1_D16_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d16 not selected0x1: This option is not supported and must not be used" "0,1" newline bitfld.long 0x48 24. "MCASP_MODE_17_VOUT1_D15_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d15 not selected0x1: mcasp2_fsx selected on pad vout1_d15 as function 17" "0,1" newline bitfld.long 0x48 23. "MCASP_MODE_17_VOUT1_D14_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d14 not selected0x1: mcasp2_aclkx selected on pad vout1_d14 as function 17" "0,1" newline bitfld.long 0x48 22. "MCASP_MODE_17_VOUT1_D13_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vout1_d13 not selected0x1: mcasp2_aclkr selected on pad vout1_d13 as function 17" "0,1" newline bitfld.long 0x48 21. "MCASP_MODE_17_GPMC_AD7_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad7 not selected0x1: mcasp2_ahclkx selected on pad gpmc_ad7 as function 17" "0,1" newline bitfld.long 0x48 20. "MCASP_MODE_17_VIN1A_D5_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_d5 not selected0x1: mcasp3_ahclkx selected on pad vin1a_d5 as function 17" "0,1" newline bitfld.long 0x48 19. "MCASP_MODE_17_VIN1A_D4_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_d4 not selected0x1: mcasp3_axr5 selected on pad vin1a_d4 as function 17" "0,1" newline bitfld.long 0x48 18. "MCASP_MODE_17_VIN1A_D3_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_d3 not selected0x1: mcasp3_axr4 selected on pad vin1a_d3 as function 17" "0,1" newline bitfld.long 0x48 17. "MCASP_MODE_17_VIN1A_D2_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_d2 not selected0x1: mcasp3_axr3 selected on pad vin1a_d2 as function 17" "0,1" newline bitfld.long 0x48 16. "MCASP_MODE_17_VIN1A_D1_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_d1 not selected0x1: mcasp3_axr2 selected on pad vin1a_d1 as function 17" "0,1" newline bitfld.long 0x48 15. "MCASP_MODE_17_VIN1A_D0_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_d0 not selected0x1: mcasp3_axr1 selected on pad vin1a_d0 as function 17" "0,1" newline bitfld.long 0x48 14. "MCASP_MODE_17_VIN1A_VSYNC0_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_vsync0 not selected0x1: mcasp3_axr0 selected on pad vin1a_vsync0 as function 17" "0,1" newline bitfld.long 0x48 13. "MCASP_MODE_17_VIN1A_HSYNC0_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_hsync0 not selected0x1: mcasp3_fsr selected on pad vin1a_hsync0 as function 17" "0,1" newline bitfld.long 0x48 12. "MCASP_MODE_17_VIN1A_FLD0_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_fld0 not selected0x1: mcasp3_aclkr selected on pad vin1a_fld0 as function 17" "0,1" newline bitfld.long 0x48 11. "MCASP_MODE_17_VIN1A_DE0_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_de0 not selected0x1: This option is not supported and must not be used" "0,1" newline bitfld.long 0x48 10. "MCASP_MODE_17_VIN1A_CLK0_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad vin1a_clk0 not selected0x1: mcasp3_aclkx selected on pad vin1a_clk0 as function 17" "0,1" newline bitfld.long 0x48 9. "MCASP_MODE_17_GPMC_AD15_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad15 not selected0x1: mcasp2_axr5 selected on pad gpmc_ad15 as function 17" "0,1" newline bitfld.long 0x48 8. "MCASP_MODE_17_GPMC_AD14_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad14 not selected0x1: mcasp2_axr4 selected on pad gpmc_ad14 as function 17" "0,1" newline bitfld.long 0x48 7. "MCASP_MODE_17_GPMC_AD13_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad13 not selected0x1: mcasp2_axr3 selected on pad gpmc_ad13 as function 17" "0,1" newline bitfld.long 0x48 6. "MCASP_MODE_17_GPMC_AD12_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad12 not selected0x1: mcasp2_axr2 selected on pad gpmc_ad12 as function 17" "0,1" newline bitfld.long 0x48 5. "MCASP_MODE_17_GPMC_AD11_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad11 not selected0x1: mcasp2_axr1 selected on pad gpmc_ad11 as function 17" "0,1" newline bitfld.long 0x48 4. "MCASP_MODE_17_GPMC_AD10_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad10 not selected0x1: mcasp2_axr0 selected on pad gpmc_ad10 as function 17" "0,1" newline bitfld.long 0x48 3. "MCASP_MODE_17_GPMC_AD9_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad9 not selected0x1: mcasp2_fsr selected on pad gpmc_ad9 as function 17" "0,1" newline bitfld.long 0x48 2. "MCASP_MODE_17_GPMC_AD8_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad8 not selected0x1: mcasp2_aclkr selected on pad gpmc_ad8 as function 17" "0,1" newline bitfld.long 0x48 1. "MCASP_MODE_17_GPMC_AD6_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad6 not selected0x1: mcasp2_fsx selected on pad gpmc_ad6 as function 17" "0,1" newline bitfld.long 0x48 0. "MCASP_MODE_17_GPMC_AD5_MUX_CONTROL_0,SR2.0 Only:0x0: Function 17 for pad gpmc_ad5 not selected0x1: mcasp2_aclkx selected on pad gpmc_ad5 as function 17" "0,1" line.long 0x4C "CTRL_CORE_SMA_SW_15,OCP Spare Register (SR1.0 Only)" hexmask.long 0x4C 3.--31. 1. "SMA_SW_15,OCP Spare Bits" newline bitfld.long 0x4C 2. "MCASP_MODE_17_VOUT1_D12_MUX_CONTROL_1,SR2.0 Only:0x0: Function 17 for pad vout1_d12 not selected0x1: mcasp2_ahclkx selected on pad vout1_d12 as function 17" "0,1" newline bitfld.long 0x4C 1. "MCASP_MODE_17_VIN1A_D6_MUX_CONTROL_1,SR2.0 Only:0x0: Function 17 for pad vin1a_d6 not selected0x1: mcasp3_fsx selected on pad vin1a_d6 as function 17" "0,1" newline bitfld.long 0x4C 0. "MCASP_MODE_17_VOUT1_D23_MUX_CONTROL_1,SR2.0 Only:0x0: Function 17 for pad vout1_d23 not selected0x1: mcasp2_axr5 selected on pad vout1_d23 as function 17" "0,1" line.long 0x50 "CTRL_CORE_SMA_SW_16,OCP Spare Register (SR1.0 Only)" hexmask.long 0x50 1.--31. 1. "SMA_SW_16,OCP Spare Register" newline bitfld.long 0x50 0. "CORE_DPLL_INPUT_CLK_SELECTION,SR2.0 Only:DPLL_CORE input clock selection.0x0: SYS_CLK1 selected as input clock (REF_CLK) for" "0,1" line.long 0x54 "CTRL_CORE_SMA_SW_17,OCP Spare Register (SR1.0 Only)" hexmask.long.tbyte 0x54 12.--31. 1. "SMA_SW_17,OCP Spare Bits" newline rbitfld.long 0x54 11. "MCAN_CLK_HSDIV_CHANGE_ACK,SR2.0 Only:Acknowledge flag which indicates that the on-the-fly change of H14 divider of DPLL_GMAC_DSP is done" "0,1" newline rbitfld.long 0x54 10. "MCAN_CLK_HSDIV_EN_ACK,SR2.0 Only:Indicates whether CLKOUTX2_H14 of DPLL_GMAC_DSP is enabled or not.0x0: CLKOUTX2_H14 is" "0,1" newline bitfld.long 0x54 9. "MCAN_CLK_TENABLEDIV_SEL,SR2.0 Only:TENABLEDIV control select for H14 of" "0,1" newline bitfld.long 0x54 8. "RESERVED,Reserved" "0,1" newline bitfld.long 0x54 7. "MCAN_CLK_HSDIV_EN,SR2.0 Only:Output clock (CLKOUTX2_H14) enable for H14 of" "0,1" newline bitfld.long 0x54 6. "MCAN_CLK_HSDIV_LATCH_EN,SR2.0 Only:To be toggled (LO->HI->LO) to latch MCAN_CLK_HSDIV value in H14 of DPLL_GMAC_DSP" "0,1" newline bitfld.long 0x54 0.--5. "MCAN_CLK_HSDIV,SR2.0 Only:Divider value for H14 of DPLL_GMAC_DSP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x58 "CTRL_CORE_ROM_CPU0_BRANCH," line.long 0x5C "CTRL_CORE_ROM_CPU1_BRANCH," rgroup.long 0x1CB0++0x27 line.long 0x00 "CTRL_CORE_SMA_SW_18,OCP Spare Register" line.long 0x04 "CTRL_CORE_SMA_SW_19,OCP Spare Register" line.long 0x08 "CTRL_CORE_SMA_SW_20,OCP Spare Register" line.long 0x0C "CTRL_CORE_SMA_SW_21,OCP Spare Register" line.long 0x10 "CTRL_CORE_SMA_SW_22,OCP Spare Register (SR1.0 Only)" hexmask.long.word 0x10 18.--31. 1. "SMA_SW_22,OCP Spare Register" newline hexmask.long.tbyte 0x10 0.--17. 1. "CORE_DPLL_REGMF_CONTROL,SR2.0 Only:Fractional part of the software-configured multiplication ratio M of DPLL_CORE" line.long 0x14 "CTRL_CORE_SMA_SW_23,OCP Spare Register" line.long 0x18 "CTRL_CORE_SMA_SW_24,OCP Spare Register" line.long 0x1C "CTRL_CORE_SMA_SW_25,OCP Spare Register" line.long 0x20 "CTRL_CORE_SMA_SW_26,OCP Spare Register" line.long 0x24 "CTRL_CORE_SMA_SW_27,OCP Spare Register" repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x1CA8)++0x03 line.long 0x00 "CTRL_CORE_ROM_AUXBOOT$1," repeat.end width 0x0B tree.end tree "CTRL_MODULE_CORE_TARG" base ad:0x4A004000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CTRL_MODULE_WKUP" base ad:0x4AE0C000 group.long 0x100++0x03 line.long 0x00 "CTRL_WKUP_SEC_CTRL,Control Register" bitfld.long 0x00 31. "SECCTRLWRDISABLE,Control Register write disable control" "Write in this register is allowed,Write in this register is forbidden" newline hexmask.long 0x00 5.--30. 1. "RESERVED," newline bitfld.long 0x00 4. "SECURE_EMIF_CONFIG_RO_EN,Access mode for registers: CTRL_WKUP_EMIF1_SDRAM_CONFIG CTRL_WKUP_EMIF2_SDRAM_CONFIG" "These registers are RW,These registers are RO" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x108++0x0B line.long 0x00 "CTRL_WKUP_SEC_TAP,TAP controllers register" bitfld.long 0x00 31. "SECTAPWR_DISABLE,TAP controllers register write disable control" "0,1" newline rbitfld.long 0x00 27.--30. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 26. "RESERVED,Reserved" "0,1" newline hexmask.long.word 0x00 13.--25. 1. "RESERVED," newline bitfld.long 0x00 12. "DSP2_TAPENABLE,DSP2 TAP control" "DSP2_TAPENABLE_0,DSP2_TAPENABLE_1" newline bitfld.long 0x00 11. "JTAGEXT_TAPENABLE,External JTAG expansion TAP control" "JTAGEXT_TAPENABLE_0,JTAGEXT_TAPENABLE_1" newline rbitfld.long 0x00 5.--10. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 4. "IEEE1500_ENABLE,IEEE1500 and P1500 access enable" "0,1" newline bitfld.long 0x00 3. "P1500_ENABLE,P1500 access enable" "P1500_ENABLE_0,P1500_ENABLE_1" newline bitfld.long 0x00 2. "IPU1_TAPENABLE,IPU1 TAP control" "IPU1_TAPENABLE_0,IPU1_TAPENABLE_1" newline bitfld.long 0x00 1. "DSP1_TAPENABLE,DSP1 TAP control" "DSP1_TAPENABLE_0,DSP1_TAPENABLE_1" newline bitfld.long 0x00 0. "DAP_TAPENABLE,DAP TAP control" "DAP_TAPENABLE_0,DAP_TAPENABLE_1" line.long 0x04 "CTRL_WKUP_OCPREG_SPARE,OCP Spare Register" bitfld.long 0x04 31. "OCPREG_SPARE31,OCP spare register 31" "0,1" newline bitfld.long 0x04 30. "OCPREG_SPARE30,OCP spare register 30" "0,1" newline bitfld.long 0x04 29. "OCPREG_SPARE29,OCP spare register 29" "0,1" newline bitfld.long 0x04 28. "OCPREG_SPARE28,OCP spare register 28" "0,1" newline bitfld.long 0x04 27. "OCPREG_SPARE27,OCP spare register 27" "0,1" newline bitfld.long 0x04 26. "OCPREG_SPARE26,OCP spare register 26" "0,1" newline bitfld.long 0x04 25. "OCPREG_SPARE25,OCP spare register 25" "0,1" newline bitfld.long 0x04 24. "OCPREG_SPARE24,OCP spare register 24" "0,1" newline bitfld.long 0x04 23. "OCPREG_SPARE23,OCP spare register 23" "0,1" newline bitfld.long 0x04 22. "OCPREG_SPARE22,OCP spare register 22" "0,1" newline bitfld.long 0x04 21. "OCPREG_SPARE21,OCP spare register 21" "0,1" newline bitfld.long 0x04 20. "OCPREG_SPARE20,OCP spare register 20" "0,1" newline bitfld.long 0x04 19. "OCPREG_SPARE19,OCP spare register 19" "0,1" newline bitfld.long 0x04 18. "OCPREG_SPARE18,OCP spare register 18" "0,1" newline bitfld.long 0x04 17. "OCPREG_SPARE17,OCP spare register 17" "0,1" newline bitfld.long 0x04 16. "OCPREG_SPARE16,OCP spare register 16" "0,1" newline bitfld.long 0x04 15. "OCPREG_SPARE15,OCP spare register 15" "0,1" newline bitfld.long 0x04 14. "OCPREG_SPARE14,OCP spare register 14" "0,1" newline bitfld.long 0x04 13. "OCPREG_SPARE13,OCP spare register 13" "0,1" newline bitfld.long 0x04 12. "OCPREG_SPARE12,OCP spare register 12" "0,1" newline bitfld.long 0x04 11. "OCPREG_SPARE11,OCP spare register 11" "0,1" newline bitfld.long 0x04 10. "OCPREG_SPARE10,OCP spare register 10" "0,1" newline bitfld.long 0x04 9. "OCPREG_SPARE9,OCP spare register 9" "0,1" newline bitfld.long 0x04 8. "OCPREG_SPARE8,OCP spare register 8" "0,1" newline bitfld.long 0x04 7. "OCPREG_SPARE7,OCP spare register 7" "0,1" newline bitfld.long 0x04 6. "OCPREG_SPARE6,OCP spare register 6" "0,1" newline bitfld.long 0x04 5. "OCPREG_SPARE5,OCP spare register 5" "0,1" newline bitfld.long 0x04 4. "OCPREG_SPARE4,OCP spare register 4" "0,1" newline bitfld.long 0x04 3. "OCPREG_SPARE3,OCP spare register 3" "0,1" newline bitfld.long 0x04 2. "OCPREG_SPARE2,OCP spare register 2" "0,1" newline bitfld.long 0x04 1. "OCPREG_SPARE1,OCP spare register 1" "0,1" newline rbitfld.long 0x04 0. "RESERVED," "0,1" line.long 0x08 "CTRL_WKUP_SECURE_EMIF1_SDRAM_CONFIG,EMIF1 SDRAM configuration register" rbitfld.long 0x08 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 27.--28. "EMIF1_SDRAM_IBANK_POS,Internal bank position" "0,1,2,3" newline bitfld.long 0x08 24.--26. "EMIF1_SDRAM_DDR_TERM,DDR2 and DDR3 termination resistor value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 23. "EMIF1_SDRAM_DDR2_DDQS,DDR2 differential DQS enable" "0,1" newline bitfld.long 0x08 21.--22. "EMIF1_SDRAM_DYN_ODT,DDR3 Dynamic ODT" "0,1,2,3" newline bitfld.long 0x08 20. "EMIF1_SDRAM_DDR_DISABLE_DLL,Disable DLL select" "0,1" newline bitfld.long 0x08 18.--19. "EMIF1_SDRAM_DRIVE,SDRAM drive strength" "0,1,2,3" newline bitfld.long 0x08 16.--17. "EMIF1_SDRAM_CWL,DDR3 CAS Write latency" "0,1,2,3" newline rbitfld.long 0x08 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 10.--13. "EMIF1_SDRAM_CL,CAS Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 7.--9. "EMIF1_SDRAM_ROWSIZE,Row Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 4.--6. "EMIF1_SDRAM_IBANK,Internal Bank setup" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 0.--2. "EMIF1_SDRAM_PAGESIZE,Page Size" "0,1,2,3,4,5,6,7" rgroup.long 0x13C++0x03 line.long 0x00 "CTRL_WKUP_STD_FUSE_CONF,Standard Fuse conf [63:32]" hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline bitfld.long 0x00 19. "STD_FUSE_EMIF1_INITREF_DEF_DIS,Disable EMIF1 DDR refresh and initialization sequence" "refresh and initialization sequence is enabled,refresh and initialization sequence is disabled" newline bitfld.long 0x00 18. "STD_FUSE_EMIF1_DDR3_LPDDR2N,EMIF1 DDR3" "LPDDR2 configured,DDR3 configured" newline bitfld.long 0x00 13.--17. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. "STD_FUSE_CH_SPEEDUP_DISABLE,ROM code settings for configuration header block and speedup block" "enables CH and speedup,disables CH and speedup" newline hexmask.long.word 0x00 0.--11. 1. "RESERVED," group.long 0x144++0x03 line.long 0x00 "CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT,SLICE register for emif1 and emif2" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 17. "EMIF1_NARROW_ONLY,EMIF1 operates in narrow mode to allow for data macros to be powered down to save power" "narrow mode disabled,narrow mode enabled" newline bitfld.long 0x00 16. "EMIF1_EN_ECC,EMIF1 ECC enable" "ECC is disabled,ECC is enabled" newline bitfld.long 0x00 14.--15. "EMIF1_REG_PHY_NUM_OF_SAMPLES,Controls the number of DQ samples required for read leveling" "4 samples,8 samples,16 samples,128 samples" newline bitfld.long 0x00 13. "EMIF1_REG_PHY_SEL_LOGIC,Selects an algorithm for read leveling" "Algorithm 1 is used,Algorithm 2 is used" newline bitfld.long 0x00 12. "EMIF1_REG_PHY_ALL_DQ_MPR_RD_RESP,Analysis method of DQ bits during read leveling" "if the DRAM provides a read response on only one..,if the DRAM provides a read response on all DQ.." newline bitfld.long 0x00 9.--11. "EMIF1_REG_PHY_OUTPUT_STATUS_SELECT,Selects the status to be observed on the outputs of the DDR PHYs through" "selects phy_reg_rdlvl_start_ratio[7:0],selects phy_reg_rdlvl_start_ratio[15:8],selects phy_reg_rdlvl_end_ratio[7:0],selects phy_reg_rdlvl_end_ratio[15:8],?..." newline rbitfld.long 0x00 8. "RESERVED," "0,1" newline bitfld.long 0x00 7. "EMIF1_SDRAM_DISABLE_RESET,DDR3 SDRAM reset disable" "DDR3 SDRAM reset signal is enabled,DDR3 SDRAM reset signal is disabled" newline bitfld.long 0x00 5.--6. "EMIF1_PHY_RD_LOCAL_ODT,Control of ODT (on - die termination) settings for the device DDR I/Os" "ODT disabled,60 Ohms,80 Ohms 0x3 =120 Ohms,?..." newline bitfld.long 0x00 4. "RESERVED," "0,1" newline bitfld.long 0x00 3. "EMIF1_DFI_CLOCK_PHASE_CTRL,EMIF_FICLK clock phase control (shifting by 180)" "0,1" newline bitfld.long 0x00 2. "EMIF1_EN_SLICE_2,Enable command PHY 2" "0,1" newline bitfld.long 0x00 1. "EMIF1_EN_SLICE_1,Enable command PHY 1" "0,1" newline bitfld.long 0x00 0. "EMIF1_EN_SLICE_0,Enable command PHY 0" "0,1" rgroup.long 0x14C++0x03 line.long 0x00 "CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT_1," group.long 0x164++0x03 line.long 0x00 "CTRL_WKUP_LDOSRAM_CORE_VOLTAGE_CTRL,Core SRAM LDO Control register" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 26. "LDOSRAMCORE_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value" "LDOSRAMCORE_RETMODE_MUX_CTRL_0,LDOSRAMCORE_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x00 21.--25. "LDOSRAMCORE_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "LDOSRAMCORE_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10. "LDOSRAMCORE_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value" "LDOSRAMCORE_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x00 5.--9. "LDOSRAMCORE_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "LDOSRAMCORE_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x200++0x17 line.long 0x00 "CTRL_WKUP_STD_FUSE_DIE_ID_0,Die ID Register : Part 0" line.long 0x04 "CTRL_WKUP_ID_CODE,ID_CODE Key Register" line.long 0x08 "CTRL_WKUP_STD_FUSE_DIE_ID_1,Die ID Register : Part 1" line.long 0x0C "CTRL_WKUP_STD_FUSE_DIE_ID_2,Die ID Register : Part 2" line.long 0x10 "CTRL_WKUP_STD_FUSE_DIE_ID_3,Die ID Register : Part 3" line.long 0x14 "CTRL_WKUP_STD_FUSE_PROD_ID_0,Prod ID Register : Part 0" group.long 0x5AC++0x03 line.long 0x00 "CTRL_WKUP_CONTROL_XTAL_OSCILLATOR,XTAL OSCILLATOR control" bitfld.long 0x00 31. "OSCILLATOR0_BOOST,Fast startup control of OSC0" "Fast startup is disabled,Fast startup is enabled" newline bitfld.long 0x00 30. "OSCILLATOR0_OS_OUT,Oscillator output of OSC0" "low to high transition in BOOST mode,BOOST is disabled" newline bitfld.long 0x00 29. "OSCILLATOR1_BOOST,Fast startup control of OSC1" "Fast startup is disabled,Fast startup is enabled" newline bitfld.long 0x00 28. "OSCILLATOR1_OS_OUT,Oscillator output of OSC1" "low to high transition in BOOST mode,BOOST is disabled" newline hexmask.long 0x00 0.--27. 1. "RESERVED," group.long 0x5C8++0x0F line.long 0x00 "CTRL_WKUP_EFUSE_1,EFUSE compensation 1" bitfld.long 0x00 31. "DDRDIFF_PTV_NORTH_SIDE_N5," "0,1" newline bitfld.long 0x00 30. "DDRDIFF_PTV_NORTH_SIDE_N4," "0,1" newline bitfld.long 0x00 29. "DDRDIFF_PTV_NORTH_SIDE_N3," "0,1" newline bitfld.long 0x00 28. "DDRDIFF_PTV_NORTH_SIDE_N2," "0,1" newline bitfld.long 0x00 27. "DDRDIFF_PTV_NORTH_SIDE_N1," "0,1" newline bitfld.long 0x00 26. "DDRDIFF_PTV_NORTH_SIDE_N0," "0,1" newline bitfld.long 0x00 25. "DDRDIFF_PTV_NORTH_SIDE_P5," "0,1" newline bitfld.long 0x00 24. "DDRDIFF_PTV_NORTH_SIDE_P4," "0,1" newline bitfld.long 0x00 23. "DDRDIFF_PTV_NORTH_SIDE_P3," "0,1" newline bitfld.long 0x00 22. "DDRDIFF_PTV_NORTH_SIDE_P2," "0,1" newline bitfld.long 0x00 21. "DDRDIFF_PTV_NORTH_SIDE_P1," "0,1" newline bitfld.long 0x00 20. "DDRDIFF_PTV_NORTH_SIDE_P0," "0,1" newline bitfld.long 0x00 19. "DDRDIFF_PTV_EAST_SIDE_N5," "0,1" newline bitfld.long 0x00 18. "DDRDIFF_PTV_EAST_SIDE_N4," "0,1" newline bitfld.long 0x00 17. "DDRDIFF_PTV_EAST_SIDE_N3," "0,1" newline bitfld.long 0x00 16. "DDRDIFF_PTV_EAST_SIDE_N2," "0,1" newline bitfld.long 0x00 15. "DDRDIFF_PTV_EAST_SIDE_N1," "0,1" newline bitfld.long 0x00 14. "DDRDIFF_PTV_EAST_SIDE_N0," "0,1" newline bitfld.long 0x00 13. "DDRDIFF_PTV_EAST_SIDE_P5," "0,1" newline bitfld.long 0x00 12. "DDRDIFF_PTV_EAST_SIDE_P4," "0,1" newline bitfld.long 0x00 11. "DDRDIFF_PTV_EAST_SIDE_P3," "0,1" newline bitfld.long 0x00 10. "DDRDIFF_PTV_EAST_SIDE_P2," "0,1" newline bitfld.long 0x00 9. "DDRDIFF_PTV_EAST_SIDE_P1," "0,1" newline bitfld.long 0x00 8. "DDRDIFF_PTV_EAST_SIDE_P0," "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," line.long 0x04 "CTRL_WKUP_EFUSE_2,EFUSE compensation 2" bitfld.long 0x04 31. "DDRDIFF_PTV_SOUTH_SIDE_N5," "0,1" newline bitfld.long 0x04 30. "DDRDIFF_PTV_SOUTH_SIDE_N4," "0,1" newline bitfld.long 0x04 29. "DDRDIFF_PTV_SOUTH_SIDE_N3," "0,1" newline bitfld.long 0x04 28. "DDRDIFF_PTV_SOUTH_SIDE_N2," "0,1" newline bitfld.long 0x04 27. "DDRDIFF_PTV_SOUTH_SIDE_N1," "0,1" newline bitfld.long 0x04 26. "DDRDIFF_PTV_SOUTH_SIDE_N0," "0,1" newline bitfld.long 0x04 25. "DDRDIFF_PTV_SOUTH_SIDE_P5," "0,1" newline bitfld.long 0x04 24. "DDRDIFF_PTV_SOUTH_SIDE_P4," "0,1" newline bitfld.long 0x04 23. "DDRDIFF_PTV_SOUTH_SIDE_P3," "0,1" newline bitfld.long 0x04 22. "DDRDIFF_PTV_SOUTH_SIDE_P2," "0,1" newline bitfld.long 0x04 21. "DDRDIFF_PTV_SOUTH_SIDE_P1," "0,1" newline bitfld.long 0x04 20. "DDRDIFF_PTV_SOUTH_SIDE_P0," "0,1" newline bitfld.long 0x04 19. "DDRDIFF_PTV_WEST_SIDE_N5," "0,1" newline bitfld.long 0x04 18. "DDRDIFF_PTV_WEST_SIDE_N4," "0,1" newline bitfld.long 0x04 17. "DDRDIFF_PTV_WEST_SIDE_N3," "0,1" newline bitfld.long 0x04 16. "DDRDIFF_PTV_WEST_SIDE_N2," "0,1" newline bitfld.long 0x04 15. "DDRDIFF_PTV_WEST_SIDE_N1," "0,1" newline bitfld.long 0x04 14. "DDRDIFF_PTV_WEST_SIDE_N0," "0,1" newline bitfld.long 0x04 13. "DDRDIFF_PTV_WEST_SIDE_P5," "0,1" newline bitfld.long 0x04 12. "DDRDIFF_PTV_WEST_SIDE_P4," "0,1" newline bitfld.long 0x04 11. "DDRDIFF_PTV_WEST_SIDE_P3," "0,1" newline bitfld.long 0x04 10. "DDRDIFF_PTV_WEST_SIDE_P2," "0,1" newline bitfld.long 0x04 9. "DDRDIFF_PTV_WEST_SIDE_P1," "0,1" newline bitfld.long 0x04 8. "DDRDIFF_PTV_WEST_SIDE_P0," "0,1" newline hexmask.long.byte 0x04 0.--7. 1. "RESERVED," line.long 0x08 "CTRL_WKUP_EFUSE_3,EFUSE compensation 3" bitfld.long 0x08 31. "DDRSE_PTV_NORTH_SIDE_N5," "0,1" newline bitfld.long 0x08 30. "DDRSE_PTV_NORTH_SIDE_N4," "0,1" newline bitfld.long 0x08 29. "DDRSE_PTV_NORTH_SIDE_N3," "0,1" newline bitfld.long 0x08 28. "DDRSE_PTV_NORTH_SIDE_N2," "0,1" newline bitfld.long 0x08 27. "DDRSE_PTV_NORTH_SIDE_N1," "0,1" newline bitfld.long 0x08 26. "DDRSE_PTV_NORTH_SIDE_N0," "0,1" newline bitfld.long 0x08 25. "DDRSE_PTV_NORTH_SIDE_P5," "0,1" newline bitfld.long 0x08 24. "DDRSE_PTV_NORTH_SIDE_P4," "0,1" newline bitfld.long 0x08 23. "DDRSE_PTV_NORTH_SIDE_P3," "0,1" newline bitfld.long 0x08 22. "DDRSE_PTV_NORTH_SIDE_P2," "0,1" newline bitfld.long 0x08 21. "DDRSE_PTV_NORTH_SIDE_P1," "0,1" newline bitfld.long 0x08 20. "DDRSE_PTV_NORTH_SIDE_P0," "0,1" newline bitfld.long 0x08 19. "DDRSE_PTV_EAST_SIDE_N5," "0,1" newline bitfld.long 0x08 18. "DDRSE_PTV_EAST_SIDE_N4," "0,1" newline bitfld.long 0x08 17. "DDRSE_PTV_EAST_SIDE_N3," "0,1" newline bitfld.long 0x08 16. "DDRSE_PTV_EAST_SIDE_N2," "0,1" newline bitfld.long 0x08 15. "DDRSE_PTV_EAST_SIDE_N1," "0,1" newline bitfld.long 0x08 14. "DDRSE_PTV_EAST_SIDE_N0," "0,1" newline bitfld.long 0x08 13. "DDRSE_PTV_EAST_SIDE_P5," "0,1" newline bitfld.long 0x08 12. "DDRSE_PTV_EAST_SIDE_P4," "0,1" newline bitfld.long 0x08 11. "DDRSE_PTV_EAST_SIDE_P3," "0,1" newline bitfld.long 0x08 10. "DDRSE_PTV_EAST_SIDE_P2," "0,1" newline bitfld.long 0x08 9. "DDRSE_PTV_EAST_SIDE_P1," "0,1" newline bitfld.long 0x08 8. "DDRSE_PTV_EAST_SIDE_P0," "0,1" newline hexmask.long.byte 0x08 0.--7. 1. "RESERVED," line.long 0x0C "CTRL_WKUP_EFUSE_4,EFUSE compensation 4" bitfld.long 0x0C 31. "DDRSE_PTV_SOUTH_SIDE_N5," "0,1" newline bitfld.long 0x0C 30. "DDRSE_PTV_SOUTH_SIDE_N4," "0,1" newline bitfld.long 0x0C 29. "DDRSE_PTV_SOUTH_SIDE_N3," "0,1" newline bitfld.long 0x0C 28. "DDRSE_PTV_SOUTH_SIDE_N2," "0,1" newline bitfld.long 0x0C 27. "DDRSE_PTV_SOUTH_SIDE_N1," "0,1" newline bitfld.long 0x0C 26. "DDRSE_PTV_SOUTH_SIDE_N0," "0,1" newline bitfld.long 0x0C 25. "DDRSE_PTV_SOUTH_SIDE_P5," "0,1" newline bitfld.long 0x0C 24. "DDRSE_PTV_SOUTH_SIDE_P4," "0,1" newline bitfld.long 0x0C 23. "DDRSE_PTV_SOUTH_SIDE_P3," "0,1" newline bitfld.long 0x0C 22. "DDRSE_PTV_SOUTH_SIDE_P2," "0,1" newline bitfld.long 0x0C 21. "DDRSE_PTV_SOUTH_SIDE_P1," "0,1" newline bitfld.long 0x0C 20. "DDRSE_PTV_SOUTH_SIDE_P0," "0,1" newline bitfld.long 0x0C 19. "DDRSE_PTV_WEST_SIDE_N5," "0,1" newline bitfld.long 0x0C 18. "DDRSE_PTV_WEST_SIDE_N4," "0,1" newline bitfld.long 0x0C 17. "DDRSE_PTV_WEST_SIDE_N3," "0,1" newline bitfld.long 0x0C 16. "DDRSE_PTV_WEST_SIDE_N2," "0,1" newline bitfld.long 0x0C 15. "DDRSE_PTV_WEST_SIDE_N1," "0,1" newline bitfld.long 0x0C 14. "DDRSE_PTV_WEST_SIDE_N0," "0,1" newline bitfld.long 0x0C 13. "DDRSE_PTV_WEST_SIDE_P5," "0,1" newline bitfld.long 0x0C 12. "DDRSE_PTV_WEST_SIDE_P4," "0,1" newline bitfld.long 0x0C 11. "DDRSE_PTV_WEST_SIDE_P3," "0,1" newline bitfld.long 0x0C 10. "DDRSE_PTV_WEST_SIDE_P2," "0,1" newline bitfld.long 0x0C 9. "DDRSE_PTV_WEST_SIDE_P1," "0,1" newline bitfld.long 0x0C 8. "DDRSE_PTV_WEST_SIDE_P0," "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED," group.long 0x5F8++0x03 line.long 0x00 "CTRL_WKUP_EFUSE_13," bitfld.long 0x00 31. "SDIO1833_PTV_N5," "0,1" newline bitfld.long 0x00 30. "SDIO1833_PTV_N4," "0,1" newline bitfld.long 0x00 29. "SDIO1833_PTV_N3," "0,1" newline bitfld.long 0x00 28. "SDIO1833_PTV_N2," "0,1" newline bitfld.long 0x00 27. "SDIO1833_PTV_N1," "0,1" newline bitfld.long 0x00 26. "SDIO1833_PTV_N0," "0,1" newline bitfld.long 0x00 25. "SDIO1833_PTV_P5," "0,1" newline bitfld.long 0x00 24. "SDIO1833_PTV_P4," "0,1" newline bitfld.long 0x00 23. "SDIO1833_PTV_P3," "0,1" newline bitfld.long 0x00 22. "SDIO1833_PTV_P2," "0,1" newline bitfld.long 0x00 21. "SDIO1833_PTV_P1," "0,1" newline bitfld.long 0x00 20. "SDIO1833_PTV_P0," "0,1" newline hexmask.long.tbyte 0x00 0.--19. 1. "RESERVED," group.long 0x700++0x7F line.long 0x00 "CTRL_WKUP_CONF_DEBUG_SEL_TST_0,This register is used to select an observable signal for WKUP observability line 0" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "MODE,Selects one of the following signals to be available on WKUP observability line 0" "MODE_0,MODE_1" line.long 0x04 "CTRL_WKUP_CONF_DEBUG_SEL_TST_1,This register is used to select an observable signal for WKUP observability line 1" hexmask.long 0x04 1.--31. 1. "RESERVED," newline bitfld.long 0x04 0. "MODE,Selects one of the following signals to be available on WKUP observability line 1" "MODE_0,MODE_1" line.long 0x08 "CTRL_WKUP_CONF_DEBUG_SEL_TST_2,This register is used to select an observable signal for WKUP observability line 2" hexmask.long 0x08 1.--31. 1. "RESERVED," newline bitfld.long 0x08 0. "MODE,Selects one of the following signals to be available on WKUP observability line 2" "MODE_0,MODE_1" line.long 0x0C "CTRL_WKUP_CONF_DEBUG_SEL_TST_3,This register is used to select an observable signal for WKUP observability line 3" hexmask.long 0x0C 1.--31. 1. "RESERVED," newline bitfld.long 0x0C 0. "MODE,Selects one of the following signals to be available on WKUP observability line 3" "MODE_0,MODE_1" line.long 0x10 "CTRL_WKUP_CONF_DEBUG_SEL_TST_4,This register is used to select an observable signal for WKUP observability line 4" hexmask.long 0x10 1.--31. 1. "RESERVED," newline bitfld.long 0x10 0. "MODE,Selects one of the following signals to be available on WKUP observability line 4" "MODE_0,MODE_1" line.long 0x14 "CTRL_WKUP_CONF_DEBUG_SEL_TST_5,This register is used to select an observable signal for WKUP observability line 5" hexmask.long 0x14 1.--31. 1. "RESERVED," newline bitfld.long 0x14 0. "MODE,Selects one of the following signals to be available on WKUP observability line 5" "MODE_0,MODE_1" line.long 0x18 "CTRL_WKUP_CONF_DEBUG_SEL_TST_6,This register is used to select an observable signal for WKUP observability line 6" hexmask.long 0x18 1.--31. 1. "RESERVED," newline bitfld.long 0x18 0. "MODE,Selects one of the following signals to be available on WKUP observability line 6" "MODE_0,MODE_1" line.long 0x1C "CTRL_WKUP_CONF_DEBUG_SEL_TST_7,This register is used to select an observable signal for WKUP observability line 7" hexmask.long 0x1C 1.--31. 1. "RESERVED," newline bitfld.long 0x1C 0. "MODE,Selects one of the following signals to be available on WKUP observability line 7" "MODE_0,MODE_1" line.long 0x20 "CTRL_WKUP_CONF_DEBUG_SEL_TST_8,This register is used to select an observable signal for WKUP observability line 8" hexmask.long 0x20 1.--31. 1. "RESERVED," newline bitfld.long 0x20 0. "MODE,Selects one of the following signals to be available on WKUP observability line 8" "MODE_0,MODE_1" line.long 0x24 "CTRL_WKUP_CONF_DEBUG_SEL_TST_9,This register is used to select an observable signal for WKUP observability line 9" hexmask.long 0x24 1.--31. 1. "RESERVED," newline bitfld.long 0x24 0. "MODE,Selects one of the following signals to be available on WKUP observability line 9" "MODE_0,MODE_1" line.long 0x28 "CTRL_WKUP_CONF_DEBUG_SEL_TST_10,This register is used to select an observable signal for WKUP observability line 10" hexmask.long 0x28 1.--31. 1. "RESERVED," newline bitfld.long 0x28 0. "MODE,Selects one of the following signals to be available on WKUP observability line 10" "MODE_0,MODE_1" line.long 0x2C "CTRL_WKUP_CONF_DEBUG_SEL_TST_11,This register is used to select an observable signal for WKUP observability line 11" hexmask.long 0x2C 1.--31. 1. "RESERVED," newline bitfld.long 0x2C 0. "MODE,Selects one of the following signals to be available on WKUP observability line 11" "MODE_0,MODE_1" line.long 0x30 "CTRL_WKUP_CONF_DEBUG_SEL_TST_12,This register is used to select an observable signal for WKUP observability line 12" hexmask.long 0x30 1.--31. 1. "RESERVED," newline bitfld.long 0x30 0. "MODE,Selects one of the following signals to be available on WKUP observability line 12" "MODE_0,MODE_1" line.long 0x34 "CTRL_WKUP_CONF_DEBUG_SEL_TST_13,This register is used to select an observable signal for WKUP observability line 13" hexmask.long 0x34 1.--31. 1. "RESERVED," newline bitfld.long 0x34 0. "MODE,Selects one of the following signals to be available on WKUP observability line 13" "MODE_0,MODE_1" line.long 0x38 "CTRL_WKUP_CONF_DEBUG_SEL_TST_14,This register is used to select an observable signal for WKUP observability line 14" hexmask.long 0x38 1.--31. 1. "RESERVED," newline bitfld.long 0x38 0. "MODE,Selects one of the following signals to be available on WKUP observability line 14" "MODE_0,MODE_1" line.long 0x3C "CTRL_WKUP_CONF_DEBUG_SEL_TST_15,This register is used to select an observable signal for WKUP observability line 15" hexmask.long 0x3C 1.--31. 1. "RESERVED," newline bitfld.long 0x3C 0. "MODE,Selects one of the following signals to be available on WKUP observability line 15" "MODE_0,MODE_1" line.long 0x40 "CTRL_WKUP_CONF_DEBUG_SEL_TST_16,This register is used to select an observable signal for WKUP observability line 16" hexmask.long 0x40 1.--31. 1. "RESERVED," newline bitfld.long 0x40 0. "MODE,Selects one of the following signals to be available on WKUP observability line 16" "MODE_0,MODE_1" line.long 0x44 "CTRL_WKUP_CONF_DEBUG_SEL_TST_17,This register is used to select an observable signal for WKUP observability line 17" hexmask.long 0x44 1.--31. 1. "RESERVED," newline bitfld.long 0x44 0. "MODE,Selects one of the following signals to be available on WKUP observability line 17" "MODE_0,MODE_1" line.long 0x48 "CTRL_WKUP_CONF_DEBUG_SEL_TST_18,This register is used to select an observable signal for WKUP observability line 18" hexmask.long 0x48 1.--31. 1. "RESERVED," newline bitfld.long 0x48 0. "MODE,Selects one of the following signals to be available on WKUP observability line 18" "MODE_0,MODE_1" line.long 0x4C "CTRL_WKUP_CONF_DEBUG_SEL_TST_19,This register is used to select an observable signal for WKUP observability line 19" hexmask.long 0x4C 1.--31. 1. "RESERVED," newline bitfld.long 0x4C 0. "MODE,Selects one of the following signals to be available on WKUP observability line 19" "MODE_0,MODE_1" line.long 0x50 "CTRL_WKUP_CONF_DEBUG_SEL_TST_20,This register is used to select an observable signal for WKUP observability line 20" hexmask.long 0x50 1.--31. 1. "RESERVED," newline bitfld.long 0x50 0. "MODE,Selects one of the following signals to be available on WKUP observability line 20" "MODE_0,MODE_1" line.long 0x54 "CTRL_WKUP_CONF_DEBUG_SEL_TST_21,This register is used to select an observable signal for WKUP observability line 21" hexmask.long 0x54 1.--31. 1. "RESERVED," newline bitfld.long 0x54 0. "MODE,Selects one of the following signals to be available on WKUP observability line 21" "MODE_0,MODE_1" line.long 0x58 "CTRL_WKUP_CONF_DEBUG_SEL_TST_22,This register is used to select an observable signal for WKUP observability line 22" hexmask.long 0x58 1.--31. 1. "RESERVED," newline bitfld.long 0x58 0. "MODE,Selects one of the following signals to be available on WKUP observability line 22" "MODE_0,MODE_1" line.long 0x5C "CTRL_WKUP_CONF_DEBUG_SEL_TST_23,This register is used to select an observable signal for WKUP observability line 23" hexmask.long 0x5C 1.--31. 1. "RESERVED," newline bitfld.long 0x5C 0. "MODE,Selects one of the following signals to be available on WKUP observability line 23" "MODE_0,MODE_1" line.long 0x60 "CTRL_WKUP_CONF_DEBUG_SEL_TST_24,This register is used to select an observable signal for WKUP observability line 24" hexmask.long 0x60 1.--31. 1. "RESERVED," newline bitfld.long 0x60 0. "MODE,Selects one of the following signals to be available on WKUP observability line 24" "MODE_0,MODE_1" line.long 0x64 "CTRL_WKUP_CONF_DEBUG_SEL_TST_25,This register is used to select an observable signal for WKUP observability line 25" hexmask.long 0x64 1.--31. 1. "RESERVED," newline bitfld.long 0x64 0. "MODE,Selects one of the following signals to be available on WKUP observability line 25" "MODE_0,MODE_1" line.long 0x68 "CTRL_WKUP_CONF_DEBUG_SEL_TST_26,This register is used to select an observable signal for WKUP observability line 26" hexmask.long 0x68 1.--31. 1. "RESERVED," newline bitfld.long 0x68 0. "MODE,Selects one of the following signals to be available on WKUP observability line 26" "MODE_0,MODE_1" line.long 0x6C "CTRL_WKUP_CONF_DEBUG_SEL_TST_27,This register is used to select an observable signal for WKUP observability line 27" hexmask.long 0x6C 1.--31. 1. "RESERVED," newline bitfld.long 0x6C 0. "MODE,Selects one of the following signals to be available on WKUP observability line 27" "MODE_0,MODE_1" line.long 0x70 "CTRL_WKUP_CONF_DEBUG_SEL_TST_28,This register is used to select an observable signal for WKUP observability line 28" hexmask.long 0x70 1.--31. 1. "RESERVED," newline bitfld.long 0x70 0. "MODE,Selects one of the following signals to be available on WKUP observability line 28" "MODE_0,MODE_1" line.long 0x74 "CTRL_WKUP_CONF_DEBUG_SEL_TST_29,This register is used to select an observable signal for WKUP observability line 29" hexmask.long 0x74 1.--31. 1. "RESERVED," newline bitfld.long 0x74 0. "MODE,Selects one of the following signals to be available on WKUP observability line 29" "MODE_0,MODE_1" line.long 0x78 "CTRL_WKUP_CONF_DEBUG_SEL_TST_30,This register is used to select an observable signal for WKUP observability line 30" hexmask.long 0x78 1.--31. 1. "RESERVED," newline bitfld.long 0x78 0. "MODE,Selects one of the following signals to be available on WKUP observability line 30" "MODE_0,MODE_1" line.long 0x7C "CTRL_WKUP_CONF_DEBUG_SEL_TST_31,This register is used to select an observable signal for WKUP observability line 31" hexmask.long 0x7C 1.--31. 1. "RESERVED," newline bitfld.long 0x7C 0. "MODE,Selects one of the following signals to be available on WKUP observability line 31" "MODE_0,MODE_1" width 0x0B tree.end tree "CTRL_MODULE_WKUP_TARG" base ad:0x4AE0D000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CUSTEFUSE_CM_CORE" base ad:0x4A009600 group.long 0x00++0x03 line.long 0x00 "CM_CUSTEFUSE_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline rbitfld.long 0x00 9. "CLKACTIVITY_CUSTEFUSE_SYS_GFCLK,This field indicates the state of the Cust_Efuse_SYS_CLK clock input of the domain" "CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_0,CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_CUSTEFUSE_L4_GICLK,This field indicates the state of the L4_CUSTEFUSE_GICLK clock input of the domain" "CLKACTIVITY_CUSTEFUSE_L4_GICLK_0,CLKACTIVITY_CUSTEFUSE_L4_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the CUSTEFUSE clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x20++0x03 line.long 0x00 "CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL,This register manages the CUSTEFUSE clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "CUSTEFUSE_PRM" base ad:0x4AE07600 group.long 0x00++0x07 line.long 0x00 "PM_CUSTEFUSE_PWRSTCTRL,This register controls the CUSTEFUSE power state to reach upon a domain sleep transition" hexmask.long 0x00 5.--31. 1. "RESERVED," bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_CUSTEFUSE_PWRSTST,This register provides a status on the current CUSTEFUSE power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.tbyte 0x04 3.--19. 1. "RESERVED," rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT,This register contains dedicated CUSTEFUSE module context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end repeat 2. (list 2. 1. )(list ad:0x48480000 ad:0x4AE3C000 ) tree "DCAN$1" base $2 group.long 0x00++0x17 line.long 0x00 "DCAN_CTL,DCAN control register NOTE: The Bus-Off recovery sequence (refer to CAN specification) cannot be shortened by setting or resetting INIT bit" rbitfld.long 0x00 26.--31. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 25. "WUBA,Automatic wake up on bus activity when in local power-down mode" "WUBA_0,WUBA_1" newline bitfld.long 0x00 24. "PDR,Request for local low power-down mode" "PDR_0,PDR_1" rbitfld.long 0x00 21.--23. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. "DE3,Enable DMA request line for IF3" "DE3_0,DE3_1" bitfld.long 0x00 19. "DE2,Enable DMA request line for IF2" "DE2_0,DE2_1" newline bitfld.long 0x00 18. "DE1,Enable DMA request line for IF1" "DE1_0,DE1_1" bitfld.long 0x00 17. "IE1,Interrupt line 1 enable" "IE1_0,IE1_1" newline bitfld.long 0x00 16. "INITDBG,Internal init state while debug access" "INITDBG_0,INITDBG_1" bitfld.long 0x00 15. "SWR,Software reset enable" "SWR_0,SWR_1" newline rbitfld.long 0x00 14. "RESERVED,This bit is always read as 0" "0,1" bitfld.long 0x00 10.--13. "PMD," "?,?,?,?,?,PMD_5,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 9. "ABO,Auto-Bus-On enable" "ABO_0,ABO_1" bitfld.long 0x00 8. "IDS,Interruption debug support enable" "IDS_0,IDS_1" newline bitfld.long 0x00 7. "TEST,Test mode enable" "TEST_0,TEST_1" bitfld.long 0x00 6. "CCE,Configuration change enable" "CCE_0,CCE_1" newline bitfld.long 0x00 5. "DAR,Disable automatic retransmission" "DAR_0,DAR_1" rbitfld.long 0x00 4. "RESERVED,This bit is always read as 0" "0,1" newline bitfld.long 0x00 3. "EIE,Error interrupt enable" "EIE_0,EIE_1" bitfld.long 0x00 2. "SIE,Status change interrupt enable" "SIE_0,SIE_1" newline bitfld.long 0x00 1. "IE0,Interrupt line 0 enable" "IE0_0,IE0_1" bitfld.long 0x00 0. "INIT,Initialization" "INIT_0,INIT_1" line.long 0x04 "DCAN_ES,Error and Status Register Interrupts are generated by bits PER. BOFF and EWARN (if EIE bit in is 1) and by bits WAKEUPPND. RXOK. TXOK. and LEC (if SIE bit in is 1)" hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED,These bits are always read as 0" rbitfld.long 0x04 10. "PDA,Local power-down mode acknowledge" "PDA_0,PDA_1" newline rbitfld.long 0x04 9. "WAKEUPPND,Wake up pending" "WAKEUPPND_0,WAKEUPPND_1" bitfld.long 0x04 8. "PER,Parity error detected" "PER_0_w,PER_1_w" newline rbitfld.long 0x04 7. "BOFF,Bus-Off state" "BOFF_0,BOFF_1" rbitfld.long 0x04 6. "EWARN,Warning state" "EWARN_0,EWARN_1" newline rbitfld.long 0x04 5. "EPASS,Error passive state" "EPASS_0,EPASS_1" rbitfld.long 0x04 4. "RXOK,Received a message successfully" "RXOK_0,RXOK_1" newline rbitfld.long 0x04 3. "TXOK,Transmitted a message successfully" "TXOK_0,TXOK_1" rbitfld.long 0x04 0.--2. "LEC,Last error code" "LEC_0,LEC_1,LEC_2,LEC_3,LEC_4,LEC_5,LEC_6,LEC_7" line.long 0x08 "DCAN_ERRC,Error Counter Register" hexmask.long.word 0x08 16.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x08 15. "RP,Receive error passive" "RP_0,RP_1" newline hexmask.long.byte 0x08 8.--14. 1. "REC,Receive error counter" hexmask.long.byte 0x08 0.--7. 1. "TEC,Transmit error counter" line.long 0x0C "DCAN_BTR,Bit timing register This register is only writable if CCE and INIT bits in the are set" hexmask.long.word 0x0C 20.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x0C 16.--19. "BRPE,Baud rate prescaler extension.Valid programmed values are 0 to 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x0C 15. "RESERVED,These bits are always read as 0" "0,1" bitfld.long 0x0C 12.--14. "TSEG2,Time segment after the sample pointValid programmed values are 0 to 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 8.--11. "TSEG1,Time segment before the sample pointValid programmed values are 1 to15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 6.--7. "SJW,Synchronization Jump WidthValid programmed values are 0 to 3" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "BRP,Baud rate prescalerValue by which the CAN_CLK frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "DCAN_INT,Interrupt register" hexmask.long.byte 0x10 24.--31. 1. "RESERVED,These bits are always read as 0" hexmask.long.byte 0x10 16.--23. 1. "INT1ID,Interrupt 1 Identifier (indicates the message object with the highest pending interrupt)0x01-0x80: Number of message object which caused the interrupt" newline hexmask.long.word 0x10 0.--15. 1. "INT0ID,Interrupt Identifier (the number here indicates the source of the interrupt)0x0001-0x0080: Number of message object which caused the interrupt" line.long 0x14 "DCAN_TEST,Test Register For all test modes. the TEST bit in control register needs to be set to 1" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x14 9. "RDA,RAM direct access enable" "RDA_0,RDA_1" newline bitfld.long 0x14 8. "EXL,External loopback mode" "EXL_0,EXL_1" rbitfld.long 0x14 7. "RX,Receive pin" "RX_0,RX_1" newline bitfld.long 0x14 5.--6. "TX,Control of CAN_TX pin" "TX_0,TX_1,TX_2,TX_3" bitfld.long 0x14 4. "LBACK,Loopback mode" "LBACK_0,LBACK_1" newline bitfld.long 0x14 3. "SILENT,Silent mode" "SILENT_0,SILENT_1" rbitfld.long 0x14 0.--2. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7" rgroup.long 0x1C++0x17 line.long 0x00 "DCAN_PERR,Parity Error Code Register If a parity error is detected. the PER flag will be set in" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x00 8.--10. "WORD_NUMBER,Word number where parity error has been detectedRDA word number (1 to 5) of the message object (according to the message RAM representation in RDA mode)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Message object number where parity error has been detected (0x01-0x80)" line.long 0x04 "DCAN_REL,Core revision register" line.long 0x08 "DCAN_ECCDIAG,ECC Diagnostic Register" hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0.--3. "ECCDIAG,SECDED diagnostic mode enable/disable" "?,?,?,?,?,Diagnostic mode is enabled,?,?,?,?,Diagnostic mode is disabled single and double..,?..." line.long 0x0C "DCAN_ECCDIAG_STAT,ECC Diagnostic Status Register" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 8. "DEFLG_DIAG,Double bit error flag diagnostic" "The bit is unchanged,The bit is cleared to 0" newline hexmask.long.byte 0x0C 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x0C 0. "SEFLG_DIAG,Single bit error flag diagnostic" "The bit is unchanged,The bit is cleared to 0" line.long 0x10 "DCAN_ECC_CS,ECC Control and Status Register" rbitfld.long 0x10 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. "SBE_EVT_EN,Enable/disable SECDED single bit error event (CAN_SERR signal)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x10 20.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 16.--19. "ECCMODE,Enable/disable SECDED single bit error correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED,Reserved" bitfld.long 0x10 8. "DEFLG,Double bit error flag" "The bit is unchanged,The bit is cleared to 0" newline hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x10 0. "SEFLG,Single bit error flag" "The bit is unchanged,The bit is cleared to 0" line.long 0x14 "DCAN_ECC_SERR,ECC Single Bit Error Code Register" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 0.--7. 1. "MESSAGE_NUMBER,Message object number where ECC single bit error has been detected" group.long 0x80++0x53 line.long 0x00 "DCAN_ABOTR,Auto-Bus-On Time Register On write access to the while Auto-Bus-On timer is running. the Auto-Bus-On procedure will be aborted" line.long 0x04 "DCAN_TXRQ_X,Transmission Request X Register The software can detect if one or more bits in the different transmission request registers are set" hexmask.long.word 0x04 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x04 14.--15. "TXRQSTREG8,Transmission request bits (aggregate for 113-128 message objects)" "0,1,2,3" newline bitfld.long 0x04 12.--13. "TXRQSTREG7,Transmission request bits (aggregate for 97-112 message objects)" "0,1,2,3" bitfld.long 0x04 10.--11. "TXRQSTREG6,Transmission request bits (aggregate for 81-96 message objects)" "0,1,2,3" newline bitfld.long 0x04 8.--9. "TXRQSTREG5,Transmission request bits (aggregate for 65-80 message objects)" "0,1,2,3" bitfld.long 0x04 6.--7. "TXRQSTREG4,Transmission request bits (aggregate for 49-64 message objects)" "0,1,2,3" newline bitfld.long 0x04 4.--5. "TXRQSTREG3,Transmission request bits (aggregate for 33-48 message objects)" "0,1,2,3" bitfld.long 0x04 2.--3. "TXRQSTREG2,Transmission request bits (aggregate for 17-32 message objects)" "0,1,2,3" newline bitfld.long 0x04 0.--1. "TXRQSTREG1,Transmission request bits (aggregate for 1-16 message objects)" "0,1,2,3" line.long 0x08 "DCAN_TXRQ12,Transmission Request Register This register holds the TxRqst bits of the implemented message objects" line.long 0x0C "DCAN_TXRQ34,Transmission Request Register This register holds the TxRqst bits of the implemented message objects" line.long 0x10 "DCAN_TXRQ56,Transmission Request Register This register holds the TxRqst bits of the implemented message objects" line.long 0x14 "DCAN_TXRQ78,Transmission Request Register This register holds the TxRqst bits of the implemented message objects" line.long 0x18 "DCAN_NWDAT_X,New Data X Register With the new data X register. the software can detect if one or more bits in the different new data registers are set" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14.--15. "NEWDATREG8,New data bits (aggregate for 113-128 message objects)" "0,1,2,3" newline bitfld.long 0x18 12.--13. "NEWDATREG7,New data bits (aggregate for 97-112 message objects)" "0,1,2,3" bitfld.long 0x18 10.--11. "NEWDATREG6,New data bits (aggregate for 81-96 message objects)" "0,1,2,3" newline bitfld.long 0x18 8.--9. "NEWDATREG5,New data bits (aggregate for 65-80 message objects)" "0,1,2,3" bitfld.long 0x18 6.--7. "NEWDATREG4,New data bits (aggregate for 49-64 message objects)" "0,1,2,3" newline bitfld.long 0x18 4.--5. "NEWDATREG3,New data bits (aggregate for 33-48 message objects)" "0,1,2,3" bitfld.long 0x18 2.--3. "NEWDATREG2,New data bits (aggregate for 17-32 message objects)" "0,1,2,3" newline bitfld.long 0x18 0.--1. "NEWDATREG1,New data bits (aggregate for 1-16 message objects)" "0,1,2,3" line.long 0x1C "DCAN_NWDAT12,New Data Register This register hold the NewDat bits of the implemented message objects" line.long 0x20 "DCAN_NWDAT34,New Data Register This register hold the NewDat bits of the implemented message objects" line.long 0x24 "DCAN_NWDAT56,New Data Register This register hold the NewDat bits of the implemented message objects" line.long 0x28 "DCAN_NWDAT78,New Data Register This register hold the NewDat bits of the implemented message objects" line.long 0x2C "DCAN_INTPND_X,Interrupt Pending X Register With the interrupt pending X register. the software can detect if one or more bits in the different interrupt pending registers are set" hexmask.long.word 0x2C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 14.--15. "INTPNDREG8,Interrupt Pending bits (aggregate for 113-128 message objects)" "0,1,2,3" newline bitfld.long 0x2C 12.--13. "INTPNDREG7,Interrupt Pending bits (aggregate for 97-112 message objects)" "0,1,2,3" bitfld.long 0x2C 10.--11. "INTPNDREG6,Interrupt Pendingbits (aggregate for 81-96 message objects)" "0,1,2,3" newline bitfld.long 0x2C 8.--9. "INTPNDREG5,Interrupt Pending bits (aggregate for 65-80 message objects)" "0,1,2,3" bitfld.long 0x2C 6.--7. "INTPNDREG4,Interrupt Pending bits (aggregate for 49-64 message objects)" "0,1,2,3" newline bitfld.long 0x2C 4.--5. "INTPNDREG3,Interrupt Pending bits (aggregate for 33-48 message objects)" "0,1,2,3" bitfld.long 0x2C 2.--3. "INTPNDREG2,Interrupt Pending bits (aggregate for 17-32 message objects)" "0,1,2,3" newline bitfld.long 0x2C 0.--1. "INTPNDREG1,Interrupt Pending bits (aggregate for 1-16 message objects)" "0,1,2,3" line.long 0x30 "DCAN_INTPND12,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects" line.long 0x34 "DCAN_INTPND34,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects" line.long 0x38 "DCAN_INTPND56,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects" line.long 0x3C "DCAN_INTPND78,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects" line.long 0x40 "DCAN_MSGVAL_X,Message Valid X Register With the message valid X register. the software can detect if one or more bits in the different message valid registers are set" hexmask.long.word 0x40 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x40 14.--15. "MSGVALREG8,Message valid bits (aggregate for 113-128 message objects)" "0,1,2,3" newline bitfld.long 0x40 12.--13. "MSGVALREG7,Message valid bits (aggregate for 97-112 message objects)" "0,1,2,3" bitfld.long 0x40 10.--11. "MSGVALREG6,Message valid bits (aggregate for 81-96 message objects)" "0,1,2,3" newline bitfld.long 0x40 8.--9. "MSGVALREG5,Message valid bits (aggregate for 65-80 message objects)" "0,1,2,3" bitfld.long 0x40 6.--7. "MSGVALREG4,Message valid bits (aggregate for 49-64 message objects)" "0,1,2,3" newline bitfld.long 0x40 4.--5. "MSGVALREG3,Message valid bits (aggregate for 33-48 message objects)" "0,1,2,3" bitfld.long 0x40 2.--3. "MSGVALREG2,Message valid bits (aggregate for 17-32 message objects)" "0,1,2,3" newline bitfld.long 0x40 0.--1. "MSGVALREG1,Message valid bits (aggregate for 1-16 message objects)" "0,1,2,3" line.long 0x44 "DCAN_MSGVAL12,Message Valid Register These registers hold the MsgVal bits of the implemented message objects" line.long 0x48 "DCAN_MSGVAL34,Message Valid Register These registers hold the MsgVal bits of the implemented message objects" line.long 0x4C "DCAN_MSGVAL56,Message Valid Register These registers hold the MsgVal bits of the implemented message objects" line.long 0x50 "DCAN_MSGVAL78,Message Valid Register These registers hold the MsgVal bits of the implemented message objects" group.long 0xD8++0x0F line.long 0x00 "DCAN_INTMUX12,Interrupt Multiplexer Register The IntMux flag determine for each message object. which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set" line.long 0x04 "DCAN_INTMUX34,Interrupt Multiplexer Register The IntMux flag determine for each message object. which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set" line.long 0x08 "DCAN_INTMUX56,Interrupt Multiplexer Register The IntMux flag determine for each message object. which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set" line.long 0x0C "DCAN_INTMUX78,Interrupt Multiplexer Register The IntMux flag determine for each message object. which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set" group.long 0x100++0x17 line.long 0x00 "DCAN_IF1CMD,IF1 Command Register The IF1 Command Register () configure and initiate the transfer between the IF1 register set and the message RAM" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x00 23. "WR_RD,Write/Read" "WR_RD_0,WR_RD_1" newline bitfld.long 0x00 22. "MASK,Access mask bits" "MASK_0,MASK_1" bitfld.long 0x00 21. "ARB,Access arbitration bits" "ARB_0,ARB_1" newline bitfld.long 0x00 20. "CONTROL,Access control bitsIf the TXRQST_NEWDAT bit in this register(Bit [18]) is set the TXRQST/ NEWDAT bits in the will be ignored" "CONTROL_0,CONTROL_1" bitfld.long 0x00 19. "CLRINTPND,Clear interrupt pending bit" "CLRINTPND_0,CLRINTPND_1" newline bitfld.long 0x00 18. "TXRQST_NEWDAT,Access transmission request bitNote: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register the TxRqst/NewDat bits in the message object will be set to one independent of the values in" "TXRQST_NEWDAT_0,TXRQST_NEWDAT_1" bitfld.long 0x00 17. "DATA_A,Access Data Bytes" "DATA_A_0,DATA_A_1" newline bitfld.long 0x00 16. "DATA_B,Access Data Bytes" "DATA_B_0,DATA_B_1" bitfld.long 0x00 15. "BUSY,Busy flagThis bit is set to one after the message number has been written to bits [7:0] MESSAGE_NUMBER" "BUSY_0,BUSY_1" newline bitfld.long 0x00 14. "DMAACTIVE,Activation of DMA feature for subsequent internal IF1 updateThe DMA request remains active until the first read or write to one of the IF1 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one" "DMAACTIVE_0,DMAACTIVE_1" rbitfld.long 0x00 8.--13. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Number of message object in message RAM which is used for data transfer0x01-0x80: Valid message numbers" line.long 0x04 "DCAN_IF1MSK,IF1 Mask Register The bits of the IF1/IF2 mask registers mirror the mask bits of a message object" bitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit ('standard') identifiers are used for a message object the identifiers of received data frames are written into bits ID[28:18]" "MXTD_0,MXTD_1" bitfld.long 0x04 30. "MDIR,Mask Message Direction" "MDIR_0,MDIR_1" newline rbitfld.long 0x04 29. "RESERVED,This bit is always read as 1" "0,1" hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask" line.long 0x08 "DCAN_IF1ARB,IF1 arbitration register The Arbitration bits ID[28:0]. XTD. and DIR are used to define the identifier and type of outgoing messages and (together with the mask bits MSK[28:0]. MXTD. and MDIR) for acceptance filtering of incoming messages" bitfld.long 0x08 31. "MSGVAL,Message validThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in" "MSGVAL_0,MSGVAL_1" bitfld.long 0x08 30. "XTD,Extended identifier" "XTD_0,XTD_1" newline bitfld.long 0x08 29. "DIR,Message direction" "DIR_0,DIR_1" hexmask.long 0x08 0.--28. 1. "ID,Message identifierID[28:0]: 29-bit identifier (extended frame)" line.long 0x0C "DCAN_IF1MCTL,IF1 Message Control Register The bits of the IF1/IF2 message control registers mirror the message control bits of a message object" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x0C 15. "NEWDAT,New data" "NEWDAT_0,NEWDAT_1" newline bitfld.long 0x0C 14. "MSGLST,Message lost (only valid for message objects with direction = receive)" "MSGLST_0,MSGLST_1" bitfld.long 0x0C 13. "INTPND,Interrupt pending" "INTPND_0,INTPND_1" newline bitfld.long 0x0C 12. "UMASK,Use acceptance maskIf the UMASK bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "UMASK_0,UMASK_1" bitfld.long 0x0C 11. "TXIE,Transmit interrupt enable" "TXIE_0,TXIE_1" newline bitfld.long 0x0C 10. "RXIE,Receive interrupt enable" "RXIE_0,RXIE_1" bitfld.long 0x0C 9. "RMTEN,Remote enable" "RMTEN_0,RMTEN_1" newline bitfld.long 0x0C 8. "TXRQST,Transmit request" "TXRQST_0,TXRQST_1" bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "EOB_0,EOB_1" newline rbitfld.long 0x0C 4.--6. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--3. "DLC,Data length code0-8: Data frame has 0-8 data bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DCAN_IF1DATA,IF1 Data A Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3" hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2" newline hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1" hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0" line.long 0x14 "DCAN_IF1DATB,IF1 Data B Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7" hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6" newline hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5" hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4" group.long 0x120++0x17 line.long 0x00 "DCAN_IF2CMD,IF2 Command Register The IF2 Command Register () configure and initiate the transfer between the IF2 register set and the message RAM" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x00 23. "WR_RD,Write/Read" "WR_RD_0,WR_RD_1" newline bitfld.long 0x00 22. "MASK,Access mask bits" "MASK_0,MASK_1" bitfld.long 0x00 21. "ARB,Access arbitration bits" "ARB_0,ARB_1" newline bitfld.long 0x00 20. "CONTROL,Access control bitsIf the TXRQST_NEWDAT bit in this register(Bit [18]) is set the TXRQST/ NEWDAT bits in the/ will be ignored" "CONTROL_0,CONTROL_1" bitfld.long 0x00 19. "CLRINTPND,Clear interrupt pending bit" "CLRINTPND_0,CLRINTPND_1" newline bitfld.long 0x00 18. "TXRQST_NEWDAT,Access transmission request bitNote: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register the TxRqst/NewDat bits in the message object will be set to one independent of the values in/" "TXRQST_NEWDAT_0,TXRQST_NEWDAT_1" bitfld.long 0x00 17. "DATA_A,Access Data Bytes" "DATA_A_0,DATA_A_1" newline bitfld.long 0x00 16. "DATA_B,Access Data Bytes" "DATA_B_0,DATA_B_1" bitfld.long 0x00 15. "BUSY,Busy flagThis bit is set to one after the message number has been written to bits [7:0] MESSAGE_NUMBER" "BUSY_0,BUSY_1" newline bitfld.long 0x00 14. "DMAACTIVE,Activation of DMA feature for subsequent internal IF2 updateThe DMA request remains active until the first read or write to one of the IF2 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one" "DMAACTIVE_0,DMAACTIVE_1" rbitfld.long 0x00 8.--13. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Number of message object in message RAM which is used for data transfer0x01-0x80: Valid message numbers" line.long 0x04 "DCAN_IF2MSK,IF2 Mask Register The bits of the IF1/IF2 mask registers mirror the mask bits of a message object" bitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit ('standard') identifiers are used for a message object the identifiers of received data frames are written into bits ID[28:18]" "MXTD_0,MXTD_1" bitfld.long 0x04 30. "MDIR,Mask Message Direction" "MDIR_0,MDIR_1" newline rbitfld.long 0x04 29. "RESERVED,This bit is always read as 1" "0,1" hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask" line.long 0x08 "DCAN_IF2ARB,IF2 arbitration register The Arbitration bits ID[28:0]. XTD. and DIR are used to define the identifier and type of outgoing messages and (together with the mask bits MSK[28:0]. MXTD. and MDIR) for acceptance filtering of incoming messages" bitfld.long 0x08 31. "MSGVAL,Message validThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in" "MSGVAL_0,MSGVAL_1" bitfld.long 0x08 30. "XTD,Extended identifier" "XTD_0,XTD_1" newline bitfld.long 0x08 29. "DIR,Message direction" "DIR_0,DIR_1" hexmask.long 0x08 0.--28. 1. "ID,Message identifierID[28:0]: 29-bit identifier (extended frame)" line.long 0x0C "DCAN_IF2MCTL,IF2 Message Control Register The bits of the IF1/IF2 message control registers mirror the message control bits of a message object" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x0C 15. "NEWDAT,New data" "NEWDAT_0,NEWDAT_1" newline bitfld.long 0x0C 14. "MSGLST,Message lost (only valid for message objects with direction = receive)" "MSGLST_0,MSGLST_1" bitfld.long 0x0C 13. "INTPND,Interrupt pending" "INTPND_0,INTPND_1" newline bitfld.long 0x0C 12. "UMASK,Use acceptance maskIf the UMask bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "UMASK_0,UMASK_1" bitfld.long 0x0C 11. "TXIE,Transmit interrupt enable" "TXIE_0,TXIE_1" newline bitfld.long 0x0C 10. "RXIE,Receive interrupt enable" "RXIE_0,RXIE_1" bitfld.long 0x0C 9. "RMTEN,Remote enable" "RMTEN_0,RMTEN_1" newline bitfld.long 0x0C 8. "TXRQST,Transmit request" "TXRQST_0,TXRQST_1" bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "EOB_0,EOB_1" newline rbitfld.long 0x0C 4.--6. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--3. "DLC,Data length code0-8: Data frame has 0-8 data bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DCAN_IF2DATA,IF2 Data A Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3" hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2" newline hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1" hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0" line.long 0x14 "DCAN_IF2DATB,IF2 Data B Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7" hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6" newline hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5" hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4" group.long 0x140++0x17 line.long 0x00 "DCAN_IF3OBS,IF3 Observation Register The IF3 register set can automatically be updated with received message objects without the need to initiate the transfer from message RAM by software (Additional information can be found in NOTE: If IF3 Update.." hexmask.long.word 0x00 16.--31. 1. "RESERVED,These bits are always read as 0" rbitfld.long 0x00 15. "IF3_UPD,IF3 Update Data" "IF3_UPD_0,IF3_UPD_1" newline rbitfld.long 0x00 13.--14. "RESERVED,These bits are always read as 0" "0,1,2,3" rbitfld.long 0x00 12. "IF3_SDB,IF3 Status of Data B read access" "IF3_SDB_0,IF3_SDB_1" newline rbitfld.long 0x00 11. "IF3_SDA,IF3 Status of Data A read access" "IF3_SDA_0,IF3_SDA_1" rbitfld.long 0x00 10. "IF3_SC,IF3 Status of control bits read access" "IF3_SC_0,IF3_SC_1" newline rbitfld.long 0x00 9. "IF3_SA,IF3 Status of Arbitration data read access" "IF3_SA_0,IF3_SA_1" rbitfld.long 0x00 8. "IF3_SM,IF3 Status of Mask data read access" "IF3_SM_0,IF3_SM_1" newline rbitfld.long 0x00 5.--7. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "DATAB,Data B read observation" "DATAB_0,DATAB_1" newline bitfld.long 0x00 3. "DATAA,Data A read observation" "DATAA_0,DATAA_1" bitfld.long 0x00 2. "CTRL,Ctrl read observation" "CTRL_0,CTRL_1" newline bitfld.long 0x00 1. "ARB,Arbitration data read observation" "ARB_0,ARB_1" bitfld.long 0x00 0. "MASK,Mask data read observation" "MASK_0,MASK_1" line.long 0x04 "DCAN_IF3MSK,IF3 Mask Register" rbitfld.long 0x04 31. "MXTD,Mask Extended IdentifierWhen 11-bit ('standard') identifiers are used for a message object the identifiers of received data frames are written into bits ID[28:18]" "MXTD_0,MXTD_1" rbitfld.long 0x04 30. "MDIR,Mask Message Direction" "MDIR_0,MDIR_1" newline rbitfld.long 0x04 29. "RESERVED,These bits are always read as 1" "0,1" hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask" line.long 0x08 "DCAN_IF3ARB,IF3 Arbitration Register" bitfld.long 0x08 31. "MSGVAL,Message ValidThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in" "MSGVAL_0,MSGVAL_1" bitfld.long 0x08 30. "XTD,Extended Identifier" "XTD_0,XTD_1" newline bitfld.long 0x08 29. "DIR,Message Direction" "DIR_0,DIR_1" hexmask.long 0x08 0.--28. 1. "ID,Message IdentifierID[28:0]: 29-bit Identifier ('extended frame')" line.long 0x0C "DCAN_IF3MCTL,IF3 Message Control Register" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x0C 15. "NEWDAT,New Data" "NEWDAT_0,NEWDAT_1" newline bitfld.long 0x0C 14. "MSGLST,Message Lost (only valid for message objects with direction = receive)" "MSGLST_0,MSGLST_1" bitfld.long 0x0C 13. "INTPND,Interrupt Pending" "INTPND_0,INTPND_1" newline bitfld.long 0x0C 12. "UMASK,Use Acceptance MaskIf the UMASK bit is set to one the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one" "UMASK_0,UMASK_1" bitfld.long 0x0C 11. "TXIE,Transmit Interrupt enable" "TXIE_0,TXIE_1" newline bitfld.long 0x0C 10. "RXIE,Receive Interrupt enable" "RXIE_0,RXIE_1" bitfld.long 0x0C 9. "RMTEN,Remote enable" "RMTEN_0,RMTEN_1" newline bitfld.long 0x0C 8. "TXRQST,Transmit Request" "TXRQST_0,TXRQST_1" bitfld.long 0x0C 7. "EOB,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer" "EOB_0,EOB_1" newline bitfld.long 0x0C 4.--6. "RESERVED,These bits are always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--3. "DLC,Data Length Code0-8: Data frame has 0-8 data bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DCAN_IF3DATA,IF3 Data A The data bytes of CAN messages are stored in the IF3 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3" hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2" newline hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1" hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0" line.long 0x14 "DCAN_IF3DATB,IF3 Data B The data bytes of CAN messages are stored in the IF3 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7" hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6" newline hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5" hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4" group.long 0x160++0x0F line.long 0x00 "DCAN_IF3UPD12,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object" line.long 0x04 "DCAN_IF3UPD34,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object" line.long 0x08 "DCAN_IF3UPD56,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object" line.long 0x0C "DCAN_IF3UPD78,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object" group.long 0x1E0++0x07 line.long 0x00 "DCAN_TIOC,TX I/O Control Register The CAN_TX pin of the DCAN module can be used as general purpose IO pin if CAN function is not needed" hexmask.long.word 0x00 19.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x00 18. "PU,CAN_TX pull up/pull down select" "PU_0,PU_1" newline bitfld.long 0x00 17. "PD,CAN_TX pull disable" "PD_0,PD_1" bitfld.long 0x00 16. "OD,CAN_TX open drain enable" "OD_0,OD_1" newline hexmask.long.word 0x00 4.--15. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x00 3. "FUNC,CAN_TX function" "FUNC_0,FUNC_1" newline bitfld.long 0x00 2. "DIR,CAN_TX data direction" "DIR_0,DIR_1" bitfld.long 0x00 1. "OUT,CAN_TX data out" "OUT_0,OUT_1" newline bitfld.long 0x00 0. "IN,CAN_TX data inNote: When CAN_TX pin is connected to a CAN transceiver an external pullup resistor has to be used to ensure that the CAN bus will not be disturbed (e.g. while reset of the DCAN module)" "IN_0,IN_1" line.long 0x04 "DCAN_RIOC,RX I/O Control Register The CAN_RX pin of the DCAN_module can be used as general purpose IO pin if CAN function is not needed" hexmask.long.word 0x04 19.--31. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x04 18. "PU,CAN_RX pull up/pull down select" "PU_0,PU_1" newline bitfld.long 0x04 17. "PD,CAN_RX pull disable" "PD_0,PD_1" bitfld.long 0x04 16. "OD,CAN_RX open drain enable" "OD_0,OD_1" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED,These bits are always read as 0" bitfld.long 0x04 3. "FUNC,CAN_RX function" "FUNC_0,FUNC_1" newline bitfld.long 0x04 2. "DIR,CAN_RX data direction" "DIR_0,DIR_1" bitfld.long 0x04 1. "OUT,CAN_RX data out" "OUT_0,OUT_1" newline bitfld.long 0x04 0. "IN,CAN_RX data in" "IN_0,IN_1" width 0x0B tree.end repeat.end tree "DCAN1_TARG" base ad:0x4AE3E000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCAN2_TARG" base ad:0x48482000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end repeat 7. (list 6. 7. 5. 1. 2. 3. 4. )(list ad:0x48848000 ad:0x4884A000 ad:0x4884C000 ad:0x48856000 ad:0x48858000 ad:0x4885A000 ad:0x4885C000 ) tree "DCC$1" base $2 group.long 0x00++0x2B line.long 0x00 "DCCGCTRL,DCC Global Control RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x00 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag inDCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..." bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DCCREV,DCC Revision IDNOTE: For SR1.0 physical addresses. see" line.long 0x08 "DCCCNTSEED0,Count0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x08 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)" line.long 0x0C "DCCVALIDSEED0,Valid0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x0C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x10 "DCCCNTSEED1,Count1 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x10 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)" line.long 0x14 "DCCSTAT,DCC Status RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long 0x14 2.--31. 1. "RES," bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag" newline bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occurred" "no effect,clear the error flag" line.long 0x18 "DCCCNT0,Count0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x18 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0" line.long 0x1C "DCCVALID0,Valid0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x1C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0" line.long 0x20 "DCCCNT1,Count1 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x20 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1" line.long 0x24 "DCCCLKSRC1,Clock Source Selection Register" hexmask.long.word 0x24 16.--31. 1. "RES0,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 4.--11. 1. "RES1,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 0.--3. "CLKSRC,This field specifies the clock source for COUNT1 when the KEY field enables this feature" "Clock source 0 is selected for COUNT1,Clock source 1 is selected for COUNT1,Clock source 2 is selected for COUNT1,Clock source 3 is selected for COUNT1,Clock source 4 is selected for COUNT1,Clock source 5 is selected for COUNT1,Clock source 6 is selected for COUNT1,Clock source 7 is selected for COUNT1,?..." line.long 0x28 "DCCCLKSRC0,Clock Source Selection Register" hexmask.long 0x28 4.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for COUNT0" "?,?,?,?,?,Clock0[2] is selected as source for COUNT0,?,?,?,?,Clock0[1] is selected as source for COUNT0,?..." width 0x0B tree.end repeat.end tree "DCC1_SR2" base ad:0x48828000 group.long 0x00++0x2B line.long 0x00 "DCCGCTRL,DCC Global Control RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x00 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag inDCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..." bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DCCREV,DCC Revision IDNOTE: For SR1.0 physical addresses. see" line.long 0x08 "DCCCNTSEED0,Count0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x08 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)" line.long 0x0C "DCCVALIDSEED0,Valid0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x0C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x10 "DCCCNTSEED1,Count1 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x10 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)" line.long 0x14 "DCCSTAT,DCC Status RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long 0x14 2.--31. 1. "RES," bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag" newline bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occurred" "no effect,clear the error flag" line.long 0x18 "DCCCNT0,Count0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x18 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0" line.long 0x1C "DCCVALID0,Valid0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x1C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0" line.long 0x20 "DCCCNT1,Count1 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x20 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1" line.long 0x24 "DCCCLKSRC1,Clock Source Selection Register" hexmask.long.word 0x24 16.--31. 1. "RES0,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 4.--11. 1. "RES1,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 0.--3. "CLKSRC,This field specifies the clock source for COUNT1 when the KEY field enables this feature" "Clock source 0 is selected for COUNT1,Clock source 1 is selected for COUNT1,Clock source 2 is selected for COUNT1,Clock source 3 is selected for COUNT1,Clock source 4 is selected for COUNT1,Clock source 5 is selected for COUNT1,Clock source 6 is selected for COUNT1,Clock source 7 is selected for COUNT1,?..." line.long 0x28 "DCCCLKSRC0,Clock Source Selection Register" hexmask.long 0x28 4.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for COUNT0" "?,?,?,?,?,Clock0[2] is selected as source for COUNT0,?,?,?,?,Clock0[1] is selected as source for COUNT0,?..." width 0x0B tree.end tree "DCC1_TARG" base ad:0x48856000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC1_TARG_SR2" base ad:0x48829000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC2_SR2" base ad:0x4882A000 group.long 0x00++0x2B line.long 0x00 "DCCGCTRL,DCC Global Control RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x00 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag inDCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..." bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DCCREV,DCC Revision IDNOTE: For SR1.0 physical addresses. see" line.long 0x08 "DCCCNTSEED0,Count0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x08 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)" line.long 0x0C "DCCVALIDSEED0,Valid0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x0C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x10 "DCCCNTSEED1,Count1 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x10 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)" line.long 0x14 "DCCSTAT,DCC Status RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long 0x14 2.--31. 1. "RES," bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag" newline bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occurred" "no effect,clear the error flag" line.long 0x18 "DCCCNT0,Count0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x18 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0" line.long 0x1C "DCCVALID0,Valid0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x1C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0" line.long 0x20 "DCCCNT1,Count1 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x20 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1" line.long 0x24 "DCCCLKSRC1,Clock Source Selection Register" hexmask.long.word 0x24 16.--31. 1. "RES0,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 4.--11. 1. "RES1,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 0.--3. "CLKSRC,This field specifies the clock source for COUNT1 when the KEY field enables this feature" "Clock source 0 is selected for COUNT1,Clock source 1 is selected for COUNT1,Clock source 2 is selected for COUNT1,Clock source 3 is selected for COUNT1,Clock source 4 is selected for COUNT1,Clock source 5 is selected for COUNT1,Clock source 6 is selected for COUNT1,Clock source 7 is selected for COUNT1,?..." line.long 0x28 "DCCCLKSRC0,Clock Source Selection Register" hexmask.long 0x28 4.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for COUNT0" "?,?,?,?,?,Clock0[2] is selected as source for COUNT0,?,?,?,?,Clock0[1] is selected as source for COUNT0,?..." width 0x0B tree.end tree "DCC2_TARG" base ad:0x48858000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC2_TARG_SR2" base ad:0x4882B000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC3_SR2" base ad:0x4882C000 group.long 0x00++0x2B line.long 0x00 "DCCGCTRL,DCC Global Control RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x00 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag inDCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..." bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DCCREV,DCC Revision IDNOTE: For SR1.0 physical addresses. see" line.long 0x08 "DCCCNTSEED0,Count0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x08 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)" line.long 0x0C "DCCVALIDSEED0,Valid0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x0C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x10 "DCCCNTSEED1,Count1 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x10 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)" line.long 0x14 "DCCSTAT,DCC Status RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long 0x14 2.--31. 1. "RES," bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag" newline bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occurred" "no effect,clear the error flag" line.long 0x18 "DCCCNT0,Count0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x18 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0" line.long 0x1C "DCCVALID0,Valid0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x1C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0" line.long 0x20 "DCCCNT1,Count1 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x20 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1" line.long 0x24 "DCCCLKSRC1,Clock Source Selection Register" hexmask.long.word 0x24 16.--31. 1. "RES0,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 4.--11. 1. "RES1,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 0.--3. "CLKSRC,This field specifies the clock source for COUNT1 when the KEY field enables this feature" "Clock source 0 is selected for COUNT1,Clock source 1 is selected for COUNT1,Clock source 2 is selected for COUNT1,Clock source 3 is selected for COUNT1,Clock source 4 is selected for COUNT1,Clock source 5 is selected for COUNT1,Clock source 6 is selected for COUNT1,Clock source 7 is selected for COUNT1,?..." line.long 0x28 "DCCCLKSRC0,Clock Source Selection Register" hexmask.long 0x28 4.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for COUNT0" "?,?,?,?,?,Clock0[2] is selected as source for COUNT0,?,?,?,?,Clock0[1] is selected as source for COUNT0,?..." width 0x0B tree.end tree "DCC3_TARG" base ad:0x4885A000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC3_TARG_SR2" base ad:0x4882D000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC4_SR2" base ad:0x4882E000 group.long 0x00++0x2B line.long 0x00 "DCCGCTRL,DCC Global Control RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x00 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag inDCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..." bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DCCREV,DCC Revision IDNOTE: For SR1.0 physical addresses. see" line.long 0x08 "DCCCNTSEED0,Count0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x08 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)" line.long 0x0C "DCCVALIDSEED0,Valid0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x0C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x10 "DCCCNTSEED1,Count1 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x10 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)" line.long 0x14 "DCCSTAT,DCC Status RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long 0x14 2.--31. 1. "RES," bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag" newline bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occurred" "no effect,clear the error flag" line.long 0x18 "DCCCNT0,Count0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x18 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0" line.long 0x1C "DCCVALID0,Valid0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x1C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0" line.long 0x20 "DCCCNT1,Count1 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x20 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1" line.long 0x24 "DCCCLKSRC1,Clock Source Selection Register" hexmask.long.word 0x24 16.--31. 1. "RES0,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 4.--11. 1. "RES1,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 0.--3. "CLKSRC,This field specifies the clock source for COUNT1 when the KEY field enables this feature" "Clock source 0 is selected for COUNT1,Clock source 1 is selected for COUNT1,Clock source 2 is selected for COUNT1,Clock source 3 is selected for COUNT1,Clock source 4 is selected for COUNT1,Clock source 5 is selected for COUNT1,Clock source 6 is selected for COUNT1,Clock source 7 is selected for COUNT1,?..." line.long 0x28 "DCCCLKSRC0,Clock Source Selection Register" hexmask.long 0x28 4.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for COUNT0" "?,?,?,?,?,Clock0[2] is selected as source for COUNT0,?,?,?,?,Clock0[1] is selected as source for COUNT0,?..." width 0x0B tree.end tree "DCC4_TARG" base ad:0x4885C000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC4_TARG_SR2" base ad:0x4882F000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC5_SR2" base ad:0x4884E000 group.long 0x00++0x2B line.long 0x00 "DCCGCTRL,DCC Global Control RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x00 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag inDCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..." bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DCCREV,DCC Revision IDNOTE: For SR1.0 physical addresses. see" line.long 0x08 "DCCCNTSEED0,Count0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x08 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)" line.long 0x0C "DCCVALIDSEED0,Valid0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x0C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x10 "DCCCNTSEED1,Count1 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x10 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)" line.long 0x14 "DCCSTAT,DCC Status RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long 0x14 2.--31. 1. "RES," bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag" newline bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occurred" "no effect,clear the error flag" line.long 0x18 "DCCCNT0,Count0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x18 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0" line.long 0x1C "DCCVALID0,Valid0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x1C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0" line.long 0x20 "DCCCNT1,Count1 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x20 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1" line.long 0x24 "DCCCLKSRC1,Clock Source Selection Register" hexmask.long.word 0x24 16.--31. 1. "RES0,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 4.--11. 1. "RES1,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 0.--3. "CLKSRC,This field specifies the clock source for COUNT1 when the KEY field enables this feature" "Clock source 0 is selected for COUNT1,Clock source 1 is selected for COUNT1,Clock source 2 is selected for COUNT1,Clock source 3 is selected for COUNT1,Clock source 4 is selected for COUNT1,Clock source 5 is selected for COUNT1,Clock source 6 is selected for COUNT1,Clock source 7 is selected for COUNT1,?..." line.long 0x28 "DCCCLKSRC0,Clock Source Selection Register" hexmask.long 0x28 4.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for COUNT0" "?,?,?,?,?,Clock0[2] is selected as source for COUNT0,?,?,?,?,Clock0[1] is selected as source for COUNT0,?..." width 0x0B tree.end tree "DCC5_TARG" base ad:0x4884C000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC5_TARG_SR2" base ad:0x4884F000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC6_SR2" base ad:0x48852000 group.long 0x00++0x2B line.long 0x00 "DCCGCTRL,DCC Global Control RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x00 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag inDCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..." bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DCCREV,DCC Revision IDNOTE: For SR1.0 physical addresses. see" line.long 0x08 "DCCCNTSEED0,Count0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x08 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)" line.long 0x0C "DCCVALIDSEED0,Valid0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x0C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x10 "DCCCNTSEED1,Count1 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x10 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)" line.long 0x14 "DCCSTAT,DCC Status RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long 0x14 2.--31. 1. "RES," bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag" newline bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occurred" "no effect,clear the error flag" line.long 0x18 "DCCCNT0,Count0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x18 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0" line.long 0x1C "DCCVALID0,Valid0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x1C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0" line.long 0x20 "DCCCNT1,Count1 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x20 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1" line.long 0x24 "DCCCLKSRC1,Clock Source Selection Register" hexmask.long.word 0x24 16.--31. 1. "RES0,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 4.--11. 1. "RES1,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 0.--3. "CLKSRC,This field specifies the clock source for COUNT1 when the KEY field enables this feature" "Clock source 0 is selected for COUNT1,Clock source 1 is selected for COUNT1,Clock source 2 is selected for COUNT1,Clock source 3 is selected for COUNT1,Clock source 4 is selected for COUNT1,Clock source 5 is selected for COUNT1,Clock source 6 is selected for COUNT1,Clock source 7 is selected for COUNT1,?..." line.long 0x28 "DCCCLKSRC0,Clock Source Selection Register" hexmask.long 0x28 4.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for COUNT0" "?,?,?,?,?,Clock0[2] is selected as source for COUNT0,?,?,?,?,Clock0[1] is selected as source for COUNT0,?..." width 0x0B tree.end tree "DCC6_TARG" base ad:0x48848000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC6_TARG_SR2" base ad:0x48853000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC7_SR2" base ad:0x48854000 group.long 0x00++0x2B line.long 0x00 "DCCGCTRL,DCC Global Control RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x00 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag inDCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..." bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DCCREV,DCC Revision IDNOTE: For SR1.0 physical addresses. see" line.long 0x08 "DCCCNTSEED0,Count0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x08 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)" line.long 0x0C "DCCVALIDSEED0,Valid0 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x0C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x10 "DCCCNTSEED1,Count1 Seed Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x10 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)" line.long 0x14 "DCCSTAT,DCC Status RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long 0x14 2.--31. 1. "RES," bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag" newline bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occurred" "no effect,clear the error flag" line.long 0x18 "DCCCNT0,Count0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x18 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0" line.long 0x1C "DCCVALID0,Valid0 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x1C 16.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0" line.long 0x20 "DCCCNT1,Count1 Value RegisterNOTE: For SR1.0 physical addresses. see" hexmask.long.word 0x20 20.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1" line.long 0x24 "DCCCLKSRC1,Clock Source Selection Register" hexmask.long.word 0x24 16.--31. 1. "RES0,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 4.--11. 1. "RES1,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x24 0.--3. "CLKSRC,This field specifies the clock source for COUNT1 when the KEY field enables this feature" "Clock source 0 is selected for COUNT1,Clock source 1 is selected for COUNT1,Clock source 2 is selected for COUNT1,Clock source 3 is selected for COUNT1,Clock source 4 is selected for COUNT1,Clock source 5 is selected for COUNT1,Clock source 6 is selected for COUNT1,Clock source 7 is selected for COUNT1,?..." line.long 0x28 "DCCCLKSRC0,Clock Source Selection Register" hexmask.long 0x28 4.--31. 1. "RES,User privilege and debug mode reads return 0 and writes have no effect" bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for COUNT0" "?,?,?,?,?,Clock0[2] is selected as source for COUNT0,?,?,?,?,Clock0[1] is selected as source for COUNT0,?..." width 0x0B tree.end tree "DCC7_TARG" base ad:0x4884A000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCC7_TARG_SR2" base ad:0x48855000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DEBUGSS_CT_TBR_FW" base ad:0x4A224000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x07 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" line.long 0x04 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x04 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x04 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x04 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "DEBUGSS_CT_TBR_FW_CFG_TARG" base ad:0x4A225000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DEBUGSS_CT_TBR_TARG" base ad:0x45000300 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "DEVICE_PRM" base ad:0x4AE07D00 group.long 0x00++0x103 line.long 0x00 "PRM_RSTCTRL,Global software cold and warm reset control" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "RST_GLOBAL_COLD_SW,Global COLD software reset control" "RST_GLOBAL_COLD_SW_0,RST_GLOBAL_COLD_SW_1" newline bitfld.long 0x00 0. "RST_GLOBAL_WARM_SW,Global WARM software reset control" "RST_GLOBAL_WARM_SW_0,RST_GLOBAL_WARM_SW_1" line.long 0x04 "PRM_RSTST,This register logs the global reset sources" hexmask.long.word 0x04 17.--31. 1. "RESERVED," bitfld.long 0x04 16. "TSHUT_IVA_RST,TSHUT_IVA warm reset event" "TSHUT_IVA_RST_0,TSHUT_IVA_RST_1" newline bitfld.long 0x04 15. "TSHUT_DSPEVE_RST,TSHUT_DSPEVE warm reset event" "TSHUT_DSPEVE_RST_0,TSHUT_DSPEVE_RST_1" bitfld.long 0x04 14. "LLI_RST,LLI warm reset event" "LLI_RST_0,LLI_RST_1" newline bitfld.long 0x04 13. "TSHUT_CORE_RST,TSHUT_CORE warm reset event" "TSHUT_CORE_RST_0,TSHUT_CORE_RST_1" bitfld.long 0x04 12. "TSHUT_MM_RST,TSHUT_GPU warm reset event" "TSHUT_MM_RST_0,TSHUT_MM_RST_1" newline bitfld.long 0x04 11. "TSHUT_MPU_RST,TSHUT_MPU warm reset event" "TSHUT_MPU_RST_0,TSHUT_MPU_RST_1" bitfld.long 0x04 10. "C2C_RST,C2C warm reset event" "C2C_RST_0,C2C_RST_1" newline bitfld.long 0x04 9. "ICEPICK_RST,IcePick reset event" "ICEPICK_RST_0,ICEPICK_RST_1" bitfld.long 0x04 8. "VDD_CORE_VOLT_MGR_RST,VDD_CORE voltage manager reset event This is a source of global WARM reset" "VDD_CORE_VOLT_MGR_RST_0,VDD_CORE_VOLT_MGR_RST_1" newline bitfld.long 0x04 7. "VDD_MM_VOLT_MGR_RST,VDD_MM voltage manager reset event This is a source of global WARM reset" "VDD_MM_VOLT_MGR_RST_0,VDD_MM_VOLT_MGR_RST_1" bitfld.long 0x04 6. "VDD_MPU_VOLT_MGR_RST,VDD_MPU voltage manager reset event This is a source of global WARM reset" "VDD_MPU_VOLT_MGR_RST_0,VDD_MPU_VOLT_MGR_RST_1" newline bitfld.long 0x04 5. "EXTERNAL_WARM_RST,External warm reset event" "EXTERNAL_WARM_RST_0,EXTERNAL_WARM_RST_1" bitfld.long 0x04 4. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 3. "MPU_WDT_RST,MPU Watchdog timer reset event" "MPU_WDT_RST_0,MPU_WDT_RST_1" bitfld.long 0x04 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 1. "GLOBAL_WARM_SW_RST,Global warm software reset event" "GLOBAL_WARM_SW_RST_0,GLOBAL_WARM_SW_RST_1" bitfld.long 0x04 0. "GLOBAL_COLD_RST,Power-on (cold) reset event" "GLOBAL_COLD_RST_0,GLOBAL_COLD_RST_1" line.long 0x08 "PRM_RSTTIME,Reset duration control" hexmask.long.tbyte 0x08 15.--31. 1. "RESERVED," bitfld.long 0x08 10.--14. "RSTTIME2,Power domain reset duration 2 in number of RM.SYSCLK clock cycles" "RSTTIME2_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline hexmask.long.word 0x08 0.--9. 1. "RSTTIME1,Global reset duration 1 in number of Func_32k_clk clock cycles" line.long 0x0C "PRM_CLKREQCTRL,This register allows controlling the CLKREQ signal towards SCRM" hexmask.long 0x0C 3.--31. 1. "RESERVED," bitfld.long 0x0C 0.--2. "CLKREQ_COND,Control upon which condition CLKREQ signal is de-asserted" "CLKREQ_COND_0,CLKREQ_COND_1,CLKREQ_COND_2,CLKREQ_COND_3,CLKREQ_COND_4,CLKREQ_COND_5,CLKREQ_COND_6,CLKREQ_COND_7" line.long 0x10 "PRM_VOLTCTRL,This register provides voltage domain management controls" hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED," bitfld.long 0x10 14. "VDD_MM_I2C_DISABLE,This bit allows disabling I2C interface with powerIC for MM voltage (for debug purpose only)" "VDD_MM_I2C_DISABLE_0,VDD_MM_I2C_DISABLE_1" newline bitfld.long 0x10 13. "VDD_MPU_I2C_DISABLE,This bit allows disabling I2C interface with powerIC for MPU voltage (for debug purpose only)" "VDD_MPU_I2C_DISABLE_0,VDD_MPU_I2C_DISABLE_1" bitfld.long 0x10 12. "VDD_CORE_I2C_DISABLE,This bit allows disabling I2C interface with powerIC for CORE voltage (for debug purpose only)" "VDD_CORE_I2C_DISABLE_0,VDD_CORE_I2C_DISABLE_1" newline rbitfld.long 0x10 10.--11. "RESERVED," "0,1,2,3" bitfld.long 0x10 9. "VDD_MM_PRESENCE,This bit control the presence of MM voltage in device" "VDD_MM_PRESENCE_0,VDD_MM_PRESENCE_1" newline bitfld.long 0x10 8. "VDD_MPU_PRESENCE,This bit control the presence of MPU voltage in device" "VDD_MPU_PRESENCE_0,VDD_MPU_PRESENCE_1" rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 4.--5. "AUTO_CTRL_VDD_MM_L,This bit field specifies the state to which the hardware can automatically transition the VDD_MM_L voltage domain" "AUTO_CTRL_VDD_MM_L_0,AUTO_CTRL_VDD_MM_L_1,AUTO_CTRL_VDD_MM_L_2,AUTO_CTRL_VDD_MM_L_3" bitfld.long 0x10 2.--3. "AUTO_CTRL_VDD_MPU_L,This bit field specifies the state to which the hardware can automatically transition the VDD_MPU_L voltage domain" "AUTO_CTRL_VDD_MPU_L_0,AUTO_CTRL_VDD_MPU_L_1,AUTO_CTRL_VDD_MPU_L_2,AUTO_CTRL_VDD_MPU_L_3" newline bitfld.long 0x10 0.--1. "AUTO_CTRL_VDD_CORE_L,This bit field specifies the state to which the hardware can automatically transition the VDD_CORE_L voltage domain" "AUTO_CTRL_VDD_CORE_L_0,AUTO_CTRL_VDD_CORE_L_1,AUTO_CTRL_VDD_CORE_L_2,AUTO_CTRL_VDD_CORE_L_3" line.long 0x14 "PRM_PWRREQCTRL,This register allows controlling the PWRREQ signal towards power IC" hexmask.long 0x14 2.--31. 1. "RESERVED," bitfld.long 0x14 0.--1. "PWRREQ_COND,Control upon which condition from MPU MM and CORE voltage domains PWRREQ is de-asserted" "PWRREQ_COND_0,PWRREQ_COND_1,PWRREQ_COND_2,PWRREQ_COND_3" line.long 0x18 "PRM_PSCON_COUNT,This register allows controlling 2 parameters for power state controller" hexmask.long.byte 0x18 24.--31. 1. "RESERVED," hexmask.long.byte 0x18 16.--23. 1. "HG_PONOUT_2_PGOODIN_TIME,The value 'NbCycles' set in this field determines the duration of the PONOUT to PGOODIN transition for power domain without DPS" newline hexmask.long.byte 0x18 8.--15. 1. "PONOUT_2_PGOODIN_TIME,The value 'NbCycles' set in this field determines the duration of the PONOUT to PGOODIN transition for power domain without DPS" hexmask.long.byte 0x18 0.--7. 1. "PCHARGE_TIME,Number of system clock cycles for the SRAM pre-charge duration" line.long 0x1C "PRM_IO_COUNT,This register allows controlling DDR IO isolation removal setup" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," hexmask.long.byte 0x1C 0.--7. 1. "ISO_2_ON_TIME,Determines the setup time of the DDR IOs going out of isolation" line.long 0x20 "PRM_IO_PMCTRL,This register allows controlling power management features of the IOs" hexmask.long.word 0x20 17.--31. 1. "RESERVED," bitfld.long 0x20 16. "GLOBAL_WUEN,Global IO wakeup enable" "GLOBAL_WUEN_0,GLOBAL_WUEN_1" newline rbitfld.long 0x20 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x20 9. "WUCLK_STATUS,Gives value of WUCLKOUT signal coming back from IO pad ring" "0,1" newline bitfld.long 0x20 8. "WUCLK_CTRL,Direct control on WUCLKIN signal to IO pad ring" "WUCLK_CTRL_0,WUCLK_CTRL_1" rbitfld.long 0x20 6.--7. "RESERVED," "0,1,2,3" newline rbitfld.long 0x20 5. "IO_ON_STATUS,Gives the functional status of the IO ring" "IO_ON_STATUS_0,IO_ON_STATUS_1" bitfld.long 0x20 4. "ISOOVR_EXTEND,Control non-EMIF IO isolation extension upon a device wakeup from OFF mode" "ISOOVR_EXTEND_0,ISOOVR_EXTEND_1" newline rbitfld.long 0x20 2.--3. "RESERVED," "0,1,2,3" rbitfld.long 0x20 1. "ISOCLK_STATUS,Gives value of ISOCLKOUT signal coming back from IO pad ring" "0,1" newline bitfld.long 0x20 0. "ISOCLK_OVERRIDE,Override control on ISOCLKIN signal to IO pad ring" "ISOCLK_OVERRIDE_0,ISOCLK_OVERRIDE_1" line.long 0x24 "PRM_VOLTSETUP_WARMRESET,This register provides bit-fields for specifying voltage stabilization duration upon a global warm reset" hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED," bitfld.long 0x24 8.--9. "STABLE_PRESCAL,Determines prescaler for stabilization duration counting" "STABLE_PRESCAL_0,STABLE_PRESCAL_1,STABLE_PRESCAL_2,STABLE_PRESCAL_3" newline rbitfld.long 0x24 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x24 0.--5. "STABLE_COUNT,Determines the stabilization duration of all VDD_xxx_L regulators upon a global warm reset assertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "PRM_VOLTSETUP_CORE_OFF,This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators" rbitfld.long 0x28 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 24.--25. "RAMP_DOWN_PRESCAL,Determines prescaler for ramp-down duration counting" "RAMP_DOWN_PRESCAL_0,RAMP_DOWN_PRESCAL_1,RAMP_DOWN_PRESCAL_2,RAMP_DOWN_PRESCAL_3" newline rbitfld.long 0x28 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x28 16.--21. "RAMP_DOWN_COUNT,Determines the ramp-down duration of VDD_CORE_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x28 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 8.--9. "RAMP_UP_PRESCAL,Determines prescaler for ramp-up duration counting" "RAMP_UP_PRESCAL_0,RAMP_UP_PRESCAL_1,RAMP_UP_PRESCAL_2,RAMP_UP_PRESCAL_3" newline rbitfld.long 0x28 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x28 0.--5. "RAMP_UP_COUNT,Determines the ramp-up duration of VDD_CORE_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "PRM_VOLTSETUP_MPU_OFF,This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators" rbitfld.long 0x2C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 24.--25. "RAMP_DOWN_PRESCAL,Determines prescaler for ramp-down duration counting" "RAMP_DOWN_PRESCAL_0,RAMP_DOWN_PRESCAL_1,RAMP_DOWN_PRESCAL_2,RAMP_DOWN_PRESCAL_3" newline rbitfld.long 0x2C 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x2C 16.--21. "RAMP_DOWN_COUNT,Determines the ramp-down duration of VDD_MPU_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x2C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 8.--9. "RAMP_UP_PRESCAL,Determines prescaler for ramp-up duration counting" "RAMP_UP_PRESCAL_0,RAMP_UP_PRESCAL_1,RAMP_UP_PRESCAL_2,RAMP_UP_PRESCAL_3" newline rbitfld.long 0x2C 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x2C 0.--5. "RAMP_UP_COUNT,Determines the ramp-up duration of VDD_MPU_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x30 "PRM_VOLTSETUP_MM_OFF,This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators" rbitfld.long 0x30 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 24.--25. "RAMP_DOWN_PRESCAL,Determines prescaler for ramp-down duration counting" "RAMP_DOWN_PRESCAL_0,RAMP_DOWN_PRESCAL_1,RAMP_DOWN_PRESCAL_2,RAMP_DOWN_PRESCAL_3" newline rbitfld.long 0x30 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x30 16.--21. "RAMP_DOWN_COUNT,Determines the ramp-down duration of VDD_MM_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x30 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 8.--9. "RAMP_UP_PRESCAL,Determines prescaler for ramp-up duration counting" "RAMP_UP_PRESCAL_0,RAMP_UP_PRESCAL_1,RAMP_UP_PRESCAL_2,RAMP_UP_PRESCAL_3" newline rbitfld.long 0x30 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x30 0.--5. "RAMP_UP_COUNT,Determines the ramp-up duration of VDD_MM_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x34 "PRM_VOLTSETUP_CORE_RET_SLEEP,This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators" rbitfld.long 0x34 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 24.--25. "RAMP_DOWN_PRESCAL,Determines prescaler for ramp-down duration counting" "RAMP_DOWN_PRESCAL_0,RAMP_DOWN_PRESCAL_1,RAMP_DOWN_PRESCAL_2,RAMP_DOWN_PRESCAL_3" newline rbitfld.long 0x34 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x34 16.--21. "RAMP_DOWN_COUNT,Determines the ramp-down duration of VDD_CORE_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x34 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 8.--9. "RAMP_UP_PRESCAL,Determines prescaler for ramp-up duration counting" "RAMP_UP_PRESCAL_0,RAMP_UP_PRESCAL_1,RAMP_UP_PRESCAL_2,RAMP_UP_PRESCAL_3" newline rbitfld.long 0x34 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x34 0.--5. "RAMP_UP_COUNT,Determines the ramp-up duration of VDD_CORE_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "PRM_VOLTSETUP_MPU_RET_SLEEP,This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators" rbitfld.long 0x38 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 24.--25. "RAMP_DOWN_PRESCAL,Determines prescaler for ramp-down duration counting" "RAMP_DOWN_PRESCAL_0,RAMP_DOWN_PRESCAL_1,RAMP_DOWN_PRESCAL_2,RAMP_DOWN_PRESCAL_3" newline rbitfld.long 0x38 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x38 16.--21. "RAMP_DOWN_COUNT,Determines the ramp-down duration of VDD_MPU_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x38 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 8.--9. "RAMP_UP_PRESCAL,Determines prescaler for ramp-up duration counting" "RAMP_UP_PRESCAL_0,RAMP_UP_PRESCAL_1,RAMP_UP_PRESCAL_2,RAMP_UP_PRESCAL_3" newline rbitfld.long 0x38 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x38 0.--5. "RAMP_UP_COUNT,Determines the ramp-up duration of VDD_MPU_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x3C "PRM_VOLTSETUP_MM_RET_SLEEP,This register provides bit-fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators" rbitfld.long 0x3C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 24.--25. "RAMP_DOWN_PRESCAL,Determines prescaler for ramp-down duration counting" "RAMP_DOWN_PRESCAL_0,RAMP_DOWN_PRESCAL_1,RAMP_DOWN_PRESCAL_2,RAMP_DOWN_PRESCAL_3" newline rbitfld.long 0x3C 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x3C 16.--21. "RAMP_DOWN_COUNT,Determines the ramp-down duration of VDD_MM_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x3C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 8.--9. "RAMP_UP_PRESCAL,Determines prescaler for ramp-up duration counting" "RAMP_UP_PRESCAL_0,RAMP_UP_PRESCAL_1,RAMP_UP_PRESCAL_2,RAMP_UP_PRESCAL_3" newline rbitfld.long 0x3C 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x3C 0.--5. "RAMP_UP_COUNT,Determines the ramp-up duration of VDD_MM_L regulators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "PRM_VP_CORE_CONFIG,This register allows the configuration of the Voltage Processor dedicated to CORE Voltage Domain (VDD_CORE_L)" hexmask.long.byte 0x40 24.--31. 1. "ERROROFFSET,Offset value in the Error to Voltage converter (two's complement number)" hexmask.long.byte 0x40 16.--23. 1. "ERRORGAIN,Gain value in the Error to Voltage converter (two's complement number)" newline hexmask.long.byte 0x40 8.--15. 1. "INITVOLTAGE,Set the initial voltage level of the SMPS" rbitfld.long 0x40 4.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x40 3. "TIMEOUTEN,Enable or disable the timeout capability of the Voltage Controller State Machine" "TIMEOUTEN_0,TIMEOUTEN_1" bitfld.long 0x40 2. "INITVDD,Initializes the voltage in the Voltage Processor" "INITVDD_0,INITVDD_1" newline bitfld.long 0x40 1. "FORCEUPDATE,Forces an update of the SMPS" "FORCEUPDATE_0,FORCEUPDATE_1" bitfld.long 0x40 0. "ISSNABLE,Enables or disables the Voltage Processor updates on SR_SInterruptz" "ISSNABLE_0,ISSNABLE_1" line.long 0x44 "PRM_VP_CORE_STATUS,This register reflects the idle state of the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L. This register is read only and automatically updated" hexmask.long 0x44 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x44 0. "VPINIDLE,CORE Voltage Processor idle status" "VPINIDLE_0,VPINIDLE_1" line.long 0x48 "PRM_VP_CORE_VLIMITTO,This register allows the configuration of the voltage limits and timeout values of the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L)" hexmask.long.byte 0x48 24.--31. 1. "VDDMAX,Defines the maximum voltage supply level" hexmask.long.byte 0x48 16.--23. 1. "VDDMIN,Defines the minimum voltage supply level" newline hexmask.long.word 0x48 0.--15. 1. "TIMEOUT,Defines Voltage Controller maximum wait time for responses" line.long 0x4C "PRM_VP_CORE_VOLTAGE,This register indicates the current value of the SMPS voltage for the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L)" hexmask.long.tbyte 0x4C 8.--31. 1. "FORCEUPDATEWAIT,The time voltage processor needs to wait for SMPS to be settled after receiving SMPS acknowledge" hexmask.long.byte 0x4C 0.--7. 1. "VPVOLTAGE,Indicates the current SMPS programmed voltage" line.long 0x50 "PRM_VP_CORE_VSTEPMAX,This register allows the programming of the maximum voltage step and waiting time of the Voltage Processor dedicated to CORE Voltage Domain (VDD_CORE_L)" hexmask.long.byte 0x50 24.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x50 8.--23. 1. "SMPSWAITTIMEMAX,Slew rate for positive voltage step (in number of cycles per step)" newline hexmask.long.byte 0x50 0.--7. 1. "VSTEPMAX,Maximum voltage step" line.long 0x54 "PRM_VP_CORE_VSTEPMIN,This register allows the programming of the minimum voltage step and waiting time of the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L)" hexmask.long.byte 0x54 24.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x54 8.--23. 1. "SMPSWAITTIMEMIN,Slew rate for negative voltage step (in number of cycles per step)" newline hexmask.long.byte 0x54 0.--7. 1. "VSTEPMIN,Minimum voltage step" line.long 0x58 "PRM_VP_MPU_CONFIG,This register allows the configuration of the Voltage Processor dedicated to MPU Voltage Domain (VDD_MPU_L)" hexmask.long.byte 0x58 24.--31. 1. "ERROROFFSET,Offset value in the Error to Voltage converter (two's complement number)" hexmask.long.byte 0x58 16.--23. 1. "ERRORGAIN,Gain value in the Error to Voltage converter (two's complement number)" newline hexmask.long.byte 0x58 8.--15. 1. "INITVOLTAGE,Set the initial voltage level of the SMPS" rbitfld.long 0x58 4.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x58 3. "TIMEOUTEN,Enable or disable the timeout capability of the Voltage Controller State Machine" "TIMEOUTEN_0,TIMEOUTEN_1" bitfld.long 0x58 2. "INITVDD,Initializes the voltage in the Voltage Processor" "INITVDD_0,INITVDD_1" newline bitfld.long 0x58 1. "FORCEUPDATE,Forces an update of the SMPS" "FORCEUPDATE_0,FORCEUPDATE_1" bitfld.long 0x58 0. "ISSNABLE,Enables or disables the Voltage Processor updates on SR_SInterruptz" "ISSNABLE_0,ISSNABLE_1" line.long 0x5C "PRM_VP_MPU_STATUS,This register reflects the idle state of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L. This register is read only and automatically updated" hexmask.long 0x5C 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x5C 0. "VPINIDLE,Voltage Processor 1 idle status" "VPINIDLE_0,VPINIDLE_1" line.long 0x60 "PRM_VP_MPU_VLIMITTO,This register allows the configuration of the voltage limits and timeout values of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L)" hexmask.long.byte 0x60 24.--31. 1. "VDDMAX,Defines the maximum voltage supply level" hexmask.long.byte 0x60 16.--23. 1. "VDDMIN,Defines the minimum voltage supply level" newline hexmask.long.word 0x60 0.--15. 1. "TIMEOUT,Defines Voltage Controller maximum wait time for responses" line.long 0x64 "PRM_VP_MPU_VOLTAGE,This register indicates the current value of the SMPS voltage for the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L)" hexmask.long.tbyte 0x64 8.--31. 1. "FORCEUPDATEWAIT,The time voltage processor needs to wait for SMPS to be settled after receiving SMPS acknowledge" hexmask.long.byte 0x64 0.--7. 1. "VPVOLTAGE,Indicates the current SMPS programmed voltage" line.long 0x68 "PRM_VP_MPU_VSTEPMAX,This register allows the programming of the maximum voltage step and waiting time of the Voltage Processor dedicated to MPU Voltage Domain (VDD_MPU_L)" hexmask.long.byte 0x68 24.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x68 8.--23. 1. "SMPSWAITTIMEMAX,Slew rate for positive voltage step (in number of cycles per step)" newline hexmask.long.byte 0x68 0.--7. 1. "VSTEPMAX,Maximum voltage step" line.long 0x6C "PRM_VP_MPU_VSTEPMIN,This register allows the programming of the minimum voltage step and waiting time of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L)" hexmask.long.byte 0x6C 24.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x6C 8.--23. 1. "SMPSWAITTIMEMIN,Slew rate for negative voltage step (in number of cycles per step)" newline hexmask.long.byte 0x6C 0.--7. 1. "VSTEPMIN,Minimum voltage step" line.long 0x70 "PRM_VP_MM_CONFIG,This register allows the configuration of the Voltage Processor dedicated to MM Voltage Domain (VDD_MM_L)" hexmask.long.byte 0x70 24.--31. 1. "ERROROFFSET,Offset value in the Error to Voltage converter (two's complement number)" hexmask.long.byte 0x70 16.--23. 1. "ERRORGAIN,Gain value in the Error to Voltage converter (two's complement number)" newline hexmask.long.byte 0x70 8.--15. 1. "INITVOLTAGE,Set the initial voltage level of the SMPS" rbitfld.long 0x70 4.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x70 3. "TIMEOUTEN,Enable or disable the timeout capability of the Voltage Controller State Machine" "TIMEOUTEN_0,TIMEOUTEN_1" bitfld.long 0x70 2. "INITVDD,Initializes the voltage in the Voltage Processor" "INITVDD_0,INITVDD_1" newline bitfld.long 0x70 1. "FORCEUPDATE,Forces an update of the SMPS" "FORCEUPDATE_0,FORCEUPDATE_1" bitfld.long 0x70 0. "ISSNABLE,Enables or disables the Voltage Processor updates on SR_SInterruptz" "ISSNABLE_0,ISSNABLE_1" line.long 0x74 "PRM_VP_MM_STATUS,This register reflects the idle state of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MM_L. This register is read only and automatically updated" hexmask.long 0x74 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x74 0. "VPINIDLE,Voltage Processor 1 idle status" "VPINIDLE_0,VPINIDLE_1" line.long 0x78 "PRM_VP_MM_VLIMITTO,This register allows the configuration of the voltage limits and timeout values of the Voltage Processor dedicated to the MM voltage Domain (VDD_MM_L)" hexmask.long.byte 0x78 24.--31. 1. "VDDMAX,Defines the maximum voltage supply level" hexmask.long.byte 0x78 16.--23. 1. "VDDMIN,Defines the minimum voltage supply level" newline hexmask.long.word 0x78 0.--15. 1. "TIMEOUT,Defines Voltage Controller maximum wait time for responses" line.long 0x7C "PRM_VP_MM_VOLTAGE,This register indicates the current value of the SMPS voltage for the Voltage Processor dedicated to the MM voltage Domain (VDD_MM_L)" hexmask.long.tbyte 0x7C 8.--31. 1. "FORCEUPDATEWAIT,The time voltage processor needs to wait for SMPS to be settled after receiving SMPS acknowledge" hexmask.long.byte 0x7C 0.--7. 1. "VPVOLTAGE,Indicates the current SMPS programmed voltage" line.long 0x80 "PRM_VP_MM_VSTEPMAX,This register allows the programming of the maximum voltage step and waiting time of the Voltage Processor dedicated to MM voltage Domain (VDD_MM_L)" hexmask.long.byte 0x80 24.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x80 8.--23. 1. "SMPSWAITTIMEMAX,Slew rate for positive voltage step (in number of cycles per step)" newline hexmask.long.byte 0x80 0.--7. 1. "VSTEPMAX,Maximum voltage step" line.long 0x84 "PRM_VP_MM_VSTEPMIN,This register allows the programming of the minimum voltage step and waiting time of the Voltage Processor dedicated to the MM voltage Domain (VDD_MM_L)" hexmask.long.byte 0x84 24.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x84 8.--23. 1. "SMPSWAITTIMEMIN,Slew rate for negative voltage step (in number of cycles per step)" newline hexmask.long.byte 0x84 0.--7. 1. "VSTEPMIN,Minimum voltage step" line.long 0x88 "PRM_VC_SMPS_CORE_CONFIG,This register allows the setting of the I2C slave address of the Power IC device. the setting of the voltage configuration register address for the CORE VDD and the Command (ON/ON-Low-Power/Retention/OFF) configuration register.." rbitfld.long 0x88 29.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x88 28. "CMD_VDD_CORE_L,Command values (ON/ON-Low-Power/Retention/OFF voltage values) set selection for VDD_CORE_L channel" "CMD_VDD_CORE_L_0,CMD_VDD_CORE_L_1" newline bitfld.long 0x88 27. "RACEN_VDD_CORE_L,Enable bit for usage of RAC_VDD_CORE_L" "RACEN_VDD_CORE_L_0,RACEN_VDD_CORE_L_1" bitfld.long 0x88 26. "RAC_VDD_CORE_L,Command (ON/ON-Low-Power/Retention/OFF) configuration register address pointer for VDD_CORE_L channel" "RAC_VDD_CORE_L_0,RAC_VDD_CORE_L_1" newline bitfld.long 0x88 25. "RAV_VDD_CORE_L,Voltage configuration register address pointer for VDD_CORE_L channel" "RAV_VDD_CORE_L_0,RAV_VDD_CORE_L_1" bitfld.long 0x88 24. "SEL_SA_VDD_CORE_L,Slave address pointer for VDD_CORE_L channel" "SEL_SA_VDD_CORE_L_0,SEL_SA_VDD_CORE_L_1" newline hexmask.long.byte 0x88 16.--23. 1. "CMDRA_VDD_CORE_L,Command (ON/ON-Low-Power /Retention/OFF) configuration register address value for VDD_CORE_L channel.(if VDD_CORE_L source has different command configuration register than voltage VDD_MPU_L)" hexmask.long.byte 0x88 8.--15. 1. "VOLRA_VDD_CORE_L,Set the voltage configuration register address value for the VDD_CORE_L channel (if VDD_CORE_L source is placed in same chip as VDD_MPU_L source and have different voltage configuration register)" newline rbitfld.long 0x88 7. "RESERVED,Write 0's for future compatibility" "0,1" hexmask.long.byte 0x88 0.--6. 1. "SA_VDD_CORE_L,Set the I2C slave address value for the first Power IC device" line.long 0x8C "PRM_VC_SMPS_MM_CONFIG,This register allows the setting of the I2C slave address of the Power IC device. the setting of the voltage configuration register address for the MM VDD and the Command (ON/ON-Low-Power/Retention/OFF) configuration register.." rbitfld.long 0x8C 29.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x8C 28. "CMD_VDD_MM_L,Command values (ON/ON-Low-Power/Retention/OFF voltage values) set selection for VDD_MM_L channel" "CMD_VDD_MM_L_0,CMD_VDD_MM_L_1" newline bitfld.long 0x8C 27. "RACEN_VDD_MM_L,Enable bit for usage of RAC_VDD_MM_L" "RACEN_VDD_MM_L_0,RACEN_VDD_MM_L_1" bitfld.long 0x8C 26. "RAC_VDD_MM_L,Command (ON/ON-Low-Power/Retention/OFF) configuration register address pointer for VDD_MM_L channel" "RAC_VDD_MM_L_0,RAC_VDD_MM_L_1" newline bitfld.long 0x8C 25. "RAV_VDD_MM_L,Voltage configuration register address pointer for VDD_MM_L channel" "RAV_VDD_MM_L_0,RAV_VDD_MM_L_1" bitfld.long 0x8C 24. "SEL_SA_VDD_MM_L,Slave address pointer for VDD_MM_L channel" "SEL_SA_VDD_MM_L_0,SEL_SA_VDD_MM_L_1" newline hexmask.long.byte 0x8C 16.--23. 1. "CMDRA_VDD_MM_L,Command (ON/ON-Low-Power /Retention/OFF) configuration register address value for VDD_MM_L channel (if VDD_MM_L source has different command configuration register than voltage VDD_MPU_L)" hexmask.long.byte 0x8C 8.--15. 1. "VOLRA_VDD_MM_L,Voltage configuration register address value for VDD_MM_L channel (if VDD_MM_L source is placed in same chip as VDD_MPU_L source and have different voltage configuration register)" newline rbitfld.long 0x8C 7. "RESERVED,Write 0's for future compatibility" "0,1" hexmask.long.byte 0x8C 0.--6. 1. "SA_VDD_MM_L,Set the I2C slave address value for the second (if any) Power IC device" line.long 0x90 "PRM_VC_SMPS_MPU_CONFIG,This register allows the setting of the I2C slave address of the Power IC device. the setting of the voltage configuration register address for the MPU VDD and the Command (ON/ON-Low-Power/Retention/OFF) configuration register.." rbitfld.long 0x90 29.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x90 28. "CMD_VDD_MPU_L,Command values (ON/ON-Low-Power/Retention/OFF voltage values) set selection for VDD_MPU_L channel (This bit has no influence on VDD_MPU_L channel)" "0,1" newline bitfld.long 0x90 27. "RACEN_VDD_MPU_L,Enable bit for usage of RAC_VDD_MPU_L" "RACEN_VDD_MPU_L_0,RACEN_VDD_MPU_L_1" bitfld.long 0x90 26. "RAC_VDD_MPU_L,Command (ON/ON-Low-Power/Retention/OFF) configuration register address pointer for VDD_MPU_L channel" "0,1" newline bitfld.long 0x90 25. "RAV_VDD_MPU_L,Voltage configuration register address pointer for VDD_MPU_L channel" "0,1" bitfld.long 0x90 24. "SEL_SA_VDD_MPU_L,Slave address pointer for VDD_MPU_L channel" "0,1" newline hexmask.long.byte 0x90 16.--23. 1. "CMDRA_VDD_MPU_L,Command (ON/ON-Low-Power /Retention/OFF) configuration register address value for VDD_MPU_L channel" hexmask.long.byte 0x90 8.--15. 1. "VOLRA_VDD_MPU_L,Voltage configuration register address value for VDD_MPU_L channel" newline rbitfld.long 0x90 7. "RESERVED,Write 0's for future compatibility" "0,1" hexmask.long.byte 0x90 0.--6. 1. "SA_VDD_MPU_L,Set the I2C slave address value for the third (if any) Power IC device" line.long 0x94 "PRM_VC_VAL_CMD_VDD_CORE_L,This register allows the setting of the ON/ON-Low-Power/Retention/OFF command values for VDD_CORE_L channel" hexmask.long.byte 0x94 24.--31. 1. "ON,Set the ON command value" hexmask.long.byte 0x94 16.--23. 1. "ONLP,Set the ON-Low-Power command value" newline hexmask.long.byte 0x94 8.--15. 1. "RET,Set the RET command value" hexmask.long.byte 0x94 0.--7. 1. "OFF,Set the OFF command value" line.long 0x98 "PRM_VC_VAL_CMD_VDD_MM_L,This register allows the setting of the ON/ON-Low-Power/Retention/OFF command values for VDD_MM_L channel" hexmask.long.byte 0x98 24.--31. 1. "ON,Set the ON command value" hexmask.long.byte 0x98 16.--23. 1. "ONLP,Set the ON-Low-Power command value" newline hexmask.long.byte 0x98 8.--15. 1. "RET,Set the RET command value" hexmask.long.byte 0x98 0.--7. 1. "OFF,Set the OFF command value" line.long 0x9C "PRM_VC_VAL_CMD_VDD_MPU_L,This register allows the setting of the ON/ON-Low-Power/Retention/OFF command values for VDD_MPU_L channel" hexmask.long.byte 0x9C 24.--31. 1. "ON,Set the ON command value" hexmask.long.byte 0x9C 16.--23. 1. "ONLP,Set the ON-Low-Power command value" newline hexmask.long.byte 0x9C 8.--15. 1. "RET,Set the RET command value" hexmask.long.byte 0x9C 0.--7. 1. "OFF,Set the OFF command value" line.long 0xA0 "PRM_VC_VAL_BYPASS,Bypass data values register used for bypass command channel to send other configuration information (other then voltage configuration parameters) for SMPS chips which have no other configuration interface then this I2C interface and.." rbitfld.long 0xA0 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA0 25. "OPP_CHANGE_EMIF_LVL,This bit controls read-write leveling of EMIF memories (DDR3)" "OPP_CHANGE_EMIF_LVL_0,OPP_CHANGE_EMIF_LVL_1" newline bitfld.long 0xA0 24. "VALID,This bit validates the bypass command" "VALID_0,VALID_1" hexmask.long.byte 0xA0 16.--23. 1. "DATA,Data to send to the Power IC device" newline hexmask.long.byte 0xA0 8.--15. 1. "REGADDR,Set the address of Power IC device register to configure" rbitfld.long 0xA0 7. "RESERVED," "0,1" newline hexmask.long.byte 0xA0 0.--6. 1. "SLAVEADDR,Set the I2C slave address value" line.long 0xA4 "PRM_VC_CORE_ERRST,This debug register logs CORE related error status coming from Voltage Controller" hexmask.long 0xA4 6.--31. 1. "RESERVED," bitfld.long 0xA4 5. "VFSM_TIMEOUT_ERR_CORE,CORE voltage FSM command frame is finished but is not acknowledged by the slave or (I2C multimaster) arbitration lost" "VFSM_TIMEOUT_ERR_CORE_0,VFSM_TIMEOUT_ERR_CORE_1" newline bitfld.long 0xA4 4. "VFSM_RA_ERR_CORE,Wrong register address error for CORE voltage FSM" "VFSM_RA_ERR_CORE_0,VFSM_RA_ERR_CORE_1" bitfld.long 0xA4 3. "VFSM_SA_ERR_CORE,Wrong slave address error for CORE voltage FSM" "VFSM_SA_ERR_CORE_0,VFSM_SA_ERR_CORE_1" newline bitfld.long 0xA4 2. "SMPS_TIMEOUT_ERR_CORE,CORE voltage processor command frame is finished but is not acknowledged by the slave or (I2C multimaster) arbitration lost" "SMPS_TIMEOUT_ERR_CORE_0,SMPS_TIMEOUT_ERR_CORE_1" bitfld.long 0xA4 1. "SMPS_RA_ERR_CORE,Wrong register address error for CORE voltage processor" "SMPS_RA_ERR_CORE_0,SMPS_RA_ERR_CORE_1" newline bitfld.long 0xA4 0. "SMPS_SA_ERR_CORE,Wrong slave address error for CORE voltage processor" "SMPS_SA_ERR_CORE_0,SMPS_SA_ERR_CORE_1" line.long 0xA8 "PRM_VC_MM_ERRST,This debug register logs MM related error status coming from Voltage Controller" hexmask.long 0xA8 6.--31. 1. "RESERVED," bitfld.long 0xA8 5. "VFSM_TIMEOUT_ERR_MM,MM voltage FSM command frame is finished but is not acknowledged by the slave or (I2C multimaster) arbitration lost" "VFSM_TIMEOUT_ERR_MM_0,VFSM_TIMEOUT_ERR_MM_1" newline bitfld.long 0xA8 4. "VFSM_RA_ERR_MM,Wrong register address error for MM voltage FSM" "VFSM_RA_ERR_MM_0,VFSM_RA_ERR_MM_1" bitfld.long 0xA8 3. "VFSM_SA_ERR_MM,Wrong slave address error for MM voltage FSM" "VFSM_SA_ERR_MM_0,VFSM_SA_ERR_MM_1" newline bitfld.long 0xA8 2. "SMPS_TIMEOUT_ERR_MM,MM voltage processor command frame is finished but is not acknowledged by the slave or (I2C multimaster) arbitration lost" "SMPS_TIMEOUT_ERR_MM_0,SMPS_TIMEOUT_ERR_MM_1" bitfld.long 0xA8 1. "SMPS_RA_ERR_MM,Wrong register address error for MM voltage processor" "SMPS_RA_ERR_MM_0,SMPS_RA_ERR_MM_1" newline bitfld.long 0xA8 0. "SMPS_SA_ERR_MM,Wrong slave address error for MM voltage processor" "SMPS_SA_ERR_MM_0,SMPS_SA_ERR_MM_1" line.long 0xAC "PRM_VC_MPU_ERRST,This debug register logs MPU related error status coming from Voltage Controller" hexmask.long 0xAC 6.--31. 1. "RESERVED," bitfld.long 0xAC 5. "VFSM_TIMEOUT_ERR_MPU,MPU voltage FSM command frame is finished but is not acknowledged by the slave or (I2C multimaster) arbitration lost" "VFSM_TIMEOUT_ERR_MPU_0,VFSM_TIMEOUT_ERR_MPU_1" newline bitfld.long 0xAC 4. "VFSM_RA_ERR_MPU,Wrong register address error for MPU voltage FSM" "VFSM_RA_ERR_MPU_0,VFSM_RA_ERR_MPU_1" bitfld.long 0xAC 3. "VFSM_SA_ERR_MPU,Wrong slave address error for MPU voltage FSM" "VFSM_SA_ERR_MPU_0,VFSM_SA_ERR_MPU_1" newline bitfld.long 0xAC 2. "SMPS_TIMEOUT_ERR_MPU,MPU voltage processor command frame is finished but is not acknowledged by the slave or (I2C multimaster) arbitration lost" "SMPS_TIMEOUT_ERR_MPU_0,SMPS_TIMEOUT_ERR_MPU_1" bitfld.long 0xAC 1. "SMPS_RA_ERR_MPU,Wrong register address error for MPU voltage processor" "SMPS_RA_ERR_MPU_0,SMPS_RA_ERR_MPU_1" newline bitfld.long 0xAC 0. "SMPS_SA_ERR_MPU,Wrong slave address error for MPU voltage processor" "SMPS_SA_ERR_MPU_0,SMPS_SA_ERR_MPU_1" line.long 0xB0 "PRM_VC_BYPASS_ERRST,This debug register logs BYPASS related error status coming from Voltage Controller" hexmask.long 0xB0 3.--31. 1. "RESERVED," bitfld.long 0xB0 2. "BYPS_TIMEOUT_ERR,BYPASS command frame is finished but is not acknowledged by the slave or (I2C multimaster) arbitration lost" "BYPS_TIMEOUT_ERR_0,BYPS_TIMEOUT_ERR_1" newline bitfld.long 0xB0 1. "BYPS_RA_ERR,Wrong register address error for BYPASS command" "BYPS_RA_ERR_0,BYPS_RA_ERR_1" bitfld.long 0xB0 0. "BYPS_SA_ERR,Wrong slave address error for BYPASS command" "BYPS_SA_ERR_0,BYPS_SA_ERR_1" line.long 0xB4 "PRM_VC_CFG_I2C_MODE,I2C configuration register" hexmask.long 0xB4 7.--31. 1. "RESERVED," bitfld.long 0xB4 6. "DFILTEREN,This field enables double filter procedure for I2C input lines" "DFILTEREN_0,DFILTEREN_1" newline rbitfld.long 0xB4 5. "RESERVED," "0,1" bitfld.long 0xB4 4. "SRMODEEN,Enables the I2C repeated start operation mode (effect of holding the SCL and SDA lines low in effect blocking the I2C bus from losing arbitration between repeated start points)" "SRMODEEN_0,SRMODEEN_1" newline bitfld.long 0xB4 3. "HSMODEEN,Enables I2C bus High Speed mode" "HSMODEEN_0,HSMODEEN_1" bitfld.long 0xB4 0.--2. "HSMCODE,Master code value for I2C High Speed preamble transmission" "0,1,2,3,4,5,6,7" line.long 0xB8 "PRM_VC_CFG_I2C_CLK,I2C Interface clock configuration parameters" hexmask.long.byte 0xB8 24.--31. 1. "HSSCLL,Number of the system clock cycles necessary to count the low period of the I2C clock signal when the I2C interface runs in High-Speed mode of operation" hexmask.long.byte 0xB8 16.--23. 1. "HSSCLH,Number of the system clock cycles necessary to count the high period of the I2C clock signal when the I2C interface runs in High-Speed mode of operation" newline hexmask.long.byte 0xB8 8.--15. 1. "SCLL,Number of the system clock cycles necessary to count the low period of the I2C clock signal when the I2C interface runs in Fast mode of operation" hexmask.long.byte 0xB8 0.--7. 1. "SCLH,Number of the system clock cycles necessary to count the high period of the I2C clock signal when the I2C interface runs in Fast mode of operation" line.long 0xBC "PRM_SRAM_COUNT,Common setup for SRAM LDO transition counters" hexmask.long.byte 0xBC 24.--31. 1. "STARTUP_COUNT,Determines the start-up duration of SRAM and ABB LDO" hexmask.long.byte 0xBC 16.--23. 1. "SLPCNT_VALUE,Delay between retention/off assertion of last SRAM bank and SRAMALLRET signal to LDO is driven high" newline hexmask.long.byte 0xBC 8.--15. 1. "VSETUPCNT_VALUE,SRAM LDO rampup time from retention to active mode" rbitfld.long 0xBC 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0xBC 0.--5. "PCHARGECNT_VALUE,Delay between de-assertion of standby_rta_ret_on and standby_rta_ret_good" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0xC0 "PRM_SRAM_WKUP_SETUP,Setup of memory in WKUP voltage domain" hexmask.long 0xC0 1.--31. 1. "RESERVED," bitfld.long 0xC0 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0xC4 "PRM_SLDO_CORE_SETUP,Setup of the SRAM LDO for CORE voltage domain" hexmask.long.tbyte 0xC4 9.--31. 1. "RESERVED," bitfld.long 0xC4 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" newline bitfld.long 0xC4 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" bitfld.long 0xC4 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" newline bitfld.long 0xC4 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" bitfld.long 0xC4 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" newline bitfld.long 0xC4 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" bitfld.long 0xC4 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" newline bitfld.long 0xC4 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" bitfld.long 0xC4 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0xC8 "PRM_SLDO_CORE_CTRL,Control and status of the SRAM LDO for CORE voltage domain" hexmask.long.tbyte 0xC8 10.--31. 1. "RESERVED," bitfld.long 0xC8 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" newline bitfld.long 0xC8 8. "SRAMLDO_STATUS,SRAMLDO status" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" hexmask.long.byte 0xC8 1.--7. 1. "RESERVED," newline bitfld.long 0xC8 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,?" line.long 0xCC "PRM_SLDO_MPU_SETUP,Setup of the SRAM LDO for MPU voltage domain" hexmask.long.tbyte 0xCC 9.--31. 1. "RESERVED," bitfld.long 0xCC 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" newline bitfld.long 0xCC 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" bitfld.long 0xCC 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" newline bitfld.long 0xCC 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" bitfld.long 0xCC 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" newline bitfld.long 0xCC 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" bitfld.long 0xCC 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" newline bitfld.long 0xCC 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" bitfld.long 0xCC 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0xD0 "PRM_SLDO_MPU_CTRL,Control and status of the SRAM LDO for MPU voltage domain" hexmask.long.tbyte 0xD0 10.--31. 1. "RESERVED," rbitfld.long 0xD0 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" newline rbitfld.long 0xD0 8. "SRAMLDO_STATUS,SRAMLDO status" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" hexmask.long.byte 0xD0 1.--7. 1. "RESERVED," newline bitfld.long 0xD0 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,RETMODE_ENABLE_1" line.long 0xD4 "PRM_SLDO_GPU_SETUP,Setup of the SRAM LDO for GPU voltage domain" hexmask.long.tbyte 0xD4 9.--31. 1. "RESERVED," bitfld.long 0xD4 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" newline bitfld.long 0xD4 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" bitfld.long 0xD4 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" newline bitfld.long 0xD4 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" bitfld.long 0xD4 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" newline bitfld.long 0xD4 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" bitfld.long 0xD4 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" newline bitfld.long 0xD4 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" bitfld.long 0xD4 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0xD8 "PRM_SLDO_GPU_CTRL,Control and status of the SRAM LDO for GPU voltage domain" hexmask.long.tbyte 0xD8 10.--31. 1. "RESERVED," rbitfld.long 0xD8 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" newline rbitfld.long 0xD8 8. "SRAMLDO_STATUS,SRAMLDO status" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" hexmask.long.byte 0xD8 1.--7. 1. "RESERVED," newline bitfld.long 0xD8 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,RETMODE_ENABLE_1" line.long 0xDC "PRM_ABBLDO_MPU_SETUP,Selects the MPU_ABB LDO mode" hexmask.long.word 0xDC 16.--31. 1. "RESERVED," hexmask.long.byte 0xDC 8.--15. 1. "SR2_WTCNT_VALUE,LDO settling time for active-mode OPP change" newline rbitfld.long 0xDC 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0xDC 4. "NOCAP,Defines whether ABB LDO is cap-less or not" "NOCAP_0,NOCAP_1" newline rbitfld.long 0xDC 3. "RESERVED," "0,1" bitfld.long 0xDC 2. "ACTIVE_FBB_SEL,Defines ABB LDO mode when voltage is in slow fast OPP" "ACTIVE_FBB_SEL_0,ACTIVE_FBB_SEL_1" newline rbitfld.long 0xDC 1. "RESERVED," "0,1" bitfld.long 0xDC 0. "SR2EN,Enable ABB power management" "SR2EN_0,SR2EN_1" line.long 0xE0 "PRM_ABBLDO_MPU_CTRL,Control and Status of ABB on MPU voltage domain" hexmask.long 0xE0 7.--31. 1. "RESERVED," rbitfld.long 0xE0 6. "SR2_IN_TRANSITION,Indicates VBBLDO_CON is or is not in transition state" "SR2_IN_TRANSITION_0,SR2_IN_TRANSITION_1" newline rbitfld.long 0xE0 5. "RESERVED," "0,1" rbitfld.long 0xE0 3.--4. "SR2_STATUS,Indicate ABB LDO current operation status" "SR2_STATUS_0,SR2_STATUS_1,SR2_STATUS_2,SR2_STATUS_3" newline bitfld.long 0xE0 2. "OPP_CHANGE,When OPP_CHANGE is set to 1 VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge" "0,1" bitfld.long 0xE0 0.--1. "OPP_SEL,Selects the OPP at which the MPU voltage domain is operating" "OPP_SEL_0,OPP_SEL_1,OPP_SEL_2,OPP_SEL_3" line.long 0xE4 "PRM_ABBLDO_GPU_SETUP,Selects the GPU_ABB LDO mode" hexmask.long.word 0xE4 16.--31. 1. "RESERVED," hexmask.long.byte 0xE4 8.--15. 1. "SR2_WTCNT_VALUE,LDO settling time for active-mode OPP change" newline rbitfld.long 0xE4 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0xE4 4. "NOCAP,Defines whether ABB LDO is cap-less or not" "NOCAP_0,NOCAP_1" newline rbitfld.long 0xE4 3. "RESERVED," "0,1" bitfld.long 0xE4 2. "ACTIVE_FBB_SEL,Defines ABB LDO mode when voltage is in slow fast OPP" "ACTIVE_FBB_SEL_0,ACTIVE_FBB_SEL_1" newline rbitfld.long 0xE4 1. "RESERVED," "0,1" bitfld.long 0xE4 0. "SR2EN,Enable ABB power management" "SR2EN_0,SR2EN_1" line.long 0xE8 "PRM_ABBLDO_GPU_CTRL,Control and Status of ABB on GPU voltage domain" hexmask.long 0xE8 7.--31. 1. "RESERVED," rbitfld.long 0xE8 6. "SR2_IN_TRANSITION,Indicates VBBLDO_CON is or is not in transition state" "SR2_IN_TRANSITION_0,SR2_IN_TRANSITION_1" newline rbitfld.long 0xE8 5. "RESERVED," "0,1" rbitfld.long 0xE8 3.--4. "SR2_STATUS,Indicate ABB LDO current operation status" "SR2_STATUS_0,SR2_STATUS_1,SR2_STATUS_2,SR2_STATUS_3" newline bitfld.long 0xE8 2. "OPP_CHANGE,When OPP_CHANGE is set to 1 VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge" "0,1" bitfld.long 0xE8 0.--1. "OPP_SEL,Selects the OPP at which the MM voltage domain is operating (Fast OPP Nominal OPP or Slow OPP)" "OPP_SEL_0,OPP_SEL_1,OPP_SEL_2,OPP_SEL_3" line.long 0xEC "PRM_BANDGAP_SETUP,Setup of the bandgap" hexmask.long.tbyte 0xEC 8.--31. 1. "RESERVED," hexmask.long.byte 0xEC 0.--7. 1. "STARTUP_COUNT,Determines the start-up duration of BANDGAP" line.long 0xF0 "PRM_DEVICE_OFF_CTRL,This register is used to control device OFF transition" hexmask.long.tbyte 0xF0 10.--31. 1. "RESERVED," bitfld.long 0xF0 9. "EMIF2_OFFWKUP_DISABLE,Controls the EMIF2_DEVICE_OFFWKUP_CORESRTACTST notifier sent to EMIF1 upon a device wakeup from OFF mode" "EMIF2_OFFWKUP_DISABLE_0,EMIF2_OFFWKUP_DISABLE_1" newline bitfld.long 0xF0 8. "EMIF1_OFFWKUP_DISABLE,Controls the EMIF1_DEVICE_OFFWKUP_CORESRTACTST notifier sent to EMIF2 upon a device wakeup from OFF mode" "EMIF1_OFFWKUP_DISABLE_0,EMIF1_OFFWKUP_DISABLE_1" hexmask.long.byte 0xF0 1.--7. 1. "RESERVED," newline bitfld.long 0xF0 0. "DEVICE_OFF_ENABLE,Controls transition to device OFF mode" "DEVICE_OFF_ENABLE_0,DEVICE_OFF_ENABLE_1" line.long 0xF4 "PRM_PHASE1_CNDP,This register stores the start descriptor address of automatic restore phase1" line.long 0xF8 "PRM_PHASE2A_CNDP,This register stores the start descriptor address of automatic restore phase2A" line.long 0xFC "PRM_PHASE2B_CNDP,This register stores the start descriptor address of automatic restore phase2B" line.long 0x100 "PRM_MODEM_IF_CTRL,This register is used to control dedicated interfaces between on-chip modem and APE" hexmask.long.tbyte 0x100 10.--31. 1. "RESERVED," bitfld.long 0x100 9. "MODEM_SHUTDOWN_IRQ,Controls an interrupt signal to shutdown modem" "MODEM_SHUTDOWN_IRQ_0,MODEM_SHUTDOWN_IRQ_1" newline bitfld.long 0x100 8. "MODEM_WAKE_IRQ,Controls an interrupt signal to wakeup modem" "MODEM_WAKE_IRQ_0,MODEM_WAKE_IRQ_1" hexmask.long.byte 0x100 0.--7. 1. "RESERVED," rgroup.long 0x110++0x27 line.long 0x00 "PRM_VOLTST_MPU,This register provides a status on the current MPU voltage domain state" hexmask.long.word 0x00 21.--31. 1. "RESERVED," bitfld.long 0x00 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.tbyte 0x00 2.--19. 1. "RESERVED," bitfld.long 0x00 0.--1. "VOLTSTATEST,Current voltage state status" "VOLTSTATEST_0,VOLTSTATEST_1,VOLTSTATEST_2,VOLTSTATEST_3" line.long 0x04 "PRM_VOLTST_MM,This register provides a status on the current MM voltage domain state" hexmask.long.word 0x04 21.--31. 1. "RESERVED," bitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.tbyte 0x04 2.--19. 1. "RESERVED," bitfld.long 0x04 0.--1. "VOLTSTATEST,Current voltage state status" "VOLTSTATEST_0,VOLTSTATEST_1,VOLTSTATEST_2,VOLTSTATEST_3" line.long 0x08 "PRM_SLDO_DSPEVE_SETUP,Setup of the SRAM LDO for DSPEVE voltage domain" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," bitfld.long 0x08 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" newline bitfld.long 0x08 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" bitfld.long 0x08 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" newline bitfld.long 0x08 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" bitfld.long 0x08 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" newline bitfld.long 0x08 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" bitfld.long 0x08 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" newline bitfld.long 0x08 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" bitfld.long 0x08 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0x0C "PRM_SLDO_IVA_SETUP,Setup of the SRAM LDO for IVA voltage domain" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED," bitfld.long 0x0C 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" newline bitfld.long 0x0C 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" bitfld.long 0x0C 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" newline bitfld.long 0x0C 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" bitfld.long 0x0C 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" newline bitfld.long 0x0C 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" bitfld.long 0x0C 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" newline bitfld.long 0x0C 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" bitfld.long 0x0C 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0x10 "PRM_ABBLDO_DSPEVE_CTRL,Control and Status of ABB on DSPEVE voltage domain" hexmask.long 0x10 7.--31. 1. "RESERVED," rbitfld.long 0x10 6. "SR2_IN_TRANSITION,Indicates VBBLDO_CON is or is not in transition state" "SR2_IN_TRANSITION_0,SR2_IN_TRANSITION_1" newline rbitfld.long 0x10 5. "RESERVED," "0,1" rbitfld.long 0x10 3.--4. "SR2_STATUS,Indicate ABB LDO current operation status" "SR2_STATUS_0,SR2_STATUS_1,SR2_STATUS_2,SR2_STATUS_3" newline bitfld.long 0x10 2. "OPP_CHANGE,When OPP_CHANGE is set to 1 VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge" "0,1" bitfld.long 0x10 0.--1. "OPP_SEL,Selects the OPP at which the MM voltage domain is operating (Fast OPP Nominal OPP or Slow OPP)" "OPP_SEL_0,OPP_SEL_1,OPP_SEL_2,OPP_SEL_3" line.long 0x14 "PRM_ABBLDO_IVA_CTRL,Control and Status of ABB on IVA voltage domain" hexmask.long 0x14 7.--31. 1. "RESERVED," rbitfld.long 0x14 6. "SR2_IN_TRANSITION,Indicates VBBLDO_CON is or is not in transition state" "SR2_IN_TRANSITION_0,SR2_IN_TRANSITION_1" newline rbitfld.long 0x14 5. "RESERVED," "0,1" rbitfld.long 0x14 3.--4. "SR2_STATUS,Indicate ABB LDO current operation status" "SR2_STATUS_0,SR2_STATUS_1,SR2_STATUS_2,SR2_STATUS_3" newline bitfld.long 0x14 2. "OPP_CHANGE,When OPP_CHANGE is set to 1 VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge" "0,1" bitfld.long 0x14 0.--1. "OPP_SEL,Selects the OPP at which the MM voltage domain is operating (Fast OPP Nominal OPP or Slow OPP)" "OPP_SEL_0,OPP_SEL_1,OPP_SEL_2,OPP_SEL_3" line.long 0x18 "PRM_SLDO_DSPEVE_CTRL,Control and status of the SRAM LDO for CORE voltage domain" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," rbitfld.long 0x18 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" newline rbitfld.long 0x18 8. "SRAMLDO_STATUS,SRAMLDO status" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" hexmask.long.byte 0x18 1.--7. 1. "RESERVED," newline bitfld.long 0x18 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,RETMODE_ENABLE_1" line.long 0x1C "PRM_SLDO_IVA_CTRL,Control and status of the SRAM LDO for CORE voltage domain" hexmask.long.tbyte 0x1C 10.--31. 1. "RESERVED," rbitfld.long 0x1C 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" newline rbitfld.long 0x1C 8. "SRAMLDO_STATUS,SRAMLDO status" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" hexmask.long.byte 0x1C 1.--7. 1. "RESERVED," newline bitfld.long 0x1C 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,RETMODE_ENABLE_1" line.long 0x20 "PRM_ABBLDO_DSPEVE_SETUP,Selects the GPU_ABB LDO mode" hexmask.long.word 0x20 16.--31. 1. "RESERVED," hexmask.long.byte 0x20 8.--15. 1. "SR2_WTCNT_VALUE,LDO settling time for active-mode OPP change" newline rbitfld.long 0x20 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x20 4. "NOCAP,Defines whether ABB LDO is cap-less or not" "NOCAP_0,NOCAP_1" newline rbitfld.long 0x20 3. "RESERVED," "0,1" bitfld.long 0x20 2. "ACTIVE_FBB_SEL,Defines ABB LDO mode when voltage is in slow fast OPP" "ACTIVE_FBB_SEL_0,ACTIVE_FBB_SEL_1" newline rbitfld.long 0x20 1. "RESERVED," "0,1" bitfld.long 0x20 0. "SR2EN,Enable ABB power management" "SR2EN_0,SR2EN_1" line.long 0x24 "PRM_ABBLDO_IVA_SETUP,Selects the GPU_ABB LDO mode" hexmask.long.word 0x24 16.--31. 1. "RESERVED," hexmask.long.byte 0x24 8.--15. 1. "SR2_WTCNT_VALUE,LDO settling time for active-mode OPP change" newline rbitfld.long 0x24 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x24 4. "NOCAP,Defines whether ABB LDO is cap-less or not" "NOCAP_0,NOCAP_1" newline rbitfld.long 0x24 3. "RESERVED," "0,1" bitfld.long 0x24 2. "ACTIVE_FBB_SEL,Defines ABB LDO mode when voltage is in slow fast OPP" "ACTIVE_FBB_SEL_0,ACTIVE_FBB_SEL_1" newline rbitfld.long 0x24 1. "RESERVED," "0,1" bitfld.long 0x24 0. "SR2EN,Enable ABB power management" "SR2EN_0,SR2EN_1" width 0x0B tree.end tree "DISPC_COMMON" base ad:0x58010000 rgroup.long 0x00++0x0B line.long 0x00 "DISPC_REVISION,This register contains the IP revision code" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision" line.long 0x04 "DISPC_SYSCONFIG,This register allows to control various parameters of the OCP interface" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x04 12.--13. "MIDLEMODE,Master interface power management standby/wait control" "MIDLEMODE_0,MIDLEMODE_1,MIDLEMODE_2,MIDLEMODE_3" newline rbitfld.long 0x04 10.--11. "RESERVED,Write 0's for future compatibility" "0,1,2,3" bitfld.long 0x04 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" newline rbitfld.long 0x04 6.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3" bitfld.long 0x04 5. "WARMRESET,Warm reset" "WARMRESET_0,WARMRESET_1" newline bitfld.long 0x04 3.--4. "SIDLEMODE,Slave interface power management Idle req/ack control" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x04 2. "ENWAKEUP,WakeUp feature control" "ENWAKEUP_0,ENWAKEUP_1" newline bitfld.long 0x04 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" bitfld.long 0x04 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x08 "DISPC_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" hexmask.long 0x08 5.--31. 1. "RESERVED," bitfld.long 0x08 4. "RESERVED," "0,1" newline bitfld.long 0x08 3. "RESERVED," "0,1" bitfld.long 0x08 2. "RESERVED," "0,1" newline bitfld.long 0x08 1. "DISPC_VP1_RESETDONE,Reset status of DISPC VP1 pixel clock domain" "DISPC_VP1_RESETDONE_0,DISPC_VP1_RESETDONE_1" bitfld.long 0x08 0. "DISPC_FUNC_RESETDONE,Reset status of DISPC Functional clock domain" "DISPC_FUNC_RESETDONE_0,DISPC_FUNC_RESETDONE_1" group.long 0x20++0x17 line.long 0x00 "DISPC_IRQ_EOI,End Of Interrupt number (for H08 interrupt)" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,?" line.long 0x04 "DISPC_IRQSTATUS_RAW,Per-end of group (31 down to 0) internal signaling raw interrupt status vector. line #0" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED," bitfld.long 0x04 13. "WAKEUP_IRQ,Wake-up" "WAKEUP_IRQ_0,WAKEUP_IRQ_1" newline rbitfld.long 0x04 12. "RESERVED," "0,1" bitfld.long 0x04 11. "WB_IRQ,WB IRQ STATUS register indicates the write-back pipeline interrupt events" "WB_IRQ_0,WB_IRQ_1" newline rbitfld.long 0x04 10. "RESERVED," "0,1" rbitfld.long 0x04 9. "RESERVED," "0,1" newline bitfld.long 0x04 8. "VID2_IRQ,VID2 IRQ STATUS register indicates the video pipeline 2 interrupt events" "VID2_IRQ_0,VID2_IRQ_1" bitfld.long 0x04 7. "VID1_IRQ,VID1 IRQ STATUS register indicates the video pipeline 1 interrupt events" "VID1_IRQ_0,VID1_IRQ_1" newline rbitfld.long 0x04 6. "RESERVED," "0,1" rbitfld.long 0x04 5. "RESERVED," "0,1" newline bitfld.long 0x04 4. "GFX1_IRQ,GFX1 IRQ STATUS register indicates the graphics pipeline 1 interrupt events" "GFX1_IRQ_0,GFX1_IRQ_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline rbitfld.long 0x04 2. "RESERVED," "0,1" rbitfld.long 0x04 1. "RESERVED," "0,1" newline bitfld.long 0x04 0. "VP1_IRQ,VP1 IRQ STATUS register indicates the Video Port 1 interrupt events" "VP1_IRQ_0,VP1_IRQ_1" line.long 0x08 "DISPC_IRQSTATUS,Per-end of group (31 down to 0) internal signaling 'enabled' interrupt status vector. line #0" hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED," bitfld.long 0x08 13. "WAKEUP_IRQ,Wake-up" "WAKEUP_IRQ_0,WAKEUP_IRQ_1" newline rbitfld.long 0x08 12. "RESERVED," "0,1" bitfld.long 0x08 11. "WB_IRQ,WB IRQ STATUS register indicates the write-back pipeline interrupt events" "WB_IRQ_0,WB_IRQ_1" newline rbitfld.long 0x08 10. "RESERVED," "0,1" rbitfld.long 0x08 9. "RESERVED," "0,1" newline bitfld.long 0x08 8. "VID2_IRQ,VID2 IRQ STATUS register indicates the video pipeline 2 interrupt events" "VID2_IRQ_0,VID2_IRQ_1" bitfld.long 0x08 7. "VID1_IRQ,VID1 IRQ STATUS register indicates the video pipeline 1 interrupt events" "VID1_IRQ_0,VID1_IRQ_1" newline rbitfld.long 0x08 6. "RESERVED," "0,1" rbitfld.long 0x08 5. "RESERVED," "0,1" newline bitfld.long 0x08 4. "GFX1_IRQ,GFX1 IRQ STATUS register indicates the graphics pipeline 1 interrupt events" "GFX1_IRQ_0,GFX1_IRQ_1" rbitfld.long 0x08 3. "RESERVED," "0,1" newline rbitfld.long 0x08 2. "RESERVED," "0,1" rbitfld.long 0x08 1. "RESERVED," "0,1" newline bitfld.long 0x08 0. "VP1_IRQ,VP1 IRQ STATUS register indicates the Video Port 1 interrupt events" "VP1_IRQ_0,VP1_IRQ_1" line.long 0x0C "DISPC_IRQENABLE_SET,Per-end of group (31 down to 0) internal event interrupt enable bit vector. line #0" hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED," bitfld.long 0x0C 13. "SET_WAKEUP_IRQ,Wake Up Mask" "SET_WAKEUP_IRQ_0,SET_WAKEUP_IRQ_1" newline rbitfld.long 0x0C 12. "RESERVED," "0,1" bitfld.long 0x0C 11. "SET_WB_IRQ,WB IRQ" "SET_WB_IRQ_0,SET_WB_IRQ_1" newline rbitfld.long 0x0C 10. "RESERVED," "0,1" rbitfld.long 0x0C 9. "RESERVED," "0,1" newline bitfld.long 0x0C 8. "SET_VID2_IRQ,VID2 IRQ" "SET_VID2_IRQ_0,SET_VID2_IRQ_1" bitfld.long 0x0C 7. "SET_VID1_IRQ,VID1 IRQ" "SET_VID1_IRQ_0,SET_VID1_IRQ_1" newline rbitfld.long 0x0C 6. "RESERVED," "0,1" rbitfld.long 0x0C 5. "RESERVED," "0,1" newline bitfld.long 0x0C 4. "SET_GFX1_IRQ,GFX1 IRQ" "SET_GFX1_IRQ_0,SET_GFX1_IRQ_1" rbitfld.long 0x0C 3. "RESERVED," "0,1" newline rbitfld.long 0x0C 2. "RESERVED," "0,1" rbitfld.long 0x0C 1. "RESERVED," "0,1" newline bitfld.long 0x0C 0. "SET_VP1_IRQ,VP1 IRQ" "SET_VP1_IRQ_0,SET_VP1_IRQ_1" line.long 0x10 "DISPC_IRQENABLE_CLR," hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," bitfld.long 0x10 13. "CLR_WAKEUP_IRQ,Wake Up Mask" "CLR_WAKEUP_IRQ_0,CLR_WAKEUP_IRQ_1" newline rbitfld.long 0x10 12. "RESERVED," "0,1" bitfld.long 0x10 11. "CLR_WB_IRQ,WB IRQ" "CLR_WB_IRQ_0,CLR_WB_IRQ_1" newline rbitfld.long 0x10 10. "RESERVED," "0,1" rbitfld.long 0x10 9. "RESERVED," "0,1" newline bitfld.long 0x10 8. "CLR_VID2_IRQ,VID2 IRQ" "CLR_VID2_IRQ_0,CLR_VID2_IRQ_1" bitfld.long 0x10 7. "CLR_VID1_IRQ,VID1 IRQ" "CLR_VID1_IRQ_0,CLR_VID1_IRQ_1" newline rbitfld.long 0x10 6. "RESERVED," "0,1" rbitfld.long 0x10 5. "RESERVED," "0,1" newline bitfld.long 0x10 4. "CLR_GFX1_IRQ,GFX1 IRQ" "CLR_GFX1_IRQ_0,CLR_GFX1_IRQ_1" rbitfld.long 0x10 3. "RESERVED," "0,1" newline rbitfld.long 0x10 2. "RESERVED," "0,1" rbitfld.long 0x10 1. "RESERVED," "0,1" newline bitfld.long 0x10 0. "CLR_VP1_IRQ,VP1 IRQ" "CLR_VP1_IRQ_0,CLR_VP1_IRQ_1" line.long 0x14 "DISPC_IRQWAKEEN,IRQ wake up register" hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED," bitfld.long 0x14 11. "WB_IRQWAKEEN,wakeupen for WB first level interrupt" "WB_IRQWAKEEN_0,WB_IRQWAKEEN_1" newline rbitfld.long 0x14 10. "RESERVED," "0,1" rbitfld.long 0x14 9. "RESERVED," "0,1" newline bitfld.long 0x14 8. "VID2_IRQWAKEEN,wakeupen for VID2 first level interrupt" "VID2_IRQWAKEEN_0,VID2_IRQWAKEEN_1" bitfld.long 0x14 7. "VID1_IRQWAKEEN,wakeupen for VID1 first level interrupt" "VID1_IRQWAKEEN_0,VID1_IRQWAKEEN_1" newline rbitfld.long 0x14 6. "RESERVED," "0,1" rbitfld.long 0x14 5. "RESERVED," "0,1" newline bitfld.long 0x14 4. "GFX1_IRQWAKEEN,wakeupen for GFX1 first level interrupt" "GFX1_IRQWAKEEN_0,GFX1_IRQWAKEEN_1" rbitfld.long 0x14 3. "RESERVED," "0,1" newline rbitfld.long 0x14 2. "RESERVED," "0,1" rbitfld.long 0x14 1. "RESERVED," "0,1" newline bitfld.long 0x14 0. "VP1_IRQWAKEEN,wakeupen for VP1 first level interrupt" "VP1_IRQWAKEEN_0,VP1_IRQWAKEEN_1" group.long 0x40++0x17 line.long 0x00 "DISPC_GLOBAL_MFLAG_ATTRIBUTE,MFLAG control register" hexmask.long 0x00 3.--31. 1. "RESERVED," bitfld.long 0x00 2. "MFLAG_START," "MFLAG_START_0,MFLAG_START_1" newline bitfld.long 0x00 0.--1. "MFLAG_CTRL," "MFLAG_CTRL_0,MFLAG_CTRL_1,MFLAG_CTRL_2,?" line.long 0x04 "DISPC_GLOBAL_BUFFER,The register configures the DMA buffers allocations to the pipeline" bitfld.long 0x04 31. "BUFFERFILLING,Controls if the DMA buffers are re-filled only when the LOW threshold is reached or if all DMA buffers are re-filled when at least one of them reaches the LOW threshold" "BUFFERFILLING_0,BUFFERFILLING_1" hexmask.long.word 0x04 21.--30. 1. "RESERVED," newline bitfld.long 0x04 18.--20. "WB_BUFFER,WB DMA buffer allocation to one of the pipelines" "WB_BUFFER_0,WB_BUFFER_1,WB_BUFFER_2,WB_BUFFER_3,WB_BUFFER_4,WB_BUFFER_5,WB_BUFFER_6,WB_BUFFER_7" rbitfld.long 0x04 15.--17. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 12.--14. "VID2_BUFFER,Video2 DMA buffer allocation to one of the pipelines" "VID2_BUFFER_0,VID2_BUFFER_1,VID2_BUFFER_2,VID2_BUFFER_3,VID2_BUFFER_4,VID2_BUFFER_5,VID2_BUFFER_6,VID2_BUFFER_7" bitfld.long 0x04 9.--11. "VID1_BUFFER,Video1 DMA buffer allocation to one of the pipelines" "VID1_BUFFER_0,VID1_BUFFER_1,VID1_BUFFER_2,VID1_BUFFER_3,VID1_BUFFER_4,VID1_BUFFER_5,VID1_BUFFER_6,VID1_BUFFER_7" newline rbitfld.long 0x04 6.--8. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 3.--5. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0.--2. "GFX1_BUFFER,Gfx1 DMA buffer allocation to one of the pipelines" "GFX1_BUFFER_0,GFX1_BUFFER_1,GFX1_BUFFER_2,GFX1_BUFFER_3,GFX1_BUFFER_4,GFX1_BUFFER_5,GFX1_BUFFER_6,GFX1_BUFFER_7" line.long 0x08 "DISPC_BA0_FLIPIMMEDIATE_EN,Note: Register is not supported in this family of devices" hexmask.long 0x08 6.--31. 1. "RESERVED," bitfld.long 0x08 5. "RESERVED," "0,1" newline bitfld.long 0x08 4. "RESERVED," "0,1" bitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 2. "RESERVED," "0,1" bitfld.long 0x08 1. "RESERVED," "0,1" newline bitfld.long 0x08 0. "RESERVED," "0,1" line.long 0x0C "DISPC_DBG_CONTROL,DISPC debug bus control register Note: GFX2. GFX3. VID-3. OVR3. OVR4. VP2. VP3. VP4. GLBCE1 and GLBCE2 are not supported in this family of devices" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED," hexmask.long.byte 0x0C 1.--8. 1. "DBGMUXSEL," newline bitfld.long 0x0C 0. "DBGEN,Enable debug ports" "DBGEN_0,DBGEN_1" line.long 0x10 "DISPC_DBG_STATUS,DISPC debug status register" line.long 0x14 "DISPC_CLKGATING_DISABLE,Register to control clock gating at DISPC sub-module level Note: CUR. GFX2. GFX3. VID3. OVR3. OVR4. VP2. VP3. VP4. GLBCE1 and GLBCE2 are not supported in this family of devices" rbitfld.long 0x14 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 26. "VP4,Clock gating control for VP4" "VP4_0,VP4_1" newline bitfld.long 0x14 25. "VP3,Clock gating control for VP3" "VP3_0,VP3_1" bitfld.long 0x14 24. "VP2,Clock gating control for VP2" "VP2_0,VP2_1" newline bitfld.long 0x14 23. "VP1,Clock gating control for VP1" "VP1_0,VP1_1" bitfld.long 0x14 22. "OVR4,Clock gating control for OVR4" "OVR4_0,OVR4_1" newline bitfld.long 0x14 21. "OVR3,Clock gating control for OVR3" "OVR3_0,OVR3_1" bitfld.long 0x14 20. "OVR2,Clock gating control for OVR2" "OVR2_0,OVR2_1" newline bitfld.long 0x14 19. "OVR1,Clock gating control for OVR1" "OVR1_0,OVR1_1" bitfld.long 0x14 18. "CUR,Clock gating control for CUR" "CUR_0,CUR_1" newline bitfld.long 0x14 17. "WB,Clock gating control for WB" "WB_0,WB_1" bitfld.long 0x14 16. "GLBCE2,Clock gating control for GLBCE2" "GLBCE2_0,GLBCE2_1" newline bitfld.long 0x14 15. "GLBCE1,Clock gating control for GLBCE1" "GLBCE1_0,GLBCE1_1" bitfld.long 0x14 14. "GFX3,Clock gating control for GFX3" "GFX3_0,GFX3_1" newline bitfld.long 0x14 13. "GFX2,Clock gating control for GFX2" "GFX2_0,GFX2_1" bitfld.long 0x14 12. "GFX1,Clock gating control for GFX1" "GFX1_0,GFX1_1" newline bitfld.long 0x14 11. "VID3,Clock gating control for VID3" "VID3_0,VID3_1" bitfld.long 0x14 10. "VID2,Clock gating control for VID2" "VID2_0,VID2_1" newline bitfld.long 0x14 9. "VID1,Clock gating control for VID1" "VID1_0,VID1_1" bitfld.long 0x14 8. "DMA_CH8,Clock gating control for DMA Channel-8" "DMA_CH8_0,DMA_CH8_1" newline bitfld.long 0x14 7. "DMA_CH7,Clock gating control for DMA Channel-7" "DMA_CH7_0,DMA_CH7_1" bitfld.long 0x14 6. "DMA_CH6,Clock gating control for DMA Channel-6" "DMA_CH6_0,DMA_CH6_1" newline bitfld.long 0x14 5. "DMA_CH5,Clock gating control for DMA Channel-5" "DMA_CH5_0,DMA_CH5_1" bitfld.long 0x14 4. "DMA_CH4,Clock gating control for DMA Channel-4" "DMA_CH4_0,DMA_CH4_1" newline bitfld.long 0x14 3. "DMA_CH3,Clock gating control for DMA Channel-3" "DMA_CH3_0,DMA_CH3_1" bitfld.long 0x14 2. "DMA_CH2,Clock gating control for DMA Channel-2" "DMA_CH2_0,DMA_CH2_1" newline bitfld.long 0x14 1. "DMA_CH1,Clock gating control for DMA Channel-1" "DMA_CH1_0,DMA_CH1_1" bitfld.long 0x14 0. "DMA_COMMON,Clock gating control for DMA_COMMON module" "DMA_COMMON_0,DMA_COMMON_1" width 0x0B tree.end tree "DISPC_GFX1" base ad:0x58011000 group.long 0x00++0x3F line.long 0x00 "DISPC_GFX1_ATTRIBUTES,The register configures the graphics attributes" rbitfld.long 0x00 31. "RESERVED," "0,1" rbitfld.long 0x00 30. "RESERVED," "0,1" newline rbitfld.long 0x00 29. "RESERVED," "0,1" bitfld.long 0x00 28. "PREMULTIPLYALPHA,The field configures the DISPC GFX to process incoming data as premultiplied alpha data or non premultiplied alpha data" "PREMULTIPLYALPHA_0,PREMULTIPLYALPHA_1" newline bitfld.long 0x00 25.--27. "ZORDER,Z-Order defining the priority of the layer compared to others when overlaying" "ZORDER_0,ZORDER_1,ZORDER_2,ZORDER_3,ZORDER_4,ZORDER_5,?,?" bitfld.long 0x00 24. "ANTIFLICKER,Anti-aliasing filtering using a 3-tap filter with hardcoded coefficients (1/4 1/2 1/4)" "ANTIFLICKER_0,ANTIFLICKER_1" newline rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 18. "RESERVED," "0,1" newline bitfld.long 0x00 17. "SELFREFRESHAUTO,Automatic self refresh mode" "SELFREFRESHAUTO_0,SELFREFRESHAUTO_1" rbitfld.long 0x00 16. "RESERVED," "0,1" newline bitfld.long 0x00 15. "SELFREFRESH,Enables the self refresh of the graphics window from its own DMA buffer" "SELFREFRESH_0,SELFREFRESH_1" bitfld.long 0x00 14. "ARBITRATION,Determines the priority of the graphics pipeline" "ARBITRATION_0,ARBITRATION_1" newline rbitfld.long 0x00 12.--13. "RESERVED," "0,1,2,3" bitfld.long 0x00 11. "BUFPRELOAD,Graphics Preload Value" "BUFPRELOAD_0,BUFPRELOAD_1" newline bitfld.long 0x00 8.--10. "CHANNELOUT,Graphics Channel Out configuration wr: immediate" "CHANNELOUT_0,CHANNELOUT_1,?,?,CHANNELOUT_4,?,?,?" bitfld.long 0x00 7. "NIBBLEMODE,Graphics Nibble mode (only for 1- 2- and 4-bpp)" "NIBBLEMODE_0,NIBBLEMODE_1" newline bitfld.long 0x00 1.--6. "FORMAT,Graphics format" "FORMAT_0,FORMAT_1,FORMAT_2,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,?,FORMAT_14,FORMAT_15,FORMAT_16,FORMAT_17,FORMAT_18,FORMAT_19,FORMAT_20,FORMAT_21,FORMAT_22,?,?,?,?,?,?,?,?,?,FORMAT_32,FORMAT_33,FORMAT_34,FORMAT_35,?,FORMAT_37,FORMAT_38,FORMAT_39,FORMAT_40,FORMAT_41,FORMAT_42,FORMAT_43,?,?,FORMAT_46,FORMAT_47,FORMAT_48,FORMAT_49,FORMAT_50,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0. "ENABLE,Graphics Enable" "ENABLE_0,ENABLE_1" line.long 0x04 "DISPC_GFX1_ATTRIBUTES2,The register configures the graphics attributes" rbitfld.long 0x04 31. "RESERVED," "0,1" bitfld.long 0x04 26.--30. "TAGS,Number of OCP TAGS to be used for the pipeline (from 1 to 32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 25. "RESERVED," "0,1" bitfld.long 0x04 24. "REGION_BASED,Enable region-based mechanism" "REGION_BASED_0,REGION_BASED_1" newline hexmask.long.byte 0x04 17.--23. 1. "RESERVED," bitfld.long 0x04 16. "SECURE,OCP requests corresponds to pipeline data are secure/unsecure" "0,1" newline hexmask.long.word 0x04 0.--15. 1. "RESERVED," line.long 0x08 "DISPC_GFX1_BA_j_0,The register configures the base address of the graphics buffer displayed in the graphics window (0 & 1 :for ping-pong mechanism with external trigger. based on the field polarity)" line.long 0x0C "DISPC_GFX1_BA_j_1,The register configures the base address of the graphics buffer displayed in the graphics window (0 & 1 :for ping-pong mechanism with external trigger. based on the field polarity)" line.long 0x10 "DISPC_GFX1_BUF_SIZE_STATUS,The register defines the Graphics buffer size" hexmask.long.word 0x10 16.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x10 0.--15. 1. "BUFSIZE,DMA buffer Size in number of 128-bits" line.long 0x14 "DISPC_GFX1_BUF_THRESHOLD,The register configures the graphics buffer" hexmask.long.word 0x14 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer High Threshold Number of 128-bits defining the threshold value" hexmask.long.word 0x14 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer Low Threshold Number of 128-bits defining the threshold value" line.long 0x18 "DISPC_GFX1_GLOBAL_ALPHA,The register defines the global alpha value for the graphics pipeline" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," hexmask.long.byte 0x18 0.--7. 1. "GLOBALALPHA,Global alpha value from 0 to 255" line.long 0x1C "DISPC_GFX1_IRQENABLE,This register allows to mask/unmask the module internal sources of interrupt. on an event-by-event basis" hexmask.long 0x1C 4.--31. 1. "RESERVED," bitfld.long 0x1C 3. "GFXREGIONBASEDPIPEEND_EN,PIPE end window IRQ for region-based feature" "GFXREGIONBASEDPIPEEND_EN_0,GFXREGIONBASEDPIPEEND_EN_1" newline bitfld.long 0x1C 2. "GFXREGIONBASEDPIPESTART_EN,PIPE start window IRQ for region-based feature" "GFXREGIONBASEDPIPESTART_EN_0,GFXREGIONBASEDPIPESTART_EN_1" bitfld.long 0x1C 1. "GFXENDWINDOW_EN,The end of Gfx Window has been reached" "GFXENDWINDOW_EN_0,GFXENDWINDOW_EN_1" newline bitfld.long 0x1C 0. "GFXBUFFERUNDERFLOW_EN,Gfx DMA Buffer Underflow" "GFXBUFFERUNDERFLOW_EN_0,GFXBUFFERUNDERFLOW_EN_1" line.long 0x20 "DISPC_GFX1_IRQSTATUS,This register regroups all the status of the module internal events that generate an interrupt" hexmask.long 0x20 4.--31. 1. "RESERVED," bitfld.long 0x20 3. "GFXREGIONBASEDPIPEEND_IRQ,PIPE end window IRQ for region-based feature" "GFXREGIONBASEDPIPEEND_IRQ_0,GFXREGIONBASEDPIPEEND_IRQ_1" newline bitfld.long 0x20 2. "GFXREGIONBASEDPIPESTART_IRQ,PIPE start window IRQ for region-based feature" "GFXREGIONBASEDPIPESTART_IRQ_0,GFXREGIONBASEDPIPESTART_IRQ_1" bitfld.long 0x20 1. "GFXENDWINDOW_IRQ,The end of Gfx Window has been reached" "GFXENDWINDOW_IRQ_0,GFXENDWINDOW_IRQ_1" newline bitfld.long 0x20 0. "GFXBUFFERUNDERFLOW_IRQ,Gfx DMA Buffer Underflow" "GFXBUFFERUNDERFLOW_IRQ_0,GFXBUFFERUNDERFLOW_IRQ_1" line.long 0x24 "DISPC_GFX1_MFLAG_THRESHOLD," hexmask.long.word 0x24 16.--31. 1. "HT_MFLAG," hexmask.long.word 0x24 0.--15. 1. "LT_MFLAG," line.long 0x28 "DISPC_GFX1_PIXEL_INC,The register configures the number of bytes to increment between two pixels" hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.byte 0x28 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels" line.long 0x2C "DISPC_GFX1_POSITION,The register configures the position of the graphics window" rbitfld.long 0x2C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x2C 16.--27. 1. "POSY,Y position of the graphics window" newline rbitfld.long 0x2C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x2C 0.--11. 1. "POSX,X position of the graphics window" line.long 0x30 "DISPC_GFX1_PRELOAD,The register configures the graphics DMA buffer Shadow register" hexmask.long.tbyte 0x30 12.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x30 0.--11. 1. "PRELOAD,DMA buffer preload value Number of 128-bit words defining the preload value" line.long 0x34 "DISPC_GFX1_ROW_INC,The register configures the number of bytes to increment at the end of the row" line.long 0x38 "DISPC_GFX1_SIZE,The register configures the size of the graphics window" rbitfld.long 0x38 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x38 16.--27. 1. "SIZEY,Number of lines of the graphics window" newline rbitfld.long 0x38 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x38 0.--11. 1. "SIZEX,Number of pixels of the graphics window" line.long 0x3C "DISPC_GFX1_CLUT,The register configures the Color Look Up Table (CLUT) for GFX pipeline" hexmask.long.byte 0x3C 24.--31. 1. "INDEX,Defines the location in the table where the bit-field VALUE is stored" hexmask.long.byte 0x3C 16.--23. 1. "VALUE_R,8-bit value used to defined the value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x3C 8.--15. 1. "VALUE_G,8-bit value used to defined the value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x3C 0.--7. 1. "VALUE_B,8-bit value used to defined the value to store at the location in the table defined by the bit-field INDEX" width 0x0B tree.end repeat 2. (list 1. 2. )(list ad:0x5801A800 ad:0x5801A900 ) tree "DISPC_OVR$1" base $2 group.long 0x00++0x03 line.long 0x00 "DISPC_OVR_CONFIG,The control register configures the Display Controller module for the VP output" hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED," bitfld.long 0x00 13. "GLBCESEL,Selection between GLBCE-0 and GLBCE-1" "GLBCESEL_0,GLBCESEL_1" bitfld.long 0x00 12. "GLBCEEN,Enable the GLBCE processing" "GLBCEEN_0,GLBCEEN_1" newline bitfld.long 0x00 11. "TCKLCDSELECTION,Transparency Color Key Selection Shadow bit-field" "TCKLCDSELECTION_0,TCKLCDSELECTION_1" bitfld.long 0x00 10. "TCKLCDENABLE,Transparency Color Key Enabled Shadow bit-field" "TCKLCDENABLE_0,TCKLCDENABLE_1" bitfld.long 0x00 8.--9. "INTERLEAVED3DMODE,Define which layer contributes to odd/even lines of the line interleaving 3D format" "INTERLEAVED3DMODE_0,INTERLEAVED3DMODE_1,INTERLEAVED3DMODE_2,INTERLEAVED3DMODE_3" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0x08++0x17 line.long 0x00 "DISPC_OVR_DEFAULT_COLOR,The control register configures the default solid background color bits [31:0]" line.long 0x04 "DISPC_OVR_DEFAULT_COLOR2,The control register configures the default solid background color bits [47:32]" hexmask.long.word 0x04 16.--31. 1. "RESERVED," hexmask.long.word 0x04 0.--15. 1. "DEFAULTCOLOR,48-bit ARGB color value to specify the default solid color to display when there is no data from the overlays" line.long 0x08 "DISPC_OVR_TRANS_COLOR_MAX,The register sets the max transparency color value for the overlays" line.long 0x0C "DISPC_OVR_TRANS_COLOR_MAX2,The register sets the max transparency color value for the overlays" hexmask.long 0x0C 4.--31. 1. "RESERVED," bitfld.long 0x0C 0.--3. "TRANSCOLORKEY,[35:32] Transparency Color Key Value in 36-bit RGB format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DISPC_OVR_TRANS_COLOR_MIN,The register sets the min transparency color value for the overlays" line.long 0x14 "DISPC_OVR_TRANS_COLOR_MIN2,The register sets the min transparency color value for the overlays" hexmask.long 0x14 4.--31. 1. "RESERVED," bitfld.long 0x14 0.--3. "TRANSCOLORKEY,[35:32] Transparency Color Key Value in 36-bit RGB format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end repeat.end repeat 2. (list 1. 2. )(list ad:0x58017000 ad:0x58018000 ) tree "DISPC_VID$1" base $2 group.long 0x00++0x227 line.long 0x00 "DISPC_VID_ACCUH_j_0,The register configures the resize accumulator init values for horizontal up/down-sampling of the video window (DISPC_VIDx_ACCU__0 DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field polarity) It is.." hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x04 "DISPC_VID_ACCUH_j_1,The register configures the resize accumulator init values for horizontal up/down-sampling of the video window (DISPC_VIDx_ACCU__0 DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field polarity) It is.." hexmask.long.byte 0x04 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x04 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x08 "DISPC_VID_ACCUH2_j_0,The register configures the resize accumulator init value for horizontal up/down-sampling of the video window (DISPC_VID#n_ACCU2__0 DISPC_VID#n_ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity) It.." hexmask.long.byte 0x08 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x08 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x0C "DISPC_VID_ACCUH2_j_1,The register configures the resize accumulator init value for horizontal up/down-sampling of the video window (DISPC_VID#n_ACCU2__0 DISPC_VID#n_ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity) It.." hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x0C 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x10 "DISPC_VID_ACCUV_j_0,The register configures the resize accumulator init values for horizontal and vertical up/down-sampling of the video window (DISPC_VIDx_ACCU__0 DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.byte 0x10 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x10 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x14 "DISPC_VID_ACCUV_j_1,The register configures the resize accumulator init values for horizontal and vertical up/down-sampling of the video window (DISPC_VIDx_ACCU__0 DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.byte 0x14 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x14 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x18 "DISPC_VID_ACCUV2_j_0,The register configures the resize accumulator init value for vertical up/down-sampling of the video window (DISPC_VID1_ACCU2__0 DISPC_VID1_ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity) It is.." hexmask.long.byte 0x18 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x18 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x1C "DISPC_VID_ACCUV2_j_1,The register configures the resize accumulator init value for vertical up/down-sampling of the video window (DISPC_VID1_ACCU2__0 DISPC_VID1_ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity) It is.." hexmask.long.byte 0x1C 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x1C 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x20 "DISPC_VID_ATTRIBUTES,The register configures the attributes of the video window" rbitfld.long 0x20 31. "RESERVED," "0,1" rbitfld.long 0x20 30. "RESERVED," "0,1" newline rbitfld.long 0x20 29. "RESERVED," "0,1" bitfld.long 0x20 28. "PREMULTIPLYALPHA,The field configures the DISPC VID1 to process incoming data as premultiplied alpha data or non premultiplied alpha data" "PREMULTIPLYALPHA_0,PREMULTIPLYALPHA_1" newline bitfld.long 0x20 25.--27. "ZORDER,Z-Order defining the priority of the layer compared to others when overlaying" "ZORDER_0,ZORDER_1,ZORDER_2,ZORDER_3,ZORDER_4,ZORDER_5,?,?" bitfld.long 0x20 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "SELFREFRESH_0,SELFREFRESH_1" newline bitfld.long 0x20 23. "ARBITRATION,Determines the priority of the video pipeline" "ARBITRATION_0,ARBITRATION_1" bitfld.long 0x20 22. "DOUBLESTRIDE,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride" "DOUBLESTRIDE_0,DOUBLESTRIDE_1" newline bitfld.long 0x20 21. "VERTICALTAPS,Video Vertical Resize Tap Number" "VERTICALTAPS_0,VERTICALTAPS_1" rbitfld.long 0x20 20. "RESERVED," "0,1" newline bitfld.long 0x20 19. "BUFPRELOAD,Video Preload Value" "BUFPRELOAD_0,BUFPRELOAD_1" rbitfld.long 0x20 18. "RESERVED,Write 0's for future compatibility" "0,1" newline bitfld.long 0x20 17. "SELFREFRESHAUTO,Automatic self refresh mode" "SELFREFRESHAUTO_0,SELFREFRESHAUTO_1" bitfld.long 0x20 14.--16. "CHANNELOUT,Video Channel Out configuration wr: immediate" "CHANNELOUT_0,CHANNELOUT_1,?,?,CHANNELOUT_4,?,?,?" newline rbitfld.long 0x20 12.--13. "RESERVED," "0,1,2,3" bitfld.long 0x20 11. "FULLRANGE,Color Space Conversion full range setting" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x20 10. "NIBBLEMODE,Video Nibble mode (only for 1- 2- and 4-bpp)" "NIBBLEMODE_0,NIBBLEMODE_1" bitfld.long 0x20 9. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1" newline bitfld.long 0x20 7.--8. "RESIZEENABLE,Video Resize Enable" "RESIZEENABLE_0,RESIZEENABLE_1,RESIZEENABLE_2,RESIZEENABLE_3" bitfld.long 0x20 1.--6. "FORMAT,Video Format" "FORMAT_0,FORMAT_1,FORMAT_2,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,?,FORMAT_14,FORMAT_15,FORMAT_16,FORMAT_17,FORMAT_18,FORMAT_19,FORMAT_20,FORMAT_21,FORMAT_22,FORMAT_23,FORMAT_24,?,?,?,?,?,?,?,FORMAT_32,FORMAT_33,FORMAT_34,FORMAT_35,?,FORMAT_37,FORMAT_38,FORMAT_39,FORMAT_40,FORMAT_41,FORMAT_42,FORMAT_43,?,?,FORMAT_46,FORMAT_47,FORMAT_48,FORMAT_49,FORMAT_50,?,?,?,?,?,?,?,?,?,?,FORMAT_61,FORMAT_62,FORMAT_63" newline bitfld.long 0x20 0. "ENABLE,Video pipeline Enable" "ENABLE_0,ENABLE_1" line.long 0x24 "DISPC_VID_ATTRIBUTES2,The register configures the attributes of the video window" rbitfld.long 0x24 31. "RESERVED," "0,1" bitfld.long 0x24 26.--30. "TAGS,Number of OCP TAGS to be used for the pipeline (from 1 to 32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x24 25. "RESERVED," "0,1" bitfld.long 0x24 24. "REGION_BASED,Enable region-based mechanism" "REGION_BASED_0,REGION_BASED_1" newline hexmask.long.byte 0x24 17.--23. 1. "RESERVED," bitfld.long 0x24 16. "SECURE,OCP requests corresponds to pipeline data are secure/unsecure" "0,1" newline hexmask.long.word 0x24 7.--15. 1. "RESERVED," bitfld.long 0x24 4.--6. "VC1_RANGE_CBCR,Defines the VC1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 1.--3. "VC1_RANGE_Y,Defines the VC1 range value for the Y component from 0 to 7" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0. "VC1ENABLE,Enable/disable the VC1 range mapping processing" "VC1ENABLE_0,VC1ENABLE_1" line.long 0x28 "DISPC_VID_BA_j_0,The register configures the base address of the video buffer for the video window (DISPC_VID1_BA__0 DISPC_VID1_BA__1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_VID1_BA__0 is used)" line.long 0x2C "DISPC_VID_BA_j_1,The register configures the base address of the video buffer for the video window (DISPC_VID1_BA__0 DISPC_VID1_BA__1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_VID1_BA__0 is used)" line.long 0x30 "DISPC_VID_BA_UV_j_0,The register configures the base address of the UV buffer for the video window" line.long 0x34 "DISPC_VID_BA_UV_j_1,The register configures the base address of the UV buffer for the video window" line.long 0x38 "DISPC_VID_BUF_SIZE_STATUS,The register defines the Video buffer size for the video pipeline" hexmask.long.word 0x38 16.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x38 0.--15. 1. "BUFSIZE,Video DMA buffer Size in number of 128-bits" line.long 0x3C "DISPC_VID_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline" hexmask.long.word 0x3C 16.--31. 1. "BUFHIGHTHRESHOLD,Video DMA buffer High Threshold Number of 128-bits defining the threshold value" hexmask.long.word 0x3C 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer High Threshold Number of 128-bits defining the threshold value" line.long 0x40 "DISPC_VID_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline" rbitfld.long 0x40 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x40 16.--26. 1. "RCR,RCr Coefficient Encoded signed value (from -1024 to 1023)" newline rbitfld.long 0x40 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x40 0.--10. 1. "RY,RY Coefficient Encoded signed value (from -1024 to 1023)" line.long 0x44 "DISPC_VID_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline" rbitfld.long 0x44 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x44 16.--26. 1. "GY,GY Coefficient Encoded signed value (from -1024 to 1023)" newline rbitfld.long 0x44 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x44 0.--10. 1. "RCB,RCb Coefficient Encoded signed value (from -1024 to 1023)" line.long 0x48 "DISPC_VID_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline" rbitfld.long 0x48 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x48 16.--26. 1. "GCB,GCb Coefficient Encoded signed value (from -1024 to 1023)" newline rbitfld.long 0x48 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x48 0.--10. 1. "GCR,GCr Coefficient Encoded signed value (from -1024 to 1023)" line.long 0x4C "DISPC_VID_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline" rbitfld.long 0x4C 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x4C 16.--26. 1. "BCR,BCr coefficient Encoded signed value (from -1024 to 1023)" newline rbitfld.long 0x4C 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x4C 0.--10. 1. "BY,BY coefficient Encoded signed value (from -1024 to 1023)" line.long 0x50 "DISPC_VID_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline" hexmask.long.tbyte 0x50 11.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x50 0.--10. 1. "BCB,BCb Coefficient Encoded signed value (from -1024 to 1023)" line.long 0x54 "DISPC_VID_CONV_COEF5,The register configures the color space conversion matrix coefficients for the video pipeline" hexmask.long.word 0x54 19.--31. 1. "GOFFSET,G offset Encoded signed value (from -4096 to 4095)" rbitfld.long 0x54 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x54 3.--15. 1. "ROFFSET,R offset Encoded signed value (from -4096 to 4095)" rbitfld.long 0x54 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x58 "DISPC_VID_CONV_COEF6,The register configures the color space conversion matrix coefficients for the video pipeline" hexmask.long.word 0x58 16.--31. 1. "RESERVED," hexmask.long.word 0x58 3.--15. 1. "BOFFSET,B offset Encoded signed value (from -4096 to 4095)" newline rbitfld.long 0x58 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x5C "DISPC_VID_FIRH,The register configures the resize factor for horizontal up/down-sampling of the video window" hexmask.long.byte 0x5C 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x5C 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter" line.long 0x60 "DISPC_VID_FIRH2,The register configures the resize factor for horizontal up/down-sampling of the video window" hexmask.long.byte 0x60 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x60 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter for Cb and Cr" line.long 0x64 "DISPC_VID_FIRV,The register configures the resize factor for vertical up/down-sampling of the video window" hexmask.long.byte 0x64 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x64 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter" line.long 0x68 "DISPC_VID_FIRV2,The register configures the resize factor for vertical up/down-sampling of the video window" hexmask.long.byte 0x68 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x68 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter for Cb and Cr" line.long 0x6C "DISPC_VID_FIR_COEF_H0_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x6C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x6C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x6C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x70 "DISPC_VID_FIR_COEF_H0_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x70 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x70 10.--29. 1. "RESERVED," newline hexmask.long.word 0x70 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x74 "DISPC_VID_FIR_COEF_H0_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x74 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x74 10.--29. 1. "RESERVED," newline hexmask.long.word 0x74 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x78 "DISPC_VID_FIR_COEF_H0_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x78 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x78 10.--29. 1. "RESERVED," newline hexmask.long.word 0x78 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x7C "DISPC_VID_FIR_COEF_H0_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x7C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x7C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x7C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x80 "DISPC_VID_FIR_COEF_H0_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x80 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x80 10.--29. 1. "RESERVED," newline hexmask.long.word 0x80 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x84 "DISPC_VID_FIR_COEF_H0_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x84 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x84 10.--29. 1. "RESERVED," newline hexmask.long.word 0x84 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x88 "DISPC_VID_FIR_COEF_H0_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x88 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x88 10.--29. 1. "RESERVED," newline hexmask.long.word 0x88 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x8C "DISPC_VID_FIR_COEF_H0_i_8,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x8C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x8C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x8C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x90 "DISPC_VID_FIR_COEF_H0_C_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x90 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x90 10.--29. 1. "RESERVED," newline hexmask.long.word 0x90 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x94 "DISPC_VID_FIR_COEF_H0_C_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x94 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x94 10.--29. 1. "RESERVED," newline hexmask.long.word 0x94 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x98 "DISPC_VID_FIR_COEF_H0_C_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x98 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x98 10.--29. 1. "RESERVED," newline hexmask.long.word 0x98 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x9C "DISPC_VID_FIR_COEF_H0_C_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x9C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x9C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x9C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xA0 "DISPC_VID_FIR_COEF_H0_C_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0xA0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xA0 10.--29. 1. "RESERVED," newline hexmask.long.word 0xA0 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xA4 "DISPC_VID_FIR_COEF_H0_C_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0xA4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xA4 10.--29. 1. "RESERVED," newline hexmask.long.word 0xA4 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xA8 "DISPC_VID_FIR_COEF_H0_C_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0xA8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xA8 10.--29. 1. "RESERVED," newline hexmask.long.word 0xA8 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xAC "DISPC_VID_FIR_COEF_H0_C_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0xAC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xAC 10.--29. 1. "RESERVED," newline hexmask.long.word 0xAC 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xB0 "DISPC_VID_FIR_COEF_H0_C_i_8,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0xB0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xB0 10.--29. 1. "RESERVED," newline hexmask.long.word 0xB0 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xB4 "DISPC_VID_FIR_COEF_H12_k_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xB4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xB4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xB4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xB4 0.--9. 1. "RESERVED," line.long 0xB8 "DISPC_VID_FIR_COEF_H12_k_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xB8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xB8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xB8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xB8 0.--9. 1. "RESERVED," line.long 0xBC "DISPC_VID_FIR_COEF_H12_k_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xBC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xBC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xBC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xBC 0.--9. 1. "RESERVED," line.long 0xC0 "DISPC_VID_FIR_COEF_H12_k_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xC0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xC0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xC0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xC0 0.--9. 1. "RESERVED," line.long 0xC4 "DISPC_VID_FIR_COEF_H12_k_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xC4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xC4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xC4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xC4 0.--9. 1. "RESERVED," line.long 0xC8 "DISPC_VID_FIR_COEF_H12_k_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xC8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xC8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xC8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xC8 0.--9. 1. "RESERVED," line.long 0xCC "DISPC_VID_FIR_COEF_H12_k_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xCC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xCC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xCC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xCC 0.--9. 1. "RESERVED," line.long 0xD0 "DISPC_VID_FIR_COEF_H12_k_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xD0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xD0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xD0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xD0 0.--9. 1. "RESERVED," line.long 0xD4 "DISPC_VID_FIR_COEF_H12_k_8,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xD4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xD4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xD4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xD4 0.--9. 1. "RESERVED," line.long 0xD8 "DISPC_VID_FIR_COEF_H12_k_9,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xD8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xD8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xD8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xD8 0.--9. 1. "RESERVED," line.long 0xDC "DISPC_VID_FIR_COEF_H12_k_10,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xDC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xDC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xDC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xDC 0.--9. 1. "RESERVED," line.long 0xE0 "DISPC_VID_FIR_COEF_H12_k_11,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xE0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xE0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xE0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xE0 0.--9. 1. "RESERVED," line.long 0xE4 "DISPC_VID_FIR_COEF_H12_k_12,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xE4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xE4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xE4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xE4 0.--9. 1. "RESERVED," line.long 0xE8 "DISPC_VID_FIR_COEF_H12_k_13,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xE8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xE8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xE8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xE8 0.--9. 1. "RESERVED," line.long 0xEC "DISPC_VID_FIR_COEF_H12_k_14,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xEC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xEC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xEC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xEC 0.--9. 1. "RESERVED," line.long 0xF0 "DISPC_VID_FIR_COEF_H12_k_15,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0xF0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xF0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xF0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xF0 0.--9. 1. "RESERVED," line.long 0xF4 "DISPC_VID_FIR_COEF_H12_C_k_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0xF4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xF4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xF4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xF4 0.--9. 1. "RESERVED," line.long 0xF8 "DISPC_VID_FIR_COEF_H12_C_k_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0xF8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xF8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xF8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xF8 0.--9. 1. "RESERVED," line.long 0xFC "DISPC_VID_FIR_COEF_H12_C_k_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0xFC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xFC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xFC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xFC 0.--9. 1. "RESERVED," line.long 0x100 "DISPC_VID_FIR_COEF_H12_C_k_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x100 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x100 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x100 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x100 0.--9. 1. "RESERVED," line.long 0x104 "DISPC_VID_FIR_COEF_H12_C_k_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x104 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x104 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x104 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x104 0.--9. 1. "RESERVED," line.long 0x108 "DISPC_VID_FIR_COEF_H12_C_k_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x108 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x108 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x108 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x108 0.--9. 1. "RESERVED," line.long 0x10C "DISPC_VID_FIR_COEF_H12_C_k_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x10C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x10C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x10C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x10C 0.--9. 1. "RESERVED," line.long 0x110 "DISPC_VID_FIR_COEF_H12_C_k_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x110 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x110 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x110 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x110 0.--9. 1. "RESERVED," line.long 0x114 "DISPC_VID_FIR_COEF_H12_C_k_8,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x114 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x114 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x114 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x114 0.--9. 1. "RESERVED," line.long 0x118 "DISPC_VID_FIR_COEF_H12_C_k_9,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x118 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x118 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x118 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x118 0.--9. 1. "RESERVED," line.long 0x11C "DISPC_VID_FIR_COEF_H12_C_k_10,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x11C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x11C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x11C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x11C 0.--9. 1. "RESERVED," line.long 0x120 "DISPC_VID_FIR_COEF_H12_C_k_11,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x120 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x120 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x120 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x120 0.--9. 1. "RESERVED," line.long 0x124 "DISPC_VID_FIR_COEF_H12_C_k_12,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x124 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x124 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x124 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x124 0.--9. 1. "RESERVED," line.long 0x128 "DISPC_VID_FIR_COEF_H12_C_k_13,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x128 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x128 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x128 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x128 0.--9. 1. "RESERVED," line.long 0x12C "DISPC_VID_FIR_COEF_H12_C_k_14,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x12C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x12C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x12C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x12C 0.--9. 1. "RESERVED," line.long 0x130 "DISPC_VID_FIR_COEF_H12_C_k_15,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x130 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x130 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x130 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x130 0.--9. 1. "RESERVED," line.long 0x134 "DISPC_VID_FIR_COEF_V0_i_0,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x134 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x134 10.--29. 1. "RESERVED," newline hexmask.long.word 0x134 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x138 "DISPC_VID_FIR_COEF_V0_i_1,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x138 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x138 10.--29. 1. "RESERVED," newline hexmask.long.word 0x138 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x13C "DISPC_VID_FIR_COEF_V0_i_2,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x13C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x13C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x13C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x140 "DISPC_VID_FIR_COEF_V0_i_3,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x140 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x140 10.--29. 1. "RESERVED," newline hexmask.long.word 0x140 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x144 "DISPC_VID_FIR_COEF_V0_i_4,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x144 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x144 10.--29. 1. "RESERVED," newline hexmask.long.word 0x144 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x148 "DISPC_VID_FIR_COEF_V0_i_5,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x148 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x148 10.--29. 1. "RESERVED," newline hexmask.long.word 0x148 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x14C "DISPC_VID_FIR_COEF_V0_i_6,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x14C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x14C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x14C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x150 "DISPC_VID_FIR_COEF_V0_i_7,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x150 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x150 10.--29. 1. "RESERVED," newline hexmask.long.word 0x150 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x154 "DISPC_VID_FIR_COEF_V0_i_8,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x154 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x154 10.--29. 1. "RESERVED," newline hexmask.long.word 0x154 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x158 "DISPC_VID_FIR_COEF_V0_C_i_0,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x158 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x158 10.--29. 1. "RESERVED," newline hexmask.long.word 0x158 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x15C "DISPC_VID_FIR_COEF_V0_C_i_1,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x15C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x15C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x15C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x160 "DISPC_VID_FIR_COEF_V0_C_i_2,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x160 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x160 10.--29. 1. "RESERVED," newline hexmask.long.word 0x160 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x164 "DISPC_VID_FIR_COEF_V0_C_i_3,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x164 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x164 10.--29. 1. "RESERVED," newline hexmask.long.word 0x164 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x168 "DISPC_VID_FIR_COEF_V0_C_i_4,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x168 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x168 10.--29. 1. "RESERVED," newline hexmask.long.word 0x168 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x16C "DISPC_VID_FIR_COEF_V0_C_i_5,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x16C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x16C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x16C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x170 "DISPC_VID_FIR_COEF_V0_C_i_6,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x170 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x170 10.--29. 1. "RESERVED," newline hexmask.long.word 0x170 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x174 "DISPC_VID_FIR_COEF_V0_C_i_7,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x174 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x174 10.--29. 1. "RESERVED," newline hexmask.long.word 0x174 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x178 "DISPC_VID_FIR_COEF_V0_C_i_8,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x178 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x178 10.--29. 1. "RESERVED," newline hexmask.long.word 0x178 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x17C "DISPC_VID_FIR_COEF_V12_k_0,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x17C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x17C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x17C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x17C 0.--9. 1. "RESERVED," line.long 0x180 "DISPC_VID_FIR_COEF_V12_k_1,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x180 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x180 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x180 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x180 0.--9. 1. "RESERVED," line.long 0x184 "DISPC_VID_FIR_COEF_V12_k_2,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x184 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x184 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x184 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x184 0.--9. 1. "RESERVED," line.long 0x188 "DISPC_VID_FIR_COEF_V12_k_3,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x188 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x188 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x188 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x188 0.--9. 1. "RESERVED," line.long 0x18C "DISPC_VID_FIR_COEF_V12_k_4,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x18C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x18C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x18C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x18C 0.--9. 1. "RESERVED," line.long 0x190 "DISPC_VID_FIR_COEF_V12_k_5,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x190 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x190 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x190 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x190 0.--9. 1. "RESERVED," line.long 0x194 "DISPC_VID_FIR_COEF_V12_k_6,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x194 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x194 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x194 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x194 0.--9. 1. "RESERVED," line.long 0x198 "DISPC_VID_FIR_COEF_V12_k_7,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x198 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x198 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x198 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x198 0.--9. 1. "RESERVED," line.long 0x19C "DISPC_VID_FIR_COEF_V12_k_8,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x19C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x19C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x19C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x19C 0.--9. 1. "RESERVED," line.long 0x1A0 "DISPC_VID_FIR_COEF_V12_k_9,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x1A0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1A0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1A0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1A0 0.--9. 1. "RESERVED," line.long 0x1A4 "DISPC_VID_FIR_COEF_V12_k_10,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x1A4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1A4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1A4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1A4 0.--9. 1. "RESERVED," line.long 0x1A8 "DISPC_VID_FIR_COEF_V12_k_11,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x1A8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1A8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1A8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1A8 0.--9. 1. "RESERVED," line.long 0x1AC "DISPC_VID_FIR_COEF_V12_k_12,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x1AC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1AC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1AC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1AC 0.--9. 1. "RESERVED," line.long 0x1B0 "DISPC_VID_FIR_COEF_V12_k_13,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x1B0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1B0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1B0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1B0 0.--9. 1. "RESERVED," line.long 0x1B4 "DISPC_VID_FIR_COEF_V12_k_14,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x1B4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1B4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1B4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1B4 0.--9. 1. "RESERVED," line.long 0x1B8 "DISPC_VID_FIR_COEF_V12_k_15,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases It is used for ARGB and Y setting" rbitfld.long 0x1B8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1B8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1B8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1B8 0.--9. 1. "RESERVED," line.long 0x1BC "DISPC_VID_FIR_COEF_V12_C_k_0,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1BC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1BC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1BC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1BC 0.--9. 1. "RESERVED," line.long 0x1C0 "DISPC_VID_FIR_COEF_V12_C_k_1,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1C0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1C0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1C0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1C0 0.--9. 1. "RESERVED," line.long 0x1C4 "DISPC_VID_FIR_COEF_V12_C_k_2,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1C4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1C4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1C4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1C4 0.--9. 1. "RESERVED," line.long 0x1C8 "DISPC_VID_FIR_COEF_V12_C_k_3,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1C8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1C8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1C8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1C8 0.--9. 1. "RESERVED," line.long 0x1CC "DISPC_VID_FIR_COEF_V12_C_k_4,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1CC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1CC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1CC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1CC 0.--9. 1. "RESERVED," line.long 0x1D0 "DISPC_VID_FIR_COEF_V12_C_k_5,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1D0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1D0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1D0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1D0 0.--9. 1. "RESERVED," line.long 0x1D4 "DISPC_VID_FIR_COEF_V12_C_k_6,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1D4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1D4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1D4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1D4 0.--9. 1. "RESERVED," line.long 0x1D8 "DISPC_VID_FIR_COEF_V12_C_k_7,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1D8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1D8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1D8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1D8 0.--9. 1. "RESERVED," line.long 0x1DC "DISPC_VID_FIR_COEF_V12_C_k_8,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1DC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1DC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1DC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1DC 0.--9. 1. "RESERVED," line.long 0x1E0 "DISPC_VID_FIR_COEF_V12_C_k_9,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1E0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1E0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1E0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1E0 0.--9. 1. "RESERVED," line.long 0x1E4 "DISPC_VID_FIR_COEF_V12_C_k_10,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1E4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1E4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1E4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1E4 0.--9. 1. "RESERVED," line.long 0x1E8 "DISPC_VID_FIR_COEF_V12_C_k_11,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1E8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1E8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1E8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1E8 0.--9. 1. "RESERVED," line.long 0x1EC "DISPC_VID_FIR_COEF_V12_C_k_12,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1EC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1EC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1EC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1EC 0.--9. 1. "RESERVED," line.long 0x1F0 "DISPC_VID_FIR_COEF_V12_C_k_13,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1F0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1F0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1F0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1F0 0.--9. 1. "RESERVED," line.long 0x1F4 "DISPC_VID_FIR_COEF_V12_C_k_14,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1F4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1F4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1F4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1F4 0.--9. 1. "RESERVED," line.long 0x1F8 "DISPC_VID_FIR_COEF_V12_C_k_15,The bank of registers configure the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15" rbitfld.long 0x1F8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1F8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1F8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1F8 0.--9. 1. "RESERVED," line.long 0x1FC "DISPC_VID_GLOBAL_ALPHA,The register defines the global alpha value for the video pipeline" hexmask.long.tbyte 0x1FC 8.--31. 1. "RESERVED," hexmask.long.byte 0x1FC 0.--7. 1. "GLOBALALPHA,Global alpha value from 0 to 255" line.long 0x200 "DISPC_VID_IRQENABLE,This register allows to mask/unmask the module internal sources of interrupt. on an event-by-event basis" hexmask.long 0x200 4.--31. 1. "RESERVED," bitfld.long 0x200 3. "VIDREGIONBASEDPIPEEND_EN,PIPE end window IRQ for region-based feature" "VIDREGIONBASEDPIPEEND_EN_0,VIDREGIONBASEDPIPEEND_EN_1" newline bitfld.long 0x200 2. "VIDREGIONBASEDPIPESTART_EN,PIPE start window IRQ for region-based feature" "VIDREGIONBASEDPIPESTART_EN_0,VIDREGIONBASEDPIPESTART_EN_1" bitfld.long 0x200 1. "VIDENDWINDOW_EN,The end of the video Window has been reached" "VIDENDWINDOW_EN_0,VIDENDWINDOW_EN_1" newline bitfld.long 0x200 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow" "VIDBUFFERUNDERFLOW_EN_0,VIDBUFFERUNDERFLOW_EN_1" line.long 0x204 "DISPC_VID_IRQSTATUS,This register regroups all the status of the module internal events that generate an interrupt" hexmask.long 0x204 4.--31. 1. "RESERVED," bitfld.long 0x204 3. "VIDREGIONBASEDPIPEEND_IRQ,PIPE end window IRQ for region-based feature" "VIDREGIONBASEDPIPEEND_IRQ_0,VIDREGIONBASEDPIPEEND_IRQ_1" newline bitfld.long 0x204 2. "VIDREGIONBASEDPIPESTART_IRQ,PIPE start window IRQ for region-based feature" "VIDREGIONBASEDPIPESTART_IRQ_0,VIDREGIONBASEDPIPESTART_IRQ_1" bitfld.long 0x204 1. "VIDENDWINDOW_IRQ,The end of the video Window has been reached" "VIDENDWINDOW_IRQ_0,VIDENDWINDOW_IRQ_1" newline bitfld.long 0x204 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow" "VIDBUFFERUNDERFLOW_IRQ_0,VIDBUFFERUNDERFLOW_IRQ_1" line.long 0x208 "DISPC_VID_MFLAG_THRESHOLD,MFLAG thresholds for video pipelines" hexmask.long.word 0x208 16.--31. 1. "HT_MFLAG,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level MFLAG is reset to 0" hexmask.long.word 0x208 0.--15. 1. "LT_MFLAG,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level MFLAG is set to 1" line.long 0x20C "DISPC_VID_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer before up/down-scaling" rbitfld.long 0x20C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x20C 16.--27. 1. "MEMSIZEY,Number of lines of the video picture Encoded value (from 1 to 4096) to specify the number of lines of the video picture in memory (program to value minus one)" newline rbitfld.long 0x20C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x20C 0.--11. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value (from 1 to 4096) to specify the number of pixels of the video picture in memory (program to value minus one)" line.long 0x210 "DISPC_VID_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window" hexmask.long.tbyte 0x210 8.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.byte 0x210 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels" line.long 0x214 "DISPC_VID_POSITION,The register configures the position of the video window" rbitfld.long 0x214 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x214 16.--27. 1. "POSY,Y position of the video window Encoded value (from 0 to 4095) to specify the Y position of the video window #1 .The line at the top has the Y-position 0" newline rbitfld.long 0x214 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x214 0.--11. 1. "POSX,X position of the video window Encoded value (from 0 to 4095) to specify the X position of the video window #1" line.long 0x218 "DISPC_VID_PRELOAD,The register configures the DMA buffer of the video pipeline" hexmask.long.tbyte 0x218 12.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x218 0.--11. 1. "PRELOAD,DMA buffer preload value Number of 128-bit words defining the preload value" line.long 0x21C "DISPC_VID_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window" line.long 0x220 "DISPC_VID_SIZE,The register configures the size of the video window" rbitfld.long 0x220 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x220 16.--27. 1. "SIZEY,Number of lines of the video window" newline rbitfld.long 0x220 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x220 0.--11. 1. "SIZEX,Number of pixels of the video window" line.long 0x224 "DISPC_VID_CLUT,The register configures the Color Look Up Table (CLUT) for VID pipeline" hexmask.long.byte 0x224 24.--31. 1. "INDEX,Defines the location in the table where the bit-field VALUE is stored" hexmask.long.byte 0x224 16.--23. 1. "VALUE_R,8-bit value used to defined the value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x224 8.--15. 1. "VALUE_G,8-bit value used to defined the value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x224 0.--7. 1. "VALUE_B,8-bit value used to defined the value to store at the location in the table defined by the bit-field INDEX" width 0x0B tree.end repeat.end tree "DISPC_VP1" base ad:0x5801AC00 group.long 0x00++0x23 line.long 0x00 "DISPC_VP1_CONFIG,The control register configures the Display Controller module for the VP output" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 25. "FULLRANGE,Color Space Conversion full range setting" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x00 24. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1" bitfld.long 0x00 23. "FIDFIRST,Selects the first field to output in case of interlace mode" "FIDFIRST_0,FIDFIRST_1" newline bitfld.long 0x00 22. "OUTPUTMODEENABLE,Selects between progressive and interlace mode for the VP output" "OUTPUTMODEENABLE_0,OUTPUTMODEENABLE_1" bitfld.long 0x00 21. "BT1120ENABLE,Selects BT-1120 format on the VP output" "BT1120ENABLE_0,BT1120ENABLE_1" newline bitfld.long 0x00 20. "BT656ENABLE,Selects BT-656 format on the VP output" "BT656ENABLE_0,BT656ENABLE_1" rbitfld.long 0x00 17.--19. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. "BUFFERHANDSHAKE,Controls the handsSHAKE between DMA buffer and STALL signal in order to prevent from underflow" "BUFFERHANDSHAKE_0,BUFFERHANDSHAKE_1" bitfld.long 0x00 15. "CPR,Color Phase Rotation Control VP output). It shall be reset when ColorConvEnable bit-field is set to 1. Shadow bit-field" "CPR_0,CPR_1" newline rbitfld.long 0x00 9.--14. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8. "EXTERNALSYNCEN,Selects between external sync and internal sync mode for the VP output" "EXTERNALSYNCEN_0,EXTERNALSYNCEN_1" newline bitfld.long 0x00 7. "VSYNCGATED,VSYNC Gated Enabled (VP output) Shadow bit-field" "VSYNCGATED_0,VSYNCGATED_1" bitfld.long 0x00 6. "HSYNCGATED,HSYNC Gated Enabled (VP output) Shadow bit-field" "HSYNCGATED_0,HSYNCGATED_1" newline bitfld.long 0x00 5. "PIXELCLOCKGATED,Pixel Clock Gated Enabled (VP output) Shadow bit-field" "PIXELCLOCKGATED_0,PIXELCLOCKGATED_1" bitfld.long 0x00 4. "PIXELDATAGATED,Pixel Data Gated Enabled (VP output) Shadow bit-field" "PIXELDATAGATED_0,PIXELDATAGATED_1" newline bitfld.long 0x00 3. "HDMIMODE,Configures the timing generator in HDMI compatible mode to generate same timings as HDMI wrapper timings" "HDMIMODE_0,HDMIMODE_1" bitfld.long 0x00 2. "GAMMAENABLE,Enable the gamma Shadow bit-field" "GAMMAENABLE_0,GAMMAENABLE_1" newline bitfld.long 0x00 1. "DATAENABLEGATED,DE Gated Enable Shadow bit-field" "DATAENABLEGATED_0,DATAENABLEGATED_1" bitfld.long 0x00 0. "PIXELGATED,Pixel Gated Enable Shadow bit-field" "PIXELGATED_0,PIXELGATED_1" line.long 0x04 "DISPC_VP1_CONTROL,The control register configures the Display Controller module for the VP output" bitfld.long 0x04 30.--31. "SPATIALTEMPORALDITHERINGFRAMES,Spatial/Temporal dithering number of frames for the VP output" "SPATIALTEMPORALDITHERINGFRAMES_0,SPATIALTEMPORALDITHERINGFRAMES_1,SPATIALTEMPORALDITHERINGFRAMES_2,SPATIALTEMPORALDITHERINGFRAMES_3" rbitfld.long 0x04 27.--29. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 25.--26. "TDMUNUSEDBITS,State of unused bits (TDM mode only) for the VP output" "TDMUNUSEDBITS_0,TDMUNUSEDBITS_1,TDMUNUSEDBITS_2,TDMUNUSEDBITS_3" bitfld.long 0x04 23.--24. "TDMCYCLEFORMAT,Cycle format (TDM mode only) for the VP output" "TDMCYCLEFORMAT_0,TDMCYCLEFORMAT_1,TDMCYCLEFORMAT_2,TDMCYCLEFORMAT_3" newline bitfld.long 0x04 21.--22. "TDMPARALLELMODE,Output Interface width (TDM mode only) for the VP output" "TDMPARALLELMODE_0,TDMPARALLELMODE_1,TDMPARALLELMODE_2,TDMPARALLELMODE_3" bitfld.long 0x04 20. "TDMENABLE,Enable the multiple cycle format for the VP output" "TDMENABLE_0,TDMENABLE_1" newline rbitfld.long 0x04 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 14.--16. "HT,Hold Time for VP output" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 13. "RESERVED," "0,1" rbitfld.long 0x04 12. "RESERVED," "0,1" newline bitfld.long 0x04 11. "STALLMODE,STALL Mode for the VP output" "STALLMODE_0,STALLMODE_1" bitfld.long 0x04 8.--10. "DATALINES,Width of the data bus on VP output" "DATALINES_0,DATALINES_1,DATALINES_2,DATALINES_3,DATALINES_4,DATALINES_5,?,?" newline bitfld.long 0x04 7. "STDITHERENABLE,Spatial Temporal dithering enable for the VP output Shadow bit-field" "STDITHERENABLE_0,STDITHERENABLE_1" rbitfld.long 0x04 6. "RESERVED," "0,1" newline bitfld.long 0x04 5. "GOBIT,GO Command for the VP output" "GOBIT_0,GOBIT_1" rbitfld.long 0x04 2.--4. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 1. "VPPROGLINENUMBERMODULO,Enable the modulo of the line number interrupt generation" "VPPROGLINENUMBERMODULO_0,VPPROGLINENUMBERMODULO_1" bitfld.long 0x04 0. "VPENABLE,Enable the video port output wr:immediate" "VPENABLE_0,VPENABLE_1" line.long 0x08 "DISPC_VP1_CPR_COEF_B,The register configures the color phase rotation matrix coefficients for the Blue component" hexmask.long.word 0x08 22.--31. 1. "BR,BR Coefficient Encoded signed value (from -512 to 511)" rbitfld.long 0x08 21. "RESERVED,Write 0's for future compatibility" "0,1" newline hexmask.long.word 0x08 11.--20. 1. "BG,BG Coefficient Encoded signed value (from -512 to 511)" rbitfld.long 0x08 10. "RESERVED,Write 0's for future compatibility" "0,1" newline hexmask.long.word 0x08 0.--9. 1. "BB,BB Coefficient Encoded signed value (from -512 to 511)" line.long 0x0C "DISPC_VP1_CPR_COEF_G,The register configures the color phase rotation matrix coefficients for the Green component" hexmask.long.word 0x0C 22.--31. 1. "GR,GR Coefficient Encoded signed value (from -512 to 511)" rbitfld.long 0x0C 21. "RESERVED,Write 0's for future compatibility" "0,1" newline hexmask.long.word 0x0C 11.--20. 1. "GG,GG Coefficient Encoded signed value (from -512 to 511)" rbitfld.long 0x0C 10. "RESERVED,Write 0's for future compatibility" "0,1" newline hexmask.long.word 0x0C 0.--9. 1. "GB,GB Coefficient Encoded signed value (from -512 to 511)" line.long 0x10 "DISPC_VP1_CPR_COEF_R,The register configures the color phase rotation matrix coefficients for the Red component" hexmask.long.word 0x10 22.--31. 1. "RR,RR Coefficient Encoded signed value (from -512 to 511)" rbitfld.long 0x10 21. "RESERVED,Write 0's for future compatibility" "0,1" newline hexmask.long.word 0x10 11.--20. 1. "RG,RG Coefficient Encoded signed value (from -512 to 511)" rbitfld.long 0x10 10. "RESERVED,Write 0's for future compatibility" "0,1" newline hexmask.long.word 0x10 0.--9. 1. "RB,RB Coefficient Encoded signed value (from -512 to 511)" line.long 0x14 "DISPC_VP1_DATA_CYCLE_l_0,The control register configures the output data format over up to 3 cycles" rbitfld.long 0x14 28.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel#2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x14 21.--23. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel #2 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x14 12.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel#1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x14 5.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel #1 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "DISPC_VP1_DATA_CYCLE_l_1,The control register configures the output data format over up to 3 cycles" rbitfld.long 0x18 28.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel#2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x18 21.--23. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel #2 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x18 12.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel#1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x18 5.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel #1 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "DISPC_VP1_DATA_CYCLE_l_2,The control register configures the output data format over up to 3 cycles" rbitfld.long 0x1C 28.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel#2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 21.--23. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel #2 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x1C 12.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel#1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 5.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel #1 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "DISPC_VP1_GAMMA_TABLE,The register configures the gamma table on VP output" hexmask.long.byte 0x20 24.--31. 1. "INDEX,Defines the location in the table where the bit-field VALUE is stored" hexmask.long.byte 0x20 16.--23. 1. "VALUE_R,8-bit value used to defined the value to be stored in the gamma table" newline hexmask.long.byte 0x20 8.--15. 1. "VALUE_G,8-bit value used to defined the value to be stored in the gamma table" hexmask.long.byte 0x20 0.--7. 1. "VALUE_B,8-bit value used to defined the value to be stored in the gamma table" group.long 0x3C++0x1F line.long 0x00 "DISPC_VP1_IRQENABLE,This register allows to mask/unmask the module internal sources of interrupt. on an event-by-event basis" hexmask.long 0x00 5.--31. 1. "RESERVED," bitfld.long 0x00 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "VPSYNCLOST_EN_0,VPSYNCLOST_EN_1" newline bitfld.long 0x00 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number" "VPPROGRAMMEDLINENUMBER_EN_0,VPPROGRAMMEDLINENUMBER_EN_1" bitfld.long 0x00 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "VPVSYNC_ODD_EN_0,VPVSYNC_ODD_EN_1" newline bitfld.long 0x00 1. "VPVSYNC_EN,Vertical Synchronization for VP" "VPVSYNC_EN_0,VPVSYNC_EN_1" bitfld.long 0x00 0. "VPFRAMEDONE_EN,Frame Done for Video Port" "VPFRAMEDONE_EN_0,VPFRAMEDONE_EN_1" line.long 0x04 "DISPC_VP1_IRQSTATUS,This register regroups all the status of the module internal events that generate an interrupt" hexmask.long 0x04 5.--31. 1. "RESERVED," bitfld.long 0x04 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output" "VPSYNCLOST_IRQ_0,VPSYNCLOST_IRQ_1" newline bitfld.long 0x04 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number" "VPPROGRAMMEDLINENUMBER_IRQ_0,VPPROGRAMMEDLINENUMBER_IRQ_1" bitfld.long 0x04 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field from interlace mode only" "VPVSYNC_ODD_IRQ_0,VPVSYNC_ODD_IRQ_1" newline bitfld.long 0x04 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output" "VPVSYNC_IRQ_0,VPVSYNC_IRQ_1" bitfld.long 0x04 0. "VPFRAMEDONE_IRQ,Frame Done for VP" "VPFRAMEDONE_IRQ_0,VPFRAMEDONE_IRQ_1" line.long 0x08 "DISPC_VP1_LINE_NUMBER,The control register indicates the panel display line number for the interrupt and the DMA request" hexmask.long.tbyte 0x08 12.--31. 1. "RESERVED," hexmask.long.word 0x08 0.--11. 1. "LINENUMBER,Display panel line number programming" line.long 0x0C "DISPC_VP1_LINE_STATUS,The control register indicates the panel display line number" hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED," hexmask.long.word 0x0C 0.--11. 1. "LINENUMBER,Current display panel line number" line.long 0x10 "DISPC_VP1_POL_FREQ,The register configures the signal configuration" hexmask.long.word 0x10 19.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x10 18. "ALIGN,Defines the alignment betwwen HSYNC and VSYNC assertion" "ALIGN_0,ALIGN_1" newline bitfld.long 0x10 17. "ONOFF,HSYNC/VSYNC Pixel clock Control On/Off" "ONOFF_0,ONOFF_1" bitfld.long 0x10 16. "RF,Program HSYNC/VSYNC Rise or Fall" "RF_0,RF_1" newline bitfld.long 0x10 15. "IEO,Invert output enable" "IEO_0,IEO_1" bitfld.long 0x10 14. "IPC,Invert pixel clock" "IPC_0,IPC_1" newline bitfld.long 0x10 13. "IHS,Invert HSYNC" "IHS_0,IHS_1" bitfld.long 0x10 12. "IVS,Invert VSYNC" "IVS_0,IVS_1" newline hexmask.long.word 0x10 0.--11. 1. "RESERVED," line.long 0x14 "DISPC_VP1_SIZE_SCREEN,The register configures the panel size (horizontal and vertical)" rbitfld.long 0x14 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x14 16.--27. 1. "LPP,Lines per panel Encoded value (from 1 to 4096) to specify the number of lines per panel (program to value minus one)" newline bitfld.long 0x14 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field" "DELTA_LPP_0,DELTA_LPP_1,DELTA_LPP_2,?" rbitfld.long 0x14 12.--13. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "PPL,Pixels per line Encoded value (from 1 to 4096) to specify the number of pixels contains within each line on the display (program to value minus one)" line.long 0x18 "DISPC_VP1_TIMING_H,The register configures the timing logic for the HSYNC signal" hexmask.long.word 0x18 20.--31. 1. "HBP,Horizontal Back Porch" hexmask.long.word 0x18 8.--19. 1. "HFP,Horizontal front porch" newline hexmask.long.byte 0x18 0.--7. 1. "HSW,Horizontal synchronization pulse width Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line display (program to value minus one)" line.long 0x1C "DISPC_VP1_TIMING_V,The register configures the timing logic for the VSYNC signal" hexmask.long.word 0x1C 20.--31. 1. "VBP,Vertical back porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame" hexmask.long.word 0x1C 8.--19. 1. "VFP,Vertical front porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame" newline hexmask.long.byte 0x1C 0.--7. 1. "VSW,Vertical synchronization pulse width Encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus one) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses" width 0x0B tree.end tree "DISPC_WB" base ad:0x58015000 group.long 0x00++0x20B line.long 0x00 "DISPC_WB_ACCUH_j_0,The register configures the resize accumulator init values for horizontal up/down-sampling of the wirte-back window It is used for ARGB and Y setting" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x04 "DISPC_WB_ACCUH_j_1,The register configures the resize accumulator init values for horizontal up/down-sampling of the wirte-back window It is used for ARGB and Y setting" hexmask.long.byte 0x04 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x04 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x08 "DISPC_WB_ACCUH2_j_0,The register configures the resize accumulator init value for horizontal up/down-sampling of the write-back window It is used for Cb and Cr setting" hexmask.long.byte 0x08 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x08 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x0C "DISPC_WB_ACCUH2_j_1,The register configures the resize accumulator init value for horizontal up/down-sampling of the write-back window It is used for Cb and Cr setting" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x0C 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x10 "DISPC_WB_ACCUV_j_0,The register configures the resize accumulator init value for vertical up/down-sampling of the wirte-back window It is used for ARGB and Y setting" hexmask.long.byte 0x10 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x10 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x14 "DISPC_WB_ACCUV_j_1,The register configures the resize accumulator init value for vertical up/down-sampling of the wirte-back window It is used for ARGB and Y setting" hexmask.long.byte 0x14 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x14 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x18 "DISPC_WB_ACCUV2_j_0,The register configures the resize accumulator init value for vertical up/down-sampling of the write-back window It is used for Cb and Cr setting" hexmask.long.byte 0x18 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x18 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x1C "DISPC_WB_ACCUV2_j_1,The register configures the resize accumulator init value for vertical up/down-sampling of the write-back window It is used for Cb and Cr setting" hexmask.long.byte 0x1C 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x1C 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x20 "DISPC_WB_ATTRIBUTES,The register configures the attributes of the viwrite back pipeline" bitfld.long 0x20 28.--31. "IDLENUMBER,Determines the number of idles between requests on the L3 interconnect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x20 27. "IDLESIZE,Determines if the IDLENUMBER corresponds to a number of bursts or singles" "IDLESIZE_0,IDLESIZE_1" newline bitfld.long 0x20 24.--26. "CAPTUREMODE,Defines the frame rate capture" "CAPTUREMODE_0,CAPTUREMODE_1,CAPTUREMODE_2,CAPTUREMODE_3,CAPTUREMODE_4,CAPTUREMODE_5,CAPTUREMODE_6,CAPTUREMODE_7" bitfld.long 0x20 23. "ARBITRATION,Determines the priority of the write-back pipeline" "ARBITRATION_0,ARBITRATION_1" newline bitfld.long 0x20 22. "DOUBLESTRIDE,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride" "DOUBLESTRIDE_0,DOUBLESTRIDE_1" bitfld.long 0x20 21. "VERTICALTAPS,Video Vertical Resize Tap Number" "VERTICALTAPS_0,VERTICALTAPS_1" newline rbitfld.long 0x20 20. "RESERVED," "0,1" bitfld.long 0x20 19. "WRITEBACKMODE,When connected to the overlay output of a channel the write back can operate as a simple transfer from memory to memory (composition engine) or as a capture channel" "WRITEBACKMODE_0,WRITEBACKMODE_1" newline bitfld.long 0x20 15.--18. "CHANNELIN,WB Channel In configuration wr: immediate" "CHANNELIN_0,CHANNELIN_1,?,?,CHANNELIN_4,?,?,CHANNELIN_7,CHANNELIN_8,?,?,?,?,?,?,?" rbitfld.long 0x20 13.--14. "RESERVED," "0,1,2,3" newline bitfld.long 0x20 12. "FULLRANGE,Color Space Conversion full range setting" "FULLRANGE_0,FULLRANGE_1" bitfld.long 0x20 11. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1" newline rbitfld.long 0x20 10. "RESERVED," "0,1" bitfld.long 0x20 9. "ALPHAENABLE,Premultiplied alpha enable" "ALPHAENABLE_0,ALPHAENABLE_1" newline bitfld.long 0x20 7.--8. "RESIZEENABLE,Resize Enable" "RESIZEENABLE_0,RESIZEENABLE_1,RESIZEENABLE_2,RESIZEENABLE_3" bitfld.long 0x20 1.--6. "FORMAT,Write-back Format" "FORMAT_0,FORMAT_1,FORMAT_2,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,?,?,?,FORMAT_16,FORMAT_17,FORMAT_18,?,?,?,FORMAT_22,FORMAT_23,FORMAT_24,?,?,?,?,?,?,?,FORMAT_32,FORMAT_33,FORMAT_34,FORMAT_35,?,FORMAT_37,FORMAT_38,FORMAT_39,FORMAT_40,FORMAT_41,FORMAT_42,FORMAT_43,?,?,?,?,FORMAT_48,FORMAT_49,FORMAT_50,?,?,?,?,?,?,?,?,?,?,FORMAT_61,FORMAT_62,FORMAT_63" newline bitfld.long 0x20 0. "ENABLE,Write-back Enable" "ENABLE_0,ENABLE_1" line.long 0x24 "DISPC_WB_ATTRIBUTES2,The register set the WB pipe" rbitfld.long 0x24 31. "RESERVED," "0,1" bitfld.long 0x24 26.--30. "TAGS,Number of OCP TAGS to be used for the pipeline (from 1 to 32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x24 25. "RESERVED," "0,1" bitfld.long 0x24 24. "REGION_BASED,Enable region-based mechanism for WBPipe" "REGION_BASED_0,REGION_BASED_1" newline rbitfld.long 0x24 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x24 17. "RESERVED," "0,1" newline bitfld.long 0x24 16. "SECURE,OCP requests corresponds to pipeline data are secure/unsecure" "0,1" hexmask.long.word 0x24 1.--15. 1. "RESERVED," newline bitfld.long 0x24 0. "FSC,Field Sequential Color generation : R G and B buffers are generated from RGB buffer" "FSC_0,FSC_1" line.long 0x28 "DISPC_WB_BA_j_0,The register configures the base address of the WB buffer (DISPC_WB_BA__0 DISPC_WB_BA__1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_WB_BA__0 is used)" line.long 0x2C "DISPC_WB_BA_j_1,The register configures the base address of the WB buffer (DISPC_WB_BA__0 DISPC_WB_BA__1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_WB_BA__0 is used)" line.long 0x30 "DISPC_WB_BA_UV_j_0,The register configures the base address of the UV buffer for the write-back pipeline" line.long 0x34 "DISPC_WB_BA_UV_j_1,The register configures the base address of the UV buffer for the write-back pipeline" line.long 0x38 "DISPC_WB_BUF_SIZE_STATUS,The register defines the DMA buufer size for the write back pipeline" hexmask.long.word 0x38 16.--31. 1. "RESERVED,Write 0's for future compatibility" hexmask.long.word 0x38 0.--15. 1. "BUFSIZE,DMA buffer Size in number of 128-bits" line.long 0x3C "DISPC_WB_BUF_THRESHOLD,The register configures the DMA buffer associated with the write-back pipeline" hexmask.long.word 0x3C 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer High Threshold Number of 128-bits defining the threshold value" hexmask.long.word 0x3C 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer High Threshold Number of 128-bits defining the threshold value" line.long 0x40 "DISPC_WB_CONV_COEF0,The register configures the color space conversion matrix coefficients for the write back pipeline (YUV444 to RGB24) Shadow register" rbitfld.long 0x40 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x40 16.--26. 1. "YG,YG Coefficient Encoded signed value (from -1024 to 1023)" newline rbitfld.long 0x40 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x40 0.--10. 1. "YR,YR Coefficient Encoded signed value (from -1024 to 1023)" line.long 0x44 "DISPC_WB_CONV_COEF1,The register configures the color space conversion matrix coefficients for the write back pipeline" rbitfld.long 0x44 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x44 16.--26. 1. "CRR,CrR Coefficient Encoded signed value (from -1024 to 1023)" newline rbitfld.long 0x44 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x44 0.--10. 1. "YB,YB Coefficient Encoded signed value (from -1024 to 1023)" line.long 0x48 "DISPC_WB_CONV_COEF2,The register configures the color space conversion matrix coefficients for the write back pipeline" rbitfld.long 0x48 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x48 16.--26. 1. "CRB,CrB Coefficient Encoded signed value (from -1024 to 1023)" newline rbitfld.long 0x48 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x48 0.--10. 1. "CRG,CrG Coefficient Encoded signed value (from -1024 to 1023)" line.long 0x4C "DISPC_WB_CONV_COEF3,The register configures the color space conversion matrix coefficients for the write back pipeline" rbitfld.long 0x4C 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x4C 16.--26. 1. "CBG,CbG coefficient Encoded signed value (from -1024 to 1023)" newline rbitfld.long 0x4C 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x4C 0.--10. 1. "CBR,CbR coefficient Encoded signed value (from -1024 to 1023)" line.long 0x50 "DISPC_WB_CONV_COEF4,The register configures the color space conversion matrix coefficients for the write back pipeline" hexmask.long.tbyte 0x50 11.--31. 1. "RESERVED," hexmask.long.word 0x50 0.--10. 1. "CBB,CbB Coefficient Encoded signed value (from -1024 to 1023)" line.long 0x54 "DISPC_WB_CONV_COEF5,The register configures the color space conversion matrix coefficients for the write-back pipeline" hexmask.long.word 0x54 19.--31. 1. "GOFFSET,G offset Encoded signed value (from -4096 to 4095)" rbitfld.long 0x54 16.--18. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x54 3.--15. 1. "ROFFSET,R offset Encoded signed value (from -4096 to 4095)" rbitfld.long 0x54 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x58 "DISPC_WB_CONV_COEF6,The register configures the color space conversion matrix coefficients for the write-back pipeline" hexmask.long.word 0x58 16.--31. 1. "RESERVED," hexmask.long.word 0x58 3.--15. 1. "BOFFSET,B offset Encoded signed value (from -4096 to 4095)" newline rbitfld.long 0x58 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x5C "DISPC_WB_FIRH,The register configures the resize factor for horizontal up/down-sampling of the write-back window" hexmask.long.byte 0x5C 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x5C 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter" line.long 0x60 "DISPC_WB_FIRH2,The register configures the resize factor for horizontal up/down-sampling of the wirte-back window" hexmask.long.byte 0x60 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x60 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter for Cb and Cr" line.long 0x64 "DISPC_WB_FIRV,The register configures the resize factor for vertical up/down-sampling of the write-back window It is used for ARGB and Y setting" hexmask.long.byte 0x64 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x64 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter" line.long 0x68 "DISPC_WB_FIRV2,The register configures the resize factor for vertical up/down-sampling of the wirte-back window" hexmask.long.byte 0x68 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x68 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter for Cb and Cr" line.long 0x6C "DISPC_WB_FIR_COEF_H0_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x6C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x6C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x6C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x70 "DISPC_WB_FIR_COEF_H0_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x70 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x70 10.--29. 1. "RESERVED," newline hexmask.long.word 0x70 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x74 "DISPC_WB_FIR_COEF_H0_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x74 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x74 10.--29. 1. "RESERVED," newline hexmask.long.word 0x74 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x78 "DISPC_WB_FIR_COEF_H0_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x78 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x78 10.--29. 1. "RESERVED," newline hexmask.long.word 0x78 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x7C "DISPC_WB_FIR_COEF_H0_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x7C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x7C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x7C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x80 "DISPC_WB_FIR_COEF_H0_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x80 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x80 10.--29. 1. "RESERVED," newline hexmask.long.word 0x80 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x84 "DISPC_WB_FIR_COEF_H0_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x84 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x84 10.--29. 1. "RESERVED," newline hexmask.long.word 0x84 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x88 "DISPC_WB_FIR_COEF_H0_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x88 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x88 10.--29. 1. "RESERVED," newline hexmask.long.word 0x88 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x8C "DISPC_WB_FIR_COEF_H0_i_8,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x8C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x8C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x8C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x90 "DISPC_WB_FIR_COEF_H0_C_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x90 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x90 10.--29. 1. "RESERVED," newline hexmask.long.word 0x90 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x94 "DISPC_WB_FIR_COEF_H0_C_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x94 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x94 10.--29. 1. "RESERVED," newline hexmask.long.word 0x94 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x98 "DISPC_WB_FIR_COEF_H0_C_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x98 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x98 10.--29. 1. "RESERVED," newline hexmask.long.word 0x98 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x9C "DISPC_WB_FIR_COEF_H0_C_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x9C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x9C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x9C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xA0 "DISPC_WB_FIR_COEF_H0_C_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xA0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xA0 10.--29. 1. "RESERVED," newline hexmask.long.word 0xA0 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xA4 "DISPC_WB_FIR_COEF_H0_C_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xA4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xA4 10.--29. 1. "RESERVED," newline hexmask.long.word 0xA4 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xA8 "DISPC_WB_FIR_COEF_H0_C_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xA8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xA8 10.--29. 1. "RESERVED," newline hexmask.long.word 0xA8 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xAC "DISPC_WB_FIR_COEF_H0_C_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xAC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xAC 10.--29. 1. "RESERVED," newline hexmask.long.word 0xAC 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xB0 "DISPC_WB_FIR_COEF_H0_C_i_8,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xB0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0xB0 10.--29. 1. "RESERVED," newline hexmask.long.word 0xB0 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0xB4 "DISPC_WB_FIR_COEF_H12_k_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xB4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xB4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xB4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xB4 0.--9. 1. "RESERVED," line.long 0xB8 "DISPC_WB_FIR_COEF_H12_k_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xB8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xB8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xB8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xB8 0.--9. 1. "RESERVED," line.long 0xBC "DISPC_WB_FIR_COEF_H12_k_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xBC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xBC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xBC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xBC 0.--9. 1. "RESERVED," line.long 0xC0 "DISPC_WB_FIR_COEF_H12_k_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xC0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xC0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xC0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xC0 0.--9. 1. "RESERVED," line.long 0xC4 "DISPC_WB_FIR_COEF_H12_k_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xC4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xC4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xC4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xC4 0.--9. 1. "RESERVED," line.long 0xC8 "DISPC_WB_FIR_COEF_H12_k_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xC8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xC8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xC8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xC8 0.--9. 1. "RESERVED," line.long 0xCC "DISPC_WB_FIR_COEF_H12_k_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xCC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xCC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xCC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xCC 0.--9. 1. "RESERVED," line.long 0xD0 "DISPC_WB_FIR_COEF_H12_k_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xD0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xD0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xD0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xD0 0.--9. 1. "RESERVED," line.long 0xD4 "DISPC_WB_FIR_COEF_H12_k_8,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xD4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xD4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xD4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xD4 0.--9. 1. "RESERVED," line.long 0xD8 "DISPC_WB_FIR_COEF_H12_k_9,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xD8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xD8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xD8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xD8 0.--9. 1. "RESERVED," line.long 0xDC "DISPC_WB_FIR_COEF_H12_k_10,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xDC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xDC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xDC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xDC 0.--9. 1. "RESERVED," line.long 0xE0 "DISPC_WB_FIR_COEF_H12_k_11,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xE0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xE0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xE0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xE0 0.--9. 1. "RESERVED," line.long 0xE4 "DISPC_WB_FIR_COEF_H12_k_12,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xE4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xE4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xE4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xE4 0.--9. 1. "RESERVED," line.long 0xE8 "DISPC_WB_FIR_COEF_H12_k_13,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xE8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xE8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xE8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xE8 0.--9. 1. "RESERVED," line.long 0xEC "DISPC_WB_FIR_COEF_H12_k_14,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xEC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xEC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xEC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xEC 0.--9. 1. "RESERVED," line.long 0xF0 "DISPC_WB_FIR_COEF_H12_k_15,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xF0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xF0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xF0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xF0 0.--9. 1. "RESERVED," line.long 0xF4 "DISPC_WB_FIR_COEF_H12_C_k_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xF4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xF4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xF4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xF4 0.--9. 1. "RESERVED," line.long 0xF8 "DISPC_WB_FIR_COEF_H12_C_k_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xF8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xF8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xF8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xF8 0.--9. 1. "RESERVED," line.long 0xFC "DISPC_WB_FIR_COEF_H12_C_k_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0xFC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0xFC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0xFC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0xFC 0.--9. 1. "RESERVED," line.long 0x100 "DISPC_WB_FIR_COEF_H12_C_k_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x100 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x100 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x100 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x100 0.--9. 1. "RESERVED," line.long 0x104 "DISPC_WB_FIR_COEF_H12_C_k_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x104 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x104 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x104 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x104 0.--9. 1. "RESERVED," line.long 0x108 "DISPC_WB_FIR_COEF_H12_C_k_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x108 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x108 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x108 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x108 0.--9. 1. "RESERVED," line.long 0x10C "DISPC_WB_FIR_COEF_H12_C_k_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x10C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x10C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x10C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x10C 0.--9. 1. "RESERVED," line.long 0x110 "DISPC_WB_FIR_COEF_H12_C_k_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x110 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x110 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x110 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x110 0.--9. 1. "RESERVED," line.long 0x114 "DISPC_WB_FIR_COEF_H12_C_k_8,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x114 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x114 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x114 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x114 0.--9. 1. "RESERVED," line.long 0x118 "DISPC_WB_FIR_COEF_H12_C_k_9,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x118 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x118 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x118 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x118 0.--9. 1. "RESERVED," line.long 0x11C "DISPC_WB_FIR_COEF_H12_C_k_10,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x11C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x11C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x11C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x11C 0.--9. 1. "RESERVED," line.long 0x120 "DISPC_WB_FIR_COEF_H12_C_k_11,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x120 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x120 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x120 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x120 0.--9. 1. "RESERVED," line.long 0x124 "DISPC_WB_FIR_COEF_H12_C_k_12,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x124 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x124 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x124 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x124 0.--9. 1. "RESERVED," line.long 0x128 "DISPC_WB_FIR_COEF_H12_C_k_13,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x128 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x128 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x128 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x128 0.--9. 1. "RESERVED," line.long 0x12C "DISPC_WB_FIR_COEF_H12_C_k_14,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x12C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x12C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x12C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x12C 0.--9. 1. "RESERVED," line.long 0x130 "DISPC_WB_FIR_COEF_H12_C_k_15,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x130 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x130 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n" newline hexmask.long.word 0x130 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.word 0x130 0.--9. 1. "RESERVED," line.long 0x134 "DISPC_WB_FIR_COEF_V0_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x134 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x134 10.--29. 1. "RESERVED," newline hexmask.long.word 0x134 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x138 "DISPC_WB_FIR_COEF_V0_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x138 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x138 10.--29. 1. "RESERVED," newline hexmask.long.word 0x138 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x13C "DISPC_WB_FIR_COEF_V0_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x13C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x13C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x13C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x140 "DISPC_WB_FIR_COEF_V0_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x140 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x140 10.--29. 1. "RESERVED," newline hexmask.long.word 0x140 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x144 "DISPC_WB_FIR_COEF_V0_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x144 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x144 10.--29. 1. "RESERVED," newline hexmask.long.word 0x144 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x148 "DISPC_WB_FIR_COEF_V0_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x148 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x148 10.--29. 1. "RESERVED," newline hexmask.long.word 0x148 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x14C "DISPC_WB_FIR_COEF_V0_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x14C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x14C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x14C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x150 "DISPC_WB_FIR_COEF_V0_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x150 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x150 10.--29. 1. "RESERVED," newline hexmask.long.word 0x150 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x154 "DISPC_WB_FIR_COEF_V0_i_8,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x154 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x154 10.--29. 1. "RESERVED," newline hexmask.long.word 0x154 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x158 "DISPC_WB_FIR_COEF_V0_C_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x158 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x158 10.--29. 1. "RESERVED," newline hexmask.long.word 0x158 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x15C "DISPC_WB_FIR_COEF_V0_C_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x15C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x15C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x15C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x160 "DISPC_WB_FIR_COEF_V0_C_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x160 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x160 10.--29. 1. "RESERVED," newline hexmask.long.word 0x160 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x164 "DISPC_WB_FIR_COEF_V0_C_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x164 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x164 10.--29. 1. "RESERVED," newline hexmask.long.word 0x164 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x168 "DISPC_WB_FIR_COEF_V0_C_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x168 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x168 10.--29. 1. "RESERVED," newline hexmask.long.word 0x168 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x16C "DISPC_WB_FIR_COEF_V0_C_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x16C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x16C 10.--29. 1. "RESERVED," newline hexmask.long.word 0x16C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x170 "DISPC_WB_FIR_COEF_V0_C_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x170 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x170 10.--29. 1. "RESERVED," newline hexmask.long.word 0x170 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x174 "DISPC_WB_FIR_COEF_V0_C_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x174 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x174 10.--29. 1. "RESERVED," newline hexmask.long.word 0x174 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x178 "DISPC_WB_FIR_COEF_V0_C_i_8,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x178 30.--31. "RESERVED," "0,1,2,3" hexmask.long.tbyte 0x178 10.--29. 1. "RESERVED," newline hexmask.long.word 0x178 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n" line.long 0x17C "DISPC_WB_FIR_COEF_V12_k_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x17C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x17C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x17C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x17C 0.--9. 1. "RESERVED," line.long 0x180 "DISPC_WB_FIR_COEF_V12_k_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x180 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x180 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x180 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x180 0.--9. 1. "RESERVED," line.long 0x184 "DISPC_WB_FIR_COEF_V12_k_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x184 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x184 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x184 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x184 0.--9. 1. "RESERVED," line.long 0x188 "DISPC_WB_FIR_COEF_V12_k_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x188 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x188 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x188 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x188 0.--9. 1. "RESERVED," line.long 0x18C "DISPC_WB_FIR_COEF_V12_k_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x18C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x18C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x18C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x18C 0.--9. 1. "RESERVED," line.long 0x190 "DISPC_WB_FIR_COEF_V12_k_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x190 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x190 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x190 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x190 0.--9. 1. "RESERVED," line.long 0x194 "DISPC_WB_FIR_COEF_V12_k_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x194 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x194 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x194 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x194 0.--9. 1. "RESERVED," line.long 0x198 "DISPC_WB_FIR_COEF_V12_k_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x198 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x198 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x198 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x198 0.--9. 1. "RESERVED," line.long 0x19C "DISPC_WB_FIR_COEF_V12_k_8,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x19C 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x19C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x19C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x19C 0.--9. 1. "RESERVED," line.long 0x1A0 "DISPC_WB_FIR_COEF_V12_k_9,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1A0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1A0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1A0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1A0 0.--9. 1. "RESERVED," line.long 0x1A4 "DISPC_WB_FIR_COEF_V12_k_10,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1A4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1A4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1A4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1A4 0.--9. 1. "RESERVED," line.long 0x1A8 "DISPC_WB_FIR_COEF_V12_k_11,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1A8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1A8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1A8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1A8 0.--9. 1. "RESERVED," line.long 0x1AC "DISPC_WB_FIR_COEF_V12_k_12,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1AC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1AC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1AC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1AC 0.--9. 1. "RESERVED," line.long 0x1B0 "DISPC_WB_FIR_COEF_V12_k_13,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1B0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1B0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1B0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1B0 0.--9. 1. "RESERVED," line.long 0x1B4 "DISPC_WB_FIR_COEF_V12_k_14,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1B4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1B4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1B4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1B4 0.--9. 1. "RESERVED," line.long 0x1B8 "DISPC_WB_FIR_COEF_V12_k_15,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1B8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1B8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1B8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1B8 0.--9. 1. "RESERVED," line.long 0x1BC "DISPC_WB_FIR_COEF_V12_C_k_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1BC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1BC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1BC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1BC 0.--9. 1. "RESERVED," line.long 0x1C0 "DISPC_WB_FIR_COEF_V12_C_k_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1C0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1C0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1C0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1C0 0.--9. 1. "RESERVED," line.long 0x1C4 "DISPC_WB_FIR_COEF_V12_C_k_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1C4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1C4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1C4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1C4 0.--9. 1. "RESERVED," line.long 0x1C8 "DISPC_WB_FIR_COEF_V12_C_k_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1C8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1C8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1C8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1C8 0.--9. 1. "RESERVED," line.long 0x1CC "DISPC_WB_FIR_COEF_V12_C_k_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1CC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1CC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1CC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1CC 0.--9. 1. "RESERVED," line.long 0x1D0 "DISPC_WB_FIR_COEF_V12_C_k_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1D0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1D0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1D0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1D0 0.--9. 1. "RESERVED," line.long 0x1D4 "DISPC_WB_FIR_COEF_V12_C_k_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1D4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1D4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1D4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1D4 0.--9. 1. "RESERVED," line.long 0x1D8 "DISPC_WB_FIR_COEF_V12_C_k_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1D8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1D8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1D8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1D8 0.--9. 1. "RESERVED," line.long 0x1DC "DISPC_WB_FIR_COEF_V12_C_k_8,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1DC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1DC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1DC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1DC 0.--9. 1. "RESERVED," line.long 0x1E0 "DISPC_WB_FIR_COEF_V12_C_k_9,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1E0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1E0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1E0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1E0 0.--9. 1. "RESERVED," line.long 0x1E4 "DISPC_WB_FIR_COEF_V12_C_k_10,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1E4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1E4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1E4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1E4 0.--9. 1. "RESERVED," line.long 0x1E8 "DISPC_WB_FIR_COEF_V12_C_k_11,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1E8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1E8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1E8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1E8 0.--9. 1. "RESERVED," line.long 0x1EC "DISPC_WB_FIR_COEF_V12_C_k_12,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1EC 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1EC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1EC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1EC 0.--9. 1. "RESERVED," line.long 0x1F0 "DISPC_WB_FIR_COEF_V12_C_k_13,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1F0 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1F0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1F0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1F0 0.--9. 1. "RESERVED," line.long 0x1F4 "DISPC_WB_FIR_COEF_V12_C_k_14,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1F4 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1F4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1F4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1F4 0.--9. 1. "RESERVED," line.long 0x1F8 "DISPC_WB_FIR_COEF_V12_C_k_15,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15" rbitfld.long 0x1F8 30.--31. "RESERVED," "0,1,2,3" hexmask.long.word 0x1F8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" newline hexmask.long.word 0x1F8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.word 0x1F8 0.--9. 1. "RESERVED," line.long 0x1FC "DISPC_WB_IRQENABLE,This register allows to mask/unmask the module internal sources of interrupt. on an event-by-event basis" hexmask.long 0x1FC 5.--31. 1. "RESERVED," bitfld.long 0x1FC 4. "WBSYNC_EN,Write-back synced (configuration copied from shadow to work)" "WBSYNC_EN_0,WBSYNC_EN_1" newline bitfld.long 0x1FC 3. "WBREGIONBASEDEVENT_EN,For Write-back region-based event indicating end of current window" "WBREGIONBASEDEVENT_EN_0,WBREGIONBASEDEVENT_EN_1" bitfld.long 0x1FC 2. "WBFRAMEDONE_EN,Write-back Frame Done" "WBFRAMEDONE_EN_0,WBFRAMEDONE_EN_1" newline bitfld.long 0x1FC 1. "WBUNCOMPLETEERROR_EN,The write back buffer has been flushed before been fully drained" "WBUNCOMPLETEERROR_EN_0,WBUNCOMPLETEERROR_EN_1" bitfld.long 0x1FC 0. "WBBUFFEROVERFLOW_EN,Write-back DMA Buffer Overflow" "WBBUFFEROVERFLOW_EN_0,WBBUFFEROVERFLOW_EN_1" line.long 0x200 "DISPC_WB_IRQSTATUS,This register regroups all the status of the module internal events that generate an interrupt" hexmask.long 0x200 5.--31. 1. "RESERVED," bitfld.long 0x200 4. "WBSYNC_IRQ,Write-back synced (configuration copied from shadow to work)" "WBSYNC_IRQ_0,WBSYNC_IRQ_1" newline bitfld.long 0x200 3. "WBREGIONBASEDEVENT_IRQ,Write-back Frame Done" "WBREGIONBASEDEVENT_IRQ_0,WBREGIONBASEDEVENT_IRQ_1" bitfld.long 0x200 2. "WBFRAMEDONE_IRQ,Write-back Frame Done" "WBFRAMEDONE_IRQ_0,WBFRAMEDONE_IRQ_1" newline bitfld.long 0x200 1. "WBUNCOMPLETEERROR_IRQ,Write back DMA buffer is flushed before been completely drained" "WBUNCOMPLETEERROR_IRQ_0,WBUNCOMPLETEERROR_IRQ_1" bitfld.long 0x200 0. "WBBUFFEROVERFLOW_IRQ,Write-back DMA Buffer Overrflow" "WBBUFFEROVERFLOW_IRQ_0,WBBUFFEROVERFLOW_IRQ_1" line.long 0x204 "DISPC_WB_MFLAG_THRESHOLD," hexmask.long.word 0x204 16.--31. 1. "HT_MFLAG," hexmask.long.word 0x204 0.--15. 1. "LT_MFLAG," line.long 0x208 "DISPC_WB_PICTURE_SIZE,The register configures the size of the write-back picture associated with the write back pipeline after up/down-scaling (size of the image stored in DDR memory. generated by WB pipe)" rbitfld.long 0x208 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x208 16.--27. 1. "MEMSIZEY,Number of lines of the wb picture in memory Encoded value (from 1 to 4096) to specify the number of lines of the picture store in memory (program to value minus one)" newline rbitfld.long 0x208 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x208 0.--11. 1. "MEMSIZEX,Number of pixels of the wb picture in memory" group.long 0x210++0x0B line.long 0x00 "DISPC_WB_SIZE,The register configures the size of the output of overlay connected to the write-back pipeline when the overlay output is only used by the write-back pipeline" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 16.--27. 1. "SIZEY,Number of lines of the Write-back picture Encoded value (from 1 to 4096) to specify the number of lines of the write-back picture from overlay or pipeline" newline rbitfld.long 0x00 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. "SIZEX,Number of pixels of the Write-back picture Encoded value (from 1 to 4096) to specify the number of pixels of the write-back picture from overlay or pipeline" line.long 0x04 "DISPC_WB_POSITION,The register configures the start position of the window on overlay which wb will capture Shadow register" rbitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 16.--27. 1. "POSY,Y position of the video window Encoded value (from 0 to 4095) to specify the Y position of the video window #1 .The line at the top has the Y-position 0" newline rbitfld.long 0x04 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. "POSX,X position of the video window Encoded value (from 0 to 4095) to specify the X position of the video window #1" line.long 0x08 "DISPC_WB_REGION_BASED_TOTAL_PICTURE_SIZEY,The register configures the total sizey (total number of lines) of all the windows written back to the memory in Write-Back Region-based mode" hexmask.long.tbyte 0x08 12.--31. 1. "RESERVED," hexmask.long.word 0x08 0.--11. 1. "SIZEY,Total number of lines of the Write-back picture in Region-based mode Encoded value (from 1 to 4096) to specify the number of lines of the write-back picture from overlay or pipeline" width 0x0B tree.end tree "DRM" base ad:0x54160000 group.long 0x280++0x03 line.long 0x00 "DRM_SUSPEND_CTRL32," hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4.--8. "SUSPEND_SEL,Suspend signal selection.Selects which suspend signal affects the peripheral" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 3. "SUSPEND_DEFAULT_OVERRIDE,Enable or disable the override value in SUSPEND_SEL.0: SUSPEND_SEL field will select which suspend signal reaches the peripheral.1: SUSPEND_SEL field ignored.Default suspend signal will reach the peripheral" "0,1" newline rbitfld.long 0x00 1.--2. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x00 0. "SENSCTRL,Sensitivity Control for suspend signals.When SUSPEND_DEFAULT_OVERRIDE=1 this bit is ignored and read as a 1" "Suspend signal will not reach the peripheral,Suspend signal will reach the peripheral" repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x240)++0x03 line.long 0x00 "DRM_SUSPEND_CTRL$1," hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4.--8. "SUSPEND_SEL,Suspend signal selection.Selects which suspend signal affects the peripheral" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 3. "SUSPEND_DEFAULT_OVERRIDE,Enable or disable the override value in SUSPEND_SEL.0: SUSPEND_SEL field will select which suspend signal reaches the peripheral.1: SUSPEND_SEL field ignored.Default suspend signal will reach the peripheral" "0,1" rbitfld.long 0x00 1.--2. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 0. "SENSCTRL,Sensitivity Control for suspend signals.When SUSPEND_DEFAULT_OVERRIDE=1 this bit is ignored and read as a 1" "Suspend signal will not reach the peripheral,Suspend signal will reach the peripheral" repeat.end repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x200)++0x03 line.long 0x00 "DRM_SUSPEND_CTRL$1," hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4.--8. "SUSPEND_SEL,Suspend signal selection.Selects which suspend signal affects the peripheral" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 3. "SUSPEND_DEFAULT_OVERRIDE,Enable or disable the override value in SUSPEND_SEL.0: SUSPEND_SEL field will select which suspend signal reaches the peripheral.1: SUSPEND_SEL field ignored.Default suspend signal will reach the peripheral" "0,1" rbitfld.long 0x00 1.--2. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 0. "SENSCTRL,Sensitivity Control for suspend signals.When SUSPEND_DEFAULT_OVERRIDE=1 this bit is ignored and read as a 1" "Suspend signal will not reach the peripheral,Suspend signal will reach the peripheral" repeat.end width 0x0B tree.end tree "DSP1_CM_CORE_AON" base ad:0x4A005400 group.long 0x00++0x0B line.long 0x00 "CM_DSP1_CLKSTCTRL,This register enables the DSP domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_DSP1_GFCLK,This field indicates the state of the DSP_ROOT_CLK clock in the domain" "CLKACTIVITY_DSP1_GFCLK_0,CLKACTIVITY_DSP1_GFCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_DSP1_STATICDEP,This register controls the static domain depedencies from DSP domain towards 'target' domains" rbitfld.long 0x04 31. "RESERVED," "0,1" bitfld.long 0x04 30. "CRC_STATDEP,Static dependency towards L3INIT clock domain" "CRC_STATDEP_0,CRC_STATDEP_1" newline bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE cLOCK dOMAIN" "PCIE_STATDEP_0,PCIE_STATDEP_1" bitfld.long 0x04 28. "ISS_STATDEP,Static dependency towards ISS Clock Domain" "ISS_STATDEP_0,ISS_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 Clock Domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 Clock Domain" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC Clock Domain" "GMAC_STATDEP_0,GMAC_STATDEP_1" bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPUClock Domain" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain" "IPU1_STATDEP_0,IPU1_STATDEP_1" bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 Clock Domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" newline bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 Clock Domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2CLOCK dOMAIN" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 CLOCK dOMAIN" "EVE1_STATDEP_0,EVE1_STATDEP_1" bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain" "CUSTEFUSE_STATDEP_0,?" rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC Clock Domain" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" rbitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,?" newline rbitfld.long 0x04 11. "RESERVED," "0,1" bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU Clock Domain" "GPU_STATDEP_0,GPU_STATDEP_1" newline bitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain" "CAM_STATDEP_0,CAM_STATDEP_1" bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" rbitfld.long 0x04 6. "RESERVED," "0,1" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 3. "RESERVED," "0,1" bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline rbitfld.long 0x04 1. "RESERVED," "0,1" bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_DSP1_DYNAMICDEP,This register controls the dynamic domain depedencies from DSP domain towards 'target' domains" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.tbyte 0x08 6.--23. 1. "RESERVED," rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20++0x03 line.long 0x00 "CM_DSP1_DSP1_CLKCTRL,This register manages the DSP clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "DSP1_EDMA_TPCC" base ad:0x40D10000 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x04 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x04 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" newline rbitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x04 22.--23. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x04 19. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x04 15. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x04 11. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7" group.long 0xFC++0x113 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" line.long 0x04 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x04 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x08 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x08 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x0C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x10 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x14 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x18 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x1C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" hexmask.long.tbyte 0x20 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x20 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" hexmask.long.tbyte 0x24 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x24 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" hexmask.long.tbyte 0x28 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x28 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x28 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x2C "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.tbyte 0x2C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x2C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x2C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" hexmask.long.tbyte 0x30 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x30 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x30 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" hexmask.long.tbyte 0x34 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x34 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x34 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x38 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" hexmask.long.tbyte 0x38 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x38 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x38 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x3C "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" hexmask.long.tbyte 0x3C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x3C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x3C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" hexmask.long.tbyte 0x40 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x40 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x40 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x44 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" hexmask.long.tbyte 0x44 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x44 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x44 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x48 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" hexmask.long.tbyte 0x48 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x48 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x48 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x4C "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" hexmask.long.tbyte 0x4C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x4C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" hexmask.long.tbyte 0x50 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x50 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x50 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x54 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" hexmask.long.tbyte 0x54 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x54 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x54 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x58 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" hexmask.long.tbyte 0x58 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x58 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x58 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x5C "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" hexmask.long.tbyte 0x5C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x5C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x5C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x60 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" hexmask.long.tbyte 0x60 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x60 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x60 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x64 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" hexmask.long.tbyte 0x64 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x64 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x64 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x68 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" hexmask.long.tbyte 0x68 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x68 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x68 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x6C "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" hexmask.long.tbyte 0x6C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x6C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x6C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x70 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" hexmask.long.tbyte 0x70 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x70 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x70 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x74 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" hexmask.long.tbyte 0x74 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x74 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x74 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x78 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" hexmask.long.tbyte 0x78 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x78 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x78 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x7C "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" hexmask.long.tbyte 0x7C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x7C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x7C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x80 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" hexmask.long.tbyte 0x80 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x80 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x80 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x84 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" hexmask.long.tbyte 0x84 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x84 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x84 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x88 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" hexmask.long.tbyte 0x88 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x88 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x88 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x8C "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" hexmask.long.tbyte 0x8C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x8C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x8C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x90 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" hexmask.long.tbyte 0x90 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x90 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x90 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x94 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" hexmask.long.tbyte 0x94 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x94 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x94 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x98 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" hexmask.long.tbyte 0x98 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x98 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x98 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x9C "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" hexmask.long.tbyte 0x9C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x9C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x9C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA0 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA4 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA8 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xAC "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" hexmask.long.tbyte 0xAC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xAC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xAC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB0 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB4 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB8 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xBC "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" hexmask.long.tbyte 0xBC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xBC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xBC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC0 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC4 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC8 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xCC "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" hexmask.long.tbyte 0xCC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xCC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xCC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD0 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD4 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD8 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xDC "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" hexmask.long.tbyte 0xDC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xDC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xDC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE0 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE4 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE8 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xEC "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" hexmask.long.tbyte 0xEC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xEC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xEC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF0 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF4 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF8 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xFC "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" hexmask.long.tbyte 0xFC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xFC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xFC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x100 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" hexmask.long.tbyte 0x100 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x100 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x100 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x104 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x104 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x104 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x104 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x104 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x108 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x108 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x108 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x108 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x108 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x10C "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x10C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10C 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x10C 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x10C 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x110 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x110 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x110 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x110 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x110 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x240++0x23 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x00 31. "RESERVED,Reserved" "0,1" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 27. "RESERVED,Reserved" "0,1" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 23. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Reserved" "0,1" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 15. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x04 31. "RESERVED,Reserved" "0,1" bitfld.long 0x04 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 27. "RESERVED,Reserved" "0,1" bitfld.long 0x04 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 23. "RESERVED,Reserved" "0,1" bitfld.long 0x04 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED,Reserved" "0,1" bitfld.long 0x04 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 15. "RESERVED,Reserved" "0,1" bitfld.long 0x04 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 11. "RESERVED,Reserved" "0,1" bitfld.long 0x04 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED,Reserved" "0,1" bitfld.long 0x04 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x08 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x08 31. "RESERVED,Reserved" "0,1" bitfld.long 0x08 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 27. "RESERVED,Reserved" "0,1" bitfld.long 0x08 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 23. "RESERVED,Reserved" "0,1" bitfld.long 0x08 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED,Reserved" "0,1" bitfld.long 0x08 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 15. "RESERVED,Reserved" "0,1" bitfld.long 0x08 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 11. "RESERVED,Reserved" "0,1" bitfld.long 0x08 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED,Reserved" "0,1" bitfld.long 0x08 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x0C "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x0C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x10 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x10 31. "RESERVED,Reserved" "0,1" bitfld.long 0x10 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED,Reserved" "0,1" bitfld.long 0x10 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED,Reserved" "0,1" bitfld.long 0x10 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "RESERVED,Reserved" "0,1" bitfld.long 0x10 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 15. "RESERVED,Reserved" "0,1" bitfld.long 0x10 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 11. "RESERVED,Reserved" "0,1" bitfld.long 0x10 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" bitfld.long 0x10 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 3. "RESERVED,Reserved" "0,1" bitfld.long 0x10 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x14 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x14 31. "RESERVED,Reserved" "0,1" bitfld.long 0x14 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED,Reserved" "0,1" bitfld.long 0x14 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED,Reserved" "0,1" bitfld.long 0x14 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED,Reserved" "0,1" bitfld.long 0x14 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED,Reserved" "0,1" bitfld.long 0x14 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" bitfld.long 0x14 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED,Reserved" "0,1" bitfld.long 0x14 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x18 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x18 31. "RESERVED,Reserved" "0,1" bitfld.long 0x18 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED,Reserved" "0,1" bitfld.long 0x18 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED,Reserved" "0,1" bitfld.long 0x18 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED,Reserved" "0,1" bitfld.long 0x18 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED,Reserved" "0,1" bitfld.long 0x18 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED,Reserved" "0,1" bitfld.long 0x18 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED,Reserved" "0,1" bitfld.long 0x18 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED,Reserved" "0,1" bitfld.long 0x18 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x1C "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x1C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x20 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" rbitfld.long 0x20 31. "RESERVED," "0,1" bitfld.long 0x20 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 27. "RESERVED," "0,1" bitfld.long 0x20 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 23. "RESERVED," "0,1" bitfld.long 0x20 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 19. "RESERVED," "0,1" bitfld.long 0x20 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 15. "RESERVED," "0,1" bitfld.long 0x20 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 11. "RESERVED," "0,1" bitfld.long 0x20 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 7. "RESERVED," "0,1" bitfld.long 0x20 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 3. "RESERVED," "0,1" bitfld.long 0x20 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x280++0x07 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_QUEPRI,Queue Priority" hexmask.long 0x04 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" rgroup.long 0x300++0x23 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" newline bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" newline bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" newline bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" newline bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" newline bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" newline bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" newline bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" newline bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" newline bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" newline bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" newline bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" newline bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" newline bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" newline bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" newline bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" newline bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" newline bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" newline bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" newline bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" newline bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" line.long 0x08 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1" newline bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1" bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1" newline bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1" newline bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1" bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1" newline bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1" newline bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1" bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1" newline bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1" newline bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1" bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1" newline bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1" newline bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1" bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1" newline bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1" line.long 0x0C "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1" bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1" bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1" bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1" bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1" bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1" line.long 0x10 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,Event Missed #7" "0,1" newline bitfld.long 0x10 6. "E6,Event Missed #6" "0,1" bitfld.long 0x10 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x10 4. "E4,Event Missed #4" "0,1" bitfld.long 0x10 3. "E3,Event Missed #3" "0,1" newline bitfld.long 0x10 2. "E2,Event Missed #2" "0,1" bitfld.long 0x10 1. "E1,Event Missed #1" "0,1" newline bitfld.long 0x10 0. "E0,Event Missed #0" "0,1" line.long 0x14 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1" newline bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1" newline bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1" bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1" newline bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1" line.long 0x18 "EDMA_TPCC_CCERR,CC Error Register" hexmask.long.word 0x18 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 16. "TCERR,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register" "TCERR_0,TCERR_1" newline hexmask.long.byte 0x18 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD7_0,QTHRXCD7_1" newline bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD6_0,QTHRXCD6_1" bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD5_0,QTHRXCD5_1" newline bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD4_0,QTHRXCD4_1" bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD3_0,QTHRXCD3_1" newline bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD1_0,QTHRXCD1_1" newline bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x1C "EDMA_TPCC_CCERRCLR,CC Error Clear Register" hexmask.long.word 0x1C 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR" "0,1" newline hexmask.long.byte 0x1C 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect" "0,1" bitfld.long 0x1C 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect" "0,1" bitfld.long 0x1C 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" newline bitfld.long 0x1C 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect" "0,1" bitfld.long 0x1C 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" newline bitfld.long 0x1C 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect" "0,1" line.long 0x20 "EDMA_TPCC_EEVAL,Error Eval Register" hexmask.long 0x20 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 1. "SET,Error Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x20 0. "EVAL,Error Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x348++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x350++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x358++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x360++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x368++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x370++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x378++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x344++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x34C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x354++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x35C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x364++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x36C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x374++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x37C++0x23 line.long 0x00 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" line.long 0x04 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x04 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x04 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x04 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x04 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x04 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x04 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x04 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x08 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x08 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x08 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x08 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x08 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x08 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x08 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x08 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x0C "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x0C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x0C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x0C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x0C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x0C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x0C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x0C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x10 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x10 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x10 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x10 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x10 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x10 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x10 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x10 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x14 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x14 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x14 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x14 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x14 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x14 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x14 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x14 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x18 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x18 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x18 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x18 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x18 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x18 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x18 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x18 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x1C "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x1C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x1C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x1C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x1C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x1C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x1C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x1C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x20 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x20 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x20 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x20 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x20 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x20 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x20 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x20 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" rgroup.long 0x400++0x7F line.long 0x00 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x04 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x08 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x10 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x14 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x18 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x1C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x20 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x24 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x28 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x2C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x30 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x30 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x30 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x34 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x34 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x38 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x38 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x3C "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x3C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x40 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x40 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x44 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x44 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x44 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x48 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x48 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x48 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x4C "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x4C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x4C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x50 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x50 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x50 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x54 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x54 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x54 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x54 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x58 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x58 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x58 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x58 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x5C "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x5C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x5C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x5C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x60 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x60 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x60 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x60 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x64 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x64 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x64 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x64 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x68 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x68 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x68 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x68 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x6C "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x6C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x6C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x6C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x70 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x70 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x70 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x70 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x74 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x74 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x74 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x74 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x78 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x78 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x78 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x78 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x7C "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x7C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x7C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x7C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x600++0x07 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" line.long 0x04 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" hexmask.long.byte 0x04 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" rbitfld.long 0x00 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" rbitfld.long 0x04 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,reads return 0's" rbitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" newline rbitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" rbitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" newline rbitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" rbitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" newline bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2" rbitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" newline rbitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 14.--15. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" rbitfld.long 0x00 5.--7. "RESERVED,reads return 0's" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" rbitfld.long 0x00 3. "RESERVED,reads return 0's" "0,1" newline bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.." rbitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" newline rbitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" group.long 0x700++0x0B line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" hexmask.long.tbyte 0x00 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" line.long 0x08 "EDMA_TPCC_AETCMD,AET Command" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "CLR,AET Clear commandCPU writes 0x0 has no effect" "0,1" rgroup.long 0x800++0x2F line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" line.long 0x04 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" newline rbitfld.long 0x04 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" rbitfld.long 0x04 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" newline rbitfld.long 0x04 2. "URE,User Read Error" "URE_0,URE_1" rbitfld.long 0x04 1. "UWE,User Write Error" "UWE_0,UWE_1" newline rbitfld.long 0x04 0. "UXE,User Execute Error" "UXE_0,UXE_1" line.long 0x08 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" line.long 0x0C "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x0C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x0C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x0C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x0C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x0C 10. "AID0,Allowed ID 0" "AID0_0,AID0_1" bitfld.long 0x0C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x0C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x0C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x0C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x0C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x0C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x0C 0. "UX,User Execute permission" "UX_0,UX_1" line.long 0x10 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x10 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x10 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x10 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x10 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x10 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x10 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x10 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x10 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x10 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x10 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x10 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x10 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x10 0. "UX,User Execute permission" "UX_0,?" line.long 0x14 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x14 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x14 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x14 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x14 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x14 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x14 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x14 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x14 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x14 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x14 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x14 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x14 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x14 0. "UX,User Execute permission" "UX_0,?" line.long 0x18 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x18 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x18 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x18 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x18 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x18 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x18 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x18 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x18 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x18 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x18 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x18 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x18 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x18 0. "UX,User Execute permission" "UX_0,?" line.long 0x1C "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x1C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x1C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x1C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x1C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x1C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x1C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x1C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x1C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x1C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x1C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x1C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x1C 0. "UX,User Execute permission" "UX_0,?" line.long 0x20 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x20 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x20 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x20 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x20 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x20 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x20 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x20 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x20 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x20 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x20 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x20 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x20 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x20 0. "UX,User Execute permission" "UX_0,?" line.long 0x24 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x24 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x24 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x24 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x24 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x24 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x24 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x24 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x24 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x24 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x24 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x24 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x24 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x24 0. "UX,User Execute permission" "UX_0,?" line.long 0x28 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" hexmask.long.word 0x28 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x28 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x28 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x28 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x28 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x28 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x28 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x28 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x28 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x28 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x28 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x28 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x28 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x28 0. "UX,User Execute permission" "UX_0,?" line.long 0x2C "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" hexmask.long.word 0x2C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x2C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x2C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x2C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x2C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x2C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x2C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x2C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x2C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x2C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x2C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x2C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x2C 0. "UX,User Execute permission" "UX_0,?" rgroup.long 0x1000++0x47 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" newline bitfld.long 0x04 29. "E61,Event #61" "0,1" bitfld.long 0x04 28. "E60,Event #60" "0,1" newline bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" newline bitfld.long 0x04 23. "E55,Event #55" "0,1" bitfld.long 0x04 22. "E54,Event #54" "0,1" newline bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" newline bitfld.long 0x04 17. "E49,Event #49" "0,1" bitfld.long 0x04 16. "E48,Event #48" "0,1" newline bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" newline bitfld.long 0x04 11. "E43,Event #43" "0,1" bitfld.long 0x04 10. "E42,Event #42" "0,1" newline bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" newline bitfld.long 0x04 5. "E37,Event #37" "0,1" bitfld.long 0x04 4. "E36,Event #36" "0,1" newline bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" line.long 0x08 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event #31" "0,1" bitfld.long 0x08 30. "E30,Event #30" "0,1" newline bitfld.long 0x08 29. "E29,Event #29" "0,1" bitfld.long 0x08 28. "E28,Event #28" "0,1" newline bitfld.long 0x08 27. "E27,Event #27" "0,1" bitfld.long 0x08 26. "E26,Event #26" "0,1" newline bitfld.long 0x08 25. "E25,Event #25" "0,1" bitfld.long 0x08 24. "E24,Event #24" "0,1" newline bitfld.long 0x08 23. "E23,Event #23" "0,1" bitfld.long 0x08 22. "E22,Event #22" "0,1" newline bitfld.long 0x08 21. "E21,Event #21" "0,1" bitfld.long 0x08 20. "E20,Event #20" "0,1" newline bitfld.long 0x08 19. "E19,Event #19" "0,1" bitfld.long 0x08 18. "E18,Event #18" "0,1" newline bitfld.long 0x08 17. "E17,Event #17" "0,1" bitfld.long 0x08 16. "E16,Event #16" "0,1" newline bitfld.long 0x08 15. "E15,Event #15" "0,1" bitfld.long 0x08 14. "E14,Event #14" "0,1" newline bitfld.long 0x08 13. "E13,Event #13" "0,1" bitfld.long 0x08 12. "E12,Event #12" "0,1" newline bitfld.long 0x08 11. "E11,Event #11" "0,1" bitfld.long 0x08 10. "E10,Event #10" "0,1" newline bitfld.long 0x08 9. "E9,Event #9" "0,1" bitfld.long 0x08 8. "E8,Event #8" "0,1" newline bitfld.long 0x08 7. "E7,Event #7" "0,1" bitfld.long 0x08 6. "E6,Event #6" "0,1" newline bitfld.long 0x08 5. "E5,Event #5" "0,1" bitfld.long 0x08 4. "E4,Event #4" "0,1" newline bitfld.long 0x08 3. "E3,Event #3" "0,1" bitfld.long 0x08 2. "E2,Event #2" "0,1" newline bitfld.long 0x08 1. "E1,Event #1" "0,1" bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event #63" "0,1" bitfld.long 0x0C 30. "E62,Event #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event #61" "0,1" bitfld.long 0x0C 28. "E60,Event #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event #59" "0,1" bitfld.long 0x0C 26. "E58,Event #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event #57" "0,1" bitfld.long 0x0C 24. "E56,Event #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event #55" "0,1" bitfld.long 0x0C 22. "E54,Event #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event #53" "0,1" bitfld.long 0x0C 20. "E52,Event #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event #51" "0,1" bitfld.long 0x0C 18. "E50,Event #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event #49" "0,1" bitfld.long 0x0C 16. "E48,Event #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event #47" "0,1" bitfld.long 0x0C 14. "E46,Event #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event #45" "0,1" bitfld.long 0x0C 12. "E44,Event #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event #43" "0,1" bitfld.long 0x0C 10. "E42,Event #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event #41" "0,1" bitfld.long 0x0C 8. "E40,Event #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event #39" "0,1" bitfld.long 0x0C 6. "E38,Event #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event #37" "0,1" bitfld.long 0x0C 4. "E36,Event #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event #35" "0,1" bitfld.long 0x0C 2. "E34,Event #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event #33" "0,1" bitfld.long 0x0C 0. "E32,Event #32" "0,1" line.long 0x10 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x10 31. "E31,Event #31" "0,1" bitfld.long 0x10 30. "E30,Event #30" "0,1" newline bitfld.long 0x10 29. "E29,Event #29" "0,1" bitfld.long 0x10 28. "E28,Event #28" "0,1" newline bitfld.long 0x10 27. "E27,Event #27" "0,1" bitfld.long 0x10 26. "E26,Event #26" "0,1" newline bitfld.long 0x10 25. "E25,Event #25" "0,1" bitfld.long 0x10 24. "E24,Event #24" "0,1" newline bitfld.long 0x10 23. "E23,Event #23" "0,1" bitfld.long 0x10 22. "E22,Event #22" "0,1" newline bitfld.long 0x10 21. "E21,Event #21" "0,1" bitfld.long 0x10 20. "E20,Event #20" "0,1" newline bitfld.long 0x10 19. "E19,Event #19" "0,1" bitfld.long 0x10 18. "E18,Event #18" "0,1" newline bitfld.long 0x10 17. "E17,Event #17" "0,1" bitfld.long 0x10 16. "E16,Event #16" "0,1" newline bitfld.long 0x10 15. "E15,Event #15" "0,1" bitfld.long 0x10 14. "E14,Event #14" "0,1" newline bitfld.long 0x10 13. "E13,Event #13" "0,1" bitfld.long 0x10 12. "E12,Event #12" "0,1" newline bitfld.long 0x10 11. "E11,Event #11" "0,1" bitfld.long 0x10 10. "E10,Event #10" "0,1" newline bitfld.long 0x10 9. "E9,Event #9" "0,1" bitfld.long 0x10 8. "E8,Event #8" "0,1" newline bitfld.long 0x10 7. "E7,Event #7" "0,1" bitfld.long 0x10 6. "E6,Event #6" "0,1" newline bitfld.long 0x10 5. "E5,Event #5" "0,1" bitfld.long 0x10 4. "E4,Event #4" "0,1" newline bitfld.long 0x10 3. "E3,Event #3" "0,1" bitfld.long 0x10 2. "E2,Event #2" "0,1" newline bitfld.long 0x10 1. "E1,Event #1" "0,1" bitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x14 31. "E63,Event #63" "0,1" bitfld.long 0x14 30. "E62,Event #62" "0,1" newline bitfld.long 0x14 29. "E61,Event #61" "0,1" bitfld.long 0x14 28. "E60,Event #60" "0,1" newline bitfld.long 0x14 27. "E59,Event #59" "0,1" bitfld.long 0x14 26. "E58,Event #58" "0,1" newline bitfld.long 0x14 25. "E57,Event #57" "0,1" bitfld.long 0x14 24. "E56,Event #56" "0,1" newline bitfld.long 0x14 23. "E55,Event #55" "0,1" bitfld.long 0x14 22. "E54,Event #54" "0,1" newline bitfld.long 0x14 21. "E53,Event #53" "0,1" bitfld.long 0x14 20. "E52,Event #52" "0,1" newline bitfld.long 0x14 19. "E51,Event #51" "0,1" bitfld.long 0x14 18. "E50,Event #50" "0,1" newline bitfld.long 0x14 17. "E49,Event #49" "0,1" bitfld.long 0x14 16. "E48,Event #48" "0,1" newline bitfld.long 0x14 15. "E47,Event #47" "0,1" bitfld.long 0x14 14. "E46,Event #46" "0,1" newline bitfld.long 0x14 13. "E45,Event #45" "0,1" bitfld.long 0x14 12. "E44,Event #44" "0,1" newline bitfld.long 0x14 11. "E43,Event #43" "0,1" bitfld.long 0x14 10. "E42,Event #42" "0,1" newline bitfld.long 0x14 9. "E41,Event #41" "0,1" bitfld.long 0x14 8. "E40,Event #40" "0,1" newline bitfld.long 0x14 7. "E39,Event #39" "0,1" bitfld.long 0x14 6. "E38,Event #38" "0,1" newline bitfld.long 0x14 5. "E37,Event #37" "0,1" bitfld.long 0x14 4. "E36,Event #36" "0,1" newline bitfld.long 0x14 3. "E35,Event #35" "0,1" bitfld.long 0x14 2. "E34,Event #34" "0,1" newline bitfld.long 0x14 1. "E33,Event #33" "0,1" bitfld.long 0x14 0. "E32,Event #32" "0,1" line.long 0x18 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x18 31. "E31,Event #31" "0,1" bitfld.long 0x18 30. "E30,Event #30" "0,1" newline bitfld.long 0x18 29. "E29,Event #29" "0,1" bitfld.long 0x18 28. "E28,Event #28" "0,1" newline bitfld.long 0x18 27. "E27,Event #27" "0,1" bitfld.long 0x18 26. "E26,Event #26" "0,1" newline bitfld.long 0x18 25. "E25,Event #25" "0,1" bitfld.long 0x18 24. "E24,Event #24" "0,1" newline bitfld.long 0x18 23. "E23,Event #23" "0,1" bitfld.long 0x18 22. "E22,Event #22" "0,1" newline bitfld.long 0x18 21. "E21,Event #21" "0,1" bitfld.long 0x18 20. "E20,Event #20" "0,1" newline bitfld.long 0x18 19. "E19,Event #19" "0,1" bitfld.long 0x18 18. "E18,Event #18" "0,1" newline bitfld.long 0x18 17. "E17,Event #17" "0,1" bitfld.long 0x18 16. "E16,Event #16" "0,1" newline bitfld.long 0x18 15. "E15,Event #15" "0,1" bitfld.long 0x18 14. "E14,Event #14" "0,1" newline bitfld.long 0x18 13. "E13,Event #13" "0,1" bitfld.long 0x18 12. "E12,Event #12" "0,1" newline bitfld.long 0x18 11. "E11,Event #11" "0,1" bitfld.long 0x18 10. "E10,Event #10" "0,1" newline bitfld.long 0x18 9. "E9,Event #9" "0,1" bitfld.long 0x18 8. "E8,Event #8" "0,1" newline bitfld.long 0x18 7. "E7,Event #7" "0,1" bitfld.long 0x18 6. "E6,Event #6" "0,1" newline bitfld.long 0x18 5. "E5,Event #5" "0,1" bitfld.long 0x18 4. "E4,Event #4" "0,1" newline bitfld.long 0x18 3. "E3,Event #3" "0,1" bitfld.long 0x18 2. "E2,Event #2" "0,1" newline bitfld.long 0x18 1. "E1,Event #1" "0,1" bitfld.long 0x18 0. "E0,Event #0" "0,1" line.long 0x1C "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x1C 31. "E63,Event #63" "0,1" bitfld.long 0x1C 30. "E62,Event #62" "0,1" newline bitfld.long 0x1C 29. "E61,Event #61" "0,1" bitfld.long 0x1C 28. "E60,Event #60" "0,1" newline bitfld.long 0x1C 27. "E59,Event #59" "0,1" bitfld.long 0x1C 26. "E58,Event #58" "0,1" newline bitfld.long 0x1C 25. "E57,Event #57" "0,1" bitfld.long 0x1C 24. "E56,Event #56" "0,1" newline bitfld.long 0x1C 23. "E55,Event #55" "0,1" bitfld.long 0x1C 22. "E54,Event #54" "0,1" newline bitfld.long 0x1C 21. "E53,Event #53" "0,1" bitfld.long 0x1C 20. "E52,Event #52" "0,1" newline bitfld.long 0x1C 19. "E51,Event #51" "0,1" bitfld.long 0x1C 18. "E50,Event #50" "0,1" newline bitfld.long 0x1C 17. "E49,Event #49" "0,1" bitfld.long 0x1C 16. "E48,Event #48" "0,1" newline bitfld.long 0x1C 15. "E47,Event #47" "0,1" bitfld.long 0x1C 14. "E46,Event #46" "0,1" newline bitfld.long 0x1C 13. "E45,Event #45" "0,1" bitfld.long 0x1C 12. "E44,Event #44" "0,1" newline bitfld.long 0x1C 11. "E43,Event #43" "0,1" bitfld.long 0x1C 10. "E42,Event #42" "0,1" newline bitfld.long 0x1C 9. "E41,Event #41" "0,1" bitfld.long 0x1C 8. "E40,Event #40" "0,1" newline bitfld.long 0x1C 7. "E39,Event #39" "0,1" bitfld.long 0x1C 6. "E38,Event #38" "0,1" newline bitfld.long 0x1C 5. "E37,Event #37" "0,1" bitfld.long 0x1C 4. "E36,Event #36" "0,1" newline bitfld.long 0x1C 3. "E35,Event #35" "0,1" bitfld.long 0x1C 2. "E34,Event #34" "0,1" newline bitfld.long 0x1C 1. "E33,Event #33" "0,1" bitfld.long 0x1C 0. "E32,Event #32" "0,1" line.long 0x20 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x20 31. "E31,Event #31" "0,1" bitfld.long 0x20 30. "E30,Event #30" "0,1" newline bitfld.long 0x20 29. "E29,Event #29" "0,1" bitfld.long 0x20 28. "E28,Event #28" "0,1" newline bitfld.long 0x20 27. "E27,Event #27" "0,1" bitfld.long 0x20 26. "E26,Event #26" "0,1" newline bitfld.long 0x20 25. "E25,Event #25" "0,1" bitfld.long 0x20 24. "E24,Event #24" "0,1" newline bitfld.long 0x20 23. "E23,Event #23" "0,1" bitfld.long 0x20 22. "E22,Event #22" "0,1" newline bitfld.long 0x20 21. "E21,Event #21" "0,1" bitfld.long 0x20 20. "E20,Event #20" "0,1" newline bitfld.long 0x20 19. "E19,Event #19" "0,1" bitfld.long 0x20 18. "E18,Event #18" "0,1" newline bitfld.long 0x20 17. "E17,Event #17" "0,1" bitfld.long 0x20 16. "E16,Event #16" "0,1" newline bitfld.long 0x20 15. "E15,Event #15" "0,1" bitfld.long 0x20 14. "E14,Event #14" "0,1" newline bitfld.long 0x20 13. "E13,Event #13" "0,1" bitfld.long 0x20 12. "E12,Event #12" "0,1" newline bitfld.long 0x20 11. "E11,Event #11" "0,1" bitfld.long 0x20 10. "E10,Event #10" "0,1" newline bitfld.long 0x20 9. "E9,Event #9" "0,1" bitfld.long 0x20 8. "E8,Event #8" "0,1" newline bitfld.long 0x20 7. "E7,Event #7" "0,1" bitfld.long 0x20 6. "E6,Event #6" "0,1" newline bitfld.long 0x20 5. "E5,Event #5" "0,1" bitfld.long 0x20 4. "E4,Event #4" "0,1" newline bitfld.long 0x20 3. "E3,Event #3" "0,1" bitfld.long 0x20 2. "E2,Event #2" "0,1" newline bitfld.long 0x20 1. "E1,Event #1" "0,1" bitfld.long 0x20 0. "E0,Event #0" "0,1" line.long 0x24 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x24 31. "E63,Event #63" "0,1" bitfld.long 0x24 30. "E62,Event #62" "0,1" newline bitfld.long 0x24 29. "E61,Event #61" "0,1" bitfld.long 0x24 28. "E60,Event #60" "0,1" newline bitfld.long 0x24 27. "E59,Event #59" "0,1" bitfld.long 0x24 26. "E58,Event #58" "0,1" newline bitfld.long 0x24 25. "E57,Event #57" "0,1" bitfld.long 0x24 24. "E56,Event #56" "0,1" newline bitfld.long 0x24 23. "E55,Event #55" "0,1" bitfld.long 0x24 22. "E54,Event #54" "0,1" newline bitfld.long 0x24 21. "E53,Event #53" "0,1" bitfld.long 0x24 20. "E52,Event #52" "0,1" newline bitfld.long 0x24 19. "E51,Event #51" "0,1" bitfld.long 0x24 18. "E50,Event #50" "0,1" newline bitfld.long 0x24 17. "E49,Event #49" "0,1" bitfld.long 0x24 16. "E48,Event #48" "0,1" newline bitfld.long 0x24 15. "E47,Event #47" "0,1" bitfld.long 0x24 14. "E46,Event #46" "0,1" newline bitfld.long 0x24 13. "E45,Event #45" "0,1" bitfld.long 0x24 12. "E44,Event #44" "0,1" newline bitfld.long 0x24 11. "E43,Event #43" "0,1" bitfld.long 0x24 10. "E42,Event #42" "0,1" newline bitfld.long 0x24 9. "E41,Event #41" "0,1" bitfld.long 0x24 8. "E40,Event #40" "0,1" newline bitfld.long 0x24 7. "E39,Event #39" "0,1" bitfld.long 0x24 6. "E38,Event #38" "0,1" newline bitfld.long 0x24 5. "E37,Event #37" "0,1" bitfld.long 0x24 4. "E36,Event #36" "0,1" newline bitfld.long 0x24 3. "E35,Event #35" "0,1" bitfld.long 0x24 2. "E34,Event #34" "0,1" newline bitfld.long 0x24 1. "E33,Event #33" "0,1" bitfld.long 0x24 0. "E32,Event #32" "0,1" line.long 0x28 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x28 31. "E31,Event #31" "0,1" bitfld.long 0x28 30. "E30,Event #30" "0,1" newline bitfld.long 0x28 29. "E29,Event #29" "0,1" bitfld.long 0x28 28. "E28,Event #28" "0,1" newline bitfld.long 0x28 27. "E27,Event #27" "0,1" bitfld.long 0x28 26. "E26,Event #26" "0,1" newline bitfld.long 0x28 25. "E25,Event #25" "0,1" bitfld.long 0x28 24. "E24,Event #24" "0,1" newline bitfld.long 0x28 23. "E23,Event #23" "0,1" bitfld.long 0x28 22. "E22,Event #22" "0,1" newline bitfld.long 0x28 21. "E21,Event #21" "0,1" bitfld.long 0x28 20. "E20,Event #20" "0,1" newline bitfld.long 0x28 19. "E19,Event #19" "0,1" bitfld.long 0x28 18. "E18,Event #18" "0,1" newline bitfld.long 0x28 17. "E17,Event #17" "0,1" bitfld.long 0x28 16. "E16,Event #16" "0,1" newline bitfld.long 0x28 15. "E15,Event #15" "0,1" bitfld.long 0x28 14. "E14,Event #14" "0,1" newline bitfld.long 0x28 13. "E13,Event #13" "0,1" bitfld.long 0x28 12. "E12,Event #12" "0,1" newline bitfld.long 0x28 11. "E11,Event #11" "0,1" bitfld.long 0x28 10. "E10,Event #10" "0,1" newline bitfld.long 0x28 9. "E9,Event #9" "0,1" bitfld.long 0x28 8. "E8,Event #8" "0,1" newline bitfld.long 0x28 7. "E7,Event #7" "0,1" bitfld.long 0x28 6. "E6,Event #6" "0,1" newline bitfld.long 0x28 5. "E5,Event #5" "0,1" bitfld.long 0x28 4. "E4,Event #4" "0,1" newline bitfld.long 0x28 3. "E3,Event #3" "0,1" bitfld.long 0x28 2. "E2,Event #2" "0,1" newline bitfld.long 0x28 1. "E1,Event #1" "0,1" bitfld.long 0x28 0. "E0,Event #0" "0,1" line.long 0x2C "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x2C 31. "E63,Event #63" "0,1" bitfld.long 0x2C 30. "E62,Event #62" "0,1" newline bitfld.long 0x2C 29. "E61,Event #61" "0,1" bitfld.long 0x2C 28. "E60,Event #60" "0,1" newline bitfld.long 0x2C 27. "E59,Event #59" "0,1" bitfld.long 0x2C 26. "E58,Event #58" "0,1" newline bitfld.long 0x2C 25. "E57,Event #57" "0,1" bitfld.long 0x2C 24. "E56,Event #56" "0,1" newline bitfld.long 0x2C 23. "E55,Event #55" "0,1" bitfld.long 0x2C 22. "E54,Event #54" "0,1" newline bitfld.long 0x2C 21. "E53,Event #53" "0,1" bitfld.long 0x2C 20. "E52,Event #52" "0,1" newline bitfld.long 0x2C 19. "E51,Event #51" "0,1" bitfld.long 0x2C 18. "E50,Event #50" "0,1" newline bitfld.long 0x2C 17. "E49,Event #49" "0,1" bitfld.long 0x2C 16. "E48,Event #48" "0,1" newline bitfld.long 0x2C 15. "E47,Event #47" "0,1" bitfld.long 0x2C 14. "E46,Event #46" "0,1" newline bitfld.long 0x2C 13. "E45,Event #45" "0,1" bitfld.long 0x2C 12. "E44,Event #44" "0,1" newline bitfld.long 0x2C 11. "E43,Event #43" "0,1" bitfld.long 0x2C 10. "E42,Event #42" "0,1" newline bitfld.long 0x2C 9. "E41,Event #41" "0,1" bitfld.long 0x2C 8. "E40,Event #40" "0,1" newline bitfld.long 0x2C 7. "E39,Event #39" "0,1" bitfld.long 0x2C 6. "E38,Event #38" "0,1" newline bitfld.long 0x2C 5. "E37,Event #37" "0,1" bitfld.long 0x2C 4. "E36,Event #36" "0,1" newline bitfld.long 0x2C 3. "E35,Event #35" "0,1" bitfld.long 0x2C 2. "E34,Event #34" "0,1" newline bitfld.long 0x2C 1. "E33,Event #33" "0,1" bitfld.long 0x2C 0. "E32,Event #32" "0,1" line.long 0x30 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x30 31. "E31,Event #31" "0,1" bitfld.long 0x30 30. "E30,Event #30" "0,1" newline bitfld.long 0x30 29. "E29,Event #29" "0,1" bitfld.long 0x30 28. "E28,Event #28" "0,1" newline bitfld.long 0x30 27. "E27,Event #27" "0,1" bitfld.long 0x30 26. "E26,Event #26" "0,1" newline bitfld.long 0x30 25. "E25,Event #25" "0,1" bitfld.long 0x30 24. "E24,Event #24" "0,1" newline bitfld.long 0x30 23. "E23,Event #23" "0,1" bitfld.long 0x30 22. "E22,Event #22" "0,1" newline bitfld.long 0x30 21. "E21,Event #21" "0,1" bitfld.long 0x30 20. "E20,Event #20" "0,1" newline bitfld.long 0x30 19. "E19,Event #19" "0,1" bitfld.long 0x30 18. "E18,Event #18" "0,1" newline bitfld.long 0x30 17. "E17,Event #17" "0,1" bitfld.long 0x30 16. "E16,Event #16" "0,1" newline bitfld.long 0x30 15. "E15,Event #15" "0,1" bitfld.long 0x30 14. "E14,Event #14" "0,1" newline bitfld.long 0x30 13. "E13,Event #13" "0,1" bitfld.long 0x30 12. "E12,Event #12" "0,1" newline bitfld.long 0x30 11. "E11,Event #11" "0,1" bitfld.long 0x30 10. "E10,Event #10" "0,1" newline bitfld.long 0x30 9. "E9,Event #9" "0,1" bitfld.long 0x30 8. "E8,Event #8" "0,1" newline bitfld.long 0x30 7. "E7,Event #7" "0,1" bitfld.long 0x30 6. "E6,Event #6" "0,1" newline bitfld.long 0x30 5. "E5,Event #5" "0,1" bitfld.long 0x30 4. "E4,Event #4" "0,1" newline bitfld.long 0x30 3. "E3,Event #3" "0,1" bitfld.long 0x30 2. "E2,Event #2" "0,1" newline bitfld.long 0x30 1. "E1,Event #1" "0,1" bitfld.long 0x30 0. "E0,Event #0" "0,1" line.long 0x34 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x34 31. "E63,Event #63" "0,1" bitfld.long 0x34 30. "E62,Event #62" "0,1" newline bitfld.long 0x34 29. "E61,Event #61" "0,1" bitfld.long 0x34 28. "E60,Event #60" "0,1" newline bitfld.long 0x34 27. "E59,Event #59" "0,1" bitfld.long 0x34 26. "E58,Event #58" "0,1" newline bitfld.long 0x34 25. "E57,Event #57" "0,1" bitfld.long 0x34 24. "E56,Event #56" "0,1" newline bitfld.long 0x34 23. "E55,Event #55" "0,1" bitfld.long 0x34 22. "E54,Event #54" "0,1" newline bitfld.long 0x34 21. "E53,Event #53" "0,1" bitfld.long 0x34 20. "E52,Event #52" "0,1" newline bitfld.long 0x34 19. "E51,Event #51" "0,1" bitfld.long 0x34 18. "E50,Event #50" "0,1" newline bitfld.long 0x34 17. "E49,Event #49" "0,1" bitfld.long 0x34 16. "E48,Event #48" "0,1" newline bitfld.long 0x34 15. "E47,Event #47" "0,1" bitfld.long 0x34 14. "E46,Event #46" "0,1" newline bitfld.long 0x34 13. "E45,Event #45" "0,1" bitfld.long 0x34 12. "E44,Event #44" "0,1" newline bitfld.long 0x34 11. "E43,Event #43" "0,1" bitfld.long 0x34 10. "E42,Event #42" "0,1" newline bitfld.long 0x34 9. "E41,Event #41" "0,1" bitfld.long 0x34 8. "E40,Event #40" "0,1" newline bitfld.long 0x34 7. "E39,Event #39" "0,1" bitfld.long 0x34 6. "E38,Event #38" "0,1" newline bitfld.long 0x34 5. "E37,Event #37" "0,1" bitfld.long 0x34 4. "E36,Event #36" "0,1" newline bitfld.long 0x34 3. "E35,Event #35" "0,1" bitfld.long 0x34 2. "E34,Event #34" "0,1" newline bitfld.long 0x34 1. "E33,Event #33" "0,1" bitfld.long 0x34 0. "E32,Event #32" "0,1" line.long 0x38 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x38 31. "E31,Event #31" "0,1" bitfld.long 0x38 30. "E30,Event #30" "0,1" newline bitfld.long 0x38 29. "E29,Event #29" "0,1" bitfld.long 0x38 28. "E28,Event #28" "0,1" newline bitfld.long 0x38 27. "E27,Event #27" "0,1" bitfld.long 0x38 26. "E26,Event #26" "0,1" newline bitfld.long 0x38 25. "E25,Event #25" "0,1" bitfld.long 0x38 24. "E24,Event #24" "0,1" newline bitfld.long 0x38 23. "E23,Event #23" "0,1" bitfld.long 0x38 22. "E22,Event #22" "0,1" newline bitfld.long 0x38 21. "E21,Event #21" "0,1" bitfld.long 0x38 20. "E20,Event #20" "0,1" newline bitfld.long 0x38 19. "E19,Event #19" "0,1" bitfld.long 0x38 18. "E18,Event #18" "0,1" newline bitfld.long 0x38 17. "E17,Event #17" "0,1" bitfld.long 0x38 16. "E16,Event #16" "0,1" newline bitfld.long 0x38 15. "E15,Event #15" "0,1" bitfld.long 0x38 14. "E14,Event #14" "0,1" newline bitfld.long 0x38 13. "E13,Event #13" "0,1" bitfld.long 0x38 12. "E12,Event #12" "0,1" newline bitfld.long 0x38 11. "E11,Event #11" "0,1" bitfld.long 0x38 10. "E10,Event #10" "0,1" newline bitfld.long 0x38 9. "E9,Event #9" "0,1" bitfld.long 0x38 8. "E8,Event #8" "0,1" newline bitfld.long 0x38 7. "E7,Event #7" "0,1" bitfld.long 0x38 6. "E6,Event #6" "0,1" newline bitfld.long 0x38 5. "E5,Event #5" "0,1" bitfld.long 0x38 4. "E4,Event #4" "0,1" newline bitfld.long 0x38 3. "E3,Event #3" "0,1" bitfld.long 0x38 2. "E2,Event #2" "0,1" newline bitfld.long 0x38 1. "E1,Event #1" "0,1" bitfld.long 0x38 0. "E0,Event #0" "0,1" line.long 0x3C "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x3C 31. "E63,Event #63" "0,1" bitfld.long 0x3C 30. "E62,Event #62" "0,1" newline bitfld.long 0x3C 29. "E61,Event #61" "0,1" bitfld.long 0x3C 28. "E60,Event #60" "0,1" newline bitfld.long 0x3C 27. "E59,Event #59" "0,1" bitfld.long 0x3C 26. "E58,Event #58" "0,1" newline bitfld.long 0x3C 25. "E57,Event #57" "0,1" bitfld.long 0x3C 24. "E56,Event #56" "0,1" newline bitfld.long 0x3C 23. "E55,Event #55" "0,1" bitfld.long 0x3C 22. "E54,Event #54" "0,1" newline bitfld.long 0x3C 21. "E53,Event #53" "0,1" bitfld.long 0x3C 20. "E52,Event #52" "0,1" newline bitfld.long 0x3C 19. "E51,Event #51" "0,1" bitfld.long 0x3C 18. "E50,Event #50" "0,1" newline bitfld.long 0x3C 17. "E49,Event #49" "0,1" bitfld.long 0x3C 16. "E48,Event #48" "0,1" newline bitfld.long 0x3C 15. "E47,Event #47" "0,1" bitfld.long 0x3C 14. "E46,Event #46" "0,1" newline bitfld.long 0x3C 13. "E45,Event #45" "0,1" bitfld.long 0x3C 12. "E44,Event #44" "0,1" newline bitfld.long 0x3C 11. "E43,Event #43" "0,1" bitfld.long 0x3C 10. "E42,Event #42" "0,1" newline bitfld.long 0x3C 9. "E41,Event #41" "0,1" bitfld.long 0x3C 8. "E40,Event #40" "0,1" newline bitfld.long 0x3C 7. "E39,Event #39" "0,1" bitfld.long 0x3C 6. "E38,Event #38" "0,1" newline bitfld.long 0x3C 5. "E37,Event #37" "0,1" bitfld.long 0x3C 4. "E36,Event #36" "0,1" newline bitfld.long 0x3C 3. "E35,Event #35" "0,1" bitfld.long 0x3C 2. "E34,Event #34" "0,1" newline bitfld.long 0x3C 1. "E33,Event #33" "0,1" bitfld.long 0x3C 0. "E32,Event #32" "0,1" line.long 0x40 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x40 31. "E31,Event #31" "0,1" bitfld.long 0x40 30. "E30,Event #30" "0,1" newline bitfld.long 0x40 29. "E29,Event #29" "0,1" bitfld.long 0x40 28. "E28,Event #28" "0,1" newline bitfld.long 0x40 27. "E27,Event #27" "0,1" bitfld.long 0x40 26. "E26,Event #26" "0,1" newline bitfld.long 0x40 25. "E25,Event #25" "0,1" bitfld.long 0x40 24. "E24,Event #24" "0,1" newline bitfld.long 0x40 23. "E23,Event #23" "0,1" bitfld.long 0x40 22. "E22,Event #22" "0,1" newline bitfld.long 0x40 21. "E21,Event #21" "0,1" bitfld.long 0x40 20. "E20,Event #20" "0,1" newline bitfld.long 0x40 19. "E19,Event #19" "0,1" bitfld.long 0x40 18. "E18,Event #18" "0,1" newline bitfld.long 0x40 17. "E17,Event #17" "0,1" bitfld.long 0x40 16. "E16,Event #16" "0,1" newline bitfld.long 0x40 15. "E15,Event #15" "0,1" bitfld.long 0x40 14. "E14,Event #14" "0,1" newline bitfld.long 0x40 13. "E13,Event #13" "0,1" bitfld.long 0x40 12. "E12,Event #12" "0,1" newline bitfld.long 0x40 11. "E11,Event #11" "0,1" bitfld.long 0x40 10. "E10,Event #10" "0,1" newline bitfld.long 0x40 9. "E9,Event #9" "0,1" bitfld.long 0x40 8. "E8,Event #8" "0,1" newline bitfld.long 0x40 7. "E7,Event #7" "0,1" bitfld.long 0x40 6. "E6,Event #6" "0,1" newline bitfld.long 0x40 5. "E5,Event #5" "0,1" bitfld.long 0x40 4. "E4,Event #4" "0,1" newline bitfld.long 0x40 3. "E3,Event #3" "0,1" bitfld.long 0x40 2. "E2,Event #2" "0,1" newline bitfld.long 0x40 1. "E1,Event #1" "0,1" bitfld.long 0x40 0. "E0,Event #0" "0,1" line.long 0x44 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x44 31. "E63,Event #63" "0,1" bitfld.long 0x44 30. "E62,Event #62" "0,1" newline bitfld.long 0x44 29. "E61,Event #61" "0,1" bitfld.long 0x44 28. "E60,Event #60" "0,1" newline bitfld.long 0x44 27. "E59,Event #59" "0,1" bitfld.long 0x44 26. "E58,Event #58" "0,1" newline bitfld.long 0x44 25. "E57,Event #57" "0,1" bitfld.long 0x44 24. "E56,Event #56" "0,1" newline bitfld.long 0x44 23. "E55,Event #55" "0,1" bitfld.long 0x44 22. "E54,Event #54" "0,1" newline bitfld.long 0x44 21. "E53,Event #53" "0,1" bitfld.long 0x44 20. "E52,Event #52" "0,1" newline bitfld.long 0x44 19. "E51,Event #51" "0,1" bitfld.long 0x44 18. "E50,Event #50" "0,1" newline bitfld.long 0x44 17. "E49,Event #49" "0,1" bitfld.long 0x44 16. "E48,Event #48" "0,1" newline bitfld.long 0x44 15. "E47,Event #47" "0,1" bitfld.long 0x44 14. "E46,Event #46" "0,1" newline bitfld.long 0x44 13. "E45,Event #45" "0,1" bitfld.long 0x44 12. "E44,Event #44" "0,1" newline bitfld.long 0x44 11. "E43,Event #43" "0,1" bitfld.long 0x44 10. "E42,Event #42" "0,1" newline bitfld.long 0x44 9. "E41,Event #41" "0,1" bitfld.long 0x44 8. "E40,Event #40" "0,1" newline bitfld.long 0x44 7. "E39,Event #39" "0,1" bitfld.long 0x44 6. "E38,Event #38" "0,1" newline bitfld.long 0x44 5. "E37,Event #37" "0,1" bitfld.long 0x44 4. "E36,Event #36" "0,1" newline bitfld.long 0x44 3. "E35,Event #35" "0,1" bitfld.long 0x44 2. "E34,Event #34" "0,1" newline bitfld.long 0x44 1. "E33,Event #33" "0,1" bitfld.long 0x44 0. "E32,Event #32" "0,1" rgroup.long 0x1050++0x2B line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x08 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x0C "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x10 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x14 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x18 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x1C "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x20 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x24 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x28 "EDMA_TPCC_IEVAL,Interrupt Eval Register" hexmask.long 0x28 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" newline bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1080++0x17 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 7. "E7,Event #7" "0,1" newline rbitfld.long 0x04 6. "E6,Event #6" "0,1" rbitfld.long 0x04 5. "E5,Event #5" "0,1" newline rbitfld.long 0x04 4. "E4,Event #4" "0,1" rbitfld.long 0x04 3. "E3,Event #3" "0,1" newline rbitfld.long 0x04 2. "E2,Event #2" "0,1" rbitfld.long 0x04 1. "E1,Event #1" "0,1" newline rbitfld.long 0x04 0. "E0,Event #0" "0,1" line.long 0x08 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,Event #7" "0,1" newline bitfld.long 0x08 6. "E6,Event #6" "0,1" bitfld.long 0x08 5. "E5,Event #5" "0,1" newline bitfld.long 0x08 4. "E4,Event #4" "0,1" bitfld.long 0x08 3. "E3,Event #3" "0,1" newline bitfld.long 0x08 2. "E2,Event #2" "0,1" bitfld.long 0x08 1. "E1,Event #1" "0,1" newline bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,Event #7" "0,1" newline bitfld.long 0x0C 6. "E6,Event #6" "0,1" bitfld.long 0x0C 5. "E5,Event #5" "0,1" newline bitfld.long 0x0C 4. "E4,Event #4" "0,1" bitfld.long 0x0C 3. "E3,Event #3" "0,1" newline bitfld.long 0x0C 2. "E2,Event #2" "0,1" bitfld.long 0x0C 1. "E1,Event #1" "0,1" newline bitfld.long 0x0C 0. "E0,Event #0" "0,1" line.long 0x10 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 7. "E7,Event #7" "0,1" newline rbitfld.long 0x10 6. "E6,Event #6" "0,1" rbitfld.long 0x10 5. "E5,Event #5" "0,1" newline rbitfld.long 0x10 4. "E4,Event #4" "0,1" rbitfld.long 0x10 3. "E3,Event #3" "0,1" newline rbitfld.long 0x10 2. "E2,Event #2" "0,1" rbitfld.long 0x10 1. "E1,Event #1" "0,1" newline rbitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event #7" "0,1" newline bitfld.long 0x14 6. "E6,Event #6" "0,1" bitfld.long 0x14 5. "E5,Event #5" "0,1" newline bitfld.long 0x14 4. "E4,Event #4" "0,1" bitfld.long 0x14 3. "E3,Event #3" "0,1" newline bitfld.long 0x14 2. "E2,Event #2" "0,1" bitfld.long 0x14 1. "E1,Event #1" "0,1" newline bitfld.long 0x14 0. "E0,Event #0" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2200++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2600++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2204++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2604++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2208++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2608++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x220C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x260C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2210++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2610++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2214++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2614++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2218++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2618++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x221C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x261C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2220++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2620++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2224++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2624++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2228++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2628++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x222C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x262C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2230++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2630++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2234++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2634++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2238++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2638++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x223C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x263C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2240++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2640++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2244++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2644++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2250++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2650++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2254++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2654++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2258++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2658++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x225C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x265C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2260++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2660++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2264++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2664++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2268++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2668++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x226C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x266C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2270++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2670++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2274++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2674++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2278++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2678++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2A78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2C78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2E78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2280++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2680++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2284++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2684++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2288++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2688++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x228C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x268C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2290++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2690++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2294++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2694++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4020++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_1,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4060++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_3,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_5,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_6,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_7,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4100++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_8,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4120++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_9,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4140++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4160++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_11,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4180++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_12,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_13,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_14,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_15,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4200++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4220++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_17,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4240++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_18,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4260++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_19,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4280++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_20,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_21,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_22,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_23,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4300++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_24,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4320++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_25,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4340++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_26,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4360++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_27,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4380++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_28,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_29,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_30,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_31,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4400++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4420++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_33,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4440++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_34,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4460++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_35,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4480++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_36,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_37,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_38,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_39,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4500++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_40,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4520++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_41,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4540++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_42,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4560++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_43,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4580++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_44,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_45,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_46,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_47,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4600++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4620++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_49,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4640++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_50,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4660++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_51,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4680++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_52,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_53,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_54,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_55,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4700++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_56,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4720++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_57,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4740++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_58,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4760++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_59,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4780++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_60,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_61,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_62,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_63,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4800++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4820++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_65,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4840++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_66,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4860++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_67,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4880++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_68,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_69,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_70,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_71,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4900++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_72,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4920++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_73,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4940++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_74,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4960++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_75,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4980++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_76,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_77,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_78,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_79,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_81,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_82,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_83,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_84,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_85,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_86,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_87,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_88,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_89,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_90,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_91,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_92,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_93,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_94,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_95,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_96,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_97,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_98,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_99,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_101,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_102,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_103,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_104,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_105,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_106,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_107,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_108,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_109,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_110,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_111,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_113,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_114,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_115,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_116,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_117,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_118,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_119,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_120,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_121,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_122,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_123,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_124,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_125,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_126,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_127,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" group.long 0x4024++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_1,Source Address" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" group.long 0x4064++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_3,Source Address" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" group.long 0x40A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_5,Source Address" group.long 0x40C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_6,Source Address" group.long 0x40E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_7,Source Address" group.long 0x4104++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_8,Source Address" group.long 0x4124++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_9,Source Address" group.long 0x4144++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_10,Source Address" group.long 0x4164++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_11,Source Address" group.long 0x4184++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_12,Source Address" group.long 0x41A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_13,Source Address" group.long 0x41C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_14,Source Address" group.long 0x41E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_15,Source Address" group.long 0x4204++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_16,Source Address" group.long 0x4224++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_17,Source Address" group.long 0x4244++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_18,Source Address" group.long 0x4264++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_19,Source Address" group.long 0x4284++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_20,Source Address" group.long 0x42A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_21,Source Address" group.long 0x42C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_22,Source Address" group.long 0x42E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_23,Source Address" group.long 0x4304++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_24,Source Address" group.long 0x4324++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_25,Source Address" group.long 0x4344++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_26,Source Address" group.long 0x4364++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_27,Source Address" group.long 0x4384++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_28,Source Address" group.long 0x43A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_29,Source Address" group.long 0x43C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_30,Source Address" group.long 0x43E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_31,Source Address" group.long 0x4404++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_32,Source Address" group.long 0x4424++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_33,Source Address" group.long 0x4444++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_34,Source Address" group.long 0x4464++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_35,Source Address" group.long 0x4484++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_36,Source Address" group.long 0x44A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_37,Source Address" group.long 0x44C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_38,Source Address" group.long 0x44E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_39,Source Address" group.long 0x4504++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_40,Source Address" group.long 0x4524++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_41,Source Address" group.long 0x4544++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_42,Source Address" group.long 0x4564++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_43,Source Address" group.long 0x4584++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_44,Source Address" group.long 0x45A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_45,Source Address" group.long 0x45C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_46,Source Address" group.long 0x45E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_47,Source Address" group.long 0x4604++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_48,Source Address" group.long 0x4624++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_49,Source Address" group.long 0x4644++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_50,Source Address" group.long 0x4664++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_51,Source Address" group.long 0x4684++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_52,Source Address" group.long 0x46A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_53,Source Address" group.long 0x46C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_54,Source Address" group.long 0x46E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_55,Source Address" group.long 0x4704++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_56,Source Address" group.long 0x4724++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_57,Source Address" group.long 0x4744++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_58,Source Address" group.long 0x4764++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_59,Source Address" group.long 0x4784++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_60,Source Address" group.long 0x47A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_61,Source Address" group.long 0x47C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_62,Source Address" group.long 0x47E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_63,Source Address" group.long 0x4804++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_64,Source Address" group.long 0x4824++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_65,Source Address" group.long 0x4844++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_66,Source Address" group.long 0x4864++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_67,Source Address" group.long 0x4884++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_68,Source Address" group.long 0x48A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_69,Source Address" group.long 0x48C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_70,Source Address" group.long 0x48E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_71,Source Address" group.long 0x4904++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_72,Source Address" group.long 0x4924++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_73,Source Address" group.long 0x4944++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_74,Source Address" group.long 0x4964++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_75,Source Address" group.long 0x4984++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_76,Source Address" group.long 0x49A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_77,Source Address" group.long 0x49C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_78,Source Address" group.long 0x49E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_79,Source Address" group.long 0x4A04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_80,Source Address" group.long 0x4A24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_81,Source Address" group.long 0x4A44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_82,Source Address" group.long 0x4A64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_83,Source Address" group.long 0x4A84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_84,Source Address" group.long 0x4AA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_85,Source Address" group.long 0x4AC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_86,Source Address" group.long 0x4AE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_87,Source Address" group.long 0x4B04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_88,Source Address" group.long 0x4B24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_89,Source Address" group.long 0x4B44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_90,Source Address" group.long 0x4B64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_91,Source Address" group.long 0x4B84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_92,Source Address" group.long 0x4BA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_93,Source Address" group.long 0x4BC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_94,Source Address" group.long 0x4BE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_95,Source Address" group.long 0x4C04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_96,Source Address" group.long 0x4C24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_97,Source Address" group.long 0x4C44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_98,Source Address" group.long 0x4C64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_99,Source Address" group.long 0x4C84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_100,Source Address" group.long 0x4CA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_101,Source Address" group.long 0x4CC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_102,Source Address" group.long 0x4CE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_103,Source Address" group.long 0x4D04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_104,Source Address" group.long 0x4D24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_105,Source Address" group.long 0x4D44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_106,Source Address" group.long 0x4D64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_107,Source Address" group.long 0x4D84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_108,Source Address" group.long 0x4DA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_109,Source Address" group.long 0x4DC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_110,Source Address" group.long 0x4DE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_111,Source Address" group.long 0x4E04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_112,Source Address" group.long 0x4E24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_113,Source Address" group.long 0x4E44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_114,Source Address" group.long 0x4E64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_115,Source Address" group.long 0x4E84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_116,Source Address" group.long 0x4EA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_117,Source Address" group.long 0x4EC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_118,Source Address" group.long 0x4EE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_119,Source Address" group.long 0x4F04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_120,Source Address" group.long 0x4F24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_121,Source Address" group.long 0x4F44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_122,Source Address" group.long 0x4F64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_123,Source Address" group.long 0x4F84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_124,Source Address" group.long 0x4FA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_125,Source Address" group.long 0x4FC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_126,Source Address" group.long 0x4FE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_127,Source Address" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x402C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_1,Destination Address" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x406C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_3,Destination Address" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x40AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_5,Destination Address" group.long 0x40CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_6,Destination Address" group.long 0x40EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_7,Destination Address" group.long 0x410C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_8,Destination Address" group.long 0x412C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_9,Destination Address" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x416C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_11,Destination Address" group.long 0x418C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_12,Destination Address" group.long 0x41AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_13,Destination Address" group.long 0x41CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_14,Destination Address" group.long 0x41EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_15,Destination Address" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x422C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_17,Destination Address" group.long 0x424C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_18,Destination Address" group.long 0x426C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_19,Destination Address" group.long 0x428C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_20,Destination Address" group.long 0x42AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_21,Destination Address" group.long 0x42CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_22,Destination Address" group.long 0x42EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_23,Destination Address" group.long 0x430C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_24,Destination Address" group.long 0x432C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_25,Destination Address" group.long 0x434C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_26,Destination Address" group.long 0x436C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_27,Destination Address" group.long 0x438C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_28,Destination Address" group.long 0x43AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_29,Destination Address" group.long 0x43CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_30,Destination Address" group.long 0x43EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_31,Destination Address" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x442C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_33,Destination Address" group.long 0x444C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_34,Destination Address" group.long 0x446C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_35,Destination Address" group.long 0x448C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_36,Destination Address" group.long 0x44AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_37,Destination Address" group.long 0x44CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_38,Destination Address" group.long 0x44EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_39,Destination Address" group.long 0x450C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_40,Destination Address" group.long 0x452C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_41,Destination Address" group.long 0x454C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_42,Destination Address" group.long 0x456C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_43,Destination Address" group.long 0x458C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_44,Destination Address" group.long 0x45AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_45,Destination Address" group.long 0x45CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_46,Destination Address" group.long 0x45EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_47,Destination Address" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x462C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_49,Destination Address" group.long 0x464C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_50,Destination Address" group.long 0x466C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_51,Destination Address" group.long 0x468C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_52,Destination Address" group.long 0x46AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_53,Destination Address" group.long 0x46CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_54,Destination Address" group.long 0x46EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_55,Destination Address" group.long 0x470C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_56,Destination Address" group.long 0x472C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_57,Destination Address" group.long 0x474C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_58,Destination Address" group.long 0x476C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_59,Destination Address" group.long 0x478C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_60,Destination Address" group.long 0x47AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_61,Destination Address" group.long 0x47CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_62,Destination Address" group.long 0x47EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_63,Destination Address" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x482C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_65,Destination Address" group.long 0x484C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_66,Destination Address" group.long 0x486C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_67,Destination Address" group.long 0x488C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_68,Destination Address" group.long 0x48AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_69,Destination Address" group.long 0x48CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_70,Destination Address" group.long 0x48EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_71,Destination Address" group.long 0x490C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_72,Destination Address" group.long 0x492C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_73,Destination Address" group.long 0x494C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_74,Destination Address" group.long 0x496C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_75,Destination Address" group.long 0x498C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_76,Destination Address" group.long 0x49AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_77,Destination Address" group.long 0x49CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_78,Destination Address" group.long 0x49EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_79,Destination Address" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_81,Destination Address" group.long 0x4A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_82,Destination Address" group.long 0x4A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_83,Destination Address" group.long 0x4A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_84,Destination Address" group.long 0x4AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_85,Destination Address" group.long 0x4ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_86,Destination Address" group.long 0x4AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_87,Destination Address" group.long 0x4B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_88,Destination Address" group.long 0x4B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_89,Destination Address" group.long 0x4B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_90,Destination Address" group.long 0x4B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_91,Destination Address" group.long 0x4B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_92,Destination Address" group.long 0x4BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_93,Destination Address" group.long 0x4BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_94,Destination Address" group.long 0x4BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_95,Destination Address" group.long 0x4C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_96,Destination Address" group.long 0x4C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_97,Destination Address" group.long 0x4C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_98,Destination Address" group.long 0x4C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_99,Destination Address" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_101,Destination Address" group.long 0x4CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_102,Destination Address" group.long 0x4CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_103,Destination Address" group.long 0x4D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_104,Destination Address" group.long 0x4D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_105,Destination Address" group.long 0x4D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_106,Destination Address" group.long 0x4D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_107,Destination Address" group.long 0x4D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_108,Destination Address" group.long 0x4DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_109,Destination Address" group.long 0x4DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_110,Destination Address" group.long 0x4DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_111,Destination Address" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_113,Destination Address" group.long 0x4E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_114,Destination Address" group.long 0x4E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_115,Destination Address" group.long 0x4E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_116,Destination Address" group.long 0x4EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_117,Destination Address" group.long 0x4ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_118,Destination Address" group.long 0x4EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_119,Destination Address" group.long 0x4F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_120,Destination Address" group.long 0x4F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_121,Destination Address" group.long 0x4F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_122,Destination Address" group.long 0x4F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_123,Destination Address" group.long 0x4F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_124,Destination Address" group.long 0x4FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_125,Destination Address" group.long 0x4FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_126,Destination Address" group.long 0x4FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_127,Destination Address" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_1," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_3," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_5," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_6," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_7," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_8," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_9," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_11," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_12," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_13," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_14," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_15," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_17," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_18," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_19," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_20," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_21," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_22," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_23," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_24," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_25," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_26," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_27," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_28," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_29," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_30," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_31," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_33," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_34," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_35," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_36," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_37," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_38," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_39," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_40," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_41," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_42," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_43," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_44," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_45," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_46," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_47," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_49," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_50," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_51," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_52," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_53," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_54," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_55," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_56," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_57," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_58," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_59," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_60," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_61," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_62," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_63," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_65," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_66," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_67," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_68," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_69," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_70," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_71," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_72," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_73," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_74," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_75," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_76," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_77," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_78," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_79," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_81," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_82," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_83," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_84," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_85," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_86," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_87," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_88," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_89," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_90," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_91," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_92," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_93," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_94," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_95," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_96," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_97," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_98," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_99," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_101," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_102," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_103," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_104," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_105," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_106," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_107," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_108," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_109," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_110," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_111," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_113," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_114," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_115," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_116," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_117," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_118," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_119," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_120," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_121," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_122," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_123," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_124," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_125," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_126," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_127," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x403C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x407C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x411C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x413C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x417C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x419C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x423C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x425C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x427C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x429C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x431C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x433C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x435C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x437C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x439C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x443C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x445C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x447C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x449C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x451C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x453C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x455C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x457C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x459C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x463C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x465C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x467C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x469C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x471C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x473C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x475C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x477C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x479C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x483C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x485C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x487C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x489C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x491C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x493C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x495C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x497C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x499C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x40D05000 ad:0x40D06000 ) tree "DSP1_EDMA_TPTC$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPTCn_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPTCn_TCCFG,TC Configuration Register" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 8.--9. "DREGDEPTH,Destination Register FIFO Depth Parameterization" "0,1,2,3" bitfld.long 0x04 6.--7. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" group.long 0x100++0x13 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 11.--12. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" rbitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" rbitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" line.long 0x04 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" rbitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x08 "EDMA_TPTCn_INTEN,Interrupt Enable Register" hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x0C "EDMA_TPTCn_INTCLR,Interrupt Clear Register" hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x10 "EDMA_TPTCn_INTCMD,Interrupt Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" group.long 0x120++0x13 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" rbitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 1. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" line.long 0x04 "EDMA_TPTCn_ERREN,Error Enable Register" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x04 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x04 1. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" line.long 0x08 "EDMA_TPTCn_ERRCLR,Error Clear Register" hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x08 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x08 1. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" line.long 0x0C "EDMA_TPTCn_ERRDET,Error Details Register" hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0C 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" rbitfld.long 0x0C 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 14.--15. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EDMA_TPTCn_ERRCMD,Error Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" group.long 0x200++0x17 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" rbitfld.long 0x00 21. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" rbitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "Highest priority,Priority 1,?,?,?,?,?,Lowest priority" newline rbitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" line.long 0x08 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count" line.long 0x0C "EDMA_TPTCn_PDST,Program Set Destination Address" line.long 0x10 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" line.long 0x14 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x240++0x23 line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" line.long 0x08 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" line.long 0x0C "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved. return 0x0 w/o AERROR" line.long 0x10 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" line.long 0x14 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" line.long 0x1C "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" line.long 0x20 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" group.long 0x280++0x0B line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" line.long 0x04 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" line.long 0x08 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" group.long 0x300++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x304++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x344++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x308++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x348++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x30C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x34C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x350++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" group.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x354++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end repeat.end tree "DSP1_FW_CFG_TARG" base ad:0x4A172000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DSP1_FW_L2_NOC_CFG" base ad:0x40D03000 group.long 0x00++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0,Core 0 Error log register" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" newline rbitfld.long 0x00 26. "RESERVED," "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" bitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x40++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 2.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x88++0x17 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" line.long 0x08 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1,Start physical address of region 1" hexmask.long 0x08 4.--31. 1. "RESERVED," bitfld.long 0x08 0.--3. "START_REGION_1,Physical target start address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1,End physical address of region 1" bitfld.long 0x0C 31. "END_REGION_1_ENABLE,End Region 1 enable" "0,1" hexmask.long 0x0C 4.--30. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "END_REGION_1,Physical target end address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_1,RM_PERMISSION_REGION_1_LOW register" hexmask.long.word 0x10 16.--31. 1. "RESERVED," bitfld.long 0x10 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x10 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x10 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x10 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x10 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x10 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x10 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x10 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x10 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_1,RM_PERMISSION_REGION_1_HIGH register" bitfld.long 0x14 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x14 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x14 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x14 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x14 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x14 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x14 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x14 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x14 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x14 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x14 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x14 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x14 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x14 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x14 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x14 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x14 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x14 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x14 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x14 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x14 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x14 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x14 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x14 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x14 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x14 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x14 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x14 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x14 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x14 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x14 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x14 0. "R0,Initiator ID0 permission" "0,1" group.long 0x1000++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0,Core 0 Error log register" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" newline rbitfld.long 0x00 26. "RESERVED," "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" bitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x1040++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 2.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x1088++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" rgroup.long 0x4000++0x17 line.long 0x00 "DSPNOC_FLAGMUX_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_FLAGMUX_ID_REVISIONID," line.long 0x08 "DSPNOC_FLAGMUX_FAULTEN," hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "FAULTEN,Global Fault Enable register" "0,1" line.long 0x0C "DSPNOC_FLAGMUX_FAULTSTATUS," hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "FAULTSTATUS,Global Fault Status register" "0,1" line.long 0x10 "DSPNOC_FLAGMUX_FLAGINEN0," hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" line.long 0x14 "DSPNOC_FLAGMUX_FLAGINSTATUS0," hexmask.long 0x14 1.--31. 1. "RESERVED," bitfld.long 0x14 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" rgroup.long 0x4200++0x1B line.long 0x00 "DSPNOC_ERRORLOG_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_ERRORLOG_ID_REVISIONID," line.long 0x08 "DSPNOC_ERRORLOG_FAULTEN," hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "FAULTEN,Enable Fault output" "0,1" line.long 0x0C "DSPNOC_ERRORLOG_ERRVLD," hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "ERRVLD,Error logged Valid" "0,1" line.long 0x10 "DSPNOC_ERRORLOG_ERRCLR," hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "ERRCLR,Clr ErrVld status" "0,1" line.long 0x14 "DSPNOC_ERRORLOG_ERRLOG0,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x14 31. "FORMAT,Format of ErrLog0 register" "0,1" bitfld.long 0x14 28.--30. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--27. 1. "LEN1,Header: Len1 value" bitfld.long 0x14 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x14 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0. "LOCK,Header: Lock bit value" "0,1" line.long 0x18 "DSPNOC_ERRORLOG_ERRLOG1," hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED," hexmask.long.word 0x18 0.--14. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x4220++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG3," bitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 0.--30. 1. "ERRLOG3,Header: Addr lsb value" rgroup.long 0x4228++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG5," hexmask.long.word 0x00 22.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--21. 1. "ERRLOG5,Header: User lsb value" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x40D01000 ad:0x40D02000 ) tree "DSP1_MMU$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Write 0's for future compatibility" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" rbitfld.long 0x00 5.--7. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x00 2. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" hexmask.long 0x08 5.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" newline bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0_w,EMUMISS_1_r" bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" hexmask.long 0x0C 5.--31. 1. "RESERVED,Write 0's for future compatibility Read returns 0" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" newline bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0,EMUMISS_1" bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" hexmask.long 0x00 1.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" hexmask.long 0x04 4.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable" "TWLENABLE_0,TWLENABLE_1" newline bitfld.long 0x04 1. "MMUENABLE,MMU enable" "MMUENABLE_0,MMUENABLE_1" rbitfld.long 0x04 0. "RESERVED,Write 0's for future compatibility" "0,1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" hexmask.long.byte 0x0C 0.--6. 1. "RESERVED,Write 0's for future compatibility" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 9. "RESERVED,Write 0's for future compatibility" "0,1" newline bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 0.--3. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" hexmask.long 0x14 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x18 4.--11. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x18 3. "P,Preserved bit" "P_0,P_1" newline bitfld.long 0x18 2. "V,Valid bit" "V_0,V_1" bitfld.long 0x18 0.--1. "PAGESIZE,Page size" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x1C 0.--11. 1. "RESERVED,Write 0's for future compatibility" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" hexmask.long 0x20 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" hexmask.long 0x24 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x28 4.--11. 1. "RESERVED,Reads return 0" bitfld.long 0x28 3. "P,Preserved bit" "P_0_r,P_1_r" newline bitfld.long 0x28 2. "V,Valid bit" "V_0_r,V_1_r" bitfld.long 0x28 0.--1. "PAGESIZE,Page size" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x2C 0.--11. 1. "RESERVED,Reads return 0" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" newline rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "0,1,2,3" bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "0,1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" hexmask.long.word 0x08 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 0.--15. 1. "RESERVED,Reserved" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 0.--15. 1. "RESERVED,Reserved" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 0.--15. 1. "RESERVED,Reserved" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the fourth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 0.--15. 1. "RESERVED,Reserved" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of fourth NO TRANSLATION REGION for 2D bursts" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" width 0x0B tree.end repeat.end tree "DSP1_PRM" base ad:0x4AE06400 group.long 0x00++0x07 line.long 0x00 "PM_DSP1_PWRSTCTRL,This register controls the DSP power state to reach upon a domain sleep transition" hexmask.long.word 0x00 22.--31. 1. "RESERVED," rbitfld.long 0x00 20.--21. "DSP1_EDMA_ONSTATE,DSP_EDMA state when domain is ON" "?,?,?,DSP1_EDMA_ONSTATE_3" rbitfld.long 0x00 18.--19. "DSP1_L2_ONSTATE,DSP_L2 state when domain is ON" "?,?,?,DSP1_L2_ONSTATE_3" newline rbitfld.long 0x00 16.--17. "DSP1_L1_ONSTATE,DSP_L1 state when domain is ON" "?,?,?,DSP1_L1_ONSTATE_3" hexmask.long.word 0x00 5.--15. 1. "RESERVED," bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_DSP1_PWRSTST,This register provides a status on the DSP domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" hexmask.long.word 0x04 10.--19. 1. "RESERVED," rbitfld.long 0x04 8.--9. "DSP1_EDMA_STATEST,DSP_EDMA memory state status" "DSP1_EDMA_STATEST_0,DSP1_EDMA_STATEST_1,DSP1_EDMA_STATEST_2,DSP1_EDMA_STATEST_3" newline rbitfld.long 0x04 6.--7. "DSP1_L2_STATEST,DSP_L2 memory state status" "DSP1_L2_STATEST_0,DSP1_L2_STATEST_1,DSP1_L2_STATEST_2,DSP1_L2_STATEST_3" rbitfld.long 0x04 4.--5. "DSP1_L1_STATEST,DSP_L1 memory state status" "DSP1_L1_STATEST_0,DSP1_L1_STATEST_1,DSP1_L1_STATEST_2,DSP1_L1_STATEST_3" rbitfld.long 0x04 3. "RESERVED," "0,1" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_DSP1_RSTCTRL,This register controls the release of the DSP sub-system resets" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "RST_DSP1,DSP reset control" "RST_DSP1_0,RST_DSP1_1" bitfld.long 0x00 0. "RST_DSP1_LRST,DSP Local reset control" "RST_DSP1_LRST_0,RST_DSP1_LRST_1" line.long 0x04 "RM_DSP1_RSTST,This register logs the different reset sources of the DSP domain" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "RST_DSP1_EMU_REQ,DSP processor has been reset due to DSP emulation reset request driven from DSP-SS" "RST_DSP1_EMU_REQ_0,RST_DSP1_EMU_REQ_1" bitfld.long 0x04 2. "RST_DSP1_EMU,DSP domain has been reset due to emulation reset source e.g" "RST_DSP1_EMU_0,RST_DSP1_EMU_1" newline bitfld.long 0x04 1. "RST_DSP1,DSP SW reset status" "RST_DSP1_0,RST_DSP1_1" bitfld.long 0x04 0. "RST_DSP1_LRST,DSP Local SW reset" "RST_DSP1_LRST_0,RST_DSP1_LRST_1" group.long 0x24++0x03 line.long 0x00 "RM_DSP1_DSP1_CONTEXT,This register contains dedicated DSP context statuses" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," bitfld.long 0x00 10. "LOSTMEM_DSP_EDMA,Specify if memory-based context in DSP_EDMA memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_EDMA_0,LOSTMEM_DSP_EDMA_1" bitfld.long 0x00 9. "LOSTMEM_DSP_L2,Specify if memory-based context in DSP_L2 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_L2_0,LOSTMEM_DSP_L2_1" newline bitfld.long 0x00 8. "LOSTMEM_DSP_L1,Specify if memory-based context in DSP_L1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_L1_0,LOSTMEM_DSP_L1_1" hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "DSP1_SDMA_FW" base ad:0x4A171000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "DSP1_SDMA_TARG" base ad:0x44000300 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "DSP1_SYSTEM" base ad:0x40D00000 rgroup.long 0x00++0x1B line.long 0x00 "DSP_SYS_REVISION," line.long 0x04 "DSP_SYS_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," bitfld.long 0x04 0.--3. "NUM,Instance Number Set by subsystem input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DSP_SYS_SYSCONFIG," hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 8. "RESERVED,Reserved" "0,1" rbitfld.long 0x08 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x08 4.--5. "STANDBYMODE," "?,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x08 2.--3. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x08 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x0C "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode" hexmask.long 0x0C 6.--31. 1. "RESERVED," bitfld.long 0x0C 4.--5. "OCPI_DISC_STAT,L3_MAIN (OCP) Initiator(s) Disconnect Status" "OCPI_DISC_STAT_0_r,OCPI_DISC_STAT_1_r,OCPI_DISC_STAT_2_r,?" bitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "TC1_STAT,EDMA TC1 Status" "TC1_STAT_0,TC1_STAT_1" bitfld.long 0x0C 1. "TC0_STAT,EDMA TC0 Status" "TC0_STAT_0,TC0_STAT_1" bitfld.long 0x0C 0. "C66X_STAT,C66x Status" "C66X_STAT_0,C66X_STAT_1" line.long 0x10 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "OCPI_DISC,OCP Initiator (on L3_MAIN) Disconnect request" "OCPI_DISC_0_w,OCPI_DISC_1_w" line.long 0x14 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators" rbitfld.long 0x14 31. "RESERVED," "0,1" bitfld.long 0x14 28.--30. "SDMA_PRI,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port" "0,1,2,3,4,5,6,7" rbitfld.long 0x14 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 24. "NOPOSTOVERRIDE,OCP Posted Write vs Non-Posted Write override" "NOPOSTOVERRIDE_0,NOPOSTOVERRIDE_1" rbitfld.long 0x14 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x14 20.--21. "SDMA_L2PRES,OCP Target port L2 Interconnect Pressure" "SDMA_L2PRES_0,SDMA_L2PRES_1,SDMA_L2PRES_2,SDMA_L2PRES_3" newline rbitfld.long 0x14 18.--19. "RESERVED," "0,1,2,3" bitfld.long 0x14 16.--17. "CFG_L2PRES,DSP CFG L2 Interconnect Pressure" "CFG_L2PRES_0,CFG_L2PRES_1,CFG_L2PRES_2,CFG_L2PRES_3" rbitfld.long 0x14 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 12.--13. "TC1_L2PRES,TC1 L2 Interconnect Pressure" "TC1_L2PRES_0,TC1_L2PRES_1,TC1_L2PRES_2,TC1_L2PRES_3" rbitfld.long 0x14 10.--11. "RESERVED," "0,1,2,3" bitfld.long 0x14 8.--9. "TC0_L2PRES,TC0 L2 Interconnect Pressure" "TC0_L2PRES_0,TC0_L2PRES_1,TC0_L2PRES_2,TC0_L2PRES_3" newline rbitfld.long 0x14 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x14 4.--5. "TC1_DBS,TC1 Default Burst size" "TC1_DBS_0,TC1_DBS_1,TC1_DBS_2,TC1_DBS_3" rbitfld.long 0x14 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 0.--1. "TC0_DBS,TC0 Default Burst size" "TC0_DBS_0,TC0_DBS_1,TC0_DBS_2,TC0_DBS_3" line.long 0x18 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs" hexmask.long.tbyte 0x18 13.--31. 1. "RESERVED," bitfld.long 0x18 12. "MMU1_ABORT,MU1 Abort" "MMU1_ABORT_0,MMU1_ABORT_1" rbitfld.long 0x18 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "MMU0_ABORT,MU0 Abort" "MMU0_ABORT_0,MMU0_ABORT_1" rbitfld.long 0x18 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 4. "MMU1_EN,MU1 Enable" "MMU1_EN_0,MMU1_EN_1" newline rbitfld.long 0x18 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 0. "MMU0_EN,MU1 Enable" "MMU0_EN_0,MMU0_EN_1" group.long 0x20++0x07 line.long 0x00 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x30++0x07 line.long 0x00 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x40++0x07 line.long 0x00 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state" line.long 0x04 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state" group.long 0x50++0x2F line.long 0x00 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.word 0x00 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--18. 1. "EVENT,Settable raw status for event #n" line.long 0x04 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector" hexmask.long.word 0x04 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x04 0.--18. 1. "EVENT,Clearable enabled status for event #n" line.long 0x08 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" hexmask.long.word 0x08 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x08 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x0C "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" hexmask.long.word 0x0C 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x0C 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x10 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x14 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x18 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x1C "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" line.long 0x20 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x24 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x28 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x2C "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" group.long 0xF8++0x07 line.long 0x00 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus" hexmask.long 0x00 4.--31. 1. "RESERVED," bitfld.long 0x00 0.--3. "GROUP,Debug Group output control mux selectN: GN = select output group N" "GROUP_0,GROUP_1,GROUP_2,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group" width 0x0B tree.end tree "DSP2_CM_CORE_AON" base ad:0x4A005600 group.long 0x00++0x0B line.long 0x00 "CM_DSP2_CLKSTCTRL,This register enables the DSP domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_DSP2_GFCLK,This field indicates the state of the DSP_ROOT_CLK clock in the domain" "CLKACTIVITY_DSP2_GFCLK_0,CLKACTIVITY_DSP2_GFCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_DSP2_STATICDEP,This register controls the static domain depedencies from DSP domain towards 'target' domains" rbitfld.long 0x04 31. "RESERVED," "0,1" bitfld.long 0x04 30. "CRC_STATDEP,Static dependency towards L3INIT clock domain" "CRC_STATDEP_0,CRC_STATDEP_1" newline bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE cLOCK dOMAIN" "PCIE_STATDEP_0,PCIE_STATDEP_1" bitfld.long 0x04 28. "ISS_STATDEP,Static dependency towards ISS Clock Domain" "ISS_STATDEP_0,ISS_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 Clock Domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 Clock Domain" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC Clock Domain" "GMAC_STATDEP_0,GMAC_STATDEP_1" bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPUClock Domain" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain" "IPU1_STATDEP_0,IPU1_STATDEP_1" bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 Clock Domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" newline bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 Clock Domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2CLOCK dOMAIN" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 CLOCK dOMAIN" "EVE1_STATDEP_0,EVE1_STATDEP_1" rbitfld.long 0x04 18. "RESERVED," "0,1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain" "CUSTEFUSE_STATDEP_0,?" rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC Clock Domain" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" rbitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,?" newline rbitfld.long 0x04 11. "RESERVED," "0,1" bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU Clock Domain" "GPU_STATDEP_0,GPU_STATDEP_1" newline bitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain" "CAM_STATDEP_0,CAM_STATDEP_1" bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" rbitfld.long 0x04 6. "RESERVED," "0,1" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 3. "RESERVED," "0,1" bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP1 clock domain" "DSP1_STATDEP_0,DSP1_STATDEP_1" bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_DSP2_DYNAMICDEP,This register controls the dynamic domain depedencies from DSP domain towards 'target' domains" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.tbyte 0x08 6.--23. 1. "RESERVED," rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20++0x03 line.long 0x00 "CM_DSP2_DSP2_CLKCTRL,This register manages the DSP clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "DSP2_EDMA_TPCC" base ad:0x41510000 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x04 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x04 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" newline rbitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x04 22.--23. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x04 19. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x04 15. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x04 11. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7" group.long 0xFC++0x113 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" line.long 0x04 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x04 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x08 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x08 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x0C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x10 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x14 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x18 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x1C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" hexmask.long.tbyte 0x20 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x20 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" hexmask.long.tbyte 0x24 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x24 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" hexmask.long.tbyte 0x28 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x28 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x28 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x2C "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.tbyte 0x2C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x2C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x2C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" hexmask.long.tbyte 0x30 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x30 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x30 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" hexmask.long.tbyte 0x34 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x34 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x34 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x38 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" hexmask.long.tbyte 0x38 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x38 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x38 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x3C "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" hexmask.long.tbyte 0x3C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x3C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x3C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" hexmask.long.tbyte 0x40 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x40 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x40 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x44 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" hexmask.long.tbyte 0x44 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x44 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x44 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x48 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" hexmask.long.tbyte 0x48 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x48 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x48 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x4C "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" hexmask.long.tbyte 0x4C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x4C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" hexmask.long.tbyte 0x50 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x50 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x50 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x54 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" hexmask.long.tbyte 0x54 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x54 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x54 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x58 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" hexmask.long.tbyte 0x58 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x58 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x58 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x5C "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" hexmask.long.tbyte 0x5C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x5C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x5C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x60 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" hexmask.long.tbyte 0x60 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x60 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x60 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x64 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" hexmask.long.tbyte 0x64 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x64 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x64 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x68 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" hexmask.long.tbyte 0x68 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x68 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x68 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x6C "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" hexmask.long.tbyte 0x6C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x6C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x6C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x70 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" hexmask.long.tbyte 0x70 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x70 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x70 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x74 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" hexmask.long.tbyte 0x74 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x74 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x74 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x78 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" hexmask.long.tbyte 0x78 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x78 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x78 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x7C "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" hexmask.long.tbyte 0x7C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x7C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x7C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x80 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" hexmask.long.tbyte 0x80 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x80 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x80 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x84 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" hexmask.long.tbyte 0x84 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x84 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x84 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x88 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" hexmask.long.tbyte 0x88 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x88 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x88 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x8C "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" hexmask.long.tbyte 0x8C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x8C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x8C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x90 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" hexmask.long.tbyte 0x90 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x90 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x90 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x94 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" hexmask.long.tbyte 0x94 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x94 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x94 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x98 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" hexmask.long.tbyte 0x98 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x98 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x98 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x9C "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" hexmask.long.tbyte 0x9C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x9C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x9C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA0 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA4 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA8 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xAC "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" hexmask.long.tbyte 0xAC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xAC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xAC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB0 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB4 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB8 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xBC "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" hexmask.long.tbyte 0xBC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xBC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xBC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC0 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC4 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC8 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xCC "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" hexmask.long.tbyte 0xCC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xCC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xCC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD0 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD4 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD8 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xDC "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" hexmask.long.tbyte 0xDC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xDC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xDC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE0 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE4 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE8 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xEC "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" hexmask.long.tbyte 0xEC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xEC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xEC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF0 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF4 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF8 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xFC "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" hexmask.long.tbyte 0xFC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xFC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xFC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x100 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" hexmask.long.tbyte 0x100 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x100 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x100 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x104 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x104 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x104 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x104 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x104 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x108 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x108 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x108 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x108 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x108 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x10C "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x10C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10C 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x10C 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x10C 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x110 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x110 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x110 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x110 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x110 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x240++0x23 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x00 31. "RESERVED,Reserved" "0,1" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 27. "RESERVED,Reserved" "0,1" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 23. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Reserved" "0,1" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 15. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x04 31. "RESERVED,Reserved" "0,1" bitfld.long 0x04 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 27. "RESERVED,Reserved" "0,1" bitfld.long 0x04 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 23. "RESERVED,Reserved" "0,1" bitfld.long 0x04 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED,Reserved" "0,1" bitfld.long 0x04 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 15. "RESERVED,Reserved" "0,1" bitfld.long 0x04 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 11. "RESERVED,Reserved" "0,1" bitfld.long 0x04 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED,Reserved" "0,1" bitfld.long 0x04 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x08 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x08 31. "RESERVED,Reserved" "0,1" bitfld.long 0x08 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 27. "RESERVED,Reserved" "0,1" bitfld.long 0x08 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 23. "RESERVED,Reserved" "0,1" bitfld.long 0x08 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED,Reserved" "0,1" bitfld.long 0x08 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 15. "RESERVED,Reserved" "0,1" bitfld.long 0x08 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 11. "RESERVED,Reserved" "0,1" bitfld.long 0x08 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED,Reserved" "0,1" bitfld.long 0x08 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x0C "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x0C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x10 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x10 31. "RESERVED,Reserved" "0,1" bitfld.long 0x10 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED,Reserved" "0,1" bitfld.long 0x10 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED,Reserved" "0,1" bitfld.long 0x10 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "RESERVED,Reserved" "0,1" bitfld.long 0x10 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 15. "RESERVED,Reserved" "0,1" bitfld.long 0x10 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 11. "RESERVED,Reserved" "0,1" bitfld.long 0x10 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" bitfld.long 0x10 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 3. "RESERVED,Reserved" "0,1" bitfld.long 0x10 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x14 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x14 31. "RESERVED,Reserved" "0,1" bitfld.long 0x14 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED,Reserved" "0,1" bitfld.long 0x14 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED,Reserved" "0,1" bitfld.long 0x14 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED,Reserved" "0,1" bitfld.long 0x14 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED,Reserved" "0,1" bitfld.long 0x14 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" bitfld.long 0x14 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED,Reserved" "0,1" bitfld.long 0x14 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x18 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x18 31. "RESERVED,Reserved" "0,1" bitfld.long 0x18 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED,Reserved" "0,1" bitfld.long 0x18 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED,Reserved" "0,1" bitfld.long 0x18 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED,Reserved" "0,1" bitfld.long 0x18 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED,Reserved" "0,1" bitfld.long 0x18 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED,Reserved" "0,1" bitfld.long 0x18 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED,Reserved" "0,1" bitfld.long 0x18 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED,Reserved" "0,1" bitfld.long 0x18 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x1C "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x1C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x20 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" rbitfld.long 0x20 31. "RESERVED," "0,1" bitfld.long 0x20 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 27. "RESERVED," "0,1" bitfld.long 0x20 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 23. "RESERVED," "0,1" bitfld.long 0x20 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 19. "RESERVED," "0,1" bitfld.long 0x20 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 15. "RESERVED," "0,1" bitfld.long 0x20 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 11. "RESERVED," "0,1" bitfld.long 0x20 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 7. "RESERVED," "0,1" bitfld.long 0x20 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 3. "RESERVED," "0,1" bitfld.long 0x20 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x280++0x07 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_QUEPRI,Queue Priority" hexmask.long 0x04 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" rgroup.long 0x300++0x23 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" newline bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" newline bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" newline bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" newline bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" newline bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" newline bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" newline bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" newline bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" newline bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" newline bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" newline bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" newline bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" newline bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" newline bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" newline bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" newline bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" newline bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" newline bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" newline bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" newline bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" line.long 0x08 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1" newline bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1" bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1" newline bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1" newline bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1" bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1" newline bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1" newline bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1" bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1" newline bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1" newline bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1" bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1" newline bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1" newline bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1" bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1" newline bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1" line.long 0x0C "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1" bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1" bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1" bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1" bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1" bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1" line.long 0x10 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,Event Missed #7" "0,1" newline bitfld.long 0x10 6. "E6,Event Missed #6" "0,1" bitfld.long 0x10 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x10 4. "E4,Event Missed #4" "0,1" bitfld.long 0x10 3. "E3,Event Missed #3" "0,1" newline bitfld.long 0x10 2. "E2,Event Missed #2" "0,1" bitfld.long 0x10 1. "E1,Event Missed #1" "0,1" newline bitfld.long 0x10 0. "E0,Event Missed #0" "0,1" line.long 0x14 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1" newline bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1" newline bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1" bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1" newline bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1" line.long 0x18 "EDMA_TPCC_CCERR,CC Error Register" hexmask.long.word 0x18 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 16. "TCERR,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register" "TCERR_0,TCERR_1" newline hexmask.long.byte 0x18 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD7_0,QTHRXCD7_1" newline bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD6_0,QTHRXCD6_1" bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD5_0,QTHRXCD5_1" newline bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD4_0,QTHRXCD4_1" bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD3_0,QTHRXCD3_1" newline bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD1_0,QTHRXCD1_1" newline bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x1C "EDMA_TPCC_CCERRCLR,CC Error Clear Register" hexmask.long.word 0x1C 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR" "0,1" newline hexmask.long.byte 0x1C 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect" "0,1" bitfld.long 0x1C 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect" "0,1" bitfld.long 0x1C 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" newline bitfld.long 0x1C 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect" "0,1" bitfld.long 0x1C 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" newline bitfld.long 0x1C 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect" "0,1" line.long 0x20 "EDMA_TPCC_EEVAL,Error Eval Register" hexmask.long 0x20 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 1. "SET,Error Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x20 0. "EVAL,Error Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x348++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x350++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x358++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x360++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x368++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x370++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x378++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x344++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x34C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x354++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x35C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x364++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x36C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x374++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x37C++0x23 line.long 0x00 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" line.long 0x04 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x04 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x04 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x04 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x04 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x04 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x04 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x04 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x08 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x08 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x08 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x08 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x08 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x08 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x08 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x08 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x0C "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x0C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x0C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x0C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x0C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x0C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x0C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x0C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x10 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x10 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x10 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x10 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x10 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x10 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x10 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x10 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x14 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x14 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x14 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x14 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x14 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x14 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x14 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x14 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x18 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x18 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x18 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x18 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x18 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x18 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x18 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x18 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x1C "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x1C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x1C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x1C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x1C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x1C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x1C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x1C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x20 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x20 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x20 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x20 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x20 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x20 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x20 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x20 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" rgroup.long 0x400++0x7F line.long 0x00 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x04 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x08 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x10 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x14 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x18 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x1C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x20 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x24 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x28 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x2C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x30 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x30 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x30 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x34 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x34 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x38 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x38 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x3C "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x3C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x40 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x40 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x44 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x44 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x44 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x48 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x48 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x48 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x4C "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x4C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x4C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x50 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x50 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x50 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x54 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x54 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x54 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x54 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x58 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x58 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x58 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x58 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x5C "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x5C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x5C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x5C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x60 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x60 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x60 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x60 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x64 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x64 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x64 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x64 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x68 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x68 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x68 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x68 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x6C "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x6C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x6C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x6C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x70 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x70 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x70 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x70 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x74 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x74 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x74 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x74 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x78 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x78 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x78 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x78 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x7C "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x7C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x7C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x7C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x600++0x07 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" line.long 0x04 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" hexmask.long.byte 0x04 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" rbitfld.long 0x00 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" rbitfld.long 0x04 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,reads return 0's" rbitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" newline rbitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" rbitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" newline rbitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" rbitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" newline bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2" rbitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" newline rbitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 14.--15. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" rbitfld.long 0x00 5.--7. "RESERVED,reads return 0's" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" rbitfld.long 0x00 3. "RESERVED,reads return 0's" "0,1" newline bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.." rbitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" newline rbitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" group.long 0x700++0x0B line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" hexmask.long.tbyte 0x00 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" line.long 0x08 "EDMA_TPCC_AETCMD,AET Command" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "CLR,AET Clear commandCPU writes 0x0 has no effect" "0,1" rgroup.long 0x800++0x2F line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" line.long 0x04 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" newline rbitfld.long 0x04 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" rbitfld.long 0x04 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" newline rbitfld.long 0x04 2. "URE,User Read Error" "URE_0,URE_1" rbitfld.long 0x04 1. "UWE,User Write Error" "UWE_0,UWE_1" newline rbitfld.long 0x04 0. "UXE,User Execute Error" "UXE_0,UXE_1" line.long 0x08 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" line.long 0x0C "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x0C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x0C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x0C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x0C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x0C 10. "AID0,Allowed ID 0" "AID0_0,AID0_1" bitfld.long 0x0C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x0C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x0C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x0C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x0C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x0C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x0C 0. "UX,User Execute permission" "UX_0,UX_1" line.long 0x10 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x10 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x10 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x10 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x10 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x10 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x10 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x10 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x10 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x10 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x10 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x10 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x10 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x10 0. "UX,User Execute permission" "UX_0,?" line.long 0x14 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x14 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x14 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x14 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x14 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x14 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x14 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x14 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x14 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x14 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x14 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x14 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x14 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x14 0. "UX,User Execute permission" "UX_0,?" line.long 0x18 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x18 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x18 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x18 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x18 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x18 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x18 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x18 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x18 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x18 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x18 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x18 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x18 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x18 0. "UX,User Execute permission" "UX_0,?" line.long 0x1C "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x1C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x1C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x1C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x1C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x1C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x1C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x1C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x1C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x1C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x1C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x1C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x1C 0. "UX,User Execute permission" "UX_0,?" line.long 0x20 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x20 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x20 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x20 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x20 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x20 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x20 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x20 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x20 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x20 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x20 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x20 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x20 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x20 0. "UX,User Execute permission" "UX_0,?" line.long 0x24 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x24 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x24 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x24 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x24 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x24 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x24 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x24 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x24 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x24 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x24 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x24 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x24 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x24 0. "UX,User Execute permission" "UX_0,?" line.long 0x28 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" hexmask.long.word 0x28 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x28 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x28 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x28 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x28 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x28 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x28 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x28 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x28 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x28 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x28 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x28 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x28 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x28 0. "UX,User Execute permission" "UX_0,?" line.long 0x2C "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" hexmask.long.word 0x2C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x2C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x2C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x2C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x2C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x2C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x2C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x2C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x2C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x2C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x2C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x2C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x2C 0. "UX,User Execute permission" "UX_0,?" rgroup.long 0x1000++0x47 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" newline bitfld.long 0x04 29. "E61,Event #61" "0,1" bitfld.long 0x04 28. "E60,Event #60" "0,1" newline bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" newline bitfld.long 0x04 23. "E55,Event #55" "0,1" bitfld.long 0x04 22. "E54,Event #54" "0,1" newline bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" newline bitfld.long 0x04 17. "E49,Event #49" "0,1" bitfld.long 0x04 16. "E48,Event #48" "0,1" newline bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" newline bitfld.long 0x04 11. "E43,Event #43" "0,1" bitfld.long 0x04 10. "E42,Event #42" "0,1" newline bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" newline bitfld.long 0x04 5. "E37,Event #37" "0,1" bitfld.long 0x04 4. "E36,Event #36" "0,1" newline bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" line.long 0x08 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event #31" "0,1" bitfld.long 0x08 30. "E30,Event #30" "0,1" newline bitfld.long 0x08 29. "E29,Event #29" "0,1" bitfld.long 0x08 28. "E28,Event #28" "0,1" newline bitfld.long 0x08 27. "E27,Event #27" "0,1" bitfld.long 0x08 26. "E26,Event #26" "0,1" newline bitfld.long 0x08 25. "E25,Event #25" "0,1" bitfld.long 0x08 24. "E24,Event #24" "0,1" newline bitfld.long 0x08 23. "E23,Event #23" "0,1" bitfld.long 0x08 22. "E22,Event #22" "0,1" newline bitfld.long 0x08 21. "E21,Event #21" "0,1" bitfld.long 0x08 20. "E20,Event #20" "0,1" newline bitfld.long 0x08 19. "E19,Event #19" "0,1" bitfld.long 0x08 18. "E18,Event #18" "0,1" newline bitfld.long 0x08 17. "E17,Event #17" "0,1" bitfld.long 0x08 16. "E16,Event #16" "0,1" newline bitfld.long 0x08 15. "E15,Event #15" "0,1" bitfld.long 0x08 14. "E14,Event #14" "0,1" newline bitfld.long 0x08 13. "E13,Event #13" "0,1" bitfld.long 0x08 12. "E12,Event #12" "0,1" newline bitfld.long 0x08 11. "E11,Event #11" "0,1" bitfld.long 0x08 10. "E10,Event #10" "0,1" newline bitfld.long 0x08 9. "E9,Event #9" "0,1" bitfld.long 0x08 8. "E8,Event #8" "0,1" newline bitfld.long 0x08 7. "E7,Event #7" "0,1" bitfld.long 0x08 6. "E6,Event #6" "0,1" newline bitfld.long 0x08 5. "E5,Event #5" "0,1" bitfld.long 0x08 4. "E4,Event #4" "0,1" newline bitfld.long 0x08 3. "E3,Event #3" "0,1" bitfld.long 0x08 2. "E2,Event #2" "0,1" newline bitfld.long 0x08 1. "E1,Event #1" "0,1" bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event #63" "0,1" bitfld.long 0x0C 30. "E62,Event #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event #61" "0,1" bitfld.long 0x0C 28. "E60,Event #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event #59" "0,1" bitfld.long 0x0C 26. "E58,Event #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event #57" "0,1" bitfld.long 0x0C 24. "E56,Event #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event #55" "0,1" bitfld.long 0x0C 22. "E54,Event #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event #53" "0,1" bitfld.long 0x0C 20. "E52,Event #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event #51" "0,1" bitfld.long 0x0C 18. "E50,Event #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event #49" "0,1" bitfld.long 0x0C 16. "E48,Event #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event #47" "0,1" bitfld.long 0x0C 14. "E46,Event #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event #45" "0,1" bitfld.long 0x0C 12. "E44,Event #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event #43" "0,1" bitfld.long 0x0C 10. "E42,Event #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event #41" "0,1" bitfld.long 0x0C 8. "E40,Event #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event #39" "0,1" bitfld.long 0x0C 6. "E38,Event #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event #37" "0,1" bitfld.long 0x0C 4. "E36,Event #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event #35" "0,1" bitfld.long 0x0C 2. "E34,Event #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event #33" "0,1" bitfld.long 0x0C 0. "E32,Event #32" "0,1" line.long 0x10 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x10 31. "E31,Event #31" "0,1" bitfld.long 0x10 30. "E30,Event #30" "0,1" newline bitfld.long 0x10 29. "E29,Event #29" "0,1" bitfld.long 0x10 28. "E28,Event #28" "0,1" newline bitfld.long 0x10 27. "E27,Event #27" "0,1" bitfld.long 0x10 26. "E26,Event #26" "0,1" newline bitfld.long 0x10 25. "E25,Event #25" "0,1" bitfld.long 0x10 24. "E24,Event #24" "0,1" newline bitfld.long 0x10 23. "E23,Event #23" "0,1" bitfld.long 0x10 22. "E22,Event #22" "0,1" newline bitfld.long 0x10 21. "E21,Event #21" "0,1" bitfld.long 0x10 20. "E20,Event #20" "0,1" newline bitfld.long 0x10 19. "E19,Event #19" "0,1" bitfld.long 0x10 18. "E18,Event #18" "0,1" newline bitfld.long 0x10 17. "E17,Event #17" "0,1" bitfld.long 0x10 16. "E16,Event #16" "0,1" newline bitfld.long 0x10 15. "E15,Event #15" "0,1" bitfld.long 0x10 14. "E14,Event #14" "0,1" newline bitfld.long 0x10 13. "E13,Event #13" "0,1" bitfld.long 0x10 12. "E12,Event #12" "0,1" newline bitfld.long 0x10 11. "E11,Event #11" "0,1" bitfld.long 0x10 10. "E10,Event #10" "0,1" newline bitfld.long 0x10 9. "E9,Event #9" "0,1" bitfld.long 0x10 8. "E8,Event #8" "0,1" newline bitfld.long 0x10 7. "E7,Event #7" "0,1" bitfld.long 0x10 6. "E6,Event #6" "0,1" newline bitfld.long 0x10 5. "E5,Event #5" "0,1" bitfld.long 0x10 4. "E4,Event #4" "0,1" newline bitfld.long 0x10 3. "E3,Event #3" "0,1" bitfld.long 0x10 2. "E2,Event #2" "0,1" newline bitfld.long 0x10 1. "E1,Event #1" "0,1" bitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x14 31. "E63,Event #63" "0,1" bitfld.long 0x14 30. "E62,Event #62" "0,1" newline bitfld.long 0x14 29. "E61,Event #61" "0,1" bitfld.long 0x14 28. "E60,Event #60" "0,1" newline bitfld.long 0x14 27. "E59,Event #59" "0,1" bitfld.long 0x14 26. "E58,Event #58" "0,1" newline bitfld.long 0x14 25. "E57,Event #57" "0,1" bitfld.long 0x14 24. "E56,Event #56" "0,1" newline bitfld.long 0x14 23. "E55,Event #55" "0,1" bitfld.long 0x14 22. "E54,Event #54" "0,1" newline bitfld.long 0x14 21. "E53,Event #53" "0,1" bitfld.long 0x14 20. "E52,Event #52" "0,1" newline bitfld.long 0x14 19. "E51,Event #51" "0,1" bitfld.long 0x14 18. "E50,Event #50" "0,1" newline bitfld.long 0x14 17. "E49,Event #49" "0,1" bitfld.long 0x14 16. "E48,Event #48" "0,1" newline bitfld.long 0x14 15. "E47,Event #47" "0,1" bitfld.long 0x14 14. "E46,Event #46" "0,1" newline bitfld.long 0x14 13. "E45,Event #45" "0,1" bitfld.long 0x14 12. "E44,Event #44" "0,1" newline bitfld.long 0x14 11. "E43,Event #43" "0,1" bitfld.long 0x14 10. "E42,Event #42" "0,1" newline bitfld.long 0x14 9. "E41,Event #41" "0,1" bitfld.long 0x14 8. "E40,Event #40" "0,1" newline bitfld.long 0x14 7. "E39,Event #39" "0,1" bitfld.long 0x14 6. "E38,Event #38" "0,1" newline bitfld.long 0x14 5. "E37,Event #37" "0,1" bitfld.long 0x14 4. "E36,Event #36" "0,1" newline bitfld.long 0x14 3. "E35,Event #35" "0,1" bitfld.long 0x14 2. "E34,Event #34" "0,1" newline bitfld.long 0x14 1. "E33,Event #33" "0,1" bitfld.long 0x14 0. "E32,Event #32" "0,1" line.long 0x18 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x18 31. "E31,Event #31" "0,1" bitfld.long 0x18 30. "E30,Event #30" "0,1" newline bitfld.long 0x18 29. "E29,Event #29" "0,1" bitfld.long 0x18 28. "E28,Event #28" "0,1" newline bitfld.long 0x18 27. "E27,Event #27" "0,1" bitfld.long 0x18 26. "E26,Event #26" "0,1" newline bitfld.long 0x18 25. "E25,Event #25" "0,1" bitfld.long 0x18 24. "E24,Event #24" "0,1" newline bitfld.long 0x18 23. "E23,Event #23" "0,1" bitfld.long 0x18 22. "E22,Event #22" "0,1" newline bitfld.long 0x18 21. "E21,Event #21" "0,1" bitfld.long 0x18 20. "E20,Event #20" "0,1" newline bitfld.long 0x18 19. "E19,Event #19" "0,1" bitfld.long 0x18 18. "E18,Event #18" "0,1" newline bitfld.long 0x18 17. "E17,Event #17" "0,1" bitfld.long 0x18 16. "E16,Event #16" "0,1" newline bitfld.long 0x18 15. "E15,Event #15" "0,1" bitfld.long 0x18 14. "E14,Event #14" "0,1" newline bitfld.long 0x18 13. "E13,Event #13" "0,1" bitfld.long 0x18 12. "E12,Event #12" "0,1" newline bitfld.long 0x18 11. "E11,Event #11" "0,1" bitfld.long 0x18 10. "E10,Event #10" "0,1" newline bitfld.long 0x18 9. "E9,Event #9" "0,1" bitfld.long 0x18 8. "E8,Event #8" "0,1" newline bitfld.long 0x18 7. "E7,Event #7" "0,1" bitfld.long 0x18 6. "E6,Event #6" "0,1" newline bitfld.long 0x18 5. "E5,Event #5" "0,1" bitfld.long 0x18 4. "E4,Event #4" "0,1" newline bitfld.long 0x18 3. "E3,Event #3" "0,1" bitfld.long 0x18 2. "E2,Event #2" "0,1" newline bitfld.long 0x18 1. "E1,Event #1" "0,1" bitfld.long 0x18 0. "E0,Event #0" "0,1" line.long 0x1C "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x1C 31. "E63,Event #63" "0,1" bitfld.long 0x1C 30. "E62,Event #62" "0,1" newline bitfld.long 0x1C 29. "E61,Event #61" "0,1" bitfld.long 0x1C 28. "E60,Event #60" "0,1" newline bitfld.long 0x1C 27. "E59,Event #59" "0,1" bitfld.long 0x1C 26. "E58,Event #58" "0,1" newline bitfld.long 0x1C 25. "E57,Event #57" "0,1" bitfld.long 0x1C 24. "E56,Event #56" "0,1" newline bitfld.long 0x1C 23. "E55,Event #55" "0,1" bitfld.long 0x1C 22. "E54,Event #54" "0,1" newline bitfld.long 0x1C 21. "E53,Event #53" "0,1" bitfld.long 0x1C 20. "E52,Event #52" "0,1" newline bitfld.long 0x1C 19. "E51,Event #51" "0,1" bitfld.long 0x1C 18. "E50,Event #50" "0,1" newline bitfld.long 0x1C 17. "E49,Event #49" "0,1" bitfld.long 0x1C 16. "E48,Event #48" "0,1" newline bitfld.long 0x1C 15. "E47,Event #47" "0,1" bitfld.long 0x1C 14. "E46,Event #46" "0,1" newline bitfld.long 0x1C 13. "E45,Event #45" "0,1" bitfld.long 0x1C 12. "E44,Event #44" "0,1" newline bitfld.long 0x1C 11. "E43,Event #43" "0,1" bitfld.long 0x1C 10. "E42,Event #42" "0,1" newline bitfld.long 0x1C 9. "E41,Event #41" "0,1" bitfld.long 0x1C 8. "E40,Event #40" "0,1" newline bitfld.long 0x1C 7. "E39,Event #39" "0,1" bitfld.long 0x1C 6. "E38,Event #38" "0,1" newline bitfld.long 0x1C 5. "E37,Event #37" "0,1" bitfld.long 0x1C 4. "E36,Event #36" "0,1" newline bitfld.long 0x1C 3. "E35,Event #35" "0,1" bitfld.long 0x1C 2. "E34,Event #34" "0,1" newline bitfld.long 0x1C 1. "E33,Event #33" "0,1" bitfld.long 0x1C 0. "E32,Event #32" "0,1" line.long 0x20 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x20 31. "E31,Event #31" "0,1" bitfld.long 0x20 30. "E30,Event #30" "0,1" newline bitfld.long 0x20 29. "E29,Event #29" "0,1" bitfld.long 0x20 28. "E28,Event #28" "0,1" newline bitfld.long 0x20 27. "E27,Event #27" "0,1" bitfld.long 0x20 26. "E26,Event #26" "0,1" newline bitfld.long 0x20 25. "E25,Event #25" "0,1" bitfld.long 0x20 24. "E24,Event #24" "0,1" newline bitfld.long 0x20 23. "E23,Event #23" "0,1" bitfld.long 0x20 22. "E22,Event #22" "0,1" newline bitfld.long 0x20 21. "E21,Event #21" "0,1" bitfld.long 0x20 20. "E20,Event #20" "0,1" newline bitfld.long 0x20 19. "E19,Event #19" "0,1" bitfld.long 0x20 18. "E18,Event #18" "0,1" newline bitfld.long 0x20 17. "E17,Event #17" "0,1" bitfld.long 0x20 16. "E16,Event #16" "0,1" newline bitfld.long 0x20 15. "E15,Event #15" "0,1" bitfld.long 0x20 14. "E14,Event #14" "0,1" newline bitfld.long 0x20 13. "E13,Event #13" "0,1" bitfld.long 0x20 12. "E12,Event #12" "0,1" newline bitfld.long 0x20 11. "E11,Event #11" "0,1" bitfld.long 0x20 10. "E10,Event #10" "0,1" newline bitfld.long 0x20 9. "E9,Event #9" "0,1" bitfld.long 0x20 8. "E8,Event #8" "0,1" newline bitfld.long 0x20 7. "E7,Event #7" "0,1" bitfld.long 0x20 6. "E6,Event #6" "0,1" newline bitfld.long 0x20 5. "E5,Event #5" "0,1" bitfld.long 0x20 4. "E4,Event #4" "0,1" newline bitfld.long 0x20 3. "E3,Event #3" "0,1" bitfld.long 0x20 2. "E2,Event #2" "0,1" newline bitfld.long 0x20 1. "E1,Event #1" "0,1" bitfld.long 0x20 0. "E0,Event #0" "0,1" line.long 0x24 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x24 31. "E63,Event #63" "0,1" bitfld.long 0x24 30. "E62,Event #62" "0,1" newline bitfld.long 0x24 29. "E61,Event #61" "0,1" bitfld.long 0x24 28. "E60,Event #60" "0,1" newline bitfld.long 0x24 27. "E59,Event #59" "0,1" bitfld.long 0x24 26. "E58,Event #58" "0,1" newline bitfld.long 0x24 25. "E57,Event #57" "0,1" bitfld.long 0x24 24. "E56,Event #56" "0,1" newline bitfld.long 0x24 23. "E55,Event #55" "0,1" bitfld.long 0x24 22. "E54,Event #54" "0,1" newline bitfld.long 0x24 21. "E53,Event #53" "0,1" bitfld.long 0x24 20. "E52,Event #52" "0,1" newline bitfld.long 0x24 19. "E51,Event #51" "0,1" bitfld.long 0x24 18. "E50,Event #50" "0,1" newline bitfld.long 0x24 17. "E49,Event #49" "0,1" bitfld.long 0x24 16. "E48,Event #48" "0,1" newline bitfld.long 0x24 15. "E47,Event #47" "0,1" bitfld.long 0x24 14. "E46,Event #46" "0,1" newline bitfld.long 0x24 13. "E45,Event #45" "0,1" bitfld.long 0x24 12. "E44,Event #44" "0,1" newline bitfld.long 0x24 11. "E43,Event #43" "0,1" bitfld.long 0x24 10. "E42,Event #42" "0,1" newline bitfld.long 0x24 9. "E41,Event #41" "0,1" bitfld.long 0x24 8. "E40,Event #40" "0,1" newline bitfld.long 0x24 7. "E39,Event #39" "0,1" bitfld.long 0x24 6. "E38,Event #38" "0,1" newline bitfld.long 0x24 5. "E37,Event #37" "0,1" bitfld.long 0x24 4. "E36,Event #36" "0,1" newline bitfld.long 0x24 3. "E35,Event #35" "0,1" bitfld.long 0x24 2. "E34,Event #34" "0,1" newline bitfld.long 0x24 1. "E33,Event #33" "0,1" bitfld.long 0x24 0. "E32,Event #32" "0,1" line.long 0x28 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x28 31. "E31,Event #31" "0,1" bitfld.long 0x28 30. "E30,Event #30" "0,1" newline bitfld.long 0x28 29. "E29,Event #29" "0,1" bitfld.long 0x28 28. "E28,Event #28" "0,1" newline bitfld.long 0x28 27. "E27,Event #27" "0,1" bitfld.long 0x28 26. "E26,Event #26" "0,1" newline bitfld.long 0x28 25. "E25,Event #25" "0,1" bitfld.long 0x28 24. "E24,Event #24" "0,1" newline bitfld.long 0x28 23. "E23,Event #23" "0,1" bitfld.long 0x28 22. "E22,Event #22" "0,1" newline bitfld.long 0x28 21. "E21,Event #21" "0,1" bitfld.long 0x28 20. "E20,Event #20" "0,1" newline bitfld.long 0x28 19. "E19,Event #19" "0,1" bitfld.long 0x28 18. "E18,Event #18" "0,1" newline bitfld.long 0x28 17. "E17,Event #17" "0,1" bitfld.long 0x28 16. "E16,Event #16" "0,1" newline bitfld.long 0x28 15. "E15,Event #15" "0,1" bitfld.long 0x28 14. "E14,Event #14" "0,1" newline bitfld.long 0x28 13. "E13,Event #13" "0,1" bitfld.long 0x28 12. "E12,Event #12" "0,1" newline bitfld.long 0x28 11. "E11,Event #11" "0,1" bitfld.long 0x28 10. "E10,Event #10" "0,1" newline bitfld.long 0x28 9. "E9,Event #9" "0,1" bitfld.long 0x28 8. "E8,Event #8" "0,1" newline bitfld.long 0x28 7. "E7,Event #7" "0,1" bitfld.long 0x28 6. "E6,Event #6" "0,1" newline bitfld.long 0x28 5. "E5,Event #5" "0,1" bitfld.long 0x28 4. "E4,Event #4" "0,1" newline bitfld.long 0x28 3. "E3,Event #3" "0,1" bitfld.long 0x28 2. "E2,Event #2" "0,1" newline bitfld.long 0x28 1. "E1,Event #1" "0,1" bitfld.long 0x28 0. "E0,Event #0" "0,1" line.long 0x2C "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x2C 31. "E63,Event #63" "0,1" bitfld.long 0x2C 30. "E62,Event #62" "0,1" newline bitfld.long 0x2C 29. "E61,Event #61" "0,1" bitfld.long 0x2C 28. "E60,Event #60" "0,1" newline bitfld.long 0x2C 27. "E59,Event #59" "0,1" bitfld.long 0x2C 26. "E58,Event #58" "0,1" newline bitfld.long 0x2C 25. "E57,Event #57" "0,1" bitfld.long 0x2C 24. "E56,Event #56" "0,1" newline bitfld.long 0x2C 23. "E55,Event #55" "0,1" bitfld.long 0x2C 22. "E54,Event #54" "0,1" newline bitfld.long 0x2C 21. "E53,Event #53" "0,1" bitfld.long 0x2C 20. "E52,Event #52" "0,1" newline bitfld.long 0x2C 19. "E51,Event #51" "0,1" bitfld.long 0x2C 18. "E50,Event #50" "0,1" newline bitfld.long 0x2C 17. "E49,Event #49" "0,1" bitfld.long 0x2C 16. "E48,Event #48" "0,1" newline bitfld.long 0x2C 15. "E47,Event #47" "0,1" bitfld.long 0x2C 14. "E46,Event #46" "0,1" newline bitfld.long 0x2C 13. "E45,Event #45" "0,1" bitfld.long 0x2C 12. "E44,Event #44" "0,1" newline bitfld.long 0x2C 11. "E43,Event #43" "0,1" bitfld.long 0x2C 10. "E42,Event #42" "0,1" newline bitfld.long 0x2C 9. "E41,Event #41" "0,1" bitfld.long 0x2C 8. "E40,Event #40" "0,1" newline bitfld.long 0x2C 7. "E39,Event #39" "0,1" bitfld.long 0x2C 6. "E38,Event #38" "0,1" newline bitfld.long 0x2C 5. "E37,Event #37" "0,1" bitfld.long 0x2C 4. "E36,Event #36" "0,1" newline bitfld.long 0x2C 3. "E35,Event #35" "0,1" bitfld.long 0x2C 2. "E34,Event #34" "0,1" newline bitfld.long 0x2C 1. "E33,Event #33" "0,1" bitfld.long 0x2C 0. "E32,Event #32" "0,1" line.long 0x30 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x30 31. "E31,Event #31" "0,1" bitfld.long 0x30 30. "E30,Event #30" "0,1" newline bitfld.long 0x30 29. "E29,Event #29" "0,1" bitfld.long 0x30 28. "E28,Event #28" "0,1" newline bitfld.long 0x30 27. "E27,Event #27" "0,1" bitfld.long 0x30 26. "E26,Event #26" "0,1" newline bitfld.long 0x30 25. "E25,Event #25" "0,1" bitfld.long 0x30 24. "E24,Event #24" "0,1" newline bitfld.long 0x30 23. "E23,Event #23" "0,1" bitfld.long 0x30 22. "E22,Event #22" "0,1" newline bitfld.long 0x30 21. "E21,Event #21" "0,1" bitfld.long 0x30 20. "E20,Event #20" "0,1" newline bitfld.long 0x30 19. "E19,Event #19" "0,1" bitfld.long 0x30 18. "E18,Event #18" "0,1" newline bitfld.long 0x30 17. "E17,Event #17" "0,1" bitfld.long 0x30 16. "E16,Event #16" "0,1" newline bitfld.long 0x30 15. "E15,Event #15" "0,1" bitfld.long 0x30 14. "E14,Event #14" "0,1" newline bitfld.long 0x30 13. "E13,Event #13" "0,1" bitfld.long 0x30 12. "E12,Event #12" "0,1" newline bitfld.long 0x30 11. "E11,Event #11" "0,1" bitfld.long 0x30 10. "E10,Event #10" "0,1" newline bitfld.long 0x30 9. "E9,Event #9" "0,1" bitfld.long 0x30 8. "E8,Event #8" "0,1" newline bitfld.long 0x30 7. "E7,Event #7" "0,1" bitfld.long 0x30 6. "E6,Event #6" "0,1" newline bitfld.long 0x30 5. "E5,Event #5" "0,1" bitfld.long 0x30 4. "E4,Event #4" "0,1" newline bitfld.long 0x30 3. "E3,Event #3" "0,1" bitfld.long 0x30 2. "E2,Event #2" "0,1" newline bitfld.long 0x30 1. "E1,Event #1" "0,1" bitfld.long 0x30 0. "E0,Event #0" "0,1" line.long 0x34 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x34 31. "E63,Event #63" "0,1" bitfld.long 0x34 30. "E62,Event #62" "0,1" newline bitfld.long 0x34 29. "E61,Event #61" "0,1" bitfld.long 0x34 28. "E60,Event #60" "0,1" newline bitfld.long 0x34 27. "E59,Event #59" "0,1" bitfld.long 0x34 26. "E58,Event #58" "0,1" newline bitfld.long 0x34 25. "E57,Event #57" "0,1" bitfld.long 0x34 24. "E56,Event #56" "0,1" newline bitfld.long 0x34 23. "E55,Event #55" "0,1" bitfld.long 0x34 22. "E54,Event #54" "0,1" newline bitfld.long 0x34 21. "E53,Event #53" "0,1" bitfld.long 0x34 20. "E52,Event #52" "0,1" newline bitfld.long 0x34 19. "E51,Event #51" "0,1" bitfld.long 0x34 18. "E50,Event #50" "0,1" newline bitfld.long 0x34 17. "E49,Event #49" "0,1" bitfld.long 0x34 16. "E48,Event #48" "0,1" newline bitfld.long 0x34 15. "E47,Event #47" "0,1" bitfld.long 0x34 14. "E46,Event #46" "0,1" newline bitfld.long 0x34 13. "E45,Event #45" "0,1" bitfld.long 0x34 12. "E44,Event #44" "0,1" newline bitfld.long 0x34 11. "E43,Event #43" "0,1" bitfld.long 0x34 10. "E42,Event #42" "0,1" newline bitfld.long 0x34 9. "E41,Event #41" "0,1" bitfld.long 0x34 8. "E40,Event #40" "0,1" newline bitfld.long 0x34 7. "E39,Event #39" "0,1" bitfld.long 0x34 6. "E38,Event #38" "0,1" newline bitfld.long 0x34 5. "E37,Event #37" "0,1" bitfld.long 0x34 4. "E36,Event #36" "0,1" newline bitfld.long 0x34 3. "E35,Event #35" "0,1" bitfld.long 0x34 2. "E34,Event #34" "0,1" newline bitfld.long 0x34 1. "E33,Event #33" "0,1" bitfld.long 0x34 0. "E32,Event #32" "0,1" line.long 0x38 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x38 31. "E31,Event #31" "0,1" bitfld.long 0x38 30. "E30,Event #30" "0,1" newline bitfld.long 0x38 29. "E29,Event #29" "0,1" bitfld.long 0x38 28. "E28,Event #28" "0,1" newline bitfld.long 0x38 27. "E27,Event #27" "0,1" bitfld.long 0x38 26. "E26,Event #26" "0,1" newline bitfld.long 0x38 25. "E25,Event #25" "0,1" bitfld.long 0x38 24. "E24,Event #24" "0,1" newline bitfld.long 0x38 23. "E23,Event #23" "0,1" bitfld.long 0x38 22. "E22,Event #22" "0,1" newline bitfld.long 0x38 21. "E21,Event #21" "0,1" bitfld.long 0x38 20. "E20,Event #20" "0,1" newline bitfld.long 0x38 19. "E19,Event #19" "0,1" bitfld.long 0x38 18. "E18,Event #18" "0,1" newline bitfld.long 0x38 17. "E17,Event #17" "0,1" bitfld.long 0x38 16. "E16,Event #16" "0,1" newline bitfld.long 0x38 15. "E15,Event #15" "0,1" bitfld.long 0x38 14. "E14,Event #14" "0,1" newline bitfld.long 0x38 13. "E13,Event #13" "0,1" bitfld.long 0x38 12. "E12,Event #12" "0,1" newline bitfld.long 0x38 11. "E11,Event #11" "0,1" bitfld.long 0x38 10. "E10,Event #10" "0,1" newline bitfld.long 0x38 9. "E9,Event #9" "0,1" bitfld.long 0x38 8. "E8,Event #8" "0,1" newline bitfld.long 0x38 7. "E7,Event #7" "0,1" bitfld.long 0x38 6. "E6,Event #6" "0,1" newline bitfld.long 0x38 5. "E5,Event #5" "0,1" bitfld.long 0x38 4. "E4,Event #4" "0,1" newline bitfld.long 0x38 3. "E3,Event #3" "0,1" bitfld.long 0x38 2. "E2,Event #2" "0,1" newline bitfld.long 0x38 1. "E1,Event #1" "0,1" bitfld.long 0x38 0. "E0,Event #0" "0,1" line.long 0x3C "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x3C 31. "E63,Event #63" "0,1" bitfld.long 0x3C 30. "E62,Event #62" "0,1" newline bitfld.long 0x3C 29. "E61,Event #61" "0,1" bitfld.long 0x3C 28. "E60,Event #60" "0,1" newline bitfld.long 0x3C 27. "E59,Event #59" "0,1" bitfld.long 0x3C 26. "E58,Event #58" "0,1" newline bitfld.long 0x3C 25. "E57,Event #57" "0,1" bitfld.long 0x3C 24. "E56,Event #56" "0,1" newline bitfld.long 0x3C 23. "E55,Event #55" "0,1" bitfld.long 0x3C 22. "E54,Event #54" "0,1" newline bitfld.long 0x3C 21. "E53,Event #53" "0,1" bitfld.long 0x3C 20. "E52,Event #52" "0,1" newline bitfld.long 0x3C 19. "E51,Event #51" "0,1" bitfld.long 0x3C 18. "E50,Event #50" "0,1" newline bitfld.long 0x3C 17. "E49,Event #49" "0,1" bitfld.long 0x3C 16. "E48,Event #48" "0,1" newline bitfld.long 0x3C 15. "E47,Event #47" "0,1" bitfld.long 0x3C 14. "E46,Event #46" "0,1" newline bitfld.long 0x3C 13. "E45,Event #45" "0,1" bitfld.long 0x3C 12. "E44,Event #44" "0,1" newline bitfld.long 0x3C 11. "E43,Event #43" "0,1" bitfld.long 0x3C 10. "E42,Event #42" "0,1" newline bitfld.long 0x3C 9. "E41,Event #41" "0,1" bitfld.long 0x3C 8. "E40,Event #40" "0,1" newline bitfld.long 0x3C 7. "E39,Event #39" "0,1" bitfld.long 0x3C 6. "E38,Event #38" "0,1" newline bitfld.long 0x3C 5. "E37,Event #37" "0,1" bitfld.long 0x3C 4. "E36,Event #36" "0,1" newline bitfld.long 0x3C 3. "E35,Event #35" "0,1" bitfld.long 0x3C 2. "E34,Event #34" "0,1" newline bitfld.long 0x3C 1. "E33,Event #33" "0,1" bitfld.long 0x3C 0. "E32,Event #32" "0,1" line.long 0x40 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x40 31. "E31,Event #31" "0,1" bitfld.long 0x40 30. "E30,Event #30" "0,1" newline bitfld.long 0x40 29. "E29,Event #29" "0,1" bitfld.long 0x40 28. "E28,Event #28" "0,1" newline bitfld.long 0x40 27. "E27,Event #27" "0,1" bitfld.long 0x40 26. "E26,Event #26" "0,1" newline bitfld.long 0x40 25. "E25,Event #25" "0,1" bitfld.long 0x40 24. "E24,Event #24" "0,1" newline bitfld.long 0x40 23. "E23,Event #23" "0,1" bitfld.long 0x40 22. "E22,Event #22" "0,1" newline bitfld.long 0x40 21. "E21,Event #21" "0,1" bitfld.long 0x40 20. "E20,Event #20" "0,1" newline bitfld.long 0x40 19. "E19,Event #19" "0,1" bitfld.long 0x40 18. "E18,Event #18" "0,1" newline bitfld.long 0x40 17. "E17,Event #17" "0,1" bitfld.long 0x40 16. "E16,Event #16" "0,1" newline bitfld.long 0x40 15. "E15,Event #15" "0,1" bitfld.long 0x40 14. "E14,Event #14" "0,1" newline bitfld.long 0x40 13. "E13,Event #13" "0,1" bitfld.long 0x40 12. "E12,Event #12" "0,1" newline bitfld.long 0x40 11. "E11,Event #11" "0,1" bitfld.long 0x40 10. "E10,Event #10" "0,1" newline bitfld.long 0x40 9. "E9,Event #9" "0,1" bitfld.long 0x40 8. "E8,Event #8" "0,1" newline bitfld.long 0x40 7. "E7,Event #7" "0,1" bitfld.long 0x40 6. "E6,Event #6" "0,1" newline bitfld.long 0x40 5. "E5,Event #5" "0,1" bitfld.long 0x40 4. "E4,Event #4" "0,1" newline bitfld.long 0x40 3. "E3,Event #3" "0,1" bitfld.long 0x40 2. "E2,Event #2" "0,1" newline bitfld.long 0x40 1. "E1,Event #1" "0,1" bitfld.long 0x40 0. "E0,Event #0" "0,1" line.long 0x44 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x44 31. "E63,Event #63" "0,1" bitfld.long 0x44 30. "E62,Event #62" "0,1" newline bitfld.long 0x44 29. "E61,Event #61" "0,1" bitfld.long 0x44 28. "E60,Event #60" "0,1" newline bitfld.long 0x44 27. "E59,Event #59" "0,1" bitfld.long 0x44 26. "E58,Event #58" "0,1" newline bitfld.long 0x44 25. "E57,Event #57" "0,1" bitfld.long 0x44 24. "E56,Event #56" "0,1" newline bitfld.long 0x44 23. "E55,Event #55" "0,1" bitfld.long 0x44 22. "E54,Event #54" "0,1" newline bitfld.long 0x44 21. "E53,Event #53" "0,1" bitfld.long 0x44 20. "E52,Event #52" "0,1" newline bitfld.long 0x44 19. "E51,Event #51" "0,1" bitfld.long 0x44 18. "E50,Event #50" "0,1" newline bitfld.long 0x44 17. "E49,Event #49" "0,1" bitfld.long 0x44 16. "E48,Event #48" "0,1" newline bitfld.long 0x44 15. "E47,Event #47" "0,1" bitfld.long 0x44 14. "E46,Event #46" "0,1" newline bitfld.long 0x44 13. "E45,Event #45" "0,1" bitfld.long 0x44 12. "E44,Event #44" "0,1" newline bitfld.long 0x44 11. "E43,Event #43" "0,1" bitfld.long 0x44 10. "E42,Event #42" "0,1" newline bitfld.long 0x44 9. "E41,Event #41" "0,1" bitfld.long 0x44 8. "E40,Event #40" "0,1" newline bitfld.long 0x44 7. "E39,Event #39" "0,1" bitfld.long 0x44 6. "E38,Event #38" "0,1" newline bitfld.long 0x44 5. "E37,Event #37" "0,1" bitfld.long 0x44 4. "E36,Event #36" "0,1" newline bitfld.long 0x44 3. "E35,Event #35" "0,1" bitfld.long 0x44 2. "E34,Event #34" "0,1" newline bitfld.long 0x44 1. "E33,Event #33" "0,1" bitfld.long 0x44 0. "E32,Event #32" "0,1" rgroup.long 0x1050++0x2B line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x08 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x0C "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x10 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x14 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x18 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x1C "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x20 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x24 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x28 "EDMA_TPCC_IEVAL,Interrupt Eval Register" hexmask.long 0x28 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" newline bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1080++0x17 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 7. "E7,Event #7" "0,1" newline rbitfld.long 0x04 6. "E6,Event #6" "0,1" rbitfld.long 0x04 5. "E5,Event #5" "0,1" newline rbitfld.long 0x04 4. "E4,Event #4" "0,1" rbitfld.long 0x04 3. "E3,Event #3" "0,1" newline rbitfld.long 0x04 2. "E2,Event #2" "0,1" rbitfld.long 0x04 1. "E1,Event #1" "0,1" newline rbitfld.long 0x04 0. "E0,Event #0" "0,1" line.long 0x08 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,Event #7" "0,1" newline bitfld.long 0x08 6. "E6,Event #6" "0,1" bitfld.long 0x08 5. "E5,Event #5" "0,1" newline bitfld.long 0x08 4. "E4,Event #4" "0,1" bitfld.long 0x08 3. "E3,Event #3" "0,1" newline bitfld.long 0x08 2. "E2,Event #2" "0,1" bitfld.long 0x08 1. "E1,Event #1" "0,1" newline bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,Event #7" "0,1" newline bitfld.long 0x0C 6. "E6,Event #6" "0,1" bitfld.long 0x0C 5. "E5,Event #5" "0,1" newline bitfld.long 0x0C 4. "E4,Event #4" "0,1" bitfld.long 0x0C 3. "E3,Event #3" "0,1" newline bitfld.long 0x0C 2. "E2,Event #2" "0,1" bitfld.long 0x0C 1. "E1,Event #1" "0,1" newline bitfld.long 0x0C 0. "E0,Event #0" "0,1" line.long 0x10 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 7. "E7,Event #7" "0,1" newline rbitfld.long 0x10 6. "E6,Event #6" "0,1" rbitfld.long 0x10 5. "E5,Event #5" "0,1" newline rbitfld.long 0x10 4. "E4,Event #4" "0,1" rbitfld.long 0x10 3. "E3,Event #3" "0,1" newline rbitfld.long 0x10 2. "E2,Event #2" "0,1" rbitfld.long 0x10 1. "E1,Event #1" "0,1" newline rbitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event #7" "0,1" newline bitfld.long 0x14 6. "E6,Event #6" "0,1" bitfld.long 0x14 5. "E5,Event #5" "0,1" newline bitfld.long 0x14 4. "E4,Event #4" "0,1" bitfld.long 0x14 3. "E3,Event #3" "0,1" newline bitfld.long 0x14 2. "E2,Event #2" "0,1" bitfld.long 0x14 1. "E1,Event #1" "0,1" newline bitfld.long 0x14 0. "E0,Event #0" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2200++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2600++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2204++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2604++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2208++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2608++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x220C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x260C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2210++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2610++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2214++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2614++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2218++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2618++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x221C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x261C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2220++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2620++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2224++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2624++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2228++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2628++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x222C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x262C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2230++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2630++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2234++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2634++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2238++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2638++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x223C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x263C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2240++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2640++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2244++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2644++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2250++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2650++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2254++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2654++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2258++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2658++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x225C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x265C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2260++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2660++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2264++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2664++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2268++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2668++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x226C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x266C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2270++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2670++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2274++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2674++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2278++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2678++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2A78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2C78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2E78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2280++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2680++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2284++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2684++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2288++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2688++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x228C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x268C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2290++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2690++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2294++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2694++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4020++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_1,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4060++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_3,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_5,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_6,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_7,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4100++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_8,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4120++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_9,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4140++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4160++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_11,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4180++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_12,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_13,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_14,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_15,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4200++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4220++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_17,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4240++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_18,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4260++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_19,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4280++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_20,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_21,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_22,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_23,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4300++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_24,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4320++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_25,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4340++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_26,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4360++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_27,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4380++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_28,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_29,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_30,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_31,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4400++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4420++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_33,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4440++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_34,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4460++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_35,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4480++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_36,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_37,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_38,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_39,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4500++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_40,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4520++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_41,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4540++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_42,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4560++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_43,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4580++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_44,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_45,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_46,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_47,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4600++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4620++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_49,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4640++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_50,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4660++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_51,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4680++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_52,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_53,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_54,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_55,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4700++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_56,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4720++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_57,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4740++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_58,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4760++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_59,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4780++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_60,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_61,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_62,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_63,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4800++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4820++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_65,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4840++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_66,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4860++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_67,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4880++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_68,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_69,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_70,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_71,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4900++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_72,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4920++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_73,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4940++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_74,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4960++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_75,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4980++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_76,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_77,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_78,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_79,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_81,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_82,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_83,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_84,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_85,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_86,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_87,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_88,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_89,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_90,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_91,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_92,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_93,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_94,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_95,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_96,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_97,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_98,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_99,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_101,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_102,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_103,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_104,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_105,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_106,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_107,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_108,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_109,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_110,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_111,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_113,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_114,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_115,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_116,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_117,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_118,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_119,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_120,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_121,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_122,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_123,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_124,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_125,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_126,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_127,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" group.long 0x4024++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_1,Source Address" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" group.long 0x4064++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_3,Source Address" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" group.long 0x40A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_5,Source Address" group.long 0x40C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_6,Source Address" group.long 0x40E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_7,Source Address" group.long 0x4104++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_8,Source Address" group.long 0x4124++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_9,Source Address" group.long 0x4144++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_10,Source Address" group.long 0x4164++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_11,Source Address" group.long 0x4184++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_12,Source Address" group.long 0x41A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_13,Source Address" group.long 0x41C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_14,Source Address" group.long 0x41E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_15,Source Address" group.long 0x4204++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_16,Source Address" group.long 0x4224++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_17,Source Address" group.long 0x4244++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_18,Source Address" group.long 0x4264++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_19,Source Address" group.long 0x4284++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_20,Source Address" group.long 0x42A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_21,Source Address" group.long 0x42C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_22,Source Address" group.long 0x42E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_23,Source Address" group.long 0x4304++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_24,Source Address" group.long 0x4324++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_25,Source Address" group.long 0x4344++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_26,Source Address" group.long 0x4364++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_27,Source Address" group.long 0x4384++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_28,Source Address" group.long 0x43A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_29,Source Address" group.long 0x43C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_30,Source Address" group.long 0x43E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_31,Source Address" group.long 0x4404++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_32,Source Address" group.long 0x4424++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_33,Source Address" group.long 0x4444++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_34,Source Address" group.long 0x4464++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_35,Source Address" group.long 0x4484++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_36,Source Address" group.long 0x44A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_37,Source Address" group.long 0x44C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_38,Source Address" group.long 0x44E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_39,Source Address" group.long 0x4504++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_40,Source Address" group.long 0x4524++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_41,Source Address" group.long 0x4544++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_42,Source Address" group.long 0x4564++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_43,Source Address" group.long 0x4584++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_44,Source Address" group.long 0x45A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_45,Source Address" group.long 0x45C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_46,Source Address" group.long 0x45E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_47,Source Address" group.long 0x4604++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_48,Source Address" group.long 0x4624++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_49,Source Address" group.long 0x4644++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_50,Source Address" group.long 0x4664++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_51,Source Address" group.long 0x4684++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_52,Source Address" group.long 0x46A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_53,Source Address" group.long 0x46C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_54,Source Address" group.long 0x46E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_55,Source Address" group.long 0x4704++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_56,Source Address" group.long 0x4724++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_57,Source Address" group.long 0x4744++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_58,Source Address" group.long 0x4764++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_59,Source Address" group.long 0x4784++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_60,Source Address" group.long 0x47A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_61,Source Address" group.long 0x47C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_62,Source Address" group.long 0x47E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_63,Source Address" group.long 0x4804++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_64,Source Address" group.long 0x4824++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_65,Source Address" group.long 0x4844++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_66,Source Address" group.long 0x4864++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_67,Source Address" group.long 0x4884++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_68,Source Address" group.long 0x48A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_69,Source Address" group.long 0x48C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_70,Source Address" group.long 0x48E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_71,Source Address" group.long 0x4904++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_72,Source Address" group.long 0x4924++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_73,Source Address" group.long 0x4944++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_74,Source Address" group.long 0x4964++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_75,Source Address" group.long 0x4984++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_76,Source Address" group.long 0x49A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_77,Source Address" group.long 0x49C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_78,Source Address" group.long 0x49E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_79,Source Address" group.long 0x4A04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_80,Source Address" group.long 0x4A24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_81,Source Address" group.long 0x4A44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_82,Source Address" group.long 0x4A64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_83,Source Address" group.long 0x4A84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_84,Source Address" group.long 0x4AA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_85,Source Address" group.long 0x4AC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_86,Source Address" group.long 0x4AE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_87,Source Address" group.long 0x4B04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_88,Source Address" group.long 0x4B24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_89,Source Address" group.long 0x4B44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_90,Source Address" group.long 0x4B64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_91,Source Address" group.long 0x4B84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_92,Source Address" group.long 0x4BA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_93,Source Address" group.long 0x4BC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_94,Source Address" group.long 0x4BE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_95,Source Address" group.long 0x4C04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_96,Source Address" group.long 0x4C24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_97,Source Address" group.long 0x4C44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_98,Source Address" group.long 0x4C64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_99,Source Address" group.long 0x4C84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_100,Source Address" group.long 0x4CA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_101,Source Address" group.long 0x4CC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_102,Source Address" group.long 0x4CE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_103,Source Address" group.long 0x4D04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_104,Source Address" group.long 0x4D24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_105,Source Address" group.long 0x4D44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_106,Source Address" group.long 0x4D64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_107,Source Address" group.long 0x4D84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_108,Source Address" group.long 0x4DA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_109,Source Address" group.long 0x4DC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_110,Source Address" group.long 0x4DE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_111,Source Address" group.long 0x4E04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_112,Source Address" group.long 0x4E24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_113,Source Address" group.long 0x4E44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_114,Source Address" group.long 0x4E64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_115,Source Address" group.long 0x4E84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_116,Source Address" group.long 0x4EA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_117,Source Address" group.long 0x4EC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_118,Source Address" group.long 0x4EE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_119,Source Address" group.long 0x4F04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_120,Source Address" group.long 0x4F24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_121,Source Address" group.long 0x4F44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_122,Source Address" group.long 0x4F64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_123,Source Address" group.long 0x4F84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_124,Source Address" group.long 0x4FA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_125,Source Address" group.long 0x4FC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_126,Source Address" group.long 0x4FE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_127,Source Address" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x402C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_1,Destination Address" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x406C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_3,Destination Address" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x40AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_5,Destination Address" group.long 0x40CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_6,Destination Address" group.long 0x40EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_7,Destination Address" group.long 0x410C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_8,Destination Address" group.long 0x412C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_9,Destination Address" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x416C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_11,Destination Address" group.long 0x418C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_12,Destination Address" group.long 0x41AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_13,Destination Address" group.long 0x41CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_14,Destination Address" group.long 0x41EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_15,Destination Address" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x422C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_17,Destination Address" group.long 0x424C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_18,Destination Address" group.long 0x426C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_19,Destination Address" group.long 0x428C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_20,Destination Address" group.long 0x42AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_21,Destination Address" group.long 0x42CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_22,Destination Address" group.long 0x42EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_23,Destination Address" group.long 0x430C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_24,Destination Address" group.long 0x432C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_25,Destination Address" group.long 0x434C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_26,Destination Address" group.long 0x436C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_27,Destination Address" group.long 0x438C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_28,Destination Address" group.long 0x43AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_29,Destination Address" group.long 0x43CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_30,Destination Address" group.long 0x43EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_31,Destination Address" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x442C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_33,Destination Address" group.long 0x444C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_34,Destination Address" group.long 0x446C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_35,Destination Address" group.long 0x448C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_36,Destination Address" group.long 0x44AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_37,Destination Address" group.long 0x44CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_38,Destination Address" group.long 0x44EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_39,Destination Address" group.long 0x450C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_40,Destination Address" group.long 0x452C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_41,Destination Address" group.long 0x454C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_42,Destination Address" group.long 0x456C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_43,Destination Address" group.long 0x458C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_44,Destination Address" group.long 0x45AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_45,Destination Address" group.long 0x45CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_46,Destination Address" group.long 0x45EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_47,Destination Address" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x462C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_49,Destination Address" group.long 0x464C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_50,Destination Address" group.long 0x466C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_51,Destination Address" group.long 0x468C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_52,Destination Address" group.long 0x46AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_53,Destination Address" group.long 0x46CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_54,Destination Address" group.long 0x46EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_55,Destination Address" group.long 0x470C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_56,Destination Address" group.long 0x472C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_57,Destination Address" group.long 0x474C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_58,Destination Address" group.long 0x476C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_59,Destination Address" group.long 0x478C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_60,Destination Address" group.long 0x47AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_61,Destination Address" group.long 0x47CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_62,Destination Address" group.long 0x47EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_63,Destination Address" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x482C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_65,Destination Address" group.long 0x484C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_66,Destination Address" group.long 0x486C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_67,Destination Address" group.long 0x488C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_68,Destination Address" group.long 0x48AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_69,Destination Address" group.long 0x48CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_70,Destination Address" group.long 0x48EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_71,Destination Address" group.long 0x490C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_72,Destination Address" group.long 0x492C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_73,Destination Address" group.long 0x494C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_74,Destination Address" group.long 0x496C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_75,Destination Address" group.long 0x498C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_76,Destination Address" group.long 0x49AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_77,Destination Address" group.long 0x49CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_78,Destination Address" group.long 0x49EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_79,Destination Address" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_81,Destination Address" group.long 0x4A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_82,Destination Address" group.long 0x4A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_83,Destination Address" group.long 0x4A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_84,Destination Address" group.long 0x4AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_85,Destination Address" group.long 0x4ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_86,Destination Address" group.long 0x4AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_87,Destination Address" group.long 0x4B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_88,Destination Address" group.long 0x4B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_89,Destination Address" group.long 0x4B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_90,Destination Address" group.long 0x4B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_91,Destination Address" group.long 0x4B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_92,Destination Address" group.long 0x4BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_93,Destination Address" group.long 0x4BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_94,Destination Address" group.long 0x4BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_95,Destination Address" group.long 0x4C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_96,Destination Address" group.long 0x4C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_97,Destination Address" group.long 0x4C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_98,Destination Address" group.long 0x4C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_99,Destination Address" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_101,Destination Address" group.long 0x4CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_102,Destination Address" group.long 0x4CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_103,Destination Address" group.long 0x4D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_104,Destination Address" group.long 0x4D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_105,Destination Address" group.long 0x4D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_106,Destination Address" group.long 0x4D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_107,Destination Address" group.long 0x4D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_108,Destination Address" group.long 0x4DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_109,Destination Address" group.long 0x4DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_110,Destination Address" group.long 0x4DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_111,Destination Address" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_113,Destination Address" group.long 0x4E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_114,Destination Address" group.long 0x4E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_115,Destination Address" group.long 0x4E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_116,Destination Address" group.long 0x4EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_117,Destination Address" group.long 0x4ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_118,Destination Address" group.long 0x4EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_119,Destination Address" group.long 0x4F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_120,Destination Address" group.long 0x4F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_121,Destination Address" group.long 0x4F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_122,Destination Address" group.long 0x4F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_123,Destination Address" group.long 0x4F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_124,Destination Address" group.long 0x4FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_125,Destination Address" group.long 0x4FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_126,Destination Address" group.long 0x4FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_127,Destination Address" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_1," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_3," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_5," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_6," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_7," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_8," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_9," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_11," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_12," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_13," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_14," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_15," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_17," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_18," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_19," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_20," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_21," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_22," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_23," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_24," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_25," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_26," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_27," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_28," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_29," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_30," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_31," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_33," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_34," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_35," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_36," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_37," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_38," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_39," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_40," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_41," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_42," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_43," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_44," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_45," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_46," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_47," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_49," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_50," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_51," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_52," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_53," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_54," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_55," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_56," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_57," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_58," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_59," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_60," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_61," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_62," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_63," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_65," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_66," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_67," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_68," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_69," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_70," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_71," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_72," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_73," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_74," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_75," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_76," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_77," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_78," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_79," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_81," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_82," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_83," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_84," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_85," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_86," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_87," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_88," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_89," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_90," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_91," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_92," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_93," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_94," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_95," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_96," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_97," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_98," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_99," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_101," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_102," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_103," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_104," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_105," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_106," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_107," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_108," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_109," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_110," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_111," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_113," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_114," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_115," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_116," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_117," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_118," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_119," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_120," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_121," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_122," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_123," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_124," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_125," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_126," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_127," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x403C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x407C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x411C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x413C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x417C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x419C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x423C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x425C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x427C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x429C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x431C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x433C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x435C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x437C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x439C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x443C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x445C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x447C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x449C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x451C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x453C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x455C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x457C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x459C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x463C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x465C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x467C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x469C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x471C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x473C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x475C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x477C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x479C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x483C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x485C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x487C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x489C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x491C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x493C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x495C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x497C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x499C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x41505000 ad:0x41506000 ) tree "DSP2_EDMA_TPTC$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPTCn_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPTCn_TCCFG,TC Configuration Register" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 8.--9. "DREGDEPTH,Destination Register FIFO Depth Parameterization" "0,1,2,3" bitfld.long 0x04 6.--7. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" group.long 0x100++0x13 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 11.--12. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" rbitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" rbitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" line.long 0x04 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" rbitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x08 "EDMA_TPTCn_INTEN,Interrupt Enable Register" hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x0C "EDMA_TPTCn_INTCLR,Interrupt Clear Register" hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x10 "EDMA_TPTCn_INTCMD,Interrupt Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" group.long 0x120++0x13 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" rbitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 1. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" line.long 0x04 "EDMA_TPTCn_ERREN,Error Enable Register" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x04 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x04 1. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" line.long 0x08 "EDMA_TPTCn_ERRCLR,Error Clear Register" hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x08 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x08 1. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" line.long 0x0C "EDMA_TPTCn_ERRDET,Error Details Register" hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0C 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" rbitfld.long 0x0C 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 14.--15. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EDMA_TPTCn_ERRCMD,Error Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" group.long 0x200++0x17 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" rbitfld.long 0x00 21. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" rbitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "Highest priority,Priority 1,?,?,?,?,?,Lowest priority" newline rbitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" line.long 0x08 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count" line.long 0x0C "EDMA_TPTCn_PDST,Program Set Destination Address" line.long 0x10 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" line.long 0x14 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x240++0x23 line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" line.long 0x08 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" line.long 0x0C "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved. return 0x0 w/o AERROR" line.long 0x10 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" line.long 0x14 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" line.long 0x1C "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" line.long 0x20 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" group.long 0x280++0x0B line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" line.long 0x04 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" line.long 0x08 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" group.long 0x300++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x304++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x344++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x308++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x348++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x30C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x34C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x350++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" group.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x354++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end repeat.end tree "DSP2_FW_CFG_TARG" base ad:0x4A174000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DSP2_FW_L2_NOC_CFG" base ad:0x41503000 group.long 0x00++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0,Core 0 Error log register" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" newline rbitfld.long 0x00 26. "RESERVED," "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" bitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x40++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 2.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x88++0x17 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" line.long 0x08 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1,Start physical address of region 1" hexmask.long 0x08 4.--31. 1. "RESERVED," bitfld.long 0x08 0.--3. "START_REGION_1,Physical target start address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1,End physical address of region 1" bitfld.long 0x0C 31. "END_REGION_1_ENABLE,End Region 1 enable" "0,1" hexmask.long 0x0C 4.--30. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "END_REGION_1,Physical target end address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_1,RM_PERMISSION_REGION_1_LOW register" hexmask.long.word 0x10 16.--31. 1. "RESERVED," bitfld.long 0x10 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x10 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x10 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x10 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x10 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x10 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x10 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x10 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x10 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_1,RM_PERMISSION_REGION_1_HIGH register" bitfld.long 0x14 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x14 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x14 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x14 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x14 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x14 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x14 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x14 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x14 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x14 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x14 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x14 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x14 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x14 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x14 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x14 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x14 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x14 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x14 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x14 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x14 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x14 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x14 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x14 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x14 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x14 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x14 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x14 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x14 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x14 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x14 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x14 0. "R0,Initiator ID0 permission" "0,1" group.long 0x1000++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0,Core 0 Error log register" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" newline rbitfld.long 0x00 26. "RESERVED," "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" bitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x1040++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 2.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x1088++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" rgroup.long 0x4000++0x17 line.long 0x00 "DSPNOC_FLAGMUX_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_FLAGMUX_ID_REVISIONID," line.long 0x08 "DSPNOC_FLAGMUX_FAULTEN," hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "FAULTEN,Global Fault Enable register" "0,1" line.long 0x0C "DSPNOC_FLAGMUX_FAULTSTATUS," hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "FAULTSTATUS,Global Fault Status register" "0,1" line.long 0x10 "DSPNOC_FLAGMUX_FLAGINEN0," hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" line.long 0x14 "DSPNOC_FLAGMUX_FLAGINSTATUS0," hexmask.long 0x14 1.--31. 1. "RESERVED," bitfld.long 0x14 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" rgroup.long 0x4200++0x1B line.long 0x00 "DSPNOC_ERRORLOG_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_ERRORLOG_ID_REVISIONID," line.long 0x08 "DSPNOC_ERRORLOG_FAULTEN," hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "FAULTEN,Enable Fault output" "0,1" line.long 0x0C "DSPNOC_ERRORLOG_ERRVLD," hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "ERRVLD,Error logged Valid" "0,1" line.long 0x10 "DSPNOC_ERRORLOG_ERRCLR," hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "ERRCLR,Clr ErrVld status" "0,1" line.long 0x14 "DSPNOC_ERRORLOG_ERRLOG0,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x14 31. "FORMAT,Format of ErrLog0 register" "0,1" bitfld.long 0x14 28.--30. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--27. 1. "LEN1,Header: Len1 value" bitfld.long 0x14 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x14 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0. "LOCK,Header: Lock bit value" "0,1" line.long 0x18 "DSPNOC_ERRORLOG_ERRLOG1," hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED," hexmask.long.word 0x18 0.--14. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x4220++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG3," bitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 0.--30. 1. "ERRLOG3,Header: Addr lsb value" rgroup.long 0x4228++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG5," hexmask.long.word 0x00 22.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--21. 1. "ERRLOG5,Header: User lsb value" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x41501000 ad:0x41502000 ) tree "DSP2_MMU$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Write 0's for future compatibility" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" rbitfld.long 0x00 5.--7. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x00 2. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" hexmask.long 0x08 5.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" newline bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0_w,EMUMISS_1_r" bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" hexmask.long 0x0C 5.--31. 1. "RESERVED,Write 0's for future compatibility Read returns 0" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" newline bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0,EMUMISS_1" bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" hexmask.long 0x00 1.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" hexmask.long 0x04 4.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable" "TWLENABLE_0,TWLENABLE_1" newline bitfld.long 0x04 1. "MMUENABLE,MMU enable" "MMUENABLE_0,MMUENABLE_1" rbitfld.long 0x04 0. "RESERVED,Write 0's for future compatibility" "0,1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" hexmask.long.byte 0x0C 0.--6. 1. "RESERVED,Write 0's for future compatibility" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 9. "RESERVED,Write 0's for future compatibility" "0,1" newline bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 0.--3. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" hexmask.long 0x14 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x18 4.--11. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x18 3. "P,Preserved bit" "P_0,P_1" newline bitfld.long 0x18 2. "V,Valid bit" "V_0,V_1" bitfld.long 0x18 0.--1. "PAGESIZE,Page size" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x1C 0.--11. 1. "RESERVED,Write 0's for future compatibility" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" hexmask.long 0x20 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" hexmask.long 0x24 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x28 4.--11. 1. "RESERVED,Reads return 0" bitfld.long 0x28 3. "P,Preserved bit" "P_0_r,P_1_r" newline bitfld.long 0x28 2. "V,Valid bit" "V_0_r,V_1_r" bitfld.long 0x28 0.--1. "PAGESIZE,Page size" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x2C 0.--11. 1. "RESERVED,Reads return 0" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" newline rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "0,1,2,3" bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "0,1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" hexmask.long.word 0x08 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 0.--15. 1. "RESERVED,Reserved" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 0.--15. 1. "RESERVED,Reserved" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 0.--15. 1. "RESERVED,Reserved" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the fourth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 0.--15. 1. "RESERVED,Reserved" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of fourth NO TRANSLATION REGION for 2D bursts" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" width 0x0B tree.end repeat.end tree "DSP2_PRM" base ad:0x4AE07B00 group.long 0x00++0x07 line.long 0x00 "PM_DSP2_PWRSTCTRL,This register controls the DSP power state to reach upon a domain sleep transition" hexmask.long.word 0x00 22.--31. 1. "RESERVED," rbitfld.long 0x00 20.--21. "DSP2_EDMA_ONSTATE,DSP_EDMA state when domain is ON" "?,?,?,DSP2_EDMA_ONSTATE_3" rbitfld.long 0x00 18.--19. "DSP2_L2_ONSTATE,DSP_L2 state when domain is ON" "?,?,?,DSP2_L2_ONSTATE_3" newline rbitfld.long 0x00 16.--17. "DSP2_L1_ONSTATE,DSP_L1 state when domain is ON" "?,?,?,DSP2_L1_ONSTATE_3" hexmask.long.word 0x00 5.--15. 1. "RESERVED," bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_DSP2_PWRSTST,This register provides a status on the DSP domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" hexmask.long.word 0x04 10.--19. 1. "RESERVED," rbitfld.long 0x04 8.--9. "DSP2_EDMA_STATEST,DSP_EDMA memory state status" "DSP2_EDMA_STATEST_0,DSP2_EDMA_STATEST_1,DSP2_EDMA_STATEST_2,DSP2_EDMA_STATEST_3" newline rbitfld.long 0x04 6.--7. "DSP2_L2_STATEST,DSP_L2 memory state status" "DSP2_L2_STATEST_0,DSP2_L2_STATEST_1,DSP2_L2_STATEST_2,DSP2_L2_STATEST_3" rbitfld.long 0x04 4.--5. "DSP2_L1_STATEST,DSP_L1 memory state status" "DSP2_L1_STATEST_0,DSP2_L1_STATEST_1,DSP2_L1_STATEST_2,DSP2_L1_STATEST_3" rbitfld.long 0x04 3. "RESERVED," "0,1" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_DSP2_RSTCTRL,This register controls the release of the DSP sub-system resets" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "RST_DSP2,DSP SW reset control" "RST_DSP2_0,RST_DSP2_1" bitfld.long 0x00 0. "RST_DSP2_LRST,DSP Local reset control" "RST_DSP2_LRST_0,RST_DSP2_LRST_1" line.long 0x04 "RM_DSP2_RSTST,This register logs the different reset sources of the DSP domain" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "RST_DSP2_EMU_REQ,DSP processor has been reset due to DSP emulation reset request driven from DSP-SS" "RST_DSP2_EMU_REQ_0,RST_DSP2_EMU_REQ_1" bitfld.long 0x04 2. "RST_DSP2_EMU,DSP domain has been reset due to emulation reset source e.g" "RST_DSP2_EMU_0,RST_DSP2_EMU_1" newline bitfld.long 0x04 1. "RST_DSP2,DSP SW reset status" "RST_DSP2_0,RST_DSP2_1" bitfld.long 0x04 0. "RST_DSP2_LRST,DSP Local SW reset" "RST_DSP2_LRST_0,RST_DSP2_LRST_1" group.long 0x24++0x03 line.long 0x00 "RM_DSP2_DSP2_CONTEXT,This register contains dedicated DSP context statuses" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," bitfld.long 0x00 10. "LOSTMEM_DSP_EDMA,Specify if memory-based context in DSP_EDMA memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_EDMA_0,LOSTMEM_DSP_EDMA_1" bitfld.long 0x00 9. "LOSTMEM_DSP_L2,Specify if memory-based context in DSP_L2 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_L2_0,LOSTMEM_DSP_L2_1" newline bitfld.long 0x00 8. "LOSTMEM_DSP_L1,Specify if memory-based context in DSP_L1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_L1_0,LOSTMEM_DSP_L1_1" hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "DSP2_SDMA_FW" base ad:0x4A173000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "DSP2_SDMA_TARG" base ad:0x44000600 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "DSP2_SYSTEM" base ad:0x41500000 rgroup.long 0x00++0x1B line.long 0x00 "DSP_SYS_REVISION," line.long 0x04 "DSP_SYS_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," bitfld.long 0x04 0.--3. "NUM,Instance Number Set by subsystem input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DSP_SYS_SYSCONFIG," hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 8. "RESERVED,Reserved" "0,1" rbitfld.long 0x08 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x08 4.--5. "STANDBYMODE," "?,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x08 2.--3. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x08 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x0C "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode" hexmask.long 0x0C 6.--31. 1. "RESERVED," bitfld.long 0x0C 4.--5. "OCPI_DISC_STAT,L3_MAIN (OCP) Initiator(s) Disconnect Status" "OCPI_DISC_STAT_0_r,OCPI_DISC_STAT_1_r,OCPI_DISC_STAT_2_r,?" bitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "TC1_STAT,EDMA TC1 Status" "TC1_STAT_0,TC1_STAT_1" bitfld.long 0x0C 1. "TC0_STAT,EDMA TC0 Status" "TC0_STAT_0,TC0_STAT_1" bitfld.long 0x0C 0. "C66X_STAT,C66x Status" "C66X_STAT_0,C66X_STAT_1" line.long 0x10 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "OCPI_DISC,OCP Initiator (on L3_MAIN) Disconnect request" "OCPI_DISC_0_w,OCPI_DISC_1_w" line.long 0x14 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators" rbitfld.long 0x14 31. "RESERVED," "0,1" bitfld.long 0x14 28.--30. "SDMA_PRI,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port" "0,1,2,3,4,5,6,7" rbitfld.long 0x14 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 24. "NOPOSTOVERRIDE,OCP Posted Write vs Non-Posted Write override" "NOPOSTOVERRIDE_0,NOPOSTOVERRIDE_1" rbitfld.long 0x14 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x14 20.--21. "SDMA_L2PRES,OCP Target port L2 Interconnect Pressure" "SDMA_L2PRES_0,SDMA_L2PRES_1,SDMA_L2PRES_2,SDMA_L2PRES_3" newline rbitfld.long 0x14 18.--19. "RESERVED," "0,1,2,3" bitfld.long 0x14 16.--17. "CFG_L2PRES,DSP CFG L2 Interconnect Pressure" "CFG_L2PRES_0,CFG_L2PRES_1,CFG_L2PRES_2,CFG_L2PRES_3" rbitfld.long 0x14 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 12.--13. "TC1_L2PRES,TC1 L2 Interconnect Pressure" "TC1_L2PRES_0,TC1_L2PRES_1,TC1_L2PRES_2,TC1_L2PRES_3" rbitfld.long 0x14 10.--11. "RESERVED," "0,1,2,3" bitfld.long 0x14 8.--9. "TC0_L2PRES,TC0 L2 Interconnect Pressure" "TC0_L2PRES_0,TC0_L2PRES_1,TC0_L2PRES_2,TC0_L2PRES_3" newline rbitfld.long 0x14 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x14 4.--5. "TC1_DBS,TC1 Default Burst size" "TC1_DBS_0,TC1_DBS_1,TC1_DBS_2,TC1_DBS_3" rbitfld.long 0x14 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 0.--1. "TC0_DBS,TC0 Default Burst size" "TC0_DBS_0,TC0_DBS_1,TC0_DBS_2,TC0_DBS_3" line.long 0x18 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs" hexmask.long.tbyte 0x18 13.--31. 1. "RESERVED," bitfld.long 0x18 12. "MMU1_ABORT,MU1 Abort" "MMU1_ABORT_0,MMU1_ABORT_1" rbitfld.long 0x18 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "MMU0_ABORT,MU0 Abort" "MMU0_ABORT_0,MMU0_ABORT_1" rbitfld.long 0x18 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 4. "MMU1_EN,MU1 Enable" "MMU1_EN_0,MMU1_EN_1" newline rbitfld.long 0x18 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 0. "MMU0_EN,MU1 Enable" "MMU0_EN_0,MMU0_EN_1" group.long 0x20++0x07 line.long 0x00 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x30++0x07 line.long 0x00 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x40++0x07 line.long 0x00 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state" line.long 0x04 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state" group.long 0x50++0x2F line.long 0x00 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.word 0x00 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--18. 1. "EVENT,Settable raw status for event #n" line.long 0x04 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector" hexmask.long.word 0x04 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x04 0.--18. 1. "EVENT,Clearable enabled status for event #n" line.long 0x08 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" hexmask.long.word 0x08 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x08 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x0C "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" hexmask.long.word 0x0C 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x0C 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x10 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x14 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x18 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x1C "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" line.long 0x20 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x24 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x28 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x2C "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" group.long 0xF8++0x07 line.long 0x00 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus" hexmask.long 0x00 4.--31. 1. "RESERVED," bitfld.long 0x00 0.--3. "GROUP,Debug Group output control mux selectN: GN = select output group N" "GROUP_0,GROUP_1,GROUP_2,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group" width 0x0B tree.end tree "DSP_EDMA_TPCC" base ad:0x1D10000 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x04 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x04 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" newline rbitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x04 22.--23. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x04 19. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x04 15. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x04 11. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7" group.long 0xFC++0x113 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" line.long 0x04 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x04 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x08 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x08 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x0C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x10 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x14 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x18 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x1C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" hexmask.long.tbyte 0x20 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x20 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" hexmask.long.tbyte 0x24 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x24 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" hexmask.long.tbyte 0x28 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x28 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x28 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x2C "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.tbyte 0x2C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x2C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x2C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" hexmask.long.tbyte 0x30 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x30 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x30 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" hexmask.long.tbyte 0x34 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x34 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x34 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x38 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" hexmask.long.tbyte 0x38 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x38 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x38 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x3C "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" hexmask.long.tbyte 0x3C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x3C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x3C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" hexmask.long.tbyte 0x40 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x40 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x40 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x44 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" hexmask.long.tbyte 0x44 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x44 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x44 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x48 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" hexmask.long.tbyte 0x48 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x48 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x48 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x4C "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" hexmask.long.tbyte 0x4C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x4C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" hexmask.long.tbyte 0x50 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x50 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x50 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x54 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" hexmask.long.tbyte 0x54 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x54 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x54 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x58 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" hexmask.long.tbyte 0x58 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x58 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x58 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x5C "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" hexmask.long.tbyte 0x5C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x5C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x5C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x60 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" hexmask.long.tbyte 0x60 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x60 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x60 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x64 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" hexmask.long.tbyte 0x64 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x64 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x64 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x68 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" hexmask.long.tbyte 0x68 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x68 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x68 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x6C "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" hexmask.long.tbyte 0x6C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x6C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x6C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x70 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" hexmask.long.tbyte 0x70 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x70 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x70 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x74 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" hexmask.long.tbyte 0x74 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x74 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x74 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x78 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" hexmask.long.tbyte 0x78 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x78 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x78 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x7C "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" hexmask.long.tbyte 0x7C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x7C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x7C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x80 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" hexmask.long.tbyte 0x80 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x80 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x80 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x84 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" hexmask.long.tbyte 0x84 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x84 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x84 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x88 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" hexmask.long.tbyte 0x88 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x88 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x88 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x8C "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" hexmask.long.tbyte 0x8C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x8C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x8C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x90 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" hexmask.long.tbyte 0x90 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x90 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x90 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x94 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" hexmask.long.tbyte 0x94 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x94 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x94 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x98 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" hexmask.long.tbyte 0x98 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x98 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x98 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x9C "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" hexmask.long.tbyte 0x9C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x9C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x9C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA0 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA4 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA8 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xAC "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" hexmask.long.tbyte 0xAC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xAC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xAC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB0 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB4 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB8 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xBC "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" hexmask.long.tbyte 0xBC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xBC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xBC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC0 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC4 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC8 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xCC "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" hexmask.long.tbyte 0xCC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xCC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xCC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD0 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD4 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD8 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xDC "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" hexmask.long.tbyte 0xDC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xDC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xDC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE0 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE4 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE8 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xEC "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" hexmask.long.tbyte 0xEC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xEC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xEC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF0 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF4 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF8 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xFC "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" hexmask.long.tbyte 0xFC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xFC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xFC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x100 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" hexmask.long.tbyte 0x100 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x100 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x100 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x104 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x104 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x104 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x104 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x104 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x108 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x108 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x108 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x108 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x108 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x10C "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x10C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10C 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x10C 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x10C 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x110 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x110 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x110 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x110 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x110 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x240++0x23 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x00 31. "RESERVED,Reserved" "0,1" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 27. "RESERVED,Reserved" "0,1" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 23. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Reserved" "0,1" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 15. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x04 31. "RESERVED,Reserved" "0,1" bitfld.long 0x04 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 27. "RESERVED,Reserved" "0,1" bitfld.long 0x04 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 23. "RESERVED,Reserved" "0,1" bitfld.long 0x04 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED,Reserved" "0,1" bitfld.long 0x04 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 15. "RESERVED,Reserved" "0,1" bitfld.long 0x04 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 11. "RESERVED,Reserved" "0,1" bitfld.long 0x04 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED,Reserved" "0,1" bitfld.long 0x04 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x08 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x08 31. "RESERVED,Reserved" "0,1" bitfld.long 0x08 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 27. "RESERVED,Reserved" "0,1" bitfld.long 0x08 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 23. "RESERVED,Reserved" "0,1" bitfld.long 0x08 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED,Reserved" "0,1" bitfld.long 0x08 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 15. "RESERVED,Reserved" "0,1" bitfld.long 0x08 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 11. "RESERVED,Reserved" "0,1" bitfld.long 0x08 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED,Reserved" "0,1" bitfld.long 0x08 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x0C "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x0C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x10 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x10 31. "RESERVED,Reserved" "0,1" bitfld.long 0x10 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED,Reserved" "0,1" bitfld.long 0x10 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED,Reserved" "0,1" bitfld.long 0x10 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "RESERVED,Reserved" "0,1" bitfld.long 0x10 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 15. "RESERVED,Reserved" "0,1" bitfld.long 0x10 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 11. "RESERVED,Reserved" "0,1" bitfld.long 0x10 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" bitfld.long 0x10 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 3. "RESERVED,Reserved" "0,1" bitfld.long 0x10 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x14 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x14 31. "RESERVED,Reserved" "0,1" bitfld.long 0x14 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED,Reserved" "0,1" bitfld.long 0x14 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED,Reserved" "0,1" bitfld.long 0x14 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED,Reserved" "0,1" bitfld.long 0x14 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED,Reserved" "0,1" bitfld.long 0x14 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" bitfld.long 0x14 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED,Reserved" "0,1" bitfld.long 0x14 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x18 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x18 31. "RESERVED,Reserved" "0,1" bitfld.long 0x18 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED,Reserved" "0,1" bitfld.long 0x18 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED,Reserved" "0,1" bitfld.long 0x18 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED,Reserved" "0,1" bitfld.long 0x18 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED,Reserved" "0,1" bitfld.long 0x18 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED,Reserved" "0,1" bitfld.long 0x18 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED,Reserved" "0,1" bitfld.long 0x18 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED,Reserved" "0,1" bitfld.long 0x18 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x1C "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x1C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x20 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" rbitfld.long 0x20 31. "RESERVED," "0,1" bitfld.long 0x20 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 27. "RESERVED," "0,1" bitfld.long 0x20 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 23. "RESERVED," "0,1" bitfld.long 0x20 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 19. "RESERVED," "0,1" bitfld.long 0x20 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 15. "RESERVED," "0,1" bitfld.long 0x20 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 11. "RESERVED," "0,1" bitfld.long 0x20 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 7. "RESERVED," "0,1" bitfld.long 0x20 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 3. "RESERVED," "0,1" bitfld.long 0x20 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x280++0x07 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_QUEPRI,Queue Priority" hexmask.long 0x04 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" rgroup.long 0x300++0x23 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" newline bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" newline bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" newline bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" newline bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" newline bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" newline bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" newline bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" newline bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" newline bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" newline bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" newline bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" newline bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" newline bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" newline bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" newline bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" newline bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" newline bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" newline bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" newline bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" newline bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" line.long 0x08 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1" newline bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1" bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1" newline bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1" newline bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1" bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1" newline bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1" newline bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1" bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1" newline bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1" newline bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1" bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1" newline bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1" newline bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1" bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1" newline bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1" line.long 0x0C "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1" bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1" bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1" bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1" bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1" bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1" line.long 0x10 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,Event Missed #7" "0,1" newline bitfld.long 0x10 6. "E6,Event Missed #6" "0,1" bitfld.long 0x10 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x10 4. "E4,Event Missed #4" "0,1" bitfld.long 0x10 3. "E3,Event Missed #3" "0,1" newline bitfld.long 0x10 2. "E2,Event Missed #2" "0,1" bitfld.long 0x10 1. "E1,Event Missed #1" "0,1" newline bitfld.long 0x10 0. "E0,Event Missed #0" "0,1" line.long 0x14 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1" newline bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1" newline bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1" bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1" newline bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1" line.long 0x18 "EDMA_TPCC_CCERR,CC Error Register" hexmask.long.word 0x18 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 16. "TCERR,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register" "TCERR_0,TCERR_1" newline hexmask.long.byte 0x18 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD7_0,QTHRXCD7_1" newline bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD6_0,QTHRXCD6_1" bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD5_0,QTHRXCD5_1" newline bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD4_0,QTHRXCD4_1" bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD3_0,QTHRXCD3_1" newline bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD1_0,QTHRXCD1_1" newline bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x1C "EDMA_TPCC_CCERRCLR,CC Error Clear Register" hexmask.long.word 0x1C 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR" "0,1" newline hexmask.long.byte 0x1C 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect" "0,1" bitfld.long 0x1C 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect" "0,1" bitfld.long 0x1C 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" newline bitfld.long 0x1C 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect" "0,1" bitfld.long 0x1C 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" newline bitfld.long 0x1C 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect" "0,1" line.long 0x20 "EDMA_TPCC_EEVAL,Error Eval Register" hexmask.long 0x20 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 1. "SET,Error Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x20 0. "EVAL,Error Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x348++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x350++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x358++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x360++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x368++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x370++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x378++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x344++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x34C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x354++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x35C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x364++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x36C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x374++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x37C++0x23 line.long 0x00 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" line.long 0x04 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x04 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x04 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x04 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x04 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x04 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x04 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x04 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x08 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x08 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x08 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x08 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x08 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x08 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x08 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x08 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x0C "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x0C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x0C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x0C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x0C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x0C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x0C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x0C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x10 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x10 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x10 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x10 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x10 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x10 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x10 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x10 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x14 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x14 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x14 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x14 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x14 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x14 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x14 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x14 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x18 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x18 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x18 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x18 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x18 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x18 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x18 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x18 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x1C "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x1C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x1C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x1C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x1C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x1C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x1C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x1C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x20 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x20 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x20 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x20 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x20 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x20 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x20 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x20 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" rgroup.long 0x400++0x7F line.long 0x00 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x04 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x08 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x10 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x14 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x18 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x1C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x20 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x24 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x28 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x2C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x30 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x30 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x30 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x34 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x34 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x38 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x38 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x3C "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x3C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x40 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x40 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x44 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x44 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x44 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x48 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x48 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x48 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x4C "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x4C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x4C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x50 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x50 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x50 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x54 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x54 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x54 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x54 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x58 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x58 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x58 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x58 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x5C "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x5C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x5C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x5C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x60 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x60 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x60 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x60 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x64 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x64 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x64 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x64 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x68 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x68 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x68 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x68 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x6C "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x6C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x6C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x6C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x70 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x70 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x70 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x70 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x74 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x74 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x74 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x74 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x78 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x78 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x78 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x78 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x7C "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x7C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x7C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x7C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x600++0x07 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" line.long 0x04 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" hexmask.long.byte 0x04 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" rbitfld.long 0x00 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" rbitfld.long 0x04 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,reads return 0's" rbitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" newline rbitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" rbitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" newline rbitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" rbitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" newline bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2" rbitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" newline rbitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 14.--15. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" rbitfld.long 0x00 5.--7. "RESERVED,reads return 0's" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" rbitfld.long 0x00 3. "RESERVED,reads return 0's" "0,1" newline bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.." rbitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" newline rbitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" group.long 0x700++0x0B line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" hexmask.long.tbyte 0x00 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" line.long 0x08 "EDMA_TPCC_AETCMD,AET Command" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "CLR,AET Clear commandCPU writes 0x0 has no effect" "0,1" rgroup.long 0x800++0x2F line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" line.long 0x04 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" newline rbitfld.long 0x04 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" rbitfld.long 0x04 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" newline rbitfld.long 0x04 2. "URE,User Read Error" "URE_0,URE_1" rbitfld.long 0x04 1. "UWE,User Write Error" "UWE_0,UWE_1" newline rbitfld.long 0x04 0. "UXE,User Execute Error" "UXE_0,UXE_1" line.long 0x08 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" line.long 0x0C "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x0C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x0C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x0C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x0C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x0C 10. "AID0,Allowed ID 0" "AID0_0,AID0_1" bitfld.long 0x0C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x0C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x0C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x0C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x0C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x0C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x0C 0. "UX,User Execute permission" "UX_0,UX_1" line.long 0x10 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x10 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x10 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x10 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x10 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x10 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x10 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x10 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x10 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x10 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x10 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x10 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x10 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x10 0. "UX,User Execute permission" "UX_0,?" line.long 0x14 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x14 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x14 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x14 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x14 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x14 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x14 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x14 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x14 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x14 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x14 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x14 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x14 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x14 0. "UX,User Execute permission" "UX_0,?" line.long 0x18 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x18 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x18 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x18 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x18 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x18 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x18 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x18 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x18 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x18 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x18 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x18 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x18 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x18 0. "UX,User Execute permission" "UX_0,?" line.long 0x1C "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x1C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x1C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x1C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x1C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x1C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x1C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x1C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x1C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x1C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x1C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x1C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x1C 0. "UX,User Execute permission" "UX_0,?" line.long 0x20 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x20 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x20 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x20 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x20 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x20 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x20 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x20 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x20 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x20 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x20 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x20 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x20 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x20 0. "UX,User Execute permission" "UX_0,?" line.long 0x24 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x24 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x24 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x24 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x24 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x24 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x24 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x24 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x24 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x24 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x24 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x24 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x24 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x24 0. "UX,User Execute permission" "UX_0,?" line.long 0x28 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" hexmask.long.word 0x28 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x28 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x28 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x28 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x28 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x28 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x28 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x28 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x28 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x28 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x28 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x28 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x28 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x28 0. "UX,User Execute permission" "UX_0,?" line.long 0x2C "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" hexmask.long.word 0x2C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x2C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x2C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x2C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x2C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x2C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x2C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x2C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x2C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x2C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x2C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x2C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x2C 0. "UX,User Execute permission" "UX_0,?" rgroup.long 0x1000++0x47 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" newline bitfld.long 0x04 29. "E61,Event #61" "0,1" bitfld.long 0x04 28. "E60,Event #60" "0,1" newline bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" newline bitfld.long 0x04 23. "E55,Event #55" "0,1" bitfld.long 0x04 22. "E54,Event #54" "0,1" newline bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" newline bitfld.long 0x04 17. "E49,Event #49" "0,1" bitfld.long 0x04 16. "E48,Event #48" "0,1" newline bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" newline bitfld.long 0x04 11. "E43,Event #43" "0,1" bitfld.long 0x04 10. "E42,Event #42" "0,1" newline bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" newline bitfld.long 0x04 5. "E37,Event #37" "0,1" bitfld.long 0x04 4. "E36,Event #36" "0,1" newline bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" line.long 0x08 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event #31" "0,1" bitfld.long 0x08 30. "E30,Event #30" "0,1" newline bitfld.long 0x08 29. "E29,Event #29" "0,1" bitfld.long 0x08 28. "E28,Event #28" "0,1" newline bitfld.long 0x08 27. "E27,Event #27" "0,1" bitfld.long 0x08 26. "E26,Event #26" "0,1" newline bitfld.long 0x08 25. "E25,Event #25" "0,1" bitfld.long 0x08 24. "E24,Event #24" "0,1" newline bitfld.long 0x08 23. "E23,Event #23" "0,1" bitfld.long 0x08 22. "E22,Event #22" "0,1" newline bitfld.long 0x08 21. "E21,Event #21" "0,1" bitfld.long 0x08 20. "E20,Event #20" "0,1" newline bitfld.long 0x08 19. "E19,Event #19" "0,1" bitfld.long 0x08 18. "E18,Event #18" "0,1" newline bitfld.long 0x08 17. "E17,Event #17" "0,1" bitfld.long 0x08 16. "E16,Event #16" "0,1" newline bitfld.long 0x08 15. "E15,Event #15" "0,1" bitfld.long 0x08 14. "E14,Event #14" "0,1" newline bitfld.long 0x08 13. "E13,Event #13" "0,1" bitfld.long 0x08 12. "E12,Event #12" "0,1" newline bitfld.long 0x08 11. "E11,Event #11" "0,1" bitfld.long 0x08 10. "E10,Event #10" "0,1" newline bitfld.long 0x08 9. "E9,Event #9" "0,1" bitfld.long 0x08 8. "E8,Event #8" "0,1" newline bitfld.long 0x08 7. "E7,Event #7" "0,1" bitfld.long 0x08 6. "E6,Event #6" "0,1" newline bitfld.long 0x08 5. "E5,Event #5" "0,1" bitfld.long 0x08 4. "E4,Event #4" "0,1" newline bitfld.long 0x08 3. "E3,Event #3" "0,1" bitfld.long 0x08 2. "E2,Event #2" "0,1" newline bitfld.long 0x08 1. "E1,Event #1" "0,1" bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event #63" "0,1" bitfld.long 0x0C 30. "E62,Event #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event #61" "0,1" bitfld.long 0x0C 28. "E60,Event #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event #59" "0,1" bitfld.long 0x0C 26. "E58,Event #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event #57" "0,1" bitfld.long 0x0C 24. "E56,Event #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event #55" "0,1" bitfld.long 0x0C 22. "E54,Event #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event #53" "0,1" bitfld.long 0x0C 20. "E52,Event #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event #51" "0,1" bitfld.long 0x0C 18. "E50,Event #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event #49" "0,1" bitfld.long 0x0C 16. "E48,Event #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event #47" "0,1" bitfld.long 0x0C 14. "E46,Event #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event #45" "0,1" bitfld.long 0x0C 12. "E44,Event #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event #43" "0,1" bitfld.long 0x0C 10. "E42,Event #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event #41" "0,1" bitfld.long 0x0C 8. "E40,Event #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event #39" "0,1" bitfld.long 0x0C 6. "E38,Event #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event #37" "0,1" bitfld.long 0x0C 4. "E36,Event #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event #35" "0,1" bitfld.long 0x0C 2. "E34,Event #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event #33" "0,1" bitfld.long 0x0C 0. "E32,Event #32" "0,1" line.long 0x10 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x10 31. "E31,Event #31" "0,1" bitfld.long 0x10 30. "E30,Event #30" "0,1" newline bitfld.long 0x10 29. "E29,Event #29" "0,1" bitfld.long 0x10 28. "E28,Event #28" "0,1" newline bitfld.long 0x10 27. "E27,Event #27" "0,1" bitfld.long 0x10 26. "E26,Event #26" "0,1" newline bitfld.long 0x10 25. "E25,Event #25" "0,1" bitfld.long 0x10 24. "E24,Event #24" "0,1" newline bitfld.long 0x10 23. "E23,Event #23" "0,1" bitfld.long 0x10 22. "E22,Event #22" "0,1" newline bitfld.long 0x10 21. "E21,Event #21" "0,1" bitfld.long 0x10 20. "E20,Event #20" "0,1" newline bitfld.long 0x10 19. "E19,Event #19" "0,1" bitfld.long 0x10 18. "E18,Event #18" "0,1" newline bitfld.long 0x10 17. "E17,Event #17" "0,1" bitfld.long 0x10 16. "E16,Event #16" "0,1" newline bitfld.long 0x10 15. "E15,Event #15" "0,1" bitfld.long 0x10 14. "E14,Event #14" "0,1" newline bitfld.long 0x10 13. "E13,Event #13" "0,1" bitfld.long 0x10 12. "E12,Event #12" "0,1" newline bitfld.long 0x10 11. "E11,Event #11" "0,1" bitfld.long 0x10 10. "E10,Event #10" "0,1" newline bitfld.long 0x10 9. "E9,Event #9" "0,1" bitfld.long 0x10 8. "E8,Event #8" "0,1" newline bitfld.long 0x10 7. "E7,Event #7" "0,1" bitfld.long 0x10 6. "E6,Event #6" "0,1" newline bitfld.long 0x10 5. "E5,Event #5" "0,1" bitfld.long 0x10 4. "E4,Event #4" "0,1" newline bitfld.long 0x10 3. "E3,Event #3" "0,1" bitfld.long 0x10 2. "E2,Event #2" "0,1" newline bitfld.long 0x10 1. "E1,Event #1" "0,1" bitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x14 31. "E63,Event #63" "0,1" bitfld.long 0x14 30. "E62,Event #62" "0,1" newline bitfld.long 0x14 29. "E61,Event #61" "0,1" bitfld.long 0x14 28. "E60,Event #60" "0,1" newline bitfld.long 0x14 27. "E59,Event #59" "0,1" bitfld.long 0x14 26. "E58,Event #58" "0,1" newline bitfld.long 0x14 25. "E57,Event #57" "0,1" bitfld.long 0x14 24. "E56,Event #56" "0,1" newline bitfld.long 0x14 23. "E55,Event #55" "0,1" bitfld.long 0x14 22. "E54,Event #54" "0,1" newline bitfld.long 0x14 21. "E53,Event #53" "0,1" bitfld.long 0x14 20. "E52,Event #52" "0,1" newline bitfld.long 0x14 19. "E51,Event #51" "0,1" bitfld.long 0x14 18. "E50,Event #50" "0,1" newline bitfld.long 0x14 17. "E49,Event #49" "0,1" bitfld.long 0x14 16. "E48,Event #48" "0,1" newline bitfld.long 0x14 15. "E47,Event #47" "0,1" bitfld.long 0x14 14. "E46,Event #46" "0,1" newline bitfld.long 0x14 13. "E45,Event #45" "0,1" bitfld.long 0x14 12. "E44,Event #44" "0,1" newline bitfld.long 0x14 11. "E43,Event #43" "0,1" bitfld.long 0x14 10. "E42,Event #42" "0,1" newline bitfld.long 0x14 9. "E41,Event #41" "0,1" bitfld.long 0x14 8. "E40,Event #40" "0,1" newline bitfld.long 0x14 7. "E39,Event #39" "0,1" bitfld.long 0x14 6. "E38,Event #38" "0,1" newline bitfld.long 0x14 5. "E37,Event #37" "0,1" bitfld.long 0x14 4. "E36,Event #36" "0,1" newline bitfld.long 0x14 3. "E35,Event #35" "0,1" bitfld.long 0x14 2. "E34,Event #34" "0,1" newline bitfld.long 0x14 1. "E33,Event #33" "0,1" bitfld.long 0x14 0. "E32,Event #32" "0,1" line.long 0x18 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x18 31. "E31,Event #31" "0,1" bitfld.long 0x18 30. "E30,Event #30" "0,1" newline bitfld.long 0x18 29. "E29,Event #29" "0,1" bitfld.long 0x18 28. "E28,Event #28" "0,1" newline bitfld.long 0x18 27. "E27,Event #27" "0,1" bitfld.long 0x18 26. "E26,Event #26" "0,1" newline bitfld.long 0x18 25. "E25,Event #25" "0,1" bitfld.long 0x18 24. "E24,Event #24" "0,1" newline bitfld.long 0x18 23. "E23,Event #23" "0,1" bitfld.long 0x18 22. "E22,Event #22" "0,1" newline bitfld.long 0x18 21. "E21,Event #21" "0,1" bitfld.long 0x18 20. "E20,Event #20" "0,1" newline bitfld.long 0x18 19. "E19,Event #19" "0,1" bitfld.long 0x18 18. "E18,Event #18" "0,1" newline bitfld.long 0x18 17. "E17,Event #17" "0,1" bitfld.long 0x18 16. "E16,Event #16" "0,1" newline bitfld.long 0x18 15. "E15,Event #15" "0,1" bitfld.long 0x18 14. "E14,Event #14" "0,1" newline bitfld.long 0x18 13. "E13,Event #13" "0,1" bitfld.long 0x18 12. "E12,Event #12" "0,1" newline bitfld.long 0x18 11. "E11,Event #11" "0,1" bitfld.long 0x18 10. "E10,Event #10" "0,1" newline bitfld.long 0x18 9. "E9,Event #9" "0,1" bitfld.long 0x18 8. "E8,Event #8" "0,1" newline bitfld.long 0x18 7. "E7,Event #7" "0,1" bitfld.long 0x18 6. "E6,Event #6" "0,1" newline bitfld.long 0x18 5. "E5,Event #5" "0,1" bitfld.long 0x18 4. "E4,Event #4" "0,1" newline bitfld.long 0x18 3. "E3,Event #3" "0,1" bitfld.long 0x18 2. "E2,Event #2" "0,1" newline bitfld.long 0x18 1. "E1,Event #1" "0,1" bitfld.long 0x18 0. "E0,Event #0" "0,1" line.long 0x1C "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x1C 31. "E63,Event #63" "0,1" bitfld.long 0x1C 30. "E62,Event #62" "0,1" newline bitfld.long 0x1C 29. "E61,Event #61" "0,1" bitfld.long 0x1C 28. "E60,Event #60" "0,1" newline bitfld.long 0x1C 27. "E59,Event #59" "0,1" bitfld.long 0x1C 26. "E58,Event #58" "0,1" newline bitfld.long 0x1C 25. "E57,Event #57" "0,1" bitfld.long 0x1C 24. "E56,Event #56" "0,1" newline bitfld.long 0x1C 23. "E55,Event #55" "0,1" bitfld.long 0x1C 22. "E54,Event #54" "0,1" newline bitfld.long 0x1C 21. "E53,Event #53" "0,1" bitfld.long 0x1C 20. "E52,Event #52" "0,1" newline bitfld.long 0x1C 19. "E51,Event #51" "0,1" bitfld.long 0x1C 18. "E50,Event #50" "0,1" newline bitfld.long 0x1C 17. "E49,Event #49" "0,1" bitfld.long 0x1C 16. "E48,Event #48" "0,1" newline bitfld.long 0x1C 15. "E47,Event #47" "0,1" bitfld.long 0x1C 14. "E46,Event #46" "0,1" newline bitfld.long 0x1C 13. "E45,Event #45" "0,1" bitfld.long 0x1C 12. "E44,Event #44" "0,1" newline bitfld.long 0x1C 11. "E43,Event #43" "0,1" bitfld.long 0x1C 10. "E42,Event #42" "0,1" newline bitfld.long 0x1C 9. "E41,Event #41" "0,1" bitfld.long 0x1C 8. "E40,Event #40" "0,1" newline bitfld.long 0x1C 7. "E39,Event #39" "0,1" bitfld.long 0x1C 6. "E38,Event #38" "0,1" newline bitfld.long 0x1C 5. "E37,Event #37" "0,1" bitfld.long 0x1C 4. "E36,Event #36" "0,1" newline bitfld.long 0x1C 3. "E35,Event #35" "0,1" bitfld.long 0x1C 2. "E34,Event #34" "0,1" newline bitfld.long 0x1C 1. "E33,Event #33" "0,1" bitfld.long 0x1C 0. "E32,Event #32" "0,1" line.long 0x20 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x20 31. "E31,Event #31" "0,1" bitfld.long 0x20 30. "E30,Event #30" "0,1" newline bitfld.long 0x20 29. "E29,Event #29" "0,1" bitfld.long 0x20 28. "E28,Event #28" "0,1" newline bitfld.long 0x20 27. "E27,Event #27" "0,1" bitfld.long 0x20 26. "E26,Event #26" "0,1" newline bitfld.long 0x20 25. "E25,Event #25" "0,1" bitfld.long 0x20 24. "E24,Event #24" "0,1" newline bitfld.long 0x20 23. "E23,Event #23" "0,1" bitfld.long 0x20 22. "E22,Event #22" "0,1" newline bitfld.long 0x20 21. "E21,Event #21" "0,1" bitfld.long 0x20 20. "E20,Event #20" "0,1" newline bitfld.long 0x20 19. "E19,Event #19" "0,1" bitfld.long 0x20 18. "E18,Event #18" "0,1" newline bitfld.long 0x20 17. "E17,Event #17" "0,1" bitfld.long 0x20 16. "E16,Event #16" "0,1" newline bitfld.long 0x20 15. "E15,Event #15" "0,1" bitfld.long 0x20 14. "E14,Event #14" "0,1" newline bitfld.long 0x20 13. "E13,Event #13" "0,1" bitfld.long 0x20 12. "E12,Event #12" "0,1" newline bitfld.long 0x20 11. "E11,Event #11" "0,1" bitfld.long 0x20 10. "E10,Event #10" "0,1" newline bitfld.long 0x20 9. "E9,Event #9" "0,1" bitfld.long 0x20 8. "E8,Event #8" "0,1" newline bitfld.long 0x20 7. "E7,Event #7" "0,1" bitfld.long 0x20 6. "E6,Event #6" "0,1" newline bitfld.long 0x20 5. "E5,Event #5" "0,1" bitfld.long 0x20 4. "E4,Event #4" "0,1" newline bitfld.long 0x20 3. "E3,Event #3" "0,1" bitfld.long 0x20 2. "E2,Event #2" "0,1" newline bitfld.long 0x20 1. "E1,Event #1" "0,1" bitfld.long 0x20 0. "E0,Event #0" "0,1" line.long 0x24 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x24 31. "E63,Event #63" "0,1" bitfld.long 0x24 30. "E62,Event #62" "0,1" newline bitfld.long 0x24 29. "E61,Event #61" "0,1" bitfld.long 0x24 28. "E60,Event #60" "0,1" newline bitfld.long 0x24 27. "E59,Event #59" "0,1" bitfld.long 0x24 26. "E58,Event #58" "0,1" newline bitfld.long 0x24 25. "E57,Event #57" "0,1" bitfld.long 0x24 24. "E56,Event #56" "0,1" newline bitfld.long 0x24 23. "E55,Event #55" "0,1" bitfld.long 0x24 22. "E54,Event #54" "0,1" newline bitfld.long 0x24 21. "E53,Event #53" "0,1" bitfld.long 0x24 20. "E52,Event #52" "0,1" newline bitfld.long 0x24 19. "E51,Event #51" "0,1" bitfld.long 0x24 18. "E50,Event #50" "0,1" newline bitfld.long 0x24 17. "E49,Event #49" "0,1" bitfld.long 0x24 16. "E48,Event #48" "0,1" newline bitfld.long 0x24 15. "E47,Event #47" "0,1" bitfld.long 0x24 14. "E46,Event #46" "0,1" newline bitfld.long 0x24 13. "E45,Event #45" "0,1" bitfld.long 0x24 12. "E44,Event #44" "0,1" newline bitfld.long 0x24 11. "E43,Event #43" "0,1" bitfld.long 0x24 10. "E42,Event #42" "0,1" newline bitfld.long 0x24 9. "E41,Event #41" "0,1" bitfld.long 0x24 8. "E40,Event #40" "0,1" newline bitfld.long 0x24 7. "E39,Event #39" "0,1" bitfld.long 0x24 6. "E38,Event #38" "0,1" newline bitfld.long 0x24 5. "E37,Event #37" "0,1" bitfld.long 0x24 4. "E36,Event #36" "0,1" newline bitfld.long 0x24 3. "E35,Event #35" "0,1" bitfld.long 0x24 2. "E34,Event #34" "0,1" newline bitfld.long 0x24 1. "E33,Event #33" "0,1" bitfld.long 0x24 0. "E32,Event #32" "0,1" line.long 0x28 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x28 31. "E31,Event #31" "0,1" bitfld.long 0x28 30. "E30,Event #30" "0,1" newline bitfld.long 0x28 29. "E29,Event #29" "0,1" bitfld.long 0x28 28. "E28,Event #28" "0,1" newline bitfld.long 0x28 27. "E27,Event #27" "0,1" bitfld.long 0x28 26. "E26,Event #26" "0,1" newline bitfld.long 0x28 25. "E25,Event #25" "0,1" bitfld.long 0x28 24. "E24,Event #24" "0,1" newline bitfld.long 0x28 23. "E23,Event #23" "0,1" bitfld.long 0x28 22. "E22,Event #22" "0,1" newline bitfld.long 0x28 21. "E21,Event #21" "0,1" bitfld.long 0x28 20. "E20,Event #20" "0,1" newline bitfld.long 0x28 19. "E19,Event #19" "0,1" bitfld.long 0x28 18. "E18,Event #18" "0,1" newline bitfld.long 0x28 17. "E17,Event #17" "0,1" bitfld.long 0x28 16. "E16,Event #16" "0,1" newline bitfld.long 0x28 15. "E15,Event #15" "0,1" bitfld.long 0x28 14. "E14,Event #14" "0,1" newline bitfld.long 0x28 13. "E13,Event #13" "0,1" bitfld.long 0x28 12. "E12,Event #12" "0,1" newline bitfld.long 0x28 11. "E11,Event #11" "0,1" bitfld.long 0x28 10. "E10,Event #10" "0,1" newline bitfld.long 0x28 9. "E9,Event #9" "0,1" bitfld.long 0x28 8. "E8,Event #8" "0,1" newline bitfld.long 0x28 7. "E7,Event #7" "0,1" bitfld.long 0x28 6. "E6,Event #6" "0,1" newline bitfld.long 0x28 5. "E5,Event #5" "0,1" bitfld.long 0x28 4. "E4,Event #4" "0,1" newline bitfld.long 0x28 3. "E3,Event #3" "0,1" bitfld.long 0x28 2. "E2,Event #2" "0,1" newline bitfld.long 0x28 1. "E1,Event #1" "0,1" bitfld.long 0x28 0. "E0,Event #0" "0,1" line.long 0x2C "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x2C 31. "E63,Event #63" "0,1" bitfld.long 0x2C 30. "E62,Event #62" "0,1" newline bitfld.long 0x2C 29. "E61,Event #61" "0,1" bitfld.long 0x2C 28. "E60,Event #60" "0,1" newline bitfld.long 0x2C 27. "E59,Event #59" "0,1" bitfld.long 0x2C 26. "E58,Event #58" "0,1" newline bitfld.long 0x2C 25. "E57,Event #57" "0,1" bitfld.long 0x2C 24. "E56,Event #56" "0,1" newline bitfld.long 0x2C 23. "E55,Event #55" "0,1" bitfld.long 0x2C 22. "E54,Event #54" "0,1" newline bitfld.long 0x2C 21. "E53,Event #53" "0,1" bitfld.long 0x2C 20. "E52,Event #52" "0,1" newline bitfld.long 0x2C 19. "E51,Event #51" "0,1" bitfld.long 0x2C 18. "E50,Event #50" "0,1" newline bitfld.long 0x2C 17. "E49,Event #49" "0,1" bitfld.long 0x2C 16. "E48,Event #48" "0,1" newline bitfld.long 0x2C 15. "E47,Event #47" "0,1" bitfld.long 0x2C 14. "E46,Event #46" "0,1" newline bitfld.long 0x2C 13. "E45,Event #45" "0,1" bitfld.long 0x2C 12. "E44,Event #44" "0,1" newline bitfld.long 0x2C 11. "E43,Event #43" "0,1" bitfld.long 0x2C 10. "E42,Event #42" "0,1" newline bitfld.long 0x2C 9. "E41,Event #41" "0,1" bitfld.long 0x2C 8. "E40,Event #40" "0,1" newline bitfld.long 0x2C 7. "E39,Event #39" "0,1" bitfld.long 0x2C 6. "E38,Event #38" "0,1" newline bitfld.long 0x2C 5. "E37,Event #37" "0,1" bitfld.long 0x2C 4. "E36,Event #36" "0,1" newline bitfld.long 0x2C 3. "E35,Event #35" "0,1" bitfld.long 0x2C 2. "E34,Event #34" "0,1" newline bitfld.long 0x2C 1. "E33,Event #33" "0,1" bitfld.long 0x2C 0. "E32,Event #32" "0,1" line.long 0x30 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x30 31. "E31,Event #31" "0,1" bitfld.long 0x30 30. "E30,Event #30" "0,1" newline bitfld.long 0x30 29. "E29,Event #29" "0,1" bitfld.long 0x30 28. "E28,Event #28" "0,1" newline bitfld.long 0x30 27. "E27,Event #27" "0,1" bitfld.long 0x30 26. "E26,Event #26" "0,1" newline bitfld.long 0x30 25. "E25,Event #25" "0,1" bitfld.long 0x30 24. "E24,Event #24" "0,1" newline bitfld.long 0x30 23. "E23,Event #23" "0,1" bitfld.long 0x30 22. "E22,Event #22" "0,1" newline bitfld.long 0x30 21. "E21,Event #21" "0,1" bitfld.long 0x30 20. "E20,Event #20" "0,1" newline bitfld.long 0x30 19. "E19,Event #19" "0,1" bitfld.long 0x30 18. "E18,Event #18" "0,1" newline bitfld.long 0x30 17. "E17,Event #17" "0,1" bitfld.long 0x30 16. "E16,Event #16" "0,1" newline bitfld.long 0x30 15. "E15,Event #15" "0,1" bitfld.long 0x30 14. "E14,Event #14" "0,1" newline bitfld.long 0x30 13. "E13,Event #13" "0,1" bitfld.long 0x30 12. "E12,Event #12" "0,1" newline bitfld.long 0x30 11. "E11,Event #11" "0,1" bitfld.long 0x30 10. "E10,Event #10" "0,1" newline bitfld.long 0x30 9. "E9,Event #9" "0,1" bitfld.long 0x30 8. "E8,Event #8" "0,1" newline bitfld.long 0x30 7. "E7,Event #7" "0,1" bitfld.long 0x30 6. "E6,Event #6" "0,1" newline bitfld.long 0x30 5. "E5,Event #5" "0,1" bitfld.long 0x30 4. "E4,Event #4" "0,1" newline bitfld.long 0x30 3. "E3,Event #3" "0,1" bitfld.long 0x30 2. "E2,Event #2" "0,1" newline bitfld.long 0x30 1. "E1,Event #1" "0,1" bitfld.long 0x30 0. "E0,Event #0" "0,1" line.long 0x34 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x34 31. "E63,Event #63" "0,1" bitfld.long 0x34 30. "E62,Event #62" "0,1" newline bitfld.long 0x34 29. "E61,Event #61" "0,1" bitfld.long 0x34 28. "E60,Event #60" "0,1" newline bitfld.long 0x34 27. "E59,Event #59" "0,1" bitfld.long 0x34 26. "E58,Event #58" "0,1" newline bitfld.long 0x34 25. "E57,Event #57" "0,1" bitfld.long 0x34 24. "E56,Event #56" "0,1" newline bitfld.long 0x34 23. "E55,Event #55" "0,1" bitfld.long 0x34 22. "E54,Event #54" "0,1" newline bitfld.long 0x34 21. "E53,Event #53" "0,1" bitfld.long 0x34 20. "E52,Event #52" "0,1" newline bitfld.long 0x34 19. "E51,Event #51" "0,1" bitfld.long 0x34 18. "E50,Event #50" "0,1" newline bitfld.long 0x34 17. "E49,Event #49" "0,1" bitfld.long 0x34 16. "E48,Event #48" "0,1" newline bitfld.long 0x34 15. "E47,Event #47" "0,1" bitfld.long 0x34 14. "E46,Event #46" "0,1" newline bitfld.long 0x34 13. "E45,Event #45" "0,1" bitfld.long 0x34 12. "E44,Event #44" "0,1" newline bitfld.long 0x34 11. "E43,Event #43" "0,1" bitfld.long 0x34 10. "E42,Event #42" "0,1" newline bitfld.long 0x34 9. "E41,Event #41" "0,1" bitfld.long 0x34 8. "E40,Event #40" "0,1" newline bitfld.long 0x34 7. "E39,Event #39" "0,1" bitfld.long 0x34 6. "E38,Event #38" "0,1" newline bitfld.long 0x34 5. "E37,Event #37" "0,1" bitfld.long 0x34 4. "E36,Event #36" "0,1" newline bitfld.long 0x34 3. "E35,Event #35" "0,1" bitfld.long 0x34 2. "E34,Event #34" "0,1" newline bitfld.long 0x34 1. "E33,Event #33" "0,1" bitfld.long 0x34 0. "E32,Event #32" "0,1" line.long 0x38 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x38 31. "E31,Event #31" "0,1" bitfld.long 0x38 30. "E30,Event #30" "0,1" newline bitfld.long 0x38 29. "E29,Event #29" "0,1" bitfld.long 0x38 28. "E28,Event #28" "0,1" newline bitfld.long 0x38 27. "E27,Event #27" "0,1" bitfld.long 0x38 26. "E26,Event #26" "0,1" newline bitfld.long 0x38 25. "E25,Event #25" "0,1" bitfld.long 0x38 24. "E24,Event #24" "0,1" newline bitfld.long 0x38 23. "E23,Event #23" "0,1" bitfld.long 0x38 22. "E22,Event #22" "0,1" newline bitfld.long 0x38 21. "E21,Event #21" "0,1" bitfld.long 0x38 20. "E20,Event #20" "0,1" newline bitfld.long 0x38 19. "E19,Event #19" "0,1" bitfld.long 0x38 18. "E18,Event #18" "0,1" newline bitfld.long 0x38 17. "E17,Event #17" "0,1" bitfld.long 0x38 16. "E16,Event #16" "0,1" newline bitfld.long 0x38 15. "E15,Event #15" "0,1" bitfld.long 0x38 14. "E14,Event #14" "0,1" newline bitfld.long 0x38 13. "E13,Event #13" "0,1" bitfld.long 0x38 12. "E12,Event #12" "0,1" newline bitfld.long 0x38 11. "E11,Event #11" "0,1" bitfld.long 0x38 10. "E10,Event #10" "0,1" newline bitfld.long 0x38 9. "E9,Event #9" "0,1" bitfld.long 0x38 8. "E8,Event #8" "0,1" newline bitfld.long 0x38 7. "E7,Event #7" "0,1" bitfld.long 0x38 6. "E6,Event #6" "0,1" newline bitfld.long 0x38 5. "E5,Event #5" "0,1" bitfld.long 0x38 4. "E4,Event #4" "0,1" newline bitfld.long 0x38 3. "E3,Event #3" "0,1" bitfld.long 0x38 2. "E2,Event #2" "0,1" newline bitfld.long 0x38 1. "E1,Event #1" "0,1" bitfld.long 0x38 0. "E0,Event #0" "0,1" line.long 0x3C "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x3C 31. "E63,Event #63" "0,1" bitfld.long 0x3C 30. "E62,Event #62" "0,1" newline bitfld.long 0x3C 29. "E61,Event #61" "0,1" bitfld.long 0x3C 28. "E60,Event #60" "0,1" newline bitfld.long 0x3C 27. "E59,Event #59" "0,1" bitfld.long 0x3C 26. "E58,Event #58" "0,1" newline bitfld.long 0x3C 25. "E57,Event #57" "0,1" bitfld.long 0x3C 24. "E56,Event #56" "0,1" newline bitfld.long 0x3C 23. "E55,Event #55" "0,1" bitfld.long 0x3C 22. "E54,Event #54" "0,1" newline bitfld.long 0x3C 21. "E53,Event #53" "0,1" bitfld.long 0x3C 20. "E52,Event #52" "0,1" newline bitfld.long 0x3C 19. "E51,Event #51" "0,1" bitfld.long 0x3C 18. "E50,Event #50" "0,1" newline bitfld.long 0x3C 17. "E49,Event #49" "0,1" bitfld.long 0x3C 16. "E48,Event #48" "0,1" newline bitfld.long 0x3C 15. "E47,Event #47" "0,1" bitfld.long 0x3C 14. "E46,Event #46" "0,1" newline bitfld.long 0x3C 13. "E45,Event #45" "0,1" bitfld.long 0x3C 12. "E44,Event #44" "0,1" newline bitfld.long 0x3C 11. "E43,Event #43" "0,1" bitfld.long 0x3C 10. "E42,Event #42" "0,1" newline bitfld.long 0x3C 9. "E41,Event #41" "0,1" bitfld.long 0x3C 8. "E40,Event #40" "0,1" newline bitfld.long 0x3C 7. "E39,Event #39" "0,1" bitfld.long 0x3C 6. "E38,Event #38" "0,1" newline bitfld.long 0x3C 5. "E37,Event #37" "0,1" bitfld.long 0x3C 4. "E36,Event #36" "0,1" newline bitfld.long 0x3C 3. "E35,Event #35" "0,1" bitfld.long 0x3C 2. "E34,Event #34" "0,1" newline bitfld.long 0x3C 1. "E33,Event #33" "0,1" bitfld.long 0x3C 0. "E32,Event #32" "0,1" line.long 0x40 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x40 31. "E31,Event #31" "0,1" bitfld.long 0x40 30. "E30,Event #30" "0,1" newline bitfld.long 0x40 29. "E29,Event #29" "0,1" bitfld.long 0x40 28. "E28,Event #28" "0,1" newline bitfld.long 0x40 27. "E27,Event #27" "0,1" bitfld.long 0x40 26. "E26,Event #26" "0,1" newline bitfld.long 0x40 25. "E25,Event #25" "0,1" bitfld.long 0x40 24. "E24,Event #24" "0,1" newline bitfld.long 0x40 23. "E23,Event #23" "0,1" bitfld.long 0x40 22. "E22,Event #22" "0,1" newline bitfld.long 0x40 21. "E21,Event #21" "0,1" bitfld.long 0x40 20. "E20,Event #20" "0,1" newline bitfld.long 0x40 19. "E19,Event #19" "0,1" bitfld.long 0x40 18. "E18,Event #18" "0,1" newline bitfld.long 0x40 17. "E17,Event #17" "0,1" bitfld.long 0x40 16. "E16,Event #16" "0,1" newline bitfld.long 0x40 15. "E15,Event #15" "0,1" bitfld.long 0x40 14. "E14,Event #14" "0,1" newline bitfld.long 0x40 13. "E13,Event #13" "0,1" bitfld.long 0x40 12. "E12,Event #12" "0,1" newline bitfld.long 0x40 11. "E11,Event #11" "0,1" bitfld.long 0x40 10. "E10,Event #10" "0,1" newline bitfld.long 0x40 9. "E9,Event #9" "0,1" bitfld.long 0x40 8. "E8,Event #8" "0,1" newline bitfld.long 0x40 7. "E7,Event #7" "0,1" bitfld.long 0x40 6. "E6,Event #6" "0,1" newline bitfld.long 0x40 5. "E5,Event #5" "0,1" bitfld.long 0x40 4. "E4,Event #4" "0,1" newline bitfld.long 0x40 3. "E3,Event #3" "0,1" bitfld.long 0x40 2. "E2,Event #2" "0,1" newline bitfld.long 0x40 1. "E1,Event #1" "0,1" bitfld.long 0x40 0. "E0,Event #0" "0,1" line.long 0x44 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x44 31. "E63,Event #63" "0,1" bitfld.long 0x44 30. "E62,Event #62" "0,1" newline bitfld.long 0x44 29. "E61,Event #61" "0,1" bitfld.long 0x44 28. "E60,Event #60" "0,1" newline bitfld.long 0x44 27. "E59,Event #59" "0,1" bitfld.long 0x44 26. "E58,Event #58" "0,1" newline bitfld.long 0x44 25. "E57,Event #57" "0,1" bitfld.long 0x44 24. "E56,Event #56" "0,1" newline bitfld.long 0x44 23. "E55,Event #55" "0,1" bitfld.long 0x44 22. "E54,Event #54" "0,1" newline bitfld.long 0x44 21. "E53,Event #53" "0,1" bitfld.long 0x44 20. "E52,Event #52" "0,1" newline bitfld.long 0x44 19. "E51,Event #51" "0,1" bitfld.long 0x44 18. "E50,Event #50" "0,1" newline bitfld.long 0x44 17. "E49,Event #49" "0,1" bitfld.long 0x44 16. "E48,Event #48" "0,1" newline bitfld.long 0x44 15. "E47,Event #47" "0,1" bitfld.long 0x44 14. "E46,Event #46" "0,1" newline bitfld.long 0x44 13. "E45,Event #45" "0,1" bitfld.long 0x44 12. "E44,Event #44" "0,1" newline bitfld.long 0x44 11. "E43,Event #43" "0,1" bitfld.long 0x44 10. "E42,Event #42" "0,1" newline bitfld.long 0x44 9. "E41,Event #41" "0,1" bitfld.long 0x44 8. "E40,Event #40" "0,1" newline bitfld.long 0x44 7. "E39,Event #39" "0,1" bitfld.long 0x44 6. "E38,Event #38" "0,1" newline bitfld.long 0x44 5. "E37,Event #37" "0,1" bitfld.long 0x44 4. "E36,Event #36" "0,1" newline bitfld.long 0x44 3. "E35,Event #35" "0,1" bitfld.long 0x44 2. "E34,Event #34" "0,1" newline bitfld.long 0x44 1. "E33,Event #33" "0,1" bitfld.long 0x44 0. "E32,Event #32" "0,1" rgroup.long 0x1050++0x2B line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x08 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x0C "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x10 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x14 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x18 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x1C "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x20 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x24 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x28 "EDMA_TPCC_IEVAL,Interrupt Eval Register" hexmask.long 0x28 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" newline bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1080++0x17 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 7. "E7,Event #7" "0,1" newline rbitfld.long 0x04 6. "E6,Event #6" "0,1" rbitfld.long 0x04 5. "E5,Event #5" "0,1" newline rbitfld.long 0x04 4. "E4,Event #4" "0,1" rbitfld.long 0x04 3. "E3,Event #3" "0,1" newline rbitfld.long 0x04 2. "E2,Event #2" "0,1" rbitfld.long 0x04 1. "E1,Event #1" "0,1" newline rbitfld.long 0x04 0. "E0,Event #0" "0,1" line.long 0x08 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,Event #7" "0,1" newline bitfld.long 0x08 6. "E6,Event #6" "0,1" bitfld.long 0x08 5. "E5,Event #5" "0,1" newline bitfld.long 0x08 4. "E4,Event #4" "0,1" bitfld.long 0x08 3. "E3,Event #3" "0,1" newline bitfld.long 0x08 2. "E2,Event #2" "0,1" bitfld.long 0x08 1. "E1,Event #1" "0,1" newline bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,Event #7" "0,1" newline bitfld.long 0x0C 6. "E6,Event #6" "0,1" bitfld.long 0x0C 5. "E5,Event #5" "0,1" newline bitfld.long 0x0C 4. "E4,Event #4" "0,1" bitfld.long 0x0C 3. "E3,Event #3" "0,1" newline bitfld.long 0x0C 2. "E2,Event #2" "0,1" bitfld.long 0x0C 1. "E1,Event #1" "0,1" newline bitfld.long 0x0C 0. "E0,Event #0" "0,1" line.long 0x10 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 7. "E7,Event #7" "0,1" newline rbitfld.long 0x10 6. "E6,Event #6" "0,1" rbitfld.long 0x10 5. "E5,Event #5" "0,1" newline rbitfld.long 0x10 4. "E4,Event #4" "0,1" rbitfld.long 0x10 3. "E3,Event #3" "0,1" newline rbitfld.long 0x10 2. "E2,Event #2" "0,1" rbitfld.long 0x10 1. "E1,Event #1" "0,1" newline rbitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event #7" "0,1" newline bitfld.long 0x14 6. "E6,Event #6" "0,1" bitfld.long 0x14 5. "E5,Event #5" "0,1" newline bitfld.long 0x14 4. "E4,Event #4" "0,1" bitfld.long 0x14 3. "E3,Event #3" "0,1" newline bitfld.long 0x14 2. "E2,Event #2" "0,1" bitfld.long 0x14 1. "E1,Event #1" "0,1" newline bitfld.long 0x14 0. "E0,Event #0" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2200++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2600++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2204++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2604++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2208++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2608++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x220C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x260C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2210++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2610++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2214++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2614++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2218++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2618++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x221C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x261C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2220++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2620++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2224++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2624++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2228++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2628++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x222C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x262C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2230++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2630++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2234++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2634++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2238++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2638++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x223C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x263C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2240++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2640++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2244++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2644++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2250++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2650++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2254++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2654++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2258++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2658++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x225C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x265C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2260++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2660++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2264++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2664++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2268++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2668++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x226C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x266C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2270++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2670++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2274++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2674++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2278++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2678++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2A78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2C78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2E78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2280++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2680++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2284++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2684++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2288++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2688++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x228C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x268C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2290++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2690++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2294++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2694++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4020++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_1,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4060++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_3,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_5,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_6,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_7,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4100++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_8,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4120++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_9,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4140++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4160++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_11,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4180++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_12,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_13,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_14,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_15,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4200++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4220++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_17,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4240++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_18,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4260++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_19,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4280++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_20,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_21,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_22,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_23,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4300++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_24,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4320++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_25,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4340++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_26,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4360++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_27,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4380++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_28,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_29,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_30,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_31,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4400++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4420++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_33,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4440++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_34,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4460++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_35,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4480++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_36,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_37,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_38,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_39,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4500++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_40,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4520++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_41,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4540++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_42,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4560++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_43,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4580++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_44,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_45,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_46,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_47,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4600++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4620++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_49,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4640++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_50,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4660++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_51,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4680++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_52,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_53,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_54,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_55,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4700++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_56,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4720++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_57,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4740++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_58,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4760++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_59,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4780++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_60,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_61,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_62,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_63,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4800++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4820++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_65,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4840++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_66,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4860++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_67,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4880++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_68,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_69,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_70,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_71,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4900++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_72,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4920++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_73,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4940++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_74,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4960++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_75,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4980++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_76,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_77,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_78,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_79,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_81,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_82,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_83,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_84,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_85,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_86,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_87,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_88,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_89,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_90,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_91,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_92,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_93,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_94,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_95,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_96,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_97,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_98,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_99,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_101,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_102,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_103,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_104,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_105,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_106,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_107,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_108,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_109,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_110,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_111,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_113,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_114,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_115,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_116,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_117,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_118,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_119,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_120,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_121,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_122,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_123,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_124,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_125,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_126,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_127,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" group.long 0x4024++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_1,Source Address" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" group.long 0x4064++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_3,Source Address" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" group.long 0x40A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_5,Source Address" group.long 0x40C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_6,Source Address" group.long 0x40E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_7,Source Address" group.long 0x4104++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_8,Source Address" group.long 0x4124++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_9,Source Address" group.long 0x4144++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_10,Source Address" group.long 0x4164++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_11,Source Address" group.long 0x4184++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_12,Source Address" group.long 0x41A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_13,Source Address" group.long 0x41C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_14,Source Address" group.long 0x41E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_15,Source Address" group.long 0x4204++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_16,Source Address" group.long 0x4224++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_17,Source Address" group.long 0x4244++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_18,Source Address" group.long 0x4264++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_19,Source Address" group.long 0x4284++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_20,Source Address" group.long 0x42A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_21,Source Address" group.long 0x42C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_22,Source Address" group.long 0x42E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_23,Source Address" group.long 0x4304++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_24,Source Address" group.long 0x4324++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_25,Source Address" group.long 0x4344++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_26,Source Address" group.long 0x4364++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_27,Source Address" group.long 0x4384++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_28,Source Address" group.long 0x43A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_29,Source Address" group.long 0x43C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_30,Source Address" group.long 0x43E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_31,Source Address" group.long 0x4404++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_32,Source Address" group.long 0x4424++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_33,Source Address" group.long 0x4444++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_34,Source Address" group.long 0x4464++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_35,Source Address" group.long 0x4484++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_36,Source Address" group.long 0x44A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_37,Source Address" group.long 0x44C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_38,Source Address" group.long 0x44E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_39,Source Address" group.long 0x4504++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_40,Source Address" group.long 0x4524++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_41,Source Address" group.long 0x4544++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_42,Source Address" group.long 0x4564++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_43,Source Address" group.long 0x4584++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_44,Source Address" group.long 0x45A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_45,Source Address" group.long 0x45C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_46,Source Address" group.long 0x45E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_47,Source Address" group.long 0x4604++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_48,Source Address" group.long 0x4624++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_49,Source Address" group.long 0x4644++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_50,Source Address" group.long 0x4664++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_51,Source Address" group.long 0x4684++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_52,Source Address" group.long 0x46A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_53,Source Address" group.long 0x46C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_54,Source Address" group.long 0x46E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_55,Source Address" group.long 0x4704++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_56,Source Address" group.long 0x4724++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_57,Source Address" group.long 0x4744++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_58,Source Address" group.long 0x4764++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_59,Source Address" group.long 0x4784++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_60,Source Address" group.long 0x47A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_61,Source Address" group.long 0x47C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_62,Source Address" group.long 0x47E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_63,Source Address" group.long 0x4804++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_64,Source Address" group.long 0x4824++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_65,Source Address" group.long 0x4844++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_66,Source Address" group.long 0x4864++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_67,Source Address" group.long 0x4884++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_68,Source Address" group.long 0x48A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_69,Source Address" group.long 0x48C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_70,Source Address" group.long 0x48E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_71,Source Address" group.long 0x4904++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_72,Source Address" group.long 0x4924++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_73,Source Address" group.long 0x4944++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_74,Source Address" group.long 0x4964++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_75,Source Address" group.long 0x4984++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_76,Source Address" group.long 0x49A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_77,Source Address" group.long 0x49C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_78,Source Address" group.long 0x49E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_79,Source Address" group.long 0x4A04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_80,Source Address" group.long 0x4A24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_81,Source Address" group.long 0x4A44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_82,Source Address" group.long 0x4A64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_83,Source Address" group.long 0x4A84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_84,Source Address" group.long 0x4AA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_85,Source Address" group.long 0x4AC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_86,Source Address" group.long 0x4AE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_87,Source Address" group.long 0x4B04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_88,Source Address" group.long 0x4B24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_89,Source Address" group.long 0x4B44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_90,Source Address" group.long 0x4B64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_91,Source Address" group.long 0x4B84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_92,Source Address" group.long 0x4BA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_93,Source Address" group.long 0x4BC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_94,Source Address" group.long 0x4BE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_95,Source Address" group.long 0x4C04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_96,Source Address" group.long 0x4C24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_97,Source Address" group.long 0x4C44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_98,Source Address" group.long 0x4C64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_99,Source Address" group.long 0x4C84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_100,Source Address" group.long 0x4CA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_101,Source Address" group.long 0x4CC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_102,Source Address" group.long 0x4CE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_103,Source Address" group.long 0x4D04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_104,Source Address" group.long 0x4D24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_105,Source Address" group.long 0x4D44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_106,Source Address" group.long 0x4D64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_107,Source Address" group.long 0x4D84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_108,Source Address" group.long 0x4DA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_109,Source Address" group.long 0x4DC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_110,Source Address" group.long 0x4DE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_111,Source Address" group.long 0x4E04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_112,Source Address" group.long 0x4E24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_113,Source Address" group.long 0x4E44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_114,Source Address" group.long 0x4E64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_115,Source Address" group.long 0x4E84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_116,Source Address" group.long 0x4EA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_117,Source Address" group.long 0x4EC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_118,Source Address" group.long 0x4EE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_119,Source Address" group.long 0x4F04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_120,Source Address" group.long 0x4F24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_121,Source Address" group.long 0x4F44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_122,Source Address" group.long 0x4F64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_123,Source Address" group.long 0x4F84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_124,Source Address" group.long 0x4FA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_125,Source Address" group.long 0x4FC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_126,Source Address" group.long 0x4FE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_127,Source Address" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x402C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_1,Destination Address" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x406C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_3,Destination Address" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x40AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_5,Destination Address" group.long 0x40CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_6,Destination Address" group.long 0x40EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_7,Destination Address" group.long 0x410C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_8,Destination Address" group.long 0x412C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_9,Destination Address" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x416C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_11,Destination Address" group.long 0x418C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_12,Destination Address" group.long 0x41AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_13,Destination Address" group.long 0x41CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_14,Destination Address" group.long 0x41EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_15,Destination Address" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x422C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_17,Destination Address" group.long 0x424C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_18,Destination Address" group.long 0x426C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_19,Destination Address" group.long 0x428C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_20,Destination Address" group.long 0x42AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_21,Destination Address" group.long 0x42CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_22,Destination Address" group.long 0x42EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_23,Destination Address" group.long 0x430C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_24,Destination Address" group.long 0x432C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_25,Destination Address" group.long 0x434C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_26,Destination Address" group.long 0x436C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_27,Destination Address" group.long 0x438C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_28,Destination Address" group.long 0x43AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_29,Destination Address" group.long 0x43CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_30,Destination Address" group.long 0x43EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_31,Destination Address" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x442C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_33,Destination Address" group.long 0x444C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_34,Destination Address" group.long 0x446C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_35,Destination Address" group.long 0x448C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_36,Destination Address" group.long 0x44AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_37,Destination Address" group.long 0x44CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_38,Destination Address" group.long 0x44EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_39,Destination Address" group.long 0x450C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_40,Destination Address" group.long 0x452C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_41,Destination Address" group.long 0x454C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_42,Destination Address" group.long 0x456C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_43,Destination Address" group.long 0x458C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_44,Destination Address" group.long 0x45AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_45,Destination Address" group.long 0x45CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_46,Destination Address" group.long 0x45EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_47,Destination Address" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x462C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_49,Destination Address" group.long 0x464C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_50,Destination Address" group.long 0x466C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_51,Destination Address" group.long 0x468C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_52,Destination Address" group.long 0x46AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_53,Destination Address" group.long 0x46CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_54,Destination Address" group.long 0x46EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_55,Destination Address" group.long 0x470C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_56,Destination Address" group.long 0x472C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_57,Destination Address" group.long 0x474C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_58,Destination Address" group.long 0x476C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_59,Destination Address" group.long 0x478C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_60,Destination Address" group.long 0x47AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_61,Destination Address" group.long 0x47CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_62,Destination Address" group.long 0x47EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_63,Destination Address" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x482C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_65,Destination Address" group.long 0x484C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_66,Destination Address" group.long 0x486C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_67,Destination Address" group.long 0x488C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_68,Destination Address" group.long 0x48AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_69,Destination Address" group.long 0x48CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_70,Destination Address" group.long 0x48EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_71,Destination Address" group.long 0x490C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_72,Destination Address" group.long 0x492C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_73,Destination Address" group.long 0x494C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_74,Destination Address" group.long 0x496C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_75,Destination Address" group.long 0x498C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_76,Destination Address" group.long 0x49AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_77,Destination Address" group.long 0x49CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_78,Destination Address" group.long 0x49EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_79,Destination Address" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_81,Destination Address" group.long 0x4A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_82,Destination Address" group.long 0x4A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_83,Destination Address" group.long 0x4A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_84,Destination Address" group.long 0x4AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_85,Destination Address" group.long 0x4ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_86,Destination Address" group.long 0x4AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_87,Destination Address" group.long 0x4B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_88,Destination Address" group.long 0x4B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_89,Destination Address" group.long 0x4B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_90,Destination Address" group.long 0x4B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_91,Destination Address" group.long 0x4B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_92,Destination Address" group.long 0x4BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_93,Destination Address" group.long 0x4BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_94,Destination Address" group.long 0x4BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_95,Destination Address" group.long 0x4C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_96,Destination Address" group.long 0x4C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_97,Destination Address" group.long 0x4C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_98,Destination Address" group.long 0x4C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_99,Destination Address" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_101,Destination Address" group.long 0x4CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_102,Destination Address" group.long 0x4CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_103,Destination Address" group.long 0x4D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_104,Destination Address" group.long 0x4D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_105,Destination Address" group.long 0x4D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_106,Destination Address" group.long 0x4D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_107,Destination Address" group.long 0x4D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_108,Destination Address" group.long 0x4DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_109,Destination Address" group.long 0x4DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_110,Destination Address" group.long 0x4DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_111,Destination Address" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_113,Destination Address" group.long 0x4E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_114,Destination Address" group.long 0x4E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_115,Destination Address" group.long 0x4E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_116,Destination Address" group.long 0x4EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_117,Destination Address" group.long 0x4ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_118,Destination Address" group.long 0x4EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_119,Destination Address" group.long 0x4F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_120,Destination Address" group.long 0x4F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_121,Destination Address" group.long 0x4F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_122,Destination Address" group.long 0x4F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_123,Destination Address" group.long 0x4F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_124,Destination Address" group.long 0x4FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_125,Destination Address" group.long 0x4FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_126,Destination Address" group.long 0x4FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_127,Destination Address" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_1," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_3," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_5," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_6," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_7," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_8," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_9," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_11," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_12," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_13," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_14," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_15," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_17," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_18," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_19," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_20," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_21," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_22," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_23," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_24," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_25," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_26," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_27," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_28," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_29," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_30," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_31," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_33," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_34," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_35," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_36," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_37," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_38," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_39," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_40," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_41," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_42," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_43," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_44," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_45," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_46," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_47," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_49," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_50," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_51," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_52," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_53," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_54," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_55," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_56," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_57," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_58," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_59," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_60," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_61," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_62," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_63," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_65," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_66," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_67," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_68," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_69," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_70," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_71," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_72," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_73," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_74," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_75," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_76," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_77," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_78," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_79," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_81," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_82," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_83," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_84," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_85," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_86," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_87," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_88," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_89," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_90," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_91," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_92," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_93," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_94," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_95," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_96," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_97," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_98," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_99," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_101," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_102," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_103," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_104," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_105," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_106," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_107," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_108," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_109," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_110," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_111," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_113," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_114," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_115," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_116," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_117," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_118," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_119," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_120," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_121," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_122," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_123," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_124," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_125," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_126," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_127," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x403C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x407C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x411C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x413C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x417C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x419C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x423C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x425C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x427C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x429C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x431C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x433C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x435C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x437C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x439C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x443C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x445C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x447C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x449C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x451C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x453C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x455C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x457C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x459C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x463C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x465C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x467C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x469C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x471C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x473C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x475C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x477C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x479C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x483C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x485C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x487C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x489C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x491C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x493C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x495C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x497C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x499C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x1D05000 ad:0x1D06000 ) tree "DSP_EDMA_TPTC$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPTCn_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPTCn_TCCFG,TC Configuration Register" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 8.--9. "DREGDEPTH,Destination Register FIFO Depth Parameterization" "0,1,2,3" bitfld.long 0x04 6.--7. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" group.long 0x100++0x13 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 11.--12. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" rbitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" rbitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" line.long 0x04 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" rbitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x08 "EDMA_TPTCn_INTEN,Interrupt Enable Register" hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x0C "EDMA_TPTCn_INTCLR,Interrupt Clear Register" hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x10 "EDMA_TPTCn_INTCMD,Interrupt Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" group.long 0x120++0x13 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" rbitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 1. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" line.long 0x04 "EDMA_TPTCn_ERREN,Error Enable Register" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x04 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x04 1. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" line.long 0x08 "EDMA_TPTCn_ERRCLR,Error Clear Register" hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x08 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x08 1. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" line.long 0x0C "EDMA_TPTCn_ERRDET,Error Details Register" hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0C 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" rbitfld.long 0x0C 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 14.--15. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EDMA_TPTCn_ERRCMD,Error Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" group.long 0x200++0x17 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" rbitfld.long 0x00 21. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" rbitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "Highest priority,Priority 1,?,?,?,?,?,Lowest priority" newline rbitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" line.long 0x08 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count" line.long 0x0C "EDMA_TPTCn_PDST,Program Set Destination Address" line.long 0x10 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" line.long 0x14 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x240++0x23 line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" line.long 0x08 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" line.long 0x0C "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved. return 0x0 w/o AERROR" line.long 0x10 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" line.long 0x14 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" line.long 0x1C "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" line.long 0x20 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" group.long 0x280++0x0B line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" line.long 0x04 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" line.long 0x08 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" group.long 0x300++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x304++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x344++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x308++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x348++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x30C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x34C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x350++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" group.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x354++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end repeat.end tree "DSP_FW_L2_NOC_CFG" base ad:0x1D03000 group.long 0x00++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0,Core 0 Error log register" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" newline rbitfld.long 0x00 26. "RESERVED," "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" bitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x40++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 2.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x88++0x17 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" line.long 0x08 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1,Start physical address of region 1" hexmask.long 0x08 4.--31. 1. "RESERVED," bitfld.long 0x08 0.--3. "START_REGION_1,Physical target start address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1,End physical address of region 1" bitfld.long 0x0C 31. "END_REGION_1_ENABLE,End Region 1 enable" "0,1" hexmask.long 0x0C 4.--30. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "END_REGION_1,Physical target end address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_1,RM_PERMISSION_REGION_1_LOW register" hexmask.long.word 0x10 16.--31. 1. "RESERVED," bitfld.long 0x10 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x10 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x10 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x10 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x10 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x10 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x10 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x10 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x10 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_1,RM_PERMISSION_REGION_1_HIGH register" bitfld.long 0x14 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x14 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x14 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x14 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x14 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x14 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x14 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x14 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x14 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x14 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x14 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x14 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x14 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x14 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x14 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x14 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x14 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x14 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x14 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x14 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x14 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x14 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x14 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x14 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x14 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x14 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x14 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x14 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x14 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x14 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x14 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x14 0. "R0,Initiator ID0 permission" "0,1" group.long 0x1000++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0,Core 0 Error log register" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" newline rbitfld.long 0x00 26. "RESERVED," "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" bitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x1040++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 2.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x1088++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" rgroup.long 0x4000++0x17 line.long 0x00 "DSPNOC_FLAGMUX_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_FLAGMUX_ID_REVISIONID," line.long 0x08 "DSPNOC_FLAGMUX_FAULTEN," hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "FAULTEN,Global Fault Enable register" "0,1" line.long 0x0C "DSPNOC_FLAGMUX_FAULTSTATUS," hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "FAULTSTATUS,Global Fault Status register" "0,1" line.long 0x10 "DSPNOC_FLAGMUX_FLAGINEN0," hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" line.long 0x14 "DSPNOC_FLAGMUX_FLAGINSTATUS0," hexmask.long 0x14 1.--31. 1. "RESERVED," bitfld.long 0x14 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" rgroup.long 0x4200++0x1B line.long 0x00 "DSPNOC_ERRORLOG_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_ERRORLOG_ID_REVISIONID," line.long 0x08 "DSPNOC_ERRORLOG_FAULTEN," hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "FAULTEN,Enable Fault output" "0,1" line.long 0x0C "DSPNOC_ERRORLOG_ERRVLD," hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "ERRVLD,Error logged Valid" "0,1" line.long 0x10 "DSPNOC_ERRORLOG_ERRCLR," hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "ERRCLR,Clr ErrVld status" "0,1" line.long 0x14 "DSPNOC_ERRORLOG_ERRLOG0,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x14 31. "FORMAT,Format of ErrLog0 register" "0,1" bitfld.long 0x14 28.--30. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--27. 1. "LEN1,Header: Len1 value" bitfld.long 0x14 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x14 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0. "LOCK,Header: Lock bit value" "0,1" line.long 0x18 "DSPNOC_ERRORLOG_ERRLOG1," hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED," hexmask.long.word 0x18 0.--14. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x4220++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG3," bitfld.long 0x00 31. "RESERVED," "0,1" hexmask.long 0x00 0.--30. 1. "ERRLOG3,Header: Addr lsb value" rgroup.long 0x4228++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG5," hexmask.long.word 0x00 22.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--21. 1. "ERRLOG5,Header: User lsb value" width 0x0B tree.end tree "DSP_SYSTEM" base ad:0x1D00000 rgroup.long 0x00++0x1B line.long 0x00 "DSP_SYS_REVISION," line.long 0x04 "DSP_SYS_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," bitfld.long 0x04 0.--3. "NUM,Instance Number Set by subsystem input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DSP_SYS_SYSCONFIG," hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 8. "RESERVED,Reserved" "0,1" rbitfld.long 0x08 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x08 4.--5. "STANDBYMODE," "?,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x08 2.--3. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x08 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x0C "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode" hexmask.long 0x0C 6.--31. 1. "RESERVED," bitfld.long 0x0C 4.--5. "OCPI_DISC_STAT,L3_MAIN (OCP) Initiator(s) Disconnect Status" "OCPI_DISC_STAT_0_r,OCPI_DISC_STAT_1_r,OCPI_DISC_STAT_2_r,?" bitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "TC1_STAT,EDMA TC1 Status" "TC1_STAT_0,TC1_STAT_1" bitfld.long 0x0C 1. "TC0_STAT,EDMA TC0 Status" "TC0_STAT_0,TC0_STAT_1" bitfld.long 0x0C 0. "C66X_STAT,C66x Status" "C66X_STAT_0,C66X_STAT_1" line.long 0x10 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "OCPI_DISC,OCP Initiator (on L3_MAIN) Disconnect request" "OCPI_DISC_0_w,OCPI_DISC_1_w" line.long 0x14 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators" rbitfld.long 0x14 31. "RESERVED," "0,1" bitfld.long 0x14 28.--30. "SDMA_PRI,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port" "0,1,2,3,4,5,6,7" rbitfld.long 0x14 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 24. "NOPOSTOVERRIDE,OCP Posted Write vs Non-Posted Write override" "NOPOSTOVERRIDE_0,NOPOSTOVERRIDE_1" rbitfld.long 0x14 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x14 20.--21. "SDMA_L2PRES,OCP Target port L2 Interconnect Pressure" "SDMA_L2PRES_0,SDMA_L2PRES_1,SDMA_L2PRES_2,SDMA_L2PRES_3" newline rbitfld.long 0x14 18.--19. "RESERVED," "0,1,2,3" bitfld.long 0x14 16.--17. "CFG_L2PRES,DSP CFG L2 Interconnect Pressure" "CFG_L2PRES_0,CFG_L2PRES_1,CFG_L2PRES_2,CFG_L2PRES_3" rbitfld.long 0x14 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 12.--13. "TC1_L2PRES,TC1 L2 Interconnect Pressure" "TC1_L2PRES_0,TC1_L2PRES_1,TC1_L2PRES_2,TC1_L2PRES_3" rbitfld.long 0x14 10.--11. "RESERVED," "0,1,2,3" bitfld.long 0x14 8.--9. "TC0_L2PRES,TC0 L2 Interconnect Pressure" "TC0_L2PRES_0,TC0_L2PRES_1,TC0_L2PRES_2,TC0_L2PRES_3" newline rbitfld.long 0x14 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x14 4.--5. "TC1_DBS,TC1 Default Burst size" "TC1_DBS_0,TC1_DBS_1,TC1_DBS_2,TC1_DBS_3" rbitfld.long 0x14 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 0.--1. "TC0_DBS,TC0 Default Burst size" "TC0_DBS_0,TC0_DBS_1,TC0_DBS_2,TC0_DBS_3" line.long 0x18 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs" hexmask.long.tbyte 0x18 13.--31. 1. "RESERVED," bitfld.long 0x18 12. "MMU1_ABORT,MU1 Abort" "MMU1_ABORT_0,MMU1_ABORT_1" rbitfld.long 0x18 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "MMU0_ABORT,MU0 Abort" "MMU0_ABORT_0,MMU0_ABORT_1" rbitfld.long 0x18 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 4. "MMU1_EN,MU1 Enable" "MMU1_EN_0,MMU1_EN_1" newline rbitfld.long 0x18 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 0. "MMU0_EN,MU1 Enable" "MMU0_EN_0,MMU0_EN_1" group.long 0x20++0x07 line.long 0x00 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x30++0x07 line.long 0x00 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x40++0x07 line.long 0x00 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state" line.long 0x04 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state" group.long 0x50++0x2F line.long 0x00 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.word 0x00 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--18. 1. "EVENT,Settable raw status for event #n" line.long 0x04 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector" hexmask.long.word 0x04 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x04 0.--18. 1. "EVENT,Clearable enabled status for event #n" line.long 0x08 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" hexmask.long.word 0x08 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x08 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x0C "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" hexmask.long.word 0x0C 19.--31. 1. "RESERVED," hexmask.long.tbyte 0x0C 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x10 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x14 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x18 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x1C "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" line.long 0x20 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x24 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x28 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x2C "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" group.long 0xF8++0x07 line.long 0x00 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus" hexmask.long 0x00 4.--31. 1. "RESERVED," bitfld.long 0x00 0.--3. "GROUP,Debug Group output control mux selectN: GN = select output group N" "GROUP_0,GROUP_1,GROUP_2,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group" width 0x0B tree.end tree "DSS" base ad:0x58000000 rgroup.long 0x00++0x03 line.long 0x00 "DSS_REVISION,This register contains the DSS revision number" group.long 0x10++0x0F line.long 0x00 "DSS_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long.word 0x00 17.--31. 1. "RESERVED," rbitfld.long 0x00 16. "RESERVED," "0,1" hexmask.long.word 0x00 5.--15. 1. "RESERVED," newline rbitfld.long 0x00 4. "RESERVED," "0,1" rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "SIDLEMODE," "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" line.long 0x04 "DSS_SYSSTATUS,This register provides status information about the module" hexmask.long 0x04 7.--31. 1. "RESERVED," bitfld.long 0x04 6. "VENC_RESETDONE,Reset status of VENC module" "VENC_RESETDONE_0,VENC_RESETDONE_1" bitfld.long 0x04 5. "RESERVED," "0,1" newline bitfld.long 0x04 4. "RESERVED," "0,1" bitfld.long 0x04 3. "RESERVED," "0,1" bitfld.long 0x04 2. "RESERVED," "0,1" newline bitfld.long 0x04 1. "RESERVED," "0,1" bitfld.long 0x04 0. "DSS_RESETDONE,Reset status of DISPC/DSS" "DSS_RESETDONE_0,DSS_RESETDONE_1" line.long 0x08 "DSS_VENC_CTRL,This register contains control bits corresponding to the VENC instance in DSS" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 2. "DAC_POWERDN_BGZ,DAC power down band gap control" "DAC_POWERDN_BGZ_0,DAC_POWERDN_BGZ_1" bitfld.long 0x08 1. "DAC_DEMEN,DAC Dynamic Element Matching Enable" "DAC_DEMEN_0,DAC_DEMEN_1" newline bitfld.long 0x08 0. "VENC_CLOCK_4X_ENABLE,VENC Clock CLK4X Enable" "VENC_CLOCK_4X_ENABLE_0,VENC_CLOCK_4X_ENABLE_1" line.long 0x0C "DSS_DPI_CTRL,This register contains control bits corresponding to the DPI interface in DSS" hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "DPI_ENABLE,Enable DPI interface" "DPI_ENABLE_0,DPI_ENABLE_1" group.long 0x40++0x03 line.long 0x00 "DSS_DEBUG_CFG,Debug configuration" hexmask.long 0x00 3.--31. 1. "RESERVED," bitfld.long 0x00 0.--2. "CFG,Defines which debug bus to provide on the DSS debug bus connected at the top" "CFG_0,CFG_1,CFG_2,CFG_3,CFG_4,CFG_5,?,?" width 0x0B tree.end tree "DSS_CM_CORE" base ad:0x4A009100 group.long 0x00++0x0B line.long 0x00 "CM_DSS_CLKSTCTRL,This register enables the DSS domain power state transition" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "CLKACTIVITY_HDMI_PHY_GFCLK,This field indicates the state of the HDMI_PHY_GFCLK clock in the domain" "CLKACTIVITY_HDMI_PHY_GFCLK_0,CLKACTIVITY_HDMI_PHY_GFCLK_1" newline rbitfld.long 0x00 17. "CLKACTIVITY_HDMI_CEC_GFCLK,This field indicates the state of the HDMI_CEC_GFCLK clock in the domain" "CLKACTIVITY_HDMI_CEC_GFCLK_0,CLKACTIVITY_HDMI_CEC_GFCLK_1" rbitfld.long 0x00 16. "CLKACTIVITY_DSS_SYS_GFCLK,This field indicates the state of the DSS_SYS_GFCLK clock in the domain" "CLKACTIVITY_DSS_SYS_GFCLK_0,CLKACTIVITY_DSS_SYS_GFCLK_1" newline rbitfld.long 0x00 15. "CLKACTIVITY_DSS_L4_GICLK,This field indicates the state of the DSS_L4_GICLK clock in the domain" "CLKACTIVITY_DSS_L4_GICLK_0,CLKACTIVITY_DSS_L4_GICLK_1" rbitfld.long 0x00 14. "CLKACTIVITY_SDVENC_GFCLK,This field indicates the state of the SDVENC_GFCLK clock in the domain" "CLKACTIVITY_SDVENC_GFCLK_0,CLKACTIVITY_SDVENC_GFCLK_1" newline rbitfld.long 0x00 13. "CLKACTIVITY_BB2D_GFCLK,This field indicates the state of the BB2D_GFCLK clock in the domain" "CLKACTIVITY_BB2D_GFCLK_0,CLKACTIVITY_BB2D_GFCLK_1" rbitfld.long 0x00 12. "CLKACTIVITY_VIDEO2_DPLL_CLK,This field indicates the state of the VIDEO2_PHY_GFCLK clock in the domain" "CLKACTIVITY_VIDEO2_DPLL_CLK_0,CLKACTIVITY_VIDEO2_DPLL_CLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_HDMI_DPLL_CLK,This field indicates the state of the HDMI_DPLL_CLK clock in the domain" "CLKACTIVITY_HDMI_DPLL_CLK_0,CLKACTIVITY_HDMI_DPLL_CLK_1" rbitfld.long 0x00 10. "CLKACTIVITY_VIDEO1_DPLL_CLK,This field indicates the state of the VIDEO1_DPLL_CLK clock in the domain" "CLKACTIVITY_VIDEO1_DPLL_CLK_0,CLKACTIVITY_VIDEO1_DPLL_CLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_DSS_GFCLK,This field indicates the state of the DSS_GFCLK clock in the domain" "CLKACTIVITY_DSS_GFCLK_0,CLKACTIVITY_DSS_GFCLK_1" rbitfld.long 0x00 8. "CLKACTIVITY_DSS_L3_GICLK,This field indicates the state of the DSS_L3_GICLK clock in the domain" "CLKACTIVITY_DSS_L3_GICLK_0,CLKACTIVITY_DSS_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSS clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_DSS_STATICDEP,This register controls the static domain depedencies from DSS domain towards 'target' domains" hexmask.long 0x04 6.--31. 1. "RESERVED," rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" line.long 0x08 "CM_DSS_DYNAMICDEP,This register controls the dynamic domain depedencies from DSS domain towards 'target' domains" hexmask.long 0x08 6.--31. 1. "RESERVED," bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 domain" "L3MAIN1_DYNDEP_0,?" newline bitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20++0x03 line.long 0x00 "CM_DSS_DSS_CLKCTRL,This register manages the DSS clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" rbitfld.long 0x00 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 13. "OPTFCLKEN_VIDEO2_CLK,Optional functional clock control" "OPTFCLKEN_VIDEO2_CLK_0,OPTFCLKEN_VIDEO2_CLK_1" bitfld.long 0x00 12. "OPTFCLKEN_VIDEO1_CLK,Optional functional clock control" "OPTFCLKEN_VIDEO1_CLK_0,OPTFCLKEN_VIDEO1_CLK_1" newline bitfld.long 0x00 11. "OPTFCLKEN_32KHZ_CLK,Optional functional clock control" "OPTFCLKEN_32KHZ_CLK_0,OPTFCLKEN_32KHZ_CLK_1" bitfld.long 0x00 10. "OPTFCLKEN_HDMI_CLK,Optional functional clock control" "OPTFCLKEN_HDMI_CLK_0,OPTFCLKEN_HDMI_CLK_1" newline bitfld.long 0x00 9. "OPTFCLKEN_48MHZ_CLK,Optional functional clock control" "OPTFCLKEN_48MHZ_CLK_0,OPTFCLKEN_48MHZ_CLK_1" bitfld.long 0x00 8. "OPTFCLKEN_DSSCLK,Optional functional clock control" "OPTFCLKEN_DSSCLK_0,OPTFCLKEN_DSSCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x30++0x03 line.long 0x00 "CM_DSS_BB2D_CLKCTRL,This register manages the BB2D clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x3C++0x03 line.long 0x00 "CM_DSS_SDVENC_CLKCTRL,This register manages the SDVENC clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "DSS_FW" base ad:0x4A21C000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "DSS_FW_CFG_TARG" base ad:0x4A21D000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DSS_PRM" base ad:0x4AE07100 group.long 0x00++0x07 line.long 0x00 "PM_DSS_PWRSTCTRL,This register controls the DSS power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "DSS_MEM_ONSTATE,DSS_MEM state when domain is ON" "?,?,?,DSS_MEM_ONSTATE_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," rbitfld.long 0x00 8. "DSS_MEM_RETSTATE,DSS_MEM state when domain is RETENTION" "DSS_MEM_RETSTATE_0,?" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" rbitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION" "LOGICRETSTATE_0,?" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_DSS_PWRSTST,This register provides a status on the current DSS power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "DSS_MEM_STATEST,DSS_MEM state status" "DSS_MEM_STATEST_0,DSS_MEM_STATEST_1,DSS_MEM_STATEST_2,DSS_MEM_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x20++0x0B line.long 0x00 "PM_DSS_DSS_WKDEP,This register controls wakeup dependency based on DSS service requests" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x00 29. "WKUPDEP_DSI1_B_EVE4,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_EVE4_0,WKUPDEP_DSI1_B_EVE4_1" newline bitfld.long 0x00 28. "WKUPDEP_DSI1_B_EVE3,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_EVE3_0,WKUPDEP_DSI1_B_EVE3_1" bitfld.long 0x00 27. "WKUPDEP_DSI1_B_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_EVE2_0,WKUPDEP_DSI1_B_EVE2_1" newline bitfld.long 0x00 26. "WKUPDEP_DSI1_B_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_EVE1_0,WKUPDEP_DSI1_B_EVE1_1" bitfld.long 0x00 25. "WKUPDEP_DSI1_B_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_DSP2_0,WKUPDEP_DSI1_B_DSP2_1" newline bitfld.long 0x00 24. "WKUPDEP_DSI1_B_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_IPU1_0,WKUPDEP_DSI1_B_IPU1_1" bitfld.long 0x00 23. "WKUPDEP_DSI1_B_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_SDMA_0,WKUPDEP_DSI1_B_SDMA_1" newline bitfld.long 0x00 22. "WKUPDEP_DSI1_B_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_DSP1_0,WKUPDEP_DSI1_B_DSP1_1" bitfld.long 0x00 21. "WKUPDEP_DSI1_B_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_IPU2_0,WKUPDEP_DSI1_B_IPU2_1" newline bitfld.long 0x00 20. "WKUPDEP_DSI1_B_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_MPU_0,WKUPDEP_DSI1_B_MPU_1" bitfld.long 0x00 19. "WKUPDEP_DSI1_A_EVE4,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_EVE4_0,WKUPDEP_DSI1_A_EVE4_1" newline bitfld.long 0x00 18. "WKUPDEP_DSI1_A_EVE3,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_EVE3_0,WKUPDEP_DSI1_A_EVE3_1" bitfld.long 0x00 17. "WKUPDEP_DSI1_A_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_EVE2_0,WKUPDEP_DSI1_A_EVE2_1" newline bitfld.long 0x00 16. "WKUPDEP_DSI1_A_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_EVE1_0,WKUPDEP_DSI1_A_EVE1_1" bitfld.long 0x00 15. "WKUPDEP_DSI1_A_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_DSP2_0,WKUPDEP_DSI1_A_DSP2_1" newline bitfld.long 0x00 14. "WKUPDEP_DSI1_A_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_IPU1_0,WKUPDEP_DSI1_A_IPU1_1" bitfld.long 0x00 13. "WKUPDEP_DSI1_A_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_SDMA_0,WKUPDEP_DSI1_A_SDMA_1" newline bitfld.long 0x00 12. "WKUPDEP_DSI1_A_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_DSP1_0,WKUPDEP_DSI1_A_DSP1_1" bitfld.long 0x00 11. "WKUPDEP_DSI1_A_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_IPU2_0,WKUPDEP_DSI1_A_IPU2_1" newline bitfld.long 0x00 10. "WKUPDEP_DSI1_A_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_MPU_0,WKUPDEP_DSI1_A_MPU_1" bitfld.long 0x00 9. "WKUPDEP_DISPC_EVE4,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_EVE4_0,WKUPDEP_DISPC_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_DISPC_EVE3,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_EVE3_0,WKUPDEP_DISPC_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_DISPC_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_EVE2_0,WKUPDEP_DISPC_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_DISPC_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_EVE1_0,WKUPDEP_DISPC_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_DISPC_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_DSP2_0,WKUPDEP_DISPC_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_DISPC_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_IPU1_0,WKUPDEP_DISPC_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_DISPC_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_SDMA_0,WKUPDEP_DISPC_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_DISPC_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_DSP1_0,WKUPDEP_DISPC_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_DISPC_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_IPU2_0,WKUPDEP_DISPC_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_DISPC_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_MPU_0,WKUPDEP_DISPC_MPU_1" line.long 0x04 "RM_DSS_DSS_CONTEXT,This register contains dedicated DSS context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_DSS_MEM,Specify if memory-based context in DSS_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSS_MEM_0,LOSTMEM_DSS_MEM_1" newline rbitfld.long 0x04 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_DSS_DSS2_WKDEP,This register controls wakeup dependency based on DSS service requests" rbitfld.long 0x08 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 25. "WKUPDEP_HDMIDMA_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIDMA_DSP2_0,WKUPDEP_HDMIDMA_DSP2_1" newline rbitfld.long 0x08 24. "RESERVED," "0,1" bitfld.long 0x08 23. "WKUPDEP_HDMIDMA_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIDMA_SDMA_0,WKUPDEP_HDMIDMA_SDMA_1" newline bitfld.long 0x08 22. "WKUPDEP_HDMIDMA_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIDMA_DSP1_0,WKUPDEP_HDMIDMA_DSP1_1" rbitfld.long 0x08 20.--21. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 19. "WKUPDEP_DSI1_C_EVE4,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_EVE4_0,WKUPDEP_DSI1_C_EVE4_1" bitfld.long 0x08 18. "WKUPDEP_DSI1_C_EVE3,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_EVE3_0,WKUPDEP_DSI1_C_EVE3_1" newline bitfld.long 0x08 17. "WKUPDEP_DSI1_C_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_EVE2_0,WKUPDEP_DSI1_C_EVE2_1" bitfld.long 0x08 16. "WKUPDEP_DSI1_C_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_EVE1_0,WKUPDEP_DSI1_C_EVE1_1" newline bitfld.long 0x08 15. "WKUPDEP_DSI1_C_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_DSP2_0,WKUPDEP_DSI1_C_DSP2_1" bitfld.long 0x08 14. "WKUPDEP_DSI1_C_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_IPU1_0,WKUPDEP_DSI1_C_IPU1_1" newline bitfld.long 0x08 13. "WKUPDEP_DSI1_C_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_SDMA_0,WKUPDEP_DSI1_C_SDMA_1" bitfld.long 0x08 12. "WKUPDEP_DSI1_C_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_DSP1_0,WKUPDEP_DSI1_C_DSP1_1" newline bitfld.long 0x08 11. "WKUPDEP_DSI1_C_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_IPU2_0,WKUPDEP_DSI1_C_IPU2_1" bitfld.long 0x08 10. "WKUPDEP_DSI1_C_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_MPU_0,WKUPDEP_DSI1_C_MPU_1" newline bitfld.long 0x08 9. "WKUPDEP_HDMIIRQ_EVE4,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_EVE4_0,WKUPDEP_HDMIIRQ_EVE4_1" bitfld.long 0x08 8. "WKUPDEP_HDMIIRQ_EVE3,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_EVE3_0,WKUPDEP_HDMIIRQ_EVE3_1" newline bitfld.long 0x08 7. "WKUPDEP_HDMIIRQ_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_EVE2_0,WKUPDEP_HDMIIRQ_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_HDMIIRQ_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_EVE1_0,WKUPDEP_HDMIIRQ_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_HDMIIRQ_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_DSP2_0,WKUPDEP_HDMIIRQ_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_HDMIIRQ_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_IPU1_0,WKUPDEP_HDMIIRQ_IPU1_1" newline rbitfld.long 0x08 3. "RESERVED," "0,1" bitfld.long 0x08 2. "WKUPDEP_HDMIIRQ_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_DSP1_0,WKUPDEP_HDMIIRQ_DSP1_1" newline bitfld.long 0x08 1. "WKUPDEP_HDMIIRQ_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_IPU2_0,WKUPDEP_HDMIIRQ_IPU2_1" bitfld.long 0x08 0. "WKUPDEP_HDMIIRQ_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_MPU_0,WKUPDEP_HDMIIRQ_MPU_1" group.long 0x34++0x03 line.long 0x00 "RM_DSS_BB2D_CONTEXT,This register contains dedicated BB2B context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_DSS_MEM,Specify if memory-based context in DSS_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSS_MEM_0,LOSTMEM_DSS_MEM_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x3C++0x03 line.long 0x00 "RM_DSS_SDVENC_CONTEXT,This register contains dedicated SDVENC context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "DSS_TARG" base ad:0x44002900 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "EDMA_TC0_FW_CFG_TARG" base ad:0x4A164000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "EDMA_TPCC_FW" base ad:0x4A161000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "EDMA_TPCC_FW_CFG_TARG" base ad:0x4A162000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "EDMA_TPCC_TARG" base ad:0x44002000 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "ELM" base ad:0x48078000 rgroup.long 0x00++0x03 line.long 0x00 "ELM_REVISION,This register contains the IP revision code" group.long 0x10++0x13 line.long 0x00 "ELM_SYSCONFIG,This register allows controlling various parameters of the OCP interface" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "CLOCKACTIVITYOCP,OCP clock activity when module is in IDLE mode (during wake-up mode period)" "CLOCKACTIVITYOCP_0,CLOCKACTIVITYOCP_1" newline rbitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3.--4. "SIDLEMODE,Slave interface power management (IDLE req/ack control)" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" newline rbitfld.long 0x00 2. "RESERVED,Reserved" "0,1" bitfld.long 0x00 1. "SOFTRESET,Module software reset This bit is automatically reset by hardware (during reads it always returns 0)" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOGATING,Internal OCP clock gating strategy (no module visible effect other than saving power)" "AUTOGATING_0,AUTOGATING_1" line.long 0x04 "ELM_SYSSTATUS,Internal reset monitoring (OCP domain) Undefined since: From hardware perspective. the reset state is 0" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring (OCP domain) Undefined since: From hardware perspective the reset state is 0" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "ELM_IRQSTATUS,Interrupt status" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 8. "PAGE_VALID,Error-location status for a full page based on the mask definition Read" "No effect,Clear interrupt" newline bitfld.long 0x08 7. "LOC_VALID_7,Error-location status for syndrome polynomial 7" "No effect,Clear interrupt" bitfld.long 0x08 6. "LOC_VALID_6,Error-location status for syndrome polynomial 6" "0,1" newline bitfld.long 0x08 5. "LOC_VALID_5,Error-location status for syndrome polynomial 5" "0,1" bitfld.long 0x08 4. "LOC_VALID_4,Error-location status for syndrome polynomial 4" "0,1" newline bitfld.long 0x08 3. "LOC_VALID_3,Error-location status for syndrome polynomial 3" "0,1" bitfld.long 0x08 2. "LOC_VALID_2,Error-location status for syndrome polynomial 2" "0,1" newline bitfld.long 0x08 1. "LOC_VALID_1,Error-location status for syndrome polynomial 1" "0,1" bitfld.long 0x08 0. "LOC_VALID_0,Error-location status for syndrome polynomial 0" "0,1" line.long 0x0C "ELM_IRQENABLE,Interrupt enable" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 8. "PAGE_MASK,Page interrupt mask bit" "Disable interrupt,Enable interrupt" newline bitfld.long 0x0C 7. "LOCATION_MASK_7,Error-location interrupt mask bit for syndrome polynomial 7" "0,1" bitfld.long 0x0C 6. "LOCATION_MASK_6,Error-location interrupt mask bit for syndrome polynomial 6" "0,1" newline bitfld.long 0x0C 5. "LOCATION_MASK_5,Error-location interrupt mask bit for syndrome polynomial 5" "0,1" bitfld.long 0x0C 4. "LOCATION_MASK_4,Error-location interrupt mask bit for syndrome polynomial 4" "0,1" newline bitfld.long 0x0C 3. "LOCATION_MASK_3,Error-location interrupt mask bit for syndrome polynomial 3" "0,1" bitfld.long 0x0C 2. "LOCATION_MASK_2,Error-location interrupt mask bit for syndrome polynomial 2" "0,1" newline bitfld.long 0x0C 1. "LOCATION_MASK_1,Error-location interrupt mask bit for syndrome polynomial 1" "0,1" bitfld.long 0x0C 0. "LOCATION_MASK_0,Error-location interrupt mask bit for syndrome polynomial 0" "Disable interrupt,Enable interrupt" line.long 0x10 "ELM_LOCATION_CONFIG,ECC algorithm parameters" rbitfld.long 0x10 27.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x10 16.--26. 1. "ECC_SIZE,Maximum size of the buffers for which the error-location engine is used in number of nibbles (4-bit entities)" newline hexmask.long.word 0x10 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x10 0.--1. "ECC_BCH_LEVEL,Error correction level" "4 bits,8 bits,16 bits,Reserved" group.long 0x80++0x03 line.long 0x00 "ELM_PAGE_CTRL,Page definition" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "SECTOR_7,Set to 1 if syndrome polynomial 7 is part of the page in page mode" "0,1" newline bitfld.long 0x00 6. "SECTOR_6,Set to 1 if syndrome polynomial 6 is part of the page in page mode" "0,1" bitfld.long 0x00 5. "SECTOR_5,Set to 1 if syndrome polynomial 5 is part of the page in page mode" "0,1" newline bitfld.long 0x00 4. "SECTOR_4,Set to 1 if syndrome polynomial 4 is part of the page in page mode" "0,1" bitfld.long 0x00 3. "SECTOR_3,Set to 1 if syndrome polynomial 3 is part of the page in page mode" "0,1" newline bitfld.long 0x00 2. "SECTOR_2,Set to 1 if syndrome polynomial 2 is part of the page in page mode" "0,1" bitfld.long 0x00 1. "SECTOR_1,Set to 1 if syndrome polynomial 1 is part of the page in page mode" "0,1" newline bitfld.long 0x00 0. "SECTOR_0,Set to 1 if syndrome polynomial 0 is part of the page in page mode" "0,1" group.long 0x400++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_0,Input syndrome polynomial bits 0 to 31" group.long 0x440++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_1,Input syndrome polynomial bits 0 to 31" group.long 0x480++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_2,Input syndrome polynomial bits 0 to 31" group.long 0x4C0++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_3,Input syndrome polynomial bits 0 to 31" group.long 0x500++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_4,Input syndrome polynomial bits 0 to 31" group.long 0x540++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_5,Input syndrome polynomial bits 0 to 31" group.long 0x580++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_6,Input syndrome polynomial bits 0 to 31" group.long 0x5C0++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_7,Input syndrome polynomial bits 0 to 31" group.long 0x404++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_0,Input syndrome polynomial bits 32 to 63" group.long 0x444++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_1,Input syndrome polynomial bits 32 to 63" group.long 0x484++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_2,Input syndrome polynomial bits 32 to 63" group.long 0x4C4++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_3,Input syndrome polynomial bits 32 to 63" group.long 0x504++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_4,Input syndrome polynomial bits 32 to 63" group.long 0x544++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_5,Input syndrome polynomial bits 32 to 63" group.long 0x584++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_6,Input syndrome polynomial bits 32 to 63" group.long 0x5C4++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i_7,Input syndrome polynomial bits 32 to 63" group.long 0x408++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_0,Input syndrome polynomial bits 64 to 95" group.long 0x448++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_1,Input syndrome polynomial bits 64 to 95" group.long 0x488++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_2,Input syndrome polynomial bits 64 to 95" group.long 0x4C8++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_3,Input syndrome polynomial bits 64 to 95" group.long 0x508++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_4,Input syndrome polynomial bits 64 to 95" group.long 0x548++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_5,Input syndrome polynomial bits 64 to 95" group.long 0x588++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_6,Input syndrome polynomial bits 64 to 95" group.long 0x5C8++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i_7,Input syndrome polynomial bits 64 to 95" group.long 0x40C++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_0,Input syndrome polynomial bits 96 to 127" group.long 0x44C++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_1,Input syndrome polynomial bits 96 to 127" group.long 0x48C++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_2,Input syndrome polynomial bits 96 to 127" group.long 0x4CC++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_3,Input syndrome polynomial bits 96 to 127" group.long 0x50C++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_4,Input syndrome polynomial bits 96 to 127" group.long 0x54C++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_5,Input syndrome polynomial bits 96 to 127" group.long 0x58C++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_6,Input syndrome polynomial bits 96 to 127" group.long 0x5CC++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i_7,Input syndrome polynomial bits 96 to 127" group.long 0x410++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_0,Input syndrome polynomial bits 128 to 159" group.long 0x450++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_1,Input syndrome polynomial bits 128 to 159" group.long 0x490++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_2,Input syndrome polynomial bits 128 to 159" group.long 0x4D0++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_3,Input syndrome polynomial bits 128 to 159" group.long 0x510++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_4,Input syndrome polynomial bits 128 to 159" group.long 0x550++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_5,Input syndrome polynomial bits 128 to 159" group.long 0x590++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_6,Input syndrome polynomial bits 128 to 159" group.long 0x5D0++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i_7,Input syndrome polynomial bits 128 to 159" group.long 0x414++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_0,Input syndrome polynomial bits 160 to 191" group.long 0x454++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_1,Input syndrome polynomial bits 160 to 191" group.long 0x494++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_2,Input syndrome polynomial bits 160 to 191" group.long 0x4D4++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_3,Input syndrome polynomial bits 160 to 191" group.long 0x514++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_4,Input syndrome polynomial bits 160 to 191" group.long 0x554++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_5,Input syndrome polynomial bits 160 to 191" group.long 0x594++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_6,Input syndrome polynomial bits 160 to 191" group.long 0x5D4++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i_7,Input syndrome polynomial bits 160 to 191" group.long 0x418++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_0,Input syndrome polynomial bits 192 to 207" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" newline hexmask.long.word 0x00 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" group.long 0x458++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_1,Input syndrome polynomial bits 192 to 207" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" newline hexmask.long.word 0x00 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" group.long 0x498++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_2,Input syndrome polynomial bits 192 to 207" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" newline hexmask.long.word 0x00 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" group.long 0x4D8++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_3,Input syndrome polynomial bits 192 to 207" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" newline hexmask.long.word 0x00 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" group.long 0x518++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_4,Input syndrome polynomial bits 192 to 207" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" newline hexmask.long.word 0x00 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" group.long 0x558++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_5,Input syndrome polynomial bits 192 to 207" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" newline hexmask.long.word 0x00 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" group.long 0x598++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_6,Input syndrome polynomial bits 192 to 207" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" newline hexmask.long.word 0x00 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" group.long 0x5D8++0x03 line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i_7,Input syndrome polynomial bits 192 to 207" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" newline hexmask.long.word 0x00 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" rgroup.long 0x800++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_0,Exit status for the syndrome polynomial processing" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x900++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_1,Exit status for the syndrome polynomial processing" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_2,Exit status for the syndrome polynomial processing" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xB00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_3,Exit status for the syndrome polynomial processing" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xC00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_4,Exit status for the syndrome polynomial processing" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xD00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_5,Exit status for the syndrome polynomial processing" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xE00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_6,Exit status for the syndrome polynomial processing" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xF00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_7,Exit status for the syndrome polynomial processing" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x880++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x980++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x884++0x03 line.long 0x00 "ELM_ERROR_LOCATION_1_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x984++0x03 line.long 0x00 "ELM_ERROR_LOCATION_1_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA84++0x03 line.long 0x00 "ELM_ERROR_LOCATION_1_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB84++0x03 line.long 0x00 "ELM_ERROR_LOCATION_1_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC84++0x03 line.long 0x00 "ELM_ERROR_LOCATION_1_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD84++0x03 line.long 0x00 "ELM_ERROR_LOCATION_1_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE84++0x03 line.long 0x00 "ELM_ERROR_LOCATION_1_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF84++0x03 line.long 0x00 "ELM_ERROR_LOCATION_1_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x888++0x03 line.long 0x00 "ELM_ERROR_LOCATION_2_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x988++0x03 line.long 0x00 "ELM_ERROR_LOCATION_2_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA88++0x03 line.long 0x00 "ELM_ERROR_LOCATION_2_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB88++0x03 line.long 0x00 "ELM_ERROR_LOCATION_2_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC88++0x03 line.long 0x00 "ELM_ERROR_LOCATION_2_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD88++0x03 line.long 0x00 "ELM_ERROR_LOCATION_2_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE88++0x03 line.long 0x00 "ELM_ERROR_LOCATION_2_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF88++0x03 line.long 0x00 "ELM_ERROR_LOCATION_2_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x88C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_3_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x98C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_3_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA8C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_3_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB8C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_3_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC8C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_3_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD8C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_3_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE8C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_3_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF8C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_3_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x890++0x03 line.long 0x00 "ELM_ERROR_LOCATION_4_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x990++0x03 line.long 0x00 "ELM_ERROR_LOCATION_4_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA90++0x03 line.long 0x00 "ELM_ERROR_LOCATION_4_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB90++0x03 line.long 0x00 "ELM_ERROR_LOCATION_4_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC90++0x03 line.long 0x00 "ELM_ERROR_LOCATION_4_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD90++0x03 line.long 0x00 "ELM_ERROR_LOCATION_4_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE90++0x03 line.long 0x00 "ELM_ERROR_LOCATION_4_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF90++0x03 line.long 0x00 "ELM_ERROR_LOCATION_4_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x894++0x03 line.long 0x00 "ELM_ERROR_LOCATION_5_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x994++0x03 line.long 0x00 "ELM_ERROR_LOCATION_5_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA94++0x03 line.long 0x00 "ELM_ERROR_LOCATION_5_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB94++0x03 line.long 0x00 "ELM_ERROR_LOCATION_5_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC94++0x03 line.long 0x00 "ELM_ERROR_LOCATION_5_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD94++0x03 line.long 0x00 "ELM_ERROR_LOCATION_5_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE94++0x03 line.long 0x00 "ELM_ERROR_LOCATION_5_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF94++0x03 line.long 0x00 "ELM_ERROR_LOCATION_5_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x898++0x03 line.long 0x00 "ELM_ERROR_LOCATION_6_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x998++0x03 line.long 0x00 "ELM_ERROR_LOCATION_6_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA98++0x03 line.long 0x00 "ELM_ERROR_LOCATION_6_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB98++0x03 line.long 0x00 "ELM_ERROR_LOCATION_6_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC98++0x03 line.long 0x00 "ELM_ERROR_LOCATION_6_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD98++0x03 line.long 0x00 "ELM_ERROR_LOCATION_6_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE98++0x03 line.long 0x00 "ELM_ERROR_LOCATION_6_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF98++0x03 line.long 0x00 "ELM_ERROR_LOCATION_6_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x89C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_7_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x99C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_7_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA9C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_7_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB9C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_7_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC9C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_7_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD9C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_7_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE9C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_7_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF9C++0x03 line.long 0x00 "ELM_ERROR_LOCATION_7_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8A0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_8_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9A0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_8_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xAA0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_8_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBA0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_8_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCA0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_8_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDA0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_8_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEA0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_8_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFA0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_8_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8A4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_9_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9A4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_9_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xAA4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_9_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBA4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_9_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCA4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_9_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDA4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_9_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEA4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_9_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFA4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_9_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8A8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_10_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9A8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_10_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xAA8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_10_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBA8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_10_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCA8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_10_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDA8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_10_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEA8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_10_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFA8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_10_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8AC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_11_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9AC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_11_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xAAC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_11_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBAC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_11_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCAC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_11_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDAC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_11_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEAC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_11_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFAC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_11_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8B0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_12_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9B0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_12_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xAB0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_12_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBB0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_12_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCB0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_12_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDB0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_12_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEB0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_12_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFB0++0x03 line.long 0x00 "ELM_ERROR_LOCATION_12_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8B4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_13_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9B4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_13_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xAB4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_13_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBB4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_13_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCB4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_13_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDB4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_13_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEB4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_13_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFB4++0x03 line.long 0x00 "ELM_ERROR_LOCATION_13_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8B8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_14_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9B8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_14_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xAB8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_14_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBB8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_14_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCB8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_14_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDB8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_14_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEB8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_14_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFB8++0x03 line.long 0x00 "ELM_ERROR_LOCATION_14_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8BC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_15_i_0,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9BC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_15_i_1,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xABC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_15_i_2,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBBC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_15_i_3,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCBC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_15_i_4,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDBC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_15_i_5,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEBC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_15_i_6,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFBC++0x03 line.long 0x00 "ELM_ERROR_LOCATION_15_i_7,Error-location register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" width 0x0B tree.end tree "ELM_TARG" base ad:0x48079000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "EMIF" base ad:0x4C000000 rgroup.long 0x00++0x43 line.long 0x00 "EMIF_REVISION,Revision number register" line.long 0x04 "EMIF_STATUS,SDRAM Status Register (STATUS)" bitfld.long 0x04 31. "BE,Big endian mode select for 8 and 16-bit devices set to 1 for big endian or 0 for little endian operation" "0,1" newline bitfld.long 0x04 30. "DUAL_CLK_MODE,Dual Clock mode" "0,1" newline bitfld.long 0x04 29. "FAST_INIT,Fast Init" "0,1" newline hexmask.long.tbyte 0x04 7.--28. 1. "RESERVED,Reserved" newline bitfld.long 0x04 6. "RDLVLGATETO,Read DQS Gate Training Timeout" "0,1" newline bitfld.long 0x04 5. "RDLVLTO,Read Data Eye Training Timeout" "0,1" newline bitfld.long 0x04 4. "WRLVLTO,Write Leveling Timeout" "0,1" newline bitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "PHY_DLL_READY,DDR PHY Ready" "0,1" newline bitfld.long 0x04 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x08 "EMIF_SDRAM_CONFIG,SDRAM Config Register" bitfld.long 0x08 29.--31. "SDRAM_TYPE,SDRAM Type selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 27.--28. "IBANK_POS,Internal bank position" "0,1,2,3" newline bitfld.long 0x08 24.--26. "DDR_TERM,DDR3 termination resistor value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 23. "DDR2_DDQS,Differential DQS enable" "0,1" newline bitfld.long 0x08 21.--22. "DYN_ODT,DDR3 Dynamic ODT.Not supported" "0,1,2,3" newline bitfld.long 0x08 20. "DDR_DISABLE_DLL,Disable DLL select" "0,1" newline bitfld.long 0x08 18.--19. "SDRAM_DRIVE,SDRAM drive strength" "0,1,2,3" newline bitfld.long 0x08 16.--17. "CWL,DDR3 CAS Write latency" "0,1,2,3" newline bitfld.long 0x08 14.--15. "NARROW_MODE,SDRAM data bus width" "0,1,2,3" newline bitfld.long 0x08 10.--13. "CL,CAS Latency (referred to as read latency (RL) in some SDRAM specs)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 7.--9. "ROWSIZE,Row Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 4.--6. "IBANK,Internal Bank setup" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 0.--2. "PAGESIZE,Page Size" "0,1,2,3,4,5,6,7" line.long 0x0C "EMIF_SDRAM_CONFIG_2,SDRAM Config Register 2 CAUTION: This register is loaded with values by control module at device reset" rbitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 27. "EBANK_POS,External bank position" "0,1" newline hexmask.long 0x0C 0.--26. 1. "RESERVED," line.long 0x10 "EMIF_SDRAM_REFRESH_CONTROL,SDRAM Refresh Control Register" bitfld.long 0x10 31. "INITREF_DIS,Initialization and Refresh disable" "0,1" newline rbitfld.long 0x10 30. "RESERVED," "0,1" newline bitfld.long 0x10 29. "SRT,DDR3 Self Refresh temperature range" "0,1" newline bitfld.long 0x10 28. "ASR,DDR3 Auto Self Refresh enable" "0,1" newline rbitfld.long 0x10 27. "RESERVED," "0,1" newline bitfld.long 0x10 24.--26. "PASR,Partial Array Self Refresh" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 16.--23. 1. "RESERVED," newline hexmask.long.word 0x10 0.--15. 1. "REFRESH_RATE,Refresh Rate" line.long 0x14 "EMIF_SDRAM_REFRESH_CONTROL_SHADOW,SDRAM Refresh Control Shadow Register" hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x14 0.--15. 1. "REFRESH_RATE_SHDW,Shadow field for REFRESH_RATE" line.long 0x18 "EMIF_SDRAM_TIMING_1,SDRAM Timing 1 Register" bitfld.long 0x18 29.--31. "T_RTW,Minimum number of DDR clock cycles between Read to Write data phases minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 25.--28. "T_RP,Minimum number of DDR clock cycles from Precharge to Activate or Refresh minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 21.--24. "T_RCD,Minimum number of DDR clock cycles from Activate to Read or Write minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 17.--20. "T_WR,Minimum number of DDR clock cycles from last Write transfer to Precharge minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 12.--16. "T_RAS,Minimum number of DDR clock cycles from Activate to Precharge minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 6.--11. "T_RC,Minimum number of DDR clock cycles from Activate to Activate minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x18 3.--5. "T_RRD,Minimum number of DDR clock cycles from Activate to Activate for a different bank minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "T_WTR,Minimum number of DDR clock cycles from last Write to Read minus one" "0,1,2,3,4,5,6,7" line.long 0x1C "EMIF_SDRAM_TIMING_1_SHADOW,SDRAM Timing 1 Shadow Register" bitfld.long 0x1C 29.--31. "T_RTW_SHDW,Shadow field for T_RTW" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 25.--28. "T_RP_SHDW,Shadow field for T_RP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 21.--24. "T_RCD_SHDW,Shadow field for T_RCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 17.--20. "T_WR_SHDW,Shadow field for T_WR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 12.--16. "T_RAS_SHDW,Shadow field for T_RAS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 6.--11. "T_RC_SHDW,Shadow field for T_RC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x1C 3.--5. "T_RRD_SHDW,Shadow field for T_RRD" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0.--2. "T_WTR_SHDW,Shadow field for T_WTR" "0,1,2,3,4,5,6,7" line.long 0x20 "EMIF_SDRAM_TIMING_2,SDRAM Timing 2 Register" rbitfld.long 0x20 31. "RESERVED,Reserved" "0,1" newline bitfld.long 0x20 28.--30. "T_XP,Minimum number of DDR clock cycles from power-down exit to any command other than a read command minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 25.--27. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 16.--24. 1. "T_XSNR,Minimum number of DDR clock cycles from Self-Refresh exit to any command other than a Read command minus one" newline hexmask.long.word 0x20 6.--15. 1. "T_XSRD,Minimum number of DDR clock cycles from Self-Refresh exit to a Read command minus one" newline bitfld.long 0x20 3.--5. "T_RTP,Minimum number of DDR clock cycles for the last read command to a Precharge command minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "T_CKE,Minimum number of DDR clock cycles between CKE pin changes minus one" "0,1,2,3,4,5,6,7" line.long 0x24 "EMIF_SDRAM_TIMING_2_SHADOW,SDRAM Timing 2 Shadow Register" rbitfld.long 0x24 31. "RESERVED,Reserved" "0,1" newline bitfld.long 0x24 28.--30. "T_XP_SHDW,Shadow field for T_XP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 25.--27. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x24 16.--24. 1. "T_XSNR_SHDW,Shadow field for T_XSNR" newline hexmask.long.word 0x24 6.--15. 1. "T_XSRD_SHDW,Shadow field for T_XSRD" newline bitfld.long 0x24 3.--5. "T_RTP_SHDW,Shadow field for T_RTP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0.--2. "T_CKE_SHDW,Shadow field for T_CKE" "0,1,2,3,4,5,6,7" line.long 0x28 "EMIF_SDRAM_TIMING_3,SDRAM Timing 3 Register" bitfld.long 0x28 28.--31. "T_PDLL_UL,Minimum number of DDR clock cycles for PHY DLL to unlock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x28 24.--27. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 21.--23. "T_CKESR,Minimum number of DDR clock cycles for which SDRAM must remain in Self Refresh minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 15.--20. "ZQ_ZQCS,Number of DDR clock cycles for a ZQCS command minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x28 13.--14. "T_TDQSCKMAX,Number of DDR clock that satisfies tDQSCKmax for LPDDR2 minus one" "0,1,2,3" newline hexmask.long.word 0x28 4.--12. 1. "T_RFC,Minimum number of DDR clock cycles from Refresh or Load Mode to Refresh or Activate minus one" newline bitfld.long 0x28 0.--3. "T_RAS_MAX,Maximum number of REFRESH_RATE intervals from Activate to Precharge command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "EMIF_SDRAM_TIMING_3_SHADOW,SDRAM Timing 3 Shadow Register" bitfld.long 0x2C 28.--31. "T_PDLL_UL_SHDW,Shadow field for T_PDLL_UL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C 24.--27. "T_CSTA_SHDW,Shadow field for T_CSTA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C 21.--23. "T_CKESR_SHDW,Shadow field for T_CKESR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 15.--20. "ZQ_ZQCS_SHDW,Shadow field for ZQ_ZQCS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x2C 13.--14. "T_TDQSCKMAX_SHDW,Shadow field for T_TDQSCKMAX" "0,1,2,3" newline hexmask.long.word 0x2C 4.--12. 1. "T_RFC_SHDW,Shadow field for T_RFC" newline bitfld.long 0x2C 0.--3. "T_RAS_MAX_SHDW,Shadow field for T_RAS_MAX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x30 "EMIF_LPDDR2_NVM_TIMING,NOTE: This register is not supported" line.long 0x34 "EMIF_LPDDR2_NVM_TIMING_SHADOW,NOTE: This register is not supported" line.long 0x38 "EMIF_POWER_MANAGEMENT_CONTROL,Power Management Control Register" hexmask.long.word 0x38 16.--31. 1. "RESERVED," newline bitfld.long 0x38 12.--15. "PD_TIM,Power Management timer for Power-Down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x38 11. "DPD_EN,Deep Power Down enable" "0,1" newline bitfld.long 0x38 8.--10. "LP_MODE,Automatic Power Management enable" "Disable automatic power management,Reserved,Self Refresh mode,Disable automatic power management,Power-Down mode All other values disable..,?..." newline bitfld.long 0x38 4.--7. "SR_TIM,Power Management timer for Self Refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x38 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x3C "EMIF_POWER_MANAGEMENT_CONTROL_SHADOW,Power Management Control Shadow Register" hexmask.long.word 0x3C 16.--31. 1. "RESERVED," newline bitfld.long 0x3C 12.--15. "PD_TIM_SHDW,Shadow field for PD_TIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x3C 8.--11. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3C 4.--7. "SR_TIM_SHDW,Shadow field for SR_TIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3C 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x40 "EMIF_LPDDR2_MODE_REG_DATA,LPDDR2 Mode Reg Data Register A write to this register will cause a Mode Register write command to be sent to the LPDDR2 device with write data as specified in the VALUE_0 field" hexmask.long 0x40 7.--31. 1. "RESERVED," newline hexmask.long.byte 0x40 0.--6. 1. "VALUE_0,Mode register value" group.long 0x50++0x13 line.long 0x00 "EMIF_LPDDR2_MODE_REG_CONFIG,LPDDR2 Mode Reg Config Register" bitfld.long 0x00 31. "CS,Chip select to issue mode register command" "0,1" newline bitfld.long 0x00 30. "REFRESH_EN,Refresh Enable after MRW" "0,1" newline hexmask.long.tbyte 0x00 8.--29. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--7. 1. "ADDRESS,Mode register address" line.long 0x04 "EMIF_OCP_CONFIG,OCP Config Register" rbitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 24.--27. "SYS_THRESH_MAX,System OCP Threshold Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.tbyte 0x04 0.--23. 1. "RESERVED," line.long 0x08 "EMIF_OCP_CONFIG_VALUE_1,OCP Config Value 1 Register" bitfld.long 0x08 30.--31. "SYS_BUS_WIDTH,System OCP data bus width" "32-bit wide,64-bit wide,128-bit wide,Reserved" newline hexmask.long.word 0x08 16.--29. 1. "RESERVED," newline hexmask.long.byte 0x08 8.--15. 1. "WR_FIFO_DEPTH,Write Data FIFO depth" newline hexmask.long.byte 0x08 0.--7. 1. "CMD_FIFO_DEPTH,Command FIFO depth" line.long 0x0C "EMIF_OCP_CONFIG_VALUE_2,OCP Config Value 2 Register" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0C 16.--23. 1. "RREG_FIFO_DEPTH,Register Read Data FIFO depth" newline hexmask.long.byte 0x0C 8.--15. 1. "RSD_FIFO_DEPTH,SDRAM Read Data FIFO depth" newline hexmask.long.byte 0x0C 0.--7. 1. "RCMD_FIFO_DEPTH,Read Command FIFO depth" line.long 0x10 "EMIF_IODFT_TLGC," hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x10 15. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 14. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 13. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 12. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x10 11. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 10. "RESET_PHY,Reset the DDR PHY" "0,1" newline rbitfld.long 0x10 9. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 8. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x10 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x10 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x10 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0. "RESERVED,Reserved" "0,1" rgroup.long 0x80++0x27 line.long 0x00 "EMIF_PERFORMANCE_COUNTER_1,Performance Counter 1 Register" line.long 0x04 "EMIF_PERFORMANCE_COUNTER_2,Performance Counter 2 Register" line.long 0x08 "EMIF_PERFORMANCE_COUNTER_CONFIG,Performance Counter Config Register" bitfld.long 0x08 31. "CNTR2_MCONNID_EN,MConnID filter enable forEMIF_PERFORMANCE_COUNTER_2 register" "0,1" newline bitfld.long 0x08 30. "CNTR2_REGION_EN,Chip Select filter enable forEMIF_PERFORMANCE_COUNTER_2 register" "0,1" newline hexmask.long.word 0x08 20.--29. 1. "RESERVED,Reserved for future use" newline bitfld.long 0x08 16.--19. "CNTR2_CFG,Filter configuration forEMIF_PERFORMANCE_COUNTER_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 15. "CNTR1_MCONNID_EN,MConnID filter enable forEMIF_PERFORMANCE_COUNTER_1 register" "0,1" newline bitfld.long 0x08 14. "CNTR1_REGION_EN,Chip Select filter enable forEMIF_PERFORMANCE_COUNTER_1 register" "0,1" newline hexmask.long.word 0x08 4.--13. 1. "RESERVED,Reserved for future use" newline bitfld.long 0x08 0.--3. "CNTR1_CFG,Filter configuration forEMIF_PERFORMANCE_COUNTER_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT,Performance Counter Master Region Select Register The values programmed into the MCONNIDx fields are those in the ConnID Valuestable in . Interconnect" hexmask.long.byte 0x0C 24.--31. 1. "MCONNID2,MConnID forEMIF_PERFORMANCE_COUNTER_2 register" newline hexmask.long.byte 0x0C 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0C 8.--15. 1. "MCONNID1,MConnID forEMIF_PERFORMANCE_COUNTER_1 register" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Reserved" line.long 0x10 "EMIF_PERFORMANCE_COUNTER_TIME,Performance Counter Time Register" line.long 0x14 "EMIF_MISC_REG," hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "DLL_CALIB_OS,Phy_dll_calib one shot : Setting bit to 1 generates a phy_pll_calib pulse" "0,1" line.long 0x18 "EMIF_DLL_CALIB_CTRL,Control register to force idle window time to generate a phy_dll_calib that can be used for updating PHY DLLs during voltage ramps" hexmask.long.word 0x18 20.--31. 1. "RESERVED," newline bitfld.long 0x18 16.--19. "ACK_WAIT,The ack_wait determines the required wait time after a phy_dll_calib is generated before another command can be sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x18 9.--15. 1. "RESERVED," newline hexmask.long.word 0x18 0.--8. 1. "DLL_CALIB_INTERVAL,This field determines the interval between phy_dll_calib generation" line.long 0x1C "EMIF_DLL_CALIB_CTRL_SHADOW,Read Idle Control Shadow Register" hexmask.long.word 0x1C 20.--31. 1. "RESERVED," newline bitfld.long 0x1C 16.--19. "ACK_WAIT_SHDW,Shadow field for ACK_WAIT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x1C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x1C 0.--8. 1. "DLL_CALIB_INTERVAL_SHDW,Shadow field for DLL_CALIB_INTERVAL" line.long 0x20 "EMIF_END_OF_INTERRUPT," hexmask.long 0x20 1.--31. 1. "RESERVED," newline bitfld.long 0x20 0. "EOI,Software End Of Interrupt (EOI) control" "0,1" line.long 0x24 "EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS,System OCP Interrupt Raw Status Register" hexmask.long 0x24 6.--31. 1. "RESERVED," newline bitfld.long 0x24 5. "ONEBIT_ECC_ERR_SYS,Raw status of system ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x24 4. "TWOBIT_ECC_ERR_SYS,Raw status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x24 3. "WR_ECC_ERR_SYS,Raw status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location" "0,1" newline rbitfld.long 0x24 2. "RESERVED," "0,1" newline bitfld.long 0x24 1. "TA_SYS,Raw status of system OCP interrupt for SDRAM temperature alert" "0,1" newline bitfld.long 0x24 0. "ERR_SYS,Raw status of system OCP interrupt for command or address error" "0,1" group.long 0xAC++0x03 line.long 0x00 "EMIF_SYSTEM_OCP_INTERRUPT_STATUS,System OCP Interrupt Status Register" hexmask.long 0x00 6.--31. 1. "RESERVED," newline bitfld.long 0x00 5. "ONEBIT_ECC_ERR_SYS,Enabled status of system ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x00 4. "TWOBIT_ECC_ERR_SYS,Enabled status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location" "0,1" newline rbitfld.long 0x00 2. "RESERVED," "0,1" newline bitfld.long 0x00 1. "TA_SYS,Enabled status of system OCP interrupt for SDRAM temperature alert" "0,1" newline bitfld.long 0x00 0. "ERR_SYS,Enabled status of system OCP interrupt interrupt for command or address error" "0,1" group.long 0xB4++0x03 line.long 0x00 "EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET,System OCP Interrupt Enable Set Register" hexmask.long 0x00 6.--31. 1. "RESERVED," newline bitfld.long 0x00 5. "ONEBIT_ECC_ERR_SYS,Enabled status of sysem ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x00 4. "TWOBIT_ECC_ERR_SYS,Enabled status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location" "0,1" newline rbitfld.long 0x00 2. "RESERVED," "0,1" newline bitfld.long 0x00 1. "EN_TA_SYS,Enable set for system OCP interrupt for SDRAM temperature alert" "0,1" newline bitfld.long 0x00 0. "EN_ERR_SYS,Enable set for system OCP interrupt for command or address error" "0,1" group.long 0xBC++0x03 line.long 0x00 "EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR,System OCP Interrupt Enable Clear Register" hexmask.long 0x00 6.--31. 1. "RESERVED," newline bitfld.long 0x00 5. "ONEBIT_ECC_ERR_SYS,Enabled status of system ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x00 4. "TWOBIT_ECC_ERR_SYS,Enabled status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location" "0,1" newline rbitfld.long 0x00 2. "RESERVED," "0,1" newline bitfld.long 0x00 1. "EN_TA_SYS,Enable clear for system OCP interrupt for SDRAM temperature alert" "0,1" newline bitfld.long 0x00 0. "EN_ERR_SYS,Enable clear for system OCP interrupt for command or address error" "0,1" group.long 0xC8++0x17 line.long 0x00 "EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG,SDRAM Output Impedance Calibration Config Register" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 30. "ZQ_CS0EN,Writing a 1 enables ZQ calibration for CSN0" "0,1" newline rbitfld.long 0x00 29. "RESERVED," "0,1" newline bitfld.long 0x00 28. "ZQ_SFEXITEN,Writing a 1 enables the issuing of ZQCL on Self-Refresh Active Power-Down and Precharge Power-Down exit" "0,1" newline hexmask.long.byte 0x00 20.--27. 1. "RESERVED," newline bitfld.long 0x00 18.--19. "ZQ_ZQINIT_MULT,Indicates the number of ZQCL durations that make up a ZQINIT duration minus one" "0,1,2,3" newline bitfld.long 0x00 16.--17. "ZQ_ZQCL_MULT,Indicates the number of ZQCS intervals that make up a ZQCL duration minus one" "0,1,2,3" newline hexmask.long.word 0x00 0.--15. 1. "ZQ_REFINTERVAL,Number of refresh periods between ZQCS commands" line.long 0x04 "EMIF_TEMPERATURE_ALERT_CONFIG,Temperature Alert Config Register" rbitfld.long 0x04 31. "RESERVED," "0,1" newline bitfld.long 0x04 30. "TA_CS0EN,Writing a 1 enables temperature alert polling for CSN0" "0,1" newline rbitfld.long 0x04 29. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 28. "TA_SFEXITEN,Temperature Alert Poll on Self-Refresh Active Power-Down and Precharge Power-Down exit enable" "0,1" newline bitfld.long 0x04 26.--27. "TA_DEVWDT,This field indicates how wide a physical device is" "8-bit wide,16- bit wide,32-bit wide,?..." newline bitfld.long 0x04 24.--25. "TA_DEVCNT,This field indicates which external byte lanes contain a device for temperature monitoring" "one device,two devices,four devices,?..." newline rbitfld.long 0x04 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.tbyte 0x04 0.--21. 1. "TA_REFINTERVAL,Number of refresh periods between temperature alert polls" line.long 0x08 "EMIF_OCP_ERROR_LOG,OCP Error Log Register" hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED,Reserved for future use" newline bitfld.long 0x08 11.--13. "MBURSTSEQ,Addressing mode of the first errored transaction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 8.--10. "MCMD,Command type of the first errored transaction" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 0.--7. 1. "MCONNID,Connection ID of the first errored transaction" line.long 0x0C "EMIF_READ_WRITE_LEVELING_RAMP_WINDOW,Read/write leveling ramp window register" hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--12. 1. "RDWRLVLINC_RMP_WIN,Incremental leveling ramp window in number of refresh periods" line.long 0x10 "EMIF_READ_WRITE_LEVELING_RAMP_CONTROL,Read/write leveling ramp control register" bitfld.long 0x10 31. "RDWRLVL_EN,Read-Write Leveling enable" "0,1" newline hexmask.long.byte 0x10 24.--30. 1. "RDWRLVLINC_RMP_PRE,Incremental leveling pre-scalar in number of refresh periods during ramp window" newline hexmask.long.byte 0x10 16.--23. 1. "RDLVLINC_RMP_INT,Incremental read data eye training interval during ramp window" newline hexmask.long.byte 0x10 8.--15. 1. "RDLVLGATEINC_RMP_INT,Incremental read DQS gate training interval during ramp window" newline hexmask.long.byte 0x10 0.--7. 1. "WRLVLINC_RMP_INT,Incremental write leveling interval during ramp window" line.long 0x14 "EMIF_READ_WRITE_LEVELING_CONTROL,Read/write leveling control register" bitfld.long 0x14 31. "RDWRLVLFULL_START,Full leveling trigger" "0,1" newline hexmask.long.byte 0x14 24.--30. 1. "RDWRLVLINC_PRE,Incremental leveling pre-scalar in number of refresh periods" newline hexmask.long.byte 0x14 16.--23. 1. "RDLVLINC_INT,Incremental read data eye training interval" newline hexmask.long.byte 0x14 8.--15. 1. "RDLVLGATEINC_INT,Incremental read DQS gate training interval" newline hexmask.long.byte 0x14 0.--7. 1. "WRLVLINC_INT,Incremental write leveling interval" group.long 0xE4++0x0B line.long 0x00 "EMIF_DDR_PHY_CONTROL_1,PHY control register 1" bitfld.long 0x00 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "RDLVL_MASK,Writing a 1 to this field will mask read data eye training during full leveling command plus drives reg_phy_use_rd_data_eye_level control low to allow user to use programmed ratio values" "0,1" newline bitfld.long 0x00 26. "RDLVLGATE_MASK,Writing a 1 to this field will mask dqs gate training during full leveling command plus drives reg_phy_use_rd_dqs_level control low to allow user to use programmed ratio values" "0,1" newline bitfld.long 0x00 25. "WRLVL_MASK,Writing a 1 to this field will mask write leveling training during full leveling command plus drives reg_phy_use_wr_level control low to allow user to use programmed ratio values" "0,1" newline bitfld.long 0x00 22.--24. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 21. "PHY_HALF_DELAYS,Adjust slave delay line delays to support 2x mode" "1x mode ( MDLL clock rate is same as PHY),2x mode (MDLL clock is half the rate of PHY)" newline bitfld.long 0x00 20. "PHY_CLK_STALL_LEVEL,Enable variable idle value for delay lines" "0,1" newline bitfld.long 0x00 19. "PHY_DIS_CALIB_RST,Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of data PHYs" "0,1" newline bitfld.long 0x00 18. "PHY_INVERT_CLKOUT,Inverts the polarity of DRAM clock" "core clock is passed on to DRAM,inverted core clock is passed on to DRAM" newline hexmask.long.byte 0x00 10.--17. 1. "PHY_DLL_LOCK_DIFF,The maximum number of delay line taps variation while maintaining the master DLL lock" newline bitfld.long 0x00 9. "PHY_FAST_DLL_LOCK,Controls master DLL to lock fast or average logic must be part of locking process" "MDLL lock is asserted based on average of 16..,MDLL lock is asserted based on single sample" newline bitfld.long 0x00 5.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--4. "READ_LATENCY,This field defines the read latency for the read data from SDRAM in number of DDR clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EMIF_DDR_PHY_CONTROL_1_SHADOW," bitfld.long 0x04 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 27. "RDLVL_MASK_SHDW,Shadow field for RDLVL_MASK" "0,1" newline bitfld.long 0x04 26. "RDLVLGATE_MASK_SHDW,Shadow field for RDLVLGATE_MASK" "0,1" newline bitfld.long 0x04 25. "WRLVL_MASK_SHDW,Shadow field for WRLVL_MASK" "0,1" newline bitfld.long 0x04 22.--24. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 21. "PHY_HALF_DELAYS_SHDW,Shadow field for PHY_HALF_DELAYS" "0,1" newline bitfld.long 0x04 20. "PHY_CLK_STALL_LEVEL_SHDW,Shadow field for PHY_CLK_STALL_LEVEL" "0,1" newline bitfld.long 0x04 19. "PHY_DIS_CALIB_RST_SHDW,Shadow field for PHY_DIS_CALIB_RST" "0,1" newline bitfld.long 0x04 18. "PHY_INVERT_CLKOUT_SHDW,Shadow field for PHY_INVERT_CLKOUT" "0,1" newline hexmask.long.byte 0x04 10.--17. 1. "PHY_DLL_LOCK_DIFF_SHDW,Shadow field for PHY_DLL_LOCK_DIFF" newline bitfld.long 0x04 9. "PHY_FAST_DLL_SHDW,Shadow field for PHY_FAST_DLL" "0,1" newline bitfld.long 0x04 5.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--4. "READ_LATENCY_SHDW,Shadow field for READ_LATENCY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "EMIF_DDR_PHY_CONTROL_2," group.long 0x100++0x0B line.long 0x00 "EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING," bitfld.long 0x00 31. "PRI_COS_MAP_EN,Set 1 to enable priority to class of service mapping" "0,1" newline hexmask.long.word 0x00 16.--30. 1. "RESERVED," newline bitfld.long 0x00 14.--15. "PRI_7_COS,Class of service for commands with priority of 7" "0,1,2,3" newline bitfld.long 0x00 12.--13. "PRI_6_COS,Class of service for commands with priority of 6" "0,1,2,3" newline bitfld.long 0x00 10.--11. "PRI_5_COS,Class of service for commands with priority of 5" "0,1,2,3" newline bitfld.long 0x00 8.--9. "PRI_4_COS,Class of service for commands with priority of 4" "0,1,2,3" newline bitfld.long 0x00 6.--7. "PRI_3_COS,Class of service for commands with priority of 3" "0,1,2,3" newline bitfld.long 0x00 4.--5. "PRI_2_COS,Class of service for commands with priority of 2" "0,1,2,3" newline bitfld.long 0x00 2.--3. "PRI_1_COS,Class of service for commands with priority of 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. "PRI_0_COS,Class of service for commands with priority of 0" "0,1,2,3" line.long 0x04 "EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING," bitfld.long 0x04 31. "CONNID_COS_1_MAP_EN,Set 1 to enable Connection ID to class of service 1 mapping" "0,1" newline hexmask.long.byte 0x04 23.--30. 1. "CONNID_1_COS_1,Connection ID value 1 for class of service 1" newline bitfld.long 0x04 20.--22. "MSK_1_COS_1,Mask for Connection ID value 1 for class of service 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x04 12.--19. 1. "CONNID_2_COS_1,Connection ID value 2 for class of service 1" newline bitfld.long 0x04 10.--11. "MSK_2_COS_1,Mask for Connection ID value 2 for class of service 1" "0,1,2,3" newline hexmask.long.byte 0x04 2.--9. 1. "CONNID_3_COS_1,Connection ID value 3 for class of service 1" newline bitfld.long 0x04 0.--1. "MSK_3_COS_1,Mask for Connection ID value 3 for class of service 1" "0,1,2,3" line.long 0x08 "EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING," bitfld.long 0x08 31. "CONNID_COS_2_MAP_EN,Set 1 to enable Connection ID to class of service 2 mapping" "0,1" newline hexmask.long.byte 0x08 23.--30. 1. "CONNID_1_COS_2,Connection ID value 1 for class of service 2" newline bitfld.long 0x08 20.--22. "MSK_1_COS_2,Mask for Connection ID value 1 for class of service 2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 12.--19. 1. "CONNID_2_COS_2,Connection ID value 2 for class of service 2" newline bitfld.long 0x08 10.--11. "MSK_2_COS_2,Mask for Connection ID value 2 for class of service 2" "0,1,2,3" newline hexmask.long.byte 0x08 2.--9. 1. "CONNID_3_COS_2,Connection ID value 3 for class of service 2" newline bitfld.long 0x08 0.--1. "MSK_3_COS_2,Mask for Connection ID value 3 for class of service 2" "0,1,2,3" group.long 0x110++0x0B line.long 0x00 "EMIF_ECC_CTRL_REG," bitfld.long 0x00 31. "REG_ECC_EN,Set 1 to enable ECC" "0,1" newline bitfld.long 0x00 30. "REG_ECC_ADDR_RGN_PROT,Setting this field to 1 and reg_ecc_en to a 1 will enable ECC calculation for accesses within the address ranges and disable ECC calculation for accesses outside the address ranges" "0,1" newline hexmask.long 0x00 2.--29. 1. "RESERVED," newline bitfld.long 0x00 1. "REG_ECC_ADDR_RGN_2_EN,Set 1 to enable ECC address range 2" "0,1" newline bitfld.long 0x00 0. "REG_ECC_ADDR_RGN_1_EN,Set 1 to enable ECC address range 1" "0,1" line.long 0x04 "EMIF_ECC_ADDRESS_RANGE_1," hexmask.long.word 0x04 16.--31. 1. "REG_ECC_END_ADDR_1,End address[32:17] for ECC address range 1" newline hexmask.long.word 0x04 0.--15. 1. "REG_ECC_STRT_ADDR_1,Start address[32:17] for ECC address range 1" line.long 0x08 "EMIF_ECC_ADDRESS_RANGE_2," hexmask.long.word 0x08 16.--31. 1. "REG_ECC_END_ADDR_2,End address[32:17] for ECC address range 2" newline hexmask.long.word 0x08 0.--15. 1. "REG_ECC_STRT_ADDR_2,Start address[32:17] for ECC address range 2" group.long 0x120++0x07 line.long 0x00 "EMIF_READ_WRITE_EXECUTION_THRESHOLD," bitfld.long 0x00 31. "MFLAG_OVERRIDE,Mflag override" "MFLAG_OVERRIDE_0,MFLAG_OVERRIDE_1" newline hexmask.long.tbyte 0x00 13.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 8.--12. "WR_THRSH,Write Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 0.--4. "RD_THRSH,Read threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EMIF_COS_CONFIG,Priority Raise Counter Register" hexmask.long.byte 0x04 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x04 16.--23. 1. "COS_COUNT_1,Priority Raise Counter for class of service 1" newline hexmask.long.byte 0x04 8.--15. 1. "COS_COUNT_2,Priority Raise Counter for class of service 2" newline hexmask.long.byte 0x04 0.--7. 1. "PR_OLD_COUNT,Priority Raise Old Counter" group.long 0x130++0x83 line.long 0x00 "EMIF_1B_ECC_ERR_CNT," line.long 0x04 "EMIF_1B_ECC_ERR_THRSH," hexmask.long.byte 0x04 24.--31. 1. "REG_1B_ECC_ERR_THRSH,1-bit ECC error threshold" newline hexmask.long.byte 0x04 16.--23. 1. "RESERVED," newline hexmask.long.word 0x04 0.--15. 1. "REG_1B_ECC_ERR_WIN,1-bit ECC error window in number of refresh periods" line.long 0x08 "EMIF_1B_ECC_ERR_DIST_1," line.long 0x0C "EMIF_1B_ECC_ERR_ADDR_LOG," line.long 0x10 "EMIF_2B_ECC_ERR_ADDR_LOG," line.long 0x14 "EMIF_PHY_STATUS_1," bitfld.long 0x14 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.tbyte 0x14 12.--29. 1. "PHY_REG_PHY_CTRL_DLL_SLAVE_VALUE,DLL Slave Value" newline bitfld.long 0x14 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 4.--8. "PHY_REG_STATUS_DLL_LOCK,Lock Status for Data DLLs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 0.--1. "PHY_REG_PHY_CTRL_DLL_LOCK,Lock Status for Command DLLs" "0,1,2,3" line.long 0x18 "EMIF_PHY_STATUS_2," line.long 0x1C "EMIF_PHY_STATUS_3," bitfld.long 0x1C 31. "RESERVED," "0,1" newline hexmask.long.word 0x1C 16.--30. 1. "PHY_REG_RDFIFO_RDPTR,Read FIFO Read Pointer" newline bitfld.long 0x1C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1C 0.--12. 1. "PHY_REG_STATUS_DLL_SLAVE_VALUE_HI,Bits 44:32 of Phy_reg_status_dll_slave_value" line.long 0x20 "EMIF_PHY_STATUS_4," bitfld.long 0x20 31. "RESERVED," "0,1" newline hexmask.long.word 0x20 16.--30. 1. "PHY_REG_GATELVL_FSM,Gate Levelling FSM" newline bitfld.long 0x20 15. "RESERVED," "0,1" newline hexmask.long.word 0x20 0.--14. 1. "PHY_REG_RDFIFO_WRPTR,Read FIFO Write Pointer" line.long 0x24 "EMIF_PHY_STATUS_5," hexmask.long.word 0x24 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x24 0.--19. 1. "PHY_REG_RD_LEVEL_FSM,Read Levelling FSM" line.long 0x28 "EMIF_PHY_STATUS_6," hexmask.long.tbyte 0x28 15.--31. 1. "RESERVED," newline hexmask.long.word 0x28 0.--14. 1. "PHY_REG_WR_LEVEL_FSM,Writel Levelling FSM" line.long 0x2C "EMIF_PHY_STATUS_7," bitfld.long 0x2C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x2C 16.--25. 1. "PHY_REG_RDLVL_DQS_RATIO1,Read levelling DQS ratio1" newline bitfld.long 0x2C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x2C 0.--9. 1. "PHY_REG_RDLVL_DQS_RATIO0,Read levelling DQS ratio0" line.long 0x30 "EMIF_PHY_STATUS_8," bitfld.long 0x30 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x30 16.--25. 1. "PHY_REG_RDLVL_DQS_RATIO3,Read levelling DQS ratio3" newline bitfld.long 0x30 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x30 0.--9. 1. "PHY_REG_RDLVL_DQS_RATIO2,Read levelling DQS ratio2" line.long 0x34 "EMIF_PHY_STATUS_9," bitfld.long 0x34 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x34 16.--25. 1. "PHY_REG_RDLVL_DQS_RATIO5,Read Levelling DQS ratio5" newline bitfld.long 0x34 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x34 0.--9. 1. "PHY_REG_RDLVL_DQS_RATIO4,Read Levelling DQS ratio4" line.long 0x38 "EMIF_PHY_STATUS_10," bitfld.long 0x38 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x38 16.--25. 1. "PHY_REG_RDLVL_DQS_RATIO7,Read levelling DQS ratio7" newline bitfld.long 0x38 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x38 0.--9. 1. "PHY_REG_RDLVL_DQS_RATIO6,Read levelling DQS ratio6" line.long 0x3C "EMIF_PHY_STATUS_11," bitfld.long 0x3C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x3C 16.--25. 1. "PHY_REG_RDLVL_DQS_RATIO9,Read levelling DQS ratio9" newline bitfld.long 0x3C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x3C 0.--9. 1. "PHY_REG_RDLVL_DQS_RATIO8,Read levelling DQS ratio8" line.long 0x40 "EMIF_PHY_STATUS_12," bitfld.long 0x40 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x40 16.--26. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO1,Read levelling FIFO Write Enable Ratio1" newline bitfld.long 0x40 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x40 0.--10. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO0,Read levelling FIFO Write Enable Ratio0" line.long 0x44 "EMIF_PHY_STATUS_13," bitfld.long 0x44 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x44 16.--26. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO3,Read levelling FIFO Write Enable Ratio3" newline bitfld.long 0x44 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x44 0.--10. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO2,Read levelling FIFO Write Enable Ratio2" line.long 0x48 "EMIF_PHY_STATUS_14," bitfld.long 0x48 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 16.--26. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO5,Read levelling FIFO Write Enable Ratio5" newline bitfld.long 0x48 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 0.--10. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO4,Read levelling FIFO Write Enable Ratio4" line.long 0x4C "EMIF_PHY_STATUS_15," bitfld.long 0x4C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x4C 16.--26. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO7,Read levelling FIFO Wrie Enable Ratio7" newline bitfld.long 0x4C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x4C 0.--10. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO6,Read levelling FIFO Wrie Enable Ratio6" line.long 0x50 "EMIF_PHY_STATUS_16," bitfld.long 0x50 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x50 16.--26. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO9,Read levelling FIFO Write Enable Ratio9" newline bitfld.long 0x50 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x50 0.--10. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO8,Read levelling FIFO Write Enable Ratio8" line.long 0x54 "EMIF_PHY_STATUS_17," bitfld.long 0x54 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x54 16.--25. 1. "PHY_REG_WRLVL_DQ_RATIO1,Write levelling DQ ratio1" newline bitfld.long 0x54 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x54 0.--9. 1. "PHY_REG_WRLVL_DQ_RATIO0,Write levelling DQ ratio0" line.long 0x58 "EMIF_PHY_STATUS_18," bitfld.long 0x58 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x58 16.--25. 1. "PHY_REG_WRLVL_DQ_RATIO3,Write levelling DQ ratio3" newline bitfld.long 0x58 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x58 0.--9. 1. "PHY_REG_WRLVL_DQ_RATIO2,Write levelling DQ ratio2" line.long 0x5C "EMIF_PHY_STATUS_19," bitfld.long 0x5C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x5C 16.--25. 1. "PHY_REG_WRLVL_DQ_RATIO5,Write levelling DQ ratio5" newline bitfld.long 0x5C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x5C 0.--9. 1. "PHY_REG_WRLVL_DQ_RATIO4,Write levelling DQ ratio4" line.long 0x60 "EMIF_PHY_STATUS_20," bitfld.long 0x60 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x60 16.--25. 1. "PHY_REG_WRLVL_DQ_RATIO7,Write levelling DQ ratio7" newline bitfld.long 0x60 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x60 0.--9. 1. "PHY_REG_WRLVL_DQ_RATIO6,Write levelling DQ ratio6" line.long 0x64 "EMIF_PHY_STATUS_21," bitfld.long 0x64 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x64 16.--25. 1. "PHY_REG_WRLVL_DQ_RATIO9,Write levelling DQ ratio9" newline bitfld.long 0x64 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x64 0.--9. 1. "PHY_REG_WRLVL_DQ_RATIO8,Write levelling DQ ratio8" line.long 0x68 "EMIF_PHY_STATUS_22," bitfld.long 0x68 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x68 16.--25. 1. "PHY_REG_WRLVL_DQS_RATIO1,Write levelling DQS ratio 1" newline bitfld.long 0x68 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x68 0.--9. 1. "PHY_REG_WRLVL_DQS_RATIO0,Write levelling DQS ratio 0" line.long 0x6C "EMIF_PHY_STATUS_23," bitfld.long 0x6C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x6C 16.--25. 1. "PHY_REG_WRLVL_DQS_RATIO3,Write levelling DQS ratio3" newline bitfld.long 0x6C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x6C 0.--9. 1. "PHY_REG_WRLVL_DQS_RATIO2,Write levelling DQS ratio2" line.long 0x70 "EMIF_PHY_STATUS_24," bitfld.long 0x70 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x70 16.--25. 1. "PHY_REG_WRLVL_DQS_RATIO5,Write levelling DQS ratio5" newline bitfld.long 0x70 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x70 0.--9. 1. "PHY_REG_WRLVL_DQS_RATIO4,Write levelling DQS ratio4" line.long 0x74 "EMIF_PHY_STATUS_25," bitfld.long 0x74 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x74 16.--25. 1. "PHY_REG_WRLVL_DQS_RATIO7,Write levelling DQS ratio7" newline bitfld.long 0x74 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x74 0.--9. 1. "PHY_REG_WRLVL_DQS_RATIO6,Write levelling DQS ratio6" line.long 0x78 "EMIF_PHY_STATUS_26," bitfld.long 0x78 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x78 16.--25. 1. "PHY_REG_WRLVL_DQS_RATIO9,Write levelling DQS ratio9" newline bitfld.long 0x78 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x78 0.--9. 1. "PHY_REG_WRLVL_DQS_RATIO8,Write levelling DQS ratio8" line.long 0x7C "EMIF_PHY_STATUS_27," bitfld.long 0x7C 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x7C 28.--29. "PHY_REG_PHY_CONTROL_MDLL_UNLOCK_STICKY,Phy control MDLL unlock sticky" "0,1,2,3" newline bitfld.long 0x7C 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x7C 20.--24. "PHY_REG_STATUS_MDLL_UNLOCK_STICKY,Phy data MDLL unlock sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.tbyte 0x7C 0.--19. 1. "PHY_REG_RDC_FIFO_RST_ERR_CNT,RDC FIFO reset error count" line.long 0x80 "EMIF_PHY_STATUS_28," bitfld.long 0x80 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 24.--28. "PHY_REG_GATELVL_INC_FAIL,Gate levelling failure.NOTE: Incremental leveling is not supported on this device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x80 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 16.--20. "PHY_REG_WRLVL_INC_FAIL,Write levelling failure.NOTE: Incremental leveling is not supported on this device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x80 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 8.--12. "PHY_REG_RDLVL_INC_FAIL,Read levelling failure.NOTE: Incremental leveling is not supported on this device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x80 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 0.--4. "PHY_REG_FIFO_WE_IN_MIASALIGNED_STICKY,FIFO write enable in misaligned stickly" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x200++0x11F line.long 0x00 "EMIF_EXT_PHY_CONTROL_1,Control DLL Slave Ratio Register" rbitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 20.--29. 1. "PHY_REG_CTRL_SLAVE_RATIO2,The user programmable ratio value for address/command launch timing in PHY control macro 2" newline hexmask.long.word 0x00 10.--19. 1. "PHY_REG_CTRL_SLAVE_RATIO1,The user programmable ratio value for address/command launch timing in PHY control macro 1" newline hexmask.long.word 0x00 0.--9. 1. "PHY_REG_CTRL_SLAVE_RATIO0,The user programmable ratio value for address/command launch timing in PHY control macro 0" line.long 0x04 "EMIF_EXT_PHY_CONTROL_1_SHADOW,Control DLL Slave Ratio Shadow Register" rbitfld.long 0x04 30.--31. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x04 20.--29. 1. "PHY_REG_CTRL_SLAVE_RATIO2,The user programmable ratio value for address/command launch timing in PHY control macro 2" newline hexmask.long.word 0x04 10.--19. 1. "PHY_REG_CTRL_SLAVE_RATIO1,The user programmable ratio value for address/command launch timing in PHY control macro 1" newline hexmask.long.word 0x04 0.--9. 1. "PHY_REG_CTRL_SLAVE_RATIO0,The user programmable ratio value for address/command launch timing in PHY control macro 0" line.long 0x08 "EMIF_EXT_PHY_CONTROL_2,Data macro 0. FIFO write enable (read DQS gate) DLL Slave Ratio Register" rbitfld.long 0x08 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x08 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO1,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0x08 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x08 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO0,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0 chip select 0" line.long 0x0C "EMIF_EXT_PHY_CONTROL_2_SHADOW,Data macro 0. FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register" rbitfld.long 0x0C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x0C 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO1,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0x0C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x0C 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO0,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0 chip select 0" line.long 0x10 "EMIF_EXT_PHY_CONTROL_3,Data macro 1. FIFO write enable (read DQS gate) DLL Slave Ratio Register" rbitfld.long 0x10 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x10 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO3,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0x10 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x10 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO2,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1 chip select 0" line.long 0x14 "EMIF_EXT_PHY_CONTROL_3_SHADOW,Data macro 1. FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register" rbitfld.long 0x14 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x14 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO3,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0x14 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x14 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO2,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1 chip select 0" line.long 0x18 "EMIF_EXT_PHY_CONTROL_4,Data macro 2. FIFO write enable (read DQS gate) DLL Slave Ratio Register" rbitfld.long 0x18 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x18 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO5,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x18 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x18 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO4,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2 chip select 0" line.long 0x1C "EMIF_EXT_PHY_CONTROL_4_SHADOW,Data macro 2. FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register" rbitfld.long 0x1C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x1C 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO5,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x1C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x1C 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO4,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2 chip select 0" line.long 0x20 "EMIF_EXT_PHY_CONTROL_5,Data macro 3. FIFO write enable (read DQS gate) DLL Slave Ratio Register" rbitfld.long 0x20 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x20 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO7,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x20 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x20 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO6,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3 chip select 0" line.long 0x24 "EMIF_EXT_PHY_CONTROL_5_SHADOW,Data macro 3. FIFO write enable (read DQS gate) DLL Slave Ratio Register" rbitfld.long 0x24 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x24 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO7,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x24 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x24 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO6,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3 chip select 0" line.long 0x28 "EMIF_EXT_PHY_CONTROL_6,ECC Data macro. FIFO write enable (read DQS gate) DLL Slave Ratio Register" rbitfld.long 0x28 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x28 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO9,The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0x28 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x28 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO8,The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro chip select 0" line.long 0x2C "EMIF_EXT_PHY_CONTROL_6_SHADOW,ECC Data macro. FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register" rbitfld.long 0x2C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x2C 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO9,The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0x2C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x2C 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO8,The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro chip select 0" line.long 0x30 "EMIF_EXT_PHY_CONTROL_7,Data macro 0. read DQS DLL Slave Ratio Register" rbitfld.long 0x30 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x30 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO1,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0x30 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x30 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO0,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0 chip select 0" line.long 0x34 "EMIF_EXT_PHY_CONTROL_7_SHADOW,Data macro 0. read DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x34 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x34 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO1,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0x34 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x34 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO0,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0 chip select 0" line.long 0x38 "EMIF_EXT_PHY_CONTROL_8,Data macro 1. read DQS DLL Slave Ratio Register" rbitfld.long 0x38 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x38 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO3,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0x38 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x38 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO2,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1 chip select 0" line.long 0x3C "EMIF_EXT_PHY_CONTROL_8_SHADOW,Data macro 1. read DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x3C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x3C 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO3,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0x3C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x3C 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO2,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1 chip select 0" line.long 0x40 "EMIF_EXT_PHY_CONTROL_9,Data macro 2. read DQS DLL Slave Ratio Register" rbitfld.long 0x40 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x40 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO5,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x40 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x40 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO4,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x44 "EMIF_EXT_PHY_CONTROL_9_SHADOW,Data macro 2. read DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x44 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x44 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO5,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x44 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x44 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO4,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x48 "EMIF_EXT_PHY_CONTROL_10,Data macro 3. read DQS DLL Slave Ratio Register" rbitfld.long 0x48 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x48 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO7,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x48 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x48 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO6,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3 chip select 0" line.long 0x4C "EMIF_EXT_PHY_CONTROL_10_SHADOW,Data macro 3. read DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x4C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x4C 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO7,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x4C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x4C 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO6,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3 chip select 0" line.long 0x50 "EMIF_EXT_PHY_CONTROL_11,ECC Data macro. read DQS DLL Slave Ratio Register" rbitfld.long 0x50 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x50 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO9,The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0x50 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x50 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO8,The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro chip select 0" line.long 0x54 "EMIF_EXT_PHY_CONTROL_11_SHADOW,ECC Data macro. read DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x54 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x54 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO9,The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0x54 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x54 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO8,The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro chip select 0" line.long 0x58 "EMIF_EXT_PHY_CONTROL_12,Data macro 0. write DQ (data) DLL Slave Ratio Register" rbitfld.long 0x58 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x58 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO1,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0x58 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x58 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO0,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0 chip select 0" line.long 0x5C "EMIF_EXT_PHY_CONTROL_12_SHADOW,Data macro 0. write DQ (data) DLL Slave Ratio Shadow Register" rbitfld.long 0x5C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x5C 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO1,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0x5C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x5C 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO0,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0 chip select 0" line.long 0x60 "EMIF_EXT_PHY_CONTROL_13,Data macro 1. write DQ (data) DLL Slave Ratio Register" rbitfld.long 0x60 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x60 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO3,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0x60 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x60 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO2,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1 chip select 0" line.long 0x64 "EMIF_EXT_PHY_CONTROL_13_SHADOW,Data macro 1. write DQ (data) DLL Slave Ratio Shadow Register" rbitfld.long 0x64 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x64 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO3,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0x64 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x64 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO2,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1 chip select 0" line.long 0x68 "EMIF_EXT_PHY_CONTROL_14,Data macro 2. write DQ (data) DLL Slave Ratio Register" rbitfld.long 0x68 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x68 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO5,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x68 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x68 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO4,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2 chip select 0" line.long 0x6C "EMIF_EXT_PHY_CONTROL_14_SHADOW,Data macro 2. write DQ (data) DLL Slave Ratio Shadow Register" rbitfld.long 0x6C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x6C 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO5,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x6C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x6C 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO4,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2 chip select 0" line.long 0x70 "EMIF_EXT_PHY_CONTROL_15,Data macro 3. write DQ (data) DLL Slave Ratio Register" rbitfld.long 0x70 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x70 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO7,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x70 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x70 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO6,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3 chip select 0" line.long 0x74 "EMIF_EXT_PHY_CONTROL_15_SHADOW,Data macro 3. write DQ (data) DLL Slave Ratio Shadow Register" rbitfld.long 0x74 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x74 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO7,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x74 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x74 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO6,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3 chip select 0" line.long 0x78 "EMIF_EXT_PHY_CONTROL_16,ECC Data macro. write DQ (data) DLL Slave Ratio Register" rbitfld.long 0x78 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x78 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO9,The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0x78 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x78 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO8,The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro chip select 0" line.long 0x7C "EMIF_EXT_PHY_CONTROL_16_SHADOW,ECC Data macro. write DQ (data) DLL Slave Ratio Shadow Register" rbitfld.long 0x7C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x7C 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO9,The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0x7C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x7C 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO8,The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro chip select 0" line.long 0x80 "EMIF_EXT_PHY_CONTROL_17,Data macro 0. write DQS DLL Slave Ratio Register" rbitfld.long 0x80 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x80 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO1,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0x80 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x80 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO0,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0 chip select 0" line.long 0x84 "EMIF_EXT_PHY_CONTROL_17_SHADOW,Data macro 0. write DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x84 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x84 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO1,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0x84 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x84 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO0,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0 chip select 0" line.long 0x88 "EMIF_EXT_PHY_CONTROL_18,Data macro 1. write DQS DLL Slave Ratio Register" rbitfld.long 0x88 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x88 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO3,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0x88 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x88 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO2,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1 chip select 0" line.long 0x8C "EMIF_EXT_PHY_CONTROL_18_SHADOW,Data macro 1. write DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x8C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x8C 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO3,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0x8C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x8C 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO2,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1 chip select 0" line.long 0x90 "EMIF_EXT_PHY_CONTROL_19,Data macro 2. write DQS DLL Slave Ratio Register" rbitfld.long 0x90 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x90 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO5,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x90 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x90 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO4,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x94 "EMIF_EXT_PHY_CONTROL_19_SHADOW,Data macro 2. write DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x94 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x94 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO5,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x94 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x94 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO4,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x98 "EMIF_EXT_PHY_CONTROL_20,Data macro 3. write DQS DLL Slave Ratio Register" rbitfld.long 0x98 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x98 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO7,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x98 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x98 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO6,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3 chip select 0" line.long 0x9C "EMIF_EXT_PHY_CONTROL_20_SHADOW,Data macro 3. write DQS DLL Slave Ratio Shadow Register" rbitfld.long 0x9C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x9C 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO7,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x9C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x9C 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO6,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3 chip select 0" line.long 0xA0 "EMIF_EXT_PHY_CONTROL_21,ECC Data macro. write DQS DLL Slave Ratio Register" rbitfld.long 0xA0 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xA0 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO9,The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0xA0 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xA0 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO8,The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro chip select 0" line.long 0xA4 "EMIF_EXT_PHY_CONTROL_21_SHADOW,ECC Data macro. write DQS DLL Slave Ratio Shadow Register" rbitfld.long 0xA4 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xA4 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO9,The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0xA4 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xA4 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO8,The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro chip select 0" line.long 0xA8 "EMIF_EXT_PHY_CONTROL_22," hexmask.long.byte 0xA8 25.--31. 1. "RESERVED," newline hexmask.long.word 0xA8 16.--24. 1. "PHY_REG_FIFO_WE_IN_DELAY,The user programmable FIFO write enable delay value used when DLL_OVERRIDE = 1" newline hexmask.long.byte 0xA8 9.--15. 1. "RESERVED," newline hexmask.long.word 0xA8 0.--8. 1. "PHY_REG_CTRL_SLAVE_DELAY,The user programmable command delay value used when DLL_OVERRIDE = 1" line.long 0xAC "EMIF_EXT_PHY_CONTROL_22_SHADOW," hexmask.long.byte 0xAC 25.--31. 1. "RESERVED," newline hexmask.long.word 0xAC 16.--24. 1. "PHY_REG_FIFO_WE_IN_DELAY,The user programmable FIFO write enable delay value used when DLL_OVERRIDE = 1" newline hexmask.long.byte 0xAC 9.--15. 1. "RESERVED," newline hexmask.long.word 0xAC 0.--8. 1. "PHY_REG_CTRL_SLAVE_DELAY,The user programmable command delay value used when DLL_OVERRIDE = 1" line.long 0xB0 "EMIF_EXT_PHY_CONTROL_23," hexmask.long.byte 0xB0 25.--31. 1. "RESERVED," newline hexmask.long.word 0xB0 16.--24. 1. "PHY_REG_WR_DQS_SLAVE_DELAY,The user programmable write DQS delay value used when DLL_OVERRIDE = 1" newline hexmask.long.byte 0xB0 9.--15. 1. "RESERVED," newline hexmask.long.word 0xB0 0.--8. 1. "PHY_REG_RD_DQS_SLAVE_DELAY,The user programmable read DQS delay value used when DLL_OVERRIDE = 1" line.long 0xB4 "EMIF_EXT_PHY_CONTROL_23_SHADOW," hexmask.long.byte 0xB4 25.--31. 1. "RESERVED," newline hexmask.long.word 0xB4 16.--24. 1. "PHY_REG_WR_DQS_SLAVE_DELAY,The user programmable write DQS delay value used when DLL_OVERRIDE = 1" newline hexmask.long.byte 0xB4 9.--15. 1. "RESERVED," newline hexmask.long.word 0xB4 0.--8. 1. "PHY_REG_RD_DQS_SLAVE_DELAY,The user programmable read DQS delay value used when DLL_OVERRIDE = 1" line.long 0xB8 "EMIF_EXT_PHY_CONTROL_24," rbitfld.long 0xB8 31. "RESERVED," "0,1" newline hexmask.long.byte 0xB8 24.--30. 1. "REG_PHY_DQ_OFFSET_HI,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xB8 17.--23. 1. "RESERVED," newline bitfld.long 0xB8 16. "REG_PHY_GATELVL_INIT_MODE,The user programmable init ratio selection mode" "0,1" newline rbitfld.long 0xB8 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 12. "REG_PHY_USE_RANK0_DELAYS,Delay selection" "0,1" newline rbitfld.long 0xB8 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xB8 0.--8. 1. "REG_PHY_WR_DATA_SLAVE_DELAY,The user programmable write DQ delay value used when DLL_OVERRIDE = 1" line.long 0xBC "EMIF_EXT_PHY_CONTROL_24_SHADOW," rbitfld.long 0xBC 31. "RESERVED," "0,1" newline hexmask.long.byte 0xBC 24.--30. 1. "REG_PHY_DQ_OFFSET_HI,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xBC 17.--23. 1. "RESERVED," newline bitfld.long 0xBC 16. "REG_PHY_GATELVL_INIT_MODE,The user programmable init ratio selection mode" "0,1" newline rbitfld.long 0xBC 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0xBC 12. "REG_PHY_USE_RANK0_DELAYS,Delay selection" "0,1" newline rbitfld.long 0xBC 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xBC 0.--8. 1. "REG_PHY_WR_DATA_SLAVE_DELAY,The user programmable write DQ delay value used when DLL_OVERRIDE = 1" line.long 0xC0 "EMIF_EXT_PHY_CONTROL_25,DQ DLL Slave Ratio Offset Register" rbitfld.long 0xC0 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0xC0 21.--27. 1. "REG_PHY_DQ_OFFSET3,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC0 14.--20. 1. "REG_PHY_DQ_OFFSET2,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC0 7.--13. 1. "REG_PHY_DQ_OFFSET1,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC0 0.--6. 1. "REG_PHY_DQ_OFFSET0,The user programmable offset ratio value from write DQS to write DQ" line.long 0xC4 "EMIF_EXT_PHY_CONTROL_25_SHADOW,DQ DLL Slave Ratio Offset Shadow Register" rbitfld.long 0xC4 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0xC4 21.--27. 1. "REG_PHY_DQ_OFFSET3,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC4 14.--20. 1. "REG_PHY_DQ_OFFSET2,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC4 7.--13. 1. "REG_PHY_DQ_OFFSET1,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC4 0.--6. 1. "REG_PHY_DQ_OFFSET0,The user programmable offset ratio value from write DQS to write DQ" line.long 0xC8 "EMIF_EXT_PHY_CONTROL_26,Data macro 0. FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" rbitfld.long 0xC8 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xC8 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO1,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0xC8 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xC8 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO0,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0 chip select 0" line.long 0xCC "EMIF_EXT_PHY_CONTROL_26_SHADOW,Data macro 0. FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register" rbitfld.long 0xCC 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xCC 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO1,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0xCC 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xCC 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO0,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0 chip select 0" line.long 0xD0 "EMIF_EXT_PHY_CONTROL_27,Data macro 1. FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" rbitfld.long 0xD0 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xD0 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO3,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0xD0 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xD0 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO2,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1 chip select 0" line.long 0xD4 "EMIF_EXT_PHY_CONTROL_27_SHADOW,Data macro 1. FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register" rbitfld.long 0xD4 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xD4 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO3,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0xD4 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xD4 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO2,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1 chip select 0" line.long 0xD8 "EMIF_EXT_PHY_CONTROL_28,Data macro 2. FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" rbitfld.long 0xD8 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xD8 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO5,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0xD8 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xD8 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO4,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2 chip select 0" line.long 0xDC "EMIF_EXT_PHY_CONTROL_28_SHADOW,Data macro 2. FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register" rbitfld.long 0xDC 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xDC 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO5,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0xDC 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xDC 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO4,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2 chip select 0" line.long 0xE0 "EMIF_EXT_PHY_CONTROL_29,Data macro 3. FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" rbitfld.long 0xE0 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xE0 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO7,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0xE0 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xE0 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO6,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3 chip select 0" line.long 0xE4 "EMIF_EXT_PHY_CONTROL_29_SHADOW,Data macro 3. FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register" rbitfld.long 0xE4 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xE4 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO7,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0xE4 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xE4 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO6,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3 chip select 0" line.long 0xE8 "EMIF_EXT_PHY_CONTROL_30,ECC Data macro. FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" rbitfld.long 0xE8 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xE8 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO9,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0xE8 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xE8 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO8,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro chip select 0" line.long 0xEC "EMIF_EXT_PHY_CONTROL_30_SHADOW,ECC Data macro. FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register" rbitfld.long 0xEC 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xEC 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO9,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0xEC 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xEC 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO8,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro chip select 0" line.long 0xF0 "EMIF_EXT_PHY_CONTROL_31,Data macro 0. write DQS DLL Slave Init Ratio Register" rbitfld.long 0xF0 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xF0 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO1,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0xF0 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xF0 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO0,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0 chip select 0" line.long 0xF4 "EMIF_EXT_PHY_CONTROL_31_SHADOW,Data macro 0. write DQS DLL Slave Init Ratio Shadow Register" rbitfld.long 0xF4 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xF4 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO1,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0 chip select 1" newline rbitfld.long 0xF4 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xF4 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO0,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0 chip select 0" line.long 0xF8 "EMIF_EXT_PHY_CONTROL_32,Data macro 1. write DQS DLL Slave Init Ratio Register" rbitfld.long 0xF8 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xF8 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO3,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0xF8 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xF8 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO2,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1 chip select 0" line.long 0xFC "EMIF_EXT_PHY_CONTROL_32_SHADOW,Data macro 1. write DQS DLL Slave Init Ratio Shadow Register" rbitfld.long 0xFC 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xFC 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO3,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1 chip select 1" newline rbitfld.long 0xFC 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0xFC 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO2,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1 chip select 0" line.long 0x100 "EMIF_EXT_PHY_CONTROL_33,Data macro 2. write DQS DLL Slave Init Ratio Register" rbitfld.long 0x100 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x100 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO5,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x100 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x100 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO4,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x104 "EMIF_EXT_PHY_CONTROL_33_SHADOW,Data macro 2. write DQS DLL Slave Init Ratio Shadow Register" rbitfld.long 0x104 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x104 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO5,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2 chip select 1" newline rbitfld.long 0x104 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x104 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO4,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x108 "EMIF_EXT_PHY_CONTROL_34,Data macro 3. write DQS DLL Slave Init Ratio Register" rbitfld.long 0x108 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x108 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO7,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x108 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x108 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO6,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3 chip select 0" line.long 0x10C "EMIF_EXT_PHY_CONTROL_34_SHADOW,Data macro 3. write DQS DLL Slave Init Ratio Shadow Register" rbitfld.long 0x10C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x10C 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO7,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3 chip select 1" newline rbitfld.long 0x10C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x10C 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO6,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3 chip select 0" line.long 0x110 "EMIF_EXT_PHY_CONTROL_35,ECC Data macro. write DQS DLL Slave Init Ratio Register" rbitfld.long 0x110 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x110 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO9,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0x110 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x110 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO8,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro chip select 0" line.long 0x114 "EMIF_EXT_PHY_CONTROL_35_SHADOW,ECC Data macro. write DQS DLL Slave Init Ratio Shadow Register" rbitfld.long 0x114 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x114 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO9,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro chip select 1" newline rbitfld.long 0x114 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x114 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO8,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro chip select 0" line.long 0x118 "EMIF_EXT_PHY_CONTROL_36," hexmask.long.tbyte 0x118 11.--31. 1. "RESERVED," newline bitfld.long 0x118 10. "REG_PHY_RDC_FIFO_RST_ERR_CNT_CLR,Clear/reset the phy_reg_rdc_fifo_rst_err_cnt phy_reg_rdfifo_wrptr and phy_reg_rdfifo_rdptr status flags" "0,1" newline bitfld.long 0x118 9. "REG_PHY_MDLL_UNLOCK_CLR,Clears the phy_reg_status_mdll_unlock_sticky flag" "0,1" newline bitfld.long 0x118 8. "REG_PHY_FIFO_WE_IN_MISALIGNED_CLR,Clears the phy_reg_fifo_we_in_misaligned_sticky status flag" "0,1" newline bitfld.long 0x118 4.--7. "REG_PHY_WRLVL_NUM_OF_DQ0,Determines the number of samples fordq0_in for each ratio increment by the write leveling finite state machine (hardware leveling)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x118 0.--3. "REG_PHY_GATELVL_NUM_OF_DQ0,Determines the number of samples fordq0_in for each ratio increment by the gate training finite state machine (hardware leveling)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x11C "EMIF_EXT_PHY_CONTROL_36_SHADOW," hexmask.long.tbyte 0x11C 11.--31. 1. "RESERVED," newline bitfld.long 0x11C 10. "REG_PHY_RDC_FIFO_RST_ERR_CNT_CLR,Clear/reset the phy_reg_rdc_fifo_rst_err_cnt phy_reg_rdfifo_wrptr and phy_reg_rdfifo_rdptr status flags" "0,1" newline bitfld.long 0x11C 9. "REG_PHY_MDLL_UNLOCK_CLR,Clears the phy_reg_status_mdll_unlock_sticky flag" "0,1" newline bitfld.long 0x11C 8. "REG_PHY_FIFO_WE_IN_MISALIGNED_CLR,Clears the phy_reg_fifo_we_in_misaligned_sticky status flag" "0,1" newline bitfld.long 0x11C 4.--7. "REG_PHY_WRLVL_NUM_OF_DQ0,Determines the number of samples fordq0_in for each ratio increment by the write leveling finite state machine (hardware leveling)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x11C 0.--3. "REG_PHY_GATELVL_NUM_OF_DQ0,Determines the number of samples fordq0_in for each ratio increment by the gate training finite state machine (hardware leveling)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "EMIF_FW" base ad:0x4A20C000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" newline rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x100++0x03 line.long 0x00 "START_REGION_i_8,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x110++0x03 line.long 0x00 "START_REGION_i_9,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x120++0x03 line.long 0x00 "START_REGION_i_10,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x130++0x03 line.long 0x00 "START_REGION_i_11,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x140++0x03 line.long 0x00 "START_REGION_i_12,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x150++0x03 line.long 0x00 "START_REGION_i_13,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x160++0x03 line.long 0x00 "START_REGION_i_14,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x170++0x03 line.long 0x00 "START_REGION_i_15,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x180++0x03 line.long 0x00 "START_REGION_i_16,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x190++0x03 line.long 0x00 "START_REGION_i_17,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1A0++0x03 line.long 0x00 "START_REGION_i_18,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1B0++0x03 line.long 0x00 "START_REGION_i_19,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1C0++0x03 line.long 0x00 "START_REGION_i_20,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1D0++0x03 line.long 0x00 "START_REGION_i_21,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1E0++0x03 line.long 0x00 "START_REGION_i_22,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1F0++0x03 line.long 0x00 "START_REGION_i_23,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x104++0x03 line.long 0x00 "END_REGION_i_8,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x114++0x03 line.long 0x00 "END_REGION_i_9,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x124++0x03 line.long 0x00 "END_REGION_i_10,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x134++0x03 line.long 0x00 "END_REGION_i_11,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x144++0x03 line.long 0x00 "END_REGION_i_12,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x154++0x03 line.long 0x00 "END_REGION_i_13,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x164++0x03 line.long 0x00 "END_REGION_i_14,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x174++0x03 line.long 0x00 "END_REGION_i_15,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x184++0x03 line.long 0x00 "END_REGION_i_16,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x194++0x03 line.long 0x00 "END_REGION_i_17,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1A4++0x03 line.long 0x00 "END_REGION_i_18,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1B4++0x03 line.long 0x00 "END_REGION_i_19,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1C4++0x03 line.long 0x00 "END_REGION_i_20,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1D4++0x03 line.long 0x00 "END_REGION_i_21,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1E4++0x03 line.long 0x00 "END_REGION_i_22,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1F4++0x03 line.long 0x00 "END_REGION_i_23,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x108++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_8,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x118++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_9,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x128++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_10,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x138++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_11,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x148++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_12,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x158++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_13,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x168++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_14,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x178++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_15,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x188++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_16,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x198++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_17,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1A8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_18,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1B8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_19,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_20,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1D8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_21,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_22,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1F8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_23,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x10C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_8,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x11C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_9,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x12C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_10,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x13C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_11,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x14C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_12,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x15C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_13,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x16C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_14,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x17C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_15,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x18C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_16,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x19C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_17,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1AC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_18,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1BC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_19,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1CC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_20,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1DC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_21,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1EC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_22,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1FC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_23,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "EMIF_FW_CFG_TARG" base ad:0x4A20D000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "EMIF_P1_TARG" base ad:0x44000200 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "EMU_CM" base ad:0x4AE07A00 group.long 0x00++0x0F line.long 0x00 "CM_EMU_CLKSTCTRL,This register enables the EMU domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_EMU_SYS_CLK,This field indicates the state of the EMU_SYS_CLK clock in the domain" "CLKACTIVITY_EMU_SYS_CLK_0,CLKACTIVITY_EMU_SYS_CLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the EMU clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_EMU_DEBUGSS_CLKCTRL,This register manages the DEBUGSS clocks" hexmask.long.word 0x04 19.--31. 1. "RESERVED," bitfld.long 0x04 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline bitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x04 2.--15. 1. "RESERVED," newline bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" line.long 0x08 "CM_EMU_DYNAMICDEP,This register controls the dynamic domain depedencies from EMU domain towards 'target' domains" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.tbyte 0x08 6.--23. 1. "RESERVED," rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "CM_EMU_MPU_EMU_DBG_CLKCTRL,This register manages the MPU_EMU_DBG clocks" hexmask.long.word 0x0C 18.--31. 1. "RESERVED," bitfld.long 0x0C 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x0C 2.--15. 1. "RESERVED," bitfld.long 0x0C 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" width 0x0B tree.end tree "EMU_PRM" base ad:0x4AE07900 rgroup.long 0x00++0x07 line.long 0x00 "PM_EMU_PWRSTCTRL,This register controls the EMU power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," bitfld.long 0x00 16.--17. "EMU_BANK_ONSTATE,EMU memory state when domain is ON" "?,?,?,EMU_BANK_ONSTATE_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,?,?,?" line.long 0x04 "PM_EMU_PWRSTST,This register provides a status on the EMU domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "EMU_BANK_STATEST,EMU memory bank state status" "EMU_BANK_STATEST_0,EMU_BANK_STATEST_1,EMU_BANK_STATEST_2,EMU_BANK_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,?,?,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_EMU_DEBUGSS_CONTEXT,This register contains dedicated DEBUGSS context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_EMU_BANK,Specify if memory-based context in EMU_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EMU_BANK_0,LOSTMEM_EMU_BANK_1" hexmask.long.byte 0x00 1.--7. 1. "RESERVED," newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "ESM" base ad:0x4A23C000 group.long 0x00++0x17 line.long 0x00 "ESMIEPSR1,ESM Influence Error Pin Set/Status Register 1" line.long 0x04 "ESMIEPCR1,ESM Influence Error Pin Clear/Status Register 1" line.long 0x08 "ESMIESR1,ESM Interrupt Enable Set/Status Register 1" line.long 0x0C "ESMIECR1,ESM Interrupt Enable Clear/Status Register 1" line.long 0x10 "ESMILSR1,ESM Interrupt Level Set/Status Register 1" line.long 0x14 "ESMILCR1,ESM Interrupt Level Clear/Status Register 1" group.long 0x20++0x37 line.long 0x00 "ESMSR3,ESM Status Register 3" line.long 0x04 "ESMEPSR,ESM Error Pin Status Register" hexmask.long 0x04 1.--31. 1. "RES,Reads return 0 and writes have no effect" bitfld.long 0x04 0. "EPSF,Provides status information for the Error Pin" "Error Pin is low (active) if any error has..,Error Pin is high if no error has occurred User.." line.long 0x08 "ESMIOFFHR,ESM Interrupt Offset High Register" hexmask.long.tbyte 0x08 9.--31. 1. "RES,Reads return 0 and writes have no effect" abitfld.long 0x08 0.--8. "INTOFFH,This vector gives the channel number of the highest pending interrupt request for the high level interrupt line" "0x000=no pending interrupt,0x001=interrupt pending for channel 0 error group1,0x020=interrupt pending for channel 31 error..,0x021=interrupt pending for channel 0 error group2,0x040=interrupt pending for channel 31 error..,0x041=interrupt pending for channel 32 error..,0x060=interrupt pending for channel 63 error..,0x061=interrupt pending for channel 32 error..,0x080=interrupt pending for channel 63 error..,0x081=interrupt pending for channel 64 error..,0x0A0=interrupt pending for channel 95 error..,0x0A1=interrupt pending for channel 64 error..,0x0C0=interrupt pending for channel 95 error..,0x0C1=interrupt pending for channel 96 error..,0x0E0=interrupt pending for channel 127 error..,0x0E1=interrupt pending for channel 96 error..,0x100=interrupt pending for channel 127 error.." line.long 0x0C "ESMIOFFLR,ESM Interrupt Offset Low Register" hexmask.long.tbyte 0x0C 8.--31. 1. "RES,Reads return 0 and writes have no effect" abitfld.long 0x0C 0.--7. "INTOFFL,This vector gives the channel number of the highest pending interrupt request for the low level interrupt line" "0x00=no pending interrupt,0x01=interrupt pending for channel 0 error group1,0x20=interrupt pending for channel 31 error group1,0x41=interrupt pending for channel 32 error group1,0x60=interrupt pending for channel 63 error group1,0x81=interrupt pending for channel 64 error group1,0xA0=interrupt pending for channel 95 error group1,0xC1=interrupt pending for channel 96 error group1,0xE0=interrupt pending for channel 127 error.." line.long 0x10 "ESMLTCR,ESM Low-Time Counter Register" hexmask.long.word 0x10 16.--31. 1. "RES,Reads return 0 and writes have no effect" hexmask.long.word 0x10 0.--15. 1. "LTC,16bit pre-loadable down-counter to control low-time of error pin" line.long 0x14 "ESMLTCPR,ESM Low-Time Counter Preload Register" hexmask.long.word 0x14 16.--31. 1. "RES,Reads return 0 and writes have no effect" bitfld.long 0x14 14.--15. "LTCPW,LTCP.15 and LTCP.14 are configurable (privilege mode write) to ensure a minimum low time of 100us running at a maximum frequency of 100MHz" "0,1,2,3" hexmask.long.word 0x14 0.--13. 1. "LTCPR,pre-load value for the error pin low-time counter" line.long 0x18 "ESMEKR,ESM Error Key Register" hexmask.long 0x18 4.--31. 1. "RES,Reads return 0 and writes have no effect" bitfld.long 0x18 0.--3. "EKEY,Key to reset the error pin or to force an error on the error pin" "activates normal mode (recommended default mode),?,?,?,?,error pin will be set to high when the low time..,?,?,?,?,forces error on error pin,?..." line.long 0x1C "ESMSSR2,ESM Status Shadow Register 2" line.long 0x20 "ESMIEPSR4,ESM Influence Error Pin Set/Status Register 4" line.long 0x24 "ESMIEPCR4,ESM Influence Error Pin Clear/Status Register 4" line.long 0x28 "ESMIESR4,ESM Interrupt Enable Set/Status Register 4" line.long 0x2C "ESMIECR4,ESM Interrupt Enable Clear/Status Register 4" line.long 0x30 "ESMILSR4,ESM Interrupt Level Set/Status Register 4" line.long 0x34 "ESMILCR4,ESM Interrupt Level Clear/Status Register 4" group.long 0x5C++0x0B line.long 0x00 "ESMSR5,ESM Status Register 5" line.long 0x04 "ESMSR6,ESM Status Register 6" line.long 0x08 "ESMSSR5,ESM Status Shadow Register 5" group.long 0x80++0x17 line.long 0x00 "ESMIEPSR7,ESM Influence Error Pin Set/Status Register 7" line.long 0x04 "ESMIEPCR7,ESM Influence Error Pin Clear/Status Register 7" line.long 0x08 "ESMIESR7,ESM Interrupt Enable Set/Status Register 7" line.long 0x0C "ESMIECR7,ESM Interrupt Enable Clear/Status Register 7" line.long 0x10 "ESMILSR7,ESM Interrupt Level Set/Status Register 7" line.long 0x14 "ESMILCR7,ESM Interrupt Level Clear/Status Register 7" group.long 0x9C++0x0B line.long 0x00 "ESMSR8,ESM Status Register 8" line.long 0x04 "ESMSR9,ESM Status Register 9" line.long 0x08 "ESMSSR8,ESM Status Shadow Register 8" group.long 0xC0++0x17 line.long 0x00 "ESMIEPSR10,ESM Influence Error Pin Set/Status Register 10" line.long 0x04 "ESMIEPCR10,ESM Influence Error Pin Clear/Status Register 10" line.long 0x08 "ESMIESR10,ESM Interrupt Enable Set/Status Register 10" line.long 0x0C "ESMIECR10,ESM Interrupt Enable Clear/Status Register 10" line.long 0x10 "ESMILSR10,ESM Interrupt Level Set/Status Register 10" line.long 0x14 "ESMILCR10,ESM Interrupt Level Clear/Status Register 10" group.long 0xDC++0x0B line.long 0x00 "ESMSR11,ESM Status Register 11" line.long 0x04 "ESMSR12,ESM Status Register 12" line.long 0x08 "ESMSSR11,ESM Status Shadow Register 11" repeat 5. (list 1. 2. 4. 7. 10. )(list 0x00 0x04 0x40 0x80 0xC0 ) group.long ($2+0x18)++0x03 line.long 0x00 "ESMSR$1,ESM Status Register 1" repeat.end width 0x0B tree.end tree "ESM_TARG" base ad:0x4A23D000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "EVE" base ad:0x42000000 rgroup.long 0x80000++0x2F line.long 0x00 "EVE_REVISION," line.long 0x04 "EVE_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," newline bitfld.long 0x04 0.--3. "EVENUM,EVE instance number set by eve_num inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EVE_SYSCONFIG," hexmask.long 0x08 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x08 4.--5. "STANDBYMODE," "?,No-Standby,Smart-Standby,Smart-Standby-Wkup" newline bitfld.long 0x08 2.--3. "IDLEMODE," "?,No-idle,Smart-idle,SmartIdleWkup" newline rbitfld.long 0x08 1. "FREEEMU,Resered" "0,1" newline rbitfld.long 0x08 0. "SOFTRESET,Reserved" "0,1" line.long 0x0C "EVE_STAT," hexmask.long.word 0x0C 22.--31. 1. "RESERVED," newline bitfld.long 0x0C 20.--21. "OCPI_DISC_STAT,OCP Initiator(s) Disconnect status2" "OCPI_DISC_STAT_0,OCPI_DISC_STAT_1,OCPI_DISC_STAT_2,?" newline bitfld.long 0x0C 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 16.--17. "ARP32_DISC_STATUS,ARP32 Program/Data Bus Disconnect Status 2" "ARP32_DISC_STATUS_0,ARP32_DISC_STATUS_1,ARP32_DISC_STATUS_2,?" newline hexmask.long.byte 0x0C 9.--15. 1. "RESERVED," newline bitfld.long 0x0C 8. "INT_OUT_STAT,Interrupt Output status" "INT_OUT_STAT_0,INT_OUT_STAT_1" newline bitfld.long 0x0C 7. "ARP32_INTC_STAT,Interrupt Controller Status" "ARP32_INTC_STAT_0,ARP32_INTC_STAT_1" newline bitfld.long 0x0C 6. "RESERVED," "0,1" newline bitfld.long 0x0C 5. "TC1_STAT,Transfer Controller1 Status" "TC1_STAT_0,TC1_STAT_1" newline bitfld.long 0x0C 4. "TC0_STAT,Transfer Controller0 Status" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "PC_STAT,Program Cache Status" "PC_STAT_0,PC_STAT_1" newline bitfld.long 0x0C 1. "VCOP_STAT,VCOP Status" "VCOP_STAT_0,VCOP_STAT_1" newline bitfld.long 0x0C 0. "ARP32_STAT,Program Cache Status" "ARP32_STAT_0,ARP32_STAT_1" line.long 0x10 "EVE_DISC_CONFIG,Color 0 noise threshold" hexmask.long 0x10 5.--31. 1. "RESERVED," newline bitfld.long 0x10 4. "OCPI_DISC,OCP Initiator Disconnect request" "OCPI_DISC_0_r,OCPI_DISC_1_w" newline rbitfld.long 0x10 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0. "ARP32_DISC,ARP32 Initiator Disconnect request" "?,ARP32_DISC_1_r" line.long 0x14 "EVE_BUS_CONFIG,Color 0 noise threshold" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED," newline bitfld.long 0x14 12.--13. "TC1_DBS,TC1 default burst size" "16 byte,32 byte,64 byte,128 byte.." newline rbitfld.long 0x14 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 8.--9. "TC0_DBS,TC0 default burst size" "16 byte,32 byte,64 byte,128 byte.." newline rbitfld.long 0x14 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 4. "DBP_ENABLE,Program Cache Demand Based Prefetch enable" "DBP_ENABLE_0,DBP_ENABLE_1" newline bitfld.long 0x14 0.--3. "MAX_IN_FLIGHT,Defines maximum number of OCP requests in flight" "Reserved,1 request in flight allowed,2 requests in flight allowed,?..." line.long 0x18 "EVE_VCOP_HALT_CONFIG," hexmask.long 0x18 3.--31. 1. "RESERVED," newline bitfld.long 0x18 2. "FORCE_ABORT,VCOP Force Abort Write: Read always returns 0sWrite 0 has no effect" "?,FORCE_ABORT_1_w" newline bitfld.long 0x18 1. "MSW_EN,VCOP Memory Seitch Error Halt Enable" "MSW_EN_0,MSW_EN_1" newline bitfld.long 0x18 0. "ED_EN,VCOP Parity Error Detect Halt Enable" "ED_EN_0,ED_EN_1" line.long 0x1C "EVE_MMU_CONFIG," hexmask.long.tbyte 0x1C 13.--31. 1. "RESERVED," newline bitfld.long 0x1C 12. "MMU1_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" newline rbitfld.long 0x1C 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "MMU0_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" newline rbitfld.long 0x1C 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 4. "MMU1_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" newline rbitfld.long 0x1C 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "MMU0_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" line.long 0x20 "EVE_MEMMAP," hexmask.long 0x20 5.--31. 1. "RESERVED," newline bitfld.long 0x20 4. "LCL_EDMA_ALIAS," "?,LCL_EDMA_ALIAS_1" newline rbitfld.long 0x20 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0. "VCOP_ALIAS," "?,VCOP_ALIAS_1" line.long 0x24 "EVE_MSW_CTL,Memory switch control register" hexmask.long.word 0x24 17.--31. 1. "RESERVED," newline bitfld.long 0x24 16. "WBUF,Working buffer onwership" "WBUF_0,WBUF_1" newline rbitfld.long 0x24 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 12. "IBUFHB,Image buffer high B ownership" "IBUFHB_0,IBUFHB_1" newline rbitfld.long 0x24 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8. "IBUFLB,Image buffer low B ownership" "IBUFLB_0,IBUFLB_1" newline rbitfld.long 0x24 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 4. "IBUFHA,Image buffer high A ownership" "IBUFHA_0,IBUFHA_1" newline rbitfld.long 0x24 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "IBUFLA,Image buffer low A ownership" "IBUFLA_0,IBUFLA_1" line.long 0x28 "EVE_MSW_ERR,Memory Switch Error register" hexmask.long.byte 0x28 25.--31. 1. "RESERVED," newline hexmask.long.word 0x28 16.--24. 1. "CONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x28 4.--15. 1. "RESERVED," newline bitfld.long 0x28 3. "SYSERR," "0,1" newline bitfld.long 0x28 2. "DMAERR," "0,1" newline bitfld.long 0x28 1. "VERR," "0,1" newline bitfld.long 0x28 0. "ARP32ERR," "0,1" line.long 0x2C "EVE_MSW_ERRADDR,Memory switch error address register" group.long 0x80040++0x03 line.long 0x00 "EVE_PC_INV,Invalidate all register" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "I,Invalidate all:Read" "Invalidate operation complete / or not in progress,Invalidate operation still in progress" group.long 0x80050++0x17 line.long 0x00 "EVE_PC_IBAR,Invalidate Base Address register" line.long 0x04 "EVE_PC_IBC,Invalidate byte count register" hexmask.long.word 0x04 16.--31. 1. "RESERVED," newline hexmask.long.word 0x04 0.--15. 1. "BC,Invalidate Byte Count register" line.long 0x08 "EVE_PC_ISAR,Invalidate single address register" line.long 0x0C "EVE_PC_ISAR_DONE,Invalidate single address done register" hexmask.long 0x0C 1.--31. 1. "RESERVED," newline bitfld.long 0x0C 0. "DONE,Reads return 0x1 when the invalidate operation is complete" "0,1" line.long 0x10 "EVE_PC_PBAR,Program cache preload base address register" line.long 0x14 "EVE_PC_PBC," hexmask.long.word 0x14 16.--31. 1. "RESERVED," newline hexmask.long.word 0x14 0.--15. 1. "BC,Preload Byte Count register" group.long 0x80080++0x0B line.long 0x00 "EVE_PMEM_ED_CTL,Program Memory Error Detection Control register" hexmask.long 0x00 2.--31. 1. "RESERVED," newline bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_PMEM_ED_STAT,Error detection status register" hexmask.long.byte 0x04 25.--31. 1. "RESERVED," newline hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_PMEM_EDADDR,Program memory error detection address" group.long 0x80090++0x2F line.long 0x00 "EVE_DMEM_ED_CTL,DMEM error detection control" hexmask.long 0x00 2.--31. 1. "RESERVED," newline bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_DMEM_ED_STAT,DMEM error detection status register" hexmask.long.byte 0x04 25.--31. 1. "RESERVED," newline hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_DMEM_EDADDR,DMEM error detection address register" line.long 0x0C "EVE_DMEM_EDADDR_BO,DMEM error detection address byte offset register" line.long 0x10 "EVE_WBUF_ED_CTL,WBUF error detection control" hexmask.long 0x10 2.--31. 1. "RESERVED," newline bitfld.long 0x10 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x10 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x14 "EVE_WBUF_ED_STAT,WBUF error detection status register" hexmask.long.byte 0x14 25.--31. 1. "RESERVED," newline hexmask.long.word 0x14 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x14 4.--15. 1. "RESERVED," newline bitfld.long 0x14 3. "SYSERR," "0,1" newline bitfld.long 0x14 2. "DMAERR," "0,1" newline bitfld.long 0x14 1. "VERR," "0,1" newline bitfld.long 0x14 0. "ARP32ERR," "0,1" line.long 0x18 "EVE_WBUF_EDADDR,WBUF error detection address register" line.long 0x1C "EVE_WBUF_EDADDR_BO,WBUF error detection address byte offset register" line.long 0x20 "EVE_IBUF_ED_CTL,IBUF error detection control" hexmask.long 0x20 2.--31. 1. "RESERVED," newline bitfld.long 0x20 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x20 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x24 "EVE_IBUF_ED_STAT,IBUF error detection status register" hexmask.long.byte 0x24 25.--31. 1. "RESERVED," newline hexmask.long.word 0x24 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x24 4.--15. 1. "RESERVED," newline bitfld.long 0x24 3. "SYSERR," "0,1" newline bitfld.long 0x24 2. "DMAERR," "0,1" newline bitfld.long 0x24 1. "VERR," "0,1" newline bitfld.long 0x24 0. "ARP32ERR," "0,1" line.long 0x28 "EVE_IBUF_EDADDR,IBUF error detection address register" line.long 0x2C "EVE_IBUF_EDADDR_BO,IBUF error detection address byte offset register" group.long 0x800F8++0x07 line.long 0x00 "EVE_ED_ARP32_DISC_EN,ARP32 disconnect enable register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline abitfld.long 0x00 0.--15. "ENABLE,Disconnect Enable for Event #n" "0x0000=Disconnect disabled,0x0001=Disconnect enabled" line.long 0x04 "EVE_ED_OCPI_DISC_EN,OCP interface disconnect enable register" hexmask.long.word 0x04 16.--31. 1. "RESERVED," newline abitfld.long 0x04 0.--15. "ENABLE,Disconnect Enable for Event #n" "0x0000=Disconnect disabled,0x0001=Disconnect enabled" group.long 0x80110++0x1F line.long 0x00 "EVE_MSW_ERR_IRQSTATUS_RAW,Per event memory switch error interrupt status register" hexmask.long 0x00 4.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "EVENT,settable raw status for event #n" "No event pending,Set event (for debug),?..." line.long 0x04 "EVE_MSW_ERR_IRQSTATUS,Memory switch error interrupt status register" hexmask.long 0x04 4.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--3. "EVENT,Clearable / enabled status for event #N" "No (enabled) event pending,Clear raw event,?..." line.long 0x08 "EVE_MSW_ERR_IRQENABLE_SET,Memory switch error interrupt enable register" hexmask.long 0x08 4.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--3. "ENABLE,Enable for event #n" "Interrupt disabled,Enable interrupt,?..." line.long 0x0C "EVE_MSW_ERR_IRQENABLE_CLR,Memory switch error interrupt clear register" hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "ENABLE,Enable for event #n" "Interrupt disabled,Disable interrupt (i.e. / clear ENABLEn bit),?..." line.long 0x10 "EVE_ED_LCL_IRQSTATUS_RAW,Per event error detection local interrupt status register" hexmask.long.word 0x10 16.--31. 1. "RESERVED," newline abitfld.long 0x10 0.--15. "EVENT,settable raw status for event #n" "0x0000=No event pending,0x0001=Set event (for debug)" line.long 0x14 "EVE_ED_LCL_IRQSTATUS,Error detection local interrupt status register" hexmask.long.word 0x14 16.--31. 1. "RESERVED," newline abitfld.long 0x14 0.--15. "EVENT,Clearable / enabled status for event #N" "0x0000=No (enabled) event pending,0x0001=Clear raw event" line.long 0x18 "EVE_ED_LCL_IRQENABLE_SET,Error detection local interrupt enable register" hexmask.long.word 0x18 16.--31. 1. "RESERVED," newline abitfld.long 0x18 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Enable interrupt" line.long 0x1C "EVE_ED_LCL_IRQENABLE_CLR,Error detection local interrupt clear register" hexmask.long.word 0x1C 16.--31. 1. "RESERVED," newline abitfld.long 0x1C 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Disable interrupt (i.e. / clear ENABLEn.." group.long 0x80210++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_4," group.long 0x80220++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_5," group.long 0x80230++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_6," group.long 0x80240++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_7," group.long 0x80214++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_4," group.long 0x80224++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_5," group.long 0x80234++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_6," group.long 0x80244++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_7," group.long 0x80218++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_4," group.long 0x80228++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_5," group.long 0x80238++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_6," group.long 0x80248++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_7," group.long 0x8021C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_4," group.long 0x8022C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_5," group.long 0x8023C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_6," group.long 0x8024C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_7," group.long 0x80200++0x0F line.long 0x00 "ARP32_NMI_IRQSTATUS_RAW," line.long 0x04 "ARP32_NMI_IRQSTATUS," line.long 0x08 "ARP32_NMI_IRQENABLE_SET," line.long 0x0C "ARP32_NMI_IRQENABLE_CLR," group.long 0x802FC++0x2B line.long 0x00 "ARP32_IRQWAKEEN,Wake enable register" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," newline abitfld.long 0x00 0.--23. "ENABLE,Wakeup Enable for event EVE_EVT_INT #n" "0x000000=Interrupt #n disabled for wakeup,0x000001=Interrupt #n enabled for wakeup" line.long 0x04 "MMR_LOCKi_0,MMR Lock/Unlock register" line.long 0x08 "MMR_LOCKi_1,MMR Lock/Unlock register" line.long 0x0C "MMR_LOCKi_2,MMR Lock/Unlock register" line.long 0x10 "MMR_LOCKi_3,MMR Lock/Unlock register" line.long 0x14 "MMR_LOCKi_4,MMR Lock/Unlock register" line.long 0x18 "MMR_LOCKi_5,MMR Lock/Unlock register" line.long 0x1C "MMR_LOCKi_6,MMR Lock/Unlock register" line.long 0x20 "MMR_LOCKi_7,MMR Lock/Unlock register" line.long 0x24 "MMR_LOCKi_8,MMR Lock/Unlock register" line.long 0x28 "MMR_LOCKi_9,MMR Lock/Unlock register" group.long 0x80400++0x07 line.long 0x00 "MISR_CTL," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "ENABLE,MISR Enable #N" "ARP32 PMEM path Bit,ARP32 DMEM path Bit,INTC WBUF path,?..." line.long 0x04 "MISR_CLEAR," hexmask.long 0x04 3.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--2. "CLEAR,MISR Clear #N" "Previous MISR clear command has completed,MISR Clear in progress (this state may never..,?..." group.long 0x80410++0x1F line.long 0x00 "MISR0_A," line.long 0x04 "MISR0_D," line.long 0x08 "MISR1_A," line.long 0x0C "MISR1_D," line.long 0x10 "MISR2_Dk_0," line.long 0x14 "MISR2_Dk_1," line.long 0x18 "MISR2_Dk_2," line.long 0x1C "MISR2_Dk_3," group.long 0x80500++0x03 line.long 0x00 "EVE_IRQ_EOI," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0,1,2,3,4,5,6,7" group.long 0x80510++0x13 line.long 0x00 "EVE_ED_OUT_IRQSTATUS_RAW," hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline abitfld.long 0x00 0.--15. "EVENT,Settable raw status for event #n" "0x0000=No event pending,0x0001=Set event (for debug)" line.long 0x04 "EVE_ED_OUT_IRQSTATUS," hexmask.long.word 0x04 16.--31. 1. "RESERVED," newline abitfld.long 0x04 0.--15. "EVENT,Clearable / enabled status for event #N" "0x0000=No (enabled) event pending,0x0001=Clear raw event" line.long 0x08 "EVE_ED_OUT_IRQENABLE_SET," hexmask.long.word 0x08 16.--31. 1. "RESERVED," newline abitfld.long 0x08 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Enable interrupt" line.long 0x0C "EVE_ED_OUT_IRQENABLE_CLR," hexmask.long.word 0x0C 16.--31. 1. "RESERVED," newline abitfld.long 0x0C 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Disable interrupt (i.e. / clear ENABLEn.." line.long 0x10 "EVE_INTk_OUT_IRQSTATUS_RAW_0," group.long 0x80530++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_1," group.long 0x80540++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_2," group.long 0x80550++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_3," group.long 0x80524++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_0," group.long 0x80534++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_1," group.long 0x80544++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_2," group.long 0x80554++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_3," group.long 0x80528++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_0," group.long 0x80538++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_1," group.long 0x80548++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_2," group.long 0x80558++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_3," group.long 0x8052C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_0," group.long 0x8053C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_1," group.long 0x8054C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_2," group.long 0x8055C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_3," rgroup.long 0x80600++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_8," rgroup.long 0x80610++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_9," rgroup.long 0x80620++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_10," rgroup.long 0x80630++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_11," rgroup.long 0x80640++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_12," rgroup.long 0x80650++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_13," group.long 0x80604++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_8," group.long 0x80614++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_9," group.long 0x80624++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_10," group.long 0x80634++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_11," group.long 0x80644++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_12," group.long 0x80654++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_13," group.long 0x80608++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_8," group.long 0x80618++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_9," group.long 0x80628++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_10," group.long 0x80638++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_11," group.long 0x80648++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_12," group.long 0x80658++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_13," group.long 0x8060C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_8," group.long 0x8061C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_9," group.long 0x8062C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_10," group.long 0x8063C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_11," group.long 0x8064C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_12," group.long 0x8065C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_13," rgroup.long 0x80680++0x1F line.long 0x00 "ARP32_INT14_IRQSTATUS_RAW," line.long 0x04 "ARP32_INT14_IRQSTATUS," line.long 0x08 "ARP32_INT14_IRQENABLE_SET," line.long 0x0C "ARP32_INT14_IRQENABLE_CLR," line.long 0x10 "ARP32_INT15_IRQSTATUS_RAW," line.long 0x14 "ARP32_INT15_IRQSTATUS," line.long 0x18 "ARP32_INT15_IRQENABLE_SET," line.long 0x1C "ARP32_INT15_IRQENABLE_CLR," group.long 0x80700++0x03 line.long 0x00 "EVE_GPOUTm_0," group.long 0x80710++0x03 line.long 0x00 "EVE_GPOUTm_1," group.long 0x80704++0x03 line.long 0x00 "EVE_GPOUTm_SET_0," group.long 0x80714++0x03 line.long 0x00 "EVE_GPOUTm_SET_1," group.long 0x80708++0x03 line.long 0x00 "EVE_GPOUTm_CLR_0," group.long 0x80718++0x03 line.long 0x00 "EVE_GPOUTm_CLR_1," group.long 0x8070C++0x03 line.long 0x00 "EVE_GPOUTm_PULSE_0," group.long 0x8071C++0x03 line.long 0x00 "EVE_GPOUTm_PULSE_1," group.long 0x80780++0x17 line.long 0x00 "EVE_CME_DONE_GPOUT," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," newline abitfld.long 0x00 0.--7. "EVENT,Internal CME Done Output #n" "0x00=Drive Internal CME Done #n is low/0,0x01=Internal CME Done is high/1" line.long 0x04 "EVE_CME_DONE_GPOUT_SET," hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," newline abitfld.long 0x04 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done is high/1" line.long 0x08 "EVE_CME_DONE_GPOUT_CLR," hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED," newline abitfld.long 0x08 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done #n is high/1" line.long 0x0C "EVE_CME_DONE_GPOUT_PULSE," hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED," newline abitfld.long 0x0C 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done #n is high/1" line.long 0x10 "EVE_CME_DONE_SEL," bitfld.long 0x10 28.--31. "SEL7,CME Done Output select for Bit #7 (n=7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 24.--27. "SEL6,CME Done Output select for Bit #6 (n=6)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 20.--23. "SEL5,CME Done Output select for Bit #5 (n=5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 16.--19. "SEL4,CME Done Output select for Bit #4 (n=4)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 12.--15. "SEL3,CME Done Output select for Bit #3 (n=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 8.--11. "SEL2,CME Done Output select for Bit #2 (n=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 4.--7. "SEL1,CME Done Output select for Bit #1 (n=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--3. "SEL0,CME Done Output select for Bit #0 (n=0)" "Driven by EDMA cc_int0,Driven by EDMA cc_int1,Driven by EDMA cc_int2,Driven by EDMA cc_int3,Driven by EDMA cc_int4,Driven by EDMA cc_int5,Driven by EDMA cc_int6,Driven by EDMA cc_int7,Driven by EVE_CME_DONE_GPOUTn,driven by eve_cme_done_gpout[0+n] (from EVE),driven by eve_cme_done_gpout[8+n] (from EVE2),driven by eve_cme_done_gpout[16+n] (from EVE3),driven by eve_cme_done_gpout[24+n] (from EVE4),driven by eve_cme_done_gpout[32+n] (from EVE5),driven by eve_cme_done_gpout[40+n] (from EVE6),driven by eve_cme_done_gpout[48+n] (from EVE7)" line.long 0x14 "EVE_CME_DONE_EN," hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," newline abitfld.long 0x14 0.--7. "EN,EVE CME Done EN #n" "0x00=EVE CME Done #n is disabled,0x01=EVE CME Done #n is enabled" rgroup.long 0x80FE0++0x0B line.long 0x00 "EVE_PM_STAT0," bitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 28.--30. "OCPM1_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 26.--27. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 24.--25. "OCPM1_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 23. "RESERVED," "0,1" newline bitfld.long 0x00 20.--22. "OCPM0_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 16.--17. "OCPM0_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 12.--14. "OCPS_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 8.--9. "OCPS_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 5. "MWAIT,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 4. "MSTANDBY,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 3. "SWAKEUP,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 1.--2. "SIDLEACK,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 0. "SIDLEREQ,Readable state of OCP Power management handshake" "0,1" line.long 0x04 "EVE_PM_STAT1," hexmask.long.byte 0x04 24.--31. 1. "RESERVED," newline rbitfld.long 0x04 22.--23. "STBY_MDISCACK_OCPM1,Readable state of internal power management handshake" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "STBY_MDISCACK_OCPM0,Readable state of internal power management handshake" "0,1,2,3" newline rbitfld.long 0x04 19. "STBY_MDISCREQ_OCPM1,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 18. "STBY_MDISCREQ_OCPM0,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 17. "IDLE_SDISCONNECT_ACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 16. "IDLE_SDISCONNECT_REQ,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 15. "EVE_IDLE_INTR_DISABLE,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 14. "TPTC1_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 13. "TPTC0_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 12. "EVE_PCACHE_OCP_BUSY,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 11. "EVE_CONTROL_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 10. "SMSET_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 9. "L2_EVE_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 8. "MMU1_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 7. "MMU1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 6. "MMU0_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 5. "MMU0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 4. "SCTM_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 3. "TPCC_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 2. "TPTC1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 1. "TPTC0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline bitfld.long 0x04 0. "SUBMODULE_IDLE_REQ," "0,1" line.long 0x08 "EVE_DBGOUT," hexmask.long.tbyte 0x08 8.--31. 1. "VALUE,Read returns state of eve_dbgout bus" newline rbitfld.long 0x08 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. "GROUP,Debug Group Output control : mux select" "disabled / all debug outputs driven to 0x0,select output group1,select output group2,?..." group.long 0x80FFC++0x03 line.long 0x00 "EVE_TEST," repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x80FF4)++0x03 line.long 0x00 "EVE_RSVD$1," repeat.end repeat 2. (list 0. 1. )(list 0x00 0x04 ) rgroup.long ($2+0x80740)++0x03 line.long 0x00 "EVE_GPIN$1," repeat.end width 0x0B tree.end tree "EVE1_CM_CORE_AON" base ad:0x4A005640 group.long 0x00++0x07 line.long 0x00 "CM_EVE1_CLKSTCTRL,This register enables the EVE domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_EVE1_GFCLK,This field indicates the state of the EVE1_GFCLK clock in the domain" "CLKACTIVITY_EVE1_GFCLK_0,CLKACTIVITY_EVE1_GFCLK_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_EVE1_STATICDEP,This register controls the static domain depedencies from EVE1 domain towards 'target' domains" hexmask.long.word 0x04 23.--31. 1. "RESERVED," bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain" "EVE2_STATDEP_0,EVE2_STATDEP_1" hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 3. "RESERVED," "0,1" bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" group.long 0x20++0x03 line.long 0x00 "CM_EVE1_EVE1_CLKCTRL,This register manages the EVE clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "EVE1_PRM" base ad:0x4AE07B40 group.long 0x00++0x07 line.long 0x00 "PM_EVE1_PWRSTCTRL,This register controls the EVE power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "EVE1_BANK_ONSTATE,EVE1 state when domain is ON" "?,?,?,EVE1_BANK_ONSTATE_3" newline hexmask.long.word 0x00 5.--15. 1. "RESERVED," bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_EVE1_PWRSTST,This register provides a status on the EVE domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "EVE1_BANK_STATEST,EVE0 memory state status" "EVE1_BANK_STATEST_0,EVE1_BANK_STATEST_1,EVE1_BANK_STATEST_2,EVE1_BANK_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_EVE1_RSTCTRL,This register controls the release of the EVE sub-system resets" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "RST_EVE1,EVE reset control" "RST_EVE1_0,RST_EVE1_1" newline bitfld.long 0x00 0. "RST_EVE1_LRST,EVE Local reset control" "RST_EVE1_LRST_0,RST_EVE1_LRST_1" line.long 0x04 "RM_EVE1_RSTST,This register logs the different reset sources of the EVE domain" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "RST_EVE1_EMU_REQ,EVE1 processor has been reset due to EVE emulation reset request driven from EVE1-SS" "RST_EVE1_EMU_REQ_0,RST_EVE1_EMU_REQ_1" newline bitfld.long 0x04 2. "RST_EVE1_EMU,EVE1 domain has been reset due to emulation reset source e.g" "RST_EVE1_EMU_0,RST_EVE1_EMU_1" bitfld.long 0x04 1. "RST_EVE1,EVE0 SW reset status" "RST_EVE1_0,RST_EVE1_1" newline bitfld.long 0x04 0. "RST_EVE1_LRST,EVE0 Local SW reset" "RST_EVE1_LRST_0,RST_EVE1_LRST_1" group.long 0x20++0x07 line.long 0x00 "PM_EVE1_EVE1_WKDEP,This register controls wakeup dependency based on EVE1 service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_EVE1_EVE4,Wakeup dependency from EVE1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_EVE4_0,WKUPDEP_EVE1_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_EVE1_EVE3,Wakeup dependency from EVE1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_EVE3_0,WKUPDEP_EVE1_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_EVE1_EVE2,Wakeup dependency from EVE1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_EVE2_0,WKUPDEP_EVE1_EVE2_1" newline rbitfld.long 0x00 6. "RESERVED," "0,1" bitfld.long 0x00 5. "WKUPDEP_EVE1_DSP2,Wakeup dependency from EVE1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_DSP2_0,WKUPDEP_EVE1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_EVE1_IPU1,Wakeup dependency from EVE1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_IPU1_0,WKUPDEP_EVE1_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_EVE1_SDMA,Wakeup dependency from EVE1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_SDMA_0,WKUPDEP_EVE1_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_EVE1_DSP1,Wakeup dependency from EVE1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_DSP1_0,WKUPDEP_EVE1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_EVE1_IPU2,Wakeup dependency from EVE1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_IPU2_0,WKUPDEP_EVE1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_EVE1_MPU,Wakeup dependency from EVE1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_MPU_0,WKUPDEP_EVE1_MPU_1" line.long 0x04 "RM_EVE1_EVE1_CONTEXT,This register contains dedicated EVE context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_EVE_BANK,Specify if memory-based context in EVE1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EVE_BANK_0,LOSTMEM_EVE_BANK_1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "EVE2_CM_CORE_AON" base ad:0x4A005680 group.long 0x00++0x07 line.long 0x00 "CM_EVE2_CLKSTCTRL,This register enables the EVE domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_EVE2_GFCLK,This field indicates the state of the EVE2_GFCLK clock in the domain" "CLKACTIVITY_EVE2_GFCLK_0,CLKACTIVITY_EVE2_GFCLK_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_EVE2_STATICDEP,This register controls the static domain depedencies from EVE2 domain towards 'target' domains" hexmask.long.word 0x04 23.--31. 1. "RESERVED," bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" newline rbitfld.long 0x04 20. "RESERVED," "0,1" bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain" "EVE1_STATDEP_0,EVE1_STATDEP_1" hexmask.long.word 0x04 6.--18. 1. "RESERVED," newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" group.long 0x20++0x03 line.long 0x00 "CM_EVE2_EVE2_CLKCTRL,This register manages the EVE clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "EVE2_PRM" base ad:0x4AE07B80 group.long 0x00++0x07 line.long 0x00 "PM_EVE2_PWRSTCTRL,This register controls the EVE power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "EVE2_BANK_ONSTATE,EVE2 state when domain is ON" "?,?,?,EVE2_BANK_ONSTATE_3" newline hexmask.long.word 0x00 5.--15. 1. "RESERVED," bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_EVE2_PWRSTST,This register provides a status on the EVE domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "EVE2_BANK_STATEST,EVE2 memory state status" "EVE2_BANK_STATEST_0,EVE2_BANK_STATEST_1,EVE2_BANK_STATEST_2,EVE2_BANK_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_EVE2_RSTCTRL,This register controls the release of the EVE sub-system resets" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "RST_EVE2,EVE SW reset control" "RST_EVE2_0,RST_EVE2_1" newline bitfld.long 0x00 0. "RST_EVE2_LRST,EVE Local reset control" "RST_EVE2_LRST_0,RST_EVE2_LRST_1" line.long 0x04 "RM_EVE2_RSTST,This register logs the different reset sources of the EVE domain" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "RST_EVE2_EMU_REQ,EVE2 processor has been reset due to EVE emulation reset request driven from EVE2-SS" "RST_EVE2_EMU_REQ_0,RST_EVE2_EMU_REQ_1" newline bitfld.long 0x04 2. "RST_EVE2_EMU,EVE2 domain has been reset due to emulation reset source e.g" "RST_EVE2_EMU_0,RST_EVE2_EMU_1" bitfld.long 0x04 1. "RST_EVE2,EVE SW reset status" "RST_EVE2_0,RST_EVE2_1" newline bitfld.long 0x04 0. "RST_EVE2_LRST,EVE Local SW reset" "RST_EVE2_LRST_0,RST_EVE2_LRST_1" group.long 0x20++0x07 line.long 0x00 "PM_EVE2_EVE2_WKDEP,This register controls wakeup dependency based on EVE2 service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_EVE2_EVE4,Wakeup dependency from EVE2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_EVE4_0,WKUPDEP_EVE2_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_EVE2_EVE3,Wakeup dependency from EVE2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_EVE3_0,WKUPDEP_EVE2_EVE3_1" rbitfld.long 0x00 7. "RESERVED," "0,1" newline bitfld.long 0x00 6. "WKUPDEP_EVE2_EVE1,Wakeup dependency from EVE2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_EVE1_0,WKUPDEP_EVE2_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_EVE2_DSP2,Wakeup dependency from EVE2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_DSP2_0,WKUPDEP_EVE2_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_EVE2_IPU1,Wakeup dependency from EVE2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_IPU1_0,WKUPDEP_EVE2_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_EVE2_SDMA,Wakeup dependency from EVE2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_SDMA_0,WKUPDEP_EVE2_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_EVE2_DSP1,Wakeup dependency from EVE2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_DSP1_0,WKUPDEP_EVE2_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_EVE2_IPU2,Wakeup dependency from EVE2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_IPU2_0,WKUPDEP_EVE2_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_EVE2_MPU,Wakeup dependency from EVE2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_MPU_0,WKUPDEP_EVE2_MPU_1" line.long 0x04 "RM_EVE2_EVE2_CONTEXT,This register contains dedicated EVE context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_EVE_BANK,Specify if memory-based context in EVE2 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EVE_BANK_0,LOSTMEM_EVE_BANK_1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "EVE3_CM_CORE_AON" base ad:0x4A0056C0 group.long 0x00++0x07 line.long 0x00 "CM_EVE3_CLKSTCTRL,This register enables the EVE domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_EVE3_GFCLK,This field indicates the state of the EVE3_GFCLK clock in the domain" "CLKACTIVITY_EVE3_GFCLK_0,CLKACTIVITY_EVE3_GFCLK_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_EVE3_STATICDEP,This register controls the static domain depedencies from EVE3 domain towards 'target' domains" hexmask.long.word 0x04 23.--31. 1. "RESERVED," bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" rbitfld.long 0x04 21. "RESERVED," "0,1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain" "EVE2_STATDEP_0,EVE2_STATDEP_1" bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain" "EVE1_STATDEP_0,EVE1_STATDEP_1" hexmask.long.word 0x04 6.--18. 1. "RESERVED," newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" group.long 0x20++0x03 line.long 0x00 "CM_EVE3_EVE3_CLKCTRL,This register manages the EVE clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "EVE3_PRM" base ad:0x4AE07BC0 group.long 0x00++0x07 line.long 0x00 "PM_EVE3_PWRSTCTRL,This register controls the EVE power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "EVE3_BANK_ONSTATE,EVE3 state when domain is ON" "?,?,?,EVE3_BANK_ONSTATE_3" newline hexmask.long.word 0x00 5.--15. 1. "RESERVED," bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_EVE3_PWRSTST,This register provides a status on the EVE domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "EVE3_BANK_STATEST,EVE3 memory state status" "EVE3_BANK_STATEST_0,EVE3_BANK_STATEST_1,EVE3_BANK_STATEST_2,EVE3_BANK_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_EVE3_RSTCTRL,This register controls the release of the EVE sub-system resets" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "RST_EVE3,EVE SW reset control" "RST_EVE3_0,RST_EVE3_1" newline bitfld.long 0x00 0. "RST_EVE3_LRST,EVE3 Local reset control" "RST_EVE3_LRST_0,RST_EVE3_LRST_1" line.long 0x04 "RM_EVE3_RSTST,This register logs the different reset sources of the EVE domain" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "RST_EVE3_EMU_REQ,EVE3 processor has been reset due to EVE emulation reset request driven from EVE3-SS" "RST_EVE3_EMU_REQ_0,RST_EVE3_EMU_REQ_1" newline bitfld.long 0x04 2. "RST_EVE3_EMU,EVE3 domain has been reset due to emulation reset source e.g" "RST_EVE3_EMU_0,RST_EVE3_EMU_1" bitfld.long 0x04 1. "RST_EVE3,EVE3 SW reset status" "RST_EVE3_0,RST_EVE3_1" newline bitfld.long 0x04 0. "RST_EVE3_LRST,EVE3 Local SW reset" "RST_EVE3_LRST_0,RST_EVE3_LRST_1" group.long 0x20++0x07 line.long 0x00 "PM_EVE3_EVE3_WKDEP,This register controls wakeup dependency based on EVE3 service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_EVE3_EVE4,Wakeup dependency from EVE3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_EVE4_0,WKUPDEP_EVE3_EVE4_1" newline rbitfld.long 0x00 8. "RESERVED," "0,1" bitfld.long 0x00 7. "WKUPDEP_EVE3_EVE2,Wakeup dependency from EVE3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_EVE2_0,WKUPDEP_EVE3_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_EVE3_EVE1,Wakeup dependency from EVE3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_EVE1_0,WKUPDEP_EVE3_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_EVE3_DSP2,Wakeup dependency from EVE3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_DSP2_0,WKUPDEP_EVE3_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_EVE3_IPU1,Wakeup dependency from EVE3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_IPU1_0,WKUPDEP_EVE3_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_EVE3_SDMA,Wakeup dependency from EVE3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_SDMA_0,WKUPDEP_EVE3_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_EVE3_DSP1,Wakeup dependency from EVE3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_DSP1_0,WKUPDEP_EVE3_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_EVE3_IPU2,Wakeup dependency from EVE3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_IPU2_0,WKUPDEP_EVE3_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_EVE3_MPU,Wakeup dependency from EVE3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_MPU_0,WKUPDEP_EVE3_MPU_1" line.long 0x04 "RM_EVE3_EVE3_CONTEXT,This register contains dedicated EVE context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_EVE_BANK,Specify if memory-based context in EVE3 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EVE_BANK_0,LOSTMEM_EVE_BANK_1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "EVE4_CM_CORE_AON" base ad:0x4A005700 group.long 0x00++0x07 line.long 0x00 "CM_EVE4_CLKSTCTRL,This register enables the EVE domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_EVE4_GFCLK,This field indicates the state of the EVE3_GFCLK clock in the domain" "CLKACTIVITY_EVE4_GFCLK_0,CLKACTIVITY_EVE4_GFCLK_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_EVE4_STATICDEP,This register controls the static domain depedencies from EVE4 domain towards 'target' domains" hexmask.long.word 0x04 22.--31. 1. "RESERVED," bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain" "EVE1_STATDEP_0,EVE1_STATDEP_1" hexmask.long.word 0x04 6.--18. 1. "RESERVED," rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 3. "RESERVED," "0,1" bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" group.long 0x20++0x03 line.long 0x00 "CM_EVE4_EVE4_CLKCTRL,This register manages the EVE clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "EVE4_PRM" base ad:0x4AE07C00 group.long 0x00++0x07 line.long 0x00 "PM_EVE4_PWRSTCTRL,This register controls the EVE power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "EVE4_BANK_ONSTATE,EVE4 state when domain is ON" "?,?,?,EVE4_BANK_ONSTATE_3" newline hexmask.long.word 0x00 5.--15. 1. "RESERVED," bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_EVE4_PWRSTST,This register provides a status on the EVE domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "EVE4_BANK_STATEST,EVE4 memory state status" "EVE4_BANK_STATEST_0,EVE4_BANK_STATEST_1,EVE4_BANK_STATEST_2,EVE4_BANK_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_EVE4_RSTCTRL,This register controls the release of the EVE sub-system resets" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "RST_EVE4,EVE SW reset control" "RST_EVE4_0,RST_EVE4_1" newline bitfld.long 0x00 0. "RST_EVE4_LRST,EVE4 Local reset control" "RST_EVE4_LRST_0,RST_EVE4_LRST_1" line.long 0x04 "RM_EVE4_RSTST,This register logs the different reset sources of the EVE domain" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "RST_EVE4_EMU_REQ,EVE4 processor has been reset due to EVE emulation reset request driven from EVE4-SS" "RST_EVE4_EMU_REQ_0,RST_EVE4_EMU_REQ_1" newline bitfld.long 0x04 2. "RST_EVE4_EMU,EVE4 domain has been reset due to emulation reset source e.g" "RST_EVE4_EMU_0,RST_EVE4_EMU_1" bitfld.long 0x04 1. "RST_EVE4,EVE4 SW reset status" "RST_EVE4_0,RST_EVE4_1" newline bitfld.long 0x04 0. "RST_EVE4_LRST,EVE4 Local SW reset" "RST_EVE4_LRST_0,RST_EVE4_LRST_1" group.long 0x20++0x07 line.long 0x00 "PM_EVE4_EVE4_WKDEP,This register controls wakeup dependency based on EVE4 service requests" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "WKUPDEP_EVE4_EVE3,Wakeup dependency from EVE4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_EVE3_0,WKUPDEP_EVE4_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_EVE4_EVE2,Wakeup dependency from EVE4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_EVE2_0,WKUPDEP_EVE4_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_EVE4_EVE1,Wakeup dependency from EVE4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_EVE1_0,WKUPDEP_EVE4_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_EVE4_DSP2,Wakeup dependency from EVE4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_DSP2_0,WKUPDEP_EVE4_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_EVE4_IPU1,Wakeup dependency from EVE4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_IPU1_0,WKUPDEP_EVE4_IPU1_1" newline bitfld.long 0x00 3. "WKUPDEP_EVE4_SDMA,Wakeup dependency from EVE4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_SDMA_0,WKUPDEP_EVE4_SDMA_1" bitfld.long 0x00 2. "WKUPDEP_EVE4_DSP1,Wakeup dependency from EVE4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_DSP1_0,WKUPDEP_EVE4_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_EVE4_IPU2,Wakeup dependency from EVE4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_IPU2_0,WKUPDEP_EVE4_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_EVE4_MPU,Wakeup dependency from EVE4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_MPU_0,WKUPDEP_EVE4_MPU_1" line.long 0x04 "RM_EVE4_EVE4_CONTEXT,This register contains dedicated EVE context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_EVE_BANK,Specify if memory-based context in EVE4 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EVE_BANK_0,LOSTMEM_EVE_BANK_1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "EVE_DSP" base ad:0x2000000 rgroup.long 0x80000++0x2F line.long 0x00 "EVE_REVISION," line.long 0x04 "EVE_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," newline bitfld.long 0x04 0.--3. "EVENUM,EVE instance number set by eve_num inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EVE_SYSCONFIG," hexmask.long 0x08 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x08 4.--5. "STANDBYMODE," "?,No-Standby,Smart-Standby,Smart-Standby-Wkup" newline bitfld.long 0x08 2.--3. "IDLEMODE," "?,No-idle,Smart-idle,SmartIdleWkup" newline rbitfld.long 0x08 1. "FREEEMU,Resered" "0,1" newline rbitfld.long 0x08 0. "SOFTRESET,Reserved" "0,1" line.long 0x0C "EVE_STAT," hexmask.long.word 0x0C 22.--31. 1. "RESERVED," newline bitfld.long 0x0C 20.--21. "OCPI_DISC_STAT,OCP Initiator(s) Disconnect status2" "OCPI_DISC_STAT_0,OCPI_DISC_STAT_1,OCPI_DISC_STAT_2,?" newline bitfld.long 0x0C 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 16.--17. "ARP32_DISC_STATUS,ARP32 Program/Data Bus Disconnect Status 2" "ARP32_DISC_STATUS_0,ARP32_DISC_STATUS_1,ARP32_DISC_STATUS_2,?" newline hexmask.long.byte 0x0C 9.--15. 1. "RESERVED," newline bitfld.long 0x0C 8. "INT_OUT_STAT,Interrupt Output status" "INT_OUT_STAT_0,INT_OUT_STAT_1" newline bitfld.long 0x0C 7. "ARP32_INTC_STAT,Interrupt Controller Status" "ARP32_INTC_STAT_0,ARP32_INTC_STAT_1" newline bitfld.long 0x0C 6. "RESERVED," "0,1" newline bitfld.long 0x0C 5. "TC1_STAT,Transfer Controller1 Status" "TC1_STAT_0,TC1_STAT_1" newline bitfld.long 0x0C 4. "TC0_STAT,Transfer Controller0 Status" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "PC_STAT,Program Cache Status" "PC_STAT_0,PC_STAT_1" newline bitfld.long 0x0C 1. "VCOP_STAT,VCOP Status" "VCOP_STAT_0,VCOP_STAT_1" newline bitfld.long 0x0C 0. "ARP32_STAT,Program Cache Status" "ARP32_STAT_0,ARP32_STAT_1" line.long 0x10 "EVE_DISC_CONFIG,Color 0 noise threshold" hexmask.long 0x10 5.--31. 1. "RESERVED," newline bitfld.long 0x10 4. "OCPI_DISC,OCP Initiator Disconnect request" "OCPI_DISC_0_r,OCPI_DISC_1_w" newline rbitfld.long 0x10 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0. "ARP32_DISC,ARP32 Initiator Disconnect request" "?,ARP32_DISC_1_r" line.long 0x14 "EVE_BUS_CONFIG,Color 0 noise threshold" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED," newline bitfld.long 0x14 12.--13. "TC1_DBS,TC1 default burst size" "16 byte,32 byte,64 byte,128 byte.." newline rbitfld.long 0x14 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 8.--9. "TC0_DBS,TC0 default burst size" "16 byte,32 byte,64 byte,128 byte.." newline rbitfld.long 0x14 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 4. "DBP_ENABLE,Program Cache Demand Based Prefetch enable" "DBP_ENABLE_0,DBP_ENABLE_1" newline bitfld.long 0x14 0.--3. "MAX_IN_FLIGHT,Defines maximum number of OCP requests in flight" "Reserved,1 request in flight allowed,2 requests in flight allowed,?..." line.long 0x18 "EVE_VCOP_HALT_CONFIG," hexmask.long 0x18 3.--31. 1. "RESERVED," newline bitfld.long 0x18 2. "FORCE_ABORT,VCOP Force Abort Write: Read always returns 0sWrite 0 has no effect" "?,FORCE_ABORT_1_w" newline bitfld.long 0x18 1. "MSW_EN,VCOP Memory Seitch Error Halt Enable" "MSW_EN_0,MSW_EN_1" newline bitfld.long 0x18 0. "ED_EN,VCOP Parity Error Detect Halt Enable" "ED_EN_0,ED_EN_1" line.long 0x1C "EVE_MMU_CONFIG," hexmask.long.tbyte 0x1C 13.--31. 1. "RESERVED," newline bitfld.long 0x1C 12. "MMU1_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" newline rbitfld.long 0x1C 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "MMU0_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" newline rbitfld.long 0x1C 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 4. "MMU1_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" newline rbitfld.long 0x1C 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "MMU0_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" line.long 0x20 "EVE_MEMMAP," hexmask.long 0x20 5.--31. 1. "RESERVED," newline bitfld.long 0x20 4. "LCL_EDMA_ALIAS," "?,LCL_EDMA_ALIAS_1" newline rbitfld.long 0x20 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0. "VCOP_ALIAS," "?,VCOP_ALIAS_1" line.long 0x24 "EVE_MSW_CTL,Memory switch control register" hexmask.long.word 0x24 17.--31. 1. "RESERVED," newline bitfld.long 0x24 16. "WBUF,Working buffer onwership" "WBUF_0,WBUF_1" newline rbitfld.long 0x24 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 12. "IBUFHB,Image buffer high B ownership" "IBUFHB_0,IBUFHB_1" newline rbitfld.long 0x24 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8. "IBUFLB,Image buffer low B ownership" "IBUFLB_0,IBUFLB_1" newline rbitfld.long 0x24 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 4. "IBUFHA,Image buffer high A ownership" "IBUFHA_0,IBUFHA_1" newline rbitfld.long 0x24 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "IBUFLA,Image buffer low A ownership" "IBUFLA_0,IBUFLA_1" line.long 0x28 "EVE_MSW_ERR,Memory Switch Error register" hexmask.long.byte 0x28 25.--31. 1. "RESERVED," newline hexmask.long.word 0x28 16.--24. 1. "CONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x28 4.--15. 1. "RESERVED," newline bitfld.long 0x28 3. "SYSERR," "0,1" newline bitfld.long 0x28 2. "DMAERR," "0,1" newline bitfld.long 0x28 1. "VERR," "0,1" newline bitfld.long 0x28 0. "ARP32ERR," "0,1" line.long 0x2C "EVE_MSW_ERRADDR,Memory switch error address register" group.long 0x80040++0x03 line.long 0x00 "EVE_PC_INV,Invalidate all register" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "I,Invalidate all:Read" "Invalidate operation complete / or not in progress,Invalidate operation still in progress" group.long 0x80050++0x17 line.long 0x00 "EVE_PC_IBAR,Invalidate Base Address register" line.long 0x04 "EVE_PC_IBC,Invalidate byte count register" hexmask.long.word 0x04 16.--31. 1. "RESERVED," newline hexmask.long.word 0x04 0.--15. 1. "BC,Invalidate Byte Count register" line.long 0x08 "EVE_PC_ISAR,Invalidate single address register" line.long 0x0C "EVE_PC_ISAR_DONE,Invalidate single address done register" hexmask.long 0x0C 1.--31. 1. "RESERVED," newline bitfld.long 0x0C 0. "DONE,Reads return 0x1 when the invalidate operation is complete" "0,1" line.long 0x10 "EVE_PC_PBAR,Program cache preload base address register" line.long 0x14 "EVE_PC_PBC," hexmask.long.word 0x14 16.--31. 1. "RESERVED," newline hexmask.long.word 0x14 0.--15. 1. "BC,Preload Byte Count register" group.long 0x80080++0x0B line.long 0x00 "EVE_PMEM_ED_CTL,Program Memory Error Detection Control register" hexmask.long 0x00 2.--31. 1. "RESERVED," newline bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_PMEM_ED_STAT,Error detection status register" hexmask.long.byte 0x04 25.--31. 1. "RESERVED," newline hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_PMEM_EDADDR,Program memory error detection address" group.long 0x80090++0x2F line.long 0x00 "EVE_DMEM_ED_CTL,DMEM error detection control" hexmask.long 0x00 2.--31. 1. "RESERVED," newline bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_DMEM_ED_STAT,DMEM error detection status register" hexmask.long.byte 0x04 25.--31. 1. "RESERVED," newline hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x04 4.--15. 1. "RESERVED," newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_DMEM_EDADDR,DMEM error detection address register" line.long 0x0C "EVE_DMEM_EDADDR_BO,DMEM error detection address byte offset register" line.long 0x10 "EVE_WBUF_ED_CTL,WBUF error detection control" hexmask.long 0x10 2.--31. 1. "RESERVED," newline bitfld.long 0x10 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x10 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x14 "EVE_WBUF_ED_STAT,WBUF error detection status register" hexmask.long.byte 0x14 25.--31. 1. "RESERVED," newline hexmask.long.word 0x14 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x14 4.--15. 1. "RESERVED," newline bitfld.long 0x14 3. "SYSERR," "0,1" newline bitfld.long 0x14 2. "DMAERR," "0,1" newline bitfld.long 0x14 1. "VERR," "0,1" newline bitfld.long 0x14 0. "ARP32ERR," "0,1" line.long 0x18 "EVE_WBUF_EDADDR,WBUF error detection address register" line.long 0x1C "EVE_WBUF_EDADDR_BO,WBUF error detection address byte offset register" line.long 0x20 "EVE_IBUF_ED_CTL,IBUF error detection control" hexmask.long 0x20 2.--31. 1. "RESERVED," newline bitfld.long 0x20 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x20 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x24 "EVE_IBUF_ED_STAT,IBUF error detection status register" hexmask.long.byte 0x24 25.--31. 1. "RESERVED," newline hexmask.long.word 0x24 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline hexmask.long.word 0x24 4.--15. 1. "RESERVED," newline bitfld.long 0x24 3. "SYSERR," "0,1" newline bitfld.long 0x24 2. "DMAERR," "0,1" newline bitfld.long 0x24 1. "VERR," "0,1" newline bitfld.long 0x24 0. "ARP32ERR," "0,1" line.long 0x28 "EVE_IBUF_EDADDR,IBUF error detection address register" line.long 0x2C "EVE_IBUF_EDADDR_BO,IBUF error detection address byte offset register" group.long 0x800F8++0x07 line.long 0x00 "EVE_ED_ARP32_DISC_EN,ARP32 disconnect enable register" hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline abitfld.long 0x00 0.--15. "ENABLE,Disconnect Enable for Event #n" "0x0000=Disconnect disabled,0x0001=Disconnect enabled" line.long 0x04 "EVE_ED_OCPI_DISC_EN,OCP interface disconnect enable register" hexmask.long.word 0x04 16.--31. 1. "RESERVED," newline abitfld.long 0x04 0.--15. "ENABLE,Disconnect Enable for Event #n" "0x0000=Disconnect disabled,0x0001=Disconnect enabled" group.long 0x80110++0x1F line.long 0x00 "EVE_MSW_ERR_IRQSTATUS_RAW,Per event memory switch error interrupt status register" hexmask.long 0x00 4.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "EVENT,settable raw status for event #n" "No event pending,Set event (for debug),?..." line.long 0x04 "EVE_MSW_ERR_IRQSTATUS,Memory switch error interrupt status register" hexmask.long 0x04 4.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--3. "EVENT,Clearable / enabled status for event #N" "No (enabled) event pending,Clear raw event,?..." line.long 0x08 "EVE_MSW_ERR_IRQENABLE_SET,Memory switch error interrupt enable register" hexmask.long 0x08 4.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--3. "ENABLE,Enable for event #n" "Interrupt disabled,Enable interrupt,?..." line.long 0x0C "EVE_MSW_ERR_IRQENABLE_CLR,Memory switch error interrupt clear register" hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--3. "ENABLE,Enable for event #n" "Interrupt disabled,Disable interrupt (i.e. / clear ENABLEn bit),?..." line.long 0x10 "EVE_ED_LCL_IRQSTATUS_RAW,Per event error detection local interrupt status register" hexmask.long.word 0x10 16.--31. 1. "RESERVED," newline abitfld.long 0x10 0.--15. "EVENT,settable raw status for event #n" "0x0000=No event pending,0x0001=Set event (for debug)" line.long 0x14 "EVE_ED_LCL_IRQSTATUS,Error detection local interrupt status register" hexmask.long.word 0x14 16.--31. 1. "RESERVED," newline abitfld.long 0x14 0.--15. "EVENT,Clearable / enabled status for event #N" "0x0000=No (enabled) event pending,0x0001=Clear raw event" line.long 0x18 "EVE_ED_LCL_IRQENABLE_SET,Error detection local interrupt enable register" hexmask.long.word 0x18 16.--31. 1. "RESERVED," newline abitfld.long 0x18 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Enable interrupt" line.long 0x1C "EVE_ED_LCL_IRQENABLE_CLR,Error detection local interrupt clear register" hexmask.long.word 0x1C 16.--31. 1. "RESERVED," newline abitfld.long 0x1C 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Disable interrupt (i.e. / clear ENABLEn.." group.long 0x80210++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_4," group.long 0x80220++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_5," group.long 0x80230++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_6," group.long 0x80240++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_7," group.long 0x80214++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_4," group.long 0x80224++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_5," group.long 0x80234++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_6," group.long 0x80244++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_7," group.long 0x80218++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_4," group.long 0x80228++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_5," group.long 0x80238++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_6," group.long 0x80248++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_7," group.long 0x8021C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_4," group.long 0x8022C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_5," group.long 0x8023C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_6," group.long 0x8024C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_7," group.long 0x80200++0x0F line.long 0x00 "ARP32_NMI_IRQSTATUS_RAW," line.long 0x04 "ARP32_NMI_IRQSTATUS," line.long 0x08 "ARP32_NMI_IRQENABLE_SET," line.long 0x0C "ARP32_NMI_IRQENABLE_CLR," group.long 0x802FC++0x2B line.long 0x00 "ARP32_IRQWAKEEN,Wake enable register" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," newline abitfld.long 0x00 0.--23. "ENABLE,Wakeup Enable for event EVE_EVT_INT #n" "0x000000=Interrupt #n disabled for wakeup,0x000001=Interrupt #n enabled for wakeup" line.long 0x04 "MMR_LOCKi_0,MMR Lock/Unlock register" line.long 0x08 "MMR_LOCKi_1,MMR Lock/Unlock register" line.long 0x0C "MMR_LOCKi_2,MMR Lock/Unlock register" line.long 0x10 "MMR_LOCKi_3,MMR Lock/Unlock register" line.long 0x14 "MMR_LOCKi_4,MMR Lock/Unlock register" line.long 0x18 "MMR_LOCKi_5,MMR Lock/Unlock register" line.long 0x1C "MMR_LOCKi_6,MMR Lock/Unlock register" line.long 0x20 "MMR_LOCKi_7,MMR Lock/Unlock register" line.long 0x24 "MMR_LOCKi_8,MMR Lock/Unlock register" line.long 0x28 "MMR_LOCKi_9,MMR Lock/Unlock register" group.long 0x80400++0x07 line.long 0x00 "MISR_CTL," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "ENABLE,MISR Enable #N" "ARP32 PMEM path Bit,ARP32 DMEM path Bit,INTC WBUF path,?..." line.long 0x04 "MISR_CLEAR," hexmask.long 0x04 3.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--2. "CLEAR,MISR Clear #N" "Previous MISR clear command has completed,MISR Clear in progress (this state may never..,?..." group.long 0x80410++0x1F line.long 0x00 "MISR0_A," line.long 0x04 "MISR0_D," line.long 0x08 "MISR1_A," line.long 0x0C "MISR1_D," line.long 0x10 "MISR2_Dk_0," line.long 0x14 "MISR2_Dk_1," line.long 0x18 "MISR2_Dk_2," line.long 0x1C "MISR2_Dk_3," group.long 0x80500++0x03 line.long 0x00 "EVE_IRQ_EOI," hexmask.long 0x00 3.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0,1,2,3,4,5,6,7" group.long 0x80510++0x13 line.long 0x00 "EVE_ED_OUT_IRQSTATUS_RAW," hexmask.long.word 0x00 16.--31. 1. "RESERVED," newline abitfld.long 0x00 0.--15. "EVENT,Settable raw status for event #n" "0x0000=No event pending,0x0001=Set event (for debug)" line.long 0x04 "EVE_ED_OUT_IRQSTATUS," hexmask.long.word 0x04 16.--31. 1. "RESERVED," newline abitfld.long 0x04 0.--15. "EVENT,Clearable / enabled status for event #N" "0x0000=No (enabled) event pending,0x0001=Clear raw event" line.long 0x08 "EVE_ED_OUT_IRQENABLE_SET," hexmask.long.word 0x08 16.--31. 1. "RESERVED," newline abitfld.long 0x08 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Enable interrupt" line.long 0x0C "EVE_ED_OUT_IRQENABLE_CLR," hexmask.long.word 0x0C 16.--31. 1. "RESERVED," newline abitfld.long 0x0C 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Disable interrupt (i.e. / clear ENABLEn.." line.long 0x10 "EVE_INTk_OUT_IRQSTATUS_RAW_0," group.long 0x80530++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_1," group.long 0x80540++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_2," group.long 0x80550++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_3," group.long 0x80524++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_0," group.long 0x80534++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_1," group.long 0x80544++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_2," group.long 0x80554++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_3," group.long 0x80528++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_0," group.long 0x80538++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_1," group.long 0x80548++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_2," group.long 0x80558++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_3," group.long 0x8052C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_0," group.long 0x8053C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_1," group.long 0x8054C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_2," group.long 0x8055C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_3," rgroup.long 0x80600++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_8," rgroup.long 0x80610++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_9," rgroup.long 0x80620++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_10," rgroup.long 0x80630++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_11," rgroup.long 0x80640++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_12," rgroup.long 0x80650++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_13," group.long 0x80604++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_8," group.long 0x80614++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_9," group.long 0x80624++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_10," group.long 0x80634++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_11," group.long 0x80644++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_12," group.long 0x80654++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_13," group.long 0x80608++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_8," group.long 0x80618++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_9," group.long 0x80628++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_10," group.long 0x80638++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_11," group.long 0x80648++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_12," group.long 0x80658++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_13," group.long 0x8060C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_8," group.long 0x8061C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_9," group.long 0x8062C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_10," group.long 0x8063C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_11," group.long 0x8064C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_12," group.long 0x8065C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_13," rgroup.long 0x80680++0x1F line.long 0x00 "ARP32_INT14_IRQSTATUS_RAW," line.long 0x04 "ARP32_INT14_IRQSTATUS," line.long 0x08 "ARP32_INT14_IRQENABLE_SET," line.long 0x0C "ARP32_INT14_IRQENABLE_CLR," line.long 0x10 "ARP32_INT15_IRQSTATUS_RAW," line.long 0x14 "ARP32_INT15_IRQSTATUS," line.long 0x18 "ARP32_INT15_IRQENABLE_SET," line.long 0x1C "ARP32_INT15_IRQENABLE_CLR," group.long 0x80700++0x03 line.long 0x00 "EVE_GPOUTm_0," group.long 0x80710++0x03 line.long 0x00 "EVE_GPOUTm_1," group.long 0x80704++0x03 line.long 0x00 "EVE_GPOUTm_SET_0," group.long 0x80714++0x03 line.long 0x00 "EVE_GPOUTm_SET_1," group.long 0x80708++0x03 line.long 0x00 "EVE_GPOUTm_CLR_0," group.long 0x80718++0x03 line.long 0x00 "EVE_GPOUTm_CLR_1," group.long 0x8070C++0x03 line.long 0x00 "EVE_GPOUTm_PULSE_0," group.long 0x8071C++0x03 line.long 0x00 "EVE_GPOUTm_PULSE_1," group.long 0x80780++0x17 line.long 0x00 "EVE_CME_DONE_GPOUT," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," newline abitfld.long 0x00 0.--7. "EVENT,Internal CME Done Output #n" "0x00=Drive Internal CME Done #n is low/0,0x01=Internal CME Done is high/1" line.long 0x04 "EVE_CME_DONE_GPOUT_SET," hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," newline abitfld.long 0x04 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done is high/1" line.long 0x08 "EVE_CME_DONE_GPOUT_CLR," hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED," newline abitfld.long 0x08 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done #n is high/1" line.long 0x0C "EVE_CME_DONE_GPOUT_PULSE," hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED," newline abitfld.long 0x0C 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done #n is high/1" line.long 0x10 "EVE_CME_DONE_SEL," bitfld.long 0x10 28.--31. "SEL7,CME Done Output select for Bit #7 (n=7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 24.--27. "SEL6,CME Done Output select for Bit #6 (n=6)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 20.--23. "SEL5,CME Done Output select for Bit #5 (n=5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 16.--19. "SEL4,CME Done Output select for Bit #4 (n=4)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 12.--15. "SEL3,CME Done Output select for Bit #3 (n=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 8.--11. "SEL2,CME Done Output select for Bit #2 (n=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 4.--7. "SEL1,CME Done Output select for Bit #1 (n=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--3. "SEL0,CME Done Output select for Bit #0 (n=0)" "Driven by EDMA cc_int0,Driven by EDMA cc_int1,Driven by EDMA cc_int2,Driven by EDMA cc_int3,Driven by EDMA cc_int4,Driven by EDMA cc_int5,Driven by EDMA cc_int6,Driven by EDMA cc_int7,Driven by EVE_CME_DONE_GPOUTn,driven by eve_cme_done_gpout[0+n] (from EVE),driven by eve_cme_done_gpout[8+n] (from EVE2),driven by eve_cme_done_gpout[16+n] (from EVE3),driven by eve_cme_done_gpout[24+n] (from EVE4),driven by eve_cme_done_gpout[32+n] (from EVE5),driven by eve_cme_done_gpout[40+n] (from EVE6),driven by eve_cme_done_gpout[48+n] (from EVE7)" line.long 0x14 "EVE_CME_DONE_EN," hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," newline abitfld.long 0x14 0.--7. "EN,EVE CME Done EN #n" "0x00=EVE CME Done #n is disabled,0x01=EVE CME Done #n is enabled" rgroup.long 0x80FE0++0x0B line.long 0x00 "EVE_PM_STAT0," bitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 28.--30. "OCPM1_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 26.--27. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 24.--25. "OCPM1_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 23. "RESERVED," "0,1" newline bitfld.long 0x00 20.--22. "OCPM0_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 16.--17. "OCPM0_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 12.--14. "OCPS_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 8.--9. "OCPS_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 5. "MWAIT,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 4. "MSTANDBY,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 3. "SWAKEUP,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 1.--2. "SIDLEACK,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 0. "SIDLEREQ,Readable state of OCP Power management handshake" "0,1" line.long 0x04 "EVE_PM_STAT1," hexmask.long.byte 0x04 24.--31. 1. "RESERVED," newline rbitfld.long 0x04 22.--23. "STBY_MDISCACK_OCPM1,Readable state of internal power management handshake" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "STBY_MDISCACK_OCPM0,Readable state of internal power management handshake" "0,1,2,3" newline rbitfld.long 0x04 19. "STBY_MDISCREQ_OCPM1,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 18. "STBY_MDISCREQ_OCPM0,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 17. "IDLE_SDISCONNECT_ACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 16. "IDLE_SDISCONNECT_REQ,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 15. "EVE_IDLE_INTR_DISABLE,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 14. "TPTC1_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 13. "TPTC0_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 12. "EVE_PCACHE_OCP_BUSY,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 11. "EVE_CONTROL_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 10. "SMSET_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 9. "L2_EVE_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 8. "MMU1_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 7. "MMU1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 6. "MMU0_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 5. "MMU0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 4. "SCTM_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 3. "TPCC_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 2. "TPTC1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 1. "TPTC0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline bitfld.long 0x04 0. "SUBMODULE_IDLE_REQ," "0,1" line.long 0x08 "EVE_DBGOUT," hexmask.long.tbyte 0x08 8.--31. 1. "VALUE,Read returns state of eve_dbgout bus" newline rbitfld.long 0x08 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. "GROUP,Debug Group Output control : mux select" "disabled / all debug outputs driven to 0x0,select output group1,select output group2,?..." group.long 0x80FFC++0x03 line.long 0x00 "EVE_TEST," repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x80FF4)++0x03 line.long 0x00 "EVE_RSVD$1," repeat.end repeat 2. (list 0. 1. )(list 0x00 0x04 ) rgroup.long ($2+0x80740)++0x03 line.long 0x00 "EVE_GPIN$1," repeat.end width 0x0B tree.end tree "EVE_EDMA_TPCC" base ad:0x420A0000 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x04 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x04 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" newline rbitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x04 22.--23. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x04 19. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x04 15. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x04 11. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7" group.long 0xFC++0x43 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" line.long 0x04 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x04 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x08 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x08 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x0C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x10 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x14 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x18 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x1C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" hexmask.long.tbyte 0x20 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x20 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" hexmask.long.tbyte 0x24 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x24 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" hexmask.long.tbyte 0x28 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x28 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x28 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x2C "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.tbyte 0x2C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x2C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x2C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" hexmask.long.tbyte 0x30 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x30 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x30 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" hexmask.long.tbyte 0x34 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x34 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x34 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x38 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" hexmask.long.tbyte 0x38 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x38 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x38 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x3C "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" hexmask.long.tbyte 0x3C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x3C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x3C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" hexmask.long.tbyte 0x40 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x40 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x40 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x200++0x1F line.long 0x00 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x04 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x04 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x08 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x08 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x08 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x0C "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0C 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x0C 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x10 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x10 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x10 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x14 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x14 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x14 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x18 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x18 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x18 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x1C "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x1C 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x1C 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x240++0x23 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x00 31. "RESERVED,Reserved" "0,1" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 27. "RESERVED,Reserved" "0,1" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 23. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Reserved" "0,1" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 15. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x04 31. "RESERVED,Reserved" "0,1" bitfld.long 0x04 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 27. "RESERVED,Reserved" "0,1" bitfld.long 0x04 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 23. "RESERVED,Reserved" "0,1" bitfld.long 0x04 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED,Reserved" "0,1" bitfld.long 0x04 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 15. "RESERVED,Reserved" "0,1" bitfld.long 0x04 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 11. "RESERVED,Reserved" "0,1" bitfld.long 0x04 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED,Reserved" "0,1" bitfld.long 0x04 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x08 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x08 31. "RESERVED,Reserved" "0,1" bitfld.long 0x08 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 27. "RESERVED,Reserved" "0,1" bitfld.long 0x08 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 23. "RESERVED,Reserved" "0,1" bitfld.long 0x08 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED,Reserved" "0,1" bitfld.long 0x08 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 15. "RESERVED,Reserved" "0,1" bitfld.long 0x08 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 11. "RESERVED,Reserved" "0,1" bitfld.long 0x08 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED,Reserved" "0,1" bitfld.long 0x08 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x0C "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x0C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x10 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x10 31. "RESERVED,Reserved" "0,1" bitfld.long 0x10 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED,Reserved" "0,1" bitfld.long 0x10 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED,Reserved" "0,1" bitfld.long 0x10 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "RESERVED,Reserved" "0,1" bitfld.long 0x10 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 15. "RESERVED,Reserved" "0,1" bitfld.long 0x10 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 11. "RESERVED,Reserved" "0,1" bitfld.long 0x10 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" bitfld.long 0x10 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 3. "RESERVED,Reserved" "0,1" bitfld.long 0x10 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x14 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x14 31. "RESERVED,Reserved" "0,1" bitfld.long 0x14 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED,Reserved" "0,1" bitfld.long 0x14 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED,Reserved" "0,1" bitfld.long 0x14 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED,Reserved" "0,1" bitfld.long 0x14 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED,Reserved" "0,1" bitfld.long 0x14 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" bitfld.long 0x14 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED,Reserved" "0,1" bitfld.long 0x14 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x18 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x18 31. "RESERVED,Reserved" "0,1" bitfld.long 0x18 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED,Reserved" "0,1" bitfld.long 0x18 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED,Reserved" "0,1" bitfld.long 0x18 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED,Reserved" "0,1" bitfld.long 0x18 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED,Reserved" "0,1" bitfld.long 0x18 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED,Reserved" "0,1" bitfld.long 0x18 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED,Reserved" "0,1" bitfld.long 0x18 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED,Reserved" "0,1" bitfld.long 0x18 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x1C "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x1C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x20 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" rbitfld.long 0x20 31. "RESERVED," "0,1" bitfld.long 0x20 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 27. "RESERVED," "0,1" bitfld.long 0x20 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 23. "RESERVED," "0,1" bitfld.long 0x20 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 19. "RESERVED," "0,1" bitfld.long 0x20 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 15. "RESERVED," "0,1" bitfld.long 0x20 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 11. "RESERVED," "0,1" bitfld.long 0x20 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 7. "RESERVED," "0,1" bitfld.long 0x20 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 3. "RESERVED," "0,1" bitfld.long 0x20 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x280++0x07 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_QUEPRI,Queue Priority" hexmask.long 0x04 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" rgroup.long 0x300++0x23 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" newline bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" newline bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" newline bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" newline bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" newline bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" newline bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" newline bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" newline bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" newline bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" newline bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" newline bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" newline bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" newline bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" newline bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" newline bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" newline bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" newline bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" newline bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" newline bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" newline bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" line.long 0x08 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1" newline bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1" bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1" newline bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1" newline bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1" bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1" newline bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1" newline bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1" bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1" newline bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1" newline bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1" bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1" newline bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1" newline bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1" bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1" newline bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1" line.long 0x0C "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1" bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1" bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1" bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1" bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1" bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1" line.long 0x10 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,Event Missed #7" "0,1" newline bitfld.long 0x10 6. "E6,Event Missed #6" "0,1" bitfld.long 0x10 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x10 4. "E4,Event Missed #4" "0,1" bitfld.long 0x10 3. "E3,Event Missed #3" "0,1" newline bitfld.long 0x10 2. "E2,Event Missed #2" "0,1" bitfld.long 0x10 1. "E1,Event Missed #1" "0,1" newline bitfld.long 0x10 0. "E0,Event Missed #0" "0,1" line.long 0x14 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1" newline bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1" newline bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1" bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1" newline bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1" line.long 0x18 "EDMA_TPCC_CCERR,CC Error Register" hexmask.long.word 0x18 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 16. "TCERR,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register" "TCERR_0,TCERR_1" newline hexmask.long.byte 0x18 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD7_0,QTHRXCD7_1" newline bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD6_0,QTHRXCD6_1" bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD5_0,QTHRXCD5_1" newline bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD4_0,QTHRXCD4_1" bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD3_0,QTHRXCD3_1" newline bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD1_0,QTHRXCD1_1" newline bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x1C "EDMA_TPCC_CCERRCLR,CC Error Clear Register" hexmask.long.word 0x1C 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR" "0,1" newline hexmask.long.byte 0x1C 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect" "0,1" bitfld.long 0x1C 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect" "0,1" bitfld.long 0x1C 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" newline bitfld.long 0x1C 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect" "0,1" bitfld.long 0x1C 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" newline bitfld.long 0x1C 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect" "0,1" line.long 0x20 "EDMA_TPCC_EEVAL,Error Eval Register" hexmask.long 0x20 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 1. "SET,Error Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x20 0. "EVAL,Error Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x380++0x1F line.long 0x00 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x04 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x04 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x04 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x04 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x04 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x04 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x04 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x04 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x08 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x08 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x08 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x08 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x08 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x08 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x08 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x08 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x0C "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x0C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x0C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x0C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x0C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x0C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x0C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x0C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x10 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x10 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x10 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x10 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x10 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x10 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x10 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x10 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x14 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x14 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x14 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x14 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x14 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x14 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x14 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x14 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x18 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x18 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x18 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x18 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x18 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x18 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x18 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x18 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x1C "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x1C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x1C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x1C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x1C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x1C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x1C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x1C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x600++0x07 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" line.long 0x04 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" hexmask.long.byte 0x04 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" rbitfld.long 0x00 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" rbitfld.long 0x04 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,reads return 0's" rbitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" newline rbitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" rbitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" newline rbitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" rbitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" newline bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2" rbitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" newline rbitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 14.--15. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" rbitfld.long 0x00 5.--7. "RESERVED,reads return 0's" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" rbitfld.long 0x00 3. "RESERVED,reads return 0's" "0,1" newline bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.." rbitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" newline rbitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" group.long 0x700++0x0B line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" hexmask.long.tbyte 0x00 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" line.long 0x08 "EDMA_TPCC_AETCMD,AET Command" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "CLR,AET Clear commandCPU writes 0x0 has no effect" "0,1" rgroup.long 0x800++0x2F line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" line.long 0x04 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" newline rbitfld.long 0x04 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" rbitfld.long 0x04 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" newline rbitfld.long 0x04 2. "URE,User Read Error" "URE_0,URE_1" rbitfld.long 0x04 1. "UWE,User Write Error" "UWE_0,UWE_1" newline rbitfld.long 0x04 0. "UXE,User Execute Error" "UXE_0,UXE_1" line.long 0x08 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" line.long 0x0C "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x0C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x0C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x0C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x0C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x0C 10. "AID0,Allowed ID 0" "AID0_0,AID0_1" bitfld.long 0x0C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x0C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x0C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x0C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x0C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x0C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x0C 0. "UX,User Execute permission" "UX_0,UX_1" line.long 0x10 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x10 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x10 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x10 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x10 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x10 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x10 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x10 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x10 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x10 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x10 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x10 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x10 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x10 0. "UX,User Execute permission" "UX_0,?" line.long 0x14 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x14 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x14 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x14 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x14 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x14 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x14 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x14 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x14 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x14 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x14 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x14 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x14 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x14 0. "UX,User Execute permission" "UX_0,?" line.long 0x18 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x18 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x18 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x18 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x18 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x18 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x18 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x18 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x18 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x18 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x18 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x18 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x18 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x18 0. "UX,User Execute permission" "UX_0,?" line.long 0x1C "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x1C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x1C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x1C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x1C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x1C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x1C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x1C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x1C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x1C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x1C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x1C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x1C 0. "UX,User Execute permission" "UX_0,?" line.long 0x20 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x20 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x20 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x20 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x20 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x20 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x20 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x20 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x20 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x20 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x20 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x20 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x20 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x20 0. "UX,User Execute permission" "UX_0,?" line.long 0x24 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x24 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x24 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x24 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x24 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x24 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x24 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x24 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x24 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x24 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x24 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x24 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x24 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x24 0. "UX,User Execute permission" "UX_0,?" line.long 0x28 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" hexmask.long.word 0x28 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x28 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x28 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x28 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x28 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x28 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x28 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x28 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x28 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x28 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x28 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x28 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x28 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x28 0. "UX,User Execute permission" "UX_0,?" line.long 0x2C "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" hexmask.long.word 0x2C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x2C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x2C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x2C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x2C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x2C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x2C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x2C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x2C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x2C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x2C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x2C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x2C 0. "UX,User Execute permission" "UX_0,?" rgroup.long 0x1000++0x47 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" newline bitfld.long 0x04 29. "E61,Event #61" "0,1" bitfld.long 0x04 28. "E60,Event #60" "0,1" newline bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" newline bitfld.long 0x04 23. "E55,Event #55" "0,1" bitfld.long 0x04 22. "E54,Event #54" "0,1" newline bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" newline bitfld.long 0x04 17. "E49,Event #49" "0,1" bitfld.long 0x04 16. "E48,Event #48" "0,1" newline bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" newline bitfld.long 0x04 11. "E43,Event #43" "0,1" bitfld.long 0x04 10. "E42,Event #42" "0,1" newline bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" newline bitfld.long 0x04 5. "E37,Event #37" "0,1" bitfld.long 0x04 4. "E36,Event #36" "0,1" newline bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" line.long 0x08 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event #31" "0,1" bitfld.long 0x08 30. "E30,Event #30" "0,1" newline bitfld.long 0x08 29. "E29,Event #29" "0,1" bitfld.long 0x08 28. "E28,Event #28" "0,1" newline bitfld.long 0x08 27. "E27,Event #27" "0,1" bitfld.long 0x08 26. "E26,Event #26" "0,1" newline bitfld.long 0x08 25. "E25,Event #25" "0,1" bitfld.long 0x08 24. "E24,Event #24" "0,1" newline bitfld.long 0x08 23. "E23,Event #23" "0,1" bitfld.long 0x08 22. "E22,Event #22" "0,1" newline bitfld.long 0x08 21. "E21,Event #21" "0,1" bitfld.long 0x08 20. "E20,Event #20" "0,1" newline bitfld.long 0x08 19. "E19,Event #19" "0,1" bitfld.long 0x08 18. "E18,Event #18" "0,1" newline bitfld.long 0x08 17. "E17,Event #17" "0,1" bitfld.long 0x08 16. "E16,Event #16" "0,1" newline bitfld.long 0x08 15. "E15,Event #15" "0,1" bitfld.long 0x08 14. "E14,Event #14" "0,1" newline bitfld.long 0x08 13. "E13,Event #13" "0,1" bitfld.long 0x08 12. "E12,Event #12" "0,1" newline bitfld.long 0x08 11. "E11,Event #11" "0,1" bitfld.long 0x08 10. "E10,Event #10" "0,1" newline bitfld.long 0x08 9. "E9,Event #9" "0,1" bitfld.long 0x08 8. "E8,Event #8" "0,1" newline bitfld.long 0x08 7. "E7,Event #7" "0,1" bitfld.long 0x08 6. "E6,Event #6" "0,1" newline bitfld.long 0x08 5. "E5,Event #5" "0,1" bitfld.long 0x08 4. "E4,Event #4" "0,1" newline bitfld.long 0x08 3. "E3,Event #3" "0,1" bitfld.long 0x08 2. "E2,Event #2" "0,1" newline bitfld.long 0x08 1. "E1,Event #1" "0,1" bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event #63" "0,1" bitfld.long 0x0C 30. "E62,Event #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event #61" "0,1" bitfld.long 0x0C 28. "E60,Event #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event #59" "0,1" bitfld.long 0x0C 26. "E58,Event #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event #57" "0,1" bitfld.long 0x0C 24. "E56,Event #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event #55" "0,1" bitfld.long 0x0C 22. "E54,Event #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event #53" "0,1" bitfld.long 0x0C 20. "E52,Event #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event #51" "0,1" bitfld.long 0x0C 18. "E50,Event #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event #49" "0,1" bitfld.long 0x0C 16. "E48,Event #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event #47" "0,1" bitfld.long 0x0C 14. "E46,Event #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event #45" "0,1" bitfld.long 0x0C 12. "E44,Event #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event #43" "0,1" bitfld.long 0x0C 10. "E42,Event #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event #41" "0,1" bitfld.long 0x0C 8. "E40,Event #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event #39" "0,1" bitfld.long 0x0C 6. "E38,Event #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event #37" "0,1" bitfld.long 0x0C 4. "E36,Event #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event #35" "0,1" bitfld.long 0x0C 2. "E34,Event #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event #33" "0,1" bitfld.long 0x0C 0. "E32,Event #32" "0,1" line.long 0x10 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x10 31. "E31,Event #31" "0,1" bitfld.long 0x10 30. "E30,Event #30" "0,1" newline bitfld.long 0x10 29. "E29,Event #29" "0,1" bitfld.long 0x10 28. "E28,Event #28" "0,1" newline bitfld.long 0x10 27. "E27,Event #27" "0,1" bitfld.long 0x10 26. "E26,Event #26" "0,1" newline bitfld.long 0x10 25. "E25,Event #25" "0,1" bitfld.long 0x10 24. "E24,Event #24" "0,1" newline bitfld.long 0x10 23. "E23,Event #23" "0,1" bitfld.long 0x10 22. "E22,Event #22" "0,1" newline bitfld.long 0x10 21. "E21,Event #21" "0,1" bitfld.long 0x10 20. "E20,Event #20" "0,1" newline bitfld.long 0x10 19. "E19,Event #19" "0,1" bitfld.long 0x10 18. "E18,Event #18" "0,1" newline bitfld.long 0x10 17. "E17,Event #17" "0,1" bitfld.long 0x10 16. "E16,Event #16" "0,1" newline bitfld.long 0x10 15. "E15,Event #15" "0,1" bitfld.long 0x10 14. "E14,Event #14" "0,1" newline bitfld.long 0x10 13. "E13,Event #13" "0,1" bitfld.long 0x10 12. "E12,Event #12" "0,1" newline bitfld.long 0x10 11. "E11,Event #11" "0,1" bitfld.long 0x10 10. "E10,Event #10" "0,1" newline bitfld.long 0x10 9. "E9,Event #9" "0,1" bitfld.long 0x10 8. "E8,Event #8" "0,1" newline bitfld.long 0x10 7. "E7,Event #7" "0,1" bitfld.long 0x10 6. "E6,Event #6" "0,1" newline bitfld.long 0x10 5. "E5,Event #5" "0,1" bitfld.long 0x10 4. "E4,Event #4" "0,1" newline bitfld.long 0x10 3. "E3,Event #3" "0,1" bitfld.long 0x10 2. "E2,Event #2" "0,1" newline bitfld.long 0x10 1. "E1,Event #1" "0,1" bitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x14 31. "E63,Event #63" "0,1" bitfld.long 0x14 30. "E62,Event #62" "0,1" newline bitfld.long 0x14 29. "E61,Event #61" "0,1" bitfld.long 0x14 28. "E60,Event #60" "0,1" newline bitfld.long 0x14 27. "E59,Event #59" "0,1" bitfld.long 0x14 26. "E58,Event #58" "0,1" newline bitfld.long 0x14 25. "E57,Event #57" "0,1" bitfld.long 0x14 24. "E56,Event #56" "0,1" newline bitfld.long 0x14 23. "E55,Event #55" "0,1" bitfld.long 0x14 22. "E54,Event #54" "0,1" newline bitfld.long 0x14 21. "E53,Event #53" "0,1" bitfld.long 0x14 20. "E52,Event #52" "0,1" newline bitfld.long 0x14 19. "E51,Event #51" "0,1" bitfld.long 0x14 18. "E50,Event #50" "0,1" newline bitfld.long 0x14 17. "E49,Event #49" "0,1" bitfld.long 0x14 16. "E48,Event #48" "0,1" newline bitfld.long 0x14 15. "E47,Event #47" "0,1" bitfld.long 0x14 14. "E46,Event #46" "0,1" newline bitfld.long 0x14 13. "E45,Event #45" "0,1" bitfld.long 0x14 12. "E44,Event #44" "0,1" newline bitfld.long 0x14 11. "E43,Event #43" "0,1" bitfld.long 0x14 10. "E42,Event #42" "0,1" newline bitfld.long 0x14 9. "E41,Event #41" "0,1" bitfld.long 0x14 8. "E40,Event #40" "0,1" newline bitfld.long 0x14 7. "E39,Event #39" "0,1" bitfld.long 0x14 6. "E38,Event #38" "0,1" newline bitfld.long 0x14 5. "E37,Event #37" "0,1" bitfld.long 0x14 4. "E36,Event #36" "0,1" newline bitfld.long 0x14 3. "E35,Event #35" "0,1" bitfld.long 0x14 2. "E34,Event #34" "0,1" newline bitfld.long 0x14 1. "E33,Event #33" "0,1" bitfld.long 0x14 0. "E32,Event #32" "0,1" line.long 0x18 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x18 31. "E31,Event #31" "0,1" bitfld.long 0x18 30. "E30,Event #30" "0,1" newline bitfld.long 0x18 29. "E29,Event #29" "0,1" bitfld.long 0x18 28. "E28,Event #28" "0,1" newline bitfld.long 0x18 27. "E27,Event #27" "0,1" bitfld.long 0x18 26. "E26,Event #26" "0,1" newline bitfld.long 0x18 25. "E25,Event #25" "0,1" bitfld.long 0x18 24. "E24,Event #24" "0,1" newline bitfld.long 0x18 23. "E23,Event #23" "0,1" bitfld.long 0x18 22. "E22,Event #22" "0,1" newline bitfld.long 0x18 21. "E21,Event #21" "0,1" bitfld.long 0x18 20. "E20,Event #20" "0,1" newline bitfld.long 0x18 19. "E19,Event #19" "0,1" bitfld.long 0x18 18. "E18,Event #18" "0,1" newline bitfld.long 0x18 17. "E17,Event #17" "0,1" bitfld.long 0x18 16. "E16,Event #16" "0,1" newline bitfld.long 0x18 15. "E15,Event #15" "0,1" bitfld.long 0x18 14. "E14,Event #14" "0,1" newline bitfld.long 0x18 13. "E13,Event #13" "0,1" bitfld.long 0x18 12. "E12,Event #12" "0,1" newline bitfld.long 0x18 11. "E11,Event #11" "0,1" bitfld.long 0x18 10. "E10,Event #10" "0,1" newline bitfld.long 0x18 9. "E9,Event #9" "0,1" bitfld.long 0x18 8. "E8,Event #8" "0,1" newline bitfld.long 0x18 7. "E7,Event #7" "0,1" bitfld.long 0x18 6. "E6,Event #6" "0,1" newline bitfld.long 0x18 5. "E5,Event #5" "0,1" bitfld.long 0x18 4. "E4,Event #4" "0,1" newline bitfld.long 0x18 3. "E3,Event #3" "0,1" bitfld.long 0x18 2. "E2,Event #2" "0,1" newline bitfld.long 0x18 1. "E1,Event #1" "0,1" bitfld.long 0x18 0. "E0,Event #0" "0,1" line.long 0x1C "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x1C 31. "E63,Event #63" "0,1" bitfld.long 0x1C 30. "E62,Event #62" "0,1" newline bitfld.long 0x1C 29. "E61,Event #61" "0,1" bitfld.long 0x1C 28. "E60,Event #60" "0,1" newline bitfld.long 0x1C 27. "E59,Event #59" "0,1" bitfld.long 0x1C 26. "E58,Event #58" "0,1" newline bitfld.long 0x1C 25. "E57,Event #57" "0,1" bitfld.long 0x1C 24. "E56,Event #56" "0,1" newline bitfld.long 0x1C 23. "E55,Event #55" "0,1" bitfld.long 0x1C 22. "E54,Event #54" "0,1" newline bitfld.long 0x1C 21. "E53,Event #53" "0,1" bitfld.long 0x1C 20. "E52,Event #52" "0,1" newline bitfld.long 0x1C 19. "E51,Event #51" "0,1" bitfld.long 0x1C 18. "E50,Event #50" "0,1" newline bitfld.long 0x1C 17. "E49,Event #49" "0,1" bitfld.long 0x1C 16. "E48,Event #48" "0,1" newline bitfld.long 0x1C 15. "E47,Event #47" "0,1" bitfld.long 0x1C 14. "E46,Event #46" "0,1" newline bitfld.long 0x1C 13. "E45,Event #45" "0,1" bitfld.long 0x1C 12. "E44,Event #44" "0,1" newline bitfld.long 0x1C 11. "E43,Event #43" "0,1" bitfld.long 0x1C 10. "E42,Event #42" "0,1" newline bitfld.long 0x1C 9. "E41,Event #41" "0,1" bitfld.long 0x1C 8. "E40,Event #40" "0,1" newline bitfld.long 0x1C 7. "E39,Event #39" "0,1" bitfld.long 0x1C 6. "E38,Event #38" "0,1" newline bitfld.long 0x1C 5. "E37,Event #37" "0,1" bitfld.long 0x1C 4. "E36,Event #36" "0,1" newline bitfld.long 0x1C 3. "E35,Event #35" "0,1" bitfld.long 0x1C 2. "E34,Event #34" "0,1" newline bitfld.long 0x1C 1. "E33,Event #33" "0,1" bitfld.long 0x1C 0. "E32,Event #32" "0,1" line.long 0x20 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x20 31. "E31,Event #31" "0,1" bitfld.long 0x20 30. "E30,Event #30" "0,1" newline bitfld.long 0x20 29. "E29,Event #29" "0,1" bitfld.long 0x20 28. "E28,Event #28" "0,1" newline bitfld.long 0x20 27. "E27,Event #27" "0,1" bitfld.long 0x20 26. "E26,Event #26" "0,1" newline bitfld.long 0x20 25. "E25,Event #25" "0,1" bitfld.long 0x20 24. "E24,Event #24" "0,1" newline bitfld.long 0x20 23. "E23,Event #23" "0,1" bitfld.long 0x20 22. "E22,Event #22" "0,1" newline bitfld.long 0x20 21. "E21,Event #21" "0,1" bitfld.long 0x20 20. "E20,Event #20" "0,1" newline bitfld.long 0x20 19. "E19,Event #19" "0,1" bitfld.long 0x20 18. "E18,Event #18" "0,1" newline bitfld.long 0x20 17. "E17,Event #17" "0,1" bitfld.long 0x20 16. "E16,Event #16" "0,1" newline bitfld.long 0x20 15. "E15,Event #15" "0,1" bitfld.long 0x20 14. "E14,Event #14" "0,1" newline bitfld.long 0x20 13. "E13,Event #13" "0,1" bitfld.long 0x20 12. "E12,Event #12" "0,1" newline bitfld.long 0x20 11. "E11,Event #11" "0,1" bitfld.long 0x20 10. "E10,Event #10" "0,1" newline bitfld.long 0x20 9. "E9,Event #9" "0,1" bitfld.long 0x20 8. "E8,Event #8" "0,1" newline bitfld.long 0x20 7. "E7,Event #7" "0,1" bitfld.long 0x20 6. "E6,Event #6" "0,1" newline bitfld.long 0x20 5. "E5,Event #5" "0,1" bitfld.long 0x20 4. "E4,Event #4" "0,1" newline bitfld.long 0x20 3. "E3,Event #3" "0,1" bitfld.long 0x20 2. "E2,Event #2" "0,1" newline bitfld.long 0x20 1. "E1,Event #1" "0,1" bitfld.long 0x20 0. "E0,Event #0" "0,1" line.long 0x24 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x24 31. "E63,Event #63" "0,1" bitfld.long 0x24 30. "E62,Event #62" "0,1" newline bitfld.long 0x24 29. "E61,Event #61" "0,1" bitfld.long 0x24 28. "E60,Event #60" "0,1" newline bitfld.long 0x24 27. "E59,Event #59" "0,1" bitfld.long 0x24 26. "E58,Event #58" "0,1" newline bitfld.long 0x24 25. "E57,Event #57" "0,1" bitfld.long 0x24 24. "E56,Event #56" "0,1" newline bitfld.long 0x24 23. "E55,Event #55" "0,1" bitfld.long 0x24 22. "E54,Event #54" "0,1" newline bitfld.long 0x24 21. "E53,Event #53" "0,1" bitfld.long 0x24 20. "E52,Event #52" "0,1" newline bitfld.long 0x24 19. "E51,Event #51" "0,1" bitfld.long 0x24 18. "E50,Event #50" "0,1" newline bitfld.long 0x24 17. "E49,Event #49" "0,1" bitfld.long 0x24 16. "E48,Event #48" "0,1" newline bitfld.long 0x24 15. "E47,Event #47" "0,1" bitfld.long 0x24 14. "E46,Event #46" "0,1" newline bitfld.long 0x24 13. "E45,Event #45" "0,1" bitfld.long 0x24 12. "E44,Event #44" "0,1" newline bitfld.long 0x24 11. "E43,Event #43" "0,1" bitfld.long 0x24 10. "E42,Event #42" "0,1" newline bitfld.long 0x24 9. "E41,Event #41" "0,1" bitfld.long 0x24 8. "E40,Event #40" "0,1" newline bitfld.long 0x24 7. "E39,Event #39" "0,1" bitfld.long 0x24 6. "E38,Event #38" "0,1" newline bitfld.long 0x24 5. "E37,Event #37" "0,1" bitfld.long 0x24 4. "E36,Event #36" "0,1" newline bitfld.long 0x24 3. "E35,Event #35" "0,1" bitfld.long 0x24 2. "E34,Event #34" "0,1" newline bitfld.long 0x24 1. "E33,Event #33" "0,1" bitfld.long 0x24 0. "E32,Event #32" "0,1" line.long 0x28 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x28 31. "E31,Event #31" "0,1" bitfld.long 0x28 30. "E30,Event #30" "0,1" newline bitfld.long 0x28 29. "E29,Event #29" "0,1" bitfld.long 0x28 28. "E28,Event #28" "0,1" newline bitfld.long 0x28 27. "E27,Event #27" "0,1" bitfld.long 0x28 26. "E26,Event #26" "0,1" newline bitfld.long 0x28 25. "E25,Event #25" "0,1" bitfld.long 0x28 24. "E24,Event #24" "0,1" newline bitfld.long 0x28 23. "E23,Event #23" "0,1" bitfld.long 0x28 22. "E22,Event #22" "0,1" newline bitfld.long 0x28 21. "E21,Event #21" "0,1" bitfld.long 0x28 20. "E20,Event #20" "0,1" newline bitfld.long 0x28 19. "E19,Event #19" "0,1" bitfld.long 0x28 18. "E18,Event #18" "0,1" newline bitfld.long 0x28 17. "E17,Event #17" "0,1" bitfld.long 0x28 16. "E16,Event #16" "0,1" newline bitfld.long 0x28 15. "E15,Event #15" "0,1" bitfld.long 0x28 14. "E14,Event #14" "0,1" newline bitfld.long 0x28 13. "E13,Event #13" "0,1" bitfld.long 0x28 12. "E12,Event #12" "0,1" newline bitfld.long 0x28 11. "E11,Event #11" "0,1" bitfld.long 0x28 10. "E10,Event #10" "0,1" newline bitfld.long 0x28 9. "E9,Event #9" "0,1" bitfld.long 0x28 8. "E8,Event #8" "0,1" newline bitfld.long 0x28 7. "E7,Event #7" "0,1" bitfld.long 0x28 6. "E6,Event #6" "0,1" newline bitfld.long 0x28 5. "E5,Event #5" "0,1" bitfld.long 0x28 4. "E4,Event #4" "0,1" newline bitfld.long 0x28 3. "E3,Event #3" "0,1" bitfld.long 0x28 2. "E2,Event #2" "0,1" newline bitfld.long 0x28 1. "E1,Event #1" "0,1" bitfld.long 0x28 0. "E0,Event #0" "0,1" line.long 0x2C "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x2C 31. "E63,Event #63" "0,1" bitfld.long 0x2C 30. "E62,Event #62" "0,1" newline bitfld.long 0x2C 29. "E61,Event #61" "0,1" bitfld.long 0x2C 28. "E60,Event #60" "0,1" newline bitfld.long 0x2C 27. "E59,Event #59" "0,1" bitfld.long 0x2C 26. "E58,Event #58" "0,1" newline bitfld.long 0x2C 25. "E57,Event #57" "0,1" bitfld.long 0x2C 24. "E56,Event #56" "0,1" newline bitfld.long 0x2C 23. "E55,Event #55" "0,1" bitfld.long 0x2C 22. "E54,Event #54" "0,1" newline bitfld.long 0x2C 21. "E53,Event #53" "0,1" bitfld.long 0x2C 20. "E52,Event #52" "0,1" newline bitfld.long 0x2C 19. "E51,Event #51" "0,1" bitfld.long 0x2C 18. "E50,Event #50" "0,1" newline bitfld.long 0x2C 17. "E49,Event #49" "0,1" bitfld.long 0x2C 16. "E48,Event #48" "0,1" newline bitfld.long 0x2C 15. "E47,Event #47" "0,1" bitfld.long 0x2C 14. "E46,Event #46" "0,1" newline bitfld.long 0x2C 13. "E45,Event #45" "0,1" bitfld.long 0x2C 12. "E44,Event #44" "0,1" newline bitfld.long 0x2C 11. "E43,Event #43" "0,1" bitfld.long 0x2C 10. "E42,Event #42" "0,1" newline bitfld.long 0x2C 9. "E41,Event #41" "0,1" bitfld.long 0x2C 8. "E40,Event #40" "0,1" newline bitfld.long 0x2C 7. "E39,Event #39" "0,1" bitfld.long 0x2C 6. "E38,Event #38" "0,1" newline bitfld.long 0x2C 5. "E37,Event #37" "0,1" bitfld.long 0x2C 4. "E36,Event #36" "0,1" newline bitfld.long 0x2C 3. "E35,Event #35" "0,1" bitfld.long 0x2C 2. "E34,Event #34" "0,1" newline bitfld.long 0x2C 1. "E33,Event #33" "0,1" bitfld.long 0x2C 0. "E32,Event #32" "0,1" line.long 0x30 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x30 31. "E31,Event #31" "0,1" bitfld.long 0x30 30. "E30,Event #30" "0,1" newline bitfld.long 0x30 29. "E29,Event #29" "0,1" bitfld.long 0x30 28. "E28,Event #28" "0,1" newline bitfld.long 0x30 27. "E27,Event #27" "0,1" bitfld.long 0x30 26. "E26,Event #26" "0,1" newline bitfld.long 0x30 25. "E25,Event #25" "0,1" bitfld.long 0x30 24. "E24,Event #24" "0,1" newline bitfld.long 0x30 23. "E23,Event #23" "0,1" bitfld.long 0x30 22. "E22,Event #22" "0,1" newline bitfld.long 0x30 21. "E21,Event #21" "0,1" bitfld.long 0x30 20. "E20,Event #20" "0,1" newline bitfld.long 0x30 19. "E19,Event #19" "0,1" bitfld.long 0x30 18. "E18,Event #18" "0,1" newline bitfld.long 0x30 17. "E17,Event #17" "0,1" bitfld.long 0x30 16. "E16,Event #16" "0,1" newline bitfld.long 0x30 15. "E15,Event #15" "0,1" bitfld.long 0x30 14. "E14,Event #14" "0,1" newline bitfld.long 0x30 13. "E13,Event #13" "0,1" bitfld.long 0x30 12. "E12,Event #12" "0,1" newline bitfld.long 0x30 11. "E11,Event #11" "0,1" bitfld.long 0x30 10. "E10,Event #10" "0,1" newline bitfld.long 0x30 9. "E9,Event #9" "0,1" bitfld.long 0x30 8. "E8,Event #8" "0,1" newline bitfld.long 0x30 7. "E7,Event #7" "0,1" bitfld.long 0x30 6. "E6,Event #6" "0,1" newline bitfld.long 0x30 5. "E5,Event #5" "0,1" bitfld.long 0x30 4. "E4,Event #4" "0,1" newline bitfld.long 0x30 3. "E3,Event #3" "0,1" bitfld.long 0x30 2. "E2,Event #2" "0,1" newline bitfld.long 0x30 1. "E1,Event #1" "0,1" bitfld.long 0x30 0. "E0,Event #0" "0,1" line.long 0x34 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x34 31. "E63,Event #63" "0,1" bitfld.long 0x34 30. "E62,Event #62" "0,1" newline bitfld.long 0x34 29. "E61,Event #61" "0,1" bitfld.long 0x34 28. "E60,Event #60" "0,1" newline bitfld.long 0x34 27. "E59,Event #59" "0,1" bitfld.long 0x34 26. "E58,Event #58" "0,1" newline bitfld.long 0x34 25. "E57,Event #57" "0,1" bitfld.long 0x34 24. "E56,Event #56" "0,1" newline bitfld.long 0x34 23. "E55,Event #55" "0,1" bitfld.long 0x34 22. "E54,Event #54" "0,1" newline bitfld.long 0x34 21. "E53,Event #53" "0,1" bitfld.long 0x34 20. "E52,Event #52" "0,1" newline bitfld.long 0x34 19. "E51,Event #51" "0,1" bitfld.long 0x34 18. "E50,Event #50" "0,1" newline bitfld.long 0x34 17. "E49,Event #49" "0,1" bitfld.long 0x34 16. "E48,Event #48" "0,1" newline bitfld.long 0x34 15. "E47,Event #47" "0,1" bitfld.long 0x34 14. "E46,Event #46" "0,1" newline bitfld.long 0x34 13. "E45,Event #45" "0,1" bitfld.long 0x34 12. "E44,Event #44" "0,1" newline bitfld.long 0x34 11. "E43,Event #43" "0,1" bitfld.long 0x34 10. "E42,Event #42" "0,1" newline bitfld.long 0x34 9. "E41,Event #41" "0,1" bitfld.long 0x34 8. "E40,Event #40" "0,1" newline bitfld.long 0x34 7. "E39,Event #39" "0,1" bitfld.long 0x34 6. "E38,Event #38" "0,1" newline bitfld.long 0x34 5. "E37,Event #37" "0,1" bitfld.long 0x34 4. "E36,Event #36" "0,1" newline bitfld.long 0x34 3. "E35,Event #35" "0,1" bitfld.long 0x34 2. "E34,Event #34" "0,1" newline bitfld.long 0x34 1. "E33,Event #33" "0,1" bitfld.long 0x34 0. "E32,Event #32" "0,1" line.long 0x38 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x38 31. "E31,Event #31" "0,1" bitfld.long 0x38 30. "E30,Event #30" "0,1" newline bitfld.long 0x38 29. "E29,Event #29" "0,1" bitfld.long 0x38 28. "E28,Event #28" "0,1" newline bitfld.long 0x38 27. "E27,Event #27" "0,1" bitfld.long 0x38 26. "E26,Event #26" "0,1" newline bitfld.long 0x38 25. "E25,Event #25" "0,1" bitfld.long 0x38 24. "E24,Event #24" "0,1" newline bitfld.long 0x38 23. "E23,Event #23" "0,1" bitfld.long 0x38 22. "E22,Event #22" "0,1" newline bitfld.long 0x38 21. "E21,Event #21" "0,1" bitfld.long 0x38 20. "E20,Event #20" "0,1" newline bitfld.long 0x38 19. "E19,Event #19" "0,1" bitfld.long 0x38 18. "E18,Event #18" "0,1" newline bitfld.long 0x38 17. "E17,Event #17" "0,1" bitfld.long 0x38 16. "E16,Event #16" "0,1" newline bitfld.long 0x38 15. "E15,Event #15" "0,1" bitfld.long 0x38 14. "E14,Event #14" "0,1" newline bitfld.long 0x38 13. "E13,Event #13" "0,1" bitfld.long 0x38 12. "E12,Event #12" "0,1" newline bitfld.long 0x38 11. "E11,Event #11" "0,1" bitfld.long 0x38 10. "E10,Event #10" "0,1" newline bitfld.long 0x38 9. "E9,Event #9" "0,1" bitfld.long 0x38 8. "E8,Event #8" "0,1" newline bitfld.long 0x38 7. "E7,Event #7" "0,1" bitfld.long 0x38 6. "E6,Event #6" "0,1" newline bitfld.long 0x38 5. "E5,Event #5" "0,1" bitfld.long 0x38 4. "E4,Event #4" "0,1" newline bitfld.long 0x38 3. "E3,Event #3" "0,1" bitfld.long 0x38 2. "E2,Event #2" "0,1" newline bitfld.long 0x38 1. "E1,Event #1" "0,1" bitfld.long 0x38 0. "E0,Event #0" "0,1" line.long 0x3C "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x3C 31. "E63,Event #63" "0,1" bitfld.long 0x3C 30. "E62,Event #62" "0,1" newline bitfld.long 0x3C 29. "E61,Event #61" "0,1" bitfld.long 0x3C 28. "E60,Event #60" "0,1" newline bitfld.long 0x3C 27. "E59,Event #59" "0,1" bitfld.long 0x3C 26. "E58,Event #58" "0,1" newline bitfld.long 0x3C 25. "E57,Event #57" "0,1" bitfld.long 0x3C 24. "E56,Event #56" "0,1" newline bitfld.long 0x3C 23. "E55,Event #55" "0,1" bitfld.long 0x3C 22. "E54,Event #54" "0,1" newline bitfld.long 0x3C 21. "E53,Event #53" "0,1" bitfld.long 0x3C 20. "E52,Event #52" "0,1" newline bitfld.long 0x3C 19. "E51,Event #51" "0,1" bitfld.long 0x3C 18. "E50,Event #50" "0,1" newline bitfld.long 0x3C 17. "E49,Event #49" "0,1" bitfld.long 0x3C 16. "E48,Event #48" "0,1" newline bitfld.long 0x3C 15. "E47,Event #47" "0,1" bitfld.long 0x3C 14. "E46,Event #46" "0,1" newline bitfld.long 0x3C 13. "E45,Event #45" "0,1" bitfld.long 0x3C 12. "E44,Event #44" "0,1" newline bitfld.long 0x3C 11. "E43,Event #43" "0,1" bitfld.long 0x3C 10. "E42,Event #42" "0,1" newline bitfld.long 0x3C 9. "E41,Event #41" "0,1" bitfld.long 0x3C 8. "E40,Event #40" "0,1" newline bitfld.long 0x3C 7. "E39,Event #39" "0,1" bitfld.long 0x3C 6. "E38,Event #38" "0,1" newline bitfld.long 0x3C 5. "E37,Event #37" "0,1" bitfld.long 0x3C 4. "E36,Event #36" "0,1" newline bitfld.long 0x3C 3. "E35,Event #35" "0,1" bitfld.long 0x3C 2. "E34,Event #34" "0,1" newline bitfld.long 0x3C 1. "E33,Event #33" "0,1" bitfld.long 0x3C 0. "E32,Event #32" "0,1" line.long 0x40 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x40 31. "E31,Event #31" "0,1" bitfld.long 0x40 30. "E30,Event #30" "0,1" newline bitfld.long 0x40 29. "E29,Event #29" "0,1" bitfld.long 0x40 28. "E28,Event #28" "0,1" newline bitfld.long 0x40 27. "E27,Event #27" "0,1" bitfld.long 0x40 26. "E26,Event #26" "0,1" newline bitfld.long 0x40 25. "E25,Event #25" "0,1" bitfld.long 0x40 24. "E24,Event #24" "0,1" newline bitfld.long 0x40 23. "E23,Event #23" "0,1" bitfld.long 0x40 22. "E22,Event #22" "0,1" newline bitfld.long 0x40 21. "E21,Event #21" "0,1" bitfld.long 0x40 20. "E20,Event #20" "0,1" newline bitfld.long 0x40 19. "E19,Event #19" "0,1" bitfld.long 0x40 18. "E18,Event #18" "0,1" newline bitfld.long 0x40 17. "E17,Event #17" "0,1" bitfld.long 0x40 16. "E16,Event #16" "0,1" newline bitfld.long 0x40 15. "E15,Event #15" "0,1" bitfld.long 0x40 14. "E14,Event #14" "0,1" newline bitfld.long 0x40 13. "E13,Event #13" "0,1" bitfld.long 0x40 12. "E12,Event #12" "0,1" newline bitfld.long 0x40 11. "E11,Event #11" "0,1" bitfld.long 0x40 10. "E10,Event #10" "0,1" newline bitfld.long 0x40 9. "E9,Event #9" "0,1" bitfld.long 0x40 8. "E8,Event #8" "0,1" newline bitfld.long 0x40 7. "E7,Event #7" "0,1" bitfld.long 0x40 6. "E6,Event #6" "0,1" newline bitfld.long 0x40 5. "E5,Event #5" "0,1" bitfld.long 0x40 4. "E4,Event #4" "0,1" newline bitfld.long 0x40 3. "E3,Event #3" "0,1" bitfld.long 0x40 2. "E2,Event #2" "0,1" newline bitfld.long 0x40 1. "E1,Event #1" "0,1" bitfld.long 0x40 0. "E0,Event #0" "0,1" line.long 0x44 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x44 31. "E63,Event #63" "0,1" bitfld.long 0x44 30. "E62,Event #62" "0,1" newline bitfld.long 0x44 29. "E61,Event #61" "0,1" bitfld.long 0x44 28. "E60,Event #60" "0,1" newline bitfld.long 0x44 27. "E59,Event #59" "0,1" bitfld.long 0x44 26. "E58,Event #58" "0,1" newline bitfld.long 0x44 25. "E57,Event #57" "0,1" bitfld.long 0x44 24. "E56,Event #56" "0,1" newline bitfld.long 0x44 23. "E55,Event #55" "0,1" bitfld.long 0x44 22. "E54,Event #54" "0,1" newline bitfld.long 0x44 21. "E53,Event #53" "0,1" bitfld.long 0x44 20. "E52,Event #52" "0,1" newline bitfld.long 0x44 19. "E51,Event #51" "0,1" bitfld.long 0x44 18. "E50,Event #50" "0,1" newline bitfld.long 0x44 17. "E49,Event #49" "0,1" bitfld.long 0x44 16. "E48,Event #48" "0,1" newline bitfld.long 0x44 15. "E47,Event #47" "0,1" bitfld.long 0x44 14. "E46,Event #46" "0,1" newline bitfld.long 0x44 13. "E45,Event #45" "0,1" bitfld.long 0x44 12. "E44,Event #44" "0,1" newline bitfld.long 0x44 11. "E43,Event #43" "0,1" bitfld.long 0x44 10. "E42,Event #42" "0,1" newline bitfld.long 0x44 9. "E41,Event #41" "0,1" bitfld.long 0x44 8. "E40,Event #40" "0,1" newline bitfld.long 0x44 7. "E39,Event #39" "0,1" bitfld.long 0x44 6. "E38,Event #38" "0,1" newline bitfld.long 0x44 5. "E37,Event #37" "0,1" bitfld.long 0x44 4. "E36,Event #36" "0,1" newline bitfld.long 0x44 3. "E35,Event #35" "0,1" bitfld.long 0x44 2. "E34,Event #34" "0,1" newline bitfld.long 0x44 1. "E33,Event #33" "0,1" bitfld.long 0x44 0. "E32,Event #32" "0,1" rgroup.long 0x1050++0x2B line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x08 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x0C "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x10 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x14 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x18 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x1C "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x20 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x24 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x28 "EDMA_TPCC_IEVAL,Interrupt Eval Register" hexmask.long 0x28 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" newline bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1080++0x17 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 7. "E7,Event #7" "0,1" newline rbitfld.long 0x04 6. "E6,Event #6" "0,1" rbitfld.long 0x04 5. "E5,Event #5" "0,1" newline rbitfld.long 0x04 4. "E4,Event #4" "0,1" rbitfld.long 0x04 3. "E3,Event #3" "0,1" newline rbitfld.long 0x04 2. "E2,Event #2" "0,1" rbitfld.long 0x04 1. "E1,Event #1" "0,1" newline rbitfld.long 0x04 0. "E0,Event #0" "0,1" line.long 0x08 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,Event #7" "0,1" newline bitfld.long 0x08 6. "E6,Event #6" "0,1" bitfld.long 0x08 5. "E5,Event #5" "0,1" newline bitfld.long 0x08 4. "E4,Event #4" "0,1" bitfld.long 0x08 3. "E3,Event #3" "0,1" newline bitfld.long 0x08 2. "E2,Event #2" "0,1" bitfld.long 0x08 1. "E1,Event #1" "0,1" newline bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,Event #7" "0,1" newline bitfld.long 0x0C 6. "E6,Event #6" "0,1" bitfld.long 0x0C 5. "E5,Event #5" "0,1" newline bitfld.long 0x0C 4. "E4,Event #4" "0,1" bitfld.long 0x0C 3. "E3,Event #3" "0,1" newline bitfld.long 0x0C 2. "E2,Event #2" "0,1" bitfld.long 0x0C 1. "E1,Event #1" "0,1" newline bitfld.long 0x0C 0. "E0,Event #0" "0,1" line.long 0x10 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 7. "E7,Event #7" "0,1" newline rbitfld.long 0x10 6. "E6,Event #6" "0,1" rbitfld.long 0x10 5. "E5,Event #5" "0,1" newline rbitfld.long 0x10 4. "E4,Event #4" "0,1" rbitfld.long 0x10 3. "E3,Event #3" "0,1" newline rbitfld.long 0x10 2. "E2,Event #2" "0,1" rbitfld.long 0x10 1. "E1,Event #1" "0,1" newline rbitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event #7" "0,1" newline bitfld.long 0x14 6. "E6,Event #6" "0,1" bitfld.long 0x14 5. "E5,Event #5" "0,1" newline bitfld.long 0x14 4. "E4,Event #4" "0,1" bitfld.long 0x14 3. "E3,Event #3" "0,1" newline bitfld.long 0x14 2. "E2,Event #2" "0,1" bitfld.long 0x14 1. "E1,Event #1" "0,1" newline bitfld.long 0x14 0. "E0,Event #0" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2200++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2600++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2204++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2604++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2208++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2608++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x220C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x260C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2210++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2610++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2214++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2614++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2218++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2618++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x221C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x261C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2220++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2620++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2224++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2624++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2228++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2628++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x222C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x262C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2230++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2630++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2234++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2634++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2238++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2638++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x223C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x263C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2240++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2640++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2244++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2644++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2250++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2650++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2254++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2654++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2258++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2658++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x225C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x265C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2260++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2660++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2264++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2664++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2268++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2668++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x226C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x266C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2270++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2670++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2274++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2674++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2278++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2678++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2A78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2C78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2E78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2280++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2680++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2284++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2684++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2288++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2688++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x228C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x268C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2290++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2690++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2294++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2694++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4020++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_1,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4060++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_3,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_5,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_6,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_7,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4100++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_8,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4120++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_9,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4140++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4160++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_11,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4180++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_12,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_13,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_14,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_15,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4200++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4220++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_17,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4240++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_18,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4260++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_19,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4280++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_20,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_21,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_22,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_23,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4300++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_24,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4320++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_25,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4340++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_26,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4360++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_27,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4380++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_28,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_29,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_30,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_31,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4400++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4420++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_33,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4440++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_34,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4460++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_35,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4480++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_36,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_37,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_38,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_39,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4500++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_40,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4520++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_41,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4540++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_42,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4560++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_43,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4580++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_44,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_45,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_46,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_47,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4600++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4620++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_49,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4640++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_50,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4660++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_51,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4680++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_52,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_53,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_54,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_55,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4700++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_56,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4720++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_57,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4740++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_58,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4760++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_59,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4780++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_60,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_61,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_62,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_63,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4800++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4820++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_65,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4840++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_66,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4860++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_67,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4880++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_68,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_69,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_70,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_71,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4900++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_72,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4920++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_73,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4940++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_74,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4960++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_75,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4980++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_76,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_77,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_78,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_79,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_81,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_82,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_83,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_84,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_85,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_86,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_87,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_88,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_89,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_90,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_91,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_92,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_93,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_94,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_95,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_96,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_97,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_98,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_99,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_101,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_102,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_103,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_104,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_105,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_106,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_107,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_108,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_109,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_110,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_111,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_113,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_114,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_115,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_116,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_117,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_118,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_119,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_120,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_121,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_122,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_123,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_124,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_125,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_126,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_127,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" group.long 0x4024++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_1,Source Address" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" group.long 0x4064++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_3,Source Address" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" group.long 0x40A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_5,Source Address" group.long 0x40C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_6,Source Address" group.long 0x40E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_7,Source Address" group.long 0x4104++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_8,Source Address" group.long 0x4124++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_9,Source Address" group.long 0x4144++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_10,Source Address" group.long 0x4164++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_11,Source Address" group.long 0x4184++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_12,Source Address" group.long 0x41A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_13,Source Address" group.long 0x41C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_14,Source Address" group.long 0x41E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_15,Source Address" group.long 0x4204++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_16,Source Address" group.long 0x4224++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_17,Source Address" group.long 0x4244++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_18,Source Address" group.long 0x4264++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_19,Source Address" group.long 0x4284++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_20,Source Address" group.long 0x42A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_21,Source Address" group.long 0x42C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_22,Source Address" group.long 0x42E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_23,Source Address" group.long 0x4304++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_24,Source Address" group.long 0x4324++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_25,Source Address" group.long 0x4344++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_26,Source Address" group.long 0x4364++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_27,Source Address" group.long 0x4384++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_28,Source Address" group.long 0x43A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_29,Source Address" group.long 0x43C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_30,Source Address" group.long 0x43E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_31,Source Address" group.long 0x4404++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_32,Source Address" group.long 0x4424++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_33,Source Address" group.long 0x4444++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_34,Source Address" group.long 0x4464++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_35,Source Address" group.long 0x4484++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_36,Source Address" group.long 0x44A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_37,Source Address" group.long 0x44C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_38,Source Address" group.long 0x44E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_39,Source Address" group.long 0x4504++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_40,Source Address" group.long 0x4524++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_41,Source Address" group.long 0x4544++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_42,Source Address" group.long 0x4564++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_43,Source Address" group.long 0x4584++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_44,Source Address" group.long 0x45A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_45,Source Address" group.long 0x45C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_46,Source Address" group.long 0x45E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_47,Source Address" group.long 0x4604++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_48,Source Address" group.long 0x4624++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_49,Source Address" group.long 0x4644++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_50,Source Address" group.long 0x4664++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_51,Source Address" group.long 0x4684++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_52,Source Address" group.long 0x46A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_53,Source Address" group.long 0x46C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_54,Source Address" group.long 0x46E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_55,Source Address" group.long 0x4704++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_56,Source Address" group.long 0x4724++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_57,Source Address" group.long 0x4744++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_58,Source Address" group.long 0x4764++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_59,Source Address" group.long 0x4784++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_60,Source Address" group.long 0x47A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_61,Source Address" group.long 0x47C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_62,Source Address" group.long 0x47E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_63,Source Address" group.long 0x4804++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_64,Source Address" group.long 0x4824++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_65,Source Address" group.long 0x4844++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_66,Source Address" group.long 0x4864++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_67,Source Address" group.long 0x4884++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_68,Source Address" group.long 0x48A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_69,Source Address" group.long 0x48C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_70,Source Address" group.long 0x48E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_71,Source Address" group.long 0x4904++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_72,Source Address" group.long 0x4924++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_73,Source Address" group.long 0x4944++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_74,Source Address" group.long 0x4964++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_75,Source Address" group.long 0x4984++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_76,Source Address" group.long 0x49A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_77,Source Address" group.long 0x49C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_78,Source Address" group.long 0x49E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_79,Source Address" group.long 0x4A04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_80,Source Address" group.long 0x4A24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_81,Source Address" group.long 0x4A44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_82,Source Address" group.long 0x4A64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_83,Source Address" group.long 0x4A84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_84,Source Address" group.long 0x4AA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_85,Source Address" group.long 0x4AC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_86,Source Address" group.long 0x4AE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_87,Source Address" group.long 0x4B04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_88,Source Address" group.long 0x4B24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_89,Source Address" group.long 0x4B44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_90,Source Address" group.long 0x4B64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_91,Source Address" group.long 0x4B84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_92,Source Address" group.long 0x4BA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_93,Source Address" group.long 0x4BC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_94,Source Address" group.long 0x4BE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_95,Source Address" group.long 0x4C04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_96,Source Address" group.long 0x4C24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_97,Source Address" group.long 0x4C44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_98,Source Address" group.long 0x4C64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_99,Source Address" group.long 0x4C84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_100,Source Address" group.long 0x4CA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_101,Source Address" group.long 0x4CC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_102,Source Address" group.long 0x4CE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_103,Source Address" group.long 0x4D04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_104,Source Address" group.long 0x4D24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_105,Source Address" group.long 0x4D44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_106,Source Address" group.long 0x4D64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_107,Source Address" group.long 0x4D84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_108,Source Address" group.long 0x4DA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_109,Source Address" group.long 0x4DC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_110,Source Address" group.long 0x4DE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_111,Source Address" group.long 0x4E04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_112,Source Address" group.long 0x4E24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_113,Source Address" group.long 0x4E44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_114,Source Address" group.long 0x4E64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_115,Source Address" group.long 0x4E84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_116,Source Address" group.long 0x4EA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_117,Source Address" group.long 0x4EC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_118,Source Address" group.long 0x4EE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_119,Source Address" group.long 0x4F04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_120,Source Address" group.long 0x4F24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_121,Source Address" group.long 0x4F44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_122,Source Address" group.long 0x4F64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_123,Source Address" group.long 0x4F84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_124,Source Address" group.long 0x4FA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_125,Source Address" group.long 0x4FC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_126,Source Address" group.long 0x4FE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_127,Source Address" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x402C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_1,Destination Address" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x406C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_3,Destination Address" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x40AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_5,Destination Address" group.long 0x40CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_6,Destination Address" group.long 0x40EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_7,Destination Address" group.long 0x410C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_8,Destination Address" group.long 0x412C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_9,Destination Address" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x416C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_11,Destination Address" group.long 0x418C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_12,Destination Address" group.long 0x41AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_13,Destination Address" group.long 0x41CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_14,Destination Address" group.long 0x41EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_15,Destination Address" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x422C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_17,Destination Address" group.long 0x424C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_18,Destination Address" group.long 0x426C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_19,Destination Address" group.long 0x428C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_20,Destination Address" group.long 0x42AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_21,Destination Address" group.long 0x42CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_22,Destination Address" group.long 0x42EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_23,Destination Address" group.long 0x430C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_24,Destination Address" group.long 0x432C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_25,Destination Address" group.long 0x434C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_26,Destination Address" group.long 0x436C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_27,Destination Address" group.long 0x438C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_28,Destination Address" group.long 0x43AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_29,Destination Address" group.long 0x43CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_30,Destination Address" group.long 0x43EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_31,Destination Address" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x442C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_33,Destination Address" group.long 0x444C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_34,Destination Address" group.long 0x446C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_35,Destination Address" group.long 0x448C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_36,Destination Address" group.long 0x44AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_37,Destination Address" group.long 0x44CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_38,Destination Address" group.long 0x44EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_39,Destination Address" group.long 0x450C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_40,Destination Address" group.long 0x452C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_41,Destination Address" group.long 0x454C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_42,Destination Address" group.long 0x456C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_43,Destination Address" group.long 0x458C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_44,Destination Address" group.long 0x45AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_45,Destination Address" group.long 0x45CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_46,Destination Address" group.long 0x45EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_47,Destination Address" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x462C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_49,Destination Address" group.long 0x464C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_50,Destination Address" group.long 0x466C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_51,Destination Address" group.long 0x468C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_52,Destination Address" group.long 0x46AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_53,Destination Address" group.long 0x46CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_54,Destination Address" group.long 0x46EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_55,Destination Address" group.long 0x470C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_56,Destination Address" group.long 0x472C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_57,Destination Address" group.long 0x474C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_58,Destination Address" group.long 0x476C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_59,Destination Address" group.long 0x478C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_60,Destination Address" group.long 0x47AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_61,Destination Address" group.long 0x47CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_62,Destination Address" group.long 0x47EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_63,Destination Address" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x482C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_65,Destination Address" group.long 0x484C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_66,Destination Address" group.long 0x486C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_67,Destination Address" group.long 0x488C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_68,Destination Address" group.long 0x48AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_69,Destination Address" group.long 0x48CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_70,Destination Address" group.long 0x48EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_71,Destination Address" group.long 0x490C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_72,Destination Address" group.long 0x492C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_73,Destination Address" group.long 0x494C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_74,Destination Address" group.long 0x496C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_75,Destination Address" group.long 0x498C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_76,Destination Address" group.long 0x49AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_77,Destination Address" group.long 0x49CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_78,Destination Address" group.long 0x49EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_79,Destination Address" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_81,Destination Address" group.long 0x4A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_82,Destination Address" group.long 0x4A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_83,Destination Address" group.long 0x4A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_84,Destination Address" group.long 0x4AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_85,Destination Address" group.long 0x4ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_86,Destination Address" group.long 0x4AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_87,Destination Address" group.long 0x4B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_88,Destination Address" group.long 0x4B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_89,Destination Address" group.long 0x4B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_90,Destination Address" group.long 0x4B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_91,Destination Address" group.long 0x4B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_92,Destination Address" group.long 0x4BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_93,Destination Address" group.long 0x4BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_94,Destination Address" group.long 0x4BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_95,Destination Address" group.long 0x4C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_96,Destination Address" group.long 0x4C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_97,Destination Address" group.long 0x4C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_98,Destination Address" group.long 0x4C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_99,Destination Address" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_101,Destination Address" group.long 0x4CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_102,Destination Address" group.long 0x4CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_103,Destination Address" group.long 0x4D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_104,Destination Address" group.long 0x4D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_105,Destination Address" group.long 0x4D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_106,Destination Address" group.long 0x4D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_107,Destination Address" group.long 0x4D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_108,Destination Address" group.long 0x4DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_109,Destination Address" group.long 0x4DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_110,Destination Address" group.long 0x4DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_111,Destination Address" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_113,Destination Address" group.long 0x4E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_114,Destination Address" group.long 0x4E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_115,Destination Address" group.long 0x4E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_116,Destination Address" group.long 0x4EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_117,Destination Address" group.long 0x4ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_118,Destination Address" group.long 0x4EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_119,Destination Address" group.long 0x4F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_120,Destination Address" group.long 0x4F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_121,Destination Address" group.long 0x4F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_122,Destination Address" group.long 0x4F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_123,Destination Address" group.long 0x4F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_124,Destination Address" group.long 0x4FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_125,Destination Address" group.long 0x4FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_126,Destination Address" group.long 0x4FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_127,Destination Address" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_1," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_3," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_5," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_6," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_7," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_8," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_9," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_11," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_12," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_13," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_14," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_15," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_17," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_18," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_19," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_20," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_21," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_22," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_23," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_24," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_25," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_26," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_27," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_28," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_29," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_30," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_31," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_33," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_34," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_35," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_36," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_37," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_38," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_39," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_40," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_41," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_42," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_43," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_44," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_45," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_46," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_47," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_49," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_50," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_51," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_52," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_53," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_54," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_55," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_56," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_57," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_58," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_59," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_60," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_61," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_62," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_63," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_65," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_66," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_67," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_68," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_69," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_70," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_71," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_72," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_73," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_74," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_75," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_76," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_77," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_78," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_79," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_81," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_82," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_83," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_84," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_85," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_86," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_87," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_88," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_89," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_90," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_91," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_92," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_93," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_94," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_95," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_96," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_97," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_98," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_99," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_101," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_102," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_103," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_104," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_105," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_106," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_107," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_108," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_109," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_110," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_111," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_113," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_114," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_115," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_116," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_117," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_118," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_119," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_120," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_121," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_122," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_123," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_124," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_125," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_126," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_127," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x403C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x407C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x411C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x413C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x417C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x419C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x423C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x425C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x427C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x429C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x431C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x433C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x435C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x437C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x439C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x443C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x445C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x447C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x449C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x451C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x453C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x455C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x457C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x459C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x463C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x465C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x467C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x469C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x471C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x473C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x475C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x477C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x479C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x483C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x485C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x487C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x489C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x491C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x493C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x495C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x497C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x499C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x42086000 ad:0x42087000 ) tree "EVE_EDMA_TPTC$1" base $2 group.long 0x100++0x13 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 11.--12. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" rbitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" rbitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" line.long 0x04 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" rbitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x08 "EDMA_TPTCn_INTEN,Interrupt Enable Register" hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x0C "EDMA_TPTCn_INTCLR,Interrupt Clear Register" hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x10 "EDMA_TPTCn_INTCMD,Interrupt Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" group.long 0x120++0x13 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" rbitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 1. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" line.long 0x04 "EDMA_TPTCn_ERREN,Error Enable Register" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x04 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x04 1. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" line.long 0x08 "EDMA_TPTCn_ERRCLR,Error Clear Register" hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x08 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x08 1. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" line.long 0x0C "EDMA_TPTCn_ERRDET,Error Details Register" hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0C 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" rbitfld.long 0x0C 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 14.--15. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EDMA_TPTCn_ERRCMD,Error Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" group.long 0x200++0x17 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" rbitfld.long 0x00 21. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" rbitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "Highest priority,Priority 1,?,?,?,?,?,Lowest priority" newline rbitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" line.long 0x08 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count" line.long 0x0C "EDMA_TPTCn_PDST,Program Set Destination Address" line.long 0x10 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" line.long 0x14 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x240++0x0B line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" line.long 0x08 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" rgroup.long 0x250++0x13 line.long 0x00 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" line.long 0x04 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x08 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" line.long 0x0C "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" line.long 0x10 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" group.long 0x280++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" line.long 0x04 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" group.long 0x300++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x304++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x344++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x308++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x348++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x30C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x34C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x350++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" group.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x354++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end repeat.end tree "EVE_FW" base ad:0x4A151000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "EVE_FW_CFG_TARG" base ad:0x4A152000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "EVE_L2_FNOC" base ad:0x208A000 rgroup.long 0x00++0x03 line.long 0x00 "ERRLOGGER_i_ID_COREID_0," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" rgroup.long 0x200++0x03 line.long 0x00 "ERRLOGGER_i_ID_COREID_1," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" rgroup.long 0x04++0x03 line.long 0x00 "ERRLOGGER_i_ID_REVISIONID_0," hexmask.long.tbyte 0x00 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code" hexmask.long.byte 0x00 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself" rgroup.long 0x204++0x03 line.long 0x00 "ERRLOGGER_i_ID_REVISIONID_1," hexmask.long.tbyte 0x00 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code" hexmask.long.byte 0x00 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself" group.long 0x08++0x03 line.long 0x00 "ERRLOGGER_i_FAULTEN_0," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FAULTEN,Enable Fault output" "0,1" group.long 0x208++0x03 line.long 0x00 "ERRLOGGER_i_FAULTEN_1," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FAULTEN,Enable Fault output" "0,1" rgroup.long 0x0C++0x03 line.long 0x00 "ERRLOGGER_i_ERRVLD_0," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "ERRVLD,Error logged Valid" "0,1" rgroup.long 0x20C++0x03 line.long 0x00 "ERRLOGGER_i_ERRVLD_1," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "ERRVLD,Error logged Valid" "0,1" group.long 0x10++0x03 line.long 0x00 "ERRLOGGER_i_ERRCLR_0," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "ERRCLR,Clr ErrVld status" "0,1" group.long 0x210++0x03 line.long 0x00 "ERRLOGGER_i_ERRCLR_1," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "ERRCLR,Clr ErrVld status" "0,1" rgroup.long 0x14++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG0_0,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x00 31. "FORMAT,Format of ErrLog0 register" "0,1" bitfld.long 0x00 26.--30. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. "LEN1,Header: Len1 value" bitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "LOCK,Header: Lock bit value" "0,1" rgroup.long 0x214++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG0_1,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x00 31. "FORMAT,Format of ErrLog0 register" "0,1" bitfld.long 0x00 26.--30. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. "LEN1,Header: Len1 value" bitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "LOCK,Header: Lock bit value" "0,1" rgroup.long 0x18++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG1_0," hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED," hexmask.long.word 0x00 0.--13. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x218++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG1_1," hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED," hexmask.long.word 0x00 0.--13. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x20++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG3_0," rgroup.long 0x220++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG3_1," rgroup.long 0x28++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG5_0," hexmask.long.word 0x00 17.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--16. 1. "ERRLOG5,Header: User lsb value" rgroup.long 0x228++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG5_1," hexmask.long.word 0x00 17.--31. 1. "RESERVED," hexmask.long.tbyte 0x00 0.--16. 1. "ERRLOG5,Header: User lsb value" rgroup.long 0x100++0x03 line.long 0x00 "FLAGMUX_i_ID_COREID_0," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" rgroup.long 0x300++0x03 line.long 0x00 "FLAGMUX_i_ID_COREID_1," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" rgroup.long 0x104++0x03 line.long 0x00 "FLAGMUX_i_ID_REVISIONID_0," hexmask.long.tbyte 0x00 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code" hexmask.long.byte 0x00 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself" rgroup.long 0x304++0x03 line.long 0x00 "FLAGMUX_i_ID_REVISIONID_1," hexmask.long.tbyte 0x00 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code" hexmask.long.byte 0x00 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself" group.long 0x108++0x03 line.long 0x00 "FLAGMUX_i_FAULTEN_0," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FAULTEN,Global Fault Enable register" "0,1" group.long 0x308++0x03 line.long 0x00 "FLAGMUX_i_FAULTEN_1," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FAULTEN,Global Fault Enable register" "0,1" rgroup.long 0x10C++0x03 line.long 0x00 "FLAGMUX_i_FAULTSTATUS_0," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FAULTSTATUS,Global Fault Status register" "0,1" rgroup.long 0x30C++0x03 line.long 0x00 "FLAGMUX_i_FAULTSTATUS_1," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FAULTSTATUS,Global Fault Status register" "0,1" group.long 0x110++0x03 line.long 0x00 "FLAGMUX_i_FLAGINEN0_0," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" group.long 0x310++0x03 line.long 0x00 "FLAGMUX_i_FLAGINEN0_1," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" rgroup.long 0x114++0x03 line.long 0x00 "FLAGMUX_i_FLAGINSTATUS0_0," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" rgroup.long 0x314++0x03 line.long 0x00 "FLAGMUX_i_FLAGINSTATUS0_1," hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x42081000 ad:0x42082000 ) tree "EVE_MMU$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Write 0's for future compatibility" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" rbitfld.long 0x00 5.--7. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x00 2. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" hexmask.long 0x08 5.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" newline bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0_w,EMUMISS_1_r" bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" hexmask.long 0x0C 5.--31. 1. "RESERVED,Write 0's for future compatibility Read returns 0" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" newline bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0,EMUMISS_1" bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" hexmask.long 0x00 1.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" hexmask.long 0x04 4.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable" "TWLENABLE_0,TWLENABLE_1" newline bitfld.long 0x04 1. "MMUENABLE,MMU enable" "MMUENABLE_0,MMUENABLE_1" rbitfld.long 0x04 0. "RESERVED,Write 0's for future compatibility" "0,1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" hexmask.long.byte 0x0C 0.--6. 1. "RESERVED,Write 0's for future compatibility" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 9. "RESERVED,Write 0's for future compatibility" "0,1" newline bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 0.--3. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" hexmask.long 0x14 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x18 4.--11. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x18 3. "P,Preserved bit" "P_0,P_1" newline bitfld.long 0x18 2. "V,Valid bit" "V_0,V_1" bitfld.long 0x18 0.--1. "PAGESIZE,Page size" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x1C 0.--11. 1. "RESERVED,Write 0's for future compatibility" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" hexmask.long 0x20 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" hexmask.long 0x24 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x28 4.--11. 1. "RESERVED,Reads return 0" bitfld.long 0x28 3. "P,Preserved bit" "P_0_r,P_1_r" newline bitfld.long 0x28 2. "V,Valid bit" "V_0_r,V_1_r" bitfld.long 0x28 0.--1. "PAGESIZE,Page size" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x2C 0.--11. 1. "RESERVED,Reads return 0" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" newline rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "0,1,2,3" bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "0,1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" hexmask.long.word 0x08 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 0.--15. 1. "RESERVED,Reserved" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 0.--15. 1. "RESERVED,Reserved" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 0.--15. 1. "RESERVED,Reserved" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the fourth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 0.--15. 1. "RESERVED,Reserved" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of fourth NO TRANSLATION REGION for 2D bursts" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" width 0x0B tree.end repeat.end tree "EVE_SCTM" base ad:0x42085000 group.long 0x00++0x03 line.long 0x00 "SCTM_CTCNTL," rbitfld.long 0x00 26.--31. "NUMSTM,Number of timers that can export through STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 18.--25. 1. "NUMINPT,Number of event input signals" rbitfld.long 0x00 13.--17. "NUMTIMR,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 7.--12. "NUMCNTR,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 3.--6. "REVID,Revision ID of SCTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1.--2. "IDLEMODE,Idle mode control" "Force Idle mode,Ths SCTM will acknoledge the idle request but..,Ths SCTM uses the smart idle protocol,Since the SCTM does not support internal wakeup.." bitfld.long 0x00 0. "ENBL,SCTM global enable" "ENBL_0,ENBL_1" group.long 0x20++0x0F line.long 0x00 "SCTM_CTSTMCNTL,This register contains the control and status settings for STM export" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," rbitfld.long 0x00 10. "XPORTACT,Indicates if a frame is currently being written to the STM" "0,1" bitfld.long 0x00 5.--9. "NUMXPORT,The total number of counters designated for export" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. "CCMXPORT,SW control of CCM message export" "0,1" rbitfld.long 0x00 3. "CCMVAIL,SCTM supports CCM export" "0,1" newline bitfld.long 0x00 2. "CSMXPORT,SW control of CSM message export" "0,1" bitfld.long 0x00 1. "SENDOVR,Send overflow data in CSM frame" "0,1" bitfld.long 0x00 0. "ENBL,STM global enable" "ENBL_0,ENBL_1" line.long 0x04 "SCTM_CTSTMMSTID," hexmask.long 0x04 7.--31. 1. "RESERVED," hexmask.long.byte 0x04 0.--6. 1. "MASTID,HW Master ID for this module" line.long 0x08 "SCTM_CTSTMINTVL," hexmask.long.word 0x08 16.--31. 1. "RESERVED," hexmask.long.word 0x08 0.--15. 1. "INTERVAL,Periodic export interval" line.long 0x0C "SCTM_CTSTMSEL,These registers mark the counters selected for export in the CSM" group.long 0x40++0x1F line.long 0x00 "SCTM_TINTVLR_i_0,These registers contain the interval match value for the corresponding timers in the SCTM" line.long 0x04 "SCTM_TINTVLR_i_1,These registers contain the interval match value for the corresponding timers in the SCTM" line.long 0x08 "SCTM_TINTVLR_i_2,These registers contain the interval match value for the corresponding timers in the SCTM" line.long 0x0C "SCTM_TINTVLR_i_3,These registers contain the interval match value for the corresponding timers in the SCTM" line.long 0x10 "SCTM_TINTVLR_i_4,These registers contain the interval match value for the corresponding timers in the SCTM" line.long 0x14 "SCTM_TINTVLR_i_5,These registers contain the interval match value for the corresponding timers in the SCTM" line.long 0x18 "SCTM_TINTVLR_i_6,These registers contain the interval match value for the corresponding timers in the SCTM" line.long 0x1C "SCTM_TINTVLR_i_7,These registers contain the interval match value for the corresponding timers in the SCTM" rgroup.long 0x7C++0x07 line.long 0x00 "SCTM_CTDBGNUM,Counter Timer Number Debug Event Register" hexmask.long 0x00 3.--31. 1. "RESERVED," bitfld.long 0x00 0.--2. "NUMEVT,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" line.long 0x04 "SCTM_CTDBGEVT,Counter Timer Debug Event Register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," hexmask.long.byte 0x04 0.--7. 1. "INPSEL,Index of event input signal on the module boundary" group.long 0xF0++0x03 line.long 0x00 "SCTM_CTGNBL,These registers provide for simultaneous enable/disable of 32 counters" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," hexmask.long.byte 0x00 0.--7. 1. "ENABLE,The counter enable bit field" group.long 0xF8++0x03 line.long 0x00 "SCTM_CTGRST,These registers provide for simultaneous reset of 32 counters" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," hexmask.long.byte 0x00 0.--7. 1. "RESET,The counter reset bit field" group.long 0x100++0x1F line.long 0x00 "SCTM_CTCR_WT_m_0,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x00 21.--31. 1. "RESERVED," bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" newline bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 7. "RESERVED," "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" newline bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" line.long 0x04 "SCTM_CTCR_WT_m_1,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x04 21.--31. 1. "RESERVED," bitfld.long 0x04 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x04 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x04 9. "DBG,Signal debug logic on interval match" "0,1" newline bitfld.long 0x04 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x04 7. "RESERVED," "0,1" rbitfld.long 0x04 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x04 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x04 4. "FREE,Counter ignores processor debug halt state" "0,1" newline bitfld.long 0x04 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x04 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x04 1. "RESET,Counter reset control" "0,1" bitfld.long 0x04 0. "ENBL,Counter enable control" "0,1" line.long 0x08 "SCTM_CTCR_WOT_n_0,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x08 21.--31. 1. "RESERVED," bitfld.long 0x08 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x08 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x08 9. "DBG,Signal debug logic on interval match" "0,1" newline bitfld.long 0x08 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x08 7. "RESERVED," "0,1" rbitfld.long 0x08 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x08 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x08 4. "FREE,Counter ignores processor debug halt state" "0,1" newline bitfld.long 0x08 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x08 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x08 1. "RESET,Counter reset control" "0,1" bitfld.long 0x08 0. "ENBL,Counter enable control" "0,1" line.long 0x0C "SCTM_CTCR_WOT_n_1,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x0C 21.--31. 1. "RESERVED," bitfld.long 0x0C 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x0C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x0C 9. "DBG,Signal debug logic on interval match" "0,1" newline bitfld.long 0x0C 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x0C 7. "RESERVED," "0,1" rbitfld.long 0x0C 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x0C 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x0C 4. "FREE,Counter ignores processor debug halt state" "0,1" newline bitfld.long 0x0C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x0C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0C 1. "RESET,Counter reset control" "0,1" bitfld.long 0x0C 0. "ENBL,Counter enable control" "0,1" line.long 0x10 "SCTM_CTCR_WOT_n_2,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x10 21.--31. 1. "RESERVED," bitfld.long 0x10 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x10 9. "DBG,Signal debug logic on interval match" "0,1" newline bitfld.long 0x10 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x10 7. "RESERVED," "0,1" rbitfld.long 0x10 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x10 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x10 4. "FREE,Counter ignores processor debug halt state" "0,1" newline bitfld.long 0x10 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x10 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x10 1. "RESET,Counter reset control" "0,1" bitfld.long 0x10 0. "ENBL,Counter enable control" "0,1" line.long 0x14 "SCTM_CTCR_WOT_n_3,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x14 21.--31. 1. "RESERVED," bitfld.long 0x14 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x14 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x14 9. "DBG,Signal debug logic on interval match" "0,1" newline bitfld.long 0x14 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x14 7. "RESERVED," "0,1" rbitfld.long 0x14 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x14 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x14 4. "FREE,Counter ignores processor debug halt state" "0,1" newline bitfld.long 0x14 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x14 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x14 1. "RESET,Counter reset control" "0,1" bitfld.long 0x14 0. "ENBL,Counter enable control" "0,1" line.long 0x18 "SCTM_CTCR_WOT_n_4,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x18 21.--31. 1. "RESERVED," bitfld.long 0x18 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x18 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x18 9. "DBG,Signal debug logic on interval match" "0,1" newline bitfld.long 0x18 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x18 7. "RESERVED," "0,1" rbitfld.long 0x18 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x18 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x18 4. "FREE,Counter ignores processor debug halt state" "0,1" newline bitfld.long 0x18 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x18 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x18 1. "RESET,Counter reset control" "0,1" bitfld.long 0x18 0. "ENBL,Counter enable control" "0,1" line.long 0x1C "SCTM_CTCR_WOT_n_5,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x1C 21.--31. 1. "RESERVED," bitfld.long 0x1C 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x1C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x1C 9. "DBG,Signal debug logic on interval match" "0,1" newline bitfld.long 0x1C 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x1C 7. "RESERVED," "0,1" rbitfld.long 0x1C 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x1C 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x1C 4. "FREE,Counter ignores processor debug halt state" "0,1" newline bitfld.long 0x1C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x1C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x1C 1. "RESET,Counter reset control" "0,1" bitfld.long 0x1C 0. "ENBL,Counter enable control" "0,1" rgroup.long 0x180++0x1F line.long 0x00 "SCTM_CTCNTR_k_0,These registers contain the value of an individual counter in the moduel" line.long 0x04 "SCTM_CTCNTR_k_1,These registers contain the value of an individual counter in the moduel" line.long 0x08 "SCTM_CTCNTR_k_2,These registers contain the value of an individual counter in the moduel" line.long 0x0C "SCTM_CTCNTR_k_3,These registers contain the value of an individual counter in the moduel" line.long 0x10 "SCTM_CTCNTR_k_4,These registers contain the value of an individual counter in the moduel" line.long 0x14 "SCTM_CTCNTR_k_5,These registers contain the value of an individual counter in the moduel" line.long 0x18 "SCTM_CTCNTR_k_6,These registers contain the value of an individual counter in the moduel" line.long 0x1C "SCTM_CTCNTR_k_7,These registers contain the value of an individual counter in the moduel" width 0x0B tree.end tree "EVE_SMSET" base ad:0x42088000 rgroup.long 0x00++0x03 line.long 0x00 "SMSET_ID,SMSET identification register" group.long 0x10++0x07 line.long 0x00 "SMSET_SCFG,SMSET system configuration register" hexmask.long 0x00 4.--31. 1. "RESERVED," rbitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "0,1,2,3" rbitfld.long 0x00 1. "RESERVED," "0,1" newline bitfld.long 0x00 0. "SOFTRESET,Triggers System Event Trace module reset" "0,1" line.long 0x04 "SMSET_SR,SMSET Status Register" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "SWFIFOEMPTY,SW message FIFO empty" "0,1" bitfld.long 0x04 8. "HWFIFOEMPTY,System event trace FIFO empty" "0,1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "RESETDONE,Reset completed" "0,1" group.long 0x24++0x07 line.long 0x00 "SMSET_CFG,SMSET Configuration register" bitfld.long 0x00 30.--31. "OWNERSHIP,Read to get current ownership status" "Release ownership,Claim ownership,Enable unit,No operation" bitfld.long 0x00 29. "DEBUGGEROVERRIDE,Reading from the DebuggerOverride bit returns a 1" "0,1" rbitfld.long 0x00 28. "CURRENTOWNER,This value reflects the SMSET ownership when the register is in a non-Available state" "0,1" newline hexmask.long.tbyte 0x00 8.--27. 1. "RESERVED," bitfld.long 0x00 7. "CAPTUREEN,When high the sytem event capture is enabled" "0,1" rbitfld.long 0x00 5.--6. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 4. "EVENTLEVEL,This applies to all selected events" "low level event detection,high level evnet detection" bitfld.long 0x00 3. "EVENTMSG,essage generated based on" "sampling window,event detection" bitfld.long 0x00 2. "STOP,Stop capturing system events from external trigger detection [EMU1 HIGH to LOW]" "0,1" newline bitfld.long 0x00 1. "START,Start capturing system events from external trigger detection [EMU0 HIGH to LOW]" "0,1" rbitfld.long 0x00 0. "RESERVED," "0,1" line.long 0x04 "SMSET_SESW,System Event Sampling Window register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," hexmask.long.byte 0x04 0.--7. 1. "SAMPLINGWINDOWSIZE,System events sampling window size expressed as SMSET cycles" group.long 0x30++0x1F line.long 0x00 "SMSET_SEDEN_i_1,System Event Detection Enable register 1" bitfld.long 0x00 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x00 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x00 29. "EVENT30EN,Event 30 detection enable" "0,1" newline bitfld.long 0x00 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x00 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x00 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x00 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x00 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x00 23. "EVENT24EN,Event 24 detection enable" "0,1" newline bitfld.long 0x00 22. "EVENT23EN,Event 23 detection enable" "0,1" bitfld.long 0x00 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x00 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x00 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x00 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x00 17. "EVENT18EN,Event 18 detection enable" "0,1" newline bitfld.long 0x00 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x00 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x00 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x00 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x00 12. "EVENT13EN,Event 13 detection enable" "0,1" bitfld.long 0x00 11. "EVENT12EN,Event 12 detection enable" "0,1" newline bitfld.long 0x00 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x00 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x00 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x00 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x00 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x00 5. "EVENT6EN,Event 6 detection enable" "0,1" newline bitfld.long 0x00 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x00 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x00 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x00 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x00 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x04 "SMSET_SEDEN_i_2,System Event Detection Enable register 1" bitfld.long 0x04 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x04 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x04 29. "EVENT30EN,Event 30 detection enable" "0,1" newline bitfld.long 0x04 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x04 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x04 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x04 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x04 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x04 23. "EVENT24EN,Event 24 detection enable" "0,1" newline bitfld.long 0x04 22. "EVENT23EN,Event 23 detection enable" "0,1" bitfld.long 0x04 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x04 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x04 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x04 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x04 17. "EVENT18EN,Event 18 detection enable" "0,1" newline bitfld.long 0x04 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x04 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x04 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x04 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x04 12. "EVENT13EN,Event 13 detection enable" "0,1" bitfld.long 0x04 11. "EVENT12EN,Event 12 detection enable" "0,1" newline bitfld.long 0x04 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x04 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x04 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x04 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x04 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x04 5. "EVENT6EN,Event 6 detection enable" "0,1" newline bitfld.long 0x04 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x04 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x04 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x04 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x04 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x08 "SMSET_SEDEN_i_3,System Event Detection Enable register 1" bitfld.long 0x08 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x08 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x08 29. "EVENT30EN,Event 30 detection enable" "0,1" newline bitfld.long 0x08 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x08 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x08 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x08 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x08 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x08 23. "EVENT24EN,Event 24 detection enable" "0,1" newline bitfld.long 0x08 22. "EVENT23EN,Event 23 detection enable" "0,1" bitfld.long 0x08 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x08 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x08 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x08 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x08 17. "EVENT18EN,Event 18 detection enable" "0,1" newline bitfld.long 0x08 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x08 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x08 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x08 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x08 12. "EVENT13EN,Event 13 detection enable" "0,1" bitfld.long 0x08 11. "EVENT12EN,Event 12 detection enable" "0,1" newline bitfld.long 0x08 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x08 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x08 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x08 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x08 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x08 5. "EVENT6EN,Event 6 detection enable" "0,1" newline bitfld.long 0x08 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x08 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x08 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x08 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x08 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x0C "SMSET_SEDEN_i_4,System Event Detection Enable register 1" bitfld.long 0x0C 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x0C 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x0C 29. "EVENT30EN,Event 30 detection enable" "0,1" newline bitfld.long 0x0C 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x0C 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x0C 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x0C 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x0C 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x0C 23. "EVENT24EN,Event 24 detection enable" "0,1" newline bitfld.long 0x0C 22. "EVENT23EN,Event 23 detection enable" "0,1" bitfld.long 0x0C 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x0C 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x0C 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x0C 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x0C 17. "EVENT18EN,Event 18 detection enable" "0,1" newline bitfld.long 0x0C 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x0C 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x0C 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x0C 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x0C 12. "EVENT13EN,Event 13 detection enable" "0,1" bitfld.long 0x0C 11. "EVENT12EN,Event 12 detection enable" "0,1" newline bitfld.long 0x0C 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x0C 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x0C 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x0C 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x0C 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x0C 5. "EVENT6EN,Event 6 detection enable" "0,1" newline bitfld.long 0x0C 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x0C 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x0C 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x0C 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x0C 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x10 "SMSET_SEDEN_i_5,System Event Detection Enable register 1" bitfld.long 0x10 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x10 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x10 29. "EVENT30EN,Event 30 detection enable" "0,1" newline bitfld.long 0x10 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x10 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x10 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x10 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x10 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x10 23. "EVENT24EN,Event 24 detection enable" "0,1" newline bitfld.long 0x10 22. "EVENT23EN,Event 23 detection enable" "0,1" bitfld.long 0x10 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x10 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x10 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x10 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x10 17. "EVENT18EN,Event 18 detection enable" "0,1" newline bitfld.long 0x10 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x10 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x10 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x10 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x10 12. "EVENT13EN,Event 13 detection enable" "0,1" bitfld.long 0x10 11. "EVENT12EN,Event 12 detection enable" "0,1" newline bitfld.long 0x10 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x10 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x10 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x10 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x10 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x10 5. "EVENT6EN,Event 6 detection enable" "0,1" newline bitfld.long 0x10 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x10 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x10 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x10 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x10 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x14 "SMSET_SEDEN_i_6,System Event Detection Enable register 1" bitfld.long 0x14 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x14 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x14 29. "EVENT30EN,Event 30 detection enable" "0,1" newline bitfld.long 0x14 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x14 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x14 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x14 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x14 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x14 23. "EVENT24EN,Event 24 detection enable" "0,1" newline bitfld.long 0x14 22. "EVENT23EN,Event 23 detection enable" "0,1" bitfld.long 0x14 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x14 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x14 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x14 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x14 17. "EVENT18EN,Event 18 detection enable" "0,1" newline bitfld.long 0x14 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x14 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x14 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x14 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x14 12. "EVENT13EN,Event 13 detection enable" "0,1" bitfld.long 0x14 11. "EVENT12EN,Event 12 detection enable" "0,1" newline bitfld.long 0x14 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x14 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x14 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x14 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x14 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x14 5. "EVENT6EN,Event 6 detection enable" "0,1" newline bitfld.long 0x14 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x14 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x14 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x14 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x14 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x18 "SMSET_SEDEN_i_7,System Event Detection Enable register 1" bitfld.long 0x18 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x18 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x18 29. "EVENT30EN,Event 30 detection enable" "0,1" newline bitfld.long 0x18 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x18 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x18 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x18 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x18 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x18 23. "EVENT24EN,Event 24 detection enable" "0,1" newline bitfld.long 0x18 22. "EVENT23EN,Event 23 detection enable" "0,1" bitfld.long 0x18 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x18 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x18 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x18 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x18 17. "EVENT18EN,Event 18 detection enable" "0,1" newline bitfld.long 0x18 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x18 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x18 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x18 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x18 12. "EVENT13EN,Event 13 detection enable" "0,1" bitfld.long 0x18 11. "EVENT12EN,Event 12 detection enable" "0,1" newline bitfld.long 0x18 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x18 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x18 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x18 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x18 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x18 5. "EVENT6EN,Event 6 detection enable" "0,1" newline bitfld.long 0x18 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x18 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x18 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x18 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x18 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x1C "SMSET_SEDEN_i_8,System Event Detection Enable register 1" bitfld.long 0x1C 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x1C 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x1C 29. "EVENT30EN,Event 30 detection enable" "0,1" newline bitfld.long 0x1C 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x1C 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x1C 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x1C 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x1C 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x1C 23. "EVENT24EN,Event 24 detection enable" "0,1" newline bitfld.long 0x1C 22. "EVENT23EN,Event 23 detection enable" "0,1" bitfld.long 0x1C 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x1C 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x1C 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x1C 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x1C 17. "EVENT18EN,Event 18 detection enable" "0,1" newline bitfld.long 0x1C 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x1C 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x1C 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x1C 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x1C 12. "EVENT13EN,Event 13 detection enable" "0,1" bitfld.long 0x1C 11. "EVENT12EN,Event 12 detection enable" "0,1" newline bitfld.long 0x1C 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x1C 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x1C 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x1C 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x1C 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x1C 5. "EVENT6EN,Event 6 detection enable" "0,1" newline bitfld.long 0x1C 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x1C 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x1C 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x1C 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x1C 0. "EVENT1EN,Event 1 detection enable" "0,1" width 0x0B tree.end tree "EVE_TARG" base ad:0x44000A00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "EVE_VCOP" base ad:0x42084000 rgroup.long 0x00++0x13 line.long 0x00 "VCOP_PID," line.long 0x04 "VCOP_CTRL,VCOP Control Register" hexmask.long 0x04 2.--31. 1. "RESERVED," bitfld.long 0x04 1. "STEP_GO,Starts executing a single i4 iteration" "STEP_GO_0,STEP_GO_1" bitfld.long 0x04 0. "STEP_EN,Enable Single Step mode" "STEP_EN_0,STEP_EN_1" line.long 0x08 "VCOP_STATUS,VCOP status register" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "VEC_RDY,Vector core ready to accept next vector instruction" "0,1" bitfld.long 0x08 1. "VEC_DONE,Vector core has completed execution of submitted vector loops" "0,1" bitfld.long 0x08 0. "STEP_RDY,Ready for next step (single step)" "STEP_RDY_0,STEP_RDY_1" line.long 0x0C "VCOP_MAX_ITERS," hexmask.long.word 0x0C 16.--31. 1. "RESESERVED,Reserved" hexmask.long.word 0x0C 0.--15. 1. "MAX_ITERS,Maximum iteration count" line.long 0x10 "VCOP_ERROR,Error interrupt enalbe and status register" hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 23. "ERR_DIS7,Error Interrupt disable" "ERR_DIS7_0,ERR_DIS7_1" bitfld.long 0x10 22. "ERR_DIS6,Error Interrupt disable" "ERR_DIS6_0,ERR_DIS6_1" bitfld.long 0x10 21. "ERR_DIS5,Error Interrupt disable" "ERR_DIS5_0,ERR_DIS5_1" bitfld.long 0x10 20. "ERR_DIS4,Error Interrupt disable" "ERR_DIS4_0,ERR_DIS4_1" newline bitfld.long 0x10 19. "ERR_DIS3,Error Interrupt disable" "ERR_DIS3_0,ERR_DIS3_1" bitfld.long 0x10 18. "ERR_DIS2,Error Interrupt disable" "ERR_DIS2_0,ERR_DIS2_1" bitfld.long 0x10 17. "ERR_DIS1,Error Interrupt disable" "ERR_DIS1_0,ERR_DIS1_1" bitfld.long 0x10 16. "ERR_DIS0,Error Interrupt disable" "ERR_DIS0_0,ERR_DIS0_1" hexmask.long.byte 0x10 8.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x10 7. "ERR_ST7,ST_PDDA bank conflict error status" "ERR_ST7_0,ERR_ST7_1" bitfld.long 0x10 6. "ERR_ST6,ST WBUF out-of-bound error status" "ERR_ST6_0,ERR_ST6_1" bitfld.long 0x10 5. "ERR_ST5,ST IBUF out-of-bound error status" "ERR_ST5_0,ERR_ST5_1" bitfld.long 0x10 4. "ERR_ST4,LD WBUF out-of-bound error status" "ERR_ST4_0,ERR_ST4_1" bitfld.long 0x10 3. "ERR_ST3,LD IBUF out-of-bound error status" "ERR_ST3_0,ERR_ST3_1" newline bitfld.long 0x10 2. "ERR_ST2,Illegal parameter error status" "ERR_ST2_0,ERR_ST2_1" bitfld.long 0x10 1. "ERR_ST1,Illegal instruction error status" "ERR_ST1_0,ERR_ST1_1" bitfld.long 0x10 0. "ERR_ST0,Illegal instruction error status" "ERR_ST0_0,ERR_ST0_1" rgroup.long 0x20++0x07 line.long 0x00 "VCOP_VLOOP_PTR,The VLOOP pointer" line.long 0x04 "VCOP_PARAM_PTR," rgroup.long 0x30++0x0B line.long 0x00 "VCOP_I0_I1,I0. I1 loop variables register provides a snapshot of i0 and i1" hexmask.long.word 0x00 16.--31. 1. "I1,Snapshot of I1 loop variable" hexmask.long.word 0x00 0.--15. 1. "I0,Snapshot of I0 loop variable" line.long 0x04 "VCOP_I2_I3,I2. I3 loop variables register provides a snapshot of i2 and i3" hexmask.long.word 0x04 16.--31. 1. "I3,Snapshot of I2 loop variable" hexmask.long.word 0x04 0.--15. 1. "I2,Snapshot of I3 loop variable" line.long 0x08 "VCOP_I4,I4 loop variables register provides a snapshot of i4" hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved Read returns 0s" hexmask.long.word 0x08 0.--15. 1. "I4,Snapshot of I4 loop variable" rgroup.long 0x40++0x3F line.long 0x00 "VCOP_LD_PTR_i_0,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" line.long 0x04 "VCOP_LD_PTR_i_1,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" line.long 0x08 "VCOP_LD_PTR_i_2,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" line.long 0x0C "VCOP_LD_PTR_i_3,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" line.long 0x10 "VCOP_LD_PTR_i_4,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" line.long 0x14 "VCOP_LD_PTR_i_5,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" line.long 0x18 "VCOP_LD_PTR_i_6,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" line.long 0x1C "VCOP_LD_PTR_i_7,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" line.long 0x20 "VCOP_ST_PTR_j_0,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" line.long 0x24 "VCOP_ST_PTR_j_1,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" line.long 0x28 "VCOP_ST_PTR_j_2,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" line.long 0x2C "VCOP_ST_PTR_j_3,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" line.long 0x30 "VCOP_ST_PTR_j_4,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" line.long 0x34 "VCOP_ST_PTR_j_5,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" line.long 0x38 "VCOP_ST_PTR_j_6,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" line.long 0x3C "VCOP_ST_PTR_j_7,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" width 0x0B tree.end tree "GMAC_SW_TARG" base ad:0x48488000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end repeat 4. (list 2. 3. 4. 1. )(list ad:0x48055000 ad:0x48057000 ad:0x48059000 ad:0x4AE10000 ) tree "GPIO$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "GPIO_REVISION,IP revision identifier (X.Y.R)" group.long 0x10++0x03 line.long 0x00 "GPIO_SYSCONFIG,System configuration register" hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 3.--4. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wake-up control" "ENAWAKEUP_0,ENAWAKEUP_1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOIDLE,OCP clock gating control" "AUTOIDLE_0,AUTOIDLE_1" group.long 0x20++0x2B line.long 0x00 "GPIO_EOI,Software end of interrupt" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1" line.long 0x04 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. showing all active events (enabled and not enabled). (corresponding to first line of interrupt)" line.long 0x08 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. showing all active events (enabled and not enabled). (corresponding to second line of interrupt)" line.long 0x0C "GPIO_IRQSTATUS_0,Per-event interrupt status vector. showing all active and enabled events (corresponding to first line of interrupt)" line.long 0x10 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector. showing all active and enabled events (corresponding to second line of interrupt)" line.long 0x14 "GPIO_IRQSTATUS_SET_0,Per-event interrupt-enable set vector (corresponding to first line of interrupt)" line.long 0x18 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" line.long 0x1C "GPIO_IRQSTATUS_CLR_0,Per-event interrupt-enable clear vector (corresponding to first line of interrupt)" line.long 0x20 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" line.long 0x24 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" line.long 0x28 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" rgroup.long 0x114++0x03 line.long 0x00 "GPIO_SYSSTATUS,System status register" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "RESETDONE," "RESETDONE_0_r,RESETDONE_1_r" group.long 0x130++0x27 line.long 0x00 "GPIO_CTRL,GPIO control register" hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1.--2. "GATINGRATIO,Clock gating ratio for event detection" "GATINGRATIO_0,GATINGRATIO_1,GATINGRATIO_2,GATINGRATIO_3" bitfld.long 0x00 0. "DISABLEMODULE," "DISABLEMODULE_0,DISABLEMODULE_1" line.long 0x04 "GPIO_OE,Output enable register" line.long 0x08 "GPIO_DATAIN,Data input register (with sampled input data)" line.long 0x0C "GPIO_DATAOUT,Data-output register (data to set on output pins)" line.long 0x10 "GPIO_LEVELDETECT0,Detect low-level register" line.long 0x14 "GPIO_LEVELDETECT1,Detect high-level register" line.long 0x18 "GPIO_RISINGDETECT,Detect rising edge register" line.long 0x1C "GPIO_FALLINGDETECT,Detect falling edge register" line.long 0x20 "GPIO_DEBOUNCENABLE,Debouncing enable register" line.long 0x24 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x24 0.--7. 1. "DEBOUNCETIME,8-bit values specifying the debouncing time" group.long 0x190++0x07 line.long 0x00 "GPIO_CLEARDATAOUT,Clear data-output register" line.long 0x04 "GPIO_SETDATAOUT,Set data-output register" width 0x0B tree.end repeat.end tree "GPIO1_TARG" base ad:0x4AE11000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPIO2_TARG" base ad:0x48056000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPIO3_TARG" base ad:0x48058000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPIO4_TARG" base ad:0x4805A000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPMC" base ad:0x50000000 rgroup.long 0x00++0x03 line.long 0x00 "GPMC_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "GPMC_SYSCONFIG,This register controls the various parameters of the interconnect" hexmask.long 0x00 5.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 3.--4. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 2. "RESERVED,Write 0 for future compatibility Read returns 0" "0,1" newline bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOIDLE,Internal interface clock-gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "GPMC_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED,Read returns 0 (reserved for interconnect-socket status information)" newline bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0,RESETDONE_1" line.long 0x08 "GPMC_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x08 9. "WAIT1EDGEDETECTIONSTATUS,Status of the Wait1 Edge Detection interrupt" "WAIT1EDGEDETECTIONSTATUS_0_w,WAIT1EDGEDETECTIONSTATUS_1_w" newline bitfld.long 0x08 8. "WAIT0EDGEDETECTIONSTATUS,Status of the Wait0 Edge Detection interrupt" "WAIT0EDGEDETECTIONSTATUS_0_w,WAIT0EDGEDETECTIONSTATUS_1_w" newline bitfld.long 0x08 2.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 1. "TERMINALCOUNTSTATUS,Status of the TerminalCountEvent interrupt" "TERMINALCOUNTSTATUS_0_w,TERMINALCOUNTSTATUS_1_w" newline bitfld.long 0x08 0. "FIFOEVENTSTATUS,Status of the FIFOEvent interrupt" "FIFOEVENTSTATUS_0_w,FIFOEVENTSTATUS_1_w" line.long 0x0C "GPMC_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x0C 9. "WAIT1EDGEDETECTIONENABLE,Enables the Wait1 Edge Detection interrupt" "WAIT1EDGEDETECTIONENABLE_0,WAIT1EDGEDETECTIONENABLE_1" newline bitfld.long 0x0C 8. "WAIT0EDGEDETECTIONENABLE,Enables the Wait0 Edge Detection interrupt" "WAIT0EDGEDETECTIONENABLE_0,WAIT0EDGEDETECTIONENABLE_1" newline bitfld.long 0x0C 2.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 1. "TERMINALCOUNTEVENTENABLE,Enables TerminalCountEvent interrupt issuing in prefetch or write-posting mode" "TERMINALCOUNTEVENTENABLE_0,TERMINALCOUNTEVENTENABLE_1" newline bitfld.long 0x0C 0. "FIFOEVENTENABLE,Enables the FIFOEvent interrupt" "FIFOEVENTENABLE_0,FIFOEVENTENABLE_1" group.long 0x40++0x0B line.long 0x00 "GPMC_TIMEOUT_CONTROL,The register allows the user to set the start value of the timeout counter" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Write 0s for future compatibility" newline abitfld.long 0x00 4.--12. "TIMEOUTSTARTVALUE,Start value of the time-out counter" "0x000=Zero GPMC_FCLK cycle,0x001=One GPMC_FCLK cycle,0x1FF=511 GPMC_FCLK cycles" newline bitfld.long 0x00 1.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0. "TIMEOUTENABLE,Enable bit of the TimeOut feature" "TIMEOUTENABLE_0,TIMEOUTENABLE_1" line.long 0x04 "GPMC_ERR_ADDRESS,The register stores the address of the illegal access when an error occurs" bitfld.long 0x04 31. "RESERVED,Write 0s for future compatibility" "0,1" newline hexmask.long 0x04 0.--30. 1. "ILLEGALADD,Address of illegal access A30: 0 for memory region 1 for GPMC register region A29-A0: 1 GiB maximum" line.long 0x08 "GPMC_ERR_TYPE,The register stores the type of error when an error occurs" hexmask.long.tbyte 0x08 11.--31. 1. "RESERVED,Write 0s for future compatibility" newline rbitfld.long 0x08 8.--10. "ILLEGALMCMD,System command of the transaction that caused the error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 4. "ERRORNOTSUPPADD,Not supported address error" "ERRORNOTSUPPADD_0,ERRORNOTSUPPADD_1" newline rbitfld.long 0x08 3. "ERRORNOTSUPPMCMD,Not supported command error" "ERRORNOTSUPPMCMD_0,ERRORNOTSUPPMCMD_1" newline rbitfld.long 0x08 2. "ERRORTIMEOUT,Time-out error" "ERRORTIMEOUT_0,ERRORTIMEOUT_1" newline bitfld.long 0x08 1. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x08 0. "ERRORVALID,Error validity status - Must be explicitly cleared with a write 1 transaction" "ERRORVALID_0,ERRORVALID_1" group.long 0x50++0x07 line.long 0x00 "GPMC_CONFIG,The configuration register allows global configuration of the GPMC" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 9. "WAIT1PINPOLARITY,Selects the polarity of input pin WAIT1" "WAIT1PINPOLARITY_0,WAIT1PINPOLARITY_1" newline bitfld.long 0x00 8. "WAIT0PINPOLARITY,Selects the polarity of input pin WAIT0" "WAIT0PINPOLARITY_0,WAIT0PINPOLARITY_1" newline bitfld.long 0x00 2.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 1. "RESERVED,Write 0 for future compatibility" "0,1" newline bitfld.long 0x00 0. "NANDFORCEPOSTEDWRITE,Enables the Force Posted Write feature to NAND Cmd/Add/Data location" "NANDFORCEPOSTEDWRITE_0,NANDFORCEPOSTEDWRITE_1" line.long 0x04 "GPMC_STATUS,The status register provides global status bits of the GPMC" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Write 0s for future compatibility" newline rbitfld.long 0x04 9. "WAIT1STATUS,Is a copy of input pin WAIT1" "WAIT1STATUS_0,WAIT1STATUS_1" newline rbitfld.long 0x04 8. "WAIT0STATUS,Is a copy of input pin WAIT0" "WAIT0STATUS_0,WAIT0STATUS_1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED,Write 0s for future compatibility" newline rbitfld.long 0x04 0. "EMPTYWRITEBUFFERSTATUS,Stores the empty status of the write buffer" "EMPTYWRITEBUFFERSTATUS_0,EMPTYWRITEBUFFERSTATUS_1" group.long 0x60++0x03 line.long 0x00 "GPMC_CONFIG1_i_0,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" newline bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" newline bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" newline bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" newline bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" newline bitfld.long 0x00 20. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2 " "WAITPINSELECT_0,WAITPINSELECT_1,?,?" newline bitfld.long 0x00 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" newline bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" newline bitfld.long 0x00 2.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" group.long 0x90++0x03 line.long 0x00 "GPMC_CONFIG1_i_1,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" newline bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" newline bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" newline bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" newline bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" newline bitfld.long 0x00 20. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2 " "WAITPINSELECT_0,WAITPINSELECT_1,?,?" newline bitfld.long 0x00 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" newline bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" newline bitfld.long 0x00 2.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" group.long 0xC0++0x03 line.long 0x00 "GPMC_CONFIG1_i_2,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" newline bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" newline bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" newline bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" newline bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" newline bitfld.long 0x00 20. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2 " "WAITPINSELECT_0,WAITPINSELECT_1,?,?" newline bitfld.long 0x00 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" newline bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" newline bitfld.long 0x00 2.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" group.long 0xF0++0x03 line.long 0x00 "GPMC_CONFIG1_i_3,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" newline bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" newline bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" newline bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" newline bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" newline bitfld.long 0x00 20. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2 " "WAITPINSELECT_0,WAITPINSELECT_1,?,?" newline bitfld.long 0x00 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" newline bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" newline bitfld.long 0x00 2.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" group.long 0x120++0x03 line.long 0x00 "GPMC_CONFIG1_i_4,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" newline bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" newline bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" newline bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" newline bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" newline bitfld.long 0x00 20. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2 " "WAITPINSELECT_0,WAITPINSELECT_1,?,?" newline bitfld.long 0x00 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" newline bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" newline bitfld.long 0x00 2.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" group.long 0x150++0x03 line.long 0x00 "GPMC_CONFIG1_i_5,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" newline bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" newline bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" newline bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" newline bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" newline bitfld.long 0x00 20. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2 " "WAITPINSELECT_0,WAITPINSELECT_1,?,?" newline bitfld.long 0x00 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" newline bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" newline bitfld.long 0x00 2.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" group.long 0x180++0x03 line.long 0x00 "GPMC_CONFIG1_i_6,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" newline bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" newline bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" newline bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" newline bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" newline bitfld.long 0x00 20. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2 " "WAITPINSELECT_0,WAITPINSELECT_1,?,?" newline bitfld.long 0x00 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" newline bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" newline bitfld.long 0x00 2.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" group.long 0x1B0++0x03 line.long 0x00 "GPMC_CONFIG1_i_7,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" newline bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" newline bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" newline bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" newline bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" newline bitfld.long 0x00 20. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2 " "WAITPINSELECT_0,WAITPINSELECT_1,?,?" newline bitfld.long 0x00 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" newline bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" newline bitfld.long 0x00 2.--3. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" group.long 0x64++0x03 line.long 0x00 "GPMC_CONFIG2_i_0,CS signal timing parameter configuration" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x94++0x03 line.long 0x00 "GPMC_CONFIG2_i_1,CS signal timing parameter configuration" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0xC4++0x03 line.long 0x00 "GPMC_CONFIG2_i_2,CS signal timing parameter configuration" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0xF4++0x03 line.long 0x00 "GPMC_CONFIG2_i_3,CS signal timing parameter configuration" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x124++0x03 line.long 0x00 "GPMC_CONFIG2_i_4,CS signal timing parameter configuration" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x154++0x03 line.long 0x00 "GPMC_CONFIG2_i_5,CS signal timing parameter configuration" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x184++0x03 line.long 0x00 "GPMC_CONFIG2_i_6,CS signal timing parameter configuration" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x1B4++0x03 line.long 0x00 "GPMC_CONFIG2_i_7,CS signal timing parameter configuration" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x68++0x03 line.long 0x00 "GPMC_CONFIG3_i_0,nADV signal timing parameter configuration" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x98++0x03 line.long 0x00 "GPMC_CONFIG3_i_1,nADV signal timing parameter configuration" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0xC8++0x03 line.long 0x00 "GPMC_CONFIG3_i_2,nADV signal timing parameter configuration" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0xF8++0x03 line.long 0x00 "GPMC_CONFIG3_i_3,nADV signal timing parameter configuration" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x128++0x03 line.long 0x00 "GPMC_CONFIG3_i_4,nADV signal timing parameter configuration" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x158++0x03 line.long 0x00 "GPMC_CONFIG3_i_5,nADV signal timing parameter configuration" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x188++0x03 line.long 0x00 "GPMC_CONFIG3_i_6,nADV signal timing parameter configuration" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x1B8++0x03 line.long 0x00 "GPMC_CONFIG3_i_7,nADV signal timing parameter configuration" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x6C++0x03 line.long 0x00 "GPMC_CONFIG4_i_0,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 29.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x9C++0x03 line.long 0x00 "GPMC_CONFIG4_i_1,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 29.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0xCC++0x03 line.long 0x00 "GPMC_CONFIG4_i_2,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 29.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0xFC++0x03 line.long 0x00 "GPMC_CONFIG4_i_3,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 29.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x12C++0x03 line.long 0x00 "GPMC_CONFIG4_i_4,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 29.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x15C++0x03 line.long 0x00 "GPMC_CONFIG4_i_5,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 29.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x18C++0x03 line.long 0x00 "GPMC_CONFIG4_i_6,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 29.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x1BC++0x03 line.long 0x00 "GPMC_CONFIG4_i_7,nWE and nOE signals timing parameter configuration" bitfld.long 0x00 29.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x00 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x70++0x03 line.long 0x00 "GPMC_CONFIG5_i_0,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" group.long 0xA0++0x03 line.long 0x00 "GPMC_CONFIG5_i_1,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" group.long 0xD0++0x03 line.long 0x00 "GPMC_CONFIG5_i_2,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" group.long 0x100++0x03 line.long 0x00 "GPMC_CONFIG5_i_3,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" group.long 0x130++0x03 line.long 0x00 "GPMC_CONFIG5_i_4,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" group.long 0x160++0x03 line.long 0x00 "GPMC_CONFIG5_i_5,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" group.long 0x190++0x03 line.long 0x00 "GPMC_CONFIG5_i_6,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" group.long 0x1C0++0x03 line.long 0x00 "GPMC_CONFIG5_i_7,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x00 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 21.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 13.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 5.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" group.long 0x74++0x03 line.long 0x00 "GPMC_CONFIG6_i_0,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x00 29.--30. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 20.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x00 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" newline bitfld.long 0x00 4.--5. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0xA4++0x03 line.long 0x00 "GPMC_CONFIG6_i_1,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x00 29.--30. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 20.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x00 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" newline bitfld.long 0x00 4.--5. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0xD4++0x03 line.long 0x00 "GPMC_CONFIG6_i_2,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x00 29.--30. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 20.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x00 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" newline bitfld.long 0x00 4.--5. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x104++0x03 line.long 0x00 "GPMC_CONFIG6_i_3,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x00 29.--30. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 20.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x00 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" newline bitfld.long 0x00 4.--5. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x134++0x03 line.long 0x00 "GPMC_CONFIG6_i_4,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x00 29.--30. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 20.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x00 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" newline bitfld.long 0x00 4.--5. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x164++0x03 line.long 0x00 "GPMC_CONFIG6_i_5,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x00 29.--30. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 20.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x00 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" newline bitfld.long 0x00 4.--5. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x194++0x03 line.long 0x00 "GPMC_CONFIG6_i_6,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x00 29.--30. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 20.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x00 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" newline bitfld.long 0x00 4.--5. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x1C4++0x03 line.long 0x00 "GPMC_CONFIG6_i_7,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x00 31. "RESERVED,TI Internal use - Do not modify" "0,1" newline bitfld.long 0x00 29.--30. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x00 20.--23. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" newline bitfld.long 0x00 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x00 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" newline bitfld.long 0x00 4.--5. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x00 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" group.long 0x78++0x03 line.long 0x00 "GPMC_CONFIG7_i_0,CS address mapping configuration" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x00 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "GPMC_CONFIG7_i_1,CS address mapping configuration" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x00 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD8++0x03 line.long 0x00 "GPMC_CONFIG7_i_2,CS address mapping configuration" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x00 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x108++0x03 line.long 0x00 "GPMC_CONFIG7_i_3,CS address mapping configuration" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x00 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x138++0x03 line.long 0x00 "GPMC_CONFIG7_i_4,CS address mapping configuration" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x00 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x168++0x03 line.long 0x00 "GPMC_CONFIG7_i_5,CS address mapping configuration" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x00 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x198++0x03 line.long 0x00 "GPMC_CONFIG7_i_6,CS address mapping configuration" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x00 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C8++0x03 line.long 0x00 "GPMC_CONFIG7_i_7,CS address mapping configuration" hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x00 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x7C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_0,This register is not a true register. only an address location" group.long 0xAC++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_1,This register is not a true register. only an address location" group.long 0xDC++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_2,This register is not a true register. only an address location" group.long 0x10C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_3,This register is not a true register. only an address location" group.long 0x13C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_4,This register is not a true register. only an address location" group.long 0x16C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_5,This register is not a true register. only an address location" group.long 0x19C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_6,This register is not a true register. only an address location" group.long 0x1CC++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_7,This register is not a true register. only an address location" group.long 0x80++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_0,This register is not a true register. only an address location" group.long 0xB0++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_1,This register is not a true register. only an address location" group.long 0xE0++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_2,This register is not a true register. only an address location" group.long 0x110++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_3,This register is not a true register. only an address location" group.long 0x140++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_4,This register is not a true register. only an address location" group.long 0x170++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_5,This register is not a true register. only an address location" group.long 0x1A0++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_6,This register is not a true register. only an address location" group.long 0x1D0++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_7,This register is not a true register. only an address location" group.long 0x84++0x03 line.long 0x00 "GPMC_NAND_DATA_i_0,This register is not a true register.only an address location" group.long 0xB4++0x03 line.long 0x00 "GPMC_NAND_DATA_i_1,This register is not a true register.only an address location" group.long 0xE4++0x03 line.long 0x00 "GPMC_NAND_DATA_i_2,This register is not a true register.only an address location" group.long 0x114++0x03 line.long 0x00 "GPMC_NAND_DATA_i_3,This register is not a true register.only an address location" group.long 0x144++0x03 line.long 0x00 "GPMC_NAND_DATA_i_4,This register is not a true register.only an address location" group.long 0x174++0x03 line.long 0x00 "GPMC_NAND_DATA_i_5,This register is not a true register.only an address location" group.long 0x1A4++0x03 line.long 0x00 "GPMC_NAND_DATA_i_6,This register is not a true register.only an address location" group.long 0x1D4++0x03 line.long 0x00 "GPMC_NAND_DATA_i_7,This register is not a true register.only an address location" group.long 0x1E0++0x07 line.long 0x00 "GPMC_PREFETCH_CONFIG1,Prefetch engine configuration 1" bitfld.long 0x00 31. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 28.--30. "CYCLEOPTIMIZATION,Define the number of GPMC_FCLK cycles to be subtracted from RDCYCLETIME WRCYCLETIME RDACCESSTIME CSRDOFFTIME CSWROFFTIME ADVRDOFFTIME ADVWROFFTIME OEOFFTIME WEOFFTIME" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "ENABLEOPTIMIZEDACCESS,Enables access cycle optimization" "ENABLEOPTIMIZEDACCESS_0,ENABLEOPTIMIZEDACCESS_1" newline bitfld.long 0x00 24.--26. "ENGINECSSELECTOR,Selects the chip-select where Prefetch Postwrite engine is active" "CS0,CS1,CS2,CS3,CS4,CS5,CS6,CS7" newline bitfld.long 0x00 23. "PFPWENROUNDROBIN,Enables the PFPW RoundRobin arbitration" "PFPWENROUNDROBIN_0,PFPWENROUNDROBIN_1" newline bitfld.long 0x00 20.--22. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "PFPWWEIGHTEDPRIO,When an arbitration occurs between a DMA and a PFPW engine access the DMA is always serviced" "The next access is granted to the PFPW engine,The next two accesses are granted to the PFPW..,?,?,?,?,?,?,?,?,?,?,?,?,?,The next 16 accesses are granted to the PFPW.." newline bitfld.long 0x00 15. "RESERVED,Write 0s for future compatibility" "0,1" newline abitfld.long 0x00 8.--14. "FIFOTHRESHOLD,Selects the maximum number of bytes read from the FIFO or written to the FIFO by the host on a DMA or interrupt request" "0x00=0 byte,0x01=1 byte,0x40=64 bytes" newline bitfld.long 0x00 7. "ENABLEENGINE,Enables the Prefetch Postwite engine" "ENABLEENGINE_0,ENABLEENGINE_1" newline bitfld.long 0x00 6. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 4.--5. "WAITPINSELECTOR,Select which wait pin edge detector should start the engine in synchronized mode0x2 " "WAITPINSELECTOR_0,WAITPINSELECTOR_1,?,?" newline bitfld.long 0x00 3. "SYNCHROMODE,Selects when the engine starts the access to chip-select" "SYNCHROMODE_0,SYNCHROMODE_1" newline bitfld.long 0x00 2. "DMAMODE,Selects interrupt synchronization or DMA request synchronization" "DMAMODE_0,DMAMODE_1" newline bitfld.long 0x00 1. "RESERVED,Write 0s for future compatibility" "0,1" newline bitfld.long 0x00 0. "ACCESSMODE,Selects prefetch read or write-posting accesses" "ACCESSMODE_0,ACCESSMODE_1" line.long 0x04 "GPMC_PREFETCH_CONFIG2,Prefetch engine configuration 2" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Write 0s for future compatibility" newline abitfld.long 0x04 0.--13. "TRANSFERCOUNT,Selects the number of bytes to be read or written by the engine to the selected chip-select" "0x0000=0 byte,0x0001=1 byte,0x2000=8 Kbytes" group.long 0x1EC++0x37 line.long 0x00 "GPMC_PREFETCH_CONTROL,Prefetch engine control" hexmask.long 0x00 1.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x00 0. "STARTENGINE,Resets the FIFO pointer and starts the engine" "STARTENGINE_0_w,STARTENGINE_1_w" line.long 0x04 "GPMC_PREFETCH_STATUS,Prefetch engine status" bitfld.long 0x04 31. "RESERVED,Write 0s for future compatibility" "0,1" newline abitfld.long 0x04 24.--30. "FIFOPOINTER,Number of available bytes to be read or number of free empty byte places to be written" "0x00=0 byte available to be read or 0 free empty..,0x40=64 bytes available to be read or 64 empty.." newline hexmask.long.byte 0x04 17.--23. 1. "RESERVED,Write 0s for future compatibility" newline rbitfld.long 0x04 16. "FIFOTHRESHOLDSTATUS,Set when FIFOPointer exceeds FIFOThreshold value" "FIFOTHRESHOLDSTATUS_0,FIFOTHRESHOLDSTATUS_1" newline bitfld.long 0x04 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline abitfld.long 0x04 0.--13. "COUNTVALUE,Number of remaining bytes to be read or to be written by the engine according to the TransferCount value" "0x0000=0 byte remaining to be read or to be..,0x0001=1 byte remaining to be read or to be..,0x2000=8 KiB remaining to be read or to be written" line.long 0x08 "GPMC_ECC_CONFIG,ECC configuration" hexmask.long.word 0x08 17.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x08 16. "ECCALGORITHM,ECC algorithm used" "ECCALGORITHM_0,ECCALGORITHM_1" newline bitfld.long 0x08 14.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline bitfld.long 0x08 12.--13. "ECCBCHTSEL,Error correction capability used for BCH" "ECCBCHTSEL_0,ECCBCHTSEL_1,ECCBCHTSEL_2,ECCBCHTSEL_3" newline bitfld.long 0x08 8.--11. "ECCWRAPMODE,Spare area organization definition for the BCH algorithm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 7. "ECC16B,Selects an ECC calculated on 16 columns" "ECC16B_0,ECC16B_1" newline bitfld.long 0x08 4.--6. "ECCTOPSECTOR,Number of sectors to process with the BCH algorithm" "1 sector (512-kB page),2 sectors,?,4 sectors (2-kB page),?,?,?,8 sectors (4-kB page)" newline bitfld.long 0x08 1.--3. "ECCCS,Selects the CS where ECC is" "ECCCS_0,ECCCS_1,ECCCS_2,ECCCS_3,?,?,?,?" newline bitfld.long 0x08 0. "ECCENABLE,Enables the ECC feature" "ECCENABLE_0,ECCENABLE_1" line.long 0x0C "GPMC_ECC_CONTROL,ECC control" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED,Write 0s for future compatibility" newline bitfld.long 0x0C 8. "ECCCLEAR,Clear all ECC result registers Reads return 0" "0,1" newline bitfld.long 0x0C 4.--7. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. "ECCPOINTER,Selects ECC result register (Reads to this field give the dynamic position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored.); Other enums: writing other values disables.." "ECCPOINTER_0,ECCPOINTER_1,ECCPOINTER_2,ECCPOINTER_3,ECCPOINTER_4,ECCPOINTER_5,ECCPOINTER_6,ECCPOINTER_7,ECCPOINTER_8,ECCPOINTER_9,?,?,?,?,?,?" line.long 0x10 "GPMC_ECC_SIZE_CONFIG,ECC size" bitfld.long 0x10 30.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline abitfld.long 0x10 22.--29. "ECCSIZE1,Defines Hamming code ECC size 1 in bytes" "0x00=2 bytes,0x01=4 bytes,0x02=6 bytes,0x03=8 bytes,0xFF=512 bytes For BCH.." newline bitfld.long 0x10 20.--21. "RESERVED,Write 0s for future compatibility" "0,1,2,3" newline abitfld.long 0x10 12.--19. "ECCSIZE0,Defines Hamming code ECC size 0 in bytes" "0x00=2 bytes,0x01=4 bytes,0x02=6 bytes,0x03=8 bytes,0xFF=512 bytes For BCH.." newline bitfld.long 0x10 9.--11. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "ECC9RESULTSIZE,Selects ECC size for ECC 9 result register" "ECC9RESULTSIZE_0,ECC9RESULTSIZE_1" newline bitfld.long 0x10 7. "ECC8RESULTSIZE,Selects ECC size for ECC 8 result register" "ECC8RESULTSIZE_0,ECC8RESULTSIZE_1" newline bitfld.long 0x10 6. "ECC7RESULTSIZE,Selects ECC size for ECC 7 result register" "ECC7RESULTSIZE_0,ECC7RESULTSIZE_1" newline bitfld.long 0x10 5. "ECC6RESULTSIZE,Selects ECC size for ECC 6 result register" "ECC6RESULTSIZE_0,ECC6RESULTSIZE_1" newline bitfld.long 0x10 4. "ECC5RESULTSIZE,Selects ECC size for ECC 5 result register" "ECC5RESULTSIZE_0,ECC5RESULTSIZE_1" newline bitfld.long 0x10 3. "ECC4RESULTSIZE,Selects ECC size for ECC 4 result register" "ECC4RESULTSIZE_0,ECC4RESULTSIZE_1" newline bitfld.long 0x10 2. "ECC3RESULTSIZE,Selects ECC size for ECC 3 result register" "ECC3RESULTSIZE_0,ECC3RESULTSIZE_1" newline bitfld.long 0x10 1. "ECC2RESULTSIZE,Selects ECC size for ECC 2 result register" "ECC2RESULTSIZE_0,ECC2RESULTSIZE_1" newline bitfld.long 0x10 0. "ECC1RESULTSIZE,Selects ECC size for ECC 1 result register" "ECC1RESULTSIZE_0,ECC1RESULTSIZE_1" line.long 0x14 "GPMC_ECCj_RESULT_0,ECC result register" bitfld.long 0x14 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x14 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x14 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x14 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x14 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x14 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x14 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x14 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x14 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x14 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x14 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x14 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x14 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x14 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x14 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x14 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x14 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x14 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x14 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x14 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x14 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x14 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x14 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x14 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x14 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x14 0. "P1E,Even column parity bit 1" "0,1" line.long 0x18 "GPMC_ECCj_RESULT_1,ECC result register" bitfld.long 0x18 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x18 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x18 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x18 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x18 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x18 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x18 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x18 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x18 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x18 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x18 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x18 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x18 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x18 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x18 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x18 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x18 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x18 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x18 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x18 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x18 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x18 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x18 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x18 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x18 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x18 0. "P1E,Even column parity bit 1" "0,1" line.long 0x1C "GPMC_ECCj_RESULT_2,ECC result register" bitfld.long 0x1C 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x1C 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x1C 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x1C 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x1C 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x1C 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x1C 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x1C 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x1C 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x1C 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x1C 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x1C 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x1C 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x1C 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x1C 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x1C 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x1C 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x1C 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x1C 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x1C 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x1C 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x1C 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x1C 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x1C 0. "P1E,Even column parity bit 1" "0,1" line.long 0x20 "GPMC_ECCj_RESULT_3,ECC result register" bitfld.long 0x20 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x20 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x20 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x20 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x20 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x20 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x20 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x20 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x20 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x20 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x20 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x20 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x20 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x20 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x20 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x20 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x20 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x20 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x20 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x20 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x20 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x20 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x20 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x20 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x20 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x20 0. "P1E,Even column parity bit 1" "0,1" line.long 0x24 "GPMC_ECCj_RESULT_4,ECC result register" bitfld.long 0x24 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x24 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x24 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x24 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x24 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x24 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x24 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x24 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x24 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x24 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x24 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x24 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x24 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x24 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x24 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x24 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x24 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x24 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x24 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x24 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x24 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x24 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x24 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x24 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x24 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x24 0. "P1E,Even column parity bit 1" "0,1" line.long 0x28 "GPMC_ECCj_RESULT_5,ECC result register" bitfld.long 0x28 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x28 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x28 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x28 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x28 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x28 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x28 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x28 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x28 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x28 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x28 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x28 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x28 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x28 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x28 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x28 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x28 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x28 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x28 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x28 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x28 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x28 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x28 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x28 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x28 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x28 0. "P1E,Even column parity bit 1" "0,1" line.long 0x2C "GPMC_ECCj_RESULT_6,ECC result register" bitfld.long 0x2C 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x2C 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x2C 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x2C 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x2C 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x2C 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x2C 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x2C 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x2C 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x2C 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x2C 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x2C 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x2C 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x2C 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x2C 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x2C 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x2C 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x2C 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x2C 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x2C 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x2C 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x2C 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x2C 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x2C 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x2C 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x2C 0. "P1E,Even column parity bit 1" "0,1" line.long 0x30 "GPMC_ECCj_RESULT_7,ECC result register" bitfld.long 0x30 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x30 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x30 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x30 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x30 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x30 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x30 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x30 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x30 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x30 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x30 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x30 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x30 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x30 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x30 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x30 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x30 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x30 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x30 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x30 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x30 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x30 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x30 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x30 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x30 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x30 0. "P1E,Even column parity bit 1" "0,1" line.long 0x34 "GPMC_ECCj_RESULT_8,ECC result register" bitfld.long 0x34 28.--31. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x34 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x34 26. "P1024O,Odd row parity bit 1024" "0,1" newline rbitfld.long 0x34 25. "P512O,Odd row parity bit 512" "0,1" newline rbitfld.long 0x34 24. "P256O,Odd row parity bit 256" "0,1" newline rbitfld.long 0x34 23. "P128O,Odd row parity bit 128" "0,1" newline rbitfld.long 0x34 22. "P64O,Odd row parity bit 64" "0,1" newline rbitfld.long 0x34 21. "P32O,Odd row parity bit 32" "0,1" newline rbitfld.long 0x34 20. "P16O,Odd row parity bit 16" "0,1" newline rbitfld.long 0x34 19. "P8O,Odd row parity bit 8" "0,1" newline rbitfld.long 0x34 18. "P4O,Odd Column Parity bit 4" "0,1" newline rbitfld.long 0x34 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x34 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x34 12.--15. "RESERVED,Write 0s for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x34 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline rbitfld.long 0x34 10. "P1024E,Even row parity bit 1024" "0,1" newline rbitfld.long 0x34 9. "P512E,Even row parity bit 512" "0,1" newline rbitfld.long 0x34 8. "P256E,Even row parity bit 256" "0,1" newline rbitfld.long 0x34 7. "P128E,Even row parity bit 128" "0,1" newline rbitfld.long 0x34 6. "P64E,Even row parity bit 64" "0,1" newline rbitfld.long 0x34 5. "P32E,Even row parity bit 32" "0,1" newline rbitfld.long 0x34 4. "P16E,Even row parity bit 16" "0,1" newline rbitfld.long 0x34 3. "P8E,Even row parity bit 8" "0,1" newline rbitfld.long 0x34 2. "P4E,Even column parity bit 4" "0,1" newline rbitfld.long 0x34 1. "P2E,Even column parity bit 2" "0,1" newline rbitfld.long 0x34 0. "P1E,Even column parity bit 1" "0,1" group.long 0x240++0x03 line.long 0x00 "GPMC_BCH_RESULT0_i_0,BCH ECC result (bits 0 to 31)" group.long 0x250++0x03 line.long 0x00 "GPMC_BCH_RESULT0_i_1,BCH ECC result (bits 0 to 31)" group.long 0x260++0x03 line.long 0x00 "GPMC_BCH_RESULT0_i_2,BCH ECC result (bits 0 to 31)" group.long 0x270++0x03 line.long 0x00 "GPMC_BCH_RESULT0_i_3,BCH ECC result (bits 0 to 31)" group.long 0x280++0x03 line.long 0x00 "GPMC_BCH_RESULT0_i_4,BCH ECC result (bits 0 to 31)" group.long 0x290++0x03 line.long 0x00 "GPMC_BCH_RESULT0_i_5,BCH ECC result (bits 0 to 31)" group.long 0x2A0++0x03 line.long 0x00 "GPMC_BCH_RESULT0_i_6,BCH ECC result (bits 0 to 31)" group.long 0x2B0++0x03 line.long 0x00 "GPMC_BCH_RESULT0_i_7,BCH ECC result (bits 0 to 31)" group.long 0x244++0x03 line.long 0x00 "GPMC_BCH_RESULT1_i_0,BCH ECC result (bits 32 to 63)" group.long 0x254++0x03 line.long 0x00 "GPMC_BCH_RESULT1_i_1,BCH ECC result (bits 32 to 63)" group.long 0x264++0x03 line.long 0x00 "GPMC_BCH_RESULT1_i_2,BCH ECC result (bits 32 to 63)" group.long 0x274++0x03 line.long 0x00 "GPMC_BCH_RESULT1_i_3,BCH ECC result (bits 32 to 63)" group.long 0x284++0x03 line.long 0x00 "GPMC_BCH_RESULT1_i_4,BCH ECC result (bits 32 to 63)" group.long 0x294++0x03 line.long 0x00 "GPMC_BCH_RESULT1_i_5,BCH ECC result (bits 32 to 63)" group.long 0x2A4++0x03 line.long 0x00 "GPMC_BCH_RESULT1_i_6,BCH ECC result (bits 32 to 63)" group.long 0x2B4++0x03 line.long 0x00 "GPMC_BCH_RESULT1_i_7,BCH ECC result (bits 32 to 63)" group.long 0x248++0x03 line.long 0x00 "GPMC_BCH_RESULT2_i_0,BCH ECC result (bits 64 to 95)" group.long 0x258++0x03 line.long 0x00 "GPMC_BCH_RESULT2_i_1,BCH ECC result (bits 64 to 95)" group.long 0x268++0x03 line.long 0x00 "GPMC_BCH_RESULT2_i_2,BCH ECC result (bits 64 to 95)" group.long 0x278++0x03 line.long 0x00 "GPMC_BCH_RESULT2_i_3,BCH ECC result (bits 64 to 95)" group.long 0x288++0x03 line.long 0x00 "GPMC_BCH_RESULT2_i_4,BCH ECC result (bits 64 to 95)" group.long 0x298++0x03 line.long 0x00 "GPMC_BCH_RESULT2_i_5,BCH ECC result (bits 64 to 95)" group.long 0x2A8++0x03 line.long 0x00 "GPMC_BCH_RESULT2_i_6,BCH ECC result (bits 64 to 95)" group.long 0x2B8++0x03 line.long 0x00 "GPMC_BCH_RESULT2_i_7,BCH ECC result (bits 64 to 95)" group.long 0x24C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_i_0,BCH ECC result (bits 96 to 127)" group.long 0x25C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_i_1,BCH ECC result (bits 96 to 127)" group.long 0x26C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_i_2,BCH ECC result (bits 96 to 127)" group.long 0x27C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_i_3,BCH ECC result (bits 96 to 127)" group.long 0x28C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_i_4,BCH ECC result (bits 96 to 127)" group.long 0x29C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_i_5,BCH ECC result (bits 96 to 127)" group.long 0x2AC++0x03 line.long 0x00 "GPMC_BCH_RESULT3_i_6,BCH ECC result (bits 96 to 127)" group.long 0x2BC++0x03 line.long 0x00 "GPMC_BCH_RESULT3_i_7,BCH ECC result (bits 96 to 127)" group.long 0x2D0++0x03 line.long 0x00 "GPMC_BCH_SWDATA,This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND flash interface" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_DATA,Data to be included in the BCH calculation Only bits 0 to 7 are considered if the calculator is configured to use 8-bit data (GPMC_ECC_CONFIG[7] ECC16B = 0)" group.long 0x300++0x03 line.long 0x00 "GPMC_BCH_RESULT4_i_0,BCH ECC result (bits 128 to 159)" group.long 0x310++0x03 line.long 0x00 "GPMC_BCH_RESULT4_i_1,BCH ECC result (bits 128 to 159)" group.long 0x320++0x03 line.long 0x00 "GPMC_BCH_RESULT4_i_2,BCH ECC result (bits 128 to 159)" group.long 0x330++0x03 line.long 0x00 "GPMC_BCH_RESULT4_i_3,BCH ECC result (bits 128 to 159)" group.long 0x340++0x03 line.long 0x00 "GPMC_BCH_RESULT4_i_4,BCH ECC result (bits 128 to 159)" group.long 0x350++0x03 line.long 0x00 "GPMC_BCH_RESULT4_i_5,BCH ECC result (bits 128 to 159)" group.long 0x360++0x03 line.long 0x00 "GPMC_BCH_RESULT4_i_6,BCH ECC result (bits 128 to 159)" group.long 0x370++0x03 line.long 0x00 "GPMC_BCH_RESULT4_i_7,BCH ECC result (bits 128 to 159)" group.long 0x304++0x03 line.long 0x00 "GPMC_BCH_RESULT5_i_0,BCH ECC result (bits 160 to 191)" group.long 0x314++0x03 line.long 0x00 "GPMC_BCH_RESULT5_i_1,BCH ECC result (bits 160 to 191)" group.long 0x324++0x03 line.long 0x00 "GPMC_BCH_RESULT5_i_2,BCH ECC result (bits 160 to 191)" group.long 0x334++0x03 line.long 0x00 "GPMC_BCH_RESULT5_i_3,BCH ECC result (bits 160 to 191)" group.long 0x344++0x03 line.long 0x00 "GPMC_BCH_RESULT5_i_4,BCH ECC result (bits 160 to 191)" group.long 0x354++0x03 line.long 0x00 "GPMC_BCH_RESULT5_i_5,BCH ECC result (bits 160 to 191)" group.long 0x364++0x03 line.long 0x00 "GPMC_BCH_RESULT5_i_6,BCH ECC result (bits 160 to 191)" group.long 0x374++0x03 line.long 0x00 "GPMC_BCH_RESULT5_i_7,BCH ECC result (bits 160 to 191)" group.long 0x308++0x03 line.long 0x00 "GPMC_BCH_RESULT6_i_0,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x318++0x03 line.long 0x00 "GPMC_BCH_RESULT6_i_1,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x328++0x03 line.long 0x00 "GPMC_BCH_RESULT6_i_2,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x338++0x03 line.long 0x00 "GPMC_BCH_RESULT6_i_3,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x348++0x03 line.long 0x00 "GPMC_BCH_RESULT6_i_4,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x358++0x03 line.long 0x00 "GPMC_BCH_RESULT6_i_5,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x368++0x03 line.long 0x00 "GPMC_BCH_RESULT6_i_6,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x378++0x03 line.long 0x00 "GPMC_BCH_RESULT6_i_7,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0s for future compatibility" newline hexmask.long.word 0x00 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" width 0x0B tree.end tree "GPMC_FW" base ad:0x4A210000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "GPMC_FW_CFG_TARG" base ad:0x4A211000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPMC_TARG" base ad:0x44000100 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "GPU_CM_CORE" base ad:0x4A009200 group.long 0x00++0x0B line.long 0x00 "CM_GPU_CLKSTCTRL,This register enables the GPU domain power state transition" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," rbitfld.long 0x00 10. "CLKACTIVITY_GPU_HYD_GCLK,This field indicates the state of the GPU_HYD_GCLK clock in the domain" "CLKACTIVITY_GPU_HYD_GCLK_0,CLKACTIVITY_GPU_HYD_GCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_GPU_CORE_GCLK,This field indicates the state of the GPU_CORE_GCLK clock in the domain" "CLKACTIVITY_GPU_CORE_GCLK_0,CLKACTIVITY_GPU_CORE_GCLK_1" rbitfld.long 0x00 8. "CLKACTIVITY_GPU_L3_GICLK,This field indicates the state of the GPU_L3_GICLK clock in the domain" "CLKACTIVITY_GPU_L3_GICLK_0,CLKACTIVITY_GPU_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the GPU clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_GPU_STATICDEP,This register controls the static domain depedencies from GPU domain towards 'target' domains" hexmask.long 0x04 6.--31. 1. "RESERVED," rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" line.long 0x08 "CM_GPU_DYNAMICDEP,This register controls the dynamic domain depedencies from GPU domain towards 'target' domains" hexmask.long 0x08 7.--31. 1. "RESERVED," bitfld.long 0x08 6. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "L3MAIN1_DYNDEP_0,?" newline bitfld.long 0x08 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x20++0x03 line.long 0x00 "CM_GPU_GPU_CLKCTRL,This register manages the GPU clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 26.--27. "CLKSEL_HYD_CLK,Select the source of the functional clock" "CLKSEL_HYD_CLK_0,CLKSEL_HYD_CLK_1,CLKSEL_HYD_CLK_2,CLKSEL_HYD_CLK_3" newline bitfld.long 0x00 24.--25. "CLKSEL_CORE_CLK,Select the source of the functional clock" "CLKSEL_CORE_CLK_0,CLKSEL_CORE_CLK_1,CLKSEL_CORE_CLK_2,CLKSEL_CORE_CLK_3" rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "GPU_PRM" base ad:0x4AE07200 group.long 0x00++0x07 line.long 0x00 "PM_GPU_PWRSTCTRL,This register controls the GPU power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "GPU_MEM_ONSTATE,GPU_MEM memory bank state when domain is ON" "?,?,?,GPU_MEM_ONSTATE_3" hexmask.long.word 0x00 5.--15. 1. "RESERVED," newline bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_GPU_PWRSTST,This register provides a status on the current GPU power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "GPU_MEM_STATEST,GPU_MEM memory bank state status" "GPU_MEM_STATEST_0,GPU_MEM_STATEST_1,GPU_MEM_STATEST_2,GPU_MEM_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_GPU_GPU_CONTEXT,This register contains dedicated GPU context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_GPU_MEM,Specify if memory-based context in GPU_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_GPU_MEM_0,LOSTMEM_GPU_MEM_1" hexmask.long.byte 0x00 1.--7. 1. "RESERVED," newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end repeat 2. (list 1. 2. )(list ad:0x48070000 ad:0x48072000 ) tree "I2C$1" base $2 rgroup.word 0x00++0x01 line.word 0x00 "I2C_REVNB_LO,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" rgroup.word 0x04++0x01 line.word 0x00 "I2C_REVNB_HI,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" group.word 0x10++0x01 line.word 0x00 "I2C_SYSC,System Configuration register" rbitfld.word 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits" "CLKACTIVITY_0,CLKACTIVITY_1,CLKACTIVITY_2,CLKACTIVITY_3" rbitfld.word 0x00 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 3.--4. "IDLEMODE,Idle Mode selection bits" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.word 0x00 2. "ENAWAKEUP,Enable Wakeup control bit" "ENAWAKEUP_0,ENAWAKEUP_1" bitfld.word 0x00 1. "SRST,SoftReset bit" "SRST_0,SRST_1" newline bitfld.word 0x00 0. "AUTOIDLE,Autoidle bit" "AUTOIDLE_0,AUTOIDLE_1" group.word 0x20++0x01 line.word 0x00 "I2C_EOI,End Of Interrupt number specification" hexmask.word 0x00 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0,1" group.word 0x24++0x01 line.word 0x00 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.word 0x00 15. "RESERVED,Write 0s for future compatibility" "0,1" bitfld.word 0x00 14. "XDR,Transmit draining IRQ status" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive draining IRQ status" "RDR_0,RDR_1" newline rbitfld.word 0x00 12. "BB,Bus busy status" "BB_0_r,BB_1_r" bitfld.word 0x00 11. "ROVR,Receive overrun status" "ROVR_0_r,ROVR_1_r" bitfld.word 0x00 10. "XUDF,Transmit underflow status" "XUDF_0_r,XUDF_1_r" newline bitfld.word 0x00 9. "AAS,Address recognized as slave IRQ status" "AAS_0,AAS_1" bitfld.word 0x00 8. "BF,Bus Free IRQ status" "BF_0,BF_1" bitfld.word 0x00 7. "AERR,Access Error IRQ status" "AERR_0,AERR_1" newline bitfld.word 0x00 6. "STC,Start Condition IRQ status" "STC_0,STC_1" bitfld.word 0x00 5. "GC,General call IRQ status" "GC_0,GC_1" bitfld.word 0x00 4. "XRDY,Transmit data ready IRQ status" "XRDY_0,XRDY_1" newline bitfld.word 0x00 3. "RRDY,Receive data ready IRQ status" "RRDY_0,RRDY_1" bitfld.word 0x00 2. "ARDY,Register access ready IRQ status" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgement IRQ status" "NACK_0,NACK_1" newline bitfld.word 0x00 0. "AL,Arbitration lost IRQ status" "AL_0,AL_1" group.word 0x28++0x01 line.word 0x00 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.word 0x00 15. "RESERVED,Write 0s for future compatibility" "0,1" bitfld.word 0x00 14. "XDR,Transmit draining IRQ enabled status" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive draining IRQ enabled status" "RDR_0,RDR_1" newline rbitfld.word 0x00 12. "BB,Bus busy enabled status" "BB_0_r,BB_1_r" bitfld.word 0x00 11. "ROVR,Receive overrun enabled status" "ROVR_0_r,ROVR_1_r" bitfld.word 0x00 10. "XUDF,Transmit underflow enabled status" "XUDF_0_r,XUDF_1_r" newline bitfld.word 0x00 9. "AAS,Address recognized as slave IRQ enabled status" "AAS_0,AAS_1" bitfld.word 0x00 8. "BF,Bus Free IRQ enabled status" "BF_0,BF_1" bitfld.word 0x00 7. "AERR,Access Error IRQ enabled status" "AERR_0,AERR_1" newline bitfld.word 0x00 6. "STC,Start Condition IRQ enabled status" "STC_0,STC_1" bitfld.word 0x00 5. "GC,General call IRQ enabled status" "GC_0,GC_1" bitfld.word 0x00 4. "XRDY,Transmit data ready IRQ enabled status" "XRDY_0,XRDY_1" newline bitfld.word 0x00 3. "RRDY,Receive data ready IRQ enabled status" "RRDY_0,RRDY_1" bitfld.word 0x00 2. "ARDY,Register access ready IRQ enabled status" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgement IRQ enabled status" "NACK_0,NACK_1" newline bitfld.word 0x00 0. "AL,Arbitration lost IRQ enabled status" "AL_0,AL_1" group.word 0x2C++0x01 line.word 0x00 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector" rbitfld.word 0x00 15. "RESERVED,Write 0s for future compatibility" "0,1" bitfld.word 0x00 14. "XDR_IE,Transmit Draining interrupt enable set" "XDR_IE_0,XDR_IE_1" bitfld.word 0x00 13. "RDR_IE,Receive Draining interrupt enable set" "RDR_IE_0,RDR_IE_1" newline rbitfld.word 0x00 12. "RESERVED,Reserved" "0,1" bitfld.word 0x00 11. "ROVR,Receive overrun enable set.Read: enum=disable" "ROVR_0,ROVR_1" bitfld.word 0x00 10. "XUDF,Transmit underflow enable set.Read: enum=disable" "XUDF_0,XUDF_1" newline bitfld.word 0x00 9. "AAS_IE,Addressed as Slave interrupt enable set" "AAS_IE_0,AAS_IE_1" bitfld.word 0x00 8. "BF_IE,Bus Free interrupt enable set" "BF_IE_0,BF_IE_1" bitfld.word 0x00 7. "AERR_IE,Access Error interrupt enable set" "AERR_IE_0,AERR_IE_1" newline bitfld.word 0x00 6. "STC_IE,Start Condition interrupt enable set" "STC_IE_0,STC_IE_1" bitfld.word 0x00 5. "GC_IE,General call Interrupt enable set" "GC_IE_0,GC_IE_1" bitfld.word 0x00 4. "XRDY_IE,Transmit data ready interrupt enable set" "XRDY_IE_0,XRDY_IE_1" newline bitfld.word 0x00 3. "RRDY_IE,Receive data ready interrupt enable set" "RRDY_IE_0,RRDY_IE_1" bitfld.word 0x00 2. "ARDY_IE,Register access ready interrupt enable set" "ARDY_IE_0,ARDY_IE_1" bitfld.word 0x00 1. "NACK_IE,No acknowledgement interrupt enable set" "NACK_IE_0,NACK_IE_1" newline bitfld.word 0x00 0. "AL_IE,Arbitration lost interrupt enable set" "AL_IE_0,AL_IE_1" group.word 0x30++0x01 line.word 0x00 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector" rbitfld.word 0x00 15. "RESERVED,Write 0s for future compatibility" "0,1" bitfld.word 0x00 14. "XDR_IE,Transmit Draining interrupt enable clear" "XDR_IE_0,XDR_IE_1" bitfld.word 0x00 13. "RDR_IE,Receive Draining interrupt enable clear" "RDR_IE_0,RDR_IE_1" newline rbitfld.word 0x00 12. "RESERVED,Reserved" "0,1" bitfld.word 0x00 11. "ROVR,Receive overrun enable clear.Read: enum=disable" "ROVR_0,ROVR_1" bitfld.word 0x00 10. "XUDF,Transmit underflow enable clear.Read: enum=disable" "XUDF_0,XUDF_1" newline bitfld.word 0x00 9. "AAS_IE,Addressed as Slave interrupt enable clear" "AAS_IE_0,AAS_IE_1" bitfld.word 0x00 8. "BF_IE,Bus Free interrupt enable clear" "BF_IE_0,BF_IE_1" bitfld.word 0x00 7. "AERR_IE,Access Error interrupt enable clear" "AERR_IE_0,AERR_IE_1" newline bitfld.word 0x00 6. "STC_IE,Start Condition interrupt enable clear" "STC_IE_0,STC_IE_1" bitfld.word 0x00 5. "GC_IE,General call Interrupt enable clear" "GC_IE_0,GC_IE_1" bitfld.word 0x00 4. "XRDY_IE,Transmit data ready interrupt enable clear" "XRDY_IE_0,XRDY_IE_1" newline bitfld.word 0x00 3. "RRDY_IE,Receive data ready interrupt enable clear" "RRDY_IE_0,RRDY_IE_1" bitfld.word 0x00 2. "ARDY_IE,Register access ready interrupt enable clear" "ARDY_IE_0,ARDY_IE_1" bitfld.word 0x00 1. "NACK_IE,No acknowledgement interrupt enable clear" "NACK_IE_0,NACK_IE_1" newline bitfld.word 0x00 0. "AL_IE,Arbitration lost interrupt enable clear" "AL_IE_0,AL_IE_1" group.word 0x34++0x01 line.word 0x00 "I2C_WE,I2C wakeup enable vector" rbitfld.word 0x00 15. "RESERVED,Reserved" "0,1" bitfld.word 0x00 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1" newline rbitfld.word 0x00 12. "RESERVED,Reserved" "0,1" bitfld.word 0x00 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1" bitfld.word 0x00 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1" newline bitfld.word 0x00 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1" bitfld.word 0x00 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1" rbitfld.word 0x00 7. "RESERVED,Reserved" "0,1" newline bitfld.word 0x00 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1" bitfld.word 0x00 5. "GC,General call IRQ wakeup set" "GC_0,GC_1" rbitfld.word 0x00 4. "RESERVED,Reserved" "0,1" newline bitfld.word 0x00 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1" bitfld.word 0x00 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1" newline bitfld.word 0x00 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1" group.word 0x38++0x01 line.word 0x00 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set" hexmask.word 0x00 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x00 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" group.word 0x3C++0x01 line.word 0x00 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set" hexmask.word 0x00 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x00 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" group.word 0x40++0x01 line.word 0x00 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear" hexmask.word 0x00 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x00 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" group.word 0x44++0x01 line.word 0x00 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear" hexmask.word 0x00 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x00 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" group.word 0x48++0x01 line.word 0x00 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable" rbitfld.word 0x00 15. "RESERVED,Reserved" "0,1" bitfld.word 0x00 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1" newline rbitfld.word 0x00 12. "RESERVED,Reserved" "0,1" bitfld.word 0x00 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1" bitfld.word 0x00 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1" newline bitfld.word 0x00 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1" bitfld.word 0x00 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1" rbitfld.word 0x00 7. "RESERVED,Reserved" "0,1" newline bitfld.word 0x00 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1" bitfld.word 0x00 5. "GC,General call IRQ wakeup set" "GC_0,GC_1" rbitfld.word 0x00 4. "RESERVED,Reserved" "0,1" newline bitfld.word 0x00 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1" bitfld.word 0x00 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1" newline bitfld.word 0x00 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1" group.word 0x4C++0x01 line.word 0x00 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable" rbitfld.word 0x00 15. "RESERVED,Reserved" "0,1" bitfld.word 0x00 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1" newline rbitfld.word 0x00 12. "RESERVED,Reserved" "0,1" bitfld.word 0x00 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1" bitfld.word 0x00 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1" newline bitfld.word 0x00 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1" bitfld.word 0x00 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1" rbitfld.word 0x00 7. "RESERVED,Reserved" "0,1" newline bitfld.word 0x00 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1" bitfld.word 0x00 5. "GC,General call IRQ wakeup set" "GC_0,GC_1" rbitfld.word 0x00 4. "RESERVED,Reserved" "0,1" newline bitfld.word 0x00 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1" bitfld.word 0x00 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1" newline bitfld.word 0x00 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1" group.word 0x90++0x01 line.word 0x00 "I2C_SYSS,System Status register" hexmask.word 0x00 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x00 0. "RDONE,Reset done bit" "RDONE_0_r,RDONE_1_r" group.word 0x94++0x01 line.word 0x00 "I2C_BUF,Buffer Configuration register" bitfld.word 0x00 15. "RDMA_EN,Receive DMA channel enable" "RDMA_EN_0,RDMA_EN_1" bitfld.word 0x00 14. "RXFIFO_CLR,Receive FIFO clear" "RXFIFO_CLR_0,RXFIFO_CLR_1" bitfld.word 0x00 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.word 0x00 7. "XDMA_EN,Transmit DMA channel enable" "XDMA_EN_0,XDMA_EN_1" bitfld.word 0x00 6. "TXFIFO_CLR,Transmit FIFO clear" "TXFIFO_CLR_0,TXFIFO_CLR_1" bitfld.word 0x00 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x98++0x01 line.word 0x00 "I2C_CNT,Data counter register" group.word 0x9C++0x01 line.word 0x00 "I2C_DATA,Data access register" hexmask.word.byte 0x00 8.--15. 1. "RESERVED,Reserved" hexmask.word.byte 0x00 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.word 0xA4++0x01 line.word 0x00 "I2C_CON,I2C configuration register" bitfld.word 0x00 15. "I2C_EN,I2C module enable" "I2C_EN_0,I2C_EN_1" rbitfld.word 0x00 14. "RESERVED,Reserved" "0,1" bitfld.word 0x00 12.--13. "OPMODE,Operation mode selection" "OPMODE_0,OPMODE_1,OPMODE_2,OPMODE_3" newline bitfld.word 0x00 11. "STB,Start byte mode (master mode only)" "STB_0,STB_1" bitfld.word 0x00 10. "MST,Master/slave mode" "MST_0,MST_1" bitfld.word 0x00 9. "TRX,Transmitter/Receiver mode (master mode only)" "TRX_0,TRX_1" newline bitfld.word 0x00 8. "XSA,Expand Slave address" "XSA_0,XSA_1" bitfld.word 0x00 7. "XOA0,Expand Own address 0" "XOA0_0,XOA0_1" bitfld.word 0x00 6. "XOA1,Expand Own address 1" "XOA1_0,XOA1_1" newline bitfld.word 0x00 5. "XOA2,Expand Own address 2" "XOA2_0,XOA2_1" bitfld.word 0x00 4. "XOA3,Expand Own address 3" "XOA3_0,XOA3_1" rbitfld.word 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.word 0x00 1. "STP,Stop condition (master mode only)" "STP_0,STP_1" bitfld.word 0x00 0. "STT,Start condition (master mode only)" "STT_0,STT_1" group.word 0xA8++0x01 line.word 0x00 "I2C_OA,Own address register" bitfld.word 0x00 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 10.--12. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.word 0x00 0.--9. 1. "OA,Own address" group.word 0xAC++0x01 line.word 0x00 "I2C_SA,Slave address register" rbitfld.word 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.word 0x00 0.--9. 1. "SA,Slave address" group.word 0xB0++0x01 line.word 0x00 "I2C_PSC,I2C Clock Prescaler Register" hexmask.word.byte 0x00 8.--15. 1. "RESERVED,Reserved" abitfld.word 0x00 0.--7. "PSC,Fast/Standard mode prescale sampling clock divider value" "0x00=Divide by 1,0x01=Divide by 2,0xFF=Divide by 256" group.word 0xB4++0x01 line.word 0x00 "I2C_SCLL,I2C SCL Low Time Register" hexmask.word.byte 0x00 8.--15. 1. "RESERVED,Reserved" hexmask.word.byte 0x00 0.--7. 1. "SCLL,Fast/standard mode SCL low timeThe value of the bit field is automatically increased by 7" group.word 0xB8++0x01 line.word 0x00 "I2C_SCLH,I2C SCL High Time Register" hexmask.word.byte 0x00 8.--15. 1. "RESERVED,Reserved" hexmask.word.byte 0x00 0.--7. 1. "SCLH,Fast/standard mode SCL high timeThe value of the bit field is automatically increased by 5" group.word 0xBC++0x01 line.word 0x00 "I2C_SYSTEST,I2C System Test Register" bitfld.word 0x00 15. "ST_EN,System test enable" "ST_EN_0,ST_EN_1" bitfld.word 0x00 14. "FREE,Free running mode (on breakpoint)" "FREE_0,FREE_1" bitfld.word 0x00 12.--13. "TMODE,Test mode select" "TMODE_0,TMODE_1,TMODE_2,TMODE_3" newline bitfld.word 0x00 11. "SSB,Set all status bits inI2C_IRQSTATUS_RAW [14:0]" "SSB_0,SSB_1" rbitfld.word 0x00 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.word 0x00 8. "SCL_I_FUNC,SCL line input value (functional mode)" "SCL_I_FUNC_0_r,SCL_I_FUNC_1_r" newline rbitfld.word 0x00 7. "SCL_O_FUNC,SCL line output value (functional mode)" "SCL_O_FUNC_0_r,SCL_O_FUNC_1_r" rbitfld.word 0x00 6. "SDA_I_FUNC,SDA line input value (functional mode)" "SDA_I_FUNC_0_r,SDA_I_FUNC_1_r" rbitfld.word 0x00 5. "SDA_O_FUNC,SDA line output value (functional mode)" "SDA_O_FUNC_0_r,SDA_O_FUNC_1_r" newline rbitfld.word 0x00 4. "RESERVED,Reserved" "0,1" rbitfld.word 0x00 3. "SCL_I,SCL line sense input value" "SCL_I_0_r,SCL_I_1_r" bitfld.word 0x00 2. "SCL_O,SCL line drive output value" "SCL_O_0,SCL_O_1" newline rbitfld.word 0x00 1. "SDA_I,SDA line sense input value" "SDA_I_0_r,SDA_I_1_r" bitfld.word 0x00 0. "SDA_O,SDA line drive output value" "SDA_O_0,SDA_O_1" rgroup.word 0xC0++0x01 line.word 0x00 "I2C_BUFSTAT,I2C Buffer Status Register" bitfld.word 0x00 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "FIFODEPTH_0_r,FIFODEPTH_1_r,FIFODEPTH_2_r,FIFODEPTH_3_r" bitfld.word 0x00 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.word 0x00 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0xC4++0x01 line.word 0x00 "I2C_OA1,I2C Own Address 1 Register" rbitfld.word 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.word 0x00 0.--9. 1. "OA1,Own address 1" group.word 0xC8++0x01 line.word 0x00 "I2C_OA2,I2C Own Address 2 Register" rbitfld.word 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.word 0x00 0.--9. 1. "OA2,Own address 2" group.word 0xCC++0x01 line.word 0x00 "I2C_OA3,I2C Own Address 3 Register" rbitfld.word 0x00 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.word 0x00 0.--9. 1. "OA3,Own address 3" rgroup.word 0xD0++0x01 line.word 0x00 "I2C_ACTOA,I2C Active Own Address Register" hexmask.word 0x00 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x00 3. "OA3_ACT,Own Address 3 active" "OA3_ACT_0_r,OA3_ACT_1_r" bitfld.word 0x00 2. "OA2_ACT,Own Address 2 active" "OA2_ACT_0_r,OA2_ACT_1_r" newline bitfld.word 0x00 1. "OA1_ACT,Own Address 1 active" "OA1_ACT_0_r,OA1_ACT_1_r" bitfld.word 0x00 0. "OA0_ACT,Own Address 0 active" "OA0_ACT_0_r,OA0_ACT_1_r" group.word 0xD4++0x01 line.word 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register" hexmask.word 0x00 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x00 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "OA3_EN_0,OA3_EN_1" bitfld.word 0x00 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "OA2_EN_0,OA2_EN_1" newline bitfld.word 0x00 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "OA1_EN_0,OA1_EN_1" bitfld.word 0x00 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "OA0_EN_0,OA0_EN_1" width 0x0B tree.end repeat.end tree "I2C1_TARG" base ad:0x48071000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "I2C2_TARG" base ad:0x48073000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "IEEE1500_2_OCP_TARG" base ad:0x4A109000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "INSTR_CM_CORE_AON" base ad:0x4A005F00 rgroup.long 0x00++0x03 line.long 0x00 "CMI_IDENTICATION,CM profiling identification register" bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3" bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates a software compatible module family" bitfld.long 0x00 11.--15. "RTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x07 line.long 0x00 "CMI_SYS_CONFIG,CM profiling system configuartion register" hexmask.long 0x00 4.--31. 1. "RESERVED," bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "0,1,2,3" rbitfld.long 0x00 1. "RESERVED," "0,1" bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1" line.long 0x04 "CMI_STATUS,CM profiling status register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "FIFOEMPTY,PM Profiling buffer empty" "0,1" hexmask.long.byte 0x04 0.--7. 1. "RESERVED," group.long 0x24++0x0F line.long 0x00 "CMI_CONFIGURATION,CM profiling configuration register" bitfld.long 0x00 30.--31. "CLAIM_3,Ownership" "0,1,2,3" bitfld.long 0x00 29. "CLAIM_2,Debugger override qualifier" "0,1" rbitfld.long 0x00 28. "CLAIM_1,Current owner" "0,1" hexmask.long.word 0x00 16.--27. 1. "RESERVED," bitfld.long 0x00 15. "MOD_ACT_EN,When HIGH the CM Module Activity collection is enabled" "0,1" newline hexmask.long.byte 0x00 8.--14. 1. "RESERVED," bitfld.long 0x00 7. "EVT_CAPT_EN,When HIGH the CM events capture is enabled" "0,1" hexmask.long.byte 0x00 0.--6. 1. "RESERVED," line.long 0x04 "CMI_CLASS_FILTERING,CM profiling class filtering register" bitfld.long 0x04 31. "SNAP_CAPT_EN_1F,Snapshot capture enable - Class-ID = 0x1F" "0,1" bitfld.long 0x04 30. "SNAP_CAPT_EN_1E," "0,1" bitfld.long 0x04 29. "SNAP_CAPT_EN_1D," "0,1" bitfld.long 0x04 28. "SNAP_CAPT_EN_1C," "0,1" bitfld.long 0x04 27. "SNAP_CAPT_EN_1B," "0,1" newline bitfld.long 0x04 26. "SNAP_CAPT_EN_1A," "0,1" bitfld.long 0x04 25. "SNAP_CAPT_EN_19," "0,1" bitfld.long 0x04 24. "SNAP_CAPT_EN_18," "0,1" bitfld.long 0x04 23. "SNAP_CAPT_EN_17," "0,1" bitfld.long 0x04 22. "SNAP_CAPT_EN_16," "0,1" newline bitfld.long 0x04 21. "SNAP_CAPT_EN_15," "0,1" bitfld.long 0x04 20. "SNAP_CAPT_EN_14," "0,1" bitfld.long 0x04 19. "SNAP_CAPT_EN_13," "0,1" bitfld.long 0x04 18. "SNAP_CAPT_EN_12," "0,1" bitfld.long 0x04 17. "SNAP_CAPT_EN_11," "0,1" newline bitfld.long 0x04 16. "SNAP_CAPT_EN_10,Snapshot capture enable - Class-ID = 0x10" "0,1" hexmask.long.word 0x04 4.--15. 1. "RESERVED," bitfld.long 0x04 3. "SNAP_CAPT_EN_03,Snapshot capture enable - Class-ID = 0x03 [0x23]" "0,1" bitfld.long 0x04 2. "SNAP_CAPT_EN_02,Snapshot capture enable - Class-ID = 0x02 [0x22]" "0,1" bitfld.long 0x04 1. "SNAP_CAPT_EN_01,Snapshot capture enable - Class-ID = 0x01 [0x21]" "0,1" newline bitfld.long 0x04 0. "SNAP_CAPT_EN_00,Snapshot capture enable - Class-ID = 0x00 [0x20]" "0,1" line.long 0x08 "CMI_TRIGGERING,CM profiling triggering control register" hexmask.long 0x08 2.--31. 1. "RESERVED," bitfld.long 0x08 1. "TRIG_STOP_EN,Enable stop capturing CM events from external trigger detection" "0,1" bitfld.long 0x08 0. "TRIG_START_EN,Enable start capturing CM events from external trigger detection" "0,1" line.long 0x0C "CMI_SAMPLING,CM profiling sampling window register" hexmask.long.word 0x0C 20.--31. 1. "RESERVED," bitfld.long 0x0C 16.--19. "FCLK_DIV_FACOR,FunClk divide factor ranging from 1 to 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0C 8.--15. 1. "RESERVED," hexmask.long.byte 0x0C 0.--7. 1. "SAMP_WIND_SIZE,CM events sampling window size" width 0x0B tree.end tree "INSTR_PRM" base ad:0x4AE07F00 rgroup.long 0x00++0x03 line.long 0x00 "PMI_IDENTICATION,PM profiling identification register" bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3" bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates a software compatible module family" bitfld.long 0x00 11.--15. "RTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "0,1,2,3" newline bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x07 line.long 0x00 "PMI_SYS_CONFIG,PM profiling system configuartion register" hexmask.long 0x00 4.--31. 1. "RESERVED," bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "0,1,2,3" rbitfld.long 0x00 1. "RESERVED," "0,1" bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1" line.long 0x04 "PMI_STATUS,PM profiling status register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "FIFOEMPTY,PM Profiling buffer empty" "0,1" hexmask.long.byte 0x04 0.--7. 1. "RESERVED," group.long 0x24++0x0F line.long 0x00 "PMI_CONFIGURATION,PM profiling configuration register" bitfld.long 0x00 30.--31. "CLAIM_3,Ownership" "0,1,2,3" bitfld.long 0x00 29. "CLAIM_2,Debugger override qualifier" "0,1" rbitfld.long 0x00 28. "CLAIM_1,Current owner" "0,1" hexmask.long.tbyte 0x00 8.--27. 1. "RESERVED," bitfld.long 0x00 7. "EVT_CAPT_EN,When HIGH the PM events capture is enabled" "0,1" hexmask.long.byte 0x00 0.--6. 1. "RESERVED," line.long 0x04 "PMI_CLASS_FILTERING,PM profiling class filtering register" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "SNAP_CAPT_EN_03,Snapshot capture enable - Class-ID = 0x03" "0,1" bitfld.long 0x04 2. "SNAP_CAPT_EN_02,Snapshot capture enable - Class-ID = 0x02" "0,1" bitfld.long 0x04 1. "SNAP_CAPT_EN_01,Snapshot capture enable - Class-ID = 0x01" "0,1" bitfld.long 0x04 0. "SNAP_CAPT_EN_00,Snapshot capture enable - Class-ID = 0x00" "0,1" line.long 0x08 "PMI_TRIGGERING,PM profiling triggering control register" hexmask.long 0x08 2.--31. 1. "RESERVED," bitfld.long 0x08 1. "TRIG_STOP_EN,Enable stop capturing PM events from external trigger detection" "0,1" bitfld.long 0x08 0. "TRIG_START_EN,Enable start capturing PM events from external trigger detection" "0,1" line.long 0x0C "PMI_SAMPLING,PM profiling sampling window register" hexmask.long.word 0x0C 20.--31. 1. "RESERVED," bitfld.long 0x0C 16.--19. "FCLK_DIV_FACOR,FunClk divide factor ranging from 1 to 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0C 8.--15. 1. "RESERVED," hexmask.long.byte 0x0C 0.--7. 1. "SAMP_WIND_SIZE,PM events sampling window size" width 0x0B tree.end tree "IPU_C0_RW_TABLE" base ad:0xE00FE000 group.long 0x00++0x07 line.long 0x00 "CORTEXM4_RW_PID1,Peripheral Identification register- allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs)" line.long 0x04 "CORTEXM4_RW_PID2,Peripheral Identification register - allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs)" width 0x0B tree.end tree "IPU_C1_RW_TABLE" base ad:0xE00FE000 group.long 0x00++0x07 line.long 0x00 "CORTEXM4_RW_PID1,Peripheral Identification register- allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs)" line.long 0x04 "CORTEXM4_RW_PID2,Peripheral Identification register - allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs)" width 0x0B tree.end tree "IPU_CM_CORE_AON" base ad:0x4A005500 group.long 0x00++0x0B line.long 0x00 "CM_IPU1_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_IPU1_GFCLK,This field indicates the state of the IPU1_GFCLK clock in the domain" "CLKACTIVITY_IPU1_GFCLK_0,CLKACTIVITY_IPU1_GFCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the IPU1 clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_IPU1_STATICDEP,This register controls the static domain depedencies from IPU domain towards 'target' domains" rbitfld.long 0x04 31. "RESERVED," "0,1" bitfld.long 0x04 30. "CRC_STATDEP,Static dependency towards CRC clock domain" "CRC_STATDEP_0,CRC_STATDEP_1" newline bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE clock domain" "PCIE_STATDEP_0,PCIE_STATDEP_1" bitfld.long 0x04 28. "ISS_STATDEP,Static dependency towards ISS clock domain" "ISS_STATDEP_0,ISS_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain" "GMAC_STATDEP_0,GMAC_STATDEP_1" bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain" "IPU_STATDEP_0,IPU_STATDEP_1" newline rbitfld.long 0x04 23. "RESERVED," "0,1" bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" newline bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain" "EVE1_STATDEP_0,EVE1_STATDEP_1" bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain" "CUSTEFUSE_STATDEP_0,?" rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 11. "SDMA_STATDEP,Static dependency towards DMA clock domain" "SDMA_STATDEP_0,?" bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU clock domain" "GPU_STATDEP_0,GPU_STATDEP_1" newline rbitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain" "CAM_STATDEP_0,?" bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" rbitfld.long 0x04 6. "RESERVED," "0,1" newline bitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "L3MAIN1_STATDEP_0,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 3. "RESERVED," "0,1" bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP clock domain" "DSP1_STATDEP_0,DSP1_STATDEP_1" bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_IPU1_DYNAMICDEP,This register controls the dynamic domain depedencies from IPU domain towards 'target' domains" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.tbyte 0x08 6.--23. 1. "RESERVED," rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20++0x03 line.long 0x00 "CM_IPU1_IPU1_CLKCTRL,This register manages the IPU1 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects the IPU functional clock" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_IPU_CLKSTCTRL,This register enables the IPU domain power state transition" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "CLKACTIVITY_MCASP1_AHCLKR,This field indicates the state of the MCASP1_AHCLKR clock in the domain" "CLKACTIVITY_MCASP1_AHCLKR_0,CLKACTIVITY_MCASP1_AHCLKR_1" newline rbitfld.long 0x00 17. "CLKACTIVITY_MCASP1_AHCLKX,This field indicates the state of the MCASP1_AHCLKX clock in the domain" "CLKACTIVITY_MCASP1_AHCLKX_0,CLKACTIVITY_MCASP1_AHCLKX_1" rbitfld.long 0x00 16. "CLKACTIVITY_MCASP1_AUX_GFCLK,This field indicates the state of the MCASP1_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP1_AUX_GFCLK_0,CLKACTIVITY_MCASP1_AUX_GFCLK_1" newline rbitfld.long 0x00 15. "RESERVED," "0,1" rbitfld.long 0x00 14. "CLKACTIVITY_UART6_GFCLK,This field indicates the state of the UART6_GFCLK clock in the domain" "CLKACTIVITY_UART6_GFCLK_0,CLKACTIVITY_UART6_GFCLK_1" newline rbitfld.long 0x00 13. "CLKACTIVITY_IPU_96M_GFCLK,This field indicates the state of the IPU_96M_GFCLK clock in the domain" "CLKACTIVITY_IPU_96M_GFCLK_0,CLKACTIVITY_IPU_96M_GFCLK_1" rbitfld.long 0x00 12. "CLKACTIVITY_TIMER8_GFCLK,This field indicates the state of the TIMER8_GFCLK clock in the domain" "CLKACTIVITY_TIMER8_GFCLK_0,CLKACTIVITY_TIMER8_GFCLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_TIMER7_GFCLK,This field indicates the state of the TIMER7_GFCLK clock in the domain" "CLKACTIVITY_TIMER7_GFCLK_0,CLKACTIVITY_TIMER7_GFCLK_1" rbitfld.long 0x00 10. "CLKACTIVITY_TIMER6_GFCLK,This field indicates the state of the TIMER6_GFCLK clock in the domain" "CLKACTIVITY_TIMER6_GFCLK_0,CLKACTIVITY_TIMER6_GFCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_TIMER5_GFCLK,This field indicates the state of the TIMER5_GFCLK functional clock in the domain" "CLKACTIVITY_TIMER5_GFCLK_0,CLKACTIVITY_TIMER5_GFCLK_1" rbitfld.long 0x00 8. "CLKACTIVITY_IPU_L3_GICLK,This field indicates the state of the IPU_L3_GICLK interface clock in the domain" "CLKACTIVITY_IPU_L3_GICLK_0,CLKACTIVITY_IPU_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the IPU clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x50++0x03 line.long 0x00 "CM_IPU_MCASP1_CLKCTRL,This register manages the MCASP1 clocks" bitfld.long 0x00 28.--31. "CLKSEL_AHCLKR,Selects reference clock for AHCLKR" "CLKSEL_AHCLKR_0,CLKSEL_AHCLKR_1,CLKSEL_AHCLKR_2,CLKSEL_AHCLKR_3,CLKSEL_AHCLKR_4,CLKSEL_AHCLKR_5,CLKSEL_AHCLKR_6,CLKSEL_AHCLKR_7,CLKSEL_AHCLKR_8,CLKSEL_AHCLKR_9,CLKSEL_AHCLKR_10,CLKSEL_AHCLKR_11,CLKSEL_AHCLKR_12,CLKSEL_AHCLKR_13,CLKSEL_AHCLKR_14,CLKSEL_AHCLKR_15" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" newline bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x00 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x58++0x03 line.long 0x00 "CM_IPU_TIMER5_CLKCTRL,This register manages the TIMER5 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,?,?,?,?" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x60++0x03 line.long 0x00 "CM_IPU_TIMER6_CLKCTRL,This register manages the TIMER6 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,?,?,?,?" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x68++0x03 line.long 0x00 "CM_IPU_TIMER7_CLKCTRL,This register manages the TIMER7 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,?,?,?,?" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x70++0x03 line.long 0x00 "CM_IPU_TIMER8_CLKCTRL,This register manages the TIMER8 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,?,?,?,?" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x78++0x03 line.long 0x00 "CM_IPU_I2C5_CLKCTRL,This register manages the I2C5 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x80++0x03 line.long 0x00 "CM_IPU_UART6_CLKCTRL,This register manages the UART6 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "IPU_FW" base ad:0x4A15B000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" newline rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "IPU_FW_CFG_TARG" base ad:0x4A15C000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "IPU_MMU" base ad:0x58882000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Write 0's for future compatibility" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" rbitfld.long 0x00 5.--7. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x00 2. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" hexmask.long 0x08 5.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" newline bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0_w,EMUMISS_1_r" bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" hexmask.long 0x0C 5.--31. 1. "RESERVED,Write 0's for future compatibility Read returns 0" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" newline bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0,EMUMISS_1" bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" hexmask.long 0x00 1.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" hexmask.long 0x04 4.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable" "TWLENABLE_0,TWLENABLE_1" newline bitfld.long 0x04 1. "MMUENABLE,MMU enable" "MMUENABLE_0,MMUENABLE_1" rbitfld.long 0x04 0. "RESERVED,Write 0's for future compatibility" "0,1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" hexmask.long.byte 0x0C 0.--6. 1. "RESERVED,Write 0's for future compatibility" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 9. "RESERVED,Write 0's for future compatibility" "0,1" newline bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 0.--3. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" hexmask.long 0x14 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x18 4.--11. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x18 3. "P,Preserved bit" "P_0,P_1" newline bitfld.long 0x18 2. "V,Valid bit" "V_0,V_1" bitfld.long 0x18 0.--1. "PAGESIZE,Page size" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x1C 0.--11. 1. "RESERVED,Write 0's for future compatibility" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" hexmask.long 0x20 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" hexmask.long 0x24 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x28 4.--11. 1. "RESERVED,Reads return 0" bitfld.long 0x28 3. "P,Preserved bit" "P_0_r,P_1_r" newline bitfld.long 0x28 2. "V,Valid bit" "V_0_r,V_1_r" bitfld.long 0x28 0.--1. "PAGESIZE,Page size" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x2C 0.--11. 1. "RESERVED,Reads return 0" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" newline rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "0,1,2,3" bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "0,1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" hexmask.long.word 0x08 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" width 0x0B tree.end tree "IPU_PRM" base ad:0x4AE06500 group.long 0x00++0x07 line.long 0x00 "PM_IPU_PWRSTCTRL,This register controls the IPU domain power state to reach upon a domain sleep transition" hexmask.long.word 0x00 22.--31. 1. "RESERVED," rbitfld.long 0x00 20.--21. "PERIPHMEM_ONSTATE,PERIPHMEM memory state when domain is ON" "?,?,?,PERIPHMEM_ONSTATE_3" newline rbitfld.long 0x00 18.--19. "RESERVED," "0,1,2,3" rbitfld.long 0x00 16.--17. "AESSMEM_ONSTATE,AESSMEM memory state when domain is ON" "?,?,?,AESSMEM_ONSTATE_3" newline rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "PERIPHMEM_RETSTATE,PERIPHMEM memory state when domain is RETENTION" "PERIPHMEM_RETSTATE_0,PERIPHMEM_RETSTATE_1" newline rbitfld.long 0x00 9. "RESERVED," "0,1" bitfld.long 0x00 8. "AESSMEM_RETSTATE,AESSMEM memory state when domain is RETENTION" "AESSMEM_RETSTATE_0,AESSMEM_RETSTATE_1" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" rbitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION" "LOGICRETSTATE_0,?" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_IPU_PWRSTST,This register provides a status on the IPU domain current power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 10.--19. 1. "RESERVED," rbitfld.long 0x04 8.--9. "PERIPHMEM_STATEST,PERIPHMEM memory state status" "PERIPHMEM_STATEST_0,PERIPHMEM_STATEST_1,PERIPHMEM_STATEST_2,PERIPHMEM_STATEST_3" newline rbitfld.long 0x04 6.--7. "RESERVED," "0,1,2,3" rbitfld.long 0x04 4.--5. "AESSMEM_STATEST,AESSMEM memory state status" "AESSMEM_STATEST_0,AESSMEM_STATEST_1,AESSMEM_STATEST_2,AESSMEM_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_IPU1_RSTCTRL,This register controls the release of the IPU1 sub-system resets" hexmask.long 0x00 3.--31. 1. "RESERVED," bitfld.long 0x00 2. "RST_IPU,BELLINI system reset control" "RST_IPU_0,RST_IPU_1" newline bitfld.long 0x00 1. "RST_CPU1,BELLINI Cortex M3 CPU1 reset control" "RST_CPU1_0,RST_CPU1_1" bitfld.long 0x00 0. "RST_CPU0,BELLINI Cortex M3 CPU0 reset control" "RST_CPU0_0,RST_CPU0_1" line.long 0x04 "RM_IPU1_RSTST,This register logs the different reset sources of the IPU1 SS" hexmask.long 0x04 7.--31. 1. "RESERVED," bitfld.long 0x04 6. "RST_ICECRUSHER_CPU1,CPU1 has been reset due to IPU ICECRUSHER1 reset source" "RST_ICECRUSHER_CPU1_0,RST_ICECRUSHER_CPU1_1" newline bitfld.long 0x04 5. "RST_ICECRUSHER_CPU0,CPU0 has been reset due to IPU ICECRUSHER0 reset source" "RST_ICECRUSHER_CPU0_0,RST_ICECRUSHER_CPU0_1" bitfld.long 0x04 4. "RST_EMULATION_CPU1,CPU1 has been reset due to emulation reset source e.g" "RST_EMULATION_CPU1_0,RST_EMULATION_CPU1_1" newline bitfld.long 0x04 3. "RST_EMULATION_CPU0,CPU0 has been reset due to emulation reset source e.g" "RST_EMULATION_CPU0_0,RST_EMULATION_CPU0_1" bitfld.long 0x04 2. "RST_IPU,IPU system SW reset status" "RST_IPU_0,RST_IPU_1" newline bitfld.long 0x04 1. "RST_CPU1,CPU1 SW reset status" "RST_CPU1_0,RST_CPU1_1" bitfld.long 0x04 0. "RST_CPU0,CPU0 SW reset status" "RST_CPU0_0,RST_CPU0_1" group.long 0x24++0x03 line.long 0x00 "RM_IPU1_IPU1_CONTEXT,This register contains dedicated IPU1 context statuses" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "LOSTMEM_IPU_L2RAM,Specify if memory-based context in IPU_L2RAM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_IPU_L2RAM_0,LOSTMEM_IPU_L2RAM_1" newline bitfld.long 0x00 8. "LOSTMEM_IPU_UNICACHE,Specify if memory-based context in IPU_UNICACHE memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_IPU_UNICACHE_0,LOSTMEM_IPU_UNICACHE_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x50++0x37 line.long 0x00 "PM_IPU_MCASP1_WKDEP,This register controls wakeup dependency based on MCASP1 service requests" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "WKUPDEP_MCASP1_DMA_DSP2,Wakeup dependency from MCASP1 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_DMA_DSP2_0,WKUPDEP_MCASP1_DMA_DSP2_1" newline rbitfld.long 0x00 14. "RESERVED," "0,1" bitfld.long 0x00 13. "WKUPDEP_MCASP1_DMA_SDMA,Wakeup dependency from MCASP1 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_DMA_SDMA_0,WKUPDEP_MCASP1_DMA_SDMA_1" newline bitfld.long 0x00 12. "WKUPDEP_MCASP1_DMA_DSP1,Wakeup dependency from MCASP1 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_DMA_DSP1_0,WKUPDEP_MCASP1_DMA_DSP1_1" rbitfld.long 0x00 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 9. "WKUPDEP_MCASP1_IRQ_EVE4,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_EVE4_0,WKUPDEP_MCASP1_IRQ_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_MCASP1_IRQ_EVE3,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_EVE3_0,WKUPDEP_MCASP1_IRQ_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_MCASP1_IRQ_EVE2,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_EVE2_0,WKUPDEP_MCASP1_IRQ_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_MCASP1_IRQ_EVE1,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_EVE1_0,WKUPDEP_MCASP1_IRQ_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_MCASP1_IRQ_DSP2,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_DSP2_0,WKUPDEP_MCASP1_IRQ_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_MCASP1_IRQ_IPU1,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_IPU1_0,WKUPDEP_MCASP1_IRQ_IPU1_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" bitfld.long 0x00 2. "WKUPDEP_MCASP1_IRQ_DSP1,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_DSP1_0,WKUPDEP_MCASP1_IRQ_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_MCASP1_IRQ_IPU2,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_IPU2_0,WKUPDEP_MCASP1_IRQ_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_MCASP1_IRQ_MPU,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_MPU_0,WKUPDEP_MCASP1_IRQ_MPU_1" line.long 0x04 "RM_IPU_MCASP1_CONTEXT,This register contains dedicated MCASP context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_IPU_TIMER5_WKDEP,This register controls wakeup dependency based on TIMER5 service requests" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "WKUPDEP_TIMER5_EVE4,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_EVE4_0,WKUPDEP_TIMER5_EVE4_1" newline bitfld.long 0x08 8. "WKUPDEP_TIMER5_EVE3,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_EVE3_0,WKUPDEP_TIMER5_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_TIMER5_EVE2,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_EVE2_0,WKUPDEP_TIMER5_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_TIMER5_EVE1,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_EVE1_0,WKUPDEP_TIMER5_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_TIMER5_DSP2,Wakeup dependency from TIMER5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_DSP2_0,WKUPDEP_TIMER5_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_TIMER5_IPU1,Wakeup dependency from TIMER5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_IPU1_0,WKUPDEP_TIMER5_IPU1_1" rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 2. "WKUPDEP_TIMER5_DSP1,Wakeup dependency from TIMER5 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_DSP1_0,WKUPDEP_TIMER5_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_TIMER5_IPU2,Wakeup dependency from TIMER5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_IPU2_0,WKUPDEP_TIMER5_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_TIMER5_MPU,Wakeup dependency from TIMER5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_MPU_0,WKUPDEP_TIMER5_MPU_1" line.long 0x0C "RM_IPU_TIMER5_CONTEXT,This register contains dedicated TIMER5 context statuses" hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_IPU_TIMER6_WKDEP,This register controls wakeup dependency based on TIMER6 service requests" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED," bitfld.long 0x10 9. "WKUPDEP_TIMER6_EVE4,Wakeup dependency from TIMER6 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_EVE4_0,WKUPDEP_TIMER6_EVE4_1" newline bitfld.long 0x10 8. "WKUPDEP_TIMER6_EVE3,Wakeup dependency from TIMER6 (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_EVE3_0,WKUPDEP_TIMER6_EVE3_1" bitfld.long 0x10 7. "WKUPDEP_TIMER6_EVE2,Wakeup dependency from TIMER6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_EVE2_0,WKUPDEP_TIMER6_EVE2_1" newline bitfld.long 0x10 6. "WKUPDEP_TIMER6_EVE1,Wakeup dependency from TIMER6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_EVE1_0,WKUPDEP_TIMER6_EVE1_1" bitfld.long 0x10 5. "WKUPDEP_TIMER6_DSP2,Wakeup dependency from TIMER6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_DSP2_0,WKUPDEP_TIMER6_DSP2_1" newline bitfld.long 0x10 4. "WKUPDEP_TIMER6_IPU1,Wakeup dependency from TIMER6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_IPU1_0,WKUPDEP_TIMER6_IPU1_1" rbitfld.long 0x10 3. "RESERVED," "0,1" newline bitfld.long 0x10 2. "WKUPDEP_TIMER6_DSP1,Wakeup dependency from TIMER6 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_DSP1_0,WKUPDEP_TIMER6_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_TIMER6_IPU2,Wakeup dependency from TIMER6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_IPU2_0,WKUPDEP_TIMER6_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_TIMER6_MPU,Wakeup dependency from TIMER6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_MPU_0,WKUPDEP_TIMER6_MPU_1" line.long 0x14 "RM_IPU_TIMER6_CONTEXT,This register contains dedicated TIMER6 context statuses" hexmask.long 0x14 1.--31. 1. "RESERVED," bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x18 "PM_IPU_TIMER7_WKDEP,This register controls wakeup dependency based on TIMER7 service requests" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," bitfld.long 0x18 9. "WKUPDEP_TIMER7_EVE4,Wakeup dependency from TIMER7 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_EVE4_0,WKUPDEP_TIMER7_EVE4_1" newline bitfld.long 0x18 8. "WKUPDEP_TIMER7_EVE3,Wakeup dependency from TIMER7 (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_EVE3_0,WKUPDEP_TIMER7_EVE3_1" bitfld.long 0x18 7. "WKUPDEP_TIMER7_EVE2,Wakeup dependency from TIMER7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_EVE2_0,WKUPDEP_TIMER7_EVE2_1" newline bitfld.long 0x18 6. "WKUPDEP_TIMER7_EVE1,Wakeup dependency from TIMER7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_EVE1_0,WKUPDEP_TIMER7_EVE1_1" bitfld.long 0x18 5. "WKUPDEP_TIMER7_DSP2,Wakeup dependency from TIMER7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_DSP2_0,WKUPDEP_TIMER7_DSP2_1" newline bitfld.long 0x18 4. "WKUPDEP_TIMER7_IPU1,Wakeup dependency from TIMER7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_IPU1_0,WKUPDEP_TIMER7_IPU1_1" rbitfld.long 0x18 3. "RESERVED," "0,1" newline bitfld.long 0x18 2. "WKUPDEP_TIMER7_DSP1,Wakeup dependency from TIMER7 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_DSP1_0,WKUPDEP_TIMER7_DSP1_1" bitfld.long 0x18 1. "WKUPDEP_TIMER7_IPU2,Wakeup dependency from TIMER7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_IPU2_0,WKUPDEP_TIMER7_IPU2_1" newline bitfld.long 0x18 0. "WKUPDEP_TIMER7_MPU,Wakeup dependency from TIMER7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_MPU_0,WKUPDEP_TIMER7_MPU_1" line.long 0x1C "RM_IPU_TIMER7_CONTEXT,This register contains dedicated TIMER7 context statuses" hexmask.long 0x1C 1.--31. 1. "RESERVED," bitfld.long 0x1C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x20 "PM_IPU_TIMER8_WKDEP,This register controls wakeup dependency based on TIMER8 service requests" hexmask.long.tbyte 0x20 10.--31. 1. "RESERVED," bitfld.long 0x20 9. "WKUPDEP_TIMER8_EVE4,Wakeup dependency from TIMER8 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_EVE4_0,WKUPDEP_TIMER8_EVE4_1" newline bitfld.long 0x20 8. "WKUPDEP_TIMER8_EVE3,Wakeup dependency from TIMER8 (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_EVE3_0,WKUPDEP_TIMER8_EVE3_1" bitfld.long 0x20 7. "WKUPDEP_TIMER8_EVE2,Wakeup dependency from TIMER8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_EVE2_0,WKUPDEP_TIMER8_EVE2_1" newline bitfld.long 0x20 6. "WKUPDEP_TIMER8_EVE1,Wakeup dependency from TIMER8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_EVE1_0,WKUPDEP_TIMER8_EVE1_1" bitfld.long 0x20 5. "WKUPDEP_TIMER8_DSP2,Wakeup dependency from TIMER8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_DSP2_0,WKUPDEP_TIMER8_DSP2_1" newline bitfld.long 0x20 4. "WKUPDEP_TIMER8_IPU1,Wakeup dependency from TIMER8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_IPU1_0,WKUPDEP_TIMER8_IPU1_1" rbitfld.long 0x20 3. "RESERVED," "0,1" newline bitfld.long 0x20 2. "WKUPDEP_TIMER8_DSP1,Wakeup dependency from TIMER8 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_DSP1_0,WKUPDEP_TIMER8_DSP1_1" bitfld.long 0x20 1. "WKUPDEP_TIMER8_IPU2,Wakeup dependency from TIMER8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_IPU2_0,WKUPDEP_TIMER8_IPU2_1" newline bitfld.long 0x20 0. "WKUPDEP_TIMER8_MPU,Wakeup dependency from TIMER8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_MPU_0,WKUPDEP_TIMER8_MPU_1" line.long 0x24 "RM_IPU_TIMER8_CONTEXT,This register contains dedicated TIMER8 context statuses" hexmask.long 0x24 1.--31. 1. "RESERVED," bitfld.long 0x24 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x28 "PM_IPU_I2C5_WKDEP,This register controls wakeup dependency based on I2C5 service requests" hexmask.long.word 0x28 16.--31. 1. "RESERVED," bitfld.long 0x28 15. "WKUPDEP_I2C5_DMA_DSP2,Wakeup dependency from I2C5 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_DMA_DSP2_0,WKUPDEP_I2C5_DMA_DSP2_1" newline rbitfld.long 0x28 14. "RESERVED," "0,1" bitfld.long 0x28 13. "WKUPDEP_I2C5_DMA_SDMA,Wakeup dependency from I2C5 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_DMA_SDMA_0,WKUPDEP_I2C5_DMA_SDMA_1" newline bitfld.long 0x28 12. "WKUPDEP_I2C5_DMA_DSP1,Wakeup dependency from I2C5 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_DMA_DSP1_0,WKUPDEP_I2C5_DMA_DSP1_1" rbitfld.long 0x28 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x28 9. "WKUPDEP_I2C5_IRQ_EVE4,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_EVE4_0,WKUPDEP_I2C5_IRQ_EVE4_1" bitfld.long 0x28 8. "WKUPDEP_I2C5_IRQ_EVE3,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_EVE3_0,WKUPDEP_I2C5_IRQ_EVE3_1" newline bitfld.long 0x28 7. "WKUPDEP_I2C5_IRQ_EVE2,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_EVE2_0,WKUPDEP_I2C5_IRQ_EVE2_1" bitfld.long 0x28 6. "WKUPDEP_I2C5_IRQ_EVE1,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_EVE1_0,WKUPDEP_I2C5_IRQ_EVE1_1" newline bitfld.long 0x28 5. "WKUPDEP_I2C5_IRQ_DSP2,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_DSP2_0,WKUPDEP_I2C5_IRQ_DSP2_1" bitfld.long 0x28 4. "WKUPDEP_I2C5_IRQ_IPU1,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_IPU1_0,WKUPDEP_I2C5_IRQ_IPU1_1" newline rbitfld.long 0x28 3. "RESERVED," "0,1" bitfld.long 0x28 2. "WKUPDEP_I2C5_IRQ_DSP1,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_DSP1_0,WKUPDEP_I2C5_IRQ_DSP1_1" newline bitfld.long 0x28 1. "WKUPDEP_I2C5_IRQ_IPU2,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_IPU2_0,WKUPDEP_I2C5_IRQ_IPU2_1" bitfld.long 0x28 0. "WKUPDEP_I2C5_IRQ_MPU,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_MPU_0,WKUPDEP_I2C5_IRQ_MPU_1" line.long 0x2C "RM_IPU_I2C5_CONTEXT,This register contains dedicated I2C5 context statuses" hexmask.long 0x2C 1.--31. 1. "RESERVED," bitfld.long 0x2C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x30 "PM_IPU_UART6_WKDEP,This register controls wakeup dependency based on UART6 service requests" hexmask.long.tbyte 0x30 10.--31. 1. "RESERVED," bitfld.long 0x30 9. "WKUPDEP_UART6_EVE4,Wakeup dependency from UART6 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_EVE4_0,WKUPDEP_UART6_EVE4_1" newline bitfld.long 0x30 8. "WKUPDEP_UART6_EVE3,Wakeup dependency from UART6 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_EVE3_0,WKUPDEP_UART6_EVE3_1" bitfld.long 0x30 7. "WKUPDEP_UART6_EVE2,Wakeup dependency from UART6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_EVE2_0,WKUPDEP_UART6_EVE2_1" newline bitfld.long 0x30 6. "WKUPDEP_UART6_EVE1,Wakeup dependency from UART6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_EVE1_0,WKUPDEP_UART6_EVE1_1" bitfld.long 0x30 5. "WKUPDEP_UART6_DSP2,Wakeup dependency from UART6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_DSP2_0,WKUPDEP_UART6_DSP2_1" newline bitfld.long 0x30 4. "WKUPDEP_UART6_IPU1,Wakeup dependency from UART6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_IPU1_0,WKUPDEP_UART6_IPU1_1" bitfld.long 0x30 3. "WKUPDEP_UART6_SDMA,Wakeup dependency from UART6 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_SDMA_0,WKUPDEP_UART6_SDMA_1" newline bitfld.long 0x30 2. "WKUPDEP_UART6_DSP1,Wakeup dependency from UART6 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_DSP1_0,WKUPDEP_UART6_DSP1_1" bitfld.long 0x30 1. "WKUPDEP_UART6_IPU2,Wakeup dependency from UART6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_IPU2_0,WKUPDEP_UART6_IPU2_1" newline bitfld.long 0x30 0. "WKUPDEP_UART6_MPU,Wakeup dependency from UART6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_MPU_0,WKUPDEP_UART6_MPU_1" line.long 0x34 "RM_IPU_UART6_CONTEXT,This register contains dedicated UART6 context statuses" hexmask.long.tbyte 0x34 9.--31. 1. "RESERVED," bitfld.long 0x34 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x34 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 1. "LOSTCONTEXT_RFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x34 0. "RESERVED," "0,1" width 0x0B tree.end tree "IPU_TARG" base ad:0x44001000 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "IPU_UNICACHE_CFG" base ad:0x58880000 group.long 0x04++0x27 line.long 0x00 "CACHE_CONFIG,Configuration Register" hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4. "LOCK_MAIN,Lock access to maintenance registers" "LOCK_MAIN_0,LOCK_MAIN_1" bitfld.long 0x00 3. "LOCK_PORT,Lock access to interface registers" "LOCK_PORT_0,LOCK_PORT_1" newline bitfld.long 0x00 2. "LOCK_INT,Lock access to interrupt registers" "LOCK_INT_0,LOCK_INT_1" bitfld.long 0x00 1. "BYPASS,Bypass cache" "BYPASS_0,BYPASS_1" bitfld.long 0x00 0. "CACHE_LOCK,Unicache lock" "CACHE_LOCK_0,CACHE_LOCK_1" line.long 0x04 "CACHE_INT,Interrupt Register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 5.--8. "PORT,Slave interface number that has recorded an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4. "READ,Interface read response error" "0,1" newline bitfld.long 0x04 3. "WRITE,Interface write response error" "0,1" bitfld.long 0x04 2. "MAINT,Maintenance is completed" "0,1" bitfld.long 0x04 1. "PAGEFAULT,Unicache MMU page fault" "0,1" newline bitfld.long 0x04 0. "CONFIG,Configuration error" "0,1" line.long 0x08 "CACHE_OCP,Interface Configuration Register" hexmask.long 0x08 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 5. "CLEANBUF,Clean write and prefetch buffers in cache" "CLEANBUF_0,CLEANBUF_1" bitfld.long 0x08 4. "PREFETCH,Always prefetch data" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x08 3. "CACHED,Follow cacheable sideband signals" "CACHED_0,CACHED_1" bitfld.long 0x08 2. "WRALLOCATE,Follow write allocate sideband signals" "WRALLOCATE_0,WRALLOCATE_1" bitfld.long 0x08 1. "WRBUFFER,Write throughs and write back no allocate are buffered" "WRBUFFER_0,WRBUFFER_1" newline bitfld.long 0x08 0. "WRAP,OCP wrap mode (critical word first)" "WRAP_0,WRAP_1" line.long 0x0C "CACHE_MAINT,Maintenance Configuration Register" hexmask.long 0x0C 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 5. "INTERRUPT,Generate interrupt when maintenance operation is complete" "INTERRUPT_0,INTERRUPT_1" bitfld.long 0x0C 4. "INVALIDATE,Invalidate lines in region defined by maintenance start/end addresses" "INVALIDATE_0,INVALIDATE_1" newline bitfld.long 0x0C 3. "CLEAN,Evict dirty lines in region defined by maintenance start/end addresses" "CLEAN_0,CLEAN_1" bitfld.long 0x0C 2. "UNLOCK,Unlock region defined by maintenance start/end addresses" "UNLOCK_0,UNLOCK_1" bitfld.long 0x0C 1. "LOCK,Lock region defined by maintenance start/end addresses" "LOCK_0,LOCK_1" newline bitfld.long 0x0C 0. "PRELOAD,Preload region defined by maintenance start/end addresses" "PRELOAD_0,PRELOAD_1" line.long 0x10 "CACHE_MTSTART,Maintenance Start Configuration Register" line.long 0x14 "CACHE_MTEND,Maintenance End Configuration Register" line.long 0x18 "CACHE_CTADDR,Cache Test Address Register" line.long 0x1C "CACHE_CTDATA,Cache Test Data Register" line.long 0x20 "ECC_CFG,ECC configuration register" hexmask.long.tbyte 0x20 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 14. "L2RAM_SEC_AUTO_EN,Enables auto-correction of data in case of SEC error in L2 RAM" "0,1" bitfld.long 0x20 13. "L2RAM_SRESP_EN,Enables error response to master in case of DED error in L2 RAM" "0,1" newline bitfld.long 0x20 12. "L2RAM_DATA_MASK,L2 RAM ECC Code Mask register" "0,1" bitfld.long 0x20 11. "L2RAM_CODE_MASK,L2 RAM ECC Code Mask register" "0,1" bitfld.long 0x20 10. "L2RAM_ECC_EN,L2 RAM ECC enable" "0,1" newline bitfld.long 0x20 9. "L1TAG_SEC_AUTO_EN,Enables auto-correction of data in case of SEC error in L1 Tag" "0,1" bitfld.long 0x20 8. "RESERVED,Reserved" "0,1" bitfld.long 0x20 7. "L1TAG_DATA_MASK,L1 Tag ECC Code Mask register" "0,1" newline bitfld.long 0x20 6. "L1TAG_CODE_MASK,L1 Tag ECC Code Mask register" "0,1" bitfld.long 0x20 5. "L1TAG_ECC_EN,L1 Tag ECC enable" "0,1" bitfld.long 0x20 4. "L1DATA_SEC_AUTO_EN,Enables auto-correction of data in case of SEC error in L1 Data" "0,1" newline bitfld.long 0x20 3. "L1DATA_SRESP_EN,Enables error response to master in case of DED error in L1 Data" "0,1" bitfld.long 0x20 2. "L1DATA_DATA_MASK,L1 Data ECC Code Mask register" "0,1" bitfld.long 0x20 1. "L1DATA_CODE_MASK,L1 Data ECC Code Mask register" "0,1" newline bitfld.long 0x20 0. "L1DATA_ECC_EN,L1 Data ECC enable" "0,1" line.long 0x24 "L1DATA_ERR_INFO,L1 Data ECC information register" hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 3. "ACCESS_TYPE,Indicates what access type resulted in ECC error in L1 Data" "indicates access other..,eviction" bitfld.long 0x24 2. "DED,Indicates DED error in L1 Data" "0,1" newline bitfld.long 0x24 1. "CODE_ERR,Indicates SEC error in ECC code area of memory in L1 Data" "0,1" bitfld.long 0x24 0. "SEC,Indicates SEC error in L1 Data" "0,1" rgroup.long 0x30++0x07 line.long 0x00 "L1DATA_ERR_ADDR_LOC,Indicates address location of error occurence in L1 Data" line.long 0x04 "L1TAG_ERR_INFO,L1 Tag ECC information register" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 3. "ACCESS_TYPE,Indicates what access type resulted in ECC error in L1 Tag" "indicates access other..,eviction" bitfld.long 0x04 2. "DED,Indicates DED error in L1 Tag" "0,1" newline bitfld.long 0x04 1. "CODE_ERR,Indicates SEC error in ECC code area of memory in L1 Tag" "0,1" bitfld.long 0x04 0. "SEC,Indicates SEC error in L1 Tag" "0,1" rgroup.long 0x3C++0x07 line.long 0x00 "L1TAG_ERR_ADDR_LOC,Indicates address location of error occurence in L1 Data" line.long 0x04 "L2RAM_ERR_INFO,L2 RAM ECC information register" hexmask.long 0x04 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 5. "ACCESS_TYPE_MPORT,This bit is set whenever an access is made to L2RAM via the slave configuration interface" "0,1" bitfld.long 0x04 4. "ACCESS_TYPE_CACHE1,This bit is set whenever an access is made to L2RAM via the Unicache interface" "0,1" newline bitfld.long 0x04 3. "ACCESS_TYPE_CACHE2,This bit is reserved since L2 cache is not implemented in IPU subsystem" "0,1" bitfld.long 0x04 2. "DED,Indicates DED error in L2 RAM" "0,1" bitfld.long 0x04 1. "CODE_ERR,Indicates SEC error in ECC code area of memory in L2 RAM" "0,1" newline bitfld.long 0x04 0. "SEC,Indicates SEC error in L2 RAM" "0,1" rgroup.long 0x48++0x03 line.long 0x00 "L2RAM_ERR_ADDR_LOC,Indicates address location of error occurence in L2 RAM" width 0x0B tree.end tree "IPU_UNICACHE_MMU" base ad:0x58880800 group.long 0x00++0x0F line.long 0x00 "CACHE_MMU_LARGE_ADDR_i_0,Large page address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source address" hexmask.long 0x00 0.--24. 1. "RESERVED,Reserved" line.long 0x04 "CACHE_MMU_LARGE_ADDR_i_1,Large page address" hexmask.long.byte 0x04 25.--31. 1. "ADDRESS,Logical source address" hexmask.long 0x04 0.--24. 1. "RESERVED,Reserved" line.long 0x08 "CACHE_MMU_LARGE_ADDR_i_2,Large page address" hexmask.long.byte 0x08 25.--31. 1. "ADDRESS,Logical source address" hexmask.long 0x08 0.--24. 1. "RESERVED,Reserved" line.long 0x0C "CACHE_MMU_LARGE_ADDR_i_3,Large page address" hexmask.long.byte 0x0C 25.--31. 1. "ADDRESS,Logical source address" hexmask.long 0x0C 0.--24. 1. "RESERVED,Reserved" group.long 0x20++0x0F line.long 0x00 "CACHE_MMU_LARGE_XLTE_i_0,Large page translated address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.tbyte 0x00 1.--24. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" line.long 0x04 "CACHE_MMU_LARGE_XLTE_i_1,Large page translated address" hexmask.long.byte 0x04 25.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.tbyte 0x04 1.--24. 1. "RESERVED,Reserved" bitfld.long 0x04 0. "IGNORE,Do not use translated address" "0,1" line.long 0x08 "CACHE_MMU_LARGE_XLTE_i_2,Large page translated address" hexmask.long.byte 0x08 25.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.tbyte 0x08 1.--24. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "IGNORE,Do not use translated address" "0,1" line.long 0x0C "CACHE_MMU_LARGE_XLTE_i_3,Large page translated address" hexmask.long.byte 0x0C 25.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.tbyte 0x0C 1.--24. 1. "RESERVED,Reserved" bitfld.long 0x0C 0. "IGNORE,Do not use translated address" "0,1" group.long 0x40++0x0F line.long 0x00 "CACHE_MMU_LARGE_POLICY_i_0,Large page policy" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x00 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" newline bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" rbitfld.long 0x00 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x04 "CACHE_MMU_LARGE_POLICY_i_1,Large page policy" hexmask.long.word 0x04 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x04 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x04 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x04 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x04 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x04 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x04 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" newline bitfld.long 0x04 5. "READ,Read only" "0,1" bitfld.long 0x04 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x04 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" rbitfld.long 0x04 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x04 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x08 "CACHE_MMU_LARGE_POLICY_i_2,Large page policy" hexmask.long.word 0x08 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x08 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x08 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x08 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x08 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x08 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" newline bitfld.long 0x08 5. "READ,Read only" "0,1" bitfld.long 0x08 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x08 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" rbitfld.long 0x08 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x08 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x0C "CACHE_MMU_LARGE_POLICY_i_3,Large page policy" hexmask.long.word 0x0C 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x0C 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x0C 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x0C 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x0C 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x0C 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" newline bitfld.long 0x0C 5. "READ,Read only" "0,1" bitfld.long 0x0C 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x0C 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" rbitfld.long 0x0C 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x0C 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x60++0x07 line.long 0x00 "CACHE_MMU_MED_ADDR_j_0,Medium page address" hexmask.long.word 0x00 17.--31. 1. "ADDRESS,Logical source address" hexmask.long.tbyte 0x00 0.--16. 1. "RESERVED,Reserved" line.long 0x04 "CACHE_MMU_MED_ADDR_j_1,Medium page address" hexmask.long.word 0x04 17.--31. 1. "ADDRESS,Logical source address" hexmask.long.tbyte 0x04 0.--16. 1. "RESERVED,Reserved" group.long 0xA0++0x07 line.long 0x00 "CACHE_MMU_MED_XLTE_j_0,Medium page translated address" hexmask.long.word 0x00 17.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x00 1.--16. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" line.long 0x04 "CACHE_MMU_MED_XLTE_j_1,Medium page translated address" hexmask.long.word 0x04 17.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x04 1.--16. 1. "RESERVED,Reserved" bitfld.long 0x04 0. "IGNORE,Do not use translated address" "0,1" group.long 0xE0++0x07 line.long 0x00 "CACHE_MMU_MED_POLICY_j_0,Medium page policy" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x00 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" newline bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x04 "CACHE_MMU_MED_POLICY_j_1,Medium page policy" hexmask.long.word 0x04 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x04 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x04 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x04 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x04 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x04 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x04 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" newline bitfld.long 0x04 5. "READ,Read only" "0,1" bitfld.long 0x04 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x04 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x04 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x04 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x120++0x27 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_0,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reserved" line.long 0x04 "CACHE_MMU_SMALL_ADDR_k_1,Small page address" hexmask.long.tbyte 0x04 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x04 0.--11. 1. "RESERVED,Reserved" line.long 0x08 "CACHE_MMU_SMALL_ADDR_k_2,Small page address" hexmask.long.tbyte 0x08 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x08 0.--11. 1. "RESERVED,Reserved" line.long 0x0C "CACHE_MMU_SMALL_ADDR_k_3,Small page address" hexmask.long.tbyte 0x0C 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x0C 0.--11. 1. "RESERVED,Reserved" line.long 0x10 "CACHE_MMU_SMALL_ADDR_k_4,Small page address" hexmask.long.tbyte 0x10 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x10 0.--11. 1. "RESERVED,Reserved" line.long 0x14 "CACHE_MMU_SMALL_ADDR_k_5,Small page address" hexmask.long.tbyte 0x14 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x14 0.--11. 1. "RESERVED,Reserved" line.long 0x18 "CACHE_MMU_SMALL_ADDR_k_6,Small page address" hexmask.long.tbyte 0x18 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x18 0.--11. 1. "RESERVED,Reserved" line.long 0x1C "CACHE_MMU_SMALL_ADDR_k_7,Small page address" hexmask.long.tbyte 0x1C 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x1C 0.--11. 1. "RESERVED,Reserved" line.long 0x20 "CACHE_MMU_SMALL_ADDR_k_8,Small page address" hexmask.long.tbyte 0x20 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x20 0.--11. 1. "RESERVED,Reserved" line.long 0x24 "CACHE_MMU_SMALL_ADDR_k_9,Small page address" hexmask.long.tbyte 0x24 12.--31. 1. "ADDRESS,Logical source address" hexmask.long.word 0x24 0.--11. 1. "RESERVED,Reserved" group.long 0x1A0++0x27 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_0,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" line.long 0x04 "CACHE_MMU_SMALL_XLTE_k_1,Small page translated address" hexmask.long.tbyte 0x04 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x04 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x04 0. "IGNORE,Do not use translated address" "0,1" line.long 0x08 "CACHE_MMU_SMALL_XLTE_k_2,Small page translated address" hexmask.long.tbyte 0x08 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x08 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "IGNORE,Do not use translated address" "0,1" line.long 0x0C "CACHE_MMU_SMALL_XLTE_k_3,Small page translated address" hexmask.long.tbyte 0x0C 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x0C 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x0C 0. "IGNORE,Do not use translated address" "0,1" line.long 0x10 "CACHE_MMU_SMALL_XLTE_k_4,Small page translated address" hexmask.long.tbyte 0x10 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x10 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x10 0. "IGNORE,Do not use translated address" "0,1" line.long 0x14 "CACHE_MMU_SMALL_XLTE_k_5,Small page translated address" hexmask.long.tbyte 0x14 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x14 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x14 0. "IGNORE,Do not use translated address" "0,1" line.long 0x18 "CACHE_MMU_SMALL_XLTE_k_6,Small page translated address" hexmask.long.tbyte 0x18 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x18 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x18 0. "IGNORE,Do not use translated address" "0,1" line.long 0x1C "CACHE_MMU_SMALL_XLTE_k_7,Small page translated address" hexmask.long.tbyte 0x1C 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x1C 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x1C 0. "IGNORE,Do not use translated address" "0,1" line.long 0x20 "CACHE_MMU_SMALL_XLTE_k_8,Small page translated address" hexmask.long.tbyte 0x20 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x20 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x20 0. "IGNORE,Do not use translated address" "0,1" line.long 0x24 "CACHE_MMU_SMALL_XLTE_k_9,Small page translated address" hexmask.long.tbyte 0x24 12.--31. 1. "ADDRESS,Logical source translated address" hexmask.long.word 0x24 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x24 0. "IGNORE,Do not use translated address" "0,1" group.long 0x220++0x27 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_0,Small page policy" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x00 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x00 2. "RESERVED,Reserved" "0,1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x04 "CACHE_MMU_SMALL_POLICY_k_1,Small page policy" hexmask.long.word 0x04 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x04 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x04 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x04 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x04 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x04 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x04 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x04 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x04 5. "READ,Read only" "0,1" bitfld.long 0x04 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x04 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x04 2. "RESERVED,Reserved" "0,1" bitfld.long 0x04 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x04 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x08 "CACHE_MMU_SMALL_POLICY_k_2,Small page policy" hexmask.long.word 0x08 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x08 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x08 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x08 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x08 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x08 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x08 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x08 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x08 5. "READ,Read only" "0,1" bitfld.long 0x08 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x08 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x08 2. "RESERVED,Reserved" "0,1" bitfld.long 0x08 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x08 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x0C "CACHE_MMU_SMALL_POLICY_k_3,Small page policy" hexmask.long.word 0x0C 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x0C 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x0C 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x0C 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x0C 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x0C 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x0C 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x0C 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x0C 5. "READ,Read only" "0,1" bitfld.long 0x0C 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x0C 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x0C 2. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x0C 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x10 "CACHE_MMU_SMALL_POLICY_k_4,Small page policy" hexmask.long.word 0x10 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x10 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x10 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x10 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x10 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x10 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x10 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x10 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x10 5. "READ,Read only" "0,1" bitfld.long 0x10 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x10 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x10 2. "RESERVED,Reserved" "0,1" bitfld.long 0x10 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x10 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x14 "CACHE_MMU_SMALL_POLICY_k_5,Small page policy" hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x14 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x14 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x14 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x14 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x14 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x14 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x14 5. "READ,Read only" "0,1" bitfld.long 0x14 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x14 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x14 2. "RESERVED,Reserved" "0,1" bitfld.long 0x14 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x14 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x18 "CACHE_MMU_SMALL_POLICY_k_6,Small page policy" hexmask.long.word 0x18 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x18 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x18 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x18 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x18 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x18 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x18 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x18 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x18 5. "READ,Read only" "0,1" bitfld.long 0x18 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x18 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x18 2. "RESERVED,Reserved" "0,1" bitfld.long 0x18 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x18 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x1C "CACHE_MMU_SMALL_POLICY_k_7,Small page policy" hexmask.long.word 0x1C 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x1C 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x1C 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x1C 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x1C 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x1C 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x1C 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x1C 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x1C 5. "READ,Read only" "0,1" bitfld.long 0x1C 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x1C 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x1C 2. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x1C 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x20 "CACHE_MMU_SMALL_POLICY_k_8,Small page policy" hexmask.long.word 0x20 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x20 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x20 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x20 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x20 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x20 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x20 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x20 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x20 5. "READ,Read only" "0,1" bitfld.long 0x20 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x20 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x20 2. "RESERVED,Reserved" "0,1" bitfld.long 0x20 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x20 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" line.long 0x24 "CACHE_MMU_SMALL_POLICY_k_9,Small page policy" hexmask.long.word 0x24 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x24 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x24 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" newline bitfld.long 0x24 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" hexmask.long.byte 0x24 9.--15. 1. "RESERVED,Reserved" rbitfld.long 0x24 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x24 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" newline bitfld.long 0x24 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x24 5. "READ,Read only" "0,1" bitfld.long 0x24 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x24 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" newline bitfld.long 0x24 2. "RESERVED,Reserved" "0,1" bitfld.long 0x24 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x24 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x2A0++0x27 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_0,Small page maintenance configuration" hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x00 1. "LOCK,Lock page" "0,1" bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" line.long 0x04 "CACHE_MMU_SMALL_MAINT_k_1,Small page maintenance configuration" hexmask.long 0x04 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x04 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x04 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x04 1. "LOCK,Lock page" "0,1" bitfld.long 0x04 0. "PRELOAD,Preload page" "0,1" line.long 0x08 "CACHE_MMU_SMALL_MAINT_k_2,Small page maintenance configuration" hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x08 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x08 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x08 1. "LOCK,Lock page" "0,1" bitfld.long 0x08 0. "PRELOAD,Preload page" "0,1" line.long 0x0C "CACHE_MMU_SMALL_MAINT_k_3,Small page maintenance configuration" hexmask.long 0x0C 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x0C 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x0C 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x0C 1. "LOCK,Lock page" "0,1" bitfld.long 0x0C 0. "PRELOAD,Preload page" "0,1" line.long 0x10 "CACHE_MMU_SMALL_MAINT_k_4,Small page maintenance configuration" hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x10 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x10 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x10 1. "LOCK,Lock page" "0,1" bitfld.long 0x10 0. "PRELOAD,Preload page" "0,1" line.long 0x14 "CACHE_MMU_SMALL_MAINT_k_5,Small page maintenance configuration" hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x14 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x14 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x14 1. "LOCK,Lock page" "0,1" bitfld.long 0x14 0. "PRELOAD,Preload page" "0,1" line.long 0x18 "CACHE_MMU_SMALL_MAINT_k_6,Small page maintenance configuration" hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x18 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x18 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x18 1. "LOCK,Lock page" "0,1" bitfld.long 0x18 0. "PRELOAD,Preload page" "0,1" line.long 0x1C "CACHE_MMU_SMALL_MAINT_k_7,Small page maintenance configuration" hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x1C 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x1C 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x1C 1. "LOCK,Lock page" "0,1" bitfld.long 0x1C 0. "PRELOAD,Preload page" "0,1" line.long 0x20 "CACHE_MMU_SMALL_MAINT_k_8,Small page maintenance configuration" hexmask.long 0x20 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x20 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x20 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x20 1. "LOCK,Lock page" "0,1" bitfld.long 0x20 0. "PRELOAD,Preload page" "0,1" line.long 0x24 "CACHE_MMU_SMALL_MAINT_k_9,Small page maintenance configuration" hexmask.long 0x24 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x24 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x24 2. "CLEAN,Evict page" "0,1" newline bitfld.long 0x24 1. "LOCK,Lock page" "0,1" bitfld.long 0x24 0. "PRELOAD,Preload page" "0,1" group.long 0x4A8++0x13 line.long 0x00 "CACHE_MMU_MAINT,Maintenance configuration register" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 10. "G_FLUSH,Global flush bit" "G_FLUSH_0,G_FLUSH_1" bitfld.long 0x00 8.--9. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x00 7. "L1_CACHE1,Do maintenance operation in L1 cache" "L1_CACHE1_0,L1_CACHE1_1" newline bitfld.long 0x00 6. "CPU_INTERRUPT,Generate interrupt to cpu when maintenance operation initiated by CPU is complete" "CPU_INTERRUPT_0,CPU_INTERRUPT_1" bitfld.long 0x00 5. "HOST_INTERRUPT,Generate interrupt when maintenance operation is complete" "HOST_INTERRUPT_0,HOST_INTERRUPT_1" bitfld.long 0x00 4. "INVALIDATE,Invalidate lines in region defined by maintenance start/end addresses" "INVALIDATE_0,INVALIDATE_1" bitfld.long 0x00 3. "CLEAN,Evict dirty lines in region defined by maintenance start/end addresses" "CLEAN_0,CLEAN_1" newline bitfld.long 0x00 2. "UNLOCK,Unlock region defined by maintenance start/end addresses" "UNLOCK_0,UNLOCK_1" bitfld.long 0x00 1. "LOCK,Lock region defined by maintenance start/end addresses" "LOCK_0,LOCK_1" bitfld.long 0x00 0. "PRELOAD,Preload region defined by maintenance start/end addresses" "PRELOAD_0,PRELOAD_1" line.long 0x04 "CACHE_MMU_MTSTART,Maintenance start configuratoin register" line.long 0x08 "CACHE_MMU_MTEND,Maintenance end configuration register" line.long 0x0C "CACHE_MMU_MAINTST,Maintenance status register" hexmask.long 0x0C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 0. "STATUS,Status bit" "STATUS_0_r,STATUS_1_r" line.long 0x10 "CACHE_MMU_MMUCONFIG,MMU configuration register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "PRIVILEGE,Privilege bit" "PRIVILEGE_0,PRIVILEGE_1" bitfld.long 0x10 0. "MMU_LOCK,MMU lock" "MMU_LOCK_0,MMU_LOCK_1" width 0x0B tree.end tree "IPU_UNICACHE_SCTM" base ad:0x58880400 group.long 0x00++0x03 line.long 0x00 "CACHE_SCTM_CTCNTL," rbitfld.long 0x00 26.--31. "NUMSTM,Number of timers that can export via STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 18.--25. 1. "NUMINPT,Number of event input signals" rbitfld.long 0x00 13.--17. "NUMTIMR,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 7.--12. "NUMCNTR,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 3.--6. "REVISION,Revision ID of SCTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. "IDLEMODE,Idle mode control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 0. "ENBL,SCTM global enable" "ENBL_0,ENBL_1" group.long 0x40++0x07 line.long 0x00 "CACHE_SCTM_TINTVLR_i_0,These registers contain the interval match value for the corresponding timers in the SCTM" line.long 0x04 "CACHE_SCTM_TINTVLR_i_1,These registers contain the interval match value for the corresponding timers in the SCTM" rgroup.long 0x7C++0x03 line.long 0x00 "CACHE_SCTM_CTDBGNUM,Counter Timer Number Debug Event Register" hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0.--2. "NUMEVT,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" group.long 0xF0++0x03 line.long 0x00 "CACHE_SCTM_CTGNBL,These registers provide for simultaneous enable/disable of 32 counters" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x00 0.--7. 1. "ENABLE,The counter enable bit field" group.long 0xF8++0x03 line.long 0x00 "CACHE_SCTM_CTGRST,These registers provide for simultaneous reset of 32 counters" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x00 0.--7. 1. "RESET,The counter reset bit field" group.long 0x100++0x1F line.long 0x00 "CACHE_SCTM_CTCR_WT_i_0,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection1-31: Index of event input signal selected" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 11.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "RESTART_0,RESTART_1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "DBG_0,DBG_1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "INT_0,INT_1" newline rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "OVRFLW_0,OVRFLW_1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" newline bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" line.long 0x04 "CACHE_SCTM_CTCR_WT_i_1,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x04 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 16.--20. "INPSEL,Counter Timer input selection1-31: Index of event input signal selected" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 11.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 10. "RESTART,Restart the timer after an interval match" "RESTART_0,RESTART_1" bitfld.long 0x04 9. "DBG,Signal debug logic on interval match" "DBG_0,DBG_1" bitfld.long 0x04 8. "INT,Generate interrupt on interval match" "INT_0,INT_1" newline rbitfld.long 0x04 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x04 6. "OVRFLW,Counter has wrapped since it was last" "OVRFLW_0,OVRFLW_1" bitfld.long 0x04 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x04 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x04 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x04 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" newline bitfld.long 0x04 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x04 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" line.long 0x08 "CACHE_SCTM_CTCR_WOT_j_0,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x08 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 16.--20. "INPSEL,Counter input selection1-31: Index of event input signal selected" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" hexmask.long.byte 0x08 8.--15. 1. "RESERVED,Reserved" rbitfld.long 0x08 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x08 6. "OVRFLW,Counter has wrapped since it was last" "OVRFLW_0,OVRFLW_1" bitfld.long 0x08 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" newline bitfld.long 0x08 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x08 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x08 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x08 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x08 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" line.long 0x0C "CACHE_SCTM_CTCR_WOT_j_1,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x0C 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 16.--20. "INPSEL,Counter input selection1-31: Index of event input signal selected" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" hexmask.long.byte 0x0C 8.--15. 1. "RESERVED,Reserved" rbitfld.long 0x0C 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x0C 6. "OVRFLW,Counter has wrapped since it was last" "OVRFLW_0,OVRFLW_1" bitfld.long 0x0C 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" newline bitfld.long 0x0C 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x0C 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x0C 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x0C 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x0C 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" line.long 0x10 "CACHE_SCTM_CTCR_WOT_j_2,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x10 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 16.--20. "INPSEL,Counter input selection1-31: Index of event input signal selected" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" hexmask.long.byte 0x10 8.--15. 1. "RESERVED,Reserved" rbitfld.long 0x10 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x10 6. "OVRFLW,Counter has wrapped since it was last" "OVRFLW_0,OVRFLW_1" bitfld.long 0x10 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" newline bitfld.long 0x10 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x10 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x10 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x10 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x10 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" line.long 0x14 "CACHE_SCTM_CTCR_WOT_j_3,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x14 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 16.--20. "INPSEL,Counter input selection1-31: Index of event input signal selected" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" hexmask.long.byte 0x14 8.--15. 1. "RESERVED,Reserved" rbitfld.long 0x14 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x14 6. "OVRFLW,Counter has wrapped since it was last" "OVRFLW_0,OVRFLW_1" bitfld.long 0x14 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" newline bitfld.long 0x14 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x14 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x14 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x14 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x14 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" line.long 0x18 "CACHE_SCTM_CTCR_WOT_j_4,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x18 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 16.--20. "INPSEL,Counter input selection1-31: Index of event input signal selected" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" hexmask.long.byte 0x18 8.--15. 1. "RESERVED,Reserved" rbitfld.long 0x18 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x18 6. "OVRFLW,Counter has wrapped since it was last" "OVRFLW_0,OVRFLW_1" bitfld.long 0x18 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" newline bitfld.long 0x18 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x18 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x18 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x18 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x18 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" line.long 0x1C "CACHE_SCTM_CTCR_WOT_j_5,These registers contain the control and status settings for a single counter in the module" hexmask.long.word 0x1C 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 16.--20. "INPSEL,Counter input selection1-31: Index of event input signal selected" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" hexmask.long.byte 0x1C 8.--15. 1. "RESERVED,Reserved" rbitfld.long 0x1C 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x1C 6. "OVRFLW,Counter has wrapped since it was last" "OVRFLW_0,OVRFLW_1" bitfld.long 0x1C 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" newline bitfld.long 0x1C 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x1C 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x1C 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x1C 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x1C 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" rgroup.long 0x180++0x1F line.long 0x00 "CACHE_SCTM_CTCNTR_k_0,These registers contain the value of an individual counter in the module" line.long 0x04 "CACHE_SCTM_CTCNTR_k_1,These registers contain the value of an individual counter in the module" line.long 0x08 "CACHE_SCTM_CTCNTR_k_2,These registers contain the value of an individual counter in the module" line.long 0x0C "CACHE_SCTM_CTCNTR_k_3,These registers contain the value of an individual counter in the module" line.long 0x10 "CACHE_SCTM_CTCNTR_k_4,These registers contain the value of an individual counter in the module" line.long 0x14 "CACHE_SCTM_CTCNTR_k_5,These registers contain the value of an individual counter in the module" line.long 0x18 "CACHE_SCTM_CTCNTR_k_6,These registers contain the value of an individual counter in the module" line.long 0x1C "CACHE_SCTM_CTCNTR_k_7,These registers contain the value of an individual counter in the module" width 0x0B tree.end tree "IPU_WUGEN" base ad:0x58881000 group.long 0x00++0x13 line.long 0x00 "CORTEXM4_CTRL_REG,The register is used by one CPU to interrupt the other. thus used as a handshake between the two CPUs" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "INT_CORTEX_2,Interrupt to IPU_C1" "0,1" hexmask.long.word 0x00 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "INT_CORTEX_1,Interrupt to IPU_C0" "0,1" line.long 0x04 "STANDBY_CORE_SYSCONFIG,Standby protocol" hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 0.--1. "STANDBYMODE," "?,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" line.long 0x08 "IDLE_CORE_SYSCONFIG,Idle protocol" hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0.--1. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" line.long 0x0C "WUGEN_MEVT0,This register contains the interrupt mask (LSB) wake-up enable bit per interrupt request" bitfld.long 0x0C 31. "MIRQ31,Interrupt Mask bit 31" "0,1" bitfld.long 0x0C 30. "MIRQ30,Interrupt Mask bit 30" "0,1" bitfld.long 0x0C 29. "MIRQ29,Interrupt Mask bit 29" "0,1" bitfld.long 0x0C 28. "MIRQ28,Interrupt Mask bit 28" "0,1" bitfld.long 0x0C 27. "MIRQ27,Interrupt Mask bit 27" "0,1" bitfld.long 0x0C 26. "MIRQ26,Interrupt Mask bit 26" "0,1" newline bitfld.long 0x0C 25. "MIRQ25,Interrupt Mask bit 25" "0,1" bitfld.long 0x0C 24. "MIRQ24,Interrupt Mask bit 24" "0,1" bitfld.long 0x0C 23. "MIRQ23,Interrupt Mask bit 23" "0,1" bitfld.long 0x0C 22. "MIRQ22,Interrupt Mask bit 22" "0,1" bitfld.long 0x0C 21. "MIRQ21,Interrupt Mask bit 21" "0,1" bitfld.long 0x0C 20. "MIRQ20,Interrupt Mask bit 20" "0,1" newline bitfld.long 0x0C 19. "MIRQ19,Interrupt Mask bit 19" "0,1" bitfld.long 0x0C 18. "MIRQ18,Interrupt Mask bit 18" "0,1" bitfld.long 0x0C 17. "MIRQ17,Interrupt Mask bit 17" "0,1" bitfld.long 0x0C 16. "MIRQ16,Interrupt Mask bit 16" "0,1" bitfld.long 0x0C 15. "MIRQ15,Interrupt Mask bit 15" "0,1" bitfld.long 0x0C 14. "MIRQ14,Interrupt Mask bit 14" "0,1" newline bitfld.long 0x0C 13. "MIRQ13,Interrupt Mask bit 13" "0,1" bitfld.long 0x0C 12. "MIRQ12,Interrupt Mask bit 12" "0,1" bitfld.long 0x0C 11. "MIRQ11,Interrupt Mask bit 11" "0,1" bitfld.long 0x0C 10. "MIRQ10,Interrupt Mask bit 10" "0,1" bitfld.long 0x0C 9. "MIRQ9,Interrupt Mask bit 9" "0,1" bitfld.long 0x0C 8. "MIRQ8,Interrupt Mask bit 8" "0,1" newline bitfld.long 0x0C 7. "MIRQ7,Interrupt Mask bit 7" "0,1" bitfld.long 0x0C 6. "MIRQ6,Interrupt Mask bit 6" "0,1" bitfld.long 0x0C 5. "MIRQ5,Interrupt Mask bit 5" "0,1" bitfld.long 0x0C 4. "MIRQ4,Interrupt Mask bit 4" "0,1" bitfld.long 0x0C 3. "MIRQ3,Interrupt Mask bit 3" "0,1" bitfld.long 0x0C 2. "MIRQ2,Interrupt Mask bit 2" "0,1" newline bitfld.long 0x0C 1. "MIRQ1,Interrupt Mask bit 1" "0,1" bitfld.long 0x0C 0. "MIRQ0,Interrupt Mask bit 0" "0,1" line.long 0x10 "WUGEN_MEVT1,This register contains the interrupt mask (MSB) wake-up enable bit per interrupt request" bitfld.long 0x10 31. "MIRQ63,Interrupt Mask bit 63" "0,1" bitfld.long 0x10 30. "MIRQ62,Interrupt Mask bit 62" "0,1" bitfld.long 0x10 29. "MIRQ61,Interrupt Mask bit 61" "0,1" bitfld.long 0x10 28. "MIRQ60,Interrupt Mask bit 60" "0,1" bitfld.long 0x10 27. "MIRQ59,Interrupt Mask bit 59" "0,1" bitfld.long 0x10 26. "MIRQ58,Interrupt Mask bit 58" "0,1" newline bitfld.long 0x10 25. "MIRQ57,Interrupt Mask bit 57" "0,1" bitfld.long 0x10 24. "MIRQ56,Interrupt Mask bit 56" "0,1" bitfld.long 0x10 23. "MIRQ55,Interrupt Mask bit 55" "0,1" bitfld.long 0x10 22. "MIRQ54,Interrupt Mask bit 54" "0,1" bitfld.long 0x10 21. "MIRQ53,Interrupt Mask bit 53" "0,1" bitfld.long 0x10 20. "MIRQ52,Interrupt Mask bit 52" "0,1" newline bitfld.long 0x10 19. "MIRQ51,Interrupt Mask bit 51" "0,1" bitfld.long 0x10 18. "MIRQ50,Interrupt Mask bit 50" "0,1" bitfld.long 0x10 17. "MIRQ49,Interrupt Mask bit 49" "0,1" bitfld.long 0x10 16. "MIRQ48,Interrupt Mask bit 48" "0,1" bitfld.long 0x10 15. "MIRQ47,Interrupt Mask bit 47" "0,1" bitfld.long 0x10 14. "MIRQ46,Interrupt Mask bit 46" "0,1" newline bitfld.long 0x10 13. "MIRQ45,Interrupt Mask bit 45" "0,1" bitfld.long 0x10 12. "MIRQ44,Interrupt Mask bit 44" "0,1" bitfld.long 0x10 11. "MIRQ43,Interrupt Mask bit 43" "0,1" bitfld.long 0x10 10. "MIRQ42,Interrupt Mask bit 42" "0,1" bitfld.long 0x10 9. "MIRQ41,Interrupt Mask bit 41" "0,1" bitfld.long 0x10 8. "MIRQ40,Interrupt Mask bit 40" "0,1" newline bitfld.long 0x10 7. "MIRQ39,Interrupt Mask bit 39" "0,1" bitfld.long 0x10 6. "MIRQ38,Interrupt Mask bit 38" "0,1" bitfld.long 0x10 5. "MIRQ37,Interrupt Mask bit 37" "0,1" bitfld.long 0x10 4. "MIRQ36,Interrupt Mask bit 36" "0,1" bitfld.long 0x10 3. "MIRQ35,Interrupt Mask bit 35" "0,1" bitfld.long 0x10 2. "MIRQ34,Interrupt Mask bit 34" "0,1" newline bitfld.long 0x10 1. "MIRQ33,Interrupt Mask bit 33" "0,1" bitfld.long 0x10 0. "MIRQ32,Interrupt Mask bit 32" "0,1" width 0x0B tree.end tree "ISS_CM_CORE_AON" base ad:0x4A005760 group.long 0x00++0x0B line.long 0x00 "CM_ISS_CLKSTCTRL,This register enables the ISS domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_ISS_GCLK,This field indicates the state of the ISS_GCLK clock in the domain" "CLKACTIVITY_ISS_GCLK_0,CLKACTIVITY_ISS_GCLK_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_ISS_ISS_CLKCTRL,This register manages the ISS clocks" hexmask.long.word 0x04 19.--31. 1. "RESERVED," rbitfld.long 0x04 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x04 2.--15. 1. "RESERVED," bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x08 "CM_ISS_STATICDEP,This register controls the static domain depedencies from ISS domain towards 'target' domains" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" hexmask.long.tbyte 0x08 6.--26. 1. "RESERVED," newline rbitfld.long 0x08 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" bitfld.long 0x08 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x08 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "ISS_FW" base ad:0x4A23E000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" newline rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "ISS_FW_CFG_TARG" base ad:0x4A23F000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "ISS_PRM" base ad:0x4AE07C80 group.long 0x00++0x07 line.long 0x00 "PM_ISS_PWRSTCTRL,This register controls the ISS power state to reach upon a domain sleep transition" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "ISS_BANK_ONSTATE,ISS_BANK state when domain is ON" "?,?,?,ISS_BANK_ONSTATE_3" hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "ISS_BANK_RETSTATE,ISS_BANK state when domain is RETENTION" "ISS_BANK_RETSTATE_0,ISS_BANK_RETSTATE_1" rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION" "LOGICRETSTATE_0,LOGICRETSTATE_1" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_ISS_PWRSTST,This register provides a status on the ISS domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" hexmask.long.word 0x04 6.--19. 1. "RESERVED," rbitfld.long 0x04 4.--5. "ISS_BANK_STATEST,ISS_BANK memory state status" "ISS_BANK_STATEST_0,ISS_BANK_STATEST_1,ISS_BANK_STATEST_2,ISS_BANK_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x20++0x07 line.long 0x00 "PM_ISS_ISS_WKDEP,This register controls wakeup dependency based on ISS service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_ISS_EVE4,Wakeup dependency from ISS module (Swakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_EVE4_0,WKUPDEP_ISS_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_ISS_EVE3,Wakeup dependency from ISS module (Swakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_EVE3_0,WKUPDEP_ISS_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_ISS_EVE2,Wakeup dependency from ISS module (Swakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_EVE2_0,WKUPDEP_ISS_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_ISS_EVE1,Wakeup dependency from ISS module ( Swakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_EVE1_0,WKUPDEP_ISS_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_ISS_DSP2,Wakeup dependency from ISS module (Swakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_DSP2_0,WKUPDEP_ISS_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_ISS_IPU1,Wakeup dependency from ISS module (Swakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_IPU1_0,WKUPDEP_ISS_IPU1_1" rbitfld.long 0x00 3. "RESERVED," "0,1" bitfld.long 0x00 2. "WKUPDEP_ISS_DSP1,Wakeup dependency from ISS module (Swakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_DSP1_0,WKUPDEP_ISS_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_ISS_IPU2,Wakeup dependency from ISS module ( Swakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_IPU2_0,WKUPDEP_ISS_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_ISS_MPU,Wakeup dependency from ISS module (Swakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ISS_MPU_0,WKUPDEP_ISS_MPU_1" line.long 0x04 "RM_ISS_ISS_CONTEXT,This register contains dedicated ISS context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_ISS_BANK,Specify if memory-based context in ISS memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_ISS_BANK_0,LOSTMEM_ISS_BANK_1" hexmask.long.byte 0x04 1.--7. 1. "RESERVED," newline bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "ISS_TARG" base ad:0x44000800 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "IVA_CM_CORE" base ad:0x4A008F00 group.long 0x00++0x0B line.long 0x00 "CM_IVA_CLKSTCTRL,This register enables the IVA domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_IVA_GCLK,This field indicates the state of the IVA_ROOT_CLK clock input of the domain" "CLKACTIVITY_IVA_GCLK_0,CLKACTIVITY_IVA_GCLK_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the IVA clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_IVA_STATICDEP,This register controls the static domain depedencies from IVA domain towards 'target' domains" hexmask.long 0x04 6.--31. 1. "RESERVED," rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "CM_IVA_DYNAMICDEP,This register controls the dynamic domain depedencies from IVA domain towards 'target' domains" hexmask.long 0x08 6.--31. 1. "RESERVED," bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "L3MAIN1_DYNDEP_0,?" bitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20++0x03 line.long 0x00 "CM_IVA_IVA_CLKCTRL,This register manages the IVA clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x28++0x03 line.long 0x00 "CM_IVA_SL2_CLKCTRL,This register manages the SL2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "IVA_PRM" base ad:0x4AE06F00 group.long 0x00++0x07 line.long 0x00 "PM_IVA_PWRSTCTRL,This register controls the IVA power state to reach upon a domain sleep transition" hexmask.long.byte 0x00 24.--31. 1. "RESERVED," rbitfld.long 0x00 22.--23. "TCM2_MEM_ONSTATE,TCM_CORE memory state when domain is ON" "?,?,?,TCM2_MEM_ONSTATE_3" newline rbitfld.long 0x00 20.--21. "TCM1_MEM_ONSTATE,TCM1 memory state when domain is ON" "?,?,?,TCM1_MEM_ONSTATE_3" rbitfld.long 0x00 18.--19. "SL2_MEM_ONSTATE,SL2 memory state when domain is ON" "?,?,?,SL2_MEM_ONSTATE_3" newline rbitfld.long 0x00 16.--17. "HWA_MEM_ONSTATE,HWA memory state when domain is ON" "?,?,?,HWA_MEM_ONSTATE_3" rbitfld.long 0x00 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 11. "TCM2_MEM_RETSTATE,TCM2 memory state when domain is RETENTION" "TCM2_MEM_RETSTATE_0,TCM2_MEM_RETSTATE_1" bitfld.long 0x00 10. "TCM1_MEM_RETSTATE,TCM1 memory state when domain is RETENTION" "TCM1_MEM_RETSTATE_0,TCM1_MEM_RETSTATE_1" newline bitfld.long 0x00 9. "SL2_MEM_RETSTATE,SL2 memory state when domain is RETENTION" "SL2_MEM_RETSTATE_0,SL2_MEM_RETSTATE_1" rbitfld.long 0x00 8. "HWA_MEM_RETSTATE,HWA memory state when domain is RETENTION" "HWA_MEM_RETSTATE_0,?" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" rbitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION" "LOGICRETSTATE_0,?" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_IVA_PWRSTST,This register provides a status on the current IVA power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.byte 0x04 12.--19. 1. "RESERVED," rbitfld.long 0x04 10.--11. "TCM2_MEM_STATEST,TCM2 memory state status" "TCM2_MEM_STATEST_0,TCM2_MEM_STATEST_1,TCM2_MEM_STATEST_2,TCM2_MEM_STATEST_3" newline rbitfld.long 0x04 8.--9. "TCM1_MEM_STATEST,TCM1 memory state status" "TCM1_MEM_STATEST_0,TCM1_MEM_STATEST_1,TCM1_MEM_STATEST_2,TCM1_MEM_STATEST_3" rbitfld.long 0x04 6.--7. "SL2_MEM_STATEST,SL2 memory state status" "SL2_MEM_STATEST_0,SL2_MEM_STATEST_1,SL2_MEM_STATEST_2,SL2_MEM_STATEST_3" newline rbitfld.long 0x04 4.--5. "HWA_MEM_STATEST,HWA memory state status" "HWA_MEM_STATEST_0,HWA_MEM_STATEST_1,HWA_MEM_STATEST_2,HWA_MEM_STATEST_3" rbitfld.long 0x04 3. "RESERVED," "0,1" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_IVA_RSTCTRL,This register controls the release of the IVA sub-system resets" hexmask.long 0x00 3.--31. 1. "RESERVED," bitfld.long 0x00 2. "RST_LOGIC,IVA logic and SL2 reset control" "RST_LOGIC_0,RST_LOGIC_1" newline bitfld.long 0x00 1. "RST_SEQ2,IVA Sequencer2 reset control" "RST_SEQ2_0,RST_SEQ2_1" bitfld.long 0x00 0. "RST_SEQ1,IVA sequencer1 reset control" "RST_SEQ1_0,RST_SEQ1_1" line.long 0x04 "RM_IVA_RSTST,This register logs the different reset sources of the IVA domain" hexmask.long 0x04 7.--31. 1. "RESERVED," bitfld.long 0x04 6. "RST_ICECRUSHER_SEQ2,Sequencer2 CPU has been reset due to IVA ICECRUSHER2 reset event" "RST_ICECRUSHER_SEQ2_0,RST_ICECRUSHER_SEQ2_1" newline bitfld.long 0x04 5. "RST_ICECRUSHER_SEQ1,Sequencer1 CPU has been reset due to IVA ICECRUSHER1 reset event" "RST_ICECRUSHER_SEQ1_0,RST_ICECRUSHER_SEQ1_1" bitfld.long 0x04 4. "RST_EMULATION_SEQ2,Sequencer2 CPU has been reset due to emulation reset source e.g" "RST_EMULATION_SEQ2_0,RST_EMULATION_SEQ2_1" newline bitfld.long 0x04 3. "RST_EMULATION_SEQ1,Sequencer1 CPU has been reset due to emulation reset source e.g" "RST_EMULATION_SEQ1_0,RST_EMULATION_SEQ1_1" bitfld.long 0x04 2. "RST_LOGIC,IVA logic and SL2 SW reset" "RST_LOGIC_0,RST_LOGIC_1" newline bitfld.long 0x04 1. "RST_SEQ2,IVA Sequencer2 CPU SW reset" "RST_SEQ2_0,RST_SEQ2_1" bitfld.long 0x04 0. "RST_SEQ1,IVA Sequencer1 CPU SW reset" "RST_SEQ1_0,RST_SEQ1_1" group.long 0x24++0x03 line.long 0x00 "RM_IVA_IVA_CONTEXT,This register contains dedicated IVA context statuses" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," bitfld.long 0x00 10. "LOSTMEM_HWA_MEM,Specify if memory-based context in HWA_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_HWA_MEM_0,LOSTMEM_HWA_MEM_1" newline bitfld.long 0x00 9. "LOSTMEM_TCM2_MEM,Specify if memory-based context in TCM2_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_TCM2_MEM_0,LOSTMEM_TCM2_MEM_1" bitfld.long 0x00 8. "LOSTMEM_TCM1_MEM,Specify if memory-based context in TCM1_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_TCM1_MEM_0,LOSTMEM_TCM1_MEM_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x2C++0x03 line.long 0x00 "RM_IVA_SL2_CONTEXT,This register contains dedicated SL2 context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_SL2_MEM,Specify if memory-based context in SL2_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_SL2_MEM_0,LOSTMEM_SL2_MEM_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "L3_INSTR" base ad:0x45000100 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L3_INSTR_FW" base ad:0x4A226000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "L3_INSTR_FW_CFG_TARG" base ad:0x4A227000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "L3INIT_CM_CORE" base ad:0x4A009300 group.long 0x00++0x0B line.long 0x00 "CM_L3INIT_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," newline rbitfld.long 0x00 24. "CLKACTIVITY_SATA_REF_GFCLK,This field indicates the state of the SATA_REF_GFCLK clock in the domain" "CLKACTIVITY_SATA_REF_GFCLK_0,CLKACTIVITY_SATA_REF_GFCLK_1" newline rbitfld.long 0x00 23. "CLKACTIVITY_L3INIT_32K_GFCLK,This field indicates the state of the L3INIT_32K_FCLK clock in the domain" "CLKACTIVITY_L3INIT_32K_GFCLK_0,CLKACTIVITY_L3INIT_32K_GFCLK_1" newline rbitfld.long 0x00 22. "CLKACTIVITY_L3INIT_960M_GFCLK,This field indicates the state of the L3INIT_960M_GFCLK clock in the domain" "CLKACTIVITY_L3INIT_960M_GFCLK_0,CLKACTIVITY_L3INIT_960M_GFCLK_1" newline rbitfld.long 0x00 21. "CLKACTIVITY_L3INIT_480M_GFCLK,This field indicates the state of the L3INIT_480M_GFCLK clock in the domain" "CLKACTIVITY_L3INIT_480M_GFCLK_0,CLKACTIVITY_L3INIT_480M_GFCLK_1" newline rbitfld.long 0x00 20. "CLKACTIVITY_USB_OTG_SS_REF_CLK,This field indicates the state of the USB_OTG_SS_REF_CLK clock in the domain" "CLKACTIVITY_USB_OTG_SS_REF_CLK_0,CLKACTIVITY_USB_OTG_SS_REF_CLK_1" newline rbitfld.long 0x00 19. "CLKACTIVITY_MLB_SYS_L3_GFCLK,This field indicates the state of the MLB_SYS_L3_GFCLK clock in the domain" "CLKACTIVITY_MLB_SYS_L3_GFCLK_0,CLKACTIVITY_MLB_SYS_L3_GFCLK_1" newline rbitfld.long 0x00 18. "CLKACTIVITY_MLB_SPB_L4_GICLK,This field indicates the state of the MLB_SPB_L4_GICLK clock in the domain" "CLKACTIVITY_MLB_SPB_L4_GICLK_0,CLKACTIVITY_MLB_SPB_L4_GICLK_1" newline rbitfld.long 0x00 17. "CLKACTIVITY_MLB_SHB_L3_GICLK,This field indicates the state of the MLB_SHB_L3_GICLK clock in the domain" "CLKACTIVITY_MLB_SHB_L3_GICLK_0,CLKACTIVITY_MLB_SHB_L3_GICLK_1" newline rbitfld.long 0x00 16. "CLKACTIVITY_MMC2_GFCLK,This field indicates the state of the MMC2 clock in the domain" "CLKACTIVITY_MMC2_GFCLK_0,CLKACTIVITY_MMC2_GFCLK_1" newline rbitfld.long 0x00 15. "CLKACTIVITY_MMC1_GFCLK,This field indicates the state of the MMC1_GFCLK clock in the domain" "CLKACTIVITY_MMC1_GFCLK_0,CLKACTIVITY_MMC1_GFCLK_1" newline rbitfld.long 0x00 14. "CLKACTIVITY_HSI_GFCLK,This field indicates the state of the HSI_GFCLK clock in the domain" "CLKACTIVITY_HSI_GFCLK_0,CLKACTIVITY_HSI_GFCLK_1" newline rbitfld.long 0x00 13. "CLKACTIVITY_USB_DPLL_HS_CLK,This field indicates the state of the USB_DPLL_HS_CLK clock in the domain" "CLKACTIVITY_USB_DPLL_HS_CLK_0,CLKACTIVITY_USB_DPLL_HS_CLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_USB_DPLL_CLK,This field indicates the state of the USB_DPLL_CLK clock in the domain" "CLKACTIVITY_USB_DPLL_CLK_0,CLKACTIVITY_USB_DPLL_CLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_L3INIT_48M_GFCLK,This field indicates the state of the INIT_48M_GFCLK clock in the domain" "CLKACTIVITY_L3INIT_48M_GFCLK_0,CLKACTIVITY_L3INIT_48M_GFCLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK,This field indicates the state of the L3INIT_USB_LFPS_TX_GFCLK clock in the domain" "CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK_0,CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_L3INIT_L4_GICLK,This field indicates the state of the L3INIT_L4_GICLK clock in the domain" "CLKACTIVITY_L3INIT_L4_GICLK_0,CLKACTIVITY_L3INIT_L4_GICLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_L3INIT_L3_GICLK,This field indicates the state of the L3INIT_L3_GICLK clock in the domain" "CLKACTIVITY_L3INIT_L3_GICLK_0,CLKACTIVITY_L3INIT_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L3INIT clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_L3INIT_STATICDEP,This register controls the static domain depedencies from L3INIT domain towards 'target' domains" rbitfld.long 0x04 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline hexmask.long.word 0x04 16.--26. 1. "RESERVED," newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 6.--11. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" line.long 0x08 "CM_L3INIT_DYNAMICDEP,This register controls the dynamic domain depedencies from L3INIT domain towards 'target' domains" hexmask.long 0x08 6.--31. 1. "RESERVED," newline bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "L3MAIN1_DYNDEP_0,?" newline bitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x28++0x03 line.long 0x00 "CM_L3INIT_MMC1_CLKCTRL,This register manages the MMC1 clocks" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 25.--26. "CLKSEL_DIV,MMC1 clock divide ratio" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" newline bitfld.long 0x00 24. "CLKSEL_SOURCE,Selects the source of the functional clock" "CLKSEL_SOURCE_0,CLKSEL_SOURCE_1" newline rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,MMC optional clock control: 32K CLK" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x30++0x03 line.long 0x00 "CM_L3INIT_MMC2_CLKCTRL,This register manages the MMC2 clocks" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 25.--26. "CLKSEL_DIV,MMC2 clock divide ratio" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" newline bitfld.long 0x00 24. "CLKSEL_SOURCE,Selects the source of the functional clock" "CLKSEL_SOURCE_0,CLKSEL_SOURCE_1" newline rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,MMC optional clock control: 32K CLK" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_L3INIT_USB_OTG_SS2_CLKCTRL,This register manages the USB_OTG_SS2 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_REFCLK960M,USB_OTG_SS optional clock control: REFCLK960M (960MHz clock)" "OPTFCLKEN_REFCLK960M_0,OPTFCLKEN_REFCLK960M_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x48++0x03 line.long 0x00 "CM_L3INIT_USB_OTG_SS3_CLKCTRL,This register manages the USB_OTG_SS3 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x50++0x03 line.long 0x00 "CM_L3INIT_USB_OTG_SS4_CLKCTRL,This register manages the USB_OTG_SS4 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x58++0x03 line.long 0x00 "CM_L3INIT_MLB_SS_CLKCTRL,This register manages the MLBSS clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x78++0x03 line.long 0x00 "CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,This register manages the IEE1500_2_OCP clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x88++0x03 line.long 0x00 "CM_L3INIT_SATA_CLKCTRL,This register manages the SATA clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_REF_CLK,SATA optional clock control: REF_CLK (from SYS_CLK clock)" "OPTFCLKEN_REF_CLK_0,OPTFCLKEN_REF_CLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xA0++0x07 line.long 0x00 "CM_PCIE_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED," newline rbitfld.long 0x00 13. "CLKACTIVITY_PCIE_32K_GFCLK,This field indicates the state of the PCIE_32K_GFCLK clock in the domain" "CLKACTIVITY_PCIE_32K_GFCLK_0,CLKACTIVITY_PCIE_32K_GFCLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_PCIE_SYS_GFCLK,This field indicates the state of the PCIE_SYS_GFCLK clock in the domain" "CLKACTIVITY_PCIE_SYS_GFCLK_0,CLKACTIVITY_PCIE_SYS_GFCLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_PCIE_REF_GFCLK,This field indicates the state of the PCIE_REF_GFCLK clock in the domain" "CLKACTIVITY_PCIE_REF_GFCLK_0,CLKACTIVITY_PCIE_REF_GFCLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_PCIE_PHY_DIV_GCLK,This field indicates the state of the PCIE_PHY_DIV_GCLK clock in the domain" "CLKACTIVITY_PCIE_PHY_DIV_GCLK_0,CLKACTIVITY_PCIE_PHY_DIV_GCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_PCIE_PHY_GCLK,This field indicates the state of the PCIE_PHY_GCLK clock in the domain" "CLKACTIVITY_PCIE_PHY_GCLK_0,CLKACTIVITY_PCIE_PHY_GCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_PCIE_L3_GICLK,This field indicates the state of the PCIE_L3_GICLK clock in the domain" "CLKACTIVITY_PCIE_L3_GICLK_0,CLKACTIVITY_PCIE_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L3INIT clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_PCIE_STATICDEP,This register controls the static domain depedencies from PCIE domain towards 'target' domains" rbitfld.long 0x04 31. "RESERVED," "0,1" newline bitfld.long 0x04 30. "CRC_STATDEP,Static dependency towards CRC clock domain" "CRC_STATDEP_0,CRC_STATDEP_1" newline rbitfld.long 0x04 29. "RESERVED," "0,1" newline bitfld.long 0x04 28. "ISS_STATDEP,Static dependency towards ISS clock domain" "ISS_STATDEP_0,ISS_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain" "GMAC_STATDEP_0,GMAC_STATDEP_1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" newline bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain" "EVE1_STATDEP_0,EVE1_STATDEP_1" newline bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain" "CUSTEFUSE_STATDEP_0,?" newline rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain" "COREAON_STATDEP_0,?" newline rbitfld.long 0x04 15. "RESERVED," "0,1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 11. "SDMA_STATDEP,Static dependency towards SDMA clock domain" "SDMA_STATDEP_0,?" newline bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU clock domain" "GPU_STATDEP_0,GPU_STATDEP_1" newline bitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain" "CAM_STATDEP_0,CAM_STATDEP_1" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline rbitfld.long 0x04 5.--6. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP1 clock domain" "DSP1_STATDEP_0,DSP1_STATDEP_1" newline rbitfld.long 0x04 0. "RESERVED," "0,1" group.long 0xB0++0x03 line.long 0x00 "CM_PCIE_PCIESS1_CLKCTRL,This register manages the PCESS1 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10. "OPTFCLKEN_PCIEPHY_CLK_DIV,PCIE PHY optional clock control" "OPTFCLKEN_PCIEPHY_CLK_DIV_0,OPTFCLKEN_PCIEPHY_CLK_DIV_1" newline bitfld.long 0x00 9. "OPTFCLKEN_PCIEPHY_CLK,PCIE PHY optional clock control" "OPTFCLKEN_PCIEPHY_CLK_0,OPTFCLKEN_PCIEPHY_CLK_1" newline bitfld.long 0x00 8. "OPTFCLKEN_32KHZ,PCIE PHY optional clock control" "OPTFCLKEN_32KHZ_0,OPTFCLKEN_32KHZ_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xB8++0x03 line.long 0x00 "CM_PCIE_PCIESS2_CLKCTRL,This register manages the PCESS2 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10. "OPTFCLKEN_PCIEPHY_CLK_DIV,PCIE PHY optional clock control" "OPTFCLKEN_PCIEPHY_CLK_DIV_0,OPTFCLKEN_PCIEPHY_CLK_DIV_1" newline bitfld.long 0x00 9. "OPTFCLKEN_PCIEPHY_CLK,PCIE PHY optional clock control" "OPTFCLKEN_PCIEPHY_CLK_0,OPTFCLKEN_PCIEPHY_CLK_1" newline bitfld.long 0x00 8. "OPTFCLKEN_32KHZ,PCIE PHY optional clock control" "OPTFCLKEN_32KHZ_0,OPTFCLKEN_32KHZ_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xC0++0x0B line.long 0x00 "CM_GMAC_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED," newline rbitfld.long 0x00 12. "CLKACTIVITY_GMAC_MAIN_CLK,This field indicates the state of the GMAC_MAIN_CLK clock in the domain" "CLKACTIVITY_GMAC_MAIN_CLK_0,CLKACTIVITY_GMAC_MAIN_CLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_GMAC_RFT_CLK,This field indicates the state of the GMAC_RFT_CLK clock in the domain" "CLKACTIVITY_GMAC_RFT_CLK_0,CLKACTIVITY_GMAC_RFT_CLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_RMII_50MHZ_CLK,This field indicates the state of the RMII_50MHZ_CLK clock in the domain" "CLKACTIVITY_RMII_50MHZ_CLK_0,CLKACTIVITY_RMII_50MHZ_CLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_RGMII_5MHZ_CLK,This field indicates the state of the RGMII_5MHZ_CLK clock in the domain" "CLKACTIVITY_RGMII_5MHZ_CLK_0,CLKACTIVITY_RGMII_5MHZ_CLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_GMII_250MHZ_CLK,This field indicates the state of the GMII_250MHZ_CLK clock in the domain" "CLKACTIVITY_GMII_250MHZ_CLK_0,CLKACTIVITY_GMII_250MHZ_CLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,This bit field must not be programmed for SW_SLEEP or HW_AUTO when in EEE mode" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_GMAC_STATICDEP,This register controls the static domain depedencies from GMAC domain towards 'target' domains" rbitfld.long 0x04 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline hexmask.long.tbyte 0x04 6.--25. 1. "RESERVED," newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline rbitfld.long 0x04 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "CM_GMAC_DYNAMICDEP,This register controls the dynamic domain depedencies from GMAC domain towards 'target' domains" hexmask.long 0x08 6.--31. 1. "RESERVED," newline bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "L3MAIN1_DYNDEP_0,?" newline bitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xD0++0x03 line.long 0x00 "CM_GMAC_GMAC_CLKCTRL,This register manages the GMAC clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 25.--27. "CLKSEL_RFT,Selects the source of the GMAC_RFT_CLK" "CLKSEL_RFT_0,CLKSEL_RFT_1,CLKSEL_RFT_2,CLKSEL_RFT_3,CLKSEL_RFT_4,CLKSEL_RFT_5,CLKSEL_RFT_6,CLKSEL_RFT_7" newline bitfld.long 0x00 24. "CLKSEL_REF,Selects the source of the RMII_50MHZ_CLK functional clock" "CLKSEL_REF_0,CLKSEL_REF_1" newline rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xE0++0x03 line.long 0x00 "CM_L3INIT_OCP2SCP1_CLKCTRL,This register manages the OCP2SCP1 clocks and the optional clock of USB PHY" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xE8++0x03 line.long 0x00 "CM_L3INIT_OCP2SCP3_CLKCTRL,This register manages the OCP2SCP3 clocks and the optional clock of USB PHY" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xF0++0x03 line.long 0x00 "CM_L3INIT_USB_OTG_SS1_CLKCTRL,This register manages the USB_OTG_SS1 clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_REFCLK960M,USB_OTG_SS optional clock control: REFCLK960M (960MHz clock)" "OPTFCLKEN_REFCLK960M_0,OPTFCLKEN_REFCLK960M_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "L3INIT_PRM" base ad:0x4AE07300 group.long 0x00++0x07 line.long 0x00 "PM_L3INIT_PWRSTCTRL,This register controls the L3INIT power state to reach upon a domain sleep transition" hexmask.long.word 0x00 20.--31. 1. "RESERVED," rbitfld.long 0x00 18.--19. "GMAC_BANK_ONSTATE,GMAC BANK state when domain is ON" "?,?,?,GMAC_BANK_ONSTATE_3" newline rbitfld.long 0x00 16.--17. "L3INIT_BANK2_ONSTATE,L3INIT BANK2 state when domain is ON" "?,?,?,L3INIT_BANK2_ONSTATE_3" rbitfld.long 0x00 14.--15. "L3INIT_BANK1_ONSTATE,L3INIT BANK1 state when domain is ON" "?,?,?,L3INIT_BANK1_ONSTATE_3" newline rbitfld.long 0x00 11.--13. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x00 10. "GMAC_BANK_RETSTATE,GMAC BANK state when domain is RETENTION" "?,GMAC_BANK_RETSTATE_1" newline rbitfld.long 0x00 9. "L3INIT_BANK2_RETSTATE,L3INIT BANK2 state when domain is RETENTION" "?,L3INIT_BANK2_RETSTATE_1" rbitfld.long 0x00 8. "L3INIT_BANK1_RETSTATE,L3INIT BANK1 state when domain is RETENTION" "L3INIT_BANK1_RETSTATE_0,?" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION" "LOGICRETSTATE_0,LOGICRETSTATE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_L3INIT_PWRSTST,This register provides a status on the current L3INIT power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 10.--19. 1. "RESERVED," rbitfld.long 0x04 8.--9. "L3INIT_GMAC_STATEST,L3INIT GMAC state status" "L3INIT_GMAC_STATEST_0,L3INIT_GMAC_STATEST_1,L3INIT_GMAC_STATEST_2,L3INIT_GMAC_STATEST_3" newline rbitfld.long 0x04 6.--7. "L3INIT_BANK2_STATEST,L3INIT BANK2 state status" "L3INIT_BANK2_STATEST_0,L3INIT_BANK2_STATEST_1,L3INIT_BANK2_STATEST_2,L3INIT_BANK2_STATEST_3" rbitfld.long 0x04 4.--5. "L3INIT_BANK1_STATEST,L3INIT BANK1 state status" "L3INIT_BANK1_STATEST_0,L3INIT_BANK1_STATEST_1,L3INIT_BANK1_STATEST_2,L3INIT_BANK1_STATEST_3" newline rbitfld.long 0x04 3. "RESERVED," "0,1" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_PCIESS_RSTCTRL,This register controls the release of the PCIESS local reset" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "RST_LOCAL_PCIE2,PCIESS2 local reset control" "RST_LOCAL_PCIE2_0,RST_LOCAL_PCIE2_1" newline bitfld.long 0x00 0. "RST_LOCAL_PCIE1,PCIESS1 local reset control" "RST_LOCAL_PCIE1_0,RST_LOCAL_PCIE1_1" line.long 0x04 "RM_PCIESS_RSTST,This register logs the different reset sources of the PCIESS domain" hexmask.long 0x04 2.--31. 1. "RESERVED," bitfld.long 0x04 1. "RST_LOCAL_PCIE2,PCIESS2 local SW reset" "RST_LOCAL_PCIE2_0,RST_LOCAL_PCIE2_1" newline bitfld.long 0x04 0. "RST_LOCAL_PCIE1,PCIESS1 local SW reset" "RST_LOCAL_PCIE1_0,RST_LOCAL_PCIE1_1" group.long 0x28++0x0F line.long 0x00 "PM_L3INIT_MMC1_WKDEP,This register controls wakeup dependency based on MMC1 service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_MMC1_EVE4,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_EVE4_0,WKUPDEP_MMC1_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_MMC1_EVE3,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_EVE3_0,WKUPDEP_MMC1_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_MMC1_EVE2,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_EVE2_0,WKUPDEP_MMC1_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_MMC1_EVE1,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_EVE1_0,WKUPDEP_MMC1_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_MMC1_DSP2,Wakeup dependency from MMC1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_DSP2_0,WKUPDEP_MMC1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_MMC1_IPU1,Wakeup dependency from MMC1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_IPU1_0,WKUPDEP_MMC1_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_MMC1_SDMA,Wakeup dependency from MMC1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_SDMA_0,WKUPDEP_MMC1_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_MMC1_DSP1,Wakeup dependency from MMC1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_DSP1_0,WKUPDEP_MMC1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_MMC1_IPU2,Wakeup dependency from MMC1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_IPU2_0,WKUPDEP_MMC1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_MMC1_MPU,Wakeup dependency from MMC1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC1_MPU_0,WKUPDEP_MMC1_MPU_1" line.long 0x04 "RM_L3INIT_MMC1_CONTEXT,This register contains dedicated MMC1 context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline rbitfld.long 0x04 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x04 0. "RESERVED," "0,1" line.long 0x08 "PM_L3INIT_MMC2_WKDEP,This register controls wakeup dependency based on MMC2 service requests" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "WKUPDEP_MMC2_EVE4,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_EVE4_0,WKUPDEP_MMC2_EVE4_1" newline bitfld.long 0x08 8. "WKUPDEP_MMC2_EVE3,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_EVE3_0,WKUPDEP_MMC2_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_MMC2_EVE2,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_EVE2_0,WKUPDEP_MMC2_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_MMC2_EVE1,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_EVE1_0,WKUPDEP_MMC2_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_MMC2_DSP2,Wakeup dependency from MMC2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_DSP2_0,WKUPDEP_MMC2_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_MMC2_IPU1,Wakeup dependency from MMC2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_IPU1_0,WKUPDEP_MMC2_IPU1_1" bitfld.long 0x08 3. "WKUPDEP_MMC2_SDMA,Wakeup dependency from MMC2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_SDMA_0,WKUPDEP_MMC2_SDMA_1" newline bitfld.long 0x08 2. "WKUPDEP_MMC2_DSP1,Wakeup dependency from MMC2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_DSP1_0,WKUPDEP_MMC2_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_MMC2_IPU2,Wakeup dependency from MMC2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_IPU2_0,WKUPDEP_MMC2_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_MMC2_MPU,Wakeup dependency from MMC2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC2_MPU_0,WKUPDEP_MMC2_MPU_1" line.long 0x0C "RM_L3INIT_MMC2_CONTEXT,This register contains dedicated MMC2 context statuses" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED," bitfld.long 0x0C 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline rbitfld.long 0x0C 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x0C 0. "RESERVED," "0,1" group.long 0x40++0x17 line.long 0x00 "PM_L3INIT_USB_OTG_SS2_WKDEP,This register controls wakeup dependency based on USB_OTG_SS2 service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_USB_OTG_SS2_EVE4,Wakeup dependency from USB2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_EVE4_0,WKUPDEP_USB_OTG_SS2_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_USB_OTG_SS2_EVE3,Wakeup dependency from USB2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_EVE3_0,WKUPDEP_USB_OTG_SS2_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_USB_OTG_SS2_EVE2,Wakeup dependency from USB2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_EVE2_0,WKUPDEP_USB_OTG_SS2_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_USB_OTG_SS2_EVE1,Wakeup dependency from USB2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_EVE1_0,WKUPDEP_USB_OTG_SS2_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_USB_OTG_SS2_DSP2,Wakeup dependency from USB2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_DSP2_0,WKUPDEP_USB_OTG_SS2_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_USB_OTG_SS2_IPU1,Wakeup dependency from USB2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_IPU1_0,WKUPDEP_USB_OTG_SS2_IPU1_1" rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_USB_OTG_SS2_DSP1,Wakeup dependency from USB2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_DSP1_0,WKUPDEP_USB_OTG_SS2_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_USB_OTG_SS2_IPU2,Wakeup dependency from USB2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_IPU2_0,WKUPDEP_USB_OTG_SS2_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_USB_OTG_SS2_MPU,Wakeup dependency from USB2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS2_MPU_0,WKUPDEP_USB_OTG_SS2_MPU_1" line.long 0x04 "RM_L3INIT_USB_OTG_SS2_CONTEXT,This register contains dedicated USB_OTG_SS2 context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline rbitfld.long 0x04 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x04 0. "RESERVED," "0,1" line.long 0x08 "PM_L3INIT_USB_OTG_SS3_WKDEP,This register controls wakeup dependency based on USB_OTG_SS3 service requests" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "WKUPDEP_USB_OTG_SS3_EVE4,Wakeup dependency from USB3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_EVE4_0,WKUPDEP_USB_OTG_SS3_EVE4_1" newline bitfld.long 0x08 8. "WKUPDEP_USB_OTG_SS3_EVE3,Wakeup dependency from USB3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_EVE3_0,WKUPDEP_USB_OTG_SS3_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_USB_OTG_SS3_EVE2,Wakeup dependency from USB3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_EVE2_0,WKUPDEP_USB_OTG_SS3_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_USB_OTG_SS3_EVE1,Wakeup dependency from USB3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_EVE1_0,WKUPDEP_USB_OTG_SS3_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_USB_OTG_SS3_DSP2,Wakeup dependency from USB3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_DSP2_0,WKUPDEP_USB_OTG_SS3_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_USB_OTG_SS3_IPU1,Wakeup dependency from USB3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_IPU1_0,WKUPDEP_USB_OTG_SS3_IPU1_1" rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 2. "WKUPDEP_USB_OTG_SS3_DSP1,Wakeup dependency from USB3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_DSP1_0,WKUPDEP_USB_OTG_SS3_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_USB_OTG_SS3_IPU2,Wakeup dependency from USB3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_IPU2_0,WKUPDEP_USB_OTG_SS3_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_USB_OTG_SS3_MPU,Wakeup dependency from USB3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS3_MPU_0,WKUPDEP_USB_OTG_SS3_MPU_1" line.long 0x0C "RM_L3INIT_USB_OTG_SS3_CONTEXT,This register contains dedicated USB_OTG_SS3 context statuses" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED," bitfld.long 0x0C 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline rbitfld.long 0x0C 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x0C 0. "RESERVED," "0,1" line.long 0x10 "PM_L3INIT_USB_OTG_SS4_WKDEP,This register controls wakeup dependency based on USB_OTG_SS4 service requests" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED," bitfld.long 0x10 9. "WKUPDEP_USB_OTG_SS4_EVE4,Wakeup dependency from USB4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_EVE4_0,WKUPDEP_USB_OTG_SS4_EVE4_1" newline bitfld.long 0x10 8. "WKUPDEP_USB_OTG_SS4_EVE3,Wakeup dependency from USB4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_EVE3_0,WKUPDEP_USB_OTG_SS4_EVE3_1" bitfld.long 0x10 7. "WKUPDEP_USB_OTG_SS4_EVE2,Wakeup dependency from USB4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_EVE2_0,WKUPDEP_USB_OTG_SS4_EVE2_1" newline bitfld.long 0x10 6. "WKUPDEP_USB_OTG_SS4_EVE1,Wakeup dependency from USB4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_EVE1_0,WKUPDEP_USB_OTG_SS4_EVE1_1" bitfld.long 0x10 5. "WKUPDEP_USB_OTG_SS4_DSP2,Wakeup dependency from USB4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_DSP2_0,WKUPDEP_USB_OTG_SS4_DSP2_1" newline bitfld.long 0x10 4. "WKUPDEP_USB_OTG_SS4_IPU1,Wakeup dependency from USB4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_IPU1_0,WKUPDEP_USB_OTG_SS4_IPU1_1" rbitfld.long 0x10 3. "RESERVED," "0,1" newline bitfld.long 0x10 2. "WKUPDEP_USB_OTG_SS4_DSP1,Wakeup dependency from USB4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_DSP1_0,WKUPDEP_USB_OTG_SS4_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_USB_OTG_SS4_IPU2,Wakeup dependency from USB4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_IPU2_0,WKUPDEP_USB_OTG_SS4_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_USB_OTG_SS4_MPU,Wakeup dependency from USB4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS4_MPU_0,WKUPDEP_USB_OTG_SS4_MPU_1" line.long 0x14 "RM_L3INIT_USB_OTG_SS4_CONTEXT,This register contains dedicated USB_OTG_SS4 context statuses" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED," bitfld.long 0x14 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline rbitfld.long 0x14 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x14 0. "RESERVED," "0,1" group.long 0x5C++0x03 line.long 0x00 "RM_L3INIT_MLB_SS_CONTEXT,This register contains dedicated MLBSS context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_MLB_BANK,Specify if memory-based context in MLB_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_MLB_BANK_0,LOSTMEM_MLB_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x7C++0x03 line.long 0x00 "RM_L3INIT_IEEE1500_2_OCP_CONTEXT,This register contains dedicated IEEE1500_2_OCP context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x88++0x07 line.long 0x00 "PM_L3INIT_SATA_WKDEP,This register controls wakeup dependency based on SATA service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_SATA_EVE4,Wakeup dependency from SATA module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SATA_EVE4_0,WKUPDEP_SATA_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_SATA_EVE3,Wakeup dependency from SATA module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SATA_EVE3_0,WKUPDEP_SATA_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_SATA_EVE2,Wakeup dependency from SATA module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SATA_EVE2_0,WKUPDEP_SATA_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SATA_EVE1,Wakeup dependency from SATA module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SATA_EVE1_0,WKUPDEP_SATA_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_SATA_DSP2,Wakeup dependency from SATA module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SATA_DSP2_0,WKUPDEP_SATA_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SATA_IPU1,Wakeup dependency from SATA module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SATA_IPU1_0,WKUPDEP_SATA_IPU1_1" rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_SATA_DSP1,Wakeup dependency from SATA module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SATA_DSP1_0,WKUPDEP_SATA_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_SATA_IPU2,Wakeup dependency from SATA module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_SATA_IPU2_0,WKUPDEP_SATA_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SATA_MPU,Wakeup dependency from SATA module (SWakeup signal) towards MPU + L3MAIN1 + L4CFG domains" "WKUPDEP_SATA_MPU_0,WKUPDEP_SATA_MPU_1" line.long 0x04 "RM_L3INIT_SATA_CONTEXT,This register contains dedicated SATA context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xB0++0x0F line.long 0x00 "PM_PCIE_PCIESS1_WKDEP,This register controls wakeup dependency based on PCIESS1 service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_PCIESS1_EVE4,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_EVE4_0,WKUPDEP_PCIESS1_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_PCIESS1_EVE3,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_EVE3_0,WKUPDEP_PCIESS1_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_PCIESS1_EVE2,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_EVE2_0,WKUPDEP_PCIESS1_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_PCIESS1_EVE1,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_EVE1_0,WKUPDEP_PCIESS1_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_PCIESS1_DSP2,Wakeup dependency from PCIESS1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_DSP2_0,WKUPDEP_PCIESS1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_PCIESS1_IPU1,Wakeup dependency from PCIESS1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_IPU1_0,WKUPDEP_PCIESS1_IPU1_1" rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_PCIESS1_DSP1,Wakeup dependency from PCIESS1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_DSP1_0,WKUPDEP_PCIESS1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_PCIESS1_IPU2,Wakeup dependency from PCIESS1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_IPU2_0,WKUPDEP_PCIESS1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_PCIESS1_MPU,Wakeup dependency from PCIESS1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_MPU_0,WKUPDEP_PCIESS1_MPU_1" line.long 0x04 "RM_PCIE_PCIESS1_CONTEXT,This register contains dedicated PCIESS1 context statuses" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," bitfld.long 0x04 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in PCIESS1_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_PCIE_PCIESS2_WKDEP,This register controls wakeup dependency based on PCIESS2 service requests" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "WKUPDEP_PCIESS2_EVE4,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_EVE4_0,WKUPDEP_PCIESS2_EVE4_1" newline bitfld.long 0x08 8. "WKUPDEP_PCIESS2_EVE3,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_EVE3_0,WKUPDEP_PCIESS2_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_PCIESS2_EVE2,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_EVE2_0,WKUPDEP_PCIESS2_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_PCIESS2_EVE1,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_EVE1_0,WKUPDEP_PCIESS2_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_PCIESS2_DSP2,Wakeup dependency from PCIESS2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_DSP2_0,WKUPDEP_PCIESS2_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_PCIESS2_IPU1,Wakeup dependency from PCIESS2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_IPU1_0,WKUPDEP_PCIESS2_IPU1_1" rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 2. "WKUPDEP_PCIESS2_DSP1,Wakeup dependency from PCIESS2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_DSP1_0,WKUPDEP_PCIESS2_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_PCIESS2_IPU2,Wakeup dependency from PCIESS2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_IPU2_0,WKUPDEP_PCIESS2_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_PCIESS2_MPU,Wakeup dependency from PCIESS2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS2_MPU_0,WKUPDEP_PCIESS2_MPU_1" line.long 0x0C "RM_PCIE_PCIESS2_CONTEXT,This register contains dedicated PCIESS2 context statuses" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED," bitfld.long 0x0C 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in PCIESS1_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline hexmask.long.byte 0x0C 1.--7. 1. "RESERVED," bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xD4++0x03 line.long 0x00 "RM_GMAC_GMAC_CONTEXT,This register contains dedicated GMAC context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_GMAC_BANK,Specify if memory-based context in GMAC_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_GMAC_BANK_0,LOSTMEM_GMAC_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xE4++0x03 line.long 0x00 "RM_L3INIT_OCP2SCP1_CONTEXT,This register contains dedicated OCP2SCP1 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xEC++0x0B line.long 0x00 "RM_L3INIT_OCP2SCP3_CONTEXT,This register contains dedicated OCP2SCP3 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_L3INIT_USB_OTG_SS1_WKDEP,This register controls wakeup dependency based on USB_OTG_SS1 service requests" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "WKUPDEP_USB_OTG_SS1_EVE4,Wakeup dependency from USB1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_EVE4_0,WKUPDEP_USB_OTG_SS1_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_USB_OTG_SS1_EVE3,Wakeup dependency from USB1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_EVE3_0,WKUPDEP_USB_OTG_SS1_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_USB_OTG_SS1_EVE2,Wakeup dependency from USB1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_EVE2_0,WKUPDEP_USB_OTG_SS1_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_USB_OTG_SS1_EVE1,Wakeup dependency from USB1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_EVE1_0,WKUPDEP_USB_OTG_SS1_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_USB_OTG_SS1_DSP2,Wakeup dependency from USB1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_DSP2_0,WKUPDEP_USB_OTG_SS1_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_USB_OTG_SS1_IPU1,Wakeup dependency from USB1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_IPU1_0,WKUPDEP_USB_OTG_SS1_IPU1_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "WKUPDEP_USB_OTG_SS1_DSP1,Wakeup dependency from USB1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_DSP1_0,WKUPDEP_USB_OTG_SS1_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_USB_OTG_SS1_IPU2,Wakeup dependency from USB1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_IPU2_0,WKUPDEP_USB_OTG_SS1_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_USB_OTG_SS1_MPU,Wakeup dependency from USB1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_USB_OTG_SS1_MPU_0,WKUPDEP_USB_OTG_SS1_MPU_1" line.long 0x08 "RM_L3INIT_USB_OTG_SS1_CONTEXT,This register contains dedicated USB_OTG_SS1 context statuses" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," bitfld.long 0x08 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" newline rbitfld.long 0x08 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x08 0. "RESERVED," "0,1" width 0x0B tree.end tree "L4_CFG_AP" base ad:0x4A000000 rgroup.long 0x00++0x07 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x100++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_0,Defines the base address of each segment" rgroup.long 0x108++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_1,Defines the base address of each segment" rgroup.long 0x110++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_2,Defines the base address of each segment" rgroup.long 0x104++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_0,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x10C++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_1,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x114++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_2,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x208++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x210++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x218++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x220++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x228++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x230++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x238++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x280++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x288++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x290++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x298++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Reserved" rgroup.long 0x28C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Reserved" rgroup.long 0x294++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Reserved" rgroup.long 0x29C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Reserved" rgroup.long 0x2A4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Reserved" rgroup.long 0x2AC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Reserved" rgroup.long 0x2B4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Reserved" rgroup.long 0x2BC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Reserved" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x308++0x03 line.long 0x00 "L4_AP_REGION_l_L_1,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x310++0x03 line.long 0x00 "L4_AP_REGION_l_L_2,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x318++0x03 line.long 0x00 "L4_AP_REGION_l_L_3,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x320++0x03 line.long 0x00 "L4_AP_REGION_l_L_4,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x328++0x03 line.long 0x00 "L4_AP_REGION_l_L_5,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x330++0x03 line.long 0x00 "L4_AP_REGION_l_L_6,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x338++0x03 line.long 0x00 "L4_AP_REGION_l_L_7,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x340++0x03 line.long 0x00 "L4_AP_REGION_l_L_8,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x348++0x03 line.long 0x00 "L4_AP_REGION_l_L_9,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x358++0x03 line.long 0x00 "L4_AP_REGION_l_L_11,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x360++0x03 line.long 0x00 "L4_AP_REGION_l_L_12,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x368++0x03 line.long 0x00 "L4_AP_REGION_l_L_13,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x370++0x03 line.long 0x00 "L4_AP_REGION_l_L_14,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x378++0x03 line.long 0x00 "L4_AP_REGION_l_L_15,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x380++0x03 line.long 0x00 "L4_AP_REGION_l_L_16,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x388++0x03 line.long 0x00 "L4_AP_REGION_l_L_17,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x390++0x03 line.long 0x00 "L4_AP_REGION_l_L_18,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x398++0x03 line.long 0x00 "L4_AP_REGION_l_L_19,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_20,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_21,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_22,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_23,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_25,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_26,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_27,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_28,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_29,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_30,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_31,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x400++0x03 line.long 0x00 "L4_AP_REGION_l_L_32,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x408++0x03 line.long 0x00 "L4_AP_REGION_l_L_33,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x410++0x03 line.long 0x00 "L4_AP_REGION_l_L_34,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x418++0x03 line.long 0x00 "L4_AP_REGION_l_L_35,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x420++0x03 line.long 0x00 "L4_AP_REGION_l_L_36,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x428++0x03 line.long 0x00 "L4_AP_REGION_l_L_37,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x430++0x03 line.long 0x00 "L4_AP_REGION_l_L_38,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x438++0x03 line.long 0x00 "L4_AP_REGION_l_L_39,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x448++0x03 line.long 0x00 "L4_AP_REGION_l_L_41,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x450++0x03 line.long 0x00 "L4_AP_REGION_l_L_42,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x458++0x03 line.long 0x00 "L4_AP_REGION_l_L_43,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x460++0x03 line.long 0x00 "L4_AP_REGION_l_L_44,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x468++0x03 line.long 0x00 "L4_AP_REGION_l_L_45,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x470++0x03 line.long 0x00 "L4_AP_REGION_l_L_46,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x478++0x03 line.long 0x00 "L4_AP_REGION_l_L_47,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x480++0x03 line.long 0x00 "L4_AP_REGION_l_L_48,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x488++0x03 line.long 0x00 "L4_AP_REGION_l_L_49,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x490++0x03 line.long 0x00 "L4_AP_REGION_l_L_50,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x498++0x03 line.long 0x00 "L4_AP_REGION_l_L_51,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_52,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_53,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_54,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_55,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_56,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_57,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_58,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_59,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_60,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_61,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_62,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_63,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x500++0x03 line.long 0x00 "L4_AP_REGION_l_L_64,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x508++0x03 line.long 0x00 "L4_AP_REGION_l_L_65,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x510++0x03 line.long 0x00 "L4_AP_REGION_l_L_66,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x518++0x03 line.long 0x00 "L4_AP_REGION_l_L_67,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x520++0x03 line.long 0x00 "L4_AP_REGION_l_L_68,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x528++0x03 line.long 0x00 "L4_AP_REGION_l_L_69,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x530++0x03 line.long 0x00 "L4_AP_REGION_l_L_70,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x538++0x03 line.long 0x00 "L4_AP_REGION_l_L_71,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x540++0x03 line.long 0x00 "L4_AP_REGION_l_L_72,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x548++0x03 line.long 0x00 "L4_AP_REGION_l_L_73,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x550++0x03 line.long 0x00 "L4_AP_REGION_l_L_74,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x558++0x03 line.long 0x00 "L4_AP_REGION_l_L_75,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x560++0x03 line.long 0x00 "L4_AP_REGION_l_L_76,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x568++0x03 line.long 0x00 "L4_AP_REGION_l_L_77,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x570++0x03 line.long 0x00 "L4_AP_REGION_l_L_78,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x578++0x03 line.long 0x00 "L4_AP_REGION_l_L_79,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x580++0x03 line.long 0x00 "L4_AP_REGION_l_L_80,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x588++0x03 line.long 0x00 "L4_AP_REGION_l_L_81,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x590++0x03 line.long 0x00 "L4_AP_REGION_l_L_82,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x598++0x03 line.long 0x00 "L4_AP_REGION_l_L_83,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_84,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_85,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_86,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_87,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_88,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_89,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_90,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_91,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_92,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_93,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_94,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_95,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x600++0x03 line.long 0x00 "L4_AP_REGION_l_L_96,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x608++0x03 line.long 0x00 "L4_AP_REGION_l_L_97,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x610++0x03 line.long 0x00 "L4_AP_REGION_l_L_98,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x618++0x03 line.long 0x00 "L4_AP_REGION_l_L_99,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x620++0x03 line.long 0x00 "L4_AP_REGION_l_L_100,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x628++0x03 line.long 0x00 "L4_AP_REGION_l_L_101,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x630++0x03 line.long 0x00 "L4_AP_REGION_l_L_102,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x638++0x03 line.long 0x00 "L4_AP_REGION_l_L_103,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x640++0x03 line.long 0x00 "L4_AP_REGION_l_L_104,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x648++0x03 line.long 0x00 "L4_AP_REGION_l_L_105,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x650++0x03 line.long 0x00 "L4_AP_REGION_l_L_106,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x658++0x03 line.long 0x00 "L4_AP_REGION_l_L_107,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x660++0x03 line.long 0x00 "L4_AP_REGION_l_L_108,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x668++0x03 line.long 0x00 "L4_AP_REGION_l_L_109,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x670++0x03 line.long 0x00 "L4_AP_REGION_l_L_110,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x30C++0x03 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x314++0x03 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x31C++0x03 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x324++0x03 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x32C++0x03 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x334++0x03 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x33C++0x03 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x344++0x03 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x34C++0x03 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x35C++0x03 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x364++0x03 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x36C++0x03 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x374++0x03 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x37C++0x03 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x384++0x03 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x38C++0x03 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x394++0x03 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x39C++0x03 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x404++0x03 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x40C++0x03 line.long 0x00 "L4_AP_REGION_l_H_33,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x414++0x03 line.long 0x00 "L4_AP_REGION_l_H_34,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x41C++0x03 line.long 0x00 "L4_AP_REGION_l_H_35,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x424++0x03 line.long 0x00 "L4_AP_REGION_l_H_36,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x42C++0x03 line.long 0x00 "L4_AP_REGION_l_H_37,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x434++0x03 line.long 0x00 "L4_AP_REGION_l_H_38,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x43C++0x03 line.long 0x00 "L4_AP_REGION_l_H_39,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x44C++0x03 line.long 0x00 "L4_AP_REGION_l_H_41,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x454++0x03 line.long 0x00 "L4_AP_REGION_l_H_42,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x45C++0x03 line.long 0x00 "L4_AP_REGION_l_H_43,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x464++0x03 line.long 0x00 "L4_AP_REGION_l_H_44,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x46C++0x03 line.long 0x00 "L4_AP_REGION_l_H_45,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x474++0x03 line.long 0x00 "L4_AP_REGION_l_H_46,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x47C++0x03 line.long 0x00 "L4_AP_REGION_l_H_47,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x484++0x03 line.long 0x00 "L4_AP_REGION_l_H_48,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x48C++0x03 line.long 0x00 "L4_AP_REGION_l_H_49,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x494++0x03 line.long 0x00 "L4_AP_REGION_l_H_50,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x49C++0x03 line.long 0x00 "L4_AP_REGION_l_H_51,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_52,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_53,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_54,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_55,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_56,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_57,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_58,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_59,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_60,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_61,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_62,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_63,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x504++0x03 line.long 0x00 "L4_AP_REGION_l_H_64,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x50C++0x03 line.long 0x00 "L4_AP_REGION_l_H_65,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x514++0x03 line.long 0x00 "L4_AP_REGION_l_H_66,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x51C++0x03 line.long 0x00 "L4_AP_REGION_l_H_67,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x524++0x03 line.long 0x00 "L4_AP_REGION_l_H_68,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x52C++0x03 line.long 0x00 "L4_AP_REGION_l_H_69,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x534++0x03 line.long 0x00 "L4_AP_REGION_l_H_70,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x53C++0x03 line.long 0x00 "L4_AP_REGION_l_H_71,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x544++0x03 line.long 0x00 "L4_AP_REGION_l_H_72,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x54C++0x03 line.long 0x00 "L4_AP_REGION_l_H_73,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x554++0x03 line.long 0x00 "L4_AP_REGION_l_H_74,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x55C++0x03 line.long 0x00 "L4_AP_REGION_l_H_75,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x564++0x03 line.long 0x00 "L4_AP_REGION_l_H_76,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x56C++0x03 line.long 0x00 "L4_AP_REGION_l_H_77,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x574++0x03 line.long 0x00 "L4_AP_REGION_l_H_78,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x57C++0x03 line.long 0x00 "L4_AP_REGION_l_H_79,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x584++0x03 line.long 0x00 "L4_AP_REGION_l_H_80,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x58C++0x03 line.long 0x00 "L4_AP_REGION_l_H_81,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x594++0x03 line.long 0x00 "L4_AP_REGION_l_H_82,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x59C++0x03 line.long 0x00 "L4_AP_REGION_l_H_83,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_84,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_85,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_86,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_87,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_88,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_89,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_90,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_91,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_92,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_93,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_94,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_95,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x604++0x03 line.long 0x00 "L4_AP_REGION_l_H_96,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x60C++0x03 line.long 0x00 "L4_AP_REGION_l_H_97,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x614++0x03 line.long 0x00 "L4_AP_REGION_l_H_98,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x61C++0x03 line.long 0x00 "L4_AP_REGION_l_H_99,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x624++0x03 line.long 0x00 "L4_AP_REGION_l_H_100,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x62C++0x03 line.long 0x00 "L4_AP_REGION_l_H_101,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x634++0x03 line.long 0x00 "L4_AP_REGION_l_H_102,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x63C++0x03 line.long 0x00 "L4_AP_REGION_l_H_103,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x644++0x03 line.long 0x00 "L4_AP_REGION_l_H_104,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x64C++0x03 line.long 0x00 "L4_AP_REGION_l_H_105,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x654++0x03 line.long 0x00 "L4_AP_REGION_l_H_106,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x65C++0x03 line.long 0x00 "L4_AP_REGION_l_H_107,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x664++0x03 line.long 0x00 "L4_AP_REGION_l_H_108,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x66C++0x03 line.long 0x00 "L4_AP_REGION_l_H_109,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x674++0x03 line.long 0x00 "L4_AP_REGION_l_H_110,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" width 0x0B tree.end tree "L4_CFG_IA_IP0" base ad:0x4A001000 rgroup.long 0x00++0x07 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x17 line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" rbitfld.long 0x08 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" newline hexmask.long.tbyte 0x08 0.--23. 1. "RESERVED," line.long 0x0C "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" line.long 0x10 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x10 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x10 30. "PROT_ERROR_PRIMARY," "0,1" rbitfld.long 0x10 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x10 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x10 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x10 24. "MERROR,Value of the OCP MError signal" "0,1" newline hexmask.long.tbyte 0x10 0.--23. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0F line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" rbitfld.long 0x00 26.--29. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "No errors,Unsupported command,Address hole,Protection violation" hexmask.long.word 0x00 14.--23. 1. "RESERVED,Read returns 0" rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 3.--7. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--2. "CMD,Command that has caused an error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that has caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" line.long 0x0C "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" width 0x0B tree.end tree "L4_CFG_LA" base ad:0x4A000800 rgroup.long 0x00++0x07 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" newline hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x10++0x17 line.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" line.long 0x04 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x08 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x08 28.--31. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "PROT_GROUPS,Number of protection groups in the current L4" "No protection group,1 protection group,2 protection groups,?,?,?,?,?,8 protection groups 0x9 to,?,?,?,?,?,?,Reserved" newline abitfld.long 0x08 16.--23. "NUMBER_REGIONS,Number of regions in the current L4" "0x00=Reserved,0x01=1 region,0x02=2 regions,0xFF=Reserved 'Max regions' is listed in on row.." newline hexmask.long.word 0x08 4.--15. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 0.--3. "SEGMENTS,Number of segments in the current L4" "Reserved,1 segment,2 segments,?,?,?,?,?,8 segments,?..." line.long 0x0C "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" hexmask.long.word 0x0C 19.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x0C 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 15. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 11. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "?,16-bit data width is specified,32-bit data width is specified,?..." newline bitfld.long 0x0C 6.--7. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" hexmask.long.tbyte 0x10 11.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "Time-out disabled,L4 interconnect clock cycles divided by 64,L4 interconnect clock cycles divided by 256,L4 interconnect clock cycles divided by 1024,L4 interconnect clock cycles divided by 4096,?..." newline hexmask.long.byte 0x10 0.--7. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x14 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" newline rbitfld.long 0x14 21.--23. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 20. "THREAD0_PRI,Sets thread priority" "0,1" newline hexmask.long.word 0x14 9.--19. 1. "RESERVED,Read returns 0" newline rbitfld.long 0x14 8. "EXT_CLOCK,Global external clock control" "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "RESERVED,Read returns 0" width 0x0B tree.end tree "L4_CFG_TARG" base ad:0x44000500 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER1_AP" base ad:0x48000000 rgroup.long 0x00++0x07 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x100++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_0,Defines the base address of each segment" rgroup.long 0x108++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_1,Defines the base address of each segment" rgroup.long 0x104++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_0,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x10C++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_1,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x208++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x210++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x218++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x220++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x228++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x230++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x238++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x280++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x288++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x290++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x298++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Reserved" rgroup.long 0x28C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Reserved" rgroup.long 0x294++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Reserved" rgroup.long 0x29C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Reserved" rgroup.long 0x2A4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Reserved" rgroup.long 0x2AC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Reserved" rgroup.long 0x2B4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Reserved" rgroup.long 0x2BC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Reserved" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x308++0x03 line.long 0x00 "L4_AP_REGION_l_L_1,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x310++0x03 line.long 0x00 "L4_AP_REGION_l_L_2,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x318++0x03 line.long 0x00 "L4_AP_REGION_l_L_3,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x320++0x03 line.long 0x00 "L4_AP_REGION_l_L_4,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x328++0x03 line.long 0x00 "L4_AP_REGION_l_L_5,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x330++0x03 line.long 0x00 "L4_AP_REGION_l_L_6,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x338++0x03 line.long 0x00 "L4_AP_REGION_l_L_7,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x340++0x03 line.long 0x00 "L4_AP_REGION_l_L_8,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x348++0x03 line.long 0x00 "L4_AP_REGION_l_L_9,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x358++0x03 line.long 0x00 "L4_AP_REGION_l_L_11,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x360++0x03 line.long 0x00 "L4_AP_REGION_l_L_12,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x368++0x03 line.long 0x00 "L4_AP_REGION_l_L_13,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x370++0x03 line.long 0x00 "L4_AP_REGION_l_L_14,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x378++0x03 line.long 0x00 "L4_AP_REGION_l_L_15,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x380++0x03 line.long 0x00 "L4_AP_REGION_l_L_16,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x388++0x03 line.long 0x00 "L4_AP_REGION_l_L_17,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x390++0x03 line.long 0x00 "L4_AP_REGION_l_L_18,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x398++0x03 line.long 0x00 "L4_AP_REGION_l_L_19,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_20,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_21,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_22,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_23,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_25,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_26,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_27,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_28,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_29,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_30,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_31,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x400++0x03 line.long 0x00 "L4_AP_REGION_l_L_32,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x408++0x03 line.long 0x00 "L4_AP_REGION_l_L_33,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x410++0x03 line.long 0x00 "L4_AP_REGION_l_L_34,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x418++0x03 line.long 0x00 "L4_AP_REGION_l_L_35,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x420++0x03 line.long 0x00 "L4_AP_REGION_l_L_36,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x428++0x03 line.long 0x00 "L4_AP_REGION_l_L_37,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x430++0x03 line.long 0x00 "L4_AP_REGION_l_L_38,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x438++0x03 line.long 0x00 "L4_AP_REGION_l_L_39,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x448++0x03 line.long 0x00 "L4_AP_REGION_l_L_41,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x450++0x03 line.long 0x00 "L4_AP_REGION_l_L_42,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x458++0x03 line.long 0x00 "L4_AP_REGION_l_L_43,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x460++0x03 line.long 0x00 "L4_AP_REGION_l_L_44,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x468++0x03 line.long 0x00 "L4_AP_REGION_l_L_45,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x470++0x03 line.long 0x00 "L4_AP_REGION_l_L_46,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x478++0x03 line.long 0x00 "L4_AP_REGION_l_L_47,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x480++0x03 line.long 0x00 "L4_AP_REGION_l_L_48,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x488++0x03 line.long 0x00 "L4_AP_REGION_l_L_49,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x490++0x03 line.long 0x00 "L4_AP_REGION_l_L_50,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x498++0x03 line.long 0x00 "L4_AP_REGION_l_L_51,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_52,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_53,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_54,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_55,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_56,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_57,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_58,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_59,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_60,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_61,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_62,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_63,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x500++0x03 line.long 0x00 "L4_AP_REGION_l_L_64,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x508++0x03 line.long 0x00 "L4_AP_REGION_l_L_65,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x510++0x03 line.long 0x00 "L4_AP_REGION_l_L_66,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x518++0x03 line.long 0x00 "L4_AP_REGION_l_L_67,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x520++0x03 line.long 0x00 "L4_AP_REGION_l_L_68,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x528++0x03 line.long 0x00 "L4_AP_REGION_l_L_69,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x530++0x03 line.long 0x00 "L4_AP_REGION_l_L_70,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x538++0x03 line.long 0x00 "L4_AP_REGION_l_L_71,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x540++0x03 line.long 0x00 "L4_AP_REGION_l_L_72,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x548++0x03 line.long 0x00 "L4_AP_REGION_l_L_73,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x550++0x03 line.long 0x00 "L4_AP_REGION_l_L_74,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x558++0x03 line.long 0x00 "L4_AP_REGION_l_L_75,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x560++0x03 line.long 0x00 "L4_AP_REGION_l_L_76,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x568++0x03 line.long 0x00 "L4_AP_REGION_l_L_77,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x30C++0x03 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x314++0x03 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x31C++0x03 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x324++0x03 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x32C++0x03 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x334++0x03 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x33C++0x03 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x344++0x03 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x34C++0x03 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x35C++0x03 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x364++0x03 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x36C++0x03 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x374++0x03 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x37C++0x03 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x384++0x03 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x38C++0x03 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x394++0x03 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x39C++0x03 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x404++0x03 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x40C++0x03 line.long 0x00 "L4_AP_REGION_l_H_33,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x414++0x03 line.long 0x00 "L4_AP_REGION_l_H_34,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x41C++0x03 line.long 0x00 "L4_AP_REGION_l_H_35,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x424++0x03 line.long 0x00 "L4_AP_REGION_l_H_36,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x42C++0x03 line.long 0x00 "L4_AP_REGION_l_H_37,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x434++0x03 line.long 0x00 "L4_AP_REGION_l_H_38,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x43C++0x03 line.long 0x00 "L4_AP_REGION_l_H_39,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x44C++0x03 line.long 0x00 "L4_AP_REGION_l_H_41,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x454++0x03 line.long 0x00 "L4_AP_REGION_l_H_42,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x45C++0x03 line.long 0x00 "L4_AP_REGION_l_H_43,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x464++0x03 line.long 0x00 "L4_AP_REGION_l_H_44,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x46C++0x03 line.long 0x00 "L4_AP_REGION_l_H_45,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x474++0x03 line.long 0x00 "L4_AP_REGION_l_H_46,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x47C++0x03 line.long 0x00 "L4_AP_REGION_l_H_47,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x484++0x03 line.long 0x00 "L4_AP_REGION_l_H_48,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x48C++0x03 line.long 0x00 "L4_AP_REGION_l_H_49,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x494++0x03 line.long 0x00 "L4_AP_REGION_l_H_50,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x49C++0x03 line.long 0x00 "L4_AP_REGION_l_H_51,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_52,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_53,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_54,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_55,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_56,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_57,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_58,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_59,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_60,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_61,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_62,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_63,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x504++0x03 line.long 0x00 "L4_AP_REGION_l_H_64,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x50C++0x03 line.long 0x00 "L4_AP_REGION_l_H_65,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x514++0x03 line.long 0x00 "L4_AP_REGION_l_H_66,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x51C++0x03 line.long 0x00 "L4_AP_REGION_l_H_67,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x524++0x03 line.long 0x00 "L4_AP_REGION_l_H_68,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x52C++0x03 line.long 0x00 "L4_AP_REGION_l_H_69,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x534++0x03 line.long 0x00 "L4_AP_REGION_l_H_70,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x53C++0x03 line.long 0x00 "L4_AP_REGION_l_H_71,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x544++0x03 line.long 0x00 "L4_AP_REGION_l_H_72,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x54C++0x03 line.long 0x00 "L4_AP_REGION_l_H_73,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x554++0x03 line.long 0x00 "L4_AP_REGION_l_H_74,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x55C++0x03 line.long 0x00 "L4_AP_REGION_l_H_75,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x564++0x03 line.long 0x00 "L4_AP_REGION_l_H_76,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x56C++0x03 line.long 0x00 "L4_AP_REGION_l_H_77,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x48001000 ad:0x48001400 ) tree "L4_PER1_IA_IP$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x17 line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" rbitfld.long 0x08 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" newline hexmask.long.tbyte 0x08 0.--23. 1. "RESERVED," line.long 0x0C "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" line.long 0x10 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x10 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x10 30. "PROT_ERROR_PRIMARY," "0,1" rbitfld.long 0x10 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x10 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x10 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x10 24. "MERROR,Value of the OCP MError signal" "0,1" newline hexmask.long.tbyte 0x10 0.--23. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0F line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" rbitfld.long 0x00 26.--29. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "No errors,Unsupported command,Address hole,Protection violation" hexmask.long.word 0x00 14.--23. 1. "RESERVED,Read returns 0" rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 3.--7. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--2. "CMD,Command that has caused an error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that has caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" line.long 0x0C "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" width 0x0B tree.end repeat.end tree "L4_PER1_LA" base ad:0x48000800 rgroup.long 0x00++0x07 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" newline hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x10++0x17 line.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" line.long 0x04 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x08 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x08 28.--31. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "PROT_GROUPS,Number of protection groups in the current L4" "No protection group,1 protection group,2 protection groups,?,?,?,?,?,8 protection groups 0x9 to,?,?,?,?,?,?,Reserved" newline abitfld.long 0x08 16.--23. "NUMBER_REGIONS,Number of regions in the current L4" "0x00=Reserved,0x01=1 region,0x02=2 regions,0xFF=Reserved 'Max regions' is listed in on row.." newline hexmask.long.word 0x08 4.--15. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 0.--3. "SEGMENTS,Number of segments in the current L4" "Reserved,1 segment,2 segments,?,?,?,?,?,8 segments,?..." line.long 0x0C "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" hexmask.long.word 0x0C 19.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x0C 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 15. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 11. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "?,16-bit data width is specified,32-bit data width is specified,?..." newline bitfld.long 0x0C 6.--7. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" hexmask.long.tbyte 0x10 11.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "Time-out disabled,L4 interconnect clock cycles divided by 64,L4 interconnect clock cycles divided by 256,L4 interconnect clock cycles divided by 1024,L4 interconnect clock cycles divided by 4096,?..." newline hexmask.long.byte 0x10 0.--7. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x14 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" newline rbitfld.long 0x14 21.--23. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 20. "THREAD0_PRI,Sets thread priority" "0,1" newline hexmask.long.word 0x14 9.--19. 1. "RESERVED,Read returns 0" newline rbitfld.long 0x14 8. "EXT_CLOCK,Global external clock control" "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "RESERVED,Read returns 0" group.long 0x100++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_0,Mask of composite sideband flag(0)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x120++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_1,Mask of composite sideband flag(0)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x104++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_H_0,Status of composite sideband flag(0)" rgroup.long 0x124++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_H_1,Status of composite sideband flag(0)" group.long 0x110++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_0,Mask of composite sideband flag(1)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_1,Mask of composite sideband flag(1)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x114++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_H_0,Status of composite sideband flag(1)" rgroup.long 0x134++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_H_1,Status of composite sideband flag(1)" width 0x0B tree.end tree "L4_PER1_P1_TARG" base ad:0x44001C00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER1_P2_TARG" base ad:0x44001F00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER2_AP" base ad:0x48400000 rgroup.long 0x00++0x07 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x100++0x07 line.long 0x00 "L4_AP_SEGMENT_i_L,Defines the base address of each segment" line.long 0x04 "L4_AP_SEGMENT_i_H,Defines the size of each segment" hexmask.long 0x04 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x04 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x208++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x210++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x218++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x220++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x228++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x230++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x238++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x280++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x288++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x290++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x298++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Reserved" rgroup.long 0x28C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Reserved" rgroup.long 0x294++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Reserved" rgroup.long 0x29C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Reserved" rgroup.long 0x2A4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Reserved" rgroup.long 0x2AC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Reserved" rgroup.long 0x2B4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Reserved" rgroup.long 0x2BC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Reserved" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x308++0x03 line.long 0x00 "L4_AP_REGION_l_L_1,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x310++0x03 line.long 0x00 "L4_AP_REGION_l_L_2,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x318++0x03 line.long 0x00 "L4_AP_REGION_l_L_3,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x320++0x03 line.long 0x00 "L4_AP_REGION_l_L_4,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x328++0x03 line.long 0x00 "L4_AP_REGION_l_L_5,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x330++0x03 line.long 0x00 "L4_AP_REGION_l_L_6,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x338++0x03 line.long 0x00 "L4_AP_REGION_l_L_7,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x340++0x03 line.long 0x00 "L4_AP_REGION_l_L_8,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x348++0x03 line.long 0x00 "L4_AP_REGION_l_L_9,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x358++0x03 line.long 0x00 "L4_AP_REGION_l_L_11,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x360++0x03 line.long 0x00 "L4_AP_REGION_l_L_12,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x368++0x03 line.long 0x00 "L4_AP_REGION_l_L_13,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x370++0x03 line.long 0x00 "L4_AP_REGION_l_L_14,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x378++0x03 line.long 0x00 "L4_AP_REGION_l_L_15,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x380++0x03 line.long 0x00 "L4_AP_REGION_l_L_16,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x388++0x03 line.long 0x00 "L4_AP_REGION_l_L_17,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x390++0x03 line.long 0x00 "L4_AP_REGION_l_L_18,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x398++0x03 line.long 0x00 "L4_AP_REGION_l_L_19,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_20,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_21,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_22,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_23,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_25,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_26,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_27,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_28,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_29,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_30,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_31,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x400++0x03 line.long 0x00 "L4_AP_REGION_l_L_32,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x30C++0x03 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x314++0x03 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x31C++0x03 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x324++0x03 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x32C++0x03 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x334++0x03 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x33C++0x03 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x344++0x03 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x34C++0x03 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x35C++0x03 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x364++0x03 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x36C++0x03 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x374++0x03 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x37C++0x03 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x384++0x03 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x38C++0x03 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x394++0x03 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x39C++0x03 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x404++0x03 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" width 0x0B tree.end tree "L4_PER2_IA_IP0" base ad:0x48401000 rgroup.long 0x00++0x07 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x17 line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" rbitfld.long 0x08 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" newline hexmask.long.tbyte 0x08 0.--23. 1. "RESERVED," line.long 0x0C "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" line.long 0x10 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x10 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x10 30. "PROT_ERROR_PRIMARY," "0,1" rbitfld.long 0x10 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x10 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x10 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x10 24. "MERROR,Value of the OCP MError signal" "0,1" newline hexmask.long.tbyte 0x10 0.--23. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0F line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" rbitfld.long 0x00 26.--29. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "No errors,Unsupported command,Address hole,Protection violation" hexmask.long.word 0x00 14.--23. 1. "RESERVED,Read returns 0" rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 3.--7. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--2. "CMD,Command that has caused an error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that has caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" line.long 0x0C "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" width 0x0B tree.end tree "L4_PER2_LA" base ad:0x48400800 rgroup.long 0x00++0x07 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" newline hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x10++0x17 line.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" line.long 0x04 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x08 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x08 28.--31. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "PROT_GROUPS,Number of protection groups in the current L4" "No protection group,1 protection group,2 protection groups,?,?,?,?,?,8 protection groups 0x9 to,?,?,?,?,?,?,Reserved" newline abitfld.long 0x08 16.--23. "NUMBER_REGIONS,Number of regions in the current L4" "0x00=Reserved,0x01=1 region,0x02=2 regions,0xFF=Reserved 'Max regions' is listed in on row.." newline hexmask.long.word 0x08 4.--15. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 0.--3. "SEGMENTS,Number of segments in the current L4" "Reserved,1 segment,2 segments,?,?,?,?,?,8 segments,?..." line.long 0x0C "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" hexmask.long.word 0x0C 19.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x0C 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 15. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 11. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "?,16-bit data width is specified,32-bit data width is specified,?..." newline bitfld.long 0x0C 6.--7. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" hexmask.long.tbyte 0x10 11.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "Time-out disabled,L4 interconnect clock cycles divided by 64,L4 interconnect clock cycles divided by 256,L4 interconnect clock cycles divided by 1024,L4 interconnect clock cycles divided by 4096,?..." newline hexmask.long.byte 0x10 0.--7. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x14 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" newline rbitfld.long 0x14 21.--23. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 20. "THREAD0_PRI,Sets thread priority" "0,1" newline hexmask.long.word 0x14 9.--19. 1. "RESERVED,Read returns 0" newline rbitfld.long 0x14 8. "EXT_CLOCK,Global external clock control" "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "RESERVED,Read returns 0" group.long 0x100++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_0,Mask of composite sideband flag(0)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x120++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_1,Mask of composite sideband flag(0)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x104++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_H_0,Status of composite sideband flag(0)" rgroup.long 0x124++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_H_1,Status of composite sideband flag(0)" group.long 0x110++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_0,Mask of composite sideband flag(1)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_1,Mask of composite sideband flag(1)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x114++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_H_0,Status of composite sideband flag(1)" rgroup.long 0x134++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_H_1,Status of composite sideband flag(1)" width 0x0B tree.end tree "L4_PER2_P1_TARG" base ad:0x44002300 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER3_AP" base ad:0x48800000 rgroup.long 0x00++0x07 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x100++0x07 line.long 0x00 "L4_AP_SEGMENT_i_L,Defines the base address of each segment" line.long 0x04 "L4_AP_SEGMENT_i_H,Defines the size of each segment" hexmask.long 0x04 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x04 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x208++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x210++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x218++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x220++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x228++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x230++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x238++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x280++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x288++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x290++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x298++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Reserved" rgroup.long 0x28C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Reserved" rgroup.long 0x294++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Reserved" rgroup.long 0x29C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Reserved" rgroup.long 0x2A4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Reserved" rgroup.long 0x2AC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Reserved" rgroup.long 0x2B4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Reserved" rgroup.long 0x2BC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Reserved" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x308++0x03 line.long 0x00 "L4_AP_REGION_l_L_1,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x310++0x03 line.long 0x00 "L4_AP_REGION_l_L_2,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x318++0x03 line.long 0x00 "L4_AP_REGION_l_L_3,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x320++0x03 line.long 0x00 "L4_AP_REGION_l_L_4,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x328++0x03 line.long 0x00 "L4_AP_REGION_l_L_5,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x330++0x03 line.long 0x00 "L4_AP_REGION_l_L_6,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x338++0x03 line.long 0x00 "L4_AP_REGION_l_L_7,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x340++0x03 line.long 0x00 "L4_AP_REGION_l_L_8,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x348++0x03 line.long 0x00 "L4_AP_REGION_l_L_9,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x358++0x03 line.long 0x00 "L4_AP_REGION_l_L_11,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x360++0x03 line.long 0x00 "L4_AP_REGION_l_L_12,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x368++0x03 line.long 0x00 "L4_AP_REGION_l_L_13,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x370++0x03 line.long 0x00 "L4_AP_REGION_l_L_14,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x378++0x03 line.long 0x00 "L4_AP_REGION_l_L_15,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x380++0x03 line.long 0x00 "L4_AP_REGION_l_L_16,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x388++0x03 line.long 0x00 "L4_AP_REGION_l_L_17,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x390++0x03 line.long 0x00 "L4_AP_REGION_l_L_18,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x398++0x03 line.long 0x00 "L4_AP_REGION_l_L_19,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_20,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_21,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_22,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_23,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_25,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_26,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_27,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_28,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_29,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_30,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_31,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x400++0x03 line.long 0x00 "L4_AP_REGION_l_L_32,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x408++0x03 line.long 0x00 "L4_AP_REGION_l_L_33,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x410++0x03 line.long 0x00 "L4_AP_REGION_l_L_34,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x418++0x03 line.long 0x00 "L4_AP_REGION_l_L_35,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x420++0x03 line.long 0x00 "L4_AP_REGION_l_L_36,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x428++0x03 line.long 0x00 "L4_AP_REGION_l_L_37,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x430++0x03 line.long 0x00 "L4_AP_REGION_l_L_38,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x438++0x03 line.long 0x00 "L4_AP_REGION_l_L_39,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x448++0x03 line.long 0x00 "L4_AP_REGION_l_L_41,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x450++0x03 line.long 0x00 "L4_AP_REGION_l_L_42,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x458++0x03 line.long 0x00 "L4_AP_REGION_l_L_43,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x460++0x03 line.long 0x00 "L4_AP_REGION_l_L_44,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x468++0x03 line.long 0x00 "L4_AP_REGION_l_L_45,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x470++0x03 line.long 0x00 "L4_AP_REGION_l_L_46,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x478++0x03 line.long 0x00 "L4_AP_REGION_l_L_47,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x480++0x03 line.long 0x00 "L4_AP_REGION_l_L_48,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x488++0x03 line.long 0x00 "L4_AP_REGION_l_L_49,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x490++0x03 line.long 0x00 "L4_AP_REGION_l_L_50,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x498++0x03 line.long 0x00 "L4_AP_REGION_l_L_51,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_52,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_53,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_54,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_55,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_56,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_57,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_58,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_59,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_60,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_61,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_62,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x4F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_63,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x500++0x03 line.long 0x00 "L4_AP_REGION_l_L_64,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x508++0x03 line.long 0x00 "L4_AP_REGION_l_L_65,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x510++0x03 line.long 0x00 "L4_AP_REGION_l_L_66,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x518++0x03 line.long 0x00 "L4_AP_REGION_l_L_67,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x520++0x03 line.long 0x00 "L4_AP_REGION_l_L_68,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x528++0x03 line.long 0x00 "L4_AP_REGION_l_L_69,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x530++0x03 line.long 0x00 "L4_AP_REGION_l_L_70,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x538++0x03 line.long 0x00 "L4_AP_REGION_l_L_71,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x540++0x03 line.long 0x00 "L4_AP_REGION_l_L_72,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x548++0x03 line.long 0x00 "L4_AP_REGION_l_L_73,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x550++0x03 line.long 0x00 "L4_AP_REGION_l_L_74,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x558++0x03 line.long 0x00 "L4_AP_REGION_l_L_75,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x560++0x03 line.long 0x00 "L4_AP_REGION_l_L_76,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x568++0x03 line.long 0x00 "L4_AP_REGION_l_L_77,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x570++0x03 line.long 0x00 "L4_AP_REGION_l_L_78,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x578++0x03 line.long 0x00 "L4_AP_REGION_l_L_79,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x580++0x03 line.long 0x00 "L4_AP_REGION_l_L_80,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x588++0x03 line.long 0x00 "L4_AP_REGION_l_L_81,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x590++0x03 line.long 0x00 "L4_AP_REGION_l_L_82,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x598++0x03 line.long 0x00 "L4_AP_REGION_l_L_83,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_84,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_85,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_86,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_87,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_88,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_89,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_90,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_91,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_92,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x5E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_93,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x30C++0x03 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x314++0x03 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x31C++0x03 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x324++0x03 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x32C++0x03 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x334++0x03 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x33C++0x03 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x344++0x03 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x34C++0x03 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x35C++0x03 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x364++0x03 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x36C++0x03 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x374++0x03 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x37C++0x03 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x384++0x03 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x38C++0x03 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x394++0x03 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x39C++0x03 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x404++0x03 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x40C++0x03 line.long 0x00 "L4_AP_REGION_l_H_33,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x414++0x03 line.long 0x00 "L4_AP_REGION_l_H_34,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x41C++0x03 line.long 0x00 "L4_AP_REGION_l_H_35,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x424++0x03 line.long 0x00 "L4_AP_REGION_l_H_36,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x42C++0x03 line.long 0x00 "L4_AP_REGION_l_H_37,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x434++0x03 line.long 0x00 "L4_AP_REGION_l_H_38,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x43C++0x03 line.long 0x00 "L4_AP_REGION_l_H_39,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x44C++0x03 line.long 0x00 "L4_AP_REGION_l_H_41,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x454++0x03 line.long 0x00 "L4_AP_REGION_l_H_42,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x45C++0x03 line.long 0x00 "L4_AP_REGION_l_H_43,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x464++0x03 line.long 0x00 "L4_AP_REGION_l_H_44,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x46C++0x03 line.long 0x00 "L4_AP_REGION_l_H_45,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x474++0x03 line.long 0x00 "L4_AP_REGION_l_H_46,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x47C++0x03 line.long 0x00 "L4_AP_REGION_l_H_47,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x484++0x03 line.long 0x00 "L4_AP_REGION_l_H_48,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x48C++0x03 line.long 0x00 "L4_AP_REGION_l_H_49,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x494++0x03 line.long 0x00 "L4_AP_REGION_l_H_50,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x49C++0x03 line.long 0x00 "L4_AP_REGION_l_H_51,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_52,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_53,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_54,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_55,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_56,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_57,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_58,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_59,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_60,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_61,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_62,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x4FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_63,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x504++0x03 line.long 0x00 "L4_AP_REGION_l_H_64,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x50C++0x03 line.long 0x00 "L4_AP_REGION_l_H_65,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x514++0x03 line.long 0x00 "L4_AP_REGION_l_H_66,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x51C++0x03 line.long 0x00 "L4_AP_REGION_l_H_67,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x524++0x03 line.long 0x00 "L4_AP_REGION_l_H_68,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x52C++0x03 line.long 0x00 "L4_AP_REGION_l_H_69,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x534++0x03 line.long 0x00 "L4_AP_REGION_l_H_70,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x53C++0x03 line.long 0x00 "L4_AP_REGION_l_H_71,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x544++0x03 line.long 0x00 "L4_AP_REGION_l_H_72,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x54C++0x03 line.long 0x00 "L4_AP_REGION_l_H_73,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x554++0x03 line.long 0x00 "L4_AP_REGION_l_H_74,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x55C++0x03 line.long 0x00 "L4_AP_REGION_l_H_75,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x564++0x03 line.long 0x00 "L4_AP_REGION_l_H_76,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x56C++0x03 line.long 0x00 "L4_AP_REGION_l_H_77,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x574++0x03 line.long 0x00 "L4_AP_REGION_l_H_78,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x57C++0x03 line.long 0x00 "L4_AP_REGION_l_H_79,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x584++0x03 line.long 0x00 "L4_AP_REGION_l_H_80,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x58C++0x03 line.long 0x00 "L4_AP_REGION_l_H_81,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x594++0x03 line.long 0x00 "L4_AP_REGION_l_H_82,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x59C++0x03 line.long 0x00 "L4_AP_REGION_l_H_83,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_84,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_85,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_86,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_87,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_88,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_89,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_90,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_91,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_92,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x5EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_93,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" width 0x0B tree.end repeat 2. (list 1. 2. )(list ad:0x48801400 ad:0x48801800 ) tree "L4_PER3_IA_IP$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x17 line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" rbitfld.long 0x08 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" newline hexmask.long.tbyte 0x08 0.--23. 1. "RESERVED," line.long 0x0C "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" line.long 0x10 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x10 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x10 30. "PROT_ERROR_PRIMARY," "0,1" rbitfld.long 0x10 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x10 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x10 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x10 24. "MERROR,Value of the OCP MError signal" "0,1" newline hexmask.long.tbyte 0x10 0.--23. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0F line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" rbitfld.long 0x00 26.--29. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "No errors,Unsupported command,Address hole,Protection violation" hexmask.long.word 0x00 14.--23. 1. "RESERVED,Read returns 0" rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 3.--7. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--2. "CMD,Command that has caused an error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that has caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" line.long 0x0C "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" width 0x0B tree.end repeat.end tree "L4_PER3_LA" base ad:0x48800800 rgroup.long 0x00++0x07 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" newline hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x10++0x17 line.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" line.long 0x04 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x08 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x08 28.--31. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "PROT_GROUPS,Number of protection groups in the current L4" "No protection group,1 protection group,2 protection groups,?,?,?,?,?,8 protection groups 0x9 to,?,?,?,?,?,?,Reserved" newline abitfld.long 0x08 16.--23. "NUMBER_REGIONS,Number of regions in the current L4" "0x00=Reserved,0x01=1 region,0x02=2 regions,0xFF=Reserved 'Max regions' is listed in on row.." newline hexmask.long.word 0x08 4.--15. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 0.--3. "SEGMENTS,Number of segments in the current L4" "Reserved,1 segment,2 segments,?,?,?,?,?,8 segments,?..." line.long 0x0C "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" hexmask.long.word 0x0C 19.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x0C 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 15. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 11. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "?,16-bit data width is specified,32-bit data width is specified,?..." newline bitfld.long 0x0C 6.--7. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" hexmask.long.tbyte 0x10 11.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "Time-out disabled,L4 interconnect clock cycles divided by 64,L4 interconnect clock cycles divided by 256,L4 interconnect clock cycles divided by 1024,L4 interconnect clock cycles divided by 4096,?..." newline hexmask.long.byte 0x10 0.--7. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x14 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" newline rbitfld.long 0x14 21.--23. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 20. "THREAD0_PRI,Sets thread priority" "0,1" newline hexmask.long.word 0x14 9.--19. 1. "RESERVED,Read returns 0" newline rbitfld.long 0x14 8. "EXT_CLOCK,Global external clock control" "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "RESERVED,Read returns 0" group.long 0x100++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_0,Mask of composite sideband flag(0)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x120++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_1,Mask of composite sideband flag(0)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x104++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_H_0,Status of composite sideband flag(0)" rgroup.long 0x124++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_H_1,Status of composite sideband flag(0)" group.long 0x110++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_0,Mask of composite sideband flag(1)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_1,Mask of composite sideband flag(1)" hexmask.long 0x00 4.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x114++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_H_0,Status of composite sideband flag(1)" rgroup.long 0x134++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_H_1,Status of composite sideband flag(1)" width 0x0B tree.end tree "L4_PER3_P1_TARG" base ad:0x44002600 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER3_P2_TARG" base ad:0x44002700 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_WKUP_AP" base ad:0x4AE00000 rgroup.long 0x00++0x07 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x100++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_0,Defines the base address of each segment" rgroup.long 0x108++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_1,Defines the base address of each segment" rgroup.long 0x110++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_2,Defines the base address of each segment" rgroup.long 0x118++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_3,Defines the base address of each segment" rgroup.long 0x104++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_0,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x10C++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_1,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x114++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_2,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x11C++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_3,Defines the size of each segment" hexmask.long 0x00 6.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 0.--5. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x208++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x210++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x218++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x220++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x228++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x230++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x238++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Defines which initiator can access the protection groupk" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,The protection group is accessible by an initiator with ConnID when bit of this field is set to 1" group.long 0x280++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x288++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x290++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x298++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2A8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" group.long 0x2B8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Defines the initiator requests accepted or not by the L4 firewalls depending on combination of L4 qualifiers" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Reserved" rgroup.long 0x28C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Reserved" rgroup.long 0x294++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Reserved" rgroup.long 0x29C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Reserved" rgroup.long 0x2A4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Reserved" rgroup.long 0x2AC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Reserved" rgroup.long 0x2B4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Reserved" rgroup.long 0x2BC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Reserved" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x308++0x03 line.long 0x00 "L4_AP_REGION_l_L_1,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x310++0x03 line.long 0x00 "L4_AP_REGION_l_L_2,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x318++0x03 line.long 0x00 "L4_AP_REGION_l_L_3,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x320++0x03 line.long 0x00 "L4_AP_REGION_l_L_4,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x328++0x03 line.long 0x00 "L4_AP_REGION_l_L_5,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x330++0x03 line.long 0x00 "L4_AP_REGION_l_L_6,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x338++0x03 line.long 0x00 "L4_AP_REGION_l_L_7,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x340++0x03 line.long 0x00 "L4_AP_REGION_l_L_8,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x348++0x03 line.long 0x00 "L4_AP_REGION_l_L_9,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x358++0x03 line.long 0x00 "L4_AP_REGION_l_L_11,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x360++0x03 line.long 0x00 "L4_AP_REGION_l_L_12,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x368++0x03 line.long 0x00 "L4_AP_REGION_l_L_13,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x370++0x03 line.long 0x00 "L4_AP_REGION_l_L_14,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x378++0x03 line.long 0x00 "L4_AP_REGION_l_L_15,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x380++0x03 line.long 0x00 "L4_AP_REGION_l_L_16,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x388++0x03 line.long 0x00 "L4_AP_REGION_l_L_17,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x390++0x03 line.long 0x00 "L4_AP_REGION_l_L_18,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x398++0x03 line.long 0x00 "L4_AP_REGION_l_L_19,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_20,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_21,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_22,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_23,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_25,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_26,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_27,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_28,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_29,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_30,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x3F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_31,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x400++0x03 line.long 0x00 "L4_AP_REGION_l_L_32,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x408++0x03 line.long 0x00 "L4_AP_REGION_l_L_33,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x410++0x03 line.long 0x00 "L4_AP_REGION_l_L_34,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x418++0x03 line.long 0x00 "L4_AP_REGION_l_L_35,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x420++0x03 line.long 0x00 "L4_AP_REGION_l_L_36,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x428++0x03 line.long 0x00 "L4_AP_REGION_l_L_37,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x430++0x03 line.long 0x00 "L4_AP_REGION_l_L_38,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x438++0x03 line.long 0x00 "L4_AP_REGION_l_L_39,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x448++0x03 line.long 0x00 "L4_AP_REGION_l_L_41,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x450++0x03 line.long 0x00 "L4_AP_REGION_l_L_42,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x458++0x03 line.long 0x00 "L4_AP_REGION_l_L_43,Defines the base address of the region in respect to the segment it belongs to" hexmask.long.word 0x00 21.--31. 1. "RESERVED,Read returns 0" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x30C++0x03 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x314++0x03 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x31C++0x03 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x324++0x03 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x32C++0x03 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x334++0x03 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x33C++0x03 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x344++0x03 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x34C++0x03 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x35C++0x03 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x364++0x03 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x36C++0x03 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x374++0x03 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x37C++0x03 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x384++0x03 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x38C++0x03 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x394++0x03 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x39C++0x03 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x3FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x404++0x03 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x40C++0x03 line.long 0x00 "L4_AP_REGION_l_H_33,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x414++0x03 line.long 0x00 "L4_AP_REGION_l_H_34,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x41C++0x03 line.long 0x00 "L4_AP_REGION_l_H_35,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x424++0x03 line.long 0x00 "L4_AP_REGION_l_H_36,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x42C++0x03 line.long 0x00 "L4_AP_REGION_l_H_37,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x434++0x03 line.long 0x00 "L4_AP_REGION_l_H_38,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x43C++0x03 line.long 0x00 "L4_AP_REGION_l_H_39,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x44C++0x03 line.long 0x00 "L4_AP_REGION_l_H_41,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x454++0x03 line.long 0x00 "L4_AP_REGION_l_H_42,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" group.long 0x45C++0x03 line.long 0x00 "L4_AP_REGION_l_H_43,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 23. "RESERVED,Read returns 0" "0,1" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Read returns 0" "0,1" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" rbitfld.long 0x00 15.--16. "RESERVED,Read returns 0" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 7. "RESERVED,Read returns 0" "0,1" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" width 0x0B tree.end tree "L4_WKUP_COUNTER_32K" base ad:0x4AE04000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION,This register contains the sync counter IP revision code" group.long 0x10++0x03 line.long 0x00 "SYSCONFIG,This register is used for idle modes only" hexmask.long 0x00 5.--31. 1. "Reserved,Reads return 0" bitfld.long 0x00 3.--4. "IDLEMODE,Power management REQ/ACK control" "0,1,2,3" rbitfld.long 0x00 1.--2. "Reserved,Reads return 0" "0,1,2,3" bitfld.long 0x00 0. "SYNCMODE,Synchronization scheme0x0 Gray synchronization scheme" "0,1" rgroup.long 0x30++0x03 line.long 0x00 "CR,This register contains the 32-kHz sync counter value" width 0x0B tree.end tree "L4_WKUP_IA_IP0" base ad:0x4AE01000 rgroup.long 0x00++0x07 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x17 line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" rbitfld.long 0x08 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" newline hexmask.long.tbyte 0x08 0.--23. 1. "RESERVED," line.long 0x0C "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" line.long 0x10 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x10 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x10 30. "PROT_ERROR_PRIMARY," "0,1" rbitfld.long 0x10 28.--29. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x10 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x10 25.--26. "RESERVED,Read returns 0" "0,1,2,3" rbitfld.long 0x10 24. "MERROR,Value of the OCP MError signal" "0,1" newline hexmask.long.tbyte 0x10 0.--23. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0F line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" rbitfld.long 0x00 26.--29. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "No errors,Unsupported command,Address hole,Protection violation" hexmask.long.word 0x00 14.--23. 1. "RESERVED,Read returns 0" rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 3.--7. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--2. "CMD,Command that has caused an error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that has caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" line.long 0x0C "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" width 0x0B tree.end tree "L4_WKUP_LA" base ad:0x4AE00800 rgroup.long 0x00++0x07 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" newline hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x10++0x17 line.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" line.long 0x04 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x08 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x08 28.--31. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "PROT_GROUPS,Number of protection groups in the current L4" "No protection group,1 protection group,2 protection groups,?,?,?,?,?,8 protection groups 0x9 to,?,?,?,?,?,?,Reserved" newline abitfld.long 0x08 16.--23. "NUMBER_REGIONS,Number of regions in the current L4" "0x00=Reserved,0x01=1 region,0x02=2 regions,0xFF=Reserved 'Max regions' is listed in on row.." newline hexmask.long.word 0x08 4.--15. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 0.--3. "SEGMENTS,Number of segments in the current L4" "Reserved,1 segment,2 segments,?,?,?,?,?,8 segments,?..." line.long 0x0C "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" hexmask.long.word 0x0C 19.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x0C 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 15. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 11. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x0C 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "?,16-bit data width is specified,32-bit data width is specified,?..." newline bitfld.long 0x0C 6.--7. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" hexmask.long.tbyte 0x10 11.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "Time-out disabled,L4 interconnect clock cycles divided by 64,L4 interconnect clock cycles divided by 256,L4 interconnect clock cycles divided by 1024,L4 interconnect clock cycles divided by 4096,?..." newline hexmask.long.byte 0x10 0.--7. 1. "RESERVED,Read returns 0" line.long 0x14 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x14 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" newline rbitfld.long 0x14 21.--23. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 20. "THREAD0_PRI,Sets thread priority" "0,1" newline hexmask.long.word 0x14 9.--19. 1. "RESERVED,Read returns 0" newline rbitfld.long 0x14 8. "EXT_CLOCK,Global external clock control" "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "RESERVED,Read returns 0" width 0x0B tree.end tree "L4_WKUP_TARG" base ad:0x44001D00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4PER_CM_CORE" base ad:0x4A009700 group.long 0x00++0x03 line.long 0x00 "CM_L4PER_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. "CLKACTIVITY_L4PER_32K_GFCLK,This field indicates the state of the L4PER_32K_FCLK clock in the domain" "CLKACTIVITY_L4PER_32K_GFCLK_0,CLKACTIVITY_L4PER_32K_GFCLK_1" newline rbitfld.long 0x00 26. "CLKACTIVITY_UART5_GFCLK,This field indicates the state of the UART5_GFCLK clock in the domain" "CLKACTIVITY_UART5_GFCLK_0,CLKACTIVITY_UART5_GFCLK_1" rbitfld.long 0x00 25. "CLKACTIVITY_PER_192M_GFCLK,This field indicates the state of the PER_192M_GFCLK clock in the domain" "CLKACTIVITY_PER_192M_GFCLK_0,CLKACTIVITY_PER_192M_GFCLK_1" newline rbitfld.long 0x00 24. "CLKACTIVITY_GPIO_GFCLK,This field indicates the state of the GPIO_GFCLK clock in the domain" "CLKACTIVITY_GPIO_GFCLK_0,CLKACTIVITY_GPIO_GFCLK_1" rbitfld.long 0x00 23. "CLKACTIVITY_MMC4_GFCLK,This field indicates the state of the MMC4_GFCLK clock in the domain" "CLKACTIVITY_MMC4_GFCLK_0,CLKACTIVITY_MMC4_GFCLK_1" newline rbitfld.long 0x00 22. "CLKACTIVITY_MMC3_GFCLK,This field indicates the state of the MMC3_GFCLK clock in the domain" "CLKACTIVITY_MMC3_GFCLK_0,CLKACTIVITY_MMC3_GFCLK_1" rbitfld.long 0x00 21. "CLKACTIVITY_PER_96M_GFCLK,This field indicates the state of the PER_96M_GFCLK clock in the domain" "CLKACTIVITY_PER_96M_GFCLK_0,CLKACTIVITY_PER_96M_GFCLK_1" newline rbitfld.long 0x00 20. "CLKACTIVITY_PER_48M_GFCLK,This field indicates the state of the PER_48M_GFCLK clock in the domain" "CLKACTIVITY_PER_48M_GFCLK_0,CLKACTIVITY_PER_48M_GFCLK_1" rbitfld.long 0x00 19. "CLKACTIVITY_PER_12M_GFCLK,This field indicates the state of the PER_12M_GFCLK clock in the domain" "CLKACTIVITY_PER_12M_GFCLK_0,CLKACTIVITY_PER_12M_GFCLK_1" newline rbitfld.long 0x00 18. "CLKACTIVITY_UART4_GFCLK,This field indicates the state of the UART4_GFCLK clock in the domain" "CLKACTIVITY_UART4_GFCLK_0,CLKACTIVITY_UART4_GFCLK_1" rbitfld.long 0x00 17. "CLKACTIVITY_UART3_GFCLK,This field indicates the state of the UART3_GFCLK clock in the domain" "CLKACTIVITY_UART3_GFCLK_0,CLKACTIVITY_UART3_GFCLK_1" newline rbitfld.long 0x00 16. "CLKACTIVITY_UART2_GFCLK,This field indicates the state of the UART2_GFCLK clock in the domain" "CLKACTIVITY_UART2_GFCLK_0,CLKACTIVITY_UART2_GFCLK_1" rbitfld.long 0x00 15. "CLKACTIVITY_UART1_GFCLK,This field indicates the state of the UART1_GFCLK clock in the domain" "CLKACTIVITY_UART1_GFCLK_0,CLKACTIVITY_UART1_GFCLK_1" newline rbitfld.long 0x00 14. "CLKACTIVITY_DCC5_GFCLK,This field indicates the state of the DMT9_GFCLK clock in the domain" "CLKACTIVITY_DCC5_GFCLK_0,CLKACTIVITY_DCC5_GFCLK_1" rbitfld.long 0x00 13. "CLKACTIVITY_TIMER4_GFCLK,This field indicates the state of the DMT4_GFCLK clock in the domain" "CLKACTIVITY_TIMER4_GFCLK_0,CLKACTIVITY_TIMER4_GFCLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_TIMER3_GFCLK,This field indicates the state of the DMT3_GFCLK clock in the domain" "CLKACTIVITY_TIMER3_GFCLK_0,CLKACTIVITY_TIMER3_GFCLK_1" rbitfld.long 0x00 11. "CLKACTIVITY_TIMER2_GFCLK,This field indicates the state of the DMT2_GFCLK clock in the domain" "CLKACTIVITY_TIMER2_GFCLK_0,CLKACTIVITY_TIMER2_GFCLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_DCC7_GFCLK,This field indicates the state of the DMT11_GFCLK clock in the domain" "CLKACTIVITY_DCC7_GFCLK_0,CLKACTIVITY_DCC7_GFCLK_1" rbitfld.long 0x00 9. "CLKACTIVITY_DCC6_GFCLK,This field indicates the state of the DMT10_GFCLK clock in the domain" "CLKACTIVITY_DCC6_GFCLK_0,CLKACTIVITY_DCC6_GFCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_L4PER_L3_GICLK,This field indicates the state of the L4PER_L3_GICLK clock in the domain" "CLKACTIVITY_L4PER_L3_GICLK_0,CLKACTIVITY_L4PER_L3_GICLK_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4PER clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x08++0x07 line.long 0x00 "CM_L4PER_DYNAMICDEP,This register controls the dynamic domain depedencies from L4PER domain towards 'target' domains" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 15.--23. 1. "RESERVED," rbitfld.long 0x00 14. "L4SEC_DYNDEP,Dynamic dependency towards L4SEC clock domain" "?,L4SEC_DYNDEP_1" newline rbitfld.long 0x00 9.--13. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 8. "DSS_DYNDEP,Dynamic dependency towards DSS clock domain" "?,DSS_DYNDEP_1" newline rbitfld.long 0x00 7. "L3INIT_DYNDEP,Dynamic dependency towards L3INIT clock domain" "?,L3INIT_DYNDEP_1" rbitfld.long 0x00 4.--6. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "IPU_DYNDEP,Dynamic dependency towards IPU clock domain" "?,IPU_DYNDEP_1" rbitfld.long 0x00 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x04 "CM_L4PER2_L4_PER2_CLKCTRL,This register manages the L4_PER2 clocks" hexmask.long.word 0x04 18.--31. 1. "RESERVED," bitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x04 2.--15. 1. "RESERVED," bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x14++0x07 line.long 0x00 "CM_L4PER3_L4_PER3_CLKCTRL,This register manages the L4_PER3 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" line.long 0x04 "CM_L4PER2_PRUSS1_CLKCTRL,This register manages the PRUSS clocks" hexmask.long.word 0x04 19.--31. 1. "RESERVED," rbitfld.long 0x04 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x04 2.--15. 1. "RESERVED," newline bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x20++0x03 line.long 0x00 "CM_L4PER2_PRUSS2_CLKCTRL,This register manages the PRUSS clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x28++0x03 line.long 0x00 "CM_L4PER_DCC6_CLKCTRL,This register manages the DCC6 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x30++0x03 line.long 0x00 "CM_L4PER_DCC7_CLKCTRL,This register manages the DCC7 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x38++0x03 line.long 0x00 "CM_L4PER_TIMER2_CLKCTRL,This register manages the TIMER2 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_L4PER_TIMER3_CLKCTRL,This register manages the TIMER3 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x48++0x03 line.long 0x00 "CM_L4PER_TIMER4_CLKCTRL,This register manages the TIMER4 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x50++0x03 line.long 0x00 "CM_L4PER_DCC5_CLKCTRL,This register manages the DCC5 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x58++0x03 line.long 0x00 "CM_L4PER_ELM_CLKCTRL,This register manages the ELM clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x60++0x03 line.long 0x00 "CM_L4PER_GPIO2_CLKCTRL,This register manages the GPIO2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x68++0x03 line.long 0x00 "CM_L4PER_GPIO3_CLKCTRL,This register manages the GPIO3 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x70++0x03 line.long 0x00 "CM_L4PER_GPIO4_CLKCTRL,This register manages the GPIO4 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x78++0x03 line.long 0x00 "CM_L4PER_GPIO5_CLKCTRL,This register manages the GPIO5 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x80++0x03 line.long 0x00 "CM_L4PER_GPIO6_CLKCTRL,This register manages the GPIO6 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x88++0x03 line.long 0x00 "CM_L4PER_ESM_CLKCTRL,This register manages the ESM clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x90++0x03 line.long 0x00 "CM_L4PER2_PWMSS2_CLKCTRL,This register manages the PWMSS1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x98++0x03 line.long 0x00 "CM_L4PER2_PWMSS3_CLKCTRL,This register manages the PWMSS2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xA0++0x03 line.long 0x00 "CM_L4PER_I2C1_CLKCTRL,This register manages the I2C1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xA8++0x03 line.long 0x00 "CM_L4PER_I2C2_CLKCTRL,This register manages the I2C2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xB0++0x03 line.long 0x00 "CM_L4PER_I2C3_CLKCTRL,This register manages the I2C3 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xB8++0x03 line.long 0x00 "CM_L4PER_I2C4_CLKCTRL,This register manages the I2C4 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0xC0++0x0B line.long 0x00 "CM_L4PER_L4_PER1_CLKCTRL,This register manages the L4_PER1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" line.long 0x04 "CM_L4PER2_PWMSS1_CLKCTRL,This register manages the PWMSS1 clocks" hexmask.long.word 0x04 18.--31. 1. "RESERVED," rbitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x04 2.--15. 1. "RESERVED," bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x08 "CM_L4PER3_DCC1_CLKCTRL,This register manages the DCC1 clocks" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. "CLKSEL,Select the source of the functional clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" newline rbitfld.long 0x08 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x08 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x08 2.--15. 1. "RESERVED," bitfld.long 0x08 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xD0++0x03 line.long 0x00 "CM_L4PER3_DCC2_CLKCTRL,This register manages the DCC2 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xD8++0x03 line.long 0x00 "CM_L4PER3_DCC3_CLKCTRL,This register manages the DCC3 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xF0++0x03 line.long 0x00 "CM_L4PER_MCSPI1_CLKCTRL,This register manages the MCSPI1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xF8++0x03 line.long 0x00 "CM_L4PER_MCSPI2_CLKCTRL,This register manages the MCSPI2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x100++0x03 line.long 0x00 "CM_L4PER_MCSPI3_CLKCTRL,This register manages the MCSPI3 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x108++0x03 line.long 0x00 "CM_L4PER_MCSPI4_CLKCTRL,This register manages the MCSPI4 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x110++0x03 line.long 0x00 "CM_L4PER_GPIO7_CLKCTRL,This register manages the GPIO7 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x118++0x03 line.long 0x00 "CM_L4PER_GPIO8_CLKCTRL,This register manages the GPIO8 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x120++0x03 line.long 0x00 "CM_L4PER_MMC3_CLKCTRL,This register manages the MMC3 clocks" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 25.--26. "CLKSEL_DIV,Selects the divider value" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" newline bitfld.long 0x00 24. "CLKSEL_MUX,Select the clock for the MMC from DPLL_PER" "CLKSEL_MUX_0,CLKSEL_MUX_1" rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,MMC optional clock control: 32K CLK" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x128++0x03 line.long 0x00 "CM_L4PER_MMC4_CLKCTRL,This register manages the MMC4 clocks" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 25.--26. "CLKSEL_DIV,Selects the divider value" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" newline bitfld.long 0x00 24. "CLKSEL_MUX,Select the clock for the MMC from DPLL_PER" "CLKSEL_MUX_0,CLKSEL_MUX_1" rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,MMC optional clock control: 32K CLK" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x130++0x03 line.long 0x00 "CM_L4PER3_DCC4_CLKCTRL,This register manages the DCC4 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x138++0x03 line.long 0x00 "CM_L4PER2_QSPI_CLKCTRL,This register manages the QSPI clocks" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 25.--26. "CLKSEL_DIV,QSPI clock divide ratio" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" newline bitfld.long 0x00 24. "CLKSEL_SOURCE,Selects the source of the functional clock" "CLKSEL_SOURCE_0,CLKSEL_SOURCE_1" rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x140++0x03 line.long 0x00 "CM_L4PER_UART1_CLKCTRL,This register manages the UART1 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNC_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x148++0x03 line.long 0x00 "CM_L4PER_UART2_CLKCTRL,This register manages the UART2 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNC_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x150++0x03 line.long 0x00 "CM_L4PER_UART3_CLKCTRL,This register manages the UART3 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNC_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x158++0x03 line.long 0x00 "CM_L4PER_UART4_CLKCTRL,This register manages the UART4 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x160++0x03 line.long 0x00 "CM_L4PER2_ADC_CLKCTRL,This register manages the ADC clocks" bitfld.long 0x00 28.--31. "CLKSEL_AHCLKR,Selects reference clock for AHCLKR" "CLKSEL_AHCLKR_0,CLKSEL_AHCLKR_1,CLKSEL_AHCLKR_2,CLKSEL_AHCLKR_3,CLKSEL_AHCLKR_4,CLKSEL_AHCLKR_5,CLKSEL_AHCLKR_6,CLKSEL_AHCLKR_7,CLKSEL_AHCLKR_8,CLKSEL_AHCLKR_9,CLKSEL_AHCLKR_10,CLKSEL_AHCLKR_11,CLKSEL_AHCLKR_12,CLKSEL_AHCLKR_13,CLKSEL_AHCLKR_14,CLKSEL_AHCLKR_15" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" newline bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x00 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x168++0x03 line.long 0x00 "CM_L4PER2_ATL_CLKCTRL,This register manages the ATL module mode (SR2.0)" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" newline bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x00 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x170++0x03 line.long 0x00 "CM_L4PER_UART5_CLKCTRL,This register manages the UART5 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x178++0x03 line.long 0x00 "CM_L4PER2_MCASP5_CLKCTRL,This register manages the MCASP3 clocks (SR2.0)" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" newline bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x00 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x180++0x0B line.long 0x00 "CM_L4SEC_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_L4SEC_L3_GICLK,This field indicates the state of the L3_SECURE_GICLK clock in the domain" "CLKACTIVITY_L4SEC_L3_GICLK_0,CLKACTIVITY_L4SEC_L3_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4PER clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_L4SEC_STATICDEP,This register controls the static domain depedencies from L4SEC domain towards 'target' domains" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED," bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline hexmask.long.byte 0x04 6.--12. 1. "RESERVED," rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "CM_L4SEC_DYNAMICDEP,This register controls the dynamic domain depedencies from L4SEC domain towards 'target' domains" hexmask.long 0x08 6.--31. 1. "RESERVED," bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "L3MAIN1_DYNDEP_0,?" newline bitfld.long 0x08 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "CM_L4PER2_MCASP8_CLKCTRL,This register manages the MCASP8 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" newline bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x00 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x198++0x03 line.long 0x00 "CM_L4PER2_MCASP4_CLKCTRL,This register manages the MCASP2 clocks (SR2.0)" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" newline bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x00 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1A0++0x03 line.long 0x00 "CM_L4SEC_AES1_CLKCTRL,This register manages the AES1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1A8++0x03 line.long 0x00 "CM_L4SEC_AES2_CLKCTRL,This register manages the AES2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1B0++0x03 line.long 0x00 "CM_L4SEC_DES3DES_CLKCTRL,This register manages the DES3DES clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1B8++0x03 line.long 0x00 "CM_L4SEC_FPKA_CLKCTRL,This register manages the FPKA clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1C0++0x03 line.long 0x00 "CM_L4SEC_RNG_CLKCTRL,This register manages the RNG clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1C8++0x03 line.long 0x00 "CM_L4SEC_SHA2MD51_CLKCTRL,This register manages the SHA2MD51 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1D0++0x03 line.long 0x00 "CM_L4PER2_UART7_CLKCTRL,This register manages the UART7 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x1D8++0x03 line.long 0x00 "CM_L4SEC_DMA_CRYPTO_CLKCTRL,This register manages the DMA_CRYPTO clocks" hexmask.long.word 0x00 19.--31. 1. "RESERVED," bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x1E0++0x03 line.long 0x00 "CM_L4PER2_UART8_CLKCTRL,This register manages the UART8 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1E8++0x03 line.long 0x00 "CM_L4PER2_UART9_CLKCTRL,This register manages the UART9 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1F0++0x03 line.long 0x00 "CM_L4PER2_DCAN2_CLKCTRL,This register manages the MCAN clocks (SR2.0) or DCAN2 clocks (SR1.0)" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1F8++0x1F line.long 0x00 "CM_L4SEC_SHA2MD52_CLKCTRL,This register manages the SHA2MD52 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x04 "CM_L4PER2_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x04 31. "CLKACTIVITY_MCASP8_AUX_GFCLK,This field indicates the state of the MCASP8_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP8_AUX_GFCLK_0,CLKACTIVITY_MCASP8_AUX_GFCLK_1" rbitfld.long 0x04 30. "CLKACTIVITY_MCASP8_AHCLKX,This field indicates the state of the MCASP8_AHCLKX clock in the domain" "CLKACTIVITY_MCASP8_AHCLKX_0,CLKACTIVITY_MCASP8_AHCLKX_1" newline rbitfld.long 0x04 29. "CLKACTIVITY_MCASP7_AUX_GFCLK,This field indicates the state of the MCASP7_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP7_AUX_GFCLK_0,CLKACTIVITY_MCASP7_AUX_GFCLK_1" rbitfld.long 0x04 28. "CLKACTIVITY_MCASP7_AHCLK,This field indicates the state of the MCASP7_AHCLKX clock in the domain" "CLKACTIVITY_MCASP7_AHCLK_0,CLKACTIVITY_MCASP7_AHCLK_1" newline rbitfld.long 0x04 27. "CLKACTIVITY_MCASP6_AUX_GFCLK,This field indicates the state of the MCASP6_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP6_AUX_GFCLK_0,CLKACTIVITY_MCASP6_AUX_GFCLK_1" rbitfld.long 0x04 26. "CLKACTIVITY_MCASP6_AHCLKX,This field indicates the state of the MCASP6_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP6_AHCLKX_0,CLKACTIVITY_MCASP6_AHCLKX_1" newline rbitfld.long 0x04 25. "CLKACTIVITY_MCASP5_AHCLKX,This field indicates the state of the MCASP5_AHCLKX clock in the domain" "CLKACTIVITY_MCASP5_AHCLKX_0,CLKACTIVITY_MCASP5_AHCLKX_1" rbitfld.long 0x04 24. "CLKACTIVITY_MCASP5_AUX_GFCLK,This field indicates the state of the MCASP5_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP5_AUX_GFCLK_0,CLKACTIVITY_MCASP5_AUX_GFCLK_1" newline rbitfld.long 0x04 23. "CLKACTIVITY_MCASP4_AUX_GFCLK,This field indicates the state of the MCASP4_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP4_AUX_GFCLK_0,CLKACTIVITY_MCASP4_AUX_GFCLK_1" rbitfld.long 0x04 22. "CLKACTIVITY_MCASP4_AHCLKX,This field indicates the state of the MCASP4_AHCLKX clock in the domain" "CLKACTIVITY_MCASP4_AHCLKX_0,CLKACTIVITY_MCASP4_AHCLKX_1" newline rbitfld.long 0x04 21. "CLKACTIVITY_MCASP3_AUX_GFCLK,This field indicates the state of the MCASP3_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP3_AUX_GFCLK_0,CLKACTIVITY_MCASP3_AUX_GFCLK_1" rbitfld.long 0x04 20. "CLKACTIVITY_MCASP3_AHCLKX,This field indicates the state of the MCASP3_AHCLKX clock in the domain" "CLKACTIVITY_MCASP3_AHCLKX_0,CLKACTIVITY_MCASP3_AHCLKX_1" newline rbitfld.long 0x04 19. "CLKACTIVITY_MCASP2_AUX_GFCLK,This field indicates the state of the ADC_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP2_AUX_GFCLK_0,CLKACTIVITY_MCASP2_AUX_GFCLK_1" rbitfld.long 0x04 18. "CLKACTIVITY_MCASP2_AHCLKR,This field indicates the state of the ADC_AHCLKR clock in the domain" "CLKACTIVITY_MCASP2_AHCLKR_0,CLKACTIVITY_MCASP2_AHCLKR_1" newline rbitfld.long 0x04 17. "CLKACTIVITY_MCASP2_AHCLKX,This field indicates the state of the ADC_AHCLKX clock in the domain" "CLKACTIVITY_MCASP2_AHCLKX_0,CLKACTIVITY_MCASP2_AHCLKX_1" rbitfld.long 0x04 16. "CLKACTIVITY_L4PER2_L3_GICLK,This field indicates the state of the L4PER2_L3_GICLK clock in the domain" "CLKACTIVITY_L4PER2_L3_GICLK_0,CLKACTIVITY_L4PER2_L3_GICLK_1" newline rbitfld.long 0x04 15. "CLKACTIVITY_DCAN2_SYS_CLK,This field indicates the state of the MCAN_CLK clock in the domain" "CLKACTIVITY_DCAN2_SYS_CLK_0,CLKACTIVITY_DCAN2_SYS_CLK_1" rbitfld.long 0x04 14. "CLKACTIVITY_ICSS_IEP_CLK,This field indicates the state of the ICSS_IEP_CLK clock in the domain" "CLKACTIVITY_ICSS_IEP_CLK_0,CLKACTIVITY_ICSS_IEP_CLK_1" newline rbitfld.long 0x04 13. "CLKACTIVITY_PER_192M_GFCLK,This field indicates the state of the PER_192M_GFCLK clock in the domain" "CLKACTIVITY_PER_192M_GFCLK_0,CLKACTIVITY_PER_192M_GFCLK_1" rbitfld.long 0x04 12. "CLKACTIVITY_QSPI_GFCLK,This field indicates the state of the QSPI_GFCLK clock in the domain" "CLKACTIVITY_QSPI_GFCLK_0,CLKACTIVITY_QSPI_GFCLK_1" newline rbitfld.long 0x04 11. "CLKACTIVITY_UART9_GFCLK,This field indicates the state of the UART9_GFCLK clock in the domain" "CLKACTIVITY_UART9_GFCLK_0,CLKACTIVITY_UART9_GFCLK_1" rbitfld.long 0x04 10. "CLKACTIVITY_UART8_GFCLK,This field indicates the state of the UART8_GFCLK clock in the domain" "CLKACTIVITY_UART8_GFCLK_0,CLKACTIVITY_UART8_GFCLK_1" newline rbitfld.long 0x04 9. "CLKACTIVITY_UART7_GFCLK,This field indicates the state of the UART7_GFCLK clock in the domain" "CLKACTIVITY_UART7_GFCLK_0,CLKACTIVITY_UART7_GFCLK_1" rbitfld.long 0x04 8. "CLKACTIVITY_ICSS_CLK,This field indicates the state of the ICSS_CLK clock in the domain" "CLKACTIVITY_ICSS_CLK_0,CLKACTIVITY_ICSS_CLK_1" newline rbitfld.long 0x04 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4PER clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x08 "CM_L4PER2_DYNAMICDEP,This register controls the dynamic domain depedencies from L4PER2 domain towards 'target' domains" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x08 23. "RESERVED," "0,1" rbitfld.long 0x08 22. "GMAC_DYNDEP,Dynamic dependency towards GMAC clock domain" "?,GMAC_DYNDEP_1" newline hexmask.long.word 0x08 13.--21. 1. "RESERVED," rbitfld.long 0x08 12. "L4CFG_DYNDEP,Dynamic dependency towards L4CFG clock domain" "?,L4CFG_DYNDEP_1" newline rbitfld.long 0x08 8.--11. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x08 7. "L3INIT_DYNDEP,Dynamic dependency towards L3INIT clock domain" "?,L3INIT_DYNDEP_1" newline rbitfld.long 0x08 6. "CRC_DYNDEP,Dynamic dependency towards CRC clock domain" "?,CRC_DYNDEP_1" rbitfld.long 0x08 4.--5. "RESERVED," "0,1,2,3" newline rbitfld.long 0x08 3. "IPU_DYNDEP,Dynamic dependency towards IPU clock domain" "?,IPU_DYNDEP_1" rbitfld.long 0x08 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" line.long 0x0C "CM_L4PER2_MCASP6_CLKCTRL,This register manages the MCASP2 clocks (SR2.0)" rbitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 24.--27. "CLKSEL_AHCLKR,Selects reference clock for AHCLKR (SR2.0)" "CLKSEL_AHCLKR_0,CLKSEL_AHCLKR_1,CLKSEL_AHCLKR_2,CLKSEL_AHCLKR_3,CLKSEL_AHCLKR_4,CLKSEL_AHCLKR_5,CLKSEL_AHCLKR_6,CLKSEL_AHCLKR_7,CLKSEL_AHCLKR_8,CLKSEL_AHCLKR_9,CLKSEL_AHCLKR_10,CLKSEL_AHCLKR_11,CLKSEL_AHCLKR_12,CLKSEL_AHCLKR_13,CLKSEL_AHCLKR_14,CLKSEL_AHCLKR_15" newline bitfld.long 0x0C 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x0C 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x0C 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x0C 2.--15. 1. "RESERVED," newline rbitfld.long 0x0C 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x10 "CM_L4PER2_MCASP7_CLKCTRL,This register manages the MCASP3 clocks (SR2.0)" rbitfld.long 0x10 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. "CLKSEL_AHCLKR,Selects reference clock for AHCLKR (SR2.0)" "CLKSEL_AHCLKR_0,CLKSEL_AHCLKR_1,CLKSEL_AHCLKR_2,CLKSEL_AHCLKR_3,CLKSEL_AHCLKR_4,CLKSEL_AHCLKR_5,CLKSEL_AHCLKR_6,CLKSEL_AHCLKR_7,CLKSEL_AHCLKR_8,CLKSEL_AHCLKR_9,CLKSEL_AHCLKR_10,CLKSEL_AHCLKR_11,CLKSEL_AHCLKR_12,CLKSEL_AHCLKR_13,CLKSEL_AHCLKR_14,CLKSEL_AHCLKR_15" newline bitfld.long 0x10 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x10 18.--21. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x10 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x10 2.--15. 1. "RESERVED," newline rbitfld.long 0x10 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x14 "CM_L4PER2_STATICDEP,This register controls the static domain depedencies from L4PER2 domain towards 'target' domains" hexmask.long.byte 0x14 24.--31. 1. "RESERVED," bitfld.long 0x14 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline rbitfld.long 0x14 19.--22. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline hexmask.long.word 0x14 6.--17. 1. "RESERVED," rbitfld.long 0x14 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain" "?,L3MAIN1_STATDEP_1" newline rbitfld.long 0x14 2.--4. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x14 1. "DSP1_STATDEP,Static dependency towards DSP1 clock domain" "DSP1_STATDEP_0,DSP1_STATDEP_1" newline bitfld.long 0x14 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x18 "CM_L4PER3_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x18 13.--31. 1. "RESERVED," rbitfld.long 0x18 12. "CLKACTIVITY_TIMER16_GFCLK,This field indicates the state of the DMT16_GFCLK clock in the domain" "CLKACTIVITY_TIMER16_GFCLK_0,CLKACTIVITY_TIMER16_GFCLK_1" newline rbitfld.long 0x18 11. "CLKACTIVITY_TIMER15_GFCLK,This field indicates the state of the DMT15_GFCLK clock in the domain" "CLKACTIVITY_TIMER15_GFCLK_0,CLKACTIVITY_TIMER15_GFCLK_1" rbitfld.long 0x18 10. "CLKACTIVITY_TIMER14_GFCLK,This field indicates the state of the DMT14_GFCLK clock in the domain" "CLKACTIVITY_TIMER14_GFCLK_0,CLKACTIVITY_TIMER14_GFCLK_1" newline rbitfld.long 0x18 9. "CLKACTIVITY_TIMER13_GFCLK,This field indicates the state of the DMT13_GFCLK clock in the domain" "CLKACTIVITY_TIMER13_GFCLK_0,CLKACTIVITY_TIMER13_GFCLK_1" rbitfld.long 0x18 8. "CLKACTIVITY_L4PER3_L3_GICLK,This field indicates the state of the L4PER2_L3_GICLK clock in the domain" "CLKACTIVITY_L4PER3_L3_GICLK_0,CLKACTIVITY_L4PER3_L3_GICLK_1" newline rbitfld.long 0x18 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4PER clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x1C "CM_L4PER3_DYNAMICDEP,This register controls the dynamic domain depedencies from L4PER3 domain towards 'target' domains" rbitfld.long 0x1C 31. "ISS_DYNDEP,Dynamic dependency towards ISS clock domain" "?,ISS_DYNDEP_1" rbitfld.long 0x1C 28.--30. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x1C 23. "RTC_DYNDEP,Dynamic dependency towards RTC clock domain" "?,RTC_DYNDEP_1" newline hexmask.long.word 0x1C 13.--22. 1. "RESERVED," rbitfld.long 0x1C 12. "L4CFG_DYNDEP,Dynamic dependency towards L4CFG clock domain" "?,L4CFG_DYNDEP_1" newline rbitfld.long 0x1C 10.--11. "RESERVED," "0,1,2,3" rbitfld.long 0x1C 9. "CAM_DYNDEP,Dynamic dependency towards CAM clock domain" "?,CAM_DYNDEP_1" newline rbitfld.long 0x1C 8. "RESERVED," "0,1" rbitfld.long 0x1C 7. "L3INIT_DYNDEP,Dynamic dependency towards L3INIT clock domain" "?,L3INIT_DYNDEP_1" newline rbitfld.long 0x1C 6. "RESERVED," "0,1" rbitfld.long 0x1C 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x1C 4. "RESERVED," "0,1" rbitfld.long 0x1C 3. "IPU_DYNDEP,Dynamic dependency towards IPU clock domain" "?,IPU_DYNDEP_1" newline rbitfld.long 0x1C 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" width 0x0B tree.end tree "L4PER_PRM" base ad:0x4AE07400 group.long 0x00++0x07 line.long 0x00 "PM_L4PER_PWRSTCTRL,This register controls the L4PER power state to reach upon a domain sleep transition" hexmask.long.word 0x00 20.--31. 1. "RESERVED," rbitfld.long 0x00 18.--19. "NONRETAINED_BANK_ONSTATE,NONRETAINED_BANK state when domain is ON" "?,?,?,NONRETAINED_BANK_ONSTATE_3" newline rbitfld.long 0x00 16.--17. "RETAINED_BANK_ONSTATE,RETAINED_BANK state when domain is ON" "?,?,?,RETAINED_BANK_ONSTATE_3" rbitfld.long 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 9. "NONRETAINED_BANK_RETSTATE,NONRETAINED_BANK state when domain is RETENTION" "NONRETAINED_BANK_RETSTATE_0,?" rbitfld.long 0x00 8. "RETAINED_BANK_RETSTATE,RETAINED_BANK state when domain is RETENTION" "?,RETAINED_BANK_RETSTATE_1" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline rbitfld.long 0x00 3. "RESERVED," "0,1" bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION" "LOGICRETSTATE_0,LOGICRETSTATE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_L4PER_PWRSTST,This register provides a status on the current L4PER power domain state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" newline hexmask.long.word 0x04 8.--19. 1. "RESERVED," rbitfld.long 0x04 6.--7. "NONRETAINED_BANK_STATEST,NONRETAINED_BANK state status" "NONRETAINED_BANK_STATEST_0,NONRETAINED_BANK_STATEST_1,NONRETAINED_BANK_STATEST_2,NONRETAINED_BANK_STATEST_3" newline rbitfld.long 0x04 4.--5. "RETAINED_BANK_STATEST,RETAINED_BANK state status" "RETAINED_BANK_STATEST_0,RETAINED_BANK_STATEST_1,RETAINED_BANK_STATEST_2,RETAINED_BANK_STATEST_3" rbitfld.long 0x04 3. "RESERVED," "0,1" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x0C++0x03 line.long 0x00 "RM_L4PER2_L4PER2_CONTEXT,This register contains dedicated L4_PER2 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x14++0x03 line.long 0x00 "RM_L4PER3_L4PER3_CONTEXT,This register contains dedicated L4_PER3 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x1C++0x03 line.long 0x00 "RM_L4PER2_PRUSS1_CONTEXT,This register contains dedicated PRUSS0 context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_PRUSS1_BANK,Specify if memory-based context in pruss memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_PRUSS1_BANK_0,LOSTMEM_PRUSS1_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x24++0x33 line.long 0x00 "RM_L4PER2_PRUSS2_CONTEXT,This register contains dedicated PRUSS1 context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_PRUSS2_BANK,Specify if memory-based context in pruss memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_PRUSS2_BANK_0,LOSTMEM_PRUSS2_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_L4PER_DCC6_WKDEP,This register controls wakeup dependency based on DCC6 service requests" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "WKUPDEP_DCC6_EVE4,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_EVE4_0,WKUPDEP_DCC6_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_DCC6_EVE3,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_EVE3_0,WKUPDEP_DCC6_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_DCC6_EVE2,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_EVE2_0,WKUPDEP_DCC6_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_DCC6_EVE1,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_EVE1_0,WKUPDEP_DCC6_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_DCC6_DSP2,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_DSP2_0,WKUPDEP_DCC6_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_DCC6_IPU1,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_IPU1_0,WKUPDEP_DCC6_IPU1_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "WKUPDEP_DCC6_DSP1,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_DSP1_0,WKUPDEP_DCC6_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_DCC6_IPU2,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_IPU2_0,WKUPDEP_DCC6_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_DCC6_MPU,Wakeup dependency from DCC6 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC6_MPU_0,WKUPDEP_DCC6_MPU_1" line.long 0x08 "RM_L4PER_DCC6_CONTEXT,This register contains dedicated DCC6 context statuses" hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x0C "PM_L4PER_DCC7_WKDEP,This register controls wakeup dependency based on DCC7 service requests" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED," bitfld.long 0x0C 9. "WKUPDEP_DCC7_EVE4,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_EVE4_0,WKUPDEP_DCC7_EVE4_1" newline bitfld.long 0x0C 8. "WKUPDEP_DCC7_EVE3,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_EVE3_0,WKUPDEP_DCC7_EVE3_1" bitfld.long 0x0C 7. "WKUPDEP_DCC7_EVE2,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_EVE2_0,WKUPDEP_DCC7_EVE2_1" newline bitfld.long 0x0C 6. "WKUPDEP_DCC7_EVE1,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_EVE1_0,WKUPDEP_DCC7_EVE1_1" bitfld.long 0x0C 5. "WKUPDEP_DCC7_DSP2,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_DSP2_0,WKUPDEP_DCC7_DSP2_1" newline bitfld.long 0x0C 4. "WKUPDEP_DCC7_IPU1,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_IPU1_0,WKUPDEP_DCC7_IPU1_1" rbitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "WKUPDEP_DCC7_DSP1,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_DSP1_0,WKUPDEP_DCC7_DSP1_1" bitfld.long 0x0C 1. "WKUPDEP_DCC7_IPU2,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_IPU2_0,WKUPDEP_DCC7_IPU2_1" newline bitfld.long 0x0C 0. "WKUPDEP_DCC7_MPU,Wakeup dependency from DCC7 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC7_MPU_0,WKUPDEP_DCC7_MPU_1" line.long 0x10 "RM_L4PER_DCC7_CONTEXT,This register contains dedicated DCC7 context statuses" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x14 "PM_L4PER_TIMER2_WKDEP,This register controls wakeup dependency based on TIMER2 service requests" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," bitfld.long 0x14 9. "WKUPDEP_TIMER2_EVE4,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_EVE4_0,WKUPDEP_TIMER2_EVE4_1" newline bitfld.long 0x14 8. "WKUPDEP_TIMER2_EVE3,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_EVE3_0,WKUPDEP_TIMER2_EVE3_1" bitfld.long 0x14 7. "WKUPDEP_TIMER2_EVE2,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_EVE2_0,WKUPDEP_TIMER2_EVE2_1" newline bitfld.long 0x14 6. "WKUPDEP_TIMER2_EVE1,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_EVE1_0,WKUPDEP_TIMER2_EVE1_1" bitfld.long 0x14 5. "WKUPDEP_TIMER2_DSP2,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_DSP2_0,WKUPDEP_TIMER2_DSP2_1" newline bitfld.long 0x14 4. "WKUPDEP_TIMER2_IPU1,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_IPU1_0,WKUPDEP_TIMER2_IPU1_1" rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 2. "WKUPDEP_TIMER2_DSP1,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_DSP1_0,WKUPDEP_TIMER2_DSP1_1" bitfld.long 0x14 1. "WKUPDEP_TIMER2_IPU2,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_IPU2_0,WKUPDEP_TIMER2_IPU2_1" newline bitfld.long 0x14 0. "WKUPDEP_TIMER2_MPU,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_MPU_0,WKUPDEP_TIMER2_MPU_1" line.long 0x18 "RM_L4PER_TIMER2_CONTEXT,This register contains dedicated TIMER2 context statuses" hexmask.long 0x18 1.--31. 1. "RESERVED," bitfld.long 0x18 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x1C "PM_L4PER_TIMER3_WKDEP,This register controls wakeup dependency based on TIMER3 service requests" hexmask.long.tbyte 0x1C 10.--31. 1. "RESERVED," bitfld.long 0x1C 9. "WKUPDEP_TIMER3_EVE4,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_EVE4_0,WKUPDEP_TIMER3_EVE4_1" newline bitfld.long 0x1C 8. "WKUPDEP_TIMER3_EVE3,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_EVE3_0,WKUPDEP_TIMER3_EVE3_1" bitfld.long 0x1C 7. "WKUPDEP_TIMER3_EVE2,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_EVE2_0,WKUPDEP_TIMER3_EVE2_1" newline bitfld.long 0x1C 6. "WKUPDEP_TIMER3_EVE1,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_EVE1_0,WKUPDEP_TIMER3_EVE1_1" bitfld.long 0x1C 5. "WKUPDEP_TIMER3_DSP2,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_DSP2_0,WKUPDEP_TIMER3_DSP2_1" newline bitfld.long 0x1C 4. "WKUPDEP_TIMER3_IPU1,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_IPU1_0,WKUPDEP_TIMER3_IPU1_1" rbitfld.long 0x1C 3. "RESERVED," "0,1" newline bitfld.long 0x1C 2. "WKUPDEP_TIMER3_DSP1,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_DSP1_0,WKUPDEP_TIMER3_DSP1_1" bitfld.long 0x1C 1. "WKUPDEP_TIMER3_IPU2,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_IPU2_0,WKUPDEP_TIMER3_IPU2_1" newline bitfld.long 0x1C 0. "WKUPDEP_TIMER3_MPU,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_MPU_0,WKUPDEP_TIMER3_MPU_1" line.long 0x20 "RM_L4PER_TIMER3_CONTEXT,This register contains dedicated TIMER3 context statuses" hexmask.long 0x20 1.--31. 1. "RESERVED," bitfld.long 0x20 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x24 "PM_L4PER_TIMER4_WKDEP,This register controls wakeup dependency based on TIMER4 service requests" hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED," bitfld.long 0x24 9. "WKUPDEP_TIMER4_EVE4,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_EVE4_0,WKUPDEP_TIMER4_EVE4_1" newline bitfld.long 0x24 8. "WKUPDEP_TIMER4_EVE3,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_EVE3_0,WKUPDEP_TIMER4_EVE3_1" bitfld.long 0x24 7. "WKUPDEP_TIMER4_EVE2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_EVE2_0,WKUPDEP_TIMER4_EVE2_1" newline bitfld.long 0x24 6. "WKUPDEP_TIMER4_EVE1,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_EVE1_0,WKUPDEP_TIMER4_EVE1_1" bitfld.long 0x24 5. "WKUPDEP_TIMER4_DSP2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_DSP2_0,WKUPDEP_TIMER4_DSP2_1" newline bitfld.long 0x24 4. "WKUPDEP_TIMER4_IPU1,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_IPU1_0,WKUPDEP_TIMER4_IPU1_1" rbitfld.long 0x24 3. "RESERVED," "0,1" newline bitfld.long 0x24 2. "WKUPDEP_TIMER4_DSP1,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_DSP1_0,WKUPDEP_TIMER4_DSP1_1" bitfld.long 0x24 1. "WKUPDEP_TIMER4_IPU2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_IPU2_0,WKUPDEP_TIMER4_IPU2_1" newline bitfld.long 0x24 0. "WKUPDEP_TIMER4_MPU,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_MPU_0,WKUPDEP_TIMER4_MPU_1" line.long 0x28 "RM_L4PER_TIMER4_CONTEXT,This register contains dedicated TIMER4 context statuses" hexmask.long 0x28 1.--31. 1. "RESERVED," bitfld.long 0x28 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x2C "PM_L4PER_DCC5_WKDEP,This register controls wakeup dependency based on DCC5 service requests" hexmask.long.tbyte 0x2C 10.--31. 1. "RESERVED," bitfld.long 0x2C 9. "WKUPDEP_DCC5_EVE4,Wakeup dependency from DCC5 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_EVE4_0,WKUPDEP_DCC5_EVE4_1" newline bitfld.long 0x2C 8. "WKUPDEP_DCC5_EVE3,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_EVE3_0,WKUPDEP_DCC5_EVE3_1" bitfld.long 0x2C 7. "WKUPDEP_DCC5_EVE2,Wakeup dependency from DCC5 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_EVE2_0,WKUPDEP_DCC5_EVE2_1" newline bitfld.long 0x2C 6. "WKUPDEP_DCC5_EVE1,Wakeup dependency from DCC5 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_EVE1_0,WKUPDEP_DCC5_EVE1_1" bitfld.long 0x2C 5. "WKUPDEP_DCC5_DSP2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_DSP2_0,WKUPDEP_DCC5_DSP2_1" newline bitfld.long 0x2C 4. "WKUPDEP_DCC5_IPU1,Wakeup dependency from DCC5 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_IPU1_0,WKUPDEP_DCC5_IPU1_1" rbitfld.long 0x2C 3. "RESERVED," "0,1" newline bitfld.long 0x2C 2. "WKUPDEP_DCC5_DSP1,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_DSP1_0,WKUPDEP_DCC5_DSP1_1" bitfld.long 0x2C 1. "WKUPDEP_DCC5_IPU2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_IPU2_0,WKUPDEP_DCC5_IPU2_1" newline bitfld.long 0x2C 0. "WKUPDEP_DCC5_MPU,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC5_MPU_0,WKUPDEP_DCC5_MPU_1" line.long 0x30 "RM_L4PER_DCC5_CONTEXT,This register contains dedicated DCC5 context statuses" hexmask.long 0x30 1.--31. 1. "RESERVED," bitfld.long 0x30 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x5C++0x2B line.long 0x00 "RM_L4PER_ELM_CONTEXT,This register contains dedicated ELM context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_L4PER_GPIO2_WKDEP,This register controls wakeup dependency based on GPIO2 service requests" hexmask.long.word 0x04 20.--31. 1. "RESERVED," bitfld.long 0x04 19. "WKUPDEP_GPIO2_IRQ2_EVE4,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_EVE4_0,WKUPDEP_GPIO2_IRQ2_EVE4_1" newline bitfld.long 0x04 18. "WKUPDEP_GPIO2_IRQ2_EVE3,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_EVE3_0,WKUPDEP_GPIO2_IRQ2_EVE3_1" bitfld.long 0x04 17. "WKUPDEP_GPIO2_IRQ2_EVE2,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_EVE2_0,WKUPDEP_GPIO2_IRQ2_EVE2_1" newline bitfld.long 0x04 16. "WKUPDEP_GPIO2_IRQ2_EVE1,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_EVE1_0,WKUPDEP_GPIO2_IRQ2_EVE1_1" bitfld.long 0x04 15. "WKUPDEP_GPIO2_IRQ2_DSP2,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_DSP2_0,WKUPDEP_GPIO2_IRQ2_DSP2_1" newline bitfld.long 0x04 14. "WKUPDEP_GPIO2_IRQ2_IPU1,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_IPU1_0,WKUPDEP_GPIO2_IRQ2_IPU1_1" rbitfld.long 0x04 13. "RESERVED," "0,1" newline bitfld.long 0x04 12. "WKUPDEP_GPIO2_IRQ2_DSP1,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_DSP1_0,WKUPDEP_GPIO2_IRQ2_DSP1_1" bitfld.long 0x04 11. "WKUPDEP_GPIO2_IRQ2_IPU2,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_IPU2_0,WKUPDEP_GPIO2_IRQ2_IPU2_1" newline bitfld.long 0x04 10. "WKUPDEP_GPIO2_IRQ2_MPU,Wakeup dependency from GPIO2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_MPU_0,WKUPDEP_GPIO2_IRQ2_MPU_1" bitfld.long 0x04 9. "WKUPDEP_GPIO2_IRQ1_EVE4,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_EVE4_0,WKUPDEP_GPIO2_IRQ1_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_GPIO2_IRQ1_EVE3,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_EVE3_0,WKUPDEP_GPIO2_IRQ1_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_GPIO2_IRQ1_EVE2,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_EVE2_0,WKUPDEP_GPIO2_IRQ1_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_GPIO2_IRQ1_EVE1,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_EVE1_0,WKUPDEP_GPIO2_IRQ1_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_GPIO2_IRQ1_DSP2,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_DSP2_0,WKUPDEP_GPIO2_IRQ1_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_GPIO2_IRQ1_IPU1,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_IPU1_0,WKUPDEP_GPIO2_IRQ1_IPU1_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "WKUPDEP_GPIO2_IRQ1_DSP1,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_DSP1_0,WKUPDEP_GPIO2_IRQ1_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_GPIO2_IRQ1_IPU2,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_IPU2_0,WKUPDEP_GPIO2_IRQ1_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_GPIO2_IRQ1_MPU,Wakeup dependency from GPIO2 module (SWakeup signal for POROCPSINTERRUPT1 ) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_MPU_0,WKUPDEP_GPIO2_IRQ1_MPU_1" line.long 0x08 "RM_L4PER_GPIO2_CONTEXT,This register contains dedicated GPIO2 context statuses" hexmask.long 0x08 2.--31. 1. "RESERVED," bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x08 0. "RESERVED," "0,1" line.long 0x0C "PM_L4PER_GPIO3_WKDEP,This register controls wakeup dependency based on GPIO3 service requests" hexmask.long.word 0x0C 20.--31. 1. "RESERVED," bitfld.long 0x0C 19. "WKUPDEP_GPIO3_IRQ2_EVE4,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_EVE4_0,WKUPDEP_GPIO3_IRQ2_EVE4_1" newline bitfld.long 0x0C 18. "WKUPDEP_GPIO3_IRQ2_EVE3,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_EVE3_0,WKUPDEP_GPIO3_IRQ2_EVE3_1" bitfld.long 0x0C 17. "WKUPDEP_GPIO3_IRQ2_EVE2,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_EVE2_0,WKUPDEP_GPIO3_IRQ2_EVE2_1" newline bitfld.long 0x0C 16. "WKUPDEP_GPIO3_IRQ2_EVE1,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_EVE1_0,WKUPDEP_GPIO3_IRQ2_EVE1_1" bitfld.long 0x0C 15. "WKUPDEP_GPIO3_IRQ2_DSP2,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_DSP2_0,WKUPDEP_GPIO3_IRQ2_DSP2_1" newline bitfld.long 0x0C 14. "WKUPDEP_GPIO3_IRQ2_IPU1,Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_IPU1_0,WKUPDEP_GPIO3_IRQ2_IPU1_1" rbitfld.long 0x0C 13. "RESERVED," "0,1" newline bitfld.long 0x0C 12. "WKUPDEP_GPIO3_IRQ2_DSP1,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_DSP1_0,WKUPDEP_GPIO3_IRQ2_DSP1_1" bitfld.long 0x0C 11. "WKUPDEP_GPIO3_IRQ2_IPU2,Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_IPU2_0,WKUPDEP_GPIO3_IRQ2_IPU2_1" newline bitfld.long 0x0C 10. "WKUPDEP_GPIO3_IRQ2_MPU,Wakeup dependency from GPIO3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_MPU_0,WKUPDEP_GPIO3_IRQ2_MPU_1" bitfld.long 0x0C 9. "WKUPDEP_GPIO3_IRQ1_EVE4,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_EVE4_0,WKUPDEP_GPIO3_IRQ1_EVE4_1" newline bitfld.long 0x0C 8. "WKUPDEP_GPIO3_IRQ1_EVE3,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_EVE3_0,WKUPDEP_GPIO3_IRQ1_EVE3_1" bitfld.long 0x0C 7. "WKUPDEP_GPIO3_IRQ1_EVE2,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_EVE2_0,WKUPDEP_GPIO3_IRQ1_EVE2_1" newline bitfld.long 0x0C 6. "WKUPDEP_GPIO3_IRQ1_EVE1,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_EVE1_0,WKUPDEP_GPIO3_IRQ1_EVE1_1" bitfld.long 0x0C 5. "WKUPDEP_GPIO3_IRQ1_DSP2,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_DSP2_0,WKUPDEP_GPIO3_IRQ1_DSP2_1" newline bitfld.long 0x0C 4. "WKUPDEP_GPIO3_IRQ1_IPU1,Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_IPU1_0,WKUPDEP_GPIO3_IRQ1_IPU1_1" rbitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "WKUPDEP_GPIO3_IRQ1_DSP1,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_DSP1_0,WKUPDEP_GPIO3_IRQ1_DSP1_1" bitfld.long 0x0C 1. "WKUPDEP_GPIO3_IRQ1_IPU2,3Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_IPU2_0,WKUPDEP_GPIO3_IRQ1_IPU2_1" newline bitfld.long 0x0C 0. "WKUPDEP_GPIO3_IRQ1_MPU,Wakeup dependency from GPIO3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_MPU_0,WKUPDEP_GPIO3_IRQ1_MPU_1" line.long 0x10 "RM_L4PER_GPIO3_CONTEXT,This register contains dedicated GPIO3 context statuses" hexmask.long 0x10 2.--31. 1. "RESERVED," bitfld.long 0x10 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x10 0. "RESERVED," "0,1" line.long 0x14 "PM_L4PER_GPIO4_WKDEP,This register controls wakeup dependency based on GPIO4 service requests" hexmask.long.word 0x14 20.--31. 1. "RESERVED," bitfld.long 0x14 19. "WKUPDEP_GPIO4_IRQ2_EVE4,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_EVE4_0,WKUPDEP_GPIO4_IRQ2_EVE4_1" newline bitfld.long 0x14 18. "WKUPDEP_GPIO4_IRQ2_EVE3,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_EVE3_0,WKUPDEP_GPIO4_IRQ2_EVE3_1" bitfld.long 0x14 17. "WKUPDEP_GPIO4_IRQ2_EVE2,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_EVE2_0,WKUPDEP_GPIO4_IRQ2_EVE2_1" newline bitfld.long 0x14 16. "WKUPDEP_GPIO4_IRQ2_EVE1,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_EVE1_0,WKUPDEP_GPIO4_IRQ2_EVE1_1" bitfld.long 0x14 15. "WKUPDEP_GPIO4_IRQ2_DSP2,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_DSP2_0,WKUPDEP_GPIO4_IRQ2_DSP2_1" newline bitfld.long 0x14 14. "WKUPDEP_GPIO4_IRQ2_IPU1,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_IPU1_0,WKUPDEP_GPIO4_IRQ2_IPU1_1" rbitfld.long 0x14 13. "RESERVED," "0,1" newline bitfld.long 0x14 12. "WKUPDEP_GPIO4_IRQ2_DSP1,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_DSP1_0,WKUPDEP_GPIO4_IRQ2_DSP1_1" bitfld.long 0x14 11. "WKUPDEP_GPIO4_IRQ2_IPU2,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_IPU2_0,WKUPDEP_GPIO4_IRQ2_IPU2_1" newline bitfld.long 0x14 10. "WKUPDEP_GPIO4_IRQ2_MPU,Wakeup dependency from GPIO4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_MPU_0,WKUPDEP_GPIO4_IRQ2_MPU_1" bitfld.long 0x14 9. "WKUPDEP_GPIO4_IRQ1_EVE4,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_EVE4_0,WKUPDEP_GPIO4_IRQ1_EVE4_1" newline bitfld.long 0x14 8. "WKUPDEP_GPIO4_IRQ1_EVE3,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_EVE3_0,WKUPDEP_GPIO4_IRQ1_EVE3_1" bitfld.long 0x14 7. "WKUPDEP_GPIO4_IRQ1_EVE2,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_EVE2_0,WKUPDEP_GPIO4_IRQ1_EVE2_1" newline bitfld.long 0x14 6. "WKUPDEP_GPIO4_IRQ1_EVE1,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_EVE1_0,WKUPDEP_GPIO4_IRQ1_EVE1_1" bitfld.long 0x14 5. "WKUPDEP_GPIO4_IRQ1_DSP2,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_DSP2_0,WKUPDEP_GPIO4_IRQ1_DSP2_1" newline bitfld.long 0x14 4. "WKUPDEP_GPIO4_IRQ1_IPU1,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_IPU1_0,WKUPDEP_GPIO4_IRQ1_IPU1_1" rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 2. "WKUPDEP_GPIO4_IRQ1_DSP1,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_DSP1_0,WKUPDEP_GPIO4_IRQ1_DSP1_1" bitfld.long 0x14 1. "WKUPDEP_GPIO4_IRQ1_IPU2,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_IPU2_0,WKUPDEP_GPIO4_IRQ1_IPU2_1" newline bitfld.long 0x14 0. "WKUPDEP_GPIO4_IRQ1_MPU,Wakeup dependency from GPIO4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_MPU_0,WKUPDEP_GPIO4_IRQ1_MPU_1" line.long 0x18 "RM_L4PER_GPIO4_CONTEXT,This register contains dedicated GPIO4 context statuses" hexmask.long 0x18 2.--31. 1. "RESERVED," bitfld.long 0x18 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x18 0. "RESERVED," "0,1" line.long 0x1C "PM_L4PER_GPIO5_WKDEP,This register controls wakeup dependency based on GPIO5 service requests" hexmask.long.word 0x1C 20.--31. 1. "RESERVED," bitfld.long 0x1C 19. "WKUPDEP_GPIO5_IRQ2_EVE4,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_EVE4_0,WKUPDEP_GPIO5_IRQ2_EVE4_1" newline bitfld.long 0x1C 18. "WKUPDEP_GPIO5_IRQ2_EVE3,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_EVE3_0,WKUPDEP_GPIO5_IRQ2_EVE3_1" bitfld.long 0x1C 17. "WKUPDEP_GPIO5_IRQ2_EVE2,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_EVE2_0,WKUPDEP_GPIO5_IRQ2_EVE2_1" newline bitfld.long 0x1C 16. "WKUPDEP_GPIO5_IRQ2_EVE1,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_EVE1_0,WKUPDEP_GPIO5_IRQ2_EVE1_1" bitfld.long 0x1C 15. "WKUPDEP_GPIO5_IRQ2_DSP2,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_DSP2_0,WKUPDEP_GPIO5_IRQ2_DSP2_1" newline bitfld.long 0x1C 14. "WKUPDEP_GPIO5_IRQ2_IPU1,Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_IPU1_0,WKUPDEP_GPIO5_IRQ2_IPU1_1" rbitfld.long 0x1C 13. "RESERVED," "0,1" newline bitfld.long 0x1C 12. "WKUPDEP_GPIO5_IRQ2_DSP1,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_DSP1_0,WKUPDEP_GPIO5_IRQ2_DSP1_1" bitfld.long 0x1C 11. "WKUPDEP_GPIO5_IRQ2_IPU2,Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_IPU2_0,WKUPDEP_GPIO5_IRQ2_IPU2_1" newline bitfld.long 0x1C 10. "WKUPDEP_GPIO5_IRQ2_MPU,Wakeup dependency from GPIO5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_MPU_0,WKUPDEP_GPIO5_IRQ2_MPU_1" bitfld.long 0x1C 9. "WKUPDEP_GPIO5_IRQ1_EVE4,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_EVE4_0,WKUPDEP_GPIO5_IRQ1_EVE4_1" newline bitfld.long 0x1C 8. "WKUPDEP_GPIO5_IRQ1_EVE3,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_EVE3_0,WKUPDEP_GPIO5_IRQ1_EVE3_1" bitfld.long 0x1C 7. "WKUPDEP_GPIO5_IRQ1_EVE2,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_EVE2_0,WKUPDEP_GPIO5_IRQ1_EVE2_1" newline bitfld.long 0x1C 6. "WKUPDEP_GPIO5_IRQ1_EVE1,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_EVE1_0,WKUPDEP_GPIO5_IRQ1_EVE1_1" bitfld.long 0x1C 5. "WKUPDEP_GPIO5_IRQ1_DSP2,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_DSP2_0,WKUPDEP_GPIO5_IRQ1_DSP2_1" newline bitfld.long 0x1C 4. "WKUPDEP_GPIO5_IRQ1_IPU1,Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_IPU1_0,WKUPDEP_GPIO5_IRQ1_IPU1_1" rbitfld.long 0x1C 3. "RESERVED," "0,1" newline bitfld.long 0x1C 2. "WKUPDEP_GPIO5_IRQ1_DSP1,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_DSP1_0,WKUPDEP_GPIO5_IRQ1_DSP1_1" bitfld.long 0x1C 1. "WKUPDEP_GPIO5_IRQ1_IPU2,5Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_IPU2_0,WKUPDEP_GPIO5_IRQ1_IPU2_1" newline bitfld.long 0x1C 0. "WKUPDEP_GPIO5_IRQ1_MPU,Wakeup dependency from GPIO5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_MPU_0,WKUPDEP_GPIO5_IRQ1_MPU_1" line.long 0x20 "RM_L4PER_GPIO5_CONTEXT,This register contains dedicated GPIO5 context statuses" hexmask.long 0x20 2.--31. 1. "RESERVED," bitfld.long 0x20 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x20 0. "RESERVED," "0,1" line.long 0x24 "PM_L4PER_GPIO6_WKDEP,This register controls wakeup dependency based on GPIO6 service requests" hexmask.long.word 0x24 20.--31. 1. "RESERVED," bitfld.long 0x24 19. "WKUPDEP_GPIO6_IRQ2_EVE4,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_EVE4_0,WKUPDEP_GPIO6_IRQ2_EVE4_1" newline bitfld.long 0x24 18. "WKUPDEP_GPIO6_IRQ2_EVE3,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_EVE3_0,WKUPDEP_GPIO6_IRQ2_EVE3_1" bitfld.long 0x24 17. "WKUPDEP_GPIO6_IRQ2_EVE2,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_EVE2_0,WKUPDEP_GPIO6_IRQ2_EVE2_1" newline bitfld.long 0x24 16. "WKUPDEP_GPIO6_IRQ2_EVE1,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_EVE1_0,WKUPDEP_GPIO6_IRQ2_EVE1_1" bitfld.long 0x24 15. "WKUPDEP_GPIO6_IRQ2_DSP2,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_DSP2_0,WKUPDEP_GPIO6_IRQ2_DSP2_1" newline bitfld.long 0x24 14. "WKUPDEP_GPIO6_IRQ2_IPU1,Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_IPU1_0,WKUPDEP_GPIO6_IRQ2_IPU1_1" rbitfld.long 0x24 13. "RESERVED," "0,1" newline bitfld.long 0x24 12. "WKUPDEP_GPIO6_IRQ2_DSP1,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_DSP1_0,WKUPDEP_GPIO6_IRQ2_DSP1_1" bitfld.long 0x24 11. "WKUPDEP_GPIO6_IRQ2_IPU2,Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_IPU2_0,WKUPDEP_GPIO6_IRQ2_IPU2_1" newline bitfld.long 0x24 10. "WKUPDEP_GPIO6_IRQ2_MPU,Wakeup dependency from GPIO6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_MPU_0,WKUPDEP_GPIO6_IRQ2_MPU_1" bitfld.long 0x24 9. "WKUPDEP_GPIO6_IRQ1_EVE4,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_EVE4_0,WKUPDEP_GPIO6_IRQ1_EVE4_1" newline bitfld.long 0x24 8. "WKUPDEP_GPIO6_IRQ1_EVE3,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_EVE3_0,WKUPDEP_GPIO6_IRQ1_EVE3_1" bitfld.long 0x24 7. "WKUPDEP_GPIO6_IRQ1_EVE2,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_EVE2_0,WKUPDEP_GPIO6_IRQ1_EVE2_1" newline bitfld.long 0x24 6. "WKUPDEP_GPIO6_IRQ1_EVE1,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_EVE1_0,WKUPDEP_GPIO6_IRQ1_EVE1_1" bitfld.long 0x24 5. "WKUPDEP_GPIO6_IRQ1_DSP2,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_DSP2_0,WKUPDEP_GPIO6_IRQ1_DSP2_1" newline bitfld.long 0x24 4. "WKUPDEP_GPIO6_IRQ1_IPU1,Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_IPU1_0,WKUPDEP_GPIO6_IRQ1_IPU1_1" rbitfld.long 0x24 3. "RESERVED," "0,1" newline bitfld.long 0x24 2. "WKUPDEP_GPIO6_IRQ1_DSP1,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_DSP1_0,WKUPDEP_GPIO6_IRQ1_DSP1_1" bitfld.long 0x24 1. "WKUPDEP_GPIO6_IRQ1_IPU2,5Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_IPU2_0,WKUPDEP_GPIO6_IRQ1_IPU2_1" newline bitfld.long 0x24 0. "WKUPDEP_GPIO6_IRQ1_MPU,Wakeup dependency from GPIO6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_MPU_0,WKUPDEP_GPIO6_IRQ1_MPU_1" line.long 0x28 "RM_L4PER_GPIO6_CONTEXT,This register contains dedicated GPIO6 context statuses" hexmask.long 0x28 2.--31. 1. "RESERVED," bitfld.long 0x28 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x28 0. "RESERVED," "0,1" group.long 0x8C++0x03 line.long 0x00 "RM_L4PER_ESM_CONTEXT,This register contains dedicated ESM context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x94++0x03 line.long 0x00 "RM_L4PER2_PWMSS2_CONTEXT,This register contains dedicated PWMSS2 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x9C++0x43 line.long 0x00 "RM_L4PER2_PWMSS3_CONTEXT,This register contains dedicated PWMSS3 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_L4PER_I2C1_WKDEP,This register controls wakeup dependency based on I2C1 service requests" hexmask.long.word 0x04 16.--31. 1. "RESERVED," bitfld.long 0x04 15. "WKUPDEP_I2C1_DMA_DSP2,Wakeup dependency from I2C1 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_DMA_DSP2_0,WKUPDEP_I2C1_DMA_DSP2_1" newline rbitfld.long 0x04 14. "RESERVED," "0,1" bitfld.long 0x04 13. "WKUPDEP_I2C1_DMA_SDMA,Wakeup dependency from I2C1 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_DMA_SDMA_0,WKUPDEP_I2C1_DMA_SDMA_1" newline bitfld.long 0x04 12. "WKUPDEP_I2C1_DMA_DSP1,Wakeup dependency from I2C1 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_DMA_DSP1_0,WKUPDEP_I2C1_DMA_DSP1_1" rbitfld.long 0x04 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 9. "WKUPDEP_I2C1_IRQ_EVE4,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_EVE4_0,WKUPDEP_I2C1_IRQ_EVE4_1" bitfld.long 0x04 8. "WKUPDEP_I2C1_IRQ_EVE3,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_EVE3_0,WKUPDEP_I2C1_IRQ_EVE3_1" newline bitfld.long 0x04 7. "WKUPDEP_I2C1_IRQ_EVE2,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_EVE2_0,WKUPDEP_I2C1_IRQ_EVE2_1" bitfld.long 0x04 6. "WKUPDEP_I2C1_IRQ_EVE1,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_EVE1_0,WKUPDEP_I2C1_IRQ_EVE1_1" newline bitfld.long 0x04 5. "WKUPDEP_I2C1_IRQ_DSP2,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_DSP2_0,WKUPDEP_I2C1_IRQ_DSP2_1" bitfld.long 0x04 4. "WKUPDEP_I2C1_IRQ_IPU1,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_IPU1_0,WKUPDEP_I2C1_IRQ_IPU1_1" newline rbitfld.long 0x04 3. "RESERVED," "0,1" bitfld.long 0x04 2. "WKUPDEP_I2C1_IRQ_DSP1,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_DSP1_0,WKUPDEP_I2C1_IRQ_DSP1_1" newline bitfld.long 0x04 1. "WKUPDEP_I2C1_IRQ_IPU2,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_IPU2_0,WKUPDEP_I2C1_IRQ_IPU2_1" bitfld.long 0x04 0. "WKUPDEP_I2C1_IRQ_MPU,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_MPU_0,WKUPDEP_I2C1_IRQ_MPU_1" line.long 0x08 "RM_L4PER_I2C1_CONTEXT,This register contains dedicated I2C1 context statuses" hexmask.long 0x08 2.--31. 1. "RESERVED," bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x08 0. "RESERVED," "0,1" line.long 0x0C "PM_L4PER_I2C2_WKDEP,This register controls wakeup dependency based on I2C2 service requests" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," bitfld.long 0x0C 15. "WKUPDEP_I2C2_DMA_DSP2,Wakeup dependency from I2C2 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_DMA_DSP2_0,WKUPDEP_I2C2_DMA_DSP2_1" newline rbitfld.long 0x0C 14. "RESERVED," "0,1" bitfld.long 0x0C 13. "WKUPDEP_I2C2_DMA_SDMA,Wakeup dependency from I2C2 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_DMA_SDMA_0,WKUPDEP_I2C2_DMA_SDMA_1" newline bitfld.long 0x0C 12. "WKUPDEP_I2C2_DMA_DSP1,Wakeup dependency from I2C2 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_DMA_DSP1_0,WKUPDEP_I2C2_DMA_DSP1_1" rbitfld.long 0x0C 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 9. "WKUPDEP_I2C2_IRQ_EVE4,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_EVE4_0,WKUPDEP_I2C2_IRQ_EVE4_1" bitfld.long 0x0C 8. "WKUPDEP_I2C2_IRQ_EVE3,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_EVE3_0,WKUPDEP_I2C2_IRQ_EVE3_1" newline bitfld.long 0x0C 7. "WKUPDEP_I2C2_IRQ_EVE2,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_EVE2_0,WKUPDEP_I2C2_IRQ_EVE2_1" bitfld.long 0x0C 6. "WKUPDEP_I2C2_IRQ_EVE1,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_EVE1_0,WKUPDEP_I2C2_IRQ_EVE1_1" newline bitfld.long 0x0C 5. "WKUPDEP_I2C2_IRQ_DSP2,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_DSP2_0,WKUPDEP_I2C2_IRQ_DSP2_1" bitfld.long 0x0C 4. "WKUPDEP_I2C2_IRQ_IPU1,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_IPU1_0,WKUPDEP_I2C2_IRQ_IPU1_1" newline rbitfld.long 0x0C 3. "RESERVED," "0,1" bitfld.long 0x0C 2. "WKUPDEP_I2C2_IRQ_DSP1,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_DSP1_0,WKUPDEP_I2C2_IRQ_DSP1_1" newline bitfld.long 0x0C 1. "WKUPDEP_I2C2_IRQ_IPU2,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_IPU2_0,WKUPDEP_I2C2_IRQ_IPU2_1" bitfld.long 0x0C 0. "WKUPDEP_I2C2_IRQ_MPU,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_MPU_0,WKUPDEP_I2C2_IRQ_MPU_1" line.long 0x10 "RM_L4PER_I2C2_CONTEXT,This register contains dedicated I2C2 context statuses" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x14 "PM_L4PER_I2C3_WKDEP,This register controls wakeup dependency based on I2C3 service requests" hexmask.long.word 0x14 16.--31. 1. "RESERVED," bitfld.long 0x14 15. "WKUPDEP_I2C3_DMA_DSP2,Wakeup dependency from I2C3 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_DMA_DSP2_0,WKUPDEP_I2C3_DMA_DSP2_1" newline rbitfld.long 0x14 14. "RESERVED," "0,1" bitfld.long 0x14 13. "WKUPDEP_I2C3_DMA_SDMA,Wakeup dependency from I2C3 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_DMA_SDMA_0,WKUPDEP_I2C3_DMA_SDMA_1" newline bitfld.long 0x14 12. "WKUPDEP_I2C3_DMA_DSP1,Wakeup dependency from I2C3 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_DMA_DSP1_0,WKUPDEP_I2C3_DMA_DSP1_1" rbitfld.long 0x14 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 9. "WKUPDEP_I2C3_IRQ_EVE4,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_EVE4_0,WKUPDEP_I2C3_IRQ_EVE4_1" bitfld.long 0x14 8. "WKUPDEP_I2C3_IRQ_EVE3,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_EVE3_0,WKUPDEP_I2C3_IRQ_EVE3_1" newline bitfld.long 0x14 7. "WKUPDEP_I2C3_IRQ_EVE2,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_EVE2_0,WKUPDEP_I2C3_IRQ_EVE2_1" bitfld.long 0x14 6. "WKUPDEP_I2C3_IRQ_EVE1,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_EVE1_0,WKUPDEP_I2C3_IRQ_EVE1_1" newline bitfld.long 0x14 5. "WKUPDEP_I2C3_IRQ_DSP2,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_DSP2_0,WKUPDEP_I2C3_IRQ_DSP2_1" bitfld.long 0x14 4. "WKUPDEP_I2C3_IRQ_IPU1,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_IPU1_0,WKUPDEP_I2C3_IRQ_IPU1_1" newline rbitfld.long 0x14 3. "RESERVED," "0,1" bitfld.long 0x14 2. "WKUPDEP_I2C3_IRQ_DSP1,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_DSP1_0,WKUPDEP_I2C3_IRQ_DSP1_1" newline bitfld.long 0x14 1. "WKUPDEP_I2C3_IRQ_IPU2,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_IPU2_0,WKUPDEP_I2C3_IRQ_IPU2_1" bitfld.long 0x14 0. "WKUPDEP_I2C3_IRQ_MPU,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_MPU_0,WKUPDEP_I2C3_IRQ_MPU_1" line.long 0x18 "RM_L4PER_I2C3_CONTEXT,This register contains dedicated I2C3 context statuses" hexmask.long 0x18 1.--31. 1. "RESERVED," bitfld.long 0x18 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x1C "PM_L4PER_I2C4_WKDEP,This register controls wakeup dependency based on I2C4 service requests" hexmask.long.word 0x1C 16.--31. 1. "RESERVED," bitfld.long 0x1C 15. "WKUPDEP_I2C4_DMA_DSP2,Wakeup dependency from I2C4 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_DMA_DSP2_0,WKUPDEP_I2C4_DMA_DSP2_1" newline rbitfld.long 0x1C 14. "RESERVED," "0,1" bitfld.long 0x1C 13. "WKUPDEP_I2C4_DMA_SDMA,Wakeup dependency from I2C4 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_DMA_SDMA_0,WKUPDEP_I2C4_DMA_SDMA_1" newline bitfld.long 0x1C 12. "WKUPDEP_I2C4_DMA_DSP1,Wakeup dependency from I2C4 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_DMA_DSP1_0,WKUPDEP_I2C4_DMA_DSP1_1" rbitfld.long 0x1C 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x1C 9. "WKUPDEP_I2C4_IRQ_EVE4,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_EVE4_0,WKUPDEP_I2C4_IRQ_EVE4_1" bitfld.long 0x1C 8. "WKUPDEP_I2C4_IRQ_EVE3,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_EVE3_0,WKUPDEP_I2C4_IRQ_EVE3_1" newline bitfld.long 0x1C 7. "WKUPDEP_I2C4_IRQ_EVE2,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_EVE2_0,WKUPDEP_I2C4_IRQ_EVE2_1" bitfld.long 0x1C 6. "WKUPDEP_I2C4_IRQ_EVE1,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_EVE1_0,WKUPDEP_I2C4_IRQ_EVE1_1" newline bitfld.long 0x1C 5. "WKUPDEP_I2C4_IRQ_DSP2,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_DSP2_0,WKUPDEP_I2C4_IRQ_DSP2_1" bitfld.long 0x1C 4. "WKUPDEP_I2C4_IRQ_IPU1,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_IPU1_0,WKUPDEP_I2C4_IRQ_IPU1_1" newline rbitfld.long 0x1C 3. "RESERVED," "0,1" bitfld.long 0x1C 2. "WKUPDEP_I2C4_IRQ_DSP1,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_DSP1_0,WKUPDEP_I2C4_IRQ_DSP1_1" newline bitfld.long 0x1C 1. "WKUPDEP_I2C4_IRQ_IPU2,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_IPU2_0,WKUPDEP_I2C4_IRQ_IPU2_1" bitfld.long 0x1C 0. "WKUPDEP_I2C4_IRQ_MPU,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_MPU_0,WKUPDEP_I2C4_IRQ_MPU_1" line.long 0x20 "RM_L4PER_I2C4_CONTEXT,This register contains dedicated I2C4 context statuses" hexmask.long 0x20 1.--31. 1. "RESERVED," bitfld.long 0x20 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x24 "RM_L4PER_L4PER1_CONTEXT,This register contains dedicated L4_PER1 context statuses" hexmask.long 0x24 2.--31. 1. "RESERVED," bitfld.long 0x24 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x24 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x28 "RM_L4PER2_PWMSS1_CONTEXT,This register contains dedicated PWMSS1 context statuses" hexmask.long 0x28 1.--31. 1. "RESERVED," bitfld.long 0x28 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x2C "PM_L4PER_DCC1_WKDEP,This register controls wakeup dependency based on DCC1 service requests" hexmask.long.tbyte 0x2C 10.--31. 1. "RESERVED," bitfld.long 0x2C 9. "WKUPDEP_DCC1_EVE4,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_EVE4_0,WKUPDEP_DCC1_EVE4_1" newline bitfld.long 0x2C 8. "WKUPDEP_DCC1_EVE3,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_EVE3_0,WKUPDEP_DCC1_EVE3_1" bitfld.long 0x2C 7. "WKUPDEP_DCC1_EVE2,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_EVE2_0,WKUPDEP_DCC1_EVE2_1" newline bitfld.long 0x2C 6. "WKUPDEP_DCC1_EVE1,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_EVE1_0,WKUPDEP_DCC1_EVE1_1" bitfld.long 0x2C 5. "WKUPDEP_DCC1_DSP2,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_DSP2_0,WKUPDEP_DCC1_DSP2_1" newline bitfld.long 0x2C 4. "WKUPDEP_DCC1_IPU1,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_IPU1_0,WKUPDEP_DCC1_IPU1_1" rbitfld.long 0x2C 3. "RESERVED," "0,1" newline bitfld.long 0x2C 2. "WKUPDEP_DCC1_DSP1,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_DSP1_0,WKUPDEP_DCC1_DSP1_1" bitfld.long 0x2C 1. "WKUPDEP_DCC1_IPU2,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_IPU2_0,WKUPDEP_DCC1_IPU2_1" newline bitfld.long 0x2C 0. "WKUPDEP_DCC1_MPU,Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC1_MPU_0,WKUPDEP_DCC1_MPU_1" line.long 0x30 "RM_L4PER3_DCC1_CONTEXT,This register contains dedicated DCC1 context statuses" hexmask.long 0x30 1.--31. 1. "RESERVED," bitfld.long 0x30 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x34 "PM_L4PER_DCC2_WKDEP,This register controls wakeup dependency based on DCC2 service requests" hexmask.long.tbyte 0x34 10.--31. 1. "RESERVED," bitfld.long 0x34 9. "WKUPDEP_DCC2_EVE4,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_EVE4_0,WKUPDEP_DCC2_EVE4_1" newline bitfld.long 0x34 8. "WKUPDEP_DCC2_EVE3,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_EVE3_0,WKUPDEP_DCC2_EVE3_1" bitfld.long 0x34 7. "WKUPDEP_DCC2_EVE2,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_EVE2_0,WKUPDEP_DCC2_EVE2_1" newline bitfld.long 0x34 6. "WKUPDEP_DCC2_EVE1,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_EVE1_0,WKUPDEP_DCC2_EVE1_1" bitfld.long 0x34 5. "WKUPDEP_DCC2_DSP2,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_DSP2_0,WKUPDEP_DCC2_DSP2_1" newline bitfld.long 0x34 4. "WKUPDEP_DCC2_IPU1,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_IPU1_0,WKUPDEP_DCC2_IPU1_1" rbitfld.long 0x34 3. "RESERVED," "0,1" newline bitfld.long 0x34 2. "WKUPDEP_DCC2_DSP1,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_DSP1_0,WKUPDEP_DCC2_DSP1_1" bitfld.long 0x34 1. "WKUPDEP_DCC2_IPU2,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_IPU2_0,WKUPDEP_DCC2_IPU2_1" newline bitfld.long 0x34 0. "WKUPDEP_DCC2_MPU,Wakeup dependency from DCC2 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC2_MPU_0,WKUPDEP_DCC2_MPU_1" line.long 0x38 "RM_L4PER3_DCC2_CONTEXT,This register contains dedicated DCC2 context statuses" hexmask.long 0x38 1.--31. 1. "RESERVED," bitfld.long 0x38 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x3C "PM_L4PER_DCC3_WKDEP,This register controls wakeup dependency based on DCC3 service requests" hexmask.long.tbyte 0x3C 10.--31. 1. "RESERVED," bitfld.long 0x3C 9. "WKUPDEP_DCC3_EVE4,5Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_EVE4_0,WKUPDEP_DCC3_EVE4_1" newline bitfld.long 0x3C 8. "WKUPDEP_DCC3_EVE3,Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_EVE3_0,WKUPDEP_DCC3_EVE3_1" bitfld.long 0x3C 7. "WKUPDEP_DCC3_EVE2,Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_EVE2_0,WKUPDEP_DCC3_EVE2_1" newline bitfld.long 0x3C 6. "WKUPDEP_DCC3_EVE1,Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_EVE1_0,WKUPDEP_DCC3_EVE1_1" bitfld.long 0x3C 5. "WKUPDEP_DCC3_DSP2,Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_DSP2_0,WKUPDEP_DCC3_DSP2_1" newline bitfld.long 0x3C 4. "WKUPDEP_DCC3_IPU1,Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_IPU1_0,WKUPDEP_DCC3_IPU1_1" rbitfld.long 0x3C 3. "RESERVED," "0,1" newline bitfld.long 0x3C 2. "WKUPDEP_DCC3_DSP1,Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_DSP1_0,WKUPDEP_DCC3_DSP1_1" bitfld.long 0x3C 1. "WKUPDEP_DCC3_IPU2,Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_IPU2_0,WKUPDEP_DCC3_IPU2_1" newline bitfld.long 0x3C 0. "WKUPDEP_DCC3_MPU,Wakeup dependency from DCC3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC3_MPU_0,WKUPDEP_DCC3_MPU_1" line.long 0x40 "RM_L4PER3_DCC3_CONTEXT,This register contains dedicated DCC3 context statuses" hexmask.long 0x40 1.--31. 1. "RESERVED," bitfld.long 0x40 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xF0++0xAF line.long 0x00 "PM_L4PER_MCSPI1_WKDEP,This register controls wakeup dependency based on MCSPI1 service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_MCSPI1_EVE4,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_EVE4_0,WKUPDEP_MCSPI1_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_MCSPI1_EVE3,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_EVE3_0,WKUPDEP_MCSPI1_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_MCSPI1_EVE2,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_EVE2_0,WKUPDEP_MCSPI1_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_MCSPI1_EVE1,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_EVE1_0,WKUPDEP_MCSPI1_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_MCSPI1_DSP2,Wakeup dependency from MCSPI1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_DSP2_0,WKUPDEP_MCSPI1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_MCSPI1_IPU1,Wakeup dependency from MCSPI1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_IPU1_0,WKUPDEP_MCSPI1_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_MCSPI1_SDMA,Wakeup dependency from MCSPI1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_SDMA_0,WKUPDEP_MCSPI1_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_MCSPI1_DSP1,Wakeup dependency from MCSPI1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_DSP1_0,WKUPDEP_MCSPI1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_MCSPI1_IPU2,Wakeup dependency from MCSPI1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_IPU2_0,WKUPDEP_MCSPI1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_MCSPI1_MPU,Wakeup dependency from MCSPI1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_MPU_0,WKUPDEP_MCSPI1_MPU_1" line.long 0x04 "RM_L4PER_MCSPI1_CONTEXT,This register contains dedicated MCSPI1 context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_L4PER_MCSPI2_WKDEP,This register controls wakeup dependency based on MCSPI2 service requests" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "WKUPDEP_MCSPI2_EVE4,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_EVE4_0,WKUPDEP_MCSPI2_EVE4_1" newline bitfld.long 0x08 8. "WKUPDEP_MCSPI2_EVE3,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_EVE3_0,WKUPDEP_MCSPI2_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_MCSPI2_EVE2,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_EVE2_0,WKUPDEP_MCSPI2_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_MCSPI2_EVE1,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_EVE1_0,WKUPDEP_MCSPI2_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_MCSPI2_DSP2,Wakeup dependency from MCSPI2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_DSP2_0,WKUPDEP_MCSPI2_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_MCSPI2_IPU1,Wakeup dependency from MCSPI2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_IPU1_0,WKUPDEP_MCSPI2_IPU1_1" bitfld.long 0x08 3. "WKUPDEP_MCSPI2_SDMA,Wakeup dependency from MCSPI2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_SDMA_0,WKUPDEP_MCSPI2_SDMA_1" newline bitfld.long 0x08 2. "WKUPDEP_MCSPI2_DSP1,Wakeup dependency from MCSPI2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_DSP1_0,WKUPDEP_MCSPI2_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_MCSPI2_IPU2,Wakeup dependency from MCSPI2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_IPU2_0,WKUPDEP_MCSPI2_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_MCSPI2_MPU,Wakeup dependency from MCSPI2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_MPU_0,WKUPDEP_MCSPI2_MPU_1" line.long 0x0C "RM_L4PER_MCSPI2_CONTEXT,This register contains dedicated MCSPI2 context statuses" hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_L4PER_MCSPI3_WKDEP,This register controls wakeup dependency based on MCSPI3 service requests" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED," bitfld.long 0x10 9. "WKUPDEP_MCSPI3_EVE4,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_EVE4_0,WKUPDEP_MCSPI3_EVE4_1" newline bitfld.long 0x10 8. "WKUPDEP_MCSPI3_EVE3,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_EVE3_0,WKUPDEP_MCSPI3_EVE3_1" bitfld.long 0x10 7. "WKUPDEP_MCSPI3_EVE2,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_EVE2_0,WKUPDEP_MCSPI3_EVE2_1" newline bitfld.long 0x10 6. "WKUPDEP_MCSPI3_EVE1,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_EVE1_0,WKUPDEP_MCSPI3_EVE1_1" bitfld.long 0x10 5. "WKUPDEP_MCSPI3_DSP2,Wakeup dependency from MCSPI3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_DSP2_0,WKUPDEP_MCSPI3_DSP2_1" newline bitfld.long 0x10 4. "WKUPDEP_MCSPI3_IPU1,Wakeup dependency from MCSPI3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_IPU1_0,WKUPDEP_MCSPI3_IPU1_1" bitfld.long 0x10 3. "WKUPDEP_MCSPI3_SDMA,Wakeup dependency from MCSPI3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_SDMA_0,WKUPDEP_MCSPI3_SDMA_1" newline bitfld.long 0x10 2. "WKUPDEP_MCSPI3_DSP1,Wakeup dependency from MCSPI3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_DSP1_0,WKUPDEP_MCSPI3_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_MCSPI3_IPU2,Wakeup dependency from MCSPI3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_IPU2_0,WKUPDEP_MCSPI3_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_MCSPI3_MPU,Wakeup dependency from MCSPI3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_MPU_0,WKUPDEP_MCSPI3_MPU_1" line.long 0x14 "RM_L4PER_MCSPI3_CONTEXT,This register contains dedicated MCSPI3 context statuses" hexmask.long 0x14 1.--31. 1. "RESERVED," bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x18 "PM_L4PER_MCSPI4_WKDEP,This register controls wakeup dependency based on MCSPI4 service requests" hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED," bitfld.long 0x18 9. "WKUPDEP_MCSPI4_EVE4,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_EVE4_0,WKUPDEP_MCSPI4_EVE4_1" newline bitfld.long 0x18 8. "WKUPDEP_MCSPI4_EVE3,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_EVE3_0,WKUPDEP_MCSPI4_EVE3_1" bitfld.long 0x18 7. "WKUPDEP_MCSPI4_EVE2,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_EVE2_0,WKUPDEP_MCSPI4_EVE2_1" newline bitfld.long 0x18 6. "WKUPDEP_MCSPI4_EVE1,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_EVE1_0,WKUPDEP_MCSPI4_EVE1_1" bitfld.long 0x18 5. "WKUPDEP_MCSPI4_DSP2,Wakeup dependency from MCSPI4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_DSP2_0,WKUPDEP_MCSPI4_DSP2_1" newline bitfld.long 0x18 4. "WKUPDEP_MCSPI4_IPU1,Wakeup dependency from MCSPI4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_IPU1_0,WKUPDEP_MCSPI4_IPU1_1" bitfld.long 0x18 3. "WKUPDEP_MCSPI4_SDMA,Wakeup dependency from MCSPI4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_SDMA_0,WKUPDEP_MCSPI4_SDMA_1" newline bitfld.long 0x18 2. "WKUPDEP_MCSPI4_DSP1,Wakeup dependency from MCSPI4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_DSP1_0,WKUPDEP_MCSPI4_DSP1_1" bitfld.long 0x18 1. "WKUPDEP_MCSPI4_IPU2,Wakeup dependency from MCSPI4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_IPU2_0,WKUPDEP_MCSPI4_IPU2_1" newline bitfld.long 0x18 0. "WKUPDEP_MCSPI4_MPU,Wakeup dependency from MCSPI4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_MPU_0,WKUPDEP_MCSPI4_MPU_1" line.long 0x1C "RM_L4PER_MCSPI4_CONTEXT,This register contains dedicated MCSPI4 context statuses" hexmask.long 0x1C 1.--31. 1. "RESERVED," bitfld.long 0x1C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x20 "PM_L4PER_GPIO7_WKDEP,This register controls wakeup dependency based on GPIO7 service requests" hexmask.long.word 0x20 20.--31. 1. "RESERVED," bitfld.long 0x20 19. "WKUPDEP_GPIO7_IRQ2_EVE4,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_EVE4_0,WKUPDEP_GPIO7_IRQ2_EVE4_1" newline bitfld.long 0x20 18. "WKUPDEP_GPIO7_IRQ2_EVE3,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_EVE3_0,WKUPDEP_GPIO7_IRQ2_EVE3_1" bitfld.long 0x20 17. "WKUPDEP_GPIO7_IRQ2_EVE2,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_EVE2_0,WKUPDEP_GPIO7_IRQ2_EVE2_1" newline bitfld.long 0x20 16. "WKUPDEP_GPIO7_IRQ2_EVE1,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_EVE1_0,WKUPDEP_GPIO7_IRQ2_EVE1_1" bitfld.long 0x20 15. "WKUPDEP_GPIO7_IRQ2_DSP2,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_DSP2_0,WKUPDEP_GPIO7_IRQ2_DSP2_1" newline bitfld.long 0x20 14. "WKUPDEP_GPIO7_IRQ2_IPU1,Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_IPU1_0,WKUPDEP_GPIO7_IRQ2_IPU1_1" rbitfld.long 0x20 13. "RESERVED," "0,1" newline bitfld.long 0x20 12. "WKUPDEP_GPIO7_IRQ2_DSP1,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_DSP1_0,WKUPDEP_GPIO7_IRQ2_DSP1_1" bitfld.long 0x20 11. "WKUPDEP_GPIO7_IRQ2_IPU2,Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_IPU2_0,WKUPDEP_GPIO7_IRQ2_IPU2_1" newline bitfld.long 0x20 10. "WKUPDEP_GPIO7_IRQ2_MPU,Wakeup dependency from GPIO7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_MPU_0,WKUPDEP_GPIO7_IRQ2_MPU_1" bitfld.long 0x20 9. "WKUPDEP_GPIO7_IRQ1_EVE4,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_EVE4_0,WKUPDEP_GPIO7_IRQ1_EVE4_1" newline bitfld.long 0x20 8. "WKUPDEP_GPIO7_IRQ1_EVE3,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_EVE3_0,WKUPDEP_GPIO7_IRQ1_EVE3_1" bitfld.long 0x20 7. "WKUPDEP_GPIO7_IRQ1_EVE2,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_EVE2_0,WKUPDEP_GPIO7_IRQ1_EVE2_1" newline bitfld.long 0x20 6. "WKUPDEP_GPIO7_IRQ1_EVE1,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_EVE1_0,WKUPDEP_GPIO7_IRQ1_EVE1_1" bitfld.long 0x20 5. "WKUPDEP_GPIO7_IRQ1_DSP2,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_DSP2_0,WKUPDEP_GPIO7_IRQ1_DSP2_1" newline bitfld.long 0x20 4. "WKUPDEP_GPIO7_IRQ1_IPU1,Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_IPU1_0,WKUPDEP_GPIO7_IRQ1_IPU1_1" rbitfld.long 0x20 3. "RESERVED," "0,1" newline bitfld.long 0x20 2. "WKUPDEP_GPIO7_IRQ1_DSP1,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_DSP1_0,WKUPDEP_GPIO7_IRQ1_DSP1_1" bitfld.long 0x20 1. "WKUPDEP_GPIO7_IRQ1_IPU2,5Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_IPU2_0,WKUPDEP_GPIO7_IRQ1_IPU2_1" newline bitfld.long 0x20 0. "WKUPDEP_GPIO7_IRQ1_MPU,Wakeup dependency from GPIO7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_MPU_0,WKUPDEP_GPIO7_IRQ1_MPU_1" line.long 0x24 "RM_L4PER_GPIO7_CONTEXT,This register contains dedicated GPIO7 context statuses" hexmask.long 0x24 2.--31. 1. "RESERVED," bitfld.long 0x24 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x24 0. "RESERVED," "0,1" line.long 0x28 "PM_L4PER_GPIO8_WKDEP,This register controls wakeup dependency based on GPIO8 service requests" hexmask.long.word 0x28 20.--31. 1. "RESERVED," bitfld.long 0x28 19. "WKUPDEP_GPIO8_IRQ2_EVE4,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_EVE4_0,WKUPDEP_GPIO8_IRQ2_EVE4_1" newline bitfld.long 0x28 18. "WKUPDEP_GPIO8_IRQ2_EVE3,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_EVE3_0,WKUPDEP_GPIO8_IRQ2_EVE3_1" bitfld.long 0x28 17. "WKUPDEP_GPIO8_IRQ2_EVE2,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_EVE2_0,WKUPDEP_GPIO8_IRQ2_EVE2_1" newline bitfld.long 0x28 16. "WKUPDEP_GPIO8_IRQ2_EVE1,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_EVE1_0,WKUPDEP_GPIO8_IRQ2_EVE1_1" bitfld.long 0x28 15. "WKUPDEP_GPIO8_IRQ2_DSP2,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_DSP2_0,WKUPDEP_GPIO8_IRQ2_DSP2_1" newline bitfld.long 0x28 14. "WKUPDEP_GPIO8_IRQ2_IPU1,Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_IPU1_0,WKUPDEP_GPIO8_IRQ2_IPU1_1" rbitfld.long 0x28 13. "RESERVED," "0,1" newline bitfld.long 0x28 12. "WKUPDEP_GPIO8_IRQ2_DSP1,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_DSP1_0,WKUPDEP_GPIO8_IRQ2_DSP1_1" bitfld.long 0x28 11. "WKUPDEP_GPIO8_IRQ2_IPU2,Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_IPU2_0,WKUPDEP_GPIO8_IRQ2_IPU2_1" newline bitfld.long 0x28 10. "WKUPDEP_GPIO8_IRQ2_MPU,Wakeup dependency from GPIO8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_MPU_0,WKUPDEP_GPIO8_IRQ2_MPU_1" bitfld.long 0x28 9. "WKUPDEP_GPIO8_IRQ1_EVE4,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_EVE4_0,WKUPDEP_GPIO8_IRQ1_EVE4_1" newline bitfld.long 0x28 8. "WKUPDEP_GPIO8_IRQ1_EVE3,Wakeup dependency from GPIO8 (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_EVE3_0,WKUPDEP_GPIO8_IRQ1_EVE3_1" bitfld.long 0x28 7. "WKUPDEP_GPIO8_IRQ1_EVE2,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_EVE2_0,WKUPDEP_GPIO8_IRQ1_EVE2_1" newline bitfld.long 0x28 6. "WKUPDEP_GPIO8_IRQ1_EVE1,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_EVE1_0,WKUPDEP_GPIO8_IRQ1_EVE1_1" bitfld.long 0x28 5. "WKUPDEP_GPIO8_IRQ1_DSP2,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_DSP2_0,WKUPDEP_GPIO8_IRQ1_DSP2_1" newline bitfld.long 0x28 4. "WKUPDEP_GPIO8_IRQ1_IPU1,Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_IPU1_0,WKUPDEP_GPIO8_IRQ1_IPU1_1" rbitfld.long 0x28 3. "RESERVED," "0,1" newline bitfld.long 0x28 2. "WKUPDEP_GPIO8_IRQ1_DSP1,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_DSP1_0,WKUPDEP_GPIO8_IRQ1_DSP1_1" bitfld.long 0x28 1. "WKUPDEP_GPIO8_IRQ1_IPU2,5Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_IPU2_0,WKUPDEP_GPIO8_IRQ1_IPU2_1" newline bitfld.long 0x28 0. "WKUPDEP_GPIO8_IRQ1_MPU,Wakeup dependency from GPIO8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_MPU_0,WKUPDEP_GPIO8_IRQ1_MPU_1" line.long 0x2C "RM_L4PER_GPIO8_CONTEXT,This register contains dedicated GPIO8 context statuses" hexmask.long 0x2C 2.--31. 1. "RESERVED," bitfld.long 0x2C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x2C 0. "RESERVED," "0,1" line.long 0x30 "PM_L4PER_MMC3_WKDEP,This register controls wakeup dependency based on MMC3 service requests" hexmask.long.tbyte 0x30 10.--31. 1. "RESERVED," bitfld.long 0x30 9. "WKUPDEP_MMC3_EVE4,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_EVE4_0,WKUPDEP_MMC3_EVE4_1" newline bitfld.long 0x30 8. "WKUPDEP_MMC3_EVE3,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_EVE3_0,WKUPDEP_MMC3_EVE3_1" bitfld.long 0x30 7. "WKUPDEP_MMC3_EVE2,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_EVE2_0,WKUPDEP_MMC3_EVE2_1" newline bitfld.long 0x30 6. "WKUPDEP_MMC3_EVE1,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_EVE1_0,WKUPDEP_MMC3_EVE1_1" bitfld.long 0x30 5. "WKUPDEP_MMC3_DSP2,Wakeup dependency from MMC3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_DSP2_0,WKUPDEP_MMC3_DSP2_1" newline bitfld.long 0x30 4. "WKUPDEP_MMC3_IPU1,Wakeup dependency from MMC3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_IPU1_0,WKUPDEP_MMC3_IPU1_1" bitfld.long 0x30 3. "WKUPDEP_MMC3_SDMA,Wakeup dependency from MMC3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_SDMA_0,WKUPDEP_MMC3_SDMA_1" newline bitfld.long 0x30 2. "WKUPDEP_MMC3_DSP1,Wakeup dependency from MMC3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_DSP1_0,WKUPDEP_MMC3_DSP1_1" bitfld.long 0x30 1. "WKUPDEP_MMC3_IPU2,Wakeup dependency from MMC3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_IPU2_0,WKUPDEP_MMC3_IPU2_1" newline bitfld.long 0x30 0. "WKUPDEP_MMC3_MPU,Wakeup dependency from MMC3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC3_MPU_0,WKUPDEP_MMC3_MPU_1" line.long 0x34 "RM_L4PER_MMC3_CONTEXT,This register contains dedicated MMC3 context statuses" hexmask.long.tbyte 0x34 9.--31. 1. "RESERVED," bitfld.long 0x34 8. "LOSTMEM_NONRETAINED_BANK,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_NONRETAINED_BANK_0,LOSTMEM_NONRETAINED_BANK_1" newline hexmask.long.byte 0x34 1.--7. 1. "RESERVED," bitfld.long 0x34 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x38 "PM_L4PER_MMC4_WKDEP,This register controls wakeup dependency based on MMC4 service requests" hexmask.long.tbyte 0x38 10.--31. 1. "RESERVED," bitfld.long 0x38 9. "WKUPDEP_MMC4_EVE4,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_EVE4_0,WKUPDEP_MMC4_EVE4_1" newline bitfld.long 0x38 8. "WKUPDEP_MMC4_EVE3,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_EVE3_0,WKUPDEP_MMC4_EVE3_1" bitfld.long 0x38 7. "WKUPDEP_MMC4_EVE2,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_EVE2_0,WKUPDEP_MMC4_EVE2_1" newline bitfld.long 0x38 6. "WKUPDEP_MMC4_EVE1,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_EVE1_0,WKUPDEP_MMC4_EVE1_1" bitfld.long 0x38 5. "WKUPDEP_MMC4_DSP2,Wakeup dependency from MMC4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_DSP2_0,WKUPDEP_MMC4_DSP2_1" newline bitfld.long 0x38 4. "WKUPDEP_MMC4_IPU1,Wakeup dependency from MMC4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_IPU1_0,WKUPDEP_MMC4_IPU1_1" bitfld.long 0x38 3. "WKUPDEP_MMC4_SDMA,Wakeup dependency from MMC4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_SDMA_0,WKUPDEP_MMC4_SDMA_1" newline bitfld.long 0x38 2. "WKUPDEP_MMC4_DSP1,Wakeup dependency from MMC4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_DSP1_0,WKUPDEP_MMC4_DSP1_1" bitfld.long 0x38 1. "WKUPDEP_MMC4_IPU2,Wakeup dependency from MMC4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_IPU2_0,WKUPDEP_MMC4_IPU2_1" newline bitfld.long 0x38 0. "WKUPDEP_MMC4_MPU,Wakeup dependency from MMC4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MMC4_MPU_0,WKUPDEP_MMC4_MPU_1" line.long 0x3C "RM_L4PER_MMC4_CONTEXT,This register contains dedicated MMC4 context statuses" hexmask.long.tbyte 0x3C 9.--31. 1. "RESERVED," bitfld.long 0x3C 8. "LOSTMEM_NONRETAINED_BANK,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_NONRETAINED_BANK_0,LOSTMEM_NONRETAINED_BANK_1" newline hexmask.long.byte 0x3C 1.--7. 1. "RESERVED," bitfld.long 0x3C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x40 "PM_L4PER_DCC4_WKDEP,This register controls wakeup dependency based on DCC4 service requests" hexmask.long.tbyte 0x40 10.--31. 1. "RESERVED," bitfld.long 0x40 9. "WKUPDEP_DCC4_EVE4,Wakeup dependency from DCC4 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_EVE4_0,WKUPDEP_DCC4_EVE4_1" newline bitfld.long 0x40 8. "WKUPDEP_DCC4_EVE3,Wakeup dependency from DCC4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_EVE3_0,WKUPDEP_DCC4_EVE3_1" bitfld.long 0x40 7. "WKUPDEP_DCC4_EVE2,Wakeup dependency from DCC4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_EVE2_0,WKUPDEP_DCC4_EVE2_1" newline bitfld.long 0x40 6. "WKUPDEP_DCC4_EVE1,Wakeup dependency from DCC4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_EVE1_0,WKUPDEP_DCC4_EVE1_1" bitfld.long 0x40 5. "WKUPDEP_DCC4_DSP2,Wakeup dependency from DCC4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_DSP2_0,WKUPDEP_DCC4_DSP2_1" newline bitfld.long 0x40 4. "WKUPDEP_DCC4_IPU1,Wakeup dependency from DCC4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_IPU1_0,WKUPDEP_DCC4_IPU1_1" rbitfld.long 0x40 3. "RESERVED," "0,1" newline bitfld.long 0x40 2. "WKUPDEP_DCC4_DSP1,Wakeup dependency from DCC4 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_DSP1_0,WKUPDEP_DCC4_DSP1_1" bitfld.long 0x40 1. "WKUPDEP_DCC4_IPU2,Wakeup dependency from DCC4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_IPU2_0,WKUPDEP_DCC4_IPU2_1" newline bitfld.long 0x40 0. "WKUPDEP_DCC4_MPU,6Wakeup dependency from DCC1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCC4_MPU_0,WKUPDEP_DCC4_MPU_1" line.long 0x44 "RM_L4PER3_DCC4_CONTEXT,This register contains dedicated DCC4 context statuses" hexmask.long 0x44 1.--31. 1. "RESERVED," bitfld.long 0x44 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x48 "PM_L4PER2_QSPI_WKDEP,This register controls wakeup dependency based on QSPI service requests" hexmask.long.tbyte 0x48 10.--31. 1. "RESERVED," bitfld.long 0x48 9. "WKUPDEP_QSPI_EVE4,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_EVE4_0,WKUPDEP_QSPI_EVE4_1" newline bitfld.long 0x48 8. "WKUPDEP_QSPI_EVE3,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_EVE3_0,WKUPDEP_QSPI_EVE3_1" bitfld.long 0x48 7. "WKUPDEP_QSPI_EVE2,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_EVE2_0,WKUPDEP_QSPI_EVE2_1" newline bitfld.long 0x48 6. "WKUPDEP_QSPI_EVE1,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_EVE1_0,WKUPDEP_QSPI_EVE1_1" bitfld.long 0x48 5. "WKUPDEP_QSPI_DSP2,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_DSP2_0,WKUPDEP_QSPI_DSP2_1" newline bitfld.long 0x48 4. "WKUPDEP_QSPI_IPU1,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_IPU1_0,WKUPDEP_QSPI_IPU1_1" rbitfld.long 0x48 3. "RESERVED," "0,1" newline bitfld.long 0x48 2. "WKUPDEP_QSPI_DSP1,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_DSP1_0,WKUPDEP_QSPI_DSP1_1" bitfld.long 0x48 1. "WKUPDEP_QSPI_IPU2,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_IPU2_0,WKUPDEP_QSPI_IPU2_1" newline bitfld.long 0x48 0. "WKUPDEP_QSPI_MPU,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_MPU_0,WKUPDEP_QSPI_MPU_1" line.long 0x4C "RM_L4PER2_QSPI_CONTEXT,This register contains dedicated QSPI context statuses" hexmask.long 0x4C 1.--31. 1. "RESERVED," bitfld.long 0x4C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x50 "PM_L4PER_UART1_WKDEP,This register controls wakeup dependency based on UART1 service requests" hexmask.long.tbyte 0x50 10.--31. 1. "RESERVED," bitfld.long 0x50 9. "WKUPDEP_UART1_EVE4,Wakeup dependency from UART1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_EVE4_0,WKUPDEP_UART1_EVE4_1" newline bitfld.long 0x50 8. "WKUPDEP_UART1_EVE3,Wakeup dependency from UART1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_EVE3_0,WKUPDEP_UART1_EVE3_1" bitfld.long 0x50 7. "WKUPDEP_UART1_EVE2,Wakeup dependency from UART1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_EVE2_0,WKUPDEP_UART1_EVE2_1" newline bitfld.long 0x50 6. "WKUPDEP_UART1_EVE1,Wakeup dependency from UART1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_EVE1_0,WKUPDEP_UART1_EVE1_1" bitfld.long 0x50 5. "WKUPDEP_UART1_DSP2,Wakeup dependency from UART1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_DSP2_0,WKUPDEP_UART1_DSP2_1" newline bitfld.long 0x50 4. "WKUPDEP_UART1_IPU1,Wakeup dependency from UART1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_IPU1_0,WKUPDEP_UART1_IPU1_1" bitfld.long 0x50 3. "WKUPDEP_UART1_SDMA,Wakeup dependency from UART1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_SDMA_0,WKUPDEP_UART1_SDMA_1" newline bitfld.long 0x50 2. "WKUPDEP_UART1_DSP1,Wakeup dependency from UART1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_DSP1_0,WKUPDEP_UART1_DSP1_1" bitfld.long 0x50 1. "WKUPDEP_UART1_IPU2,Wakeup dependency from UART1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_IPU2_0,WKUPDEP_UART1_IPU2_1" newline bitfld.long 0x50 0. "WKUPDEP_UART1_MPU,Wakeup dependency from UART1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_MPU_0,WKUPDEP_UART1_MPU_1" line.long 0x54 "RM_L4PER_UART1_CONTEXT,This register contains dedicated UART1 context statuses" hexmask.long.tbyte 0x54 9.--31. 1. "RESERVED," bitfld.long 0x54 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x54 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x54 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x54 0. "RESERVED," "0,1" line.long 0x58 "PM_L4PER_UART2_WKDEP,This register controls wakeup dependency based on UART2 service requests" hexmask.long.tbyte 0x58 10.--31. 1. "RESERVED," bitfld.long 0x58 9. "WKUPDEP_UART2_EVE4,Wakeup dependency from UART2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_EVE4_0,WKUPDEP_UART2_EVE4_1" newline bitfld.long 0x58 8. "WKUPDEP_UART2_EVE3,Wakeup dependency from UART2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_EVE3_0,WKUPDEP_UART2_EVE3_1" bitfld.long 0x58 7. "WKUPDEP_UART2_EVE2,Wakeup dependency from UART2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_EVE2_0,WKUPDEP_UART2_EVE2_1" newline bitfld.long 0x58 6. "WKUPDEP_UART2_EVE1,Wakeup dependency from UART2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_EVE1_0,WKUPDEP_UART2_EVE1_1" bitfld.long 0x58 5. "WKUPDEP_UART2_DSP2,Wakeup dependency from UART2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_DSP2_0,WKUPDEP_UART2_DSP2_1" newline bitfld.long 0x58 4. "WKUPDEP_UART2_IPU1,Wakeup dependency from UART2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_IPU1_0,WKUPDEP_UART2_IPU1_1" bitfld.long 0x58 3. "WKUPDEP_UART2_SDMA,2Wakeup dependency from UART1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_SDMA_0,WKUPDEP_UART2_SDMA_1" newline bitfld.long 0x58 2. "WKUPDEP_UART2_DSP1,Wakeup dependency from UART2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_DSP1_0,WKUPDEP_UART2_DSP1_1" bitfld.long 0x58 1. "WKUPDEP_UART2_IPU2,Wakeup dependency from UART2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_IPU2_0,WKUPDEP_UART2_IPU2_1" newline bitfld.long 0x58 0. "WKUPDEP_UART2_MPU,Wakeup dependency from UART2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_MPU_0,WKUPDEP_UART2_MPU_1" line.long 0x5C "RM_L4PER_UART2_CONTEXT,This register contains dedicated UART2 context statuses" hexmask.long.tbyte 0x5C 9.--31. 1. "RESERVED," bitfld.long 0x5C 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x5C 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x5C 0. "RESERVED," "0,1" line.long 0x60 "PM_L4PER_UART3_WKDEP,This register controls wakeup dependency based on UART3 service requests" hexmask.long.tbyte 0x60 10.--31. 1. "RESERVED," bitfld.long 0x60 9. "WKUPDEP_UART3_EVE4,Wakeup dependency from UART3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_EVE4_0,WKUPDEP_UART3_EVE4_1" newline bitfld.long 0x60 8. "WKUPDEP_UART3_EVE3,Wakeup dependency from UART3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_EVE3_0,WKUPDEP_UART3_EVE3_1" bitfld.long 0x60 7. "WKUPDEP_UART3_EVE2,Wakeup dependency from UART3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_EVE2_0,WKUPDEP_UART3_EVE2_1" newline bitfld.long 0x60 6. "WKUPDEP_UART3_EVE1,Wakeup dependency from UART3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_EVE1_0,WKUPDEP_UART3_EVE1_1" bitfld.long 0x60 5. "WKUPDEP_UART3_DSP2,Wakeup dependency from UART3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_DSP2_0,WKUPDEP_UART3_DSP2_1" newline bitfld.long 0x60 4. "WKUPDEP_UART3_IPU1,Wakeup dependency from UART3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_IPU1_0,WKUPDEP_UART3_IPU1_1" bitfld.long 0x60 3. "WKUPDEP_UART3_SDMA,Wakeup dependency from UART3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_SDMA_0,WKUPDEP_UART3_SDMA_1" newline bitfld.long 0x60 2. "WKUPDEP_UART3_DSP1,Wakeup dependency from UART3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_DSP1_0,WKUPDEP_UART3_DSP1_1" bitfld.long 0x60 1. "WKUPDEP_UART3_IPU2,Wakeup dependency from UART3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_IPU2_0,WKUPDEP_UART3_IPU2_1" newline bitfld.long 0x60 0. "WKUPDEP_UART3_MPU,Wakeup dependency from UART3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_MPU_0,WKUPDEP_UART3_MPU_1" line.long 0x64 "RM_L4PER_UART3_CONTEXT,This register contains dedicated UART3 context statuses" hexmask.long.tbyte 0x64 9.--31. 1. "RESERVED," bitfld.long 0x64 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x64 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x64 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x64 0. "RESERVED," "0,1" line.long 0x68 "PM_L4PER_UART4_WKDEP,This register controls wakeup dependency based on UART4 service requests" hexmask.long.tbyte 0x68 10.--31. 1. "RESERVED," bitfld.long 0x68 9. "WKUPDEP_UART4_EVE4,Wakeup dependency from UART4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_EVE4_0,WKUPDEP_UART4_EVE4_1" newline bitfld.long 0x68 8. "WKUPDEP_UART4_EVE3,Wakeup dependency from UART4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_EVE3_0,WKUPDEP_UART4_EVE3_1" bitfld.long 0x68 7. "WKUPDEP_UART4_EVE2,Wakeup dependency from UART4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_EVE2_0,WKUPDEP_UART4_EVE2_1" newline bitfld.long 0x68 6. "WKUPDEP_UART4_EVE1,Wakeup dependency from UART4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_EVE1_0,WKUPDEP_UART4_EVE1_1" bitfld.long 0x68 5. "WKUPDEP_UART4_DSP2,Wakeup dependency from UART4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_DSP2_0,WKUPDEP_UART4_DSP2_1" newline bitfld.long 0x68 4. "WKUPDEP_UART4_IPU1,Wakeup dependency from UART4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_IPU1_0,WKUPDEP_UART4_IPU1_1" bitfld.long 0x68 3. "WKUPDEP_UART4_SDMA,Wakeup dependency from UART4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_SDMA_0,WKUPDEP_UART4_SDMA_1" newline bitfld.long 0x68 2. "WKUPDEP_UART4_DSP1,Wakeup dependency from UART4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_DSP1_0,WKUPDEP_UART4_DSP1_1" bitfld.long 0x68 1. "WKUPDEP_UART4_IPU2,Wakeup dependency from UART4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_IPU2_0,WKUPDEP_UART4_IPU2_1" newline bitfld.long 0x68 0. "WKUPDEP_UART4_MPU,Wakeup dependency from UART4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_MPU_0,WKUPDEP_UART4_MPU_1" line.long 0x6C "RM_L4PER_UART4_CONTEXT,This register contains dedicated UART4 context statuses" hexmask.long.tbyte 0x6C 9.--31. 1. "RESERVED," bitfld.long 0x6C 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x6C 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x6C 0. "RESERVED," "0,1" line.long 0x70 "PM_L4PER2_ADC_WKDEP,This register controls wakeup dependency based on ADC service requests" hexmask.long.word 0x70 16.--31. 1. "RESERVED," bitfld.long 0x70 15. "WKUPDEP_ADC_DMA_DSP2,Wakeup dependency from ADC module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_DMA_DSP2_0,WKUPDEP_ADC_DMA_DSP2_1" newline rbitfld.long 0x70 14. "RESERVED," "0,1" bitfld.long 0x70 13. "WKUPDEP_ADC_DMA_SDMA,Wakeup dependency from ADC module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_DMA_SDMA_0,WKUPDEP_ADC_DMA_SDMA_1" newline bitfld.long 0x70 12. "WKUPDEP_ADC_DMA_DSP1,Wakeup dependency from ADC module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_DMA_DSP1_0,WKUPDEP_ADC_DMA_DSP1_1" rbitfld.long 0x70 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x70 9. "WKUPDEP_ADC_IRQ_EVE4,Wakeup dependency from ADC module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_EVE4_0,WKUPDEP_ADC_IRQ_EVE4_1" bitfld.long 0x70 8. "WKUPDEP_ADC_IRQ_EVE3,Wakeup dependency from ADC module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_EVE3_0,WKUPDEP_ADC_IRQ_EVE3_1" newline bitfld.long 0x70 7. "WKUPDEP_ADC_IRQ_EVE2,Wakeup dependency from ADC module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_EVE2_0,WKUPDEP_ADC_IRQ_EVE2_1" bitfld.long 0x70 6. "WKUPDEP_ADC_IRQ_EVE1,Wakeup dependency from ADC module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_EVE1_0,WKUPDEP_ADC_IRQ_EVE1_1" newline bitfld.long 0x70 5. "WKUPDEP_ADC_IRQ_DSP2,Wakeup dependency from ADC module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_DSP2_0,WKUPDEP_ADC_IRQ_DSP2_1" bitfld.long 0x70 4. "WKUPDEP_ADC_IRQ_IPU1,Wakeup dependency from ADC module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_IPU1_0,WKUPDEP_ADC_IRQ_IPU1_1" newline rbitfld.long 0x70 3. "RESERVED," "0,1" bitfld.long 0x70 2. "WKUPDEP_ADC_IRQ_DSP1,Wakeup dependency from ADC module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_DSP1_0,WKUPDEP_ADC_IRQ_DSP1_1" newline bitfld.long 0x70 1. "WKUPDEP_ADC_IRQ_IPU2,Wakeup dependency from ADC module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_IPU2_0,WKUPDEP_ADC_IRQ_IPU2_1" bitfld.long 0x70 0. "WKUPDEP_ADC_IRQ_MPU,Wakeup dependency from ADC module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IRQ_MPU_0,WKUPDEP_ADC_IRQ_MPU_1" line.long 0x74 "RM_L4PER2_ADC_CONTEXT,This register contains dedicated ADC context statuses" hexmask.long 0x74 1.--31. 1. "RESERVED," bitfld.long 0x74 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x78 "PM_L4PER2_MCASP3_WKDEP,This register controls wakeup dependency based on MCASP3 service requests" hexmask.long.word 0x78 16.--31. 1. "RESERVED," bitfld.long 0x78 15. "WKUPDEP_MCASP3_DMA_DSP2,Wakeup dependency from MCASP3 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_DMA_DSP2_0,WKUPDEP_MCASP3_DMA_DSP2_1" newline rbitfld.long 0x78 14. "RESERVED," "0,1" bitfld.long 0x78 13. "WKUPDEP_MCASP3_DMA_SDMA,Wakeup dependency from MCASP3 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_DMA_SDMA_0,WKUPDEP_MCASP3_DMA_SDMA_1" newline bitfld.long 0x78 12. "WKUPDEP_MCASP3_DMA_DSP1,3Wakeup dependency from ADC module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_DMA_DSP1_0,WKUPDEP_MCASP3_DMA_DSP1_1" rbitfld.long 0x78 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x78 9. "WKUPDEP_MCASP3_IRQ_EVE4,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_EVE4_0,WKUPDEP_MCASP3_IRQ_EVE4_1" bitfld.long 0x78 8. "WKUPDEP_MCASP3_IRQ_EVE3,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_EVE3_0,WKUPDEP_MCASP3_IRQ_EVE3_1" newline bitfld.long 0x78 7. "WKUPDEP_MCASP3_IRQ_EVE2,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_EVE2_0,WKUPDEP_MCASP3_IRQ_EVE2_1" bitfld.long 0x78 6. "WKUPDEP_MCASP3_IRQ_EVE1,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_EVE1_0,WKUPDEP_MCASP3_IRQ_EVE1_1" newline bitfld.long 0x78 5. "WKUPDEP_MCASP3_IRQ_DSP2,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_DSP2_0,WKUPDEP_MCASP3_IRQ_DSP2_1" bitfld.long 0x78 4. "WKUPDEP_MCASP3_IRQ_IPU1,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_IPU1_0,WKUPDEP_MCASP3_IRQ_IPU1_1" newline rbitfld.long 0x78 3. "RESERVED," "0,1" bitfld.long 0x78 2. "WKUPDEP_MCASP3_IRQ_DSP1,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_DSP1_0,WKUPDEP_MCASP3_IRQ_DSP1_1" newline bitfld.long 0x78 1. "WKUPDEP_MCASP3_IRQ_IPU2,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_IPU2_0,WKUPDEP_MCASP3_IRQ_IPU2_1" bitfld.long 0x78 0. "WKUPDEP_MCASP3_IRQ_MPU,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP3_IRQ_MPU_0,WKUPDEP_MCASP3_IRQ_MPU_1" line.long 0x7C "RM_L4PER2_MCASP3_CONTEXT,This register contains dedicated MCASP3 context statuses" hexmask.long 0x7C 1.--31. 1. "RESERVED," bitfld.long 0x7C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x80 "PM_L4PER_UART5_WKDEP,This register controls wakeup dependency based on UART5 service requests" hexmask.long.tbyte 0x80 10.--31. 1. "RESERVED," bitfld.long 0x80 9. "WKUPDEP_UART5_EVE4,Wakeup dependency from UART5 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_EVE4_0,WKUPDEP_UART5_EVE4_1" newline bitfld.long 0x80 8. "WKUPDEP_UART5_EVE3,Wakeup dependency from UART5 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_EVE3_0,WKUPDEP_UART5_EVE3_1" bitfld.long 0x80 7. "WKUPDEP_UART5_EVE2,Wakeup dependency from UART5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_EVE2_0,WKUPDEP_UART5_EVE2_1" newline bitfld.long 0x80 6. "WKUPDEP_UART5_EVE1,Wakeup dependency from UART5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_EVE1_0,WKUPDEP_UART5_EVE1_1" bitfld.long 0x80 5. "WKUPDEP_UART5_DSP2,Wakeup dependency from UART5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_DSP2_0,WKUPDEP_UART5_DSP2_1" newline bitfld.long 0x80 4. "WKUPDEP_UART5_IPU1,Wakeup dependency from UART5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_IPU1_0,WKUPDEP_UART5_IPU1_1" bitfld.long 0x80 3. "WKUPDEP_UART5_SDMA,Wakeup dependency from UART5 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_SDMA_0,WKUPDEP_UART5_SDMA_1" newline bitfld.long 0x80 2. "WKUPDEP_UART5_DSP1,Wakeup dependency from UART5 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_DSP1_0,WKUPDEP_UART5_DSP1_1" bitfld.long 0x80 1. "WKUPDEP_UART5_IPU2,Wakeup dependency from UART5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_IPU2_0,WKUPDEP_UART5_IPU2_1" newline bitfld.long 0x80 0. "WKUPDEP_UART5_MPU,Wakeup dependency from UART5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_MPU_0,WKUPDEP_UART5_MPU_1" line.long 0x84 "RM_L4PER_UART5_CONTEXT,This register contains dedicated UART5 context statuses" hexmask.long.tbyte 0x84 9.--31. 1. "RESERVED," bitfld.long 0x84 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x84 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x84 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x84 0. "RESERVED," "0,1" line.long 0x88 "PM_L4PER2_MCASP5_WKDEP,This register controls wakeup dependency based on MCASP5 service requests" hexmask.long.word 0x88 16.--31. 1. "RESERVED," bitfld.long 0x88 15. "WKUPDEP_MCASP5_DMA_DSP2,Wakeup dependency from MCASP5 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_DMA_DSP2_0,WKUPDEP_MCASP5_DMA_DSP2_1" newline rbitfld.long 0x88 14. "RESERVED," "0,1" bitfld.long 0x88 13. "WKUPDEP_MCASP5_DMA_SDMA,Wakeup dependency from MCASP5 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_DMA_SDMA_0,WKUPDEP_MCASP5_DMA_SDMA_1" newline bitfld.long 0x88 12. "WKUPDEP_MCASP5_DMA_DSP1,Wakeup dependency from MCASP5 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_DMA_DSP1_0,WKUPDEP_MCASP5_DMA_DSP1_1" rbitfld.long 0x88 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x88 9. "WKUPDEP_MCASP5_IRQ_EVE4,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_EVE4_0,WKUPDEP_MCASP5_IRQ_EVE4_1" bitfld.long 0x88 8. "WKUPDEP_MCASP5_IRQ_EVE3,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_EVE3_0,WKUPDEP_MCASP5_IRQ_EVE3_1" newline bitfld.long 0x88 7. "WKUPDEP_MCASP5_IRQ_EVE2,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_EVE2_0,WKUPDEP_MCASP5_IRQ_EVE2_1" bitfld.long 0x88 6. "WKUPDEP_MCASP5_IRQ_EVE1,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_EVE1_0,WKUPDEP_MCASP5_IRQ_EVE1_1" newline bitfld.long 0x88 5. "WKUPDEP_MCASP5_IRQ_DSP2,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_DSP2_0,WKUPDEP_MCASP5_IRQ_DSP2_1" bitfld.long 0x88 4. "WKUPDEP_MCASP5_IRQ_IPU1,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_IPU1_0,WKUPDEP_MCASP5_IRQ_IPU1_1" newline rbitfld.long 0x88 3. "RESERVED," "0,1" bitfld.long 0x88 2. "WKUPDEP_MCASP5_IRQ_DSP1,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_DSP1_0,WKUPDEP_MCASP5_IRQ_DSP1_1" newline bitfld.long 0x88 1. "WKUPDEP_MCASP5_IRQ_IPU2,Wakeup dependency from ADC module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_IPU2_0,WKUPDEP_MCASP5_IRQ_IPU2_1" bitfld.long 0x88 0. "WKUPDEP_MCASP5_IRQ_MPU,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP5_IRQ_MPU_0,WKUPDEP_MCASP5_IRQ_MPU_1" line.long 0x8C "RM_L4PER2_MCASP5_CONTEXT,This register contains dedicated MCASP5 context statuses" hexmask.long 0x8C 1.--31. 1. "RESERVED," bitfld.long 0x8C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x90 "PM_L4PER2_MCASP6_WKDEP,This register controls wakeup dependency based on MCASP6 service requests" hexmask.long.word 0x90 16.--31. 1. "RESERVED," bitfld.long 0x90 15. "WKUPDEP_MCASP6_DMA_DSP2,Wakeup dependency from MCASP6 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_DMA_DSP2_0,WKUPDEP_MCASP6_DMA_DSP2_1" newline rbitfld.long 0x90 14. "RESERVED," "0,1" bitfld.long 0x90 13. "WKUPDEP_MCASP6_DMA_SDMA,Wakeup dependency from MCASP6 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_DMA_SDMA_0,WKUPDEP_MCASP6_DMA_SDMA_1" newline bitfld.long 0x90 12. "WKUPDEP_MCASP6_DMA_DSP1,Wakeup dependency from MCASP6 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_DMA_DSP1_0,WKUPDEP_MCASP6_DMA_DSP1_1" rbitfld.long 0x90 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x90 9. "WKUPDEP_MCASP6_IRQ_EVE4,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_EVE4_0,WKUPDEP_MCASP6_IRQ_EVE4_1" bitfld.long 0x90 8. "WKUPDEP_MCASP6_IRQ_EVE3,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_EVE3_0,WKUPDEP_MCASP6_IRQ_EVE3_1" newline bitfld.long 0x90 7. "WKUPDEP_MCASP6_IRQ_EVE2,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_EVE2_0,WKUPDEP_MCASP6_IRQ_EVE2_1" bitfld.long 0x90 6. "WKUPDEP_MCASP6_IRQ_EVE1,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_EVE1_0,WKUPDEP_MCASP6_IRQ_EVE1_1" newline bitfld.long 0x90 5. "WKUPDEP_MCASP6_IRQ_DSP2,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_DSP2_0,WKUPDEP_MCASP6_IRQ_DSP2_1" bitfld.long 0x90 4. "WKUPDEP_MCASP6_IRQ_IPU1,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_IPU1_0,WKUPDEP_MCASP6_IRQ_IPU1_1" newline rbitfld.long 0x90 3. "RESERVED," "0,1" bitfld.long 0x90 2. "WKUPDEP_MCASP6_IRQ_DSP1,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_DSP1_0,WKUPDEP_MCASP6_IRQ_DSP1_1" newline bitfld.long 0x90 1. "WKUPDEP_MCASP6_IRQ_IPU2,Wakeup dependency from MCASP6 (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_IPU2_0,WKUPDEP_MCASP6_IRQ_IPU2_1" bitfld.long 0x90 0. "WKUPDEP_MCASP6_IRQ_MPU,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP6_IRQ_MPU_0,WKUPDEP_MCASP6_IRQ_MPU_1" line.long 0x94 "RM_L4PER2_MCASP6_CONTEXT,This register contains dedicated MCASP6 context statuses" hexmask.long 0x94 1.--31. 1. "RESERVED," bitfld.long 0x94 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x98 "PM_L4PER2_MCASP7_WKDEP,This register controls wakeup dependency based on MCASP7 service requests" hexmask.long.word 0x98 16.--31. 1. "RESERVED," bitfld.long 0x98 15. "WKUPDEP_MCASP7_DMA_DSP2,Wakeup dependency from MCASP7 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_DMA_DSP2_0,WKUPDEP_MCASP7_DMA_DSP2_1" newline rbitfld.long 0x98 14. "RESERVED," "0,1" bitfld.long 0x98 13. "WKUPDEP_MCASP7_DMA_SDMA,Wakeup dependency from MCASP7 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_DMA_SDMA_0,WKUPDEP_MCASP7_DMA_SDMA_1" newline bitfld.long 0x98 12. "WKUPDEP_MCASP7_DMA_DSP1,Wakeup dependency from MCASP7 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_DMA_DSP1_0,WKUPDEP_MCASP7_DMA_DSP1_1" rbitfld.long 0x98 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x98 9. "WKUPDEP_MCASP7_IRQ_EVE4,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_EVE4_0,WKUPDEP_MCASP7_IRQ_EVE4_1" bitfld.long 0x98 8. "WKUPDEP_MCASP7_IRQ_EVE3,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_EVE3_0,WKUPDEP_MCASP7_IRQ_EVE3_1" newline bitfld.long 0x98 7. "WKUPDEP_MCASP7_IRQ_EVE2,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_EVE2_0,WKUPDEP_MCASP7_IRQ_EVE2_1" bitfld.long 0x98 6. "WKUPDEP_MCASP7_IRQ_EVE1,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_EVE1_0,WKUPDEP_MCASP7_IRQ_EVE1_1" newline bitfld.long 0x98 5. "WKUPDEP_MCASP7_IRQ_DSP2,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_DSP2_0,WKUPDEP_MCASP7_IRQ_DSP2_1" bitfld.long 0x98 4. "WKUPDEP_MCASP7_IRQ_IPU1,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_IPU1_0,WKUPDEP_MCASP7_IRQ_IPU1_1" newline rbitfld.long 0x98 3. "RESERVED," "0,1" bitfld.long 0x98 2. "WKUPDEP_MCASP7_IRQ_DSP1,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_DSP1_0,WKUPDEP_MCASP7_IRQ_DSP1_1" newline bitfld.long 0x98 1. "WKUPDEP_MCASP7_IRQ_IPU2,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_IPU2_0,WKUPDEP_MCASP7_IRQ_IPU2_1" bitfld.long 0x98 0. "WKUPDEP_MCASP7_IRQ_MPU,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP7_IRQ_MPU_0,WKUPDEP_MCASP7_IRQ_MPU_1" line.long 0x9C "RM_L4PER2_MCASP7_CONTEXT,This register contains dedicated MCASP7 context statuses" hexmask.long 0x9C 1.--31. 1. "RESERVED," bitfld.long 0x9C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0xA0 "PM_L4PER2_MCASP8_WKDEP,This register controls wakeup dependency based on MCASP8 service requests" hexmask.long.word 0xA0 16.--31. 1. "RESERVED," bitfld.long 0xA0 15. "WKUPDEP_MCASP8_DMA_DSP2,Wakeup dependency from MCASP8 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_DMA_DSP2_0,WKUPDEP_MCASP8_DMA_DSP2_1" newline rbitfld.long 0xA0 14. "RESERVED," "0,1" bitfld.long 0xA0 13. "WKUPDEP_MCASP8_DMA_SDMA,Wakeup dependency from MCASP8 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_DMA_SDMA_0,WKUPDEP_MCASP8_DMA_SDMA_1" newline bitfld.long 0xA0 12. "WKUPDEP_MCASP8_DMA_DSP1,Wakeup dependency from MCASP8 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_DMA_DSP1_0,WKUPDEP_MCASP8_DMA_DSP1_1" rbitfld.long 0xA0 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0xA0 9. "WKUPDEP_MCASP8_IRQ_EVE4,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_EVE4_0,WKUPDEP_MCASP8_IRQ_EVE4_1" bitfld.long 0xA0 8. "WKUPDEP_MCASP8_IRQ_EVE3,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_EVE3_0,WKUPDEP_MCASP8_IRQ_EVE3_1" newline bitfld.long 0xA0 7. "WKUPDEP_MCASP8_IRQ_EVE2,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_EVE2_0,WKUPDEP_MCASP8_IRQ_EVE2_1" bitfld.long 0xA0 6. "WKUPDEP_MCASP8_IRQ_EVE1,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_EVE1_0,WKUPDEP_MCASP8_IRQ_EVE1_1" newline bitfld.long 0xA0 5. "WKUPDEP_MCASP8_IRQ_DSP2,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_DSP2_0,WKUPDEP_MCASP8_IRQ_DSP2_1" bitfld.long 0xA0 4. "WKUPDEP_MCASP8_IRQ_IPU1,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_IPU1_0,WKUPDEP_MCASP8_IRQ_IPU1_1" newline rbitfld.long 0xA0 3. "RESERVED," "0,1" bitfld.long 0xA0 2. "WKUPDEP_MCASP8_IRQ_DSP1,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_DSP1_0,WKUPDEP_MCASP8_IRQ_DSP1_1" newline bitfld.long 0xA0 1. "WKUPDEP_MCASP8_IRQ_IPU2,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_IPU2_0,WKUPDEP_MCASP8_IRQ_IPU2_1" bitfld.long 0xA0 0. "WKUPDEP_MCASP8_IRQ_MPU,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP8_IRQ_MPU_0,WKUPDEP_MCASP8_IRQ_MPU_1" line.long 0xA4 "RM_L4PER2_MCASP8_CONTEXT,This register contains dedicated MCASP8 context statuses" hexmask.long 0xA4 1.--31. 1. "RESERVED," bitfld.long 0xA4 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0xA8 "PM_L4PER2_MCASP4_WKDEP,This register controls wakeup dependency based on MCASP4 service requests" hexmask.long.word 0xA8 16.--31. 1. "RESERVED," bitfld.long 0xA8 15. "WKUPDEP_MCASP4_DMA_DSP2,Wakeup dependency from MCASP4 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_DMA_DSP2_0,WKUPDEP_MCASP4_DMA_DSP2_1" newline rbitfld.long 0xA8 14. "RESERVED," "0,1" bitfld.long 0xA8 13. "WKUPDEP_MCASP4_DMA_SDMA,Wakeup dependency from MCASP4 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_DMA_SDMA_0,WKUPDEP_MCASP4_DMA_SDMA_1" newline bitfld.long 0xA8 12. "WKUPDEP_MCASP4_DMA_DSP1,Wakeup dependency from MCASP4 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_DMA_DSP1_0,WKUPDEP_MCASP4_DMA_DSP1_1" rbitfld.long 0xA8 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0xA8 9. "WKUPDEP_MCASP4_IRQ_EVE4,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_EVE4_0,WKUPDEP_MCASP4_IRQ_EVE4_1" bitfld.long 0xA8 8. "WKUPDEP_MCASP4_IRQ_EVE3,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_EVE3_0,WKUPDEP_MCASP4_IRQ_EVE3_1" newline bitfld.long 0xA8 7. "WKUPDEP_MCASP4_IRQ_EVE2,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_EVE2_0,WKUPDEP_MCASP4_IRQ_EVE2_1" bitfld.long 0xA8 6. "WKUPDEP_MCASP4_IRQ_EVE1,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_EVE1_0,WKUPDEP_MCASP4_IRQ_EVE1_1" newline bitfld.long 0xA8 5. "WKUPDEP_MCASP4_IRQ_DSP2,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_DSP2_0,WKUPDEP_MCASP4_IRQ_DSP2_1" bitfld.long 0xA8 4. "WKUPDEP_MCASP4_IRQ_IPU1,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_IPU1_0,WKUPDEP_MCASP4_IRQ_IPU1_1" newline rbitfld.long 0xA8 3. "RESERVED," "0,1" bitfld.long 0xA8 2. "WKUPDEP_MCASP4_IRQ_DSP1,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_DSP1_0,WKUPDEP_MCASP4_IRQ_DSP1_1" newline bitfld.long 0xA8 1. "WKUPDEP_MCASP4_IRQ_IPU2,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_IPU2_0,WKUPDEP_MCASP4_IRQ_IPU2_1" bitfld.long 0xA8 0. "WKUPDEP_MCASP4_IRQ_MPU,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP4_IRQ_MPU_0,WKUPDEP_MCASP4_IRQ_MPU_1" line.long 0xAC "RM_L4PER2_MCASP4_CONTEXT,This register contains dedicated MCASP4 context statuses" hexmask.long 0xAC 1.--31. 1. "RESERVED," bitfld.long 0xAC 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x1A4++0x03 line.long 0x00 "RM_L4SEC_AES1_CONTEXT,This register contains dedicated AES1 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x1AC++0x03 line.long 0x00 "RM_L4SEC_AES2_CONTEXT,This register contains dedicated AES2 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x1B4++0x03 line.long 0x00 "RM_L4SEC_DES3DES_CONTEXT,This register contains dedicated DES3DES context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x1BC++0x03 line.long 0x00 "RM_L4SEC_FPKA_CONTEXT,This register contains dedicated FPKA context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_NONRETAINED_BANK,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_NONRETAINED_BANK_0,LOSTMEM_NONRETAINED_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x1C4++0x03 line.long 0x00 "RM_L4SEC_RNG_CONTEXT,This register contains dedicated RNG context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" group.long 0x1CC++0x0B line.long 0x00 "RM_L4SEC_SHA2MD51_CONTEXT,This register contains dedicated SHA2MD51 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" line.long 0x04 "PM_L4PER2_UART7_WKDEP,This register controls wakeup dependency based on UART7 service requests" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "WKUPDEP_UART7_EVE4,Wakeup dependency from UART7 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_EVE4_0,WKUPDEP_UART7_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_UART7_EVE3,Wakeup dependency from UART7 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_EVE3_0,WKUPDEP_UART7_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_UART7_EVE2,Wakeup dependency from UART7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_EVE2_0,WKUPDEP_UART7_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_UART7_EVE1,Wakeup dependency from UART7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_EVE1_0,WKUPDEP_UART7_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_UART7_DSP2,Wakeup dependency from UART7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_DSP2_0,WKUPDEP_UART7_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_UART7_IPU1,Wakeup dependency from UART7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_IPU1_0,WKUPDEP_UART7_IPU1_1" bitfld.long 0x04 3. "WKUPDEP_UART7_SDMA,Wakeup dependency from UART7 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_SDMA_0,WKUPDEP_UART7_SDMA_1" newline bitfld.long 0x04 2. "WKUPDEP_UART7_DSP1,Wakeup dependency from UART7 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_DSP1_0,WKUPDEP_UART7_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_UART7_IPU2,Wakeup dependency from UART7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_IPU2_0,WKUPDEP_UART7_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_UART7_MPU,Wakeup dependency from UART7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_MPU_0,WKUPDEP_UART7_MPU_1" line.long 0x08 "RM_L4PER2_UART7_CONTEXT,This register contains dedicated UART7 context statuses" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," bitfld.long 0x08 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x08 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x08 0. "RESERVED," "0,1" group.long 0x1DC++0x1B line.long 0x00 "RM_L4SEC_DMA_CRYPTO_CONTEXT,This register contains dedicated DMA_CRYPTO context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" line.long 0x04 "PM_L4PER2_UART8_WKDEP,This register controls wakeup dependency based on UART8 service requests" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "WKUPDEP_UART8_EVE4,Wakeup dependency from UART8 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_EVE4_0,WKUPDEP_UART8_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_UART8_EVE3,Wakeup dependency from UART8 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_EVE3_0,WKUPDEP_UART8_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_UART8_EVE2,Wakeup dependency from UART8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_EVE2_0,WKUPDEP_UART8_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_UART8_EVE1,Wakeup dependency from UART8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_EVE1_0,WKUPDEP_UART8_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_UART8_DSP2,Wakeup dependency from UART8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_DSP2_0,WKUPDEP_UART8_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_UART8_IPU1,Wakeup dependency from UART8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_IPU1_0,WKUPDEP_UART8_IPU1_1" bitfld.long 0x04 3. "WKUPDEP_UART8_SDMA,Wakeup dependency from UART8 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_SDMA_0,WKUPDEP_UART8_SDMA_1" newline bitfld.long 0x04 2. "WKUPDEP_UART8_DSP1,Wakeup dependency from UART8 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_DSP1_0,WKUPDEP_UART8_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_UART8_IPU2,Wakeup dependency from UART8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_IPU2_0,WKUPDEP_UART8_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_UART8_MPU,Wakeup dependency from UART8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_MPU_0,WKUPDEP_UART8_MPU_1" line.long 0x08 "RM_L4PER2_UART8_CONTEXT,This register contains dedicated UART8 context statuses" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," bitfld.long 0x08 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x08 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x08 0. "RESERVED," "0,1" line.long 0x0C "PM_L4PER2_UART9_WKDEP,This register controls wakeup dependency based on UART9 service requests" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED," bitfld.long 0x0C 9. "WKUPDEP_UART9_EVE4,Wakeup dependency from UART9 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_EVE4_0,WKUPDEP_UART9_EVE4_1" newline bitfld.long 0x0C 8. "WKUPDEP_UART9_EVE3,Wakeup dependency from UART9 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_EVE3_0,WKUPDEP_UART9_EVE3_1" bitfld.long 0x0C 7. "WKUPDEP_UART9_EVE2,Wakeup dependency from UART9 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_EVE2_0,WKUPDEP_UART9_EVE2_1" newline bitfld.long 0x0C 6. "WKUPDEP_UART9_EVE1,Wakeup dependency from UART9 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_EVE1_0,WKUPDEP_UART9_EVE1_1" bitfld.long 0x0C 5. "WKUPDEP_UART9_DSP2,Wakeup dependency from UART9 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_DSP2_0,WKUPDEP_UART9_DSP2_1" newline bitfld.long 0x0C 4. "WKUPDEP_UART9_IPU1,Wakeup dependency from UART9 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_IPU1_0,WKUPDEP_UART9_IPU1_1" bitfld.long 0x0C 3. "WKUPDEP_UART9_SDMA,Wakeup dependency from UART9 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_SDMA_0,WKUPDEP_UART9_SDMA_1" newline bitfld.long 0x0C 2. "WKUPDEP_UART9_DSP1,Wakeup dependency from UART4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_DSP1_0,WKUPDEP_UART9_DSP1_1" bitfld.long 0x0C 1. "WKUPDEP_UART9_IPU2,Wakeup dependency from UART4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_IPU2_0,WKUPDEP_UART9_IPU2_1" newline bitfld.long 0x0C 0. "WKUPDEP_UART9_MPU,Wakeup dependency from UART9 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_MPU_0,WKUPDEP_UART9_MPU_1" line.long 0x10 "RM_L4PER2_UART9_CONTEXT,This register contains dedicated UART9 context statuses" hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED," bitfld.long 0x10 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline rbitfld.long 0x10 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x10 0. "RESERVED," "0,1" line.long 0x14 "PM_L4PER2_DCAN2_WKDEP,This register controls wakeup dependency based on MCAN service requests" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," bitfld.long 0x14 9. "WKUPDEP_DCAN2_EVE4,Wakeup dependency from MCAN module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_EVE4_0,WKUPDEP_DCAN2_EVE4_1" newline bitfld.long 0x14 8. "WKUPDEP_DCAN2_EVE3,Wakeup dependency from MCAN module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_EVE3_0,WKUPDEP_DCAN2_EVE3_1" bitfld.long 0x14 7. "WKUPDEP_DCAN2_EVE2,Wakeup dependency from MCAN module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_EVE2_0,WKUPDEP_DCAN2_EVE2_1" newline bitfld.long 0x14 6. "WKUPDEP_DCAN2_EVE1,Wakeup dependency from MCAN module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_EVE1_0,WKUPDEP_DCAN2_EVE1_1" bitfld.long 0x14 5. "WKUPDEP_DCAN2_DSP2,Wakeup dependency from MCAN module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_DSP2_0,WKUPDEP_DCAN2_DSP2_1" newline bitfld.long 0x14 4. "WKUPDEP_DCAN2_IPU1,Wakeup dependency from MCAN module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_IPU1_0,WKUPDEP_DCAN2_IPU1_1" bitfld.long 0x14 3. "WKUPDEP_DCAN2_SDMA,Wakeup dependency from MCAN module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_SDMA_0,WKUPDEP_DCAN2_SDMA_1" newline bitfld.long 0x14 2. "WKUPDEP_DCAN2_DSP1,Wakeup dependency from MCAN module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_DSP1_0,WKUPDEP_DCAN2_DSP1_1" bitfld.long 0x14 1. "WKUPDEP_DCAN2_IPU2,Wakeup dependency from MCAN module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_IPU2_0,WKUPDEP_DCAN2_IPU2_1" newline bitfld.long 0x14 0. "WKUPDEP_DCAN2_MPU,Wakeup dependency from MCAN module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_MPU_0,WKUPDEP_DCAN2_MPU_1" line.long 0x18 "RM_L4PER2_DCAN2_CONTEXT,This register contains dedicated MCAN context statuses" hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED," bitfld.long 0x18 8. "LOSTMEM_DCAN_BANK,Specify if memory-based context in DCAN memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DCAN_BANK_0,LOSTMEM_DCAN_BANK_1" newline hexmask.long.byte 0x18 1.--7. 1. "RESERVED," bitfld.long 0x18 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x1FC++0x03 line.long 0x00 "RM_L4SEC_SHA2MD52_CONTEXT,This register contains dedicated SHA2MD52 context statuses" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline rbitfld.long 0x00 0. "RESERVED," "0,1" width 0x0B tree.end tree "MAILBOX1_TARG" base ad:0x4A0F5000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_H,Error reporting" line.long 0x14 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x14 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x14 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x14 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x14 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x14 0. "OCP_RESET,L3 Reset" "0,1" width 0x0B tree.end tree "MAILBOX2_TARG" base ad:0x4883B000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCAN" base ad:0x48480000 rgroup.long 0x1900++0x2B line.long 0x00 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the module" bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID" newline bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3" newline bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCAN module" hexmask.long 0x04 7.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" newline bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x04 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x04 3. "FREE," "0,1" newline bitfld.long 0x04 2. "SOFT,If FREE =" "debug suspend doesn't wait for Idle,debug suspend waits for Idle" newline bitfld.long 0x04 1. "CLKFACK,Clock Fast Ack" "0,1" newline bitfld.long 0x04 0. "RESET,Initiates a Soft Reset" "0,1" line.long 0x08 "MCANSS_STAT,Status Regsiter The Status register provide general status bits for the MCAN module" hexmask.long 0x08 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x08 3.--5. "STATE," "?,In transition to Idle,Idle,In transition to Active,?..." newline bitfld.long 0x08 2. "ENABLE_FDOE,Enable CAN FD configuration" "0,1" newline bitfld.long 0x08 1. "MEM_INIT_DONE," "0,1" newline bitfld.long 0x08 0. "RESET," "0,1" line.long 0x0C "MCANSS_ICS,Interrupt Clear Shadow Register Write to clear interrupt bits" hexmask.long 0x0C 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt status" "0,1" line.long 0x10 "MCANSS_IRS,Interrupt Raw Status Register Read raw interrupt status" hexmask.long 0x10 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt status" "0,1" line.long 0x14 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write to clear interrupt enable bits" hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" line.long 0x18 "MCANSS_IE,Interrupt Enable Register Read interrupt Enable" hexmask.long 0x18 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x18 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" line.long 0x1C "MCANSS_IES,Interrupt Enable Status Read Enabled Interrupts" hexmask.long 0x1C 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" line.long 0x20 "MCANSS_EOI,End Of Interrupt End of Interrupt Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x20 0.--7. 1. "EOI,Write with bit position of targetted interrupt (example: External TS is bit 0)" line.long 0x24 "MCANSS_EXT_TS_PRESCALER,External Timestamp PreScaler 0 External TImeStamp PreScaler" hexmask.long.byte 0x24 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value" line.long 0x28 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp PreScaler 0 Unserviced Interrupts Counter External TImeStamp Unserviced Interrupts Counter" hexmask.long 0x28 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of unserviced rollover interupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1980++0x03 line.long 0x00 "MCANSS_ECC_EOI,ECC EOI End Of Interrupt for ECC interrupt" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 8. "ECC_EOI,ECC EOI" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED,Reserved" rgroup.long 0x1A00++0x07 line.long 0x00 "MCAN_CREL,Core Release Register Release dependent constant (version + date)" bitfld.long 0x00 28.--31. "REL,Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "STEP,Step of Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "SUBSTEP,Sub-step of Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded" newline hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded" line.long 0x04 "MCAN_ENDN,Endian Register Constant 0x8765 4321" group.long 0x1A0C++0x23 line.long 0x00 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 23. "TDC,Transmitter Delay Compensation" "Transmitter Delay Compensation disabled,Transmitter Delay Compensation enabled" newline rbitfld.long 0x00 21.--22. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 16.--20. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0x00-0x1F)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--7. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0x0-0xF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0x0-0xF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "MCAN_TEST,Test Register Test mode selection" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 7. "RX,Receive Pin Monitors the actual value of the mcan_rx pin" "The CAN bus is dominant (mcan_rx = '0'),The CAN bus is recessive (mcan_rx = '1')" newline bitfld.long 0x04 5.--6. "TX,Control of Transmit Pin" "Reset value the mcan_tx pin controlled by the..,Sample Point can be monitored at the mcan_tx pin,Dominant ('0') level at the mcan_tx pin,Recessive ('1') at the mcan_tx pin" newline bitfld.long 0x04 4. "LBCK,Loop Back Mode" "Reset value Loop Back Mode is disabled,Loop Back Mode is enabled" newline rbitfld.long 0x04 0.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM" hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x08 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value" newline hexmask.long.byte 0x08 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter" line.long 0x0C "MCAN_CCCR,CC Control Register Operation mode configuration" hexmask.long.tbyte 0x0C 15.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame" "Transmit pause disabled,Transmit pause enabled" newline bitfld.long 0x0C 13. "EFBI,Edge Filtering during Bus Integration" "Edge filtering disabled,Two consecutive dominant t" newline bitfld.long 0x0C 12. "PXHD,Protocol Exception Handling Disable" "Protocol exception handling enabled,Protocol exception handling disabled" newline rbitfld.long 0x0C 10.--11. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 9. "BRSE,Bit Rate Switch Enable" "Bit rate switching for transmissions disabled,Bit rate switching for transmissions enabled" newline bitfld.long 0x0C 8. "FDOE,FD Operation Enable" "FD operation disabled,FD operation enabled" newline bitfld.long 0x0C 7. "TEST,Test Mode Enable" "Normal operation,Test Mode" newline bitfld.long 0x0C 6. "DAR,Disable Automatic Retransmission" "Automatic retransmission of messages not..,Automatic retransmission disabled" newline bitfld.long 0x0C 5. "MON,Bus Monitoring Mode" "Bus Monitoring Mode is disabled,Bus Monitoring Mode is enabled" newline bitfld.long 0x0C 4. "CSR,Clock Stop Request" "No clock stop is requested,Clock stop requested" newline bitfld.long 0x0C 3. "CSA,Clock Stop Acknowledge" "No clock stop acknowledged,The MCAN module may be set in power down by.." newline bitfld.long 0x0C 2. "ASM,Restricted Operation Mode" "Normal CAN operation,Restricted Operation Mode active" newline bitfld.long 0x0C 1. "CCE,Configuration Change Enable" "The Host CPU has no write access to the..,The Host CPU has write access to the protected.." newline bitfld.long 0x0C 0. "INIT,Initialization" "Normal Operation,Initialization is started" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing" hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0x00-0x7F)" newline hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (0x01-0xFF)" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0x00-0x7F)" line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 16.--19. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0x0-0xF)]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "Timestamp counter value always 0x0000,Timestamp counter value incremented according to,External timestamp counter value used,Same as '00'" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx)" line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter)" newline hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to" "Continuous operation,Timeout controlled by Tx Event FIFO,Timeout controlled by Rx FIFO 0,Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "Timeout Counter disabled,Timeout Counter enabled" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter" hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of" rgroup.long 0x1A40++0x0B line.long 0x00 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented" newline bitfld.long 0x00 15. "RP,Receive Error Passive" "The Receive Error Counter is below the error..,The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127" newline hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255" line.long 0x04 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value" hexmask.long.word 0x04 23.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x04 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the mcan_tx to mcan_rx pins and" newline bitfld.long 0x04 15. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 14. "PXE,Protocol Exception Event" "No protocol exception event occurred since last..,Protocol exception event occurred" newline bitfld.long 0x04 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering" "Since this bit was reset by the Host CPU no CAN..,Message in CAN FD format with FDF flag set has.." newline bitfld.long 0x04 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with" "Last received CAN FD message did not have its..,Last received CAN FD message had its BRS flag set" newline bitfld.long 0x04 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with" "Last received CAN FD message did not have its..,Last received CAN FD message had its ESI flag set" newline bitfld.long 0x04 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 7. "BO,Bus_Off Status" "The MCAN module is not Bus_Off,The MCAN module is in Bus_Off state" newline bitfld.long 0x04 6. "EW,Warning Status" "Both error counters are below the Error_Warning..,At least one of error counter has reached the.." newline bitfld.long 0x04 5. "EP,Error Passive" "The MCAN module is in the Error_Active state,The MCAN module is in the Error_Passive state" newline bitfld.long 0x04 3.--4. "ACT,Activity Monitors the module's CAN communication state" "Synchronizing - node is synchronizing on CAN..,Idle - node is neither receiver nor transmitter,Receiver - node is operating as receiver,Transmitter - node is operating as transmitter" newline bitfld.long 0x04 0.--2. "LEC,Last Error Code" "No Error,Stuff Error,Form Error,AckError,Bit1Error,Bit0Error,CRCError,NoChange" line.long 0x08 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length" hexmask.long.tbyte 0x08 15.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x08 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the mcan_rx and mcan_tx pins and the secondary sample point" newline rbitfld.long 0x08 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x08 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the mcan_rx pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment" group.long 0x1A50++0x0F line.long 0x00 "MCAN_IR,Interrupt RegisterThe flags are set when one of the listed conditions is detected (edge-sensitive)" rbitfld.long 0x00 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 29. "ARA,Access to Reserved Address" "No access to reserved address occurred,Access to reserved address occurred" newline bitfld.long 0x00 28. "PED,Protocol Error in Data Phase" "No protocol error in data phase,Protocol error in data phase detected (" newline bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "No protocol error in arbitration phase,Protocol error in arbitration phase detected (" newline bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "No Message RAM Watchdog event occurred,Message RAM Watchdog event due to missing READY" newline bitfld.long 0x00 25. "BO,Bus_Off Status" "Bus_Off status unchanged,Bus_Off status changed" newline bitfld.long 0x00 24. "EW,Warning Status" "Error_Warning status unchanged,Error_Warning status changed" newline bitfld.long 0x00 23. "EP,Error Passive" "Error_Passive status unchanged,Error_Passive status changed" newline bitfld.long 0x00 22. "ELO,Error Logging Overflow" "CAN Error Logging Counter did not overflow,Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x00 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected" "No bit error detected when reading from Message..,Bit error detected uncorrected (example: parity.." newline bitfld.long 0x00 20. "BEC,Bit Error Corrected Message RAM bit error detected and corrected" "No bit error detected when reading from Message..,Bit error detected and corrected (example: ECC)" newline bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer" "No Rx Buffer updated,At least one received message stored into an Rx.." newline bitfld.long 0x00 18. "TOO,Timeout Occurred" "No timeout,Timeout reached" newline bitfld.long 0x00 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received" "No Message RAM access failure occurred,Message RAM access failure occurred" newline bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "No timestamp counter wrap-around,Timestamp counter wrapped around" newline bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "No Tx Event FIFO element lost,Tx Event FIFO element lost also set after write.." newline bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "Tx Event FIFO not full,Tx Event FIFO full" newline bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "Tx Event FIFO fill level below watermark,Tx Event FIFO fill level reached watermark" newline bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "Tx Event FIFO unchanged,Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "Tx FIFO non-empty,Tx FIFO empty" newline bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "No transmission cancellation finished,Transmission cancellation finished" newline bitfld.long 0x00 9. "TC,Transmission Completed" "No transmission completed,Transmission completed" newline bitfld.long 0x00 8. "HPM,High Priority Message" "No high priority message received,High priority message received" newline bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "No Rx FIFO 1 message lost,Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "Rx FIFO 1 not full,Rx FIFO 1 full" newline bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "Rx FIFO 1 fill level below watermark,Rx FIFO 1 fill level reached watermark" newline bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "No new message written to Rx FIFO 1,New message written to Rx FIFO 1" newline bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "No Rx FIFO 0 message lost,Rx FIFO 0 message lost also set after write.." newline bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "Rx FIFO 0 not full,Rx FIFO 0 full" newline bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "Rx FIFO 0 fill level below watermark,Rx FIFO 0 fill level reached watermark" newline bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "No new message written to Rx FIFO 0,New message written to Rx FIFO 0" line.long 0x04 "MCAN_IE,Interrupt EnableThe settings in the Interrupt Enable register determine which status changes in the Interrupt Register are signalled on an interrupt line" rbitfld.long 0x04 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x04 29. "ARAE,Access to Reserved Address Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 28. "PEDE,Protocol Error in Data Phase Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 27. "PEAE,Protocol Error in Arbitration Phase Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 26. "WDIE,Watchdog Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 25. "BOE,Bus_Off Status Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 24. "EWE,Warning Status Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 23. "EPE,Error Passive Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 22. "ELOE,Error Logging Overflow Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 20. "BECE,Bit Error Corrected Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" newline bitfld.long 0x04 18. "TOOE,Timeout Occurred Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 16. "TSWE,Timestamp Wraparound Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 11. "TFEE,Tx FIFO Empty Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 9. "TCE,Transmission Completed Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 8. "HPME,High Priority Message Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "Interrupt disabled,Interrupt enabled" line.long 0x08 "MCAN_ILS,Interrupt Line SelectThe Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines" rbitfld.long 0x08 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x08 29. "ARAL,Access to Reserved Address Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 28. "PEDL,Protocol Error in Data Phase Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 27. "PEAL,Protocol Error in Arbitration Phase Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 26. "WDIL,Watchdog Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 25. "BOL,Bus_Off Status Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 24. "EWL,Warning Status Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 23. "EPL,Error Passive Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 22. "ELOL,Error Logging Overflow Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 21. "BEUL,Bit Error Uncorrected Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 20. "BECL,Bit Error Corrected Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 18. "TOOL,Timeout Occurred Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 17. "MRAFL,Message RAM Access Failure Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 16. "TSWL,Timestamp Wraparound Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 11. "TFEL,Tx FIFO Empty Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 9. "TCL,Transmission Completed Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 8. "HPML,High Priority Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" line.long 0x0C "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1" hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 1. "EINT1,Enable Interrupt Line 1" "Interrupt line INT1 disabled,Interrupt line INT1 enabled" newline bitfld.long 0x0C 0. "EINT0,Enable Interrupt Line 0" "Interrupt line INT0 disabled,Interrupt line INT0 enabled" group.long 0x1A80++0x0B line.long 0x00 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames" hexmask.long 0x00 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated" "Accept in Rx..,Accept in Rx..,Reject,Reject" newline bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated" "Accept in Rx..,Accept in Rx..,Reject,Reject" newline bitfld.long 0x00 1. "RRFS,Reject Remote Frames Standard" "Filter remote frames with 11-bit standard IDs,Reject all remote frames with 11-bit standard IDs" newline bitfld.long 0x00 0. "RRFE,Reject Remote Frames Extended" "Filter remote frames with 29-bit extended IDs,Reject all remote frames with 29-bit extended IDs" line.long 0x04 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x04 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x04 16.--23. 1. "LSS,List Size Standard" newline hexmask.long.word 0x04 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" newline rbitfld.long 0x04 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x08 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list" hexmask.long.word 0x08 23.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x08 16.--22. 1. "LSE,List Size Extended" newline hexmask.long.word 0x08 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" newline rbitfld.long 0x08 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x1A90++0x57 line.long 0x00 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939" rbitfld.long 0x00 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame" line.long 0x04 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 15. "FLST,Filter List Indicates the filter list of the matching filter element" "Standard Filter List,Extended Filter List" newline hexmask.long.byte 0x04 8.--14. 1. "FIDX,Filter Index Index of matching filter element" newline bitfld.long 0x04 6.--7. "MSI,Message Storage Indicator" "No FIFO selected,FIFO message lost,Message stored in FIFO 0,Message stored in FIFO 1" newline bitfld.long 0x04 0.--5. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x08 31. "ND31,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 30. "ND30,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 29. "ND29,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 28. "ND28,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 27. "ND27,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 26. "ND26,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 25. "ND25,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 24. "ND24,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 23. "ND23,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 22. "ND22,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 21. "ND21,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 20. "ND20,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 19. "ND19,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 18. "ND18,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 17. "ND17,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 16. "ND16,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 15. "ND15,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 14. "ND14,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 13. "ND13,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 12. "ND12,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 11. "ND11,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 10. "ND10,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 9. "ND9,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 8. "ND8,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 7. "ND7,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 6. "ND6,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 5. "ND5,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 4. "ND4,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 3. "ND3,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 2. "ND2,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 1. "ND1,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 0. "ND0,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" line.long 0x0C "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x0C 31. "ND63,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 30. "ND62,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 29. "ND61,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 28. "ND60,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 27. "ND59,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 26. "ND58,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 25. "ND57,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 24. "ND56,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 23. "ND55,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 22. "ND54,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 21. "ND53,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 20. "ND52,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 19. "ND51,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 18. "ND50,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 17. "ND49,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 16. "ND48,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 15. "ND47,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 14. "ND46,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 13. "ND45,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 12. "ND44,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 11. "ND43,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 10. "ND42,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 9. "ND41,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 8. "ND40,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 7. "ND39,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 6. "ND38,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 5. "ND37,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 4. "ND36,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 3. "ND35,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 2. "ND34,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 1. "ND33,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 0. "ND32,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" line.long 0x10 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x10 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0x0: FIFO 0 blocking mode 0x1: FIFO 0 overwrite mode" "FIFO 0 blocking mode,FIFO 0 overwrite mode" newline hexmask.long.byte 0x10 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline rbitfld.long 0x10 23. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x10 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" newline rbitfld.long 0x10 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x14 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x14 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x14 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag" "No Rx FIFO 0 message lost,Rx FIFO 0 message lost also set after write.." newline bitfld.long 0x14 24. "F0F,Rx FIFO 0 Full" "Rx FIFO 0 not full,Rx FIFO 0 full" newline bitfld.long 0x14 22.--23. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x14 16.--21. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x14 14.--15. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x14 8.--13. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x14 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x14 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64" line.long 0x18 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long 0x18 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x18 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x1C 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM Also used to reference debug messages A B C" newline rbitfld.long 0x1C 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x20 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x20 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0x0: FIFO 1 blocking mode 0x1: FIFO 1 overwrite mode" "FIFO 1 blocking mode,FIFO 1 overwrite mode" newline hexmask.long.byte 0x20 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline rbitfld.long 0x20 23. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x20 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" newline rbitfld.long 0x20 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x24 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x24 30.--31. "DMS,Debug Message Status" "Idle state wait for reception of debug messages..,Debug message A received,Debug messages A B received,Debug messages A B C received" newline bitfld.long 0x24 26.--29. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x24 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag" "No Rx FIFO 1 message lost,Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x24 24. "F1F,Rx FIFO 1 Full" "Rx FIFO 1 not full,Rx FIFO 1 full" newline bitfld.long 0x24 22.--23. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x24 16.--21. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x24 14.--15. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x24 8.--13. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x24 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x24 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64" line.long 0x28 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long 0x28 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x28 0.--5. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "MCAN_RXESC,Rx Buffer / FIFO Element Size Configuration Configure data field size for storage of accepted frames" hexmask.long.tbyte 0x2C 11.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 8.--10. "RBDS,Rx Buffer Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field" newline rbitfld.long 0x2C 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field" newline rbitfld.long 0x2C 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field" line.long 0x30 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" rbitfld.long 0x30 31. "RESERVED,Reserved" "0,1" newline bitfld.long 0x30 30. "TFQM,Tx FIFO/Queue Mode" "Tx FIFO operation,Tx Queue operation" newline bitfld.long 0x30 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x30 22.--23. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x30 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x30 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see" newline rbitfld.long 0x30 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x34 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" hexmask.long.word 0x34 22.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x34 21. "TFQF,Tx FIFO/Queue Full" "Tx FIFO/Queue not full,Tx FIFO/Queue full" newline bitfld.long 0x34 16.--20. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x34 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 8.--12. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x34 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x34 0.--5. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission" hexmask.long 0x38 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x38 0.--2. "TBDS,Tx Buffer Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field" line.long 0x3C "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request" bitfld.long 0x3C 31. "TRP31,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 30. "TRP30,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 29. "TRP29,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 28. "TRP28,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 27. "TRP27,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 26. "TRP26,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 25. "TRP25,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 24. "TRP24,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 23. "TRP23,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 22. "TRP22,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 21. "TRP21,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 20. "TRP20,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 19. "TRP19,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 18. "TRP18,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 17. "TRP17,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 16. "TRP16,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 15. "TRP15,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 14. "TRP14,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 13. "TRP13,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 12. "TRP12,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 11. "TRP11,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 10. "TRP10,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 9. "TRP9,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 8. "TRP8,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 7. "TRP7,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 6. "TRP6,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 5. "TRP5,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 4. "TRP4,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 3. "TRP3,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 2. "TRP2,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 1. "TRP1,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 0. "TRP0,Transmission Request Pending" "No transmission request pending,Transmission request pending" line.long 0x40 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests" bitfld.long 0x40 31. "AR31,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 30. "AR30,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 29. "AR29,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 28. "AR28,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 27. "AR27,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 26. "AR26,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 25. "AR25,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 24. "AR24,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 23. "AR23,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 22. "AR22,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 21. "AR21,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 20. "AR20,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 19. "AR19,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 18. "AR18,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 17. "AR17,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 16. "AR16,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 15. "AR15,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 14. "AR14,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 13. "AR13,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 12. "AR12,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 11. "AR11,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 10. "AR10,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 9. "AR9,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 8. "AR8,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 7. "AR7,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 6. "AR6,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 5. "AR5,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 4. "AR4,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 3. "AR3,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 2. "AR2,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 1. "AR1,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 0. "AR0,Add Request" "No transmission request added,Transmission requested added" line.long 0x44 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions" bitfld.long 0x44 31. "CR31,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 30. "CR30,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 29. "CR29,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 28. "CR28,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 27. "CR27,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 26. "CR26,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 25. "CR25,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 24. "CR24,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 23. "CR23,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 22. "CR22,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 21. "CR21,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 20. "CR20,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 19. "CR19,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 18. "CR18,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 17. "CR17,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 16. "CR16,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 15. "CR15,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 14. "CR14,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 13. "CR13,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 12. "CR12,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 11. "CR11,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 10. "CR10,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 9. "CR9,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 8. "CR8,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 7. "CR7,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 6. "CR6,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 5. "CR5,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 4. "CR4,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 3. "CR3,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 2. "CR2,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 1. "CR1,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 0. "CR0,Cancellation Request" "No cancellation pending,Cancellation pending" line.long 0x48 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared" bitfld.long 0x48 31. "TO31,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 30. "TO30,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 29. "TO29,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 28. "TO28,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 27. "TO27,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 26. "TO26,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 25. "TO25,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 24. "TO24,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 23. "TO23,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 22. "TO22,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 21. "TO21,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 20. "TO20,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 19. "TO19,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 18. "TO18,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 17. "TO17,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 16. "TO16,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 15. "TO15,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 14. "TO14,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 13. "TO13,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 12. "TO12,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 11. "TO11,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 10. "TO10,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 9. "TO9,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 8. "TO8,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 7. "TO7,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 6. "TO6,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 5. "TO5,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 4. "TO4,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 3. "TO3,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 2. "TO2,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 1. "TO1,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 0. "TO0,Transmission Occurred" "No transmission occurred,Transmission occurred" line.long 0x4C "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4C 31. "CF31,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 30. "CF30,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 29. "CF29,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 28. "CF28,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 27. "CF27,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 26. "CF26,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 25. "CF25,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 24. "CF24,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 23. "CF23,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 22. "CF22,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 21. "CF21,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 20. "CF20,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 19. "CF19,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 18. "CF18,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 17. "CF17,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 16. "CF16,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 15. "CF15,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 14. "CF14,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 13. "CF13,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 12. "CF12,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 11. "CF11,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 10. "CF10,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 9. "CF9,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 8. "CF8,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 7. "CF7,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 6. "CF6,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 5. "CF5,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 4. "CF4,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 3. "CF3,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 2. "CF2,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 1. "CF1,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 0. "CF0,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" line.long 0x50 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers" bitfld.long 0x50 31. "TIE31,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 30. "TIE30,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 29. "TIE29,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 28. "TIE28,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 27. "TIE27,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 26. "TIE26,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 25. "TIE25,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 24. "TIE24,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 23. "TIE23,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 22. "TIE22,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 21. "TIE21,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 20. "TIE20,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 19. "TIE19,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 18. "TIE18,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 17. "TIE17,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 16. "TIE16,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 15. "TIE15,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 14. "TIE14,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 13. "TIE13,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 12. "TIE12,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 11. "TIE11,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 10. "TIE10,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 9. "TIE9,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 8. "TIE8,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 7. "TIE7,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 6. "TIE6,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 5. "TIE5,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 4. "TIE4,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 3. "TIE3,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 2. "TIE2,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 1. "TIE1,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 0. "TIE0,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" line.long 0x54 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x54 31. "CFIE31,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 30. "CFIE30,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 29. "CFIE29,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 28. "CFIE28,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 27. "CFIE27,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 26. "CFIE26,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 25. "CFIE25,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 24. "CFIE24,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 23. "CFIE23,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 22. "CFIE22,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 21. "CFIE21,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 20. "CFIE20,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 19. "CFIE19,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 18. "CFIE18,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 17. "CFIE17,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 16. "CFIE16,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 15. "CFIE15,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 14. "CFIE14,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 13. "CFIE13,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 12. "CFIE12,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 11. "CFIE11,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 10. "CFIE10,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 9. "CFIE9,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 8. "CFIE8,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 7. "CFIE7,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 6. "CFIE6,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 5. "CFIE5,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 4. "CFIE4,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 3. "CFIE3,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 2. "CFIE2,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 1. "CFIE1,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 0. "CFIE0,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" group.long 0x1AF0++0x0B line.long 0x00 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address" rbitfld.long 0x00 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 22.--23. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" newline rbitfld.long 0x00 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x04 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x04 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 25. "TEFL,This bit is a copy of interrupt flag" "No Tx Event FIFO element lost,Tx Event FIFO element lost also set after write.." newline bitfld.long 0x04 24. "EFF,Event FIFO Full" "Tx Event FIFO not full,Tx Event FIFO full" newline bitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 16.--20. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 8.--12. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x04 0.--5. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x08 0.--4. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x1C00++0x03 line.long 0x00 "MCANSS_ECC_AGGR_REVISION,Aggregator Revision Register Revision parameters" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID" newline bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C08++0x1F line.long 0x00 "MCANSS_ECC_VECTOR,ECC Vector Register ECC Vector Register" hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read is complete" "0,1" newline hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x00 15. "RD_SVBUS,Write '1' to trigger a" "0,1" newline rbitfld.long 0x00 11.--14. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" line.long 0x04 "MCANSS_ECC_MISC_STATUS,Misc Status Misc Status" hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" line.long 0x08 "MCANSS_ECC_WRAP_REVISION,ECC Wrapper Revision Register Revision parameters" bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x08 28.--29. "BU,Business Unit" "0,1,2,3" newline hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID" newline bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "MCANSS_ECC_CONTROL,ECC Control ECC Control Register" hexmask.long 0x0C 7.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1" newline bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1" newline bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1" newline bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1" newline bitfld.long 0x0C 2. "ENABLE_RMW,Enable RMW" "0,1" newline bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1" newline bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1" line.long 0x10 "MCANSS_ECC_ERR_CTRL1,ECC Error Control1 Register ECC Error Control1 Register" hexmask.long.word 0x10 16.--31. 1. "ECC_BIT1,Data bit that needs to be flipped when FORCE_SEC is set" newline hexmask.long.word 0x10 0.--15. 1. "ECC_ROW,Row address where single or double-bit error needs to be applied" line.long 0x14 "MCANSS_ECC_ERR_CTRL2,ECC Error Control2 Register ECC Error Control2 Register" hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x14 0.--15. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced" line.long 0x18 "MCANSS_ECC_ERR_STAT1,ECC Error Status1 Register ECC Error Status1 Register" hexmask.long.word 0x18 16.--31. 1. "ECC_ROW,Row address where the single or double-bit error has occurred" newline rbitfld.long 0x18 10.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x18 9. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1" newline bitfld.long 0x18 8. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1" newline rbitfld.long 0x18 2.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x18 1. "ECC_DED,Level Double Bit Error Status" "0,1" newline bitfld.long 0x18 0. "ECC_SEC,Level Single Bit Error Status" "0,1" line.long 0x1C "MCANSS_ECC_ERR_STAT2,ECC Error Status2 Register ECC Error Status2 Register" hexmask.long.word 0x1C 16.--31. 1. "ECC_BIT2,Data bit that corresponds to the double-bit error" newline hexmask.long.word 0x1C 0.--15. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error" group.long 0x1C3C++0x07 line.long 0x00 "MCANSS_ECC_SEC_EOI_REG,EOI Register EOI Register" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1" line.long 0x04 "MCANSS_ECC_SEC_STATUS_REG0,Interrupt Status Register 0 Interrupt Status Register 0" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x1C80++0x03 line.long 0x00 "MCANSS_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0 Interrupt Enable Set Register 0" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for MSGMEM_PEND" "0,1" group.long 0x1CC0++0x03 line.long 0x00 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0 Interrupt Enable Clear Register 0" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for MSGMEM_PEND" "0,1" group.long 0x1D3C++0x07 line.long 0x00 "MCANSS_ECC_DED_EOI_REG,EOI Register EOI Register" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1" line.long 0x04 "MCANSS_ECC_DED_STATUS_REG0,Interrupt Status Register 0 Interrupt Status Register 0" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x1D80++0x03 line.long 0x00 "MCANSS_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0 Interrupt Enable Set Register 0" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for MSGMEM_PEND" "0,1" group.long 0x1DC0++0x03 line.long 0x00 "MCANSS_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0 Interrupt Enable Clear Register 0" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for MSGMEM_PEND" "0,1" width 0x0B tree.end tree "MCAN_TARG" base ad:0x48482000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP1_AFIFO" base ad:0x48461000 group.long 0x00++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" abitfld.long 0x00 8.--15. "WNUMEVT,Write word count (32-bit) to generate TX event to host" "0x40=3 to 64 words currently..,0xFF=Reserved" abitfld.long 0x00 0.--7. "WNUMDMA,Write word count (32-bit words)" "0x10=3 to 16 words,0xFF=Reserved" line.long 0x04 "WFIFOSTS,The Write FIFO status register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently..,0xFF=Reserved" line.long 0x08 "RFIFOCTL,The Read FIFO control register" hexmask.long.word 0x08 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" abitfld.long 0x08 8.--15. "RNUMEVT,Read word count (32-bit) to generate RX event to host" "0x40=3 to 64 words..,0xFF=Reserved" abitfld.long 0x08 0.--7. "RNUMDMA,Read word count (32-bit words)" "0x10=3-16 words,0xFF=Reserved" line.long 0x0C "RFIFOSTS,The Read FIFO status register" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently..,0xFF=Reserved" width 0x0B tree.end tree "MCASP1_CFG" base ad:0x48460000 rgroup.long 0x00++0x07 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x00 28.--29. "RESV,Reserved" "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. "FUNCTION,MCASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "0,1,2,3" newline bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PWRIDLESYSCONFIG,Power idle module configuration register" hexmask.long 0x04 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2.--5. "OTHER,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--1. "IDLE_MODE," "?,No-idle mode,Smart-idle mode - default..,Reserved" group.long 0x10++0x0F line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" newline bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x00 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x04 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x04 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x04 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" newline bitfld.long 0x04 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" newline bitfld.long 0x04 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" newline bitfld.long 0x04 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" newline bitfld.long 0x04 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" bitfld.long 0x04 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" newline bitfld.long 0x04 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" newline bitfld.long 0x04 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x08 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x08 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" newline bitfld.long 0x08 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1" "ACLKR_0,ACLKR_1" bitfld.long 0x08 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" newline bitfld.long 0x08 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" bitfld.long 0x08 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x08 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x08 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" newline bitfld.long 0x08 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" newline bitfld.long 0x08 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" bitfld.long 0x08 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" newline bitfld.long 0x08 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" newline bitfld.long 0x08 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" newline bitfld.long 0x08 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" newline bitfld.long 0x08 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" bitfld.long 0x08 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" newline bitfld.long 0x08 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x0C "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins" bitfld.long 0x0C 31. "AFSR,Logic level on AFSR pin (device level: mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x0C 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 29. "ACLKR,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" bitfld.long 0x0C 28. "AFSX,Logic level on AFSX pin (device level: mcaspi_fsx signal)" "AFSX_0,AFSX_1" newline bitfld.long 0x0C 27. "AHCLKX,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" bitfld.long 0x0C 26. "ACLKX,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x0C 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x0C 15. "AXR15,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" newline bitfld.long 0x0C 14. "AXR14,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x0C 13. "AXR13,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" newline bitfld.long 0x0C 12. "AXR12,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x0C 11. "AXR11,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x0C 10. "AXR10,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x0C 9. "AXR9,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" newline bitfld.long 0x0C 8. "AXR8,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x0C 7. "AXR7,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" newline bitfld.long 0x0C 6. "AXR6,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" bitfld.long 0x0C 5. "AXR5,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" newline bitfld.long 0x0C 4. "AXR4,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x0C 3. "AXR3,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" newline bitfld.long 0x0C 2. "AXR2,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x0C 1. "AXR1,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x0C 0. "AXR0,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x1C++0x07 line.long 0x00 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" newline bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x00 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x04 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x04 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x04 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x04 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x04 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x04 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x04 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x04 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x04 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x04 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x44++0x0F line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit" "XFRST_0,XFRST_1" newline bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bitAXR[n] pin state : If[n] = 0 and [n] = 1 the corresponding serializer [n] drives the AXR[n] pin to the state specified for inactive time slot" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" newline bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" line.long 0x08 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode" hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects between and loopback modes" "IOLBEN_0,IOLBEN_1" newline bitfld.long 0x08 2.--3. "MODE,Loopback generator mode bits.0x2 " "MODE_0,MODE_1,?,?" bitfld.long 0x08 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" newline bitfld.long 0x08 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" line.long 0x0C "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the MCASP" hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" newline bitfld.long 0x0C 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" bitfld.long 0x0C 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 0. "DITEN,DIT mode enable bit" "DITEN_0,DITEN_1" group.long 0x60++0x2F line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED," rbitfld.long 0x00 12. "XFRST,Frame sync generator reset" "XFRST_0,XFRST_1" newline rbitfld.long 0x00 11. "XSMRST,XMT state machine reset" "XSMRST_0,XSMRST_1" rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear" "XSRCLR_0,XSRCLR_1" newline rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "RFRST,Frame sync generator reset" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,RCV state machine reset" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" line.long 0x08 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" hexmask.long.word 0x08 18.--31. 1. "RESERVED," bitfld.long 0x08 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n]" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" newline bitfld.long 0x08 15. "RRVRS,Receive serial bitstream order" "RRVRS_0,RRVRS_1" bitfld.long 0x08 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" newline bitfld.long 0x08 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x08 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" newline bitfld.long 0x08 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" bitfld.long 0x08 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" line.long 0x0C "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," abitfld.long 0x0C 7.--15. "RMOD,Receive frame sync mode select" "0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x1FF=Reserved" newline bitfld.long 0x0C 5.--6. "RESERVED," "0,1,2,3" bitfld.long 0x0C 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" newline bitfld.long 0x0C 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x0C 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" newline bitfld.long 0x0C 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" line.long 0x10 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" hexmask.long.word 0x10 21.--31. 1. "RESERVED," bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" hexmask.long.byte 0x10 8.--15. 1. "RESERVED," newline bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" bitfld.long 0x10 6. "RESERVED," "0,1" newline bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" bitfld.long 0x10 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" hexmask.long.word 0x14 21.--31. 1. "RESERVED," bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" bitfld.long 0x14 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" bitfld.long 0x14 12.--13. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to" line.long 0x18 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" line.long 0x1C "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT)" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit" "RSTAFRM_0,RSTAFRM_1" newline bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "RDATA,Receive data-ready interrupt enable bit" "RDATA_0,RDATA_1" newline bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit" "RLAST_0,RLAST_1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit" "ROVRN_0,ROVRN_1" line.long 0x20 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED," bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" newline bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" newline bitfld.long 0x20 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" bitfld.long 0x20 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" newline bitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" newline bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" line.long 0x24 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED," hexmask.long.word 0x24 0.--8. 1. "RSLOTCNT," line.long 0x28 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "RCNT," hexmask.long.byte 0x28 16.--23. 1. "RMAX," newline hexmask.long.byte 0x28 8.--15. 1. "RMIN," bitfld.long 0x28 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 0.--3. "RPS,Receive clock check prescaler value.0x9" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" line.long 0x2C "MCASP_REVTCTL,Receiver DMA event control register" hexmask.long 0x2C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0xA0++0x33 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED," bitfld.long 0x00 12. "XFRST,Frame sync generator reset" "XFRST_0,XFRST_1" newline bitfld.long 0x00 11. "XSMRST,XMT state machine reset" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,XMT serializer clear" "XSRCLR_0,XSRCLR_1" newline bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x00 4. "RFRST,Frame sync generator reset" "RFRST_0,RFRST_1" newline rbitfld.long 0x00 3. "RSMRST,RCV state machine reset" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear" "RSRCLKR_0,RSRCLKR_1" newline rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" line.long 0x08 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 16.--17. "XDATDLY,Transmit sync bit delay" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" newline bitfld.long 0x08 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" bitfld.long 0x08 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" newline bitfld.long 0x08 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" newline bitfld.long 0x08 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" bitfld.long 0x08 0.--2. "XROT,Right-rotation value for transmit rotate right format unit" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" line.long 0x0C "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,Reserved" abitfld.long 0x0C 7.--15. "XMOD,Transmit frame-sync mode select bits" "0x000=Burst mode,0x001=Reserved,0x002=2-slot TDM mode (),0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x180=384-slot DIT mode All other: Reserved" newline bitfld.long 0x0C 5.--6. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0C 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" newline bitfld.long 0x0C 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0C 1. "FSXM,Transmit frame-sync generation select bit" "FSXM_0,FSXM_1" newline bitfld.long 0x0C 0. "FSXP,Transmit frame-sync polarity select bit" "FSXP_0,FSXP_1" line.long 0x10 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" hexmask.long.word 0x10 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" hexmask.long.byte 0x10 8.--15. 1. "RESERVED," newline bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" bitfld.long 0x10 6. "ASYNC,Transmit operation asynchronous enable bit" "ASYNC_0,ASYNC_1" newline bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit" "CLKXM_0,CLKXM_1" bitfld.long 0x10 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "Divide-by-1,Divide-by-2 0x2 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide-by-3 to divide-by-32" line.long 0x14 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" hexmask.long.word 0x14 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit" "HCLKXM_0,HCLKXM_1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" bitfld.long 0x14 12.--13. "RESERVED,Reserved" "0,1,2,3" newline abitfld.long 0x14 0.--11. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" "0x000=Divide-by-1,0x001=Divide-by-2 0x2 to,0xFFF=Divide-by-3 to divide-by-4096" line.long 0x18 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" line.long 0x1C "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit" "XSTAFRM_0,XSTAFRM_1" newline bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data-ready interrupt enable bit" "XDATA_0,XDATA_1" newline bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit" "XLAST_0,XLAST_1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit" "XUNDRN_0,XUNDRN_1" line.long 0x20 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the MCASP logic has priority and the flag remains set" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" newline bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" newline bitfld.long 0x20 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" newline bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" line.long 0x24 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 0.--8. 1. "XSLOTCNT,Current transmit time slot count" line.long 0x28 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x28 16.--23. 1. "XMAX,0x0 to" newline hexmask.long.byte 0x28 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x28 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 0.--3. "XPS,Transmit clock check prescaler value" "MCASP interface clock divided by 1,MCASP interface clock divided by 2,MCASP interface clock divided by 4,MCASP interface clock divided by 8,MCASP interface clock divided by 16,MCASP interface clock divided by 32,MCASP interface clock divided by 64,MCASP interface clock divided by 128,MCASP interface clock divided by 256 0x9 to,?,?,?,?,?,?,Reserved" line.long 0x2C "MCASP_XEVTCTL,Transmitter DMA event control register" hexmask.long 0x2C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" line.long 0x30 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" hexmask.long 0x30 1.--31. 1. "RESERVED," bitfld.long 0x30 0. "ENABLE,One-shot clock adjust enable" "ENABLE_0,ENABLE_1" group.long 0x100++0x5F line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x04 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x08 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x0C "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x10 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x14 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x18 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x1C "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x20 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x24 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x28 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x2C "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x30 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x34 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x38 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x3C "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x40 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x44 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x48 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x4C "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x50 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x54 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x58 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x5C "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x180++0x3F line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" hexmask.long 0x00 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x04 "MCASP_XRSRCTLn_1,Serializer n control register" hexmask.long 0x04 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x04 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x04 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x04 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x08 "MCASP_XRSRCTLn_2,Serializer n control register" hexmask.long 0x08 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x08 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x08 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x08 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x08 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x0C "MCASP_XRSRCTLn_3,Serializer n control register" hexmask.long 0x0C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0C 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x0C 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x0C 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x0C 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x10 "MCASP_XRSRCTLn_4,Serializer n control register" hexmask.long 0x10 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x14 "MCASP_XRSRCTLn_5,Serializer n control register" hexmask.long 0x14 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x18 "MCASP_XRSRCTLn_6,Serializer n control register" hexmask.long 0x18 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x18 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x18 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x18 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x18 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x1C "MCASP_XRSRCTLn_7,Serializer n control register" hexmask.long 0x1C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x1C 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x1C 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x1C 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x1C 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x20 "MCASP_XRSRCTLn_8,Serializer n control register" hexmask.long 0x20 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x20 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x20 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x20 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x20 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x24 "MCASP_XRSRCTLn_9,Serializer n control register" hexmask.long 0x24 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x24 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x24 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x24 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x24 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x28 "MCASP_XRSRCTLn_10,Serializer n control register" hexmask.long 0x28 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x28 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x28 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x28 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x28 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x2C "MCASP_XRSRCTLn_11,Serializer n control register" hexmask.long 0x2C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x2C 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x2C 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x2C 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x2C 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x30 "MCASP_XRSRCTLn_12,Serializer n control register" hexmask.long 0x30 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x30 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x30 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x30 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x30 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x34 "MCASP_XRSRCTLn_13,Serializer n control register" hexmask.long 0x34 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x34 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x34 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x34 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x34 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x38 "MCASP_XRSRCTLn_14,Serializer n control register" hexmask.long 0x38 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x38 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x38 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x38 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x38 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x3C "MCASP_XRSRCTLn_15,Serializer n control register" hexmask.long 0x3C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x3C 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x3C 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x3C 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x3C 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" group.long 0x200++0x3F line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x04 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x08 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x0C "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x10 "MCASP_TXBUFn_4,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x14 "MCASP_TXBUFn_5,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x18 "MCASP_TXBUFn_6,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x1C "MCASP_TXBUFn_7,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x20 "MCASP_TXBUFn_8,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x24 "MCASP_TXBUFn_9,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x28 "MCASP_TXBUFn_10,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x2C "MCASP_TXBUFn_11,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x30 "MCASP_TXBUFn_12,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x34 "MCASP_TXBUFn_13,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x38 "MCASP_TXBUFn_14,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x3C "MCASP_TXBUFn_15,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x280++0x3F line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x04 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x08 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x0C "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x10 "MCASP_RXBUFn_4,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x14 "MCASP_RXBUFn_5,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x18 "MCASP_RXBUFn_6,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x1C "MCASP_RXBUFn_7,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x20 "MCASP_RXBUFn_8,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x24 "MCASP_RXBUFn_9,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x28 "MCASP_RXBUFn_10,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x2C "MCASP_RXBUFn_11,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x30 "MCASP_RXBUFn_12,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x34 "MCASP_RXBUFn_13,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x38 "MCASP_RXBUFn_14,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x3C "MCASP_RXBUFn_15,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" width 0x0B tree.end tree "MCASP1_DAT" base ad:0x45800000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" width 0x0B tree.end tree "MCASP1_FW" base ad:0x4A167000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "MCASP1_FW_CFG_TARG" base ad:0x4A168000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP1_TARG" base ad:0x44002F00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "MCASP2_AFIFO" base ad:0x4846D000 group.long 0x00++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" abitfld.long 0x00 8.--15. "WNUMEVT,Write word count (32-bit) to generate TX event to host" "0x40=3 to 64 words currently..,0xFF=Reserved" abitfld.long 0x00 0.--7. "WNUMDMA,Write word count (32-bit words)" "0x10=3 to 16 words,0xFF=Reserved" line.long 0x04 "WFIFOSTS,The Write FIFO status register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently..,0xFF=Reserved" line.long 0x08 "RFIFOCTL,The Read FIFO control register" hexmask.long.word 0x08 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" abitfld.long 0x08 8.--15. "RNUMEVT,Read word count (32-bit) to generate RX event to host" "0x40=3 to 64 words..,0xFF=Reserved" abitfld.long 0x08 0.--7. "RNUMDMA,Read word count (32-bit words)" "0x10=3-16 words,0xFF=Reserved" line.long 0x0C "RFIFOSTS,The Read FIFO status register" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently..,0xFF=Reserved" width 0x0B tree.end tree "MCASP2_CFG" base ad:0x4846C000 rgroup.long 0x00++0x07 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x00 28.--29. "RESV,Reserved" "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. "FUNCTION,MCASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "0,1,2,3" newline bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PWRIDLESYSCONFIG,Power idle module configuration register" hexmask.long 0x04 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2.--5. "OTHER,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--1. "IDLE_MODE," "?,No-idle mode,Smart-idle mode - default..,Reserved" group.long 0x10++0x0F line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" newline bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x00 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x04 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x04 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x04 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" newline bitfld.long 0x04 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" newline bitfld.long 0x04 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" newline bitfld.long 0x04 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" newline bitfld.long 0x04 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" bitfld.long 0x04 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" newline bitfld.long 0x04 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" newline bitfld.long 0x04 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x08 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x08 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" newline bitfld.long 0x08 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1" "ACLKR_0,ACLKR_1" bitfld.long 0x08 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" newline bitfld.long 0x08 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" bitfld.long 0x08 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x08 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x08 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" newline bitfld.long 0x08 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" newline bitfld.long 0x08 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" bitfld.long 0x08 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" newline bitfld.long 0x08 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" newline bitfld.long 0x08 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" newline bitfld.long 0x08 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" newline bitfld.long 0x08 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" bitfld.long 0x08 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" newline bitfld.long 0x08 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x0C "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins" bitfld.long 0x0C 31. "AFSR,Logic level on AFSR pin (device level: mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x0C 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 29. "ACLKR,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" bitfld.long 0x0C 28. "AFSX,Logic level on AFSX pin (device level: mcaspi_fsx signal)" "AFSX_0,AFSX_1" newline bitfld.long 0x0C 27. "AHCLKX,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" bitfld.long 0x0C 26. "ACLKX,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x0C 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x0C 15. "AXR15,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" newline bitfld.long 0x0C 14. "AXR14,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x0C 13. "AXR13,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" newline bitfld.long 0x0C 12. "AXR12,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x0C 11. "AXR11,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x0C 10. "AXR10,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x0C 9. "AXR9,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" newline bitfld.long 0x0C 8. "AXR8,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x0C 7. "AXR7,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" newline bitfld.long 0x0C 6. "AXR6,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" bitfld.long 0x0C 5. "AXR5,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" newline bitfld.long 0x0C 4. "AXR4,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x0C 3. "AXR3,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" newline bitfld.long 0x0C 2. "AXR2,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x0C 1. "AXR1,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x0C 0. "AXR0,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x1C++0x07 line.long 0x00 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" newline bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x00 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x04 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x04 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x04 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x04 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x04 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x04 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x04 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x04 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x04 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x04 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x44++0x0F line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit" "XFRST_0,XFRST_1" newline bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bitAXR[n] pin state : If[n] = 0 and [n] = 1 the corresponding serializer [n] drives the AXR[n] pin to the state specified for inactive time slot" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" newline bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" line.long 0x08 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode" hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects between and loopback modes" "IOLBEN_0,IOLBEN_1" newline bitfld.long 0x08 2.--3. "MODE,Loopback generator mode bits.0x2 " "MODE_0,MODE_1,?,?" bitfld.long 0x08 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" newline bitfld.long 0x08 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" line.long 0x0C "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the MCASP" hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" newline bitfld.long 0x0C 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" bitfld.long 0x0C 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 0. "DITEN,DIT mode enable bit" "DITEN_0,DITEN_1" group.long 0x60++0x2F line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED," rbitfld.long 0x00 12. "XFRST,Frame sync generator reset" "XFRST_0,XFRST_1" newline rbitfld.long 0x00 11. "XSMRST,XMT state machine reset" "XSMRST_0,XSMRST_1" rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear" "XSRCLR_0,XSRCLR_1" newline rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "RFRST,Frame sync generator reset" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,RCV state machine reset" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" line.long 0x08 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" hexmask.long.word 0x08 18.--31. 1. "RESERVED," bitfld.long 0x08 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n]" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" newline bitfld.long 0x08 15. "RRVRS,Receive serial bitstream order" "RRVRS_0,RRVRS_1" bitfld.long 0x08 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" newline bitfld.long 0x08 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x08 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" newline bitfld.long 0x08 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" bitfld.long 0x08 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" line.long 0x0C "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," abitfld.long 0x0C 7.--15. "RMOD,Receive frame sync mode select" "0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x1FF=Reserved" newline bitfld.long 0x0C 5.--6. "RESERVED," "0,1,2,3" bitfld.long 0x0C 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" newline bitfld.long 0x0C 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x0C 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" newline bitfld.long 0x0C 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" line.long 0x10 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" hexmask.long.word 0x10 21.--31. 1. "RESERVED," bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" hexmask.long.byte 0x10 8.--15. 1. "RESERVED," newline bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" bitfld.long 0x10 6. "RESERVED," "0,1" newline bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" bitfld.long 0x10 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" hexmask.long.word 0x14 21.--31. 1. "RESERVED," bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" bitfld.long 0x14 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" bitfld.long 0x14 12.--13. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to" line.long 0x18 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" line.long 0x1C "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT)" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit" "RSTAFRM_0,RSTAFRM_1" newline bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "RDATA,Receive data-ready interrupt enable bit" "RDATA_0,RDATA_1" newline bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit" "RLAST_0,RLAST_1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit" "ROVRN_0,ROVRN_1" line.long 0x20 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED," bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" newline bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" newline bitfld.long 0x20 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" bitfld.long 0x20 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" newline bitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" newline bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" line.long 0x24 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED," hexmask.long.word 0x24 0.--8. 1. "RSLOTCNT," line.long 0x28 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "RCNT," hexmask.long.byte 0x28 16.--23. 1. "RMAX," newline hexmask.long.byte 0x28 8.--15. 1. "RMIN," bitfld.long 0x28 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 0.--3. "RPS,Receive clock check prescaler value.0x9" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" line.long 0x2C "MCASP_REVTCTL,Receiver DMA event control register" hexmask.long 0x2C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0xA0++0x33 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED," bitfld.long 0x00 12. "XFRST,Frame sync generator reset" "XFRST_0,XFRST_1" newline bitfld.long 0x00 11. "XSMRST,XMT state machine reset" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,XMT serializer clear" "XSRCLR_0,XSRCLR_1" newline bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x00 4. "RFRST,Frame sync generator reset" "RFRST_0,RFRST_1" newline rbitfld.long 0x00 3. "RSMRST,RCV state machine reset" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear" "RSRCLKR_0,RSRCLKR_1" newline rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" line.long 0x08 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 16.--17. "XDATDLY,Transmit sync bit delay" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" newline bitfld.long 0x08 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" bitfld.long 0x08 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" newline bitfld.long 0x08 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" newline bitfld.long 0x08 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" bitfld.long 0x08 0.--2. "XROT,Right-rotation value for transmit rotate right format unit" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" line.long 0x0C "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,Reserved" abitfld.long 0x0C 7.--15. "XMOD,Transmit frame-sync mode select bits" "0x000=Burst mode,0x001=Reserved,0x002=2-slot TDM mode (),0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x180=384-slot DIT mode All other: Reserved" newline bitfld.long 0x0C 5.--6. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0C 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" newline bitfld.long 0x0C 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0C 1. "FSXM,Transmit frame-sync generation select bit" "FSXM_0,FSXM_1" newline bitfld.long 0x0C 0. "FSXP,Transmit frame-sync polarity select bit" "FSXP_0,FSXP_1" line.long 0x10 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" hexmask.long.word 0x10 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" hexmask.long.byte 0x10 8.--15. 1. "RESERVED," newline bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" bitfld.long 0x10 6. "ASYNC,Transmit operation asynchronous enable bit" "ASYNC_0,ASYNC_1" newline bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit" "CLKXM_0,CLKXM_1" bitfld.long 0x10 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "Divide-by-1,Divide-by-2 0x2 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide-by-3 to divide-by-32" line.long 0x14 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" hexmask.long.word 0x14 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit" "HCLKXM_0,HCLKXM_1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" bitfld.long 0x14 12.--13. "RESERVED,Reserved" "0,1,2,3" newline abitfld.long 0x14 0.--11. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" "0x000=Divide-by-1,0x001=Divide-by-2 0x2 to,0xFFF=Divide-by-3 to divide-by-4096" line.long 0x18 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" line.long 0x1C "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit" "XSTAFRM_0,XSTAFRM_1" newline bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data-ready interrupt enable bit" "XDATA_0,XDATA_1" newline bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit" "XLAST_0,XLAST_1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit" "XUNDRN_0,XUNDRN_1" line.long 0x20 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the MCASP logic has priority and the flag remains set" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" newline bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" newline bitfld.long 0x20 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" newline bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" line.long 0x24 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 0.--8. 1. "XSLOTCNT,Current transmit time slot count" line.long 0x28 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x28 16.--23. 1. "XMAX,0x0 to" newline hexmask.long.byte 0x28 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x28 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 0.--3. "XPS,Transmit clock check prescaler value" "MCASP interface clock divided by 1,MCASP interface clock divided by 2,MCASP interface clock divided by 4,MCASP interface clock divided by 8,MCASP interface clock divided by 16,MCASP interface clock divided by 32,MCASP interface clock divided by 64,MCASP interface clock divided by 128,MCASP interface clock divided by 256 0x9 to,?,?,?,?,?,?,Reserved" line.long 0x2C "MCASP_XEVTCTL,Transmitter DMA event control register" hexmask.long 0x2C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" line.long 0x30 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" hexmask.long 0x30 1.--31. 1. "RESERVED," bitfld.long 0x30 0. "ENABLE,One-shot clock adjust enable" "ENABLE_0,ENABLE_1" group.long 0x100++0x5F line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x04 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x08 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x0C "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x10 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x14 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x18 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x1C "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x20 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x24 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x28 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x2C "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x30 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x34 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x38 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x3C "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x40 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x44 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x48 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x4C "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x50 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x54 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x58 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x5C "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x180++0x17 line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" hexmask.long 0x00 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x04 "MCASP_XRSRCTLn_1,Serializer n control register" hexmask.long 0x04 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x04 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x04 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x04 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x08 "MCASP_XRSRCTLn_2,Serializer n control register" hexmask.long 0x08 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x08 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x08 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x08 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x08 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x0C "MCASP_XRSRCTLn_3,Serializer n control register" hexmask.long 0x0C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0C 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x0C 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x0C 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x0C 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x10 "MCASP_XRSRCTLn_4,Serializer n control register" hexmask.long 0x10 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x14 "MCASP_XRSRCTLn_5,Serializer n control register" hexmask.long 0x14 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" group.long 0x200++0x17 line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x04 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x08 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x0C "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x10 "MCASP_TXBUFn_4,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x14 "MCASP_TXBUFn_5,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x280++0x17 line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x04 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x08 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x0C "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x10 "MCASP_RXBUFn_4,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x14 "MCASP_RXBUFn_5,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" width 0x0B tree.end tree "MCASP2_DAT" base ad:0x48436000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" width 0x0B tree.end tree "MCASP3_AFIFO" base ad:0x48471000 group.long 0x00++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" hexmask.long.word 0x00 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" abitfld.long 0x00 8.--15. "WNUMEVT,Write word count (32-bit) to generate TX event to host" "0x40=3 to 64 words currently..,0xFF=Reserved" abitfld.long 0x00 0.--7. "WNUMDMA,Write word count (32-bit words)" "0x10=3 to 16 words,0xFF=Reserved" line.long 0x04 "WFIFOSTS,The Write FIFO status register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently..,0xFF=Reserved" line.long 0x08 "RFIFOCTL,The Read FIFO control register" hexmask.long.word 0x08 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" abitfld.long 0x08 8.--15. "RNUMEVT,Read word count (32-bit) to generate RX event to host" "0x40=3 to 64 words..,0xFF=Reserved" abitfld.long 0x08 0.--7. "RNUMDMA,Read word count (32-bit words)" "0x10=3-16 words,0xFF=Reserved" line.long 0x0C "RFIFOSTS,The Read FIFO status register" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently..,0xFF=Reserved" width 0x0B tree.end tree "MCASP3_CFG" base ad:0x48470000 rgroup.long 0x00++0x07 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x00 28.--29. "RESV,Reserved" "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. "FUNCTION,MCASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "0,1,2,3" newline bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PWRIDLESYSCONFIG,Power idle module configuration register" hexmask.long 0x04 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2.--5. "OTHER,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--1. "IDLE_MODE," "?,No-idle mode,Smart-idle mode - default..,Reserved" group.long 0x10++0x0F line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" newline bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x00 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x04 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x04 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x04 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" newline bitfld.long 0x04 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" newline bitfld.long 0x04 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" newline bitfld.long 0x04 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" newline bitfld.long 0x04 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" bitfld.long 0x04 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" newline bitfld.long 0x04 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" newline bitfld.long 0x04 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x08 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x08 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" newline bitfld.long 0x08 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1" "ACLKR_0,ACLKR_1" bitfld.long 0x08 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" newline bitfld.long 0x08 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" bitfld.long 0x08 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x08 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x08 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" newline bitfld.long 0x08 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" newline bitfld.long 0x08 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" bitfld.long 0x08 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" newline bitfld.long 0x08 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" newline bitfld.long 0x08 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" newline bitfld.long 0x08 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" newline bitfld.long 0x08 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" bitfld.long 0x08 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" newline bitfld.long 0x08 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x0C "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins" bitfld.long 0x0C 31. "AFSR,Logic level on AFSR pin (device level: mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x0C 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 29. "ACLKR,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" bitfld.long 0x0C 28. "AFSX,Logic level on AFSX pin (device level: mcaspi_fsx signal)" "AFSX_0,AFSX_1" newline bitfld.long 0x0C 27. "AHCLKX,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" bitfld.long 0x0C 26. "ACLKX,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x0C 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x0C 15. "AXR15,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" newline bitfld.long 0x0C 14. "AXR14,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x0C 13. "AXR13,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" newline bitfld.long 0x0C 12. "AXR12,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x0C 11. "AXR11,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x0C 10. "AXR10,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x0C 9. "AXR9,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" newline bitfld.long 0x0C 8. "AXR8,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x0C 7. "AXR7,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" newline bitfld.long 0x0C 6. "AXR6,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" bitfld.long 0x0C 5. "AXR5,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" newline bitfld.long 0x0C 4. "AXR4,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x0C 3. "AXR3,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" newline bitfld.long 0x0C 2. "AXR2,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x0C 1. "AXR1,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x0C 0. "AXR0,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x1C++0x07 line.long 0x00 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" newline bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x00 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x04 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline hexmask.long.word 0x04 16.--25. 1. "RESERVED,Reserved" bitfld.long 0x04 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x04 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x04 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x04 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x04 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x04 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x04 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x04 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x44++0x0F line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit" "XFRST_0,XFRST_1" newline bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bitAXR[n] pin state : If[n] = 0 and [n] = 1 the corresponding serializer [n] drives the AXR[n] pin to the state specified for inactive time slot" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" newline bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" line.long 0x08 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode" hexmask.long 0x08 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects between and loopback modes" "IOLBEN_0,IOLBEN_1" newline bitfld.long 0x08 2.--3. "MODE,Loopback generator mode bits.0x2 " "MODE_0,MODE_1,?,?" bitfld.long 0x08 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" newline bitfld.long 0x08 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" line.long 0x0C "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the MCASP" hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" newline bitfld.long 0x0C 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" bitfld.long 0x0C 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 0. "DITEN,DIT mode enable bit" "DITEN_0,DITEN_1" group.long 0x60++0x2F line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED," rbitfld.long 0x00 12. "XFRST,Frame sync generator reset" "XFRST_0,XFRST_1" newline rbitfld.long 0x00 11. "XSMRST,XMT state machine reset" "XSMRST_0,XSMRST_1" rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear" "XSRCLR_0,XSRCLR_1" newline rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. "RFRST,Frame sync generator reset" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,RCV state machine reset" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" line.long 0x08 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" hexmask.long.word 0x08 18.--31. 1. "RESERVED," bitfld.long 0x08 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n]" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" newline bitfld.long 0x08 15. "RRVRS,Receive serial bitstream order" "RRVRS_0,RRVRS_1" bitfld.long 0x08 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" newline bitfld.long 0x08 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x08 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" newline bitfld.long 0x08 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" bitfld.long 0x08 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" line.long 0x0C "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," abitfld.long 0x0C 7.--15. "RMOD,Receive frame sync mode select" "0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x1FF=Reserved" newline bitfld.long 0x0C 5.--6. "RESERVED," "0,1,2,3" bitfld.long 0x0C 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" newline bitfld.long 0x0C 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x0C 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" newline bitfld.long 0x0C 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" line.long 0x10 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" hexmask.long.word 0x10 21.--31. 1. "RESERVED," bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" hexmask.long.byte 0x10 8.--15. 1. "RESERVED," newline bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" bitfld.long 0x10 6. "RESERVED," "0,1" newline bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" bitfld.long 0x10 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" hexmask.long.word 0x14 21.--31. 1. "RESERVED," bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" bitfld.long 0x14 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" bitfld.long 0x14 12.--13. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to" line.long 0x18 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" line.long 0x1C "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT)" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit" "RSTAFRM_0,RSTAFRM_1" newline bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "RDATA,Receive data-ready interrupt enable bit" "RDATA_0,RDATA_1" newline bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit" "RLAST_0,RLAST_1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit" "ROVRN_0,ROVRN_1" line.long 0x20 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED," bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" newline bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" newline bitfld.long 0x20 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" bitfld.long 0x20 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" newline bitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" newline bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" line.long 0x24 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED," hexmask.long.word 0x24 0.--8. 1. "RSLOTCNT," line.long 0x28 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "RCNT," hexmask.long.byte 0x28 16.--23. 1. "RMAX," newline hexmask.long.byte 0x28 8.--15. 1. "RMIN," bitfld.long 0x28 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 0.--3. "RPS,Receive clock check prescaler value.0x9" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" line.long 0x2C "MCASP_REVTCTL,Receiver DMA event control register" hexmask.long 0x2C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0xA0++0x33 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED," bitfld.long 0x00 12. "XFRST,Frame sync generator reset" "XFRST_0,XFRST_1" newline bitfld.long 0x00 11. "XSMRST,XMT state machine reset" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,XMT serializer clear" "XSRCLR_0,XSRCLR_1" newline bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x00 4. "RFRST,Frame sync generator reset" "RFRST_0,RFRST_1" newline rbitfld.long 0x00 3. "RSMRST,RCV state machine reset" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear" "RSRCLKR_0,RSRCLKR_1" newline rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" line.long 0x08 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 16.--17. "XDATDLY,Transmit sync bit delay" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" newline bitfld.long 0x08 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" bitfld.long 0x08 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" newline bitfld.long 0x08 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" newline bitfld.long 0x08 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" bitfld.long 0x08 0.--2. "XROT,Right-rotation value for transmit rotate right format unit" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" line.long 0x0C "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,Reserved" abitfld.long 0x0C 7.--15. "XMOD,Transmit frame-sync mode select bits" "0x000=Burst mode,0x001=Reserved,0x002=2-slot TDM mode (),0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x180=384-slot DIT mode All other: Reserved" newline bitfld.long 0x0C 5.--6. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0C 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" newline bitfld.long 0x0C 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0C 1. "FSXM,Transmit frame-sync generation select bit" "FSXM_0,FSXM_1" newline bitfld.long 0x0C 0. "FSXP,Transmit frame-sync polarity select bit" "FSXP_0,FSXP_1" line.long 0x10 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" hexmask.long.word 0x10 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" hexmask.long.byte 0x10 8.--15. 1. "RESERVED," newline bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" bitfld.long 0x10 6. "ASYNC,Transmit operation asynchronous enable bit" "ASYNC_0,ASYNC_1" newline bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit" "CLKXM_0,CLKXM_1" bitfld.long 0x10 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "Divide-by-1,Divide-by-2 0x2 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide-by-3 to divide-by-32" line.long 0x14 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" hexmask.long.word 0x14 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" newline bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" newline bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "?,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit" "HCLKXM_0,HCLKXM_1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" bitfld.long 0x14 12.--13. "RESERVED,Reserved" "0,1,2,3" newline abitfld.long 0x14 0.--11. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" "0x000=Divide-by-1,0x001=Divide-by-2 0x2 to,0xFFF=Divide-by-3 to divide-by-4096" line.long 0x18 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" line.long 0x1C "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit" "XSTAFRM_0,XSTAFRM_1" newline bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data-ready interrupt enable bit" "XDATA_0,XDATA_1" newline bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit" "XLAST_0,XLAST_1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit" "XUNDRN_0,XUNDRN_1" line.long 0x20 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the MCASP logic has priority and the flag remains set" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" newline bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" newline bitfld.long 0x20 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" newline bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" line.long 0x24 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 0.--8. 1. "XSLOTCNT,Current transmit time slot count" line.long 0x28 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x28 16.--23. 1. "XMAX,0x0 to" newline hexmask.long.byte 0x28 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x28 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 0.--3. "XPS,Transmit clock check prescaler value" "MCASP interface clock divided by 1,MCASP interface clock divided by 2,MCASP interface clock divided by 4,MCASP interface clock divided by 8,MCASP interface clock divided by 16,MCASP interface clock divided by 32,MCASP interface clock divided by 64,MCASP interface clock divided by 128,MCASP interface clock divided by 256 0x9 to,?,?,?,?,?,?,Reserved" line.long 0x2C "MCASP_XEVTCTL,Transmitter DMA event control register" hexmask.long 0x2C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" line.long 0x30 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" hexmask.long 0x30 1.--31. 1. "RESERVED," bitfld.long 0x30 0. "ENABLE,One-shot clock adjust enable" "ENABLE_0,ENABLE_1" group.long 0x100++0x5F line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x04 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x08 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x0C "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x10 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x14 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x18 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x1C "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x20 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x24 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x28 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x2C "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" line.long 0x30 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x34 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x38 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x3C "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x40 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x44 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" line.long 0x48 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x4C "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x50 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x54 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x58 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" line.long 0x5C "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x180++0x17 line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" hexmask.long 0x00 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x04 "MCASP_XRSRCTLn_1,Serializer n control register" hexmask.long 0x04 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x04 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x04 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x04 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x08 "MCASP_XRSRCTLn_2,Serializer n control register" hexmask.long 0x08 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x08 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x08 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x08 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x08 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x0C "MCASP_XRSRCTLn_3,Serializer n control register" hexmask.long 0x0C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0C 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x0C 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x0C 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x0C 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x10 "MCASP_XRSRCTLn_4,Serializer n control register" hexmask.long 0x10 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" line.long 0x14 "MCASP_XRSRCTLn_5,Serializer n control register" hexmask.long 0x14 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" newline rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" newline bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" group.long 0x200++0x17 line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x04 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x08 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x0C "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x10 "MCASP_TXBUFn_4,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" line.long 0x14 "MCASP_TXBUFn_5,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x280++0x17 line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x04 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x08 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x0C "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x10 "MCASP_RXBUFn_4,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" line.long 0x14 "MCASP_RXBUFn_5,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" width 0x0B tree.end tree "MCASP3_DAT" base ad:0x4843A000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" width 0x0B tree.end tree "MCASP_CFG_TARG" base ad:0x48462000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCRC" base ad:0x4BC00000 group.long 0x00++0x03 line.long 0x00 "CRC_CTRL0," hexmask.long.byte 0x00 25.--31. 1. "RESERVED," newline bitfld.long 0x00 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset" newline hexmask.long.byte 0x00 17.--23. 1. "RESERVED," newline bitfld.long 0x00 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," newline bitfld.long 0x00 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset" group.long 0x08++0x03 line.long 0x00 "CRC_CTRL1," hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "PWDN,Power Down" "MCRC is not in power down mode,MCRC is in power down mode" group.long 0x10++0x03 line.long 0x00 "CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 24.--25. "CH4_MODE,Channel 4 Mode" "Data Capture mode,AUTO mode,?,Full-CPU mode For all four channels the seed.." newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 16.--17. "CH3_MODE,Channel 3 Mode" "Data Capture mode,AUTO mode,?,Full-CPU mode" newline rbitfld.long 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--9. "CH2_MODE,Channel 2 Mode" "Data Capture mode,AUTO mode,?,Full-CPU mode" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode" "Data Trace disable,Data Trace enable" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 0.--1. "CH1_MODE,Channel 1 Mode" "Data Capture mode,AUTO mode,?,Full-CPU mode" group.long 0x18++0x03 line.long 0x00 "CRC_INTS," rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 28. "CH4_TIME_OUT_ENS,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable" newline bitfld.long 0x00 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable" newline bitfld.long 0x00 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable" newline bitfld.long 0x00 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable" newline bitfld.long 0x00 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable" newline rbitfld.long 0x00 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable" newline bitfld.long 0x00 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable" newline bitfld.long 0x00 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable" newline bitfld.long 0x00 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable" newline bitfld.long 0x00 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable" newline rbitfld.long 0x00 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12. "CH2_TIME_OUT_ENS,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable" newline bitfld.long 0x00 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable" newline bitfld.long 0x00 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable" newline bitfld.long 0x00 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable" newline bitfld.long 0x00 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "CH1_TIME_OUT_ENS,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable" newline bitfld.long 0x00 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable" newline bitfld.long 0x00 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable" newline bitfld.long 0x00 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable" newline bitfld.long 0x00 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable" group.long 0x20++0x03 line.long 0x00 "CRC_INTR," rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable" newline bitfld.long 0x00 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable" newline bitfld.long 0x00 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable" newline bitfld.long 0x00 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable" newline bitfld.long 0x00 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable" newline rbitfld.long 0x00 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. "CH3_TIME_OUT_ENR,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable" newline bitfld.long 0x00 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable" newline bitfld.long 0x00 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable" newline bitfld.long 0x00 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable" newline bitfld.long 0x00 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable" newline rbitfld.long 0x00 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12. "CH2_TIME_OUT_ENR,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable" newline bitfld.long 0x00 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable" newline bitfld.long 0x00 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable" newline bitfld.long 0x00 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable" newline bitfld.long 0x00 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable" newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "CH1_TIME_OUT_ENR,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable" newline bitfld.long 0x00 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable" newline bitfld.long 0x00 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable" newline bitfld.long 0x00 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable" newline bitfld.long 0x00 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable" group.long 0x28++0x03 line.long 0x00 "CRC_STATUS," rbitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active" newline bitfld.long 0x00 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active" newline bitfld.long 0x00 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active" newline bitfld.long 0x00 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active" newline bitfld.long 0x00 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.." newline rbitfld.long 0x00 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active" newline bitfld.long 0x00 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active" newline bitfld.long 0x00 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active" newline bitfld.long 0x00 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active" newline bitfld.long 0x00 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.." newline rbitfld.long 0x00 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active" newline bitfld.long 0x00 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active" newline bitfld.long 0x00 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active" newline bitfld.long 0x00 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active" newline bitfld.long 0x00 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.." newline rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active" newline bitfld.long 0x00 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active" newline bitfld.long 0x00 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active" newline bitfld.long 0x00 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active" newline bitfld.long 0x00 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.." group.long 0x30++0x03 line.long 0x00 "CRC_INT_OFFSET_REG," hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," newline hexmask.long.byte 0x00 0.--7. 1. "CRC,Interrupt Offset" rgroup.long 0x38++0x03 line.long 0x00 "CRC_BUSY," hexmask.long.byte 0x00 25.--31. 1. "RESERVED," newline bitfld.long 0x00 24. "CH4_BUSY,ARRAY(0x243e780)" "0,1" newline hexmask.long.byte 0x00 17.--23. 1. "RESERVED," newline bitfld.long 0x00 16. "CH3_BUSY,ARRAY(0x243e9a0)" "0,1" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "CH2_BUSY,ARRAY(0x243eba0)" "0,1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," newline bitfld.long 0x00 0. "CH1_BUSY,ARRAY(0x243eda0)" "0,1" group.long 0x40++0x13 line.long 0x00 "CRC_PCOUNT_REG1," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register" line.long 0x04 "CRC_SCOUNT_REG1," hexmask.long.word 0x04 16.--31. 1. "RESERVED," newline hexmask.long.word 0x04 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register" line.long 0x08 "CRC_CURSEC_REG1," hexmask.long.word 0x08 16.--31. 1. "RESERVED," newline hexmask.long.word 0x08 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register" line.long 0x0C "CRC_WDTOPLD1," hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x0C 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register" line.long 0x10 "CRC_BCTOPLD1," hexmask.long.byte 0x10 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register" group.long 0x60++0x33 line.long 0x00 "PSA_SIGREGL1," line.long 0x04 "PSA_SIGREGH1," line.long 0x08 "CRC_REGL1," line.long 0x0C "CRC_REGH1," line.long 0x10 "PSA_SECSIGREGL1," line.long 0x14 "PSA_SECSIGREGH1," line.long 0x18 "RAW_DATAREGL1," line.long 0x1C "RAW_DATAREGH1," line.long 0x20 "CRC_PCOUNT_REG2," hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed" line.long 0x24 "CRC_SCOUNT_REG2," hexmask.long.word 0x24 16.--31. 1. "RESERVED," newline hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register" line.long 0x28 "CRC_CURSEC_REG2," hexmask.long.word 0x28 16.--31. 1. "RESERVED," newline hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register" line.long 0x2C "CRC_WDTOPLD2," hexmask.long.byte 0x2C 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register" line.long 0x30 "CRC_BCTOPLD2," hexmask.long.byte 0x30 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register" group.long 0xA0++0x33 line.long 0x00 "PSA_SIGREGL2," line.long 0x04 "PSA_SIGREGH2," line.long 0x08 "CRC_REGL2," line.long 0x0C "CRC_REGH2," line.long 0x10 "PSA_SECSIGREGL2," line.long 0x14 "PSA_SECSIGREGH2," line.long 0x18 "RAW_DATAREGL2," line.long 0x1C "RAW_DATAREGH2," line.long 0x20 "CRC_PCOUNT_REG3," hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register" line.long 0x24 "CRC_SCOUNT_REG3," hexmask.long.word 0x24 16.--31. 1. "RESERVED," newline hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register" line.long 0x28 "CRC_CURSEC_REG3," hexmask.long.word 0x28 16.--31. 1. "RESERVED," newline hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register" line.long 0x2C "CRC_WDTOPLD3," hexmask.long.word 0x2C 16.--31. 1. "RESERVED," newline hexmask.long.word 0x2C 0.--15. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register" line.long 0x30 "CRC_BCTOPLD3," hexmask.long.byte 0x30 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register" group.long 0xE0++0x33 line.long 0x00 "PSA_SIGREGL3," line.long 0x04 "PSA_SIGREGH3," line.long 0x08 "CRC_REGL3," line.long 0x0C "CRC_REGH3," line.long 0x10 "PSA_SECSIGREGL3," line.long 0x14 "PSA_SECSIGREGH3," line.long 0x18 "RAW_DATAREGL3," line.long 0x1C "RAW_DATAREGH3," line.long 0x20 "CRC_PCOUNT_REG4," hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register" line.long 0x24 "CRC_SCOUNT_REG4," hexmask.long.word 0x24 16.--31. 1. "RESERVED," newline hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register" line.long 0x28 "CRC_CURSEC_REG4," hexmask.long.word 0x28 16.--31. 1. "RESERVED," newline hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails" line.long 0x2C "CRC_WDTOPLD4," hexmask.long.byte 0x2C 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns" line.long 0x30 "CRC_BCTOPLD4," hexmask.long.byte 0x30 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated" group.long 0x120++0x23 line.long 0x00 "PSA_SIGREGL4," hexmask.long.byte 0x00 24.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 0.--23. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register" line.long 0x04 "PSA_SIGREGH4," line.long 0x08 "CRC_REGL4," line.long 0x0C "CRC_REGH4," line.long 0x10 "PSA_SECSIGREGL4," line.long 0x14 "PSA_SECSIGREGH4," line.long 0x18 "RAW_DATAREGL4," line.long 0x1C "RAW_DATAREGH4," line.long 0x20 "MCRC_BUS_SEL," hexmask.long 0x20 3.--31. 1. "RESERVED," newline bitfld.long 0x20 2. "MEN,Enable/disables the tracing of VBUSM" "Tracing of VBUSM master bus has been disabled,Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x20 1. "DTC_MEN,Enable/disables the tracing of data TCM" "Tracing of DTCM_ODD and DTCM_EVEN buses have..,Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x20 0. "ITC_MEN,Enable/disables the tracing of instruction TCM" "Tracing of ITCM bus has been disabled,Tracing of ITCM bus has been enabled Please.." width 0x0B tree.end repeat 2. (list 2. 3. )(list ad:0x4809A000 ad:0x480B8000 ) tree "MCSPI$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any)" hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to 0 and writes to them are ignored" bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter" "Retention mode disabled,Retention mode enabled" bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This field defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "?,FFNBYTE_1_r,FFNBYTE_2_r,?,FFNBYTE_4_r,?,?,?,FFNBYTE_8_r,?,?,?,?,?,?,?,FFNBYTE_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management" "USEFIFO_0_r,USEFIFO_1_r" group.long 0x10++0x03 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" hexmask.long 0x00 4.--31. 1. "RSVD," bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_w" rgroup.long 0x100++0x03 line.long 0x00 "MCSPI_REVISION,This register contains the revision number" group.long 0x110++0x1F line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface and is not affected by software reset" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" bitfld.long 0x00 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "SIDLEMODE,Power management" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wake-up feature control" "ENAWAKEUP_0,ENAWAKEUP_1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock-gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved for module specific status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]" "EOW_0_r,EOW_1_w" bitfld.long 0x08 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "WKS_0_w,WKS_1_r" newline bitfld.long 0x08 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full" "RX3_FULL_0_w,RX3_FULL_1_r" bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow" "TX3_UNDERFLOW_0_w,TX3_UNDERFLOW_1_r" newline bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty" "TX3_EMPTY_0_w,TX3_EMPTY_1_r" bitfld.long 0x08 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full" "RX2_FULL_0_w,RX2_FULL_1_r" newline bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow" "TX2_UNDERFLOW_0_w,TX2_UNDERFLOW_1_r" bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty" "TX2_EMPTY_0_w,TX2_EMPTY_1_r" bitfld.long 0x08 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full" "RX1_FULL_0_w,RX1_FULL_1_r" bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow" "TX1_UNDERFLOW_0_w,TX1_UNDERFLOW_1_r" bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty" "TX1_EMPTY_0_w,TX1_EMPTY_1_r" newline bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only)" "RX0_OVERFLOW_0_w,RX0_OVERFLOW_1_r" bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full" "RX0_FULL_0_w,RX0_FULL_1_r" bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow" "TX0_UNDERFLOW_0_w,TX0_UNDERFLOW_1_r" newline bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty" "TX0_EMPTY_0_w,TX0_EMPTY_1_r" line.long 0x0C "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis" hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "EOW_ENABLE_0,EOW_ENABLE_1" bitfld.long 0x0C 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "WKE_0,WKE_1" newline bitfld.long 0x0C 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX3_FULL_ENABLE_0,RX3_FULL_ENABLE_1" bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX3_UNDERFLOW_ENABLE_0,TX3_UNDERFLOW_ENABLE_1" newline bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX3_EMPTY_ENABLE_0,TX3_EMPTY_ENABLE_1" bitfld.long 0x0C 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX2_FULL_ENABLE_0,RX2_FULL_ENABLE_1" newline bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX2_UNDERFLOW_ENABLE_0,TX2_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX2_EMPTY_ENABLE_0,TX2_EMPTY_ENABLE_1" bitfld.long 0x0C 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX1_FULL_ENABLE_0,RX1_FULL_ENABLE_1" bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX1_UNDERFLOW_ENABLE_0,TX1_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX1_EMPTY_ENABLE_0,TX1_EMPTY_ENABLE_1" newline bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable" "RX0_OVERFLOW_ENABLE_0,RX0_OVERFLOW_ENABLE_1" bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX0_FULL_ENABLE_0,RX0_FULL_ENABLE_1" bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX0_UNDERFLOW_ENABLE_0,TX0_UNDERFLOW_ENABLE_1" newline bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX0_EMPTY_ENABLE_0,TX0_EMPTY_ENABLE_1" line.long 0x10 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis" hexmask.long 0x10 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x10 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "WKEN_0,WKEN_1" line.long 0x14 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode" hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "SSB_0,SSB_1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "SPIENDIR_0,SPIENDIR_1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "SPIDATDIR1_0,SPIDATDIR1_1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "SPIDATDIR0_0,SPIDATDIR0_1" bitfld.long 0x14 7. "WAKD,SWAKEUP output (signal data value of internal signal to system)" "WAKD_0,WAKD_1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction) this bit returns the value on the CLKSPI line (high or low) and a write into this bit has no effect" "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction) the SPIDAT[1] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction) the SPIDAT[0] line is driven high or low according to the value written into this bit" "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[3] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[2] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[1] line is driven high or low according to the value written into this bit" "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[0] line is driven high or low according to the value written into this bit" "0,1" line.long 0x18 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface" hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA address 256-bit aligned this bit is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address" "FDAA_0,FDAA_1" bitfld.long 0x18 7. "MOA,Multiple word OCP access: this bit can only be used when a channel is enabled using a FIFO" "MOA_0,MOA_1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial SPI delay for first transfer: this field is an option only available in SINGLE master mode" "INITDLY_0,INITDLY_1,INITDLY_2,INITDLY_3,INITDLY_4,?,?,?" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "SYSTEM_TEST_0,SYSTEM_TEST_1" bitfld.long 0x18 2. "MS,Master/slave" "MS_0,MS_1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This bit is used in master or slave mode to configure the SPI pin mode (3-pin or 4-pin)" "PIN34_0,PIN34_1" bitfld.long 0x18 0. "SINGLE,Single channel/Multi Channel (master mode only)" "SINGLE_0,SINGLE_1" line.long 0x1C "MCSPI_CHxCONF_0,This register is dedicated to the configuration of the channel x" rbitfld.long 0x1C 30.--31. "RESERVED,Read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x1C 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x1C 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" newline bitfld.long 0x1C 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x1C 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x1C 17. "DPE1,Transmission enable for data line 1" "DPE1_0,DPE1_1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0" "DPE0_0,DPE0_1" bitfld.long 0x1C 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x1C 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x1C 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" newline bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x1C 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x1C 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" group.long 0x140++0x03 line.long 0x00 "MCSPI_CHxCONF_1,This register is dedicated to the configuration of the channel x" rbitfld.long 0x00 30.--31. "RESERVED,Read returns 0" "0,1,2,3" bitfld.long 0x00 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x00 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" newline bitfld.long 0x00 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x00 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x00 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" newline bitfld.long 0x00 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x00 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" bitfld.long 0x00 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" newline bitfld.long 0x00 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x00 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x00 17. "DPE1,Transmission enable for data line 1" "DPE1_0,DPE1_1" newline bitfld.long 0x00 16. "DPE0,Transmission Enable for data line 0" "DPE0_0,DPE0_1" bitfld.long 0x00 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x00 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x00 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x00 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x00 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" newline bitfld.long 0x00 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x00 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x00 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" rgroup.long 0x130++0x03 line.long 0x00 "MCSPI_CHxSTAT_0,This register provides status information about transmitter and receiver registers of channel x" hexmask.long 0x00 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" newline bitfld.long 0x00 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" newline bitfld.long 0x00 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" rgroup.long 0x144++0x03 line.long 0x00 "MCSPI_CHxSTAT_1,This register provides status information about transmitter and receiver registers of channel x" hexmask.long 0x00 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" newline bitfld.long 0x00 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" newline bitfld.long 0x00 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" group.long 0x134++0x03 line.long 0x00 "MCSPI_CHxCTRL_0,This register is dedicated to enable channel x" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" hexmask.long.byte 0x00 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" group.long 0x148++0x03 line.long 0x00 "MCSPI_CHxCTRL_1,This register is dedicated to enable channel x" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" hexmask.long.byte 0x00 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" group.long 0x138++0x03 line.long 0x00 "MCSPI_TXx_0,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" group.long 0x14C++0x03 line.long 0x00 "MCSPI_TXx_1,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" rgroup.long 0x13C++0x03 line.long 0x00 "MCSPI_RXx_0,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" rgroup.long 0x150++0x03 line.long 0x00 "MCSPI_RXx_1,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" group.long 0x17C++0x07 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer" hexmask.long.word 0x00 16.--31. 1. "WCNT,SPI word counter" hexmask.long.byte 0x00 8.--15. 1. "AFL,Buffer almost full this field holds the programmable almost full level value used to determine almost full buffer condition" hexmask.long.byte 0x00 0.--7. 1. "AEL,Buffer almost empty" line.long 0x04 "MCSPI_DAFTX,This register contains the SPI words to be transmitted on the SPI bus when FIFO is used and DMA address is aligned on 256 bit" rgroup.long 0x1A0++0x03 line.long 0x00 "MCSPI_DAFRX,This register contains the SPI words received from the SPI bus when FIFO is used and DMA address is aligned on 256 bit" width 0x0B tree.end repeat.end tree "MCSPI1" base ad:0x48098000 rgroup.long 0x00++0x07 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any)" hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to 0 and writes to them are ignored" bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter" "Retention mode disabled,Retention mode enabled" bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This field defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "?,FFNBYTE_1_r,FFNBYTE_2_r,?,FFNBYTE_4_r,?,?,?,FFNBYTE_8_r,?,?,?,?,?,?,?,FFNBYTE_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management" "USEFIFO_0_r,USEFIFO_1_r" group.long 0x10++0x03 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" hexmask.long 0x00 4.--31. 1. "RSVD," bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_w" rgroup.long 0x100++0x03 line.long 0x00 "MCSPI_REVISION,This register contains the revision number" group.long 0x110++0x1F line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface and is not affected by software reset" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" bitfld.long 0x00 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "SIDLEMODE,Power management" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wake-up feature control" "ENAWAKEUP_0,ENAWAKEUP_1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock-gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved for module specific status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]" "EOW_0_r,EOW_1_w" bitfld.long 0x08 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "WKS_0_w,WKS_1_r" newline bitfld.long 0x08 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full" "RX3_FULL_0_w,RX3_FULL_1_r" bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow" "TX3_UNDERFLOW_0_w,TX3_UNDERFLOW_1_r" newline bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty" "TX3_EMPTY_0_w,TX3_EMPTY_1_r" bitfld.long 0x08 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full" "RX2_FULL_0_w,RX2_FULL_1_r" newline bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow" "TX2_UNDERFLOW_0_w,TX2_UNDERFLOW_1_r" bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty" "TX2_EMPTY_0_w,TX2_EMPTY_1_r" bitfld.long 0x08 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full" "RX1_FULL_0_w,RX1_FULL_1_r" bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow" "TX1_UNDERFLOW_0_w,TX1_UNDERFLOW_1_r" bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty" "TX1_EMPTY_0_w,TX1_EMPTY_1_r" newline bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only)" "RX0_OVERFLOW_0_w,RX0_OVERFLOW_1_r" bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full" "RX0_FULL_0_w,RX0_FULL_1_r" bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow" "TX0_UNDERFLOW_0_w,TX0_UNDERFLOW_1_r" newline bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty" "TX0_EMPTY_0_w,TX0_EMPTY_1_r" line.long 0x0C "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis" hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "EOW_ENABLE_0,EOW_ENABLE_1" bitfld.long 0x0C 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "WKE_0,WKE_1" newline bitfld.long 0x0C 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX3_FULL_ENABLE_0,RX3_FULL_ENABLE_1" bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX3_UNDERFLOW_ENABLE_0,TX3_UNDERFLOW_ENABLE_1" newline bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX3_EMPTY_ENABLE_0,TX3_EMPTY_ENABLE_1" bitfld.long 0x0C 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX2_FULL_ENABLE_0,RX2_FULL_ENABLE_1" newline bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX2_UNDERFLOW_ENABLE_0,TX2_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX2_EMPTY_ENABLE_0,TX2_EMPTY_ENABLE_1" bitfld.long 0x0C 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX1_FULL_ENABLE_0,RX1_FULL_ENABLE_1" bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX1_UNDERFLOW_ENABLE_0,TX1_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX1_EMPTY_ENABLE_0,TX1_EMPTY_ENABLE_1" newline bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable" "RX0_OVERFLOW_ENABLE_0,RX0_OVERFLOW_ENABLE_1" bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX0_FULL_ENABLE_0,RX0_FULL_ENABLE_1" bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX0_UNDERFLOW_ENABLE_0,TX0_UNDERFLOW_ENABLE_1" newline bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX0_EMPTY_ENABLE_0,TX0_EMPTY_ENABLE_1" line.long 0x10 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis" hexmask.long 0x10 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x10 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "WKEN_0,WKEN_1" line.long 0x14 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode" hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "SSB_0,SSB_1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "SPIENDIR_0,SPIENDIR_1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "SPIDATDIR1_0,SPIDATDIR1_1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "SPIDATDIR0_0,SPIDATDIR0_1" bitfld.long 0x14 7. "WAKD,SWAKEUP output (signal data value of internal signal to system)" "WAKD_0,WAKD_1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction) this bit returns the value on the CLKSPI line (high or low) and a write into this bit has no effect" "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction) the SPIDAT[1] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction) the SPIDAT[0] line is driven high or low according to the value written into this bit" "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[3] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[2] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[1] line is driven high or low according to the value written into this bit" "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[0] line is driven high or low according to the value written into this bit" "0,1" line.long 0x18 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface" hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA address 256-bit aligned this bit is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address" "FDAA_0,FDAA_1" bitfld.long 0x18 7. "MOA,Multiple word OCP access: this bit can only be used when a channel is enabled using a FIFO" "MOA_0,MOA_1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial SPI delay for first transfer: this field is an option only available in SINGLE master mode" "INITDLY_0,INITDLY_1,INITDLY_2,INITDLY_3,INITDLY_4,?,?,?" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "SYSTEM_TEST_0,SYSTEM_TEST_1" bitfld.long 0x18 2. "MS,Master/slave" "MS_0,MS_1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This bit is used in master or slave mode to configure the SPI pin mode (3-pin or 4-pin)" "PIN34_0,PIN34_1" bitfld.long 0x18 0. "SINGLE,Single channel/Multi Channel (master mode only)" "SINGLE_0,SINGLE_1" line.long 0x1C "MCSPI_CHxCONF_0,This register is dedicated to the configuration of the channel x" rbitfld.long 0x1C 30.--31. "RESERVED,Read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x1C 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x1C 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" newline bitfld.long 0x1C 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x1C 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x1C 17. "DPE1,Transmission enable for data line 1" "DPE1_0,DPE1_1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0" "DPE0_0,DPE0_1" bitfld.long 0x1C 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x1C 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x1C 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" newline bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x1C 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x1C 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" group.long 0x140++0x03 line.long 0x00 "MCSPI_CHxCONF_1,This register is dedicated to the configuration of the channel x" rbitfld.long 0x00 30.--31. "RESERVED,Read returns 0" "0,1,2,3" bitfld.long 0x00 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x00 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" newline bitfld.long 0x00 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x00 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x00 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" newline bitfld.long 0x00 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x00 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" bitfld.long 0x00 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" newline bitfld.long 0x00 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x00 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x00 17. "DPE1,Transmission enable for data line 1" "DPE1_0,DPE1_1" newline bitfld.long 0x00 16. "DPE0,Transmission Enable for data line 0" "DPE0_0,DPE0_1" bitfld.long 0x00 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x00 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x00 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x00 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x00 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" newline bitfld.long 0x00 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x00 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x00 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" group.long 0x154++0x03 line.long 0x00 "MCSPI_CHxCONF_2,This register is dedicated to the configuration of the channel x" rbitfld.long 0x00 30.--31. "RESERVED,Read returns 0" "0,1,2,3" bitfld.long 0x00 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x00 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" newline bitfld.long 0x00 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x00 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x00 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" newline bitfld.long 0x00 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x00 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" bitfld.long 0x00 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" newline bitfld.long 0x00 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x00 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x00 17. "DPE1,Transmission enable for data line 1" "DPE1_0,DPE1_1" newline bitfld.long 0x00 16. "DPE0,Transmission Enable for data line 0" "DPE0_0,DPE0_1" bitfld.long 0x00 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x00 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x00 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x00 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x00 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" newline bitfld.long 0x00 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x00 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x00 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" group.long 0x168++0x03 line.long 0x00 "MCSPI_CHxCONF_3,This register is dedicated to the configuration of the channel x" rbitfld.long 0x00 30.--31. "RESERVED,Read returns 0" "0,1,2,3" bitfld.long 0x00 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x00 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" newline bitfld.long 0x00 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x00 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x00 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" newline bitfld.long 0x00 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x00 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" bitfld.long 0x00 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" newline bitfld.long 0x00 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x00 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x00 17. "DPE1,Transmission enable for data line 1" "DPE1_0,DPE1_1" newline bitfld.long 0x00 16. "DPE0,Transmission Enable for data line 0" "DPE0_0,DPE0_1" bitfld.long 0x00 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x00 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x00 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x00 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x00 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" newline bitfld.long 0x00 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x00 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x00 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" rgroup.long 0x130++0x03 line.long 0x00 "MCSPI_CHxSTAT_0,This register provides status information about transmitter and receiver registers of channel x" hexmask.long 0x00 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" newline bitfld.long 0x00 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" newline bitfld.long 0x00 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" rgroup.long 0x144++0x03 line.long 0x00 "MCSPI_CHxSTAT_1,This register provides status information about transmitter and receiver registers of channel x" hexmask.long 0x00 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" newline bitfld.long 0x00 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" newline bitfld.long 0x00 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" rgroup.long 0x158++0x03 line.long 0x00 "MCSPI_CHxSTAT_2,This register provides status information about transmitter and receiver registers of channel x" hexmask.long 0x00 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" newline bitfld.long 0x00 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" newline bitfld.long 0x00 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" rgroup.long 0x16C++0x03 line.long 0x00 "MCSPI_CHxSTAT_3,This register provides status information about transmitter and receiver registers of channel x" hexmask.long 0x00 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x00 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" newline bitfld.long 0x00 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" newline bitfld.long 0x00 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" group.long 0x134++0x03 line.long 0x00 "MCSPI_CHxCTRL_0,This register is dedicated to enable channel x" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" hexmask.long.byte 0x00 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" group.long 0x148++0x03 line.long 0x00 "MCSPI_CHxCTRL_1,This register is dedicated to enable channel x" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" hexmask.long.byte 0x00 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" group.long 0x15C++0x03 line.long 0x00 "MCSPI_CHxCTRL_2,This register is dedicated to enable channel x" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" hexmask.long.byte 0x00 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" group.long 0x170++0x03 line.long 0x00 "MCSPI_CHxCTRL_3,This register is dedicated to enable channel x" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" hexmask.long.byte 0x00 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" group.long 0x138++0x03 line.long 0x00 "MCSPI_TXx_0,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" group.long 0x14C++0x03 line.long 0x00 "MCSPI_TXx_1,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" group.long 0x160++0x03 line.long 0x00 "MCSPI_TXx_2,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" group.long 0x174++0x03 line.long 0x00 "MCSPI_TXx_3,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" rgroup.long 0x13C++0x03 line.long 0x00 "MCSPI_RXx_0,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" rgroup.long 0x150++0x03 line.long 0x00 "MCSPI_RXx_1,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" rgroup.long 0x164++0x03 line.long 0x00 "MCSPI_RXx_2,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" rgroup.long 0x178++0x0B line.long 0x00 "MCSPI_RXx_3,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" line.long 0x04 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer" hexmask.long.word 0x04 16.--31. 1. "WCNT,SPI word counter" hexmask.long.byte 0x04 8.--15. 1. "AFL,Buffer almost full this field holds the programmable almost full level value used to determine almost full buffer condition" hexmask.long.byte 0x04 0.--7. 1. "AEL,Buffer almost empty" line.long 0x08 "MCSPI_DAFTX,This register contains the SPI words to be transmitted on the SPI bus when FIFO is used and DMA address is aligned on 256 bit" rgroup.long 0x1A0++0x03 line.long 0x00 "MCSPI_DAFRX,This register contains the SPI words received from the SPI bus when FIFO is used and DMA address is aligned on 256 bit" width 0x0B tree.end tree "MCSPI1_TARG" base ad:0x48099000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCSPI2_TARG" base ad:0x4809B000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCSPI3_TARG" base ad:0x480B9000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCSPI4" base ad:0x480BA000 rgroup.long 0x00++0x07 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any)" hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to 0 and writes to them are ignored" bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter" "Retention mode disabled,Retention mode enabled" bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This field defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "?,FFNBYTE_1_r,FFNBYTE_2_r,?,FFNBYTE_4_r,?,?,?,FFNBYTE_8_r,?,?,?,?,?,?,?,FFNBYTE_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management" "USEFIFO_0_r,USEFIFO_1_r" group.long 0x10++0x03 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" hexmask.long 0x00 4.--31. 1. "RSVD," bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_w" rgroup.long 0x100++0x03 line.long 0x00 "MCSPI_REVISION,This register contains the revision number" group.long 0x110++0x2F line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface and is not affected by software reset" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" bitfld.long 0x00 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "SIDLEMODE,Power management" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wake-up feature control" "ENAWAKEUP_0,ENAWAKEUP_1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock-gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved for module specific status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]" "EOW_0_r,EOW_1_w" bitfld.long 0x08 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "WKS_0_w,WKS_1_r" newline bitfld.long 0x08 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full" "RX3_FULL_0_w,RX3_FULL_1_r" bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow" "TX3_UNDERFLOW_0_w,TX3_UNDERFLOW_1_r" newline bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty" "TX3_EMPTY_0_w,TX3_EMPTY_1_r" bitfld.long 0x08 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full" "RX2_FULL_0_w,RX2_FULL_1_r" newline bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow" "TX2_UNDERFLOW_0_w,TX2_UNDERFLOW_1_r" bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty" "TX2_EMPTY_0_w,TX2_EMPTY_1_r" bitfld.long 0x08 7. "RESERVED,Reads returns 0" "0,1" newline bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full" "RX1_FULL_0_w,RX1_FULL_1_r" bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow" "TX1_UNDERFLOW_0_w,TX1_UNDERFLOW_1_r" bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty" "TX1_EMPTY_0_w,TX1_EMPTY_1_r" newline bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only)" "RX0_OVERFLOW_0_w,RX0_OVERFLOW_1_r" bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full" "RX0_FULL_0_w,RX0_FULL_1_r" bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow" "TX0_UNDERFLOW_0_w,TX0_UNDERFLOW_1_r" newline bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty" "TX0_EMPTY_0_w,TX0_EMPTY_1_r" line.long 0x0C "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis" hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "EOW_ENABLE_0,EOW_ENABLE_1" bitfld.long 0x0C 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "WKE_0,WKE_1" newline bitfld.long 0x0C 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX3_FULL_ENABLE_0,RX3_FULL_ENABLE_1" bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX3_UNDERFLOW_ENABLE_0,TX3_UNDERFLOW_ENABLE_1" newline bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX3_EMPTY_ENABLE_0,TX3_EMPTY_ENABLE_1" bitfld.long 0x0C 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX2_FULL_ENABLE_0,RX2_FULL_ENABLE_1" newline bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX2_UNDERFLOW_ENABLE_0,TX2_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX2_EMPTY_ENABLE_0,TX2_EMPTY_ENABLE_1" bitfld.long 0x0C 7. "RESERVED,Reads return 0" "0,1" newline bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX1_FULL_ENABLE_0,RX1_FULL_ENABLE_1" bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX1_UNDERFLOW_ENABLE_0,TX1_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX1_EMPTY_ENABLE_0,TX1_EMPTY_ENABLE_1" newline bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable" "RX0_OVERFLOW_ENABLE_0,RX0_OVERFLOW_ENABLE_1" bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX0_FULL_ENABLE_0,RX0_FULL_ENABLE_1" bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX0_UNDERFLOW_ENABLE_0,TX0_UNDERFLOW_ENABLE_1" newline bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX0_EMPTY_ENABLE_0,TX0_EMPTY_ENABLE_1" line.long 0x10 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis" hexmask.long 0x10 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x10 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "WKEN_0,WKEN_1" line.long 0x14 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode" hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "SSB_0,SSB_1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "SPIENDIR_0,SPIENDIR_1" newline bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "SPIDATDIR1_0,SPIDATDIR1_1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "SPIDATDIR0_0,SPIDATDIR0_1" bitfld.long 0x14 7. "WAKD,SWAKEUP output (signal data value of internal signal to system)" "WAKD_0,WAKD_1" newline bitfld.long 0x14 6. "SPICLK,SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction) this bit returns the value on the CLKSPI line (high or low) and a write into this bit has no effect" "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction) the SPIDAT[1] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction) the SPIDAT[0] line is driven high or low according to the value written into this bit" "0,1" newline bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[3] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[2] line is driven high or low according to the value written into this bit" "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[1] line is driven high or low according to the value written into this bit" "0,1" newline bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[0] line is driven high or low according to the value written into this bit" "0,1" line.long 0x18 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface" hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA address 256-bit aligned this bit is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address" "FDAA_0,FDAA_1" bitfld.long 0x18 7. "MOA,Multiple word OCP access: this bit can only be used when a channel is enabled using a FIFO" "MOA_0,MOA_1" newline bitfld.long 0x18 4.--6. "INITDLY,Initial SPI delay for first transfer: this field is an option only available in SINGLE master mode" "INITDLY_0,INITDLY_1,INITDLY_2,INITDLY_3,INITDLY_4,?,?,?" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "SYSTEM_TEST_0,SYSTEM_TEST_1" bitfld.long 0x18 2. "MS,Master/slave" "MS_0,MS_1" newline bitfld.long 0x18 1. "PIN34,Pin mode selection: This bit is used in master or slave mode to configure the SPI pin mode (3-pin or 4-pin)" "PIN34_0,PIN34_1" bitfld.long 0x18 0. "SINGLE,Single channel/Multi Channel (master mode only)" "SINGLE_0,SINGLE_1" line.long 0x1C "MCSPI_CHxCONF,This register is dedicated to the configuration of the channel x" rbitfld.long 0x1C 30.--31. "RESERVED,Read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" newline bitfld.long 0x1C 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x1C 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x1C 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" newline bitfld.long 0x1C 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" newline bitfld.long 0x1C 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x1C 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x1C 17. "DPE1,Transmission enable for data line 1" "DPE1_0,DPE1_1" newline bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0" "DPE0_0,DPE0_1" bitfld.long 0x1C 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x1C 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x1C 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" newline bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x1C 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x1C 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" line.long 0x20 "MCSPI_CHxSTAT,This register provides status information about transmitter and receiver registers of channel x" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x20 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x20 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" newline bitfld.long 0x20 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x20 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x20 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" newline bitfld.long 0x20 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x20 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" line.long 0x24 "MCSPI_CHxCTRL,This register is dedicated to enable channel x" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x24 0. "EN,Channel enable" "EN_0,EN_1" line.long 0x28 "MCSPI_TXx,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" line.long 0x2C "MCSPI_RXx,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" group.long 0x17C++0x07 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer" hexmask.long.word 0x00 16.--31. 1. "WCNT,SPI word counter" hexmask.long.byte 0x00 8.--15. 1. "AFL,Buffer almost full this field holds the programmable almost full level value used to determine almost full buffer condition" hexmask.long.byte 0x00 0.--7. 1. "AEL,Buffer almost empty" line.long 0x04 "MCSPI_DAFTX,This register contains the SPI words to be transmitted on the SPI bus when FIFO is used and DMA address is aligned on 256 bit" rgroup.long 0x1A0++0x03 line.long 0x00 "MCSPI_DAFRX,This register contains the SPI words received from the SPI bus when FIFO is used and DMA address is aligned on 256 bit" width 0x0B tree.end tree "MCSPI4_TARG" base ad:0x480BB000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MDIO" base ad:0x48485000 group.long 0x00++0x17 line.long 0x00 "MDIO_VER,MDIO Revision" line.long 0x04 "MDIO_CONTROL,MDIO Control register" bitfld.long 0x04 31. "IDLE,MDIO state machine IDLE" "State machine is not in idle state,State machine is in idle state" newline bitfld.long 0x04 30. "ENABLE,Enable control" "Disables the MDIO state machine,Enable the MDIO state machine" newline rbitfld.long 0x04 29. "RESERVED," "0,1" newline rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "Standard MDIO preamble is used,Disables this device from sending MDIO frame.." newline bitfld.long 0x04 19. "FAULT,Fault indicator" "No failure,Physical layer fault; the.." newline bitfld.long 0x04 18. "FAULTENB,Fault detect enable" "Disables the physical layer fault detection,Enables the physical layer fault detection" newline bitfld.long 0x04 17. "INTTESTENB,Interrupt test enable" "Interrupt bits are not set,Enables the host to set the USERINT and LINKINT.." newline rbitfld.long 0x04 16. "RESERVED," "0,1" newline hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock divider" line.long 0x08 "MDIO_ALIVE,PHY Alive Status Register" line.long 0x0C "MDIO_LINK,PHY Link Status" line.long 0x10 "MDIO_LINKINTRAW," hexmask.long 0x10 2.--31. 1. "RESERVED," newline bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3" line.long 0x14 "MDIO_LINKINTMASKED,MDIO Link Status Change Interrupt Register" hexmask.long 0x14 2.--31. 1. "RESERVED," newline bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3" group.long 0x20++0x0F line.long 0x00 "MDIO_USERINTRAW,MDIO User Command Complete Interrupt" hexmask.long 0x00 2.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "USERINTRAW,Raw value of MDIO user command complete event for theMDIO_USERACCESS1 and MDIO_USERACCESS0 register respectively" "0,1,2,3" line.long 0x04 "MDIO_USERINTMASKED,MDIO User Command Complete Interrupt" hexmask.long 0x04 2.--31. 1. "RESERVED," newline bitfld.long 0x04 0.--1. "USERINTMASKED,Masked value of MDIO user command complete interrupt for theMDIO_USERACCESS1 and MDIO_USERACCESS0 register respectively" "0,1,2,3" line.long 0x08 "MDIO_USERINTMASKSET,MDIO User Command Complete Interrupt Mask Set" hexmask.long 0x08 2.--31. 1. "RESERVED," newline bitfld.long 0x08 0.--1. "USERINTMASKSET,MDIO user interrupt mask set for USERINTMASKED[1:0] respectively" "0,1,2,3" line.long 0x0C "MDIO_USERINTMASKCLR,MDIO User Command Complete Interrupt Mask Clear" hexmask.long 0x0C 2.--31. 1. "RESERVED," newline bitfld.long 0x0C 0.--1. "USERINTMASKCLEAR,MDIO user command complete interrupt mask clear for USERINTMASKED[1:0] respectively" "0,1,2,3" group.long 0x80++0x0F line.long 0x00 "MDIO_USERACCESS0,MDIO_User_Access" bitfld.long 0x00 31. "GO,Go" "0,1" newline bitfld.long 0x00 30. "WRITE,Write enable" "0,1" newline bitfld.long 0x00 29. "ACK,Acknowledge" "0,1" newline rbitfld.long 0x00 26.--28. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--15. 1. "DATA,User data" line.long 0x04 "MDIO_USERPHYSEL0,MDIO User PHY Select" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," newline bitfld.long 0x04 7. "LINKSEL,Link status determination select" "0,1" newline bitfld.long 0x04 6. "LINKINTENB,Link change interrupt enable" "Link change interrupts are disabled,Link change status interrupts for PHY address.." newline rbitfld.long 0x04 5. "RESERVED," "0,1" newline bitfld.long 0x04 0.--4. "PHYADDRMON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "MDIO_USERACCESS1,MDIO User Access" bitfld.long 0x08 31. "GO,Go" "0,1" newline bitfld.long 0x08 30. "WRITE,Write enable" "0,1" newline bitfld.long 0x08 29. "ACK,Acknowledge" "0,1" newline rbitfld.long 0x08 26.--28. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x08 0.--15. 1. "DATA,User data" line.long 0x0C "MDIO_USERPHYSEL1,MDIO User PHY Select" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED," newline bitfld.long 0x0C 7. "LINKSEL,Link status determination select" "0,1" newline bitfld.long 0x0C 6. "LINKINTENB,Link change interrupt enable" "Link change interrupts are disabled,Link change status interrupts for PHY address.." newline rbitfld.long 0x0C 5. "RESERVED," "0,1" newline bitfld.long 0x0C 0.--4. "PHYADDRMON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "MMC" base ad:0x480D1000 rgroup.long 0x00++0x07 line.long 0x00 "MMCHS_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "MMCHS_HL_HWINFO,Information about the IP module's hardware configuration" hexmask.long 0x04 7.--31. 1. "RESERVED," bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "RETMODE_0_r,RETMODE_1_r" bitfld.long 0x04 2.--5. "MEM_SIZE,Memory size for FIFO buffer" "?,MEM_SIZE_1_r,MEM_SIZE_2_r,?,MEM_SIZE_4_r,?,?,?,MEM_SIZE_8_r,?,?,?,?,?,?,?" newline bitfld.long 0x04 1. "MERGE_MEM,Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture" "MERGE_MEM_0_r,MERGE_MEM_1_r" bitfld.long 0x04 0. "MADMA_EN,Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA" "MADMA_EN_0_r,MADMA_EN_1_r" group.long 0x10++0x03 line.long 0x00 "MMCHS_HL_SYSCONFIG,Clock Management Configuration Register" hexmask.long 0x00 4.--31. 1. "RESERVED," bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_r" group.long 0x110++0x07 line.long 0x00 "MMCHS_SYSCONFIG,System Configuration Register This register allows controlling various parameters of the Interconnect interface" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" rbitfld.long 0x00 5.--7. "RESERVED,This bit is initialized to zero and writes to it are ignored" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "SIDLEMODE,Power management" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wakeup feature control" "ENAWAKEUP_0,ENAWAKEUP_1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_r" newline bitfld.long 0x00 0. "AUTOIDLE,Internal Clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMCHS_SYSSTATUS,System Status Register This register provides status information about the module excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "RESETDONE,Internal Reset Monitoring Note: the debounce clock the system clock (Interface) and the functional clock shall be provided to the SDIO host controller to allow the internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" group.long 0x124++0x0F line.long 0x00 "MMCHS_CSRE,Card Status Response Error This register enables the host controller to detect card status errors of response type R1. R1b for all cards and of R5. R5b and R6 response for cards types SD or SDIO" line.long 0x04 "MMCHS_SYSTEST,System Test Register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED," bitfld.long 0x04 13. "WAKD,Wake request output signal data value" "WAKD_0_r,WAKD_1_r" bitfld.long 0x04 12. "SSB,Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (MMCHS_STAT)" "SSB_0_r,SSB_1_r" newline rbitfld.long 0x04 8.--11. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 7. "D3D,DAT3 input/output signal data value" "D3D_0_r,D3D_1_r" bitfld.long 0x04 6. "D2D,DAT2 input/output signal data value" "D2D_0_r,D2D_1_r" newline bitfld.long 0x04 5. "D1D,DAT1 input/output signal data value" "D1D_0_r,D1D_1_r" bitfld.long 0x04 4. "D0D,DAT0 input/output signal data value" "D0D_0_r,D0D_1_r" bitfld.long 0x04 3. "DDIR,Control of the DAT[7:0] pins direction" "DDIR_0_r,DDIR_1_r" newline bitfld.long 0x04 2. "CDAT,CMD input/output signal data value" "CDAT_0_r,CDAT_1_r" bitfld.long 0x04 1. "CDIR,Control of the CMD pin direction" "CDIR_0_r,CDIR_1_r" bitfld.long 0x04 0. "MCKD,SDIO clock output signal data value" "MCKD_0_r,MCKD_1_r" line.long 0x08 "MMCHS_CON,Configuration Register This register is used: - to select the functional mode or the SYSTEST mode for any card" hexmask.long.word 0x08 22.--31. 1. "RESERVED," bitfld.long 0x08 21. "SDMA_LNE,Slave DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCHS_DATA register or late de-assertion request remains active until last allowed data written.." "SDMA_LNE_0,SDMA_LNE_1" bitfld.long 0x08 20. "DMA_MNS,DMA Master or Slave selection: When this bit is set and the controller is configured to use the DMA Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory).This option is only available.." "DMA_MNS_0,DMA_MNS_1" newline bitfld.long 0x08 19. "DDR,Dual Data Rate mode: When this register is set the controller uses both clock edge to emit or receive data" "DDR_0,DDR_1" rbitfld.long 0x08 17.--18. "RESERVED," "0,1,2,3" bitfld.long 0x08 16. "CLKEXTFREE,External clock free running: This register is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]" "CLKEXTFREE_0,CLKEXTFREE_1" newline bitfld.long 0x08 15. "PADEN,Control Power for SDIO Lines: This register is only useful when SDIO PADs contain power saving mechanism to minimize its leakage power" "PADEN_0,PADEN_1" rbitfld.long 0x08 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x08 11. "CTPL,Control Power for DAT[1] line SD cards: By default this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current" "CTPL_0,CTPL_1" newline bitfld.long 0x08 6.--10. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 5. "DW8,8-bit mode MMC select" "DW8_0,DW8_1" bitfld.long 0x08 4. "MODE,Mode select This bit select between Functional mode and SYSTEST mode" "MODE_0,MODE_1" newline rbitfld.long 0x08 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x08 1. "INIT,Send initialization stream All cards" "INIT_0,INIT_1" rbitfld.long 0x08 0. "RESERVED," "0,1" line.long 0x0C "MMCHS_PWCNT,Power Counter Register This register is used to program a counter to delay command transfers after activating the PAD power. this value depends on PAD characteristics and voltage" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," hexmask.long.word 0x0C 0.--15. 1. "PWRCNT,Power counter register" group.long 0x200++0x4B line.long 0x00 "MMCHS_SDMASA,This register contains the physical system memory address used for DMA transfers" line.long 0x04 "MMCHS_BLK,Transfer Length Configuration Register [BLEN] is the block size register" hexmask.long.word 0x04 16.--31. 1. "NBLK,Blocks count for current transfer This register is enabled when Block count Enable (MMCHS_CMD[BCE]) is set to 1 and is valid only for multiple block transfers" rbitfld.long 0x04 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. "BLEN,Transfer Block Size" line.long 0x08 "MMCHS_ARG,Command Argument Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register register)" line.long 0x0C "MMCHS_CMD,Command and Transfer Mode Register [31:16] = the command register [15:0] = the transfer mode" rbitfld.long 0x0C 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x0C 24.--29. "INDX,Command indexBinary encoded value from 0 to 63 specifying the command number send to card" "INDX_0,INDX_1,INDX_2,INDX_3,INDX_4,INDX_5,INDX_6,INDX_7,INDX_8,INDX_9,INDX_10,INDX_11,INDX_12,INDX_13,INDX_14,INDX_15,INDX_16,INDX_17,INDX_18,INDX_19,INDX_20,INDX_21,INDX_22,INDX_23,INDX_24,INDX_25,INDX_26,INDX_27,INDX_28,INDX_29,INDX_30,INDX_31,INDX_32,INDX_33,INDX_34,INDX_35,INDX_36,INDX_37,INDX_38,INDX_39,INDX_40,INDX_41,INDX_42,INDX_43,INDX_44,INDX_45,INDX_46,INDX_47,INDX_48,INDX_49,INDX_50,INDX_51,INDX_52,INDX_53,INDX_54,INDX_55,INDX_56,INDX_57,INDX_58,INDX_59,INDX_60,INDX_61,INDX_62,INDX_63" bitfld.long 0x0C 22.--23. "CMD_TYPE,Command typeThis register specifies three types of special command: Suspend Resume and Abort" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3" newline bitfld.long 0x0C 21. "DP,Data present selectThis register indicates that data is present and DAT line shall be used" "DP_0,DP_1" bitfld.long 0x0C 20. "CICE,Command Index check enableThis bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command" "CICE_0,CICE_1" bitfld.long 0x0C 19. "CCCE,Command CRC check enableThis bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus" "CCCE_0,CCCE_1" newline rbitfld.long 0x0C 18. "RESERVED," "0,1" bitfld.long 0x0C 16.--17. "RSP_TYPE,Response typeThis bits defines the response type of the command" "RSP_TYPE_0,RSP_TYPE_1,RSP_TYPE_2,RSP_TYPE_3" hexmask.long.word 0x0C 6.--15. 1. "RESERVED," newline bitfld.long 0x0C 5. "MSBS,Multi/Single block selectThis bit must be set to 1 for data transfer in case of multi block command" "MSBS_0,MSBS_1" bitfld.long 0x0C 4. "DDIR,Data transfer Direction SelectThis bit defines either data transfer will be a read or a" "DDIR_0,DDIR_1" bitfld.long 0x0C 2.--3. "ACEN,Auto CMD Enable - SD card only.This field determines use of auto command functions" "ACEN_0,ACEN_1,ACEN_2,ACEN_3" newline bitfld.long 0x0C 1. "BCE,Block Count EnableMultiple block transfers only" "BCE_0,BCE_1" bitfld.long 0x0C 0. "DE,DMA EnableThis bit is used to enable DMA mode for host data access" "DE_0,DE_1" line.long 0x10 "MMCHS_RSP10,Command Response[31:0] Register (bits [31:0] of the internal RSP register)" hexmask.long.word 0x10 16.--31. 1. "RSP1,Command Response [31:16]" hexmask.long.word 0x10 0.--15. 1. "RSP0,Command Response [15:0]" line.long 0x14 "MMCHS_RSP32,Command Response[63:32] Register (bits [63:32] of the internal RSP register) This 32-bit register holds bits positions [63:32] of command response type R2" hexmask.long.word 0x14 16.--31. 1. "RSP3,Command Response [63:48]" hexmask.long.word 0x14 0.--15. 1. "RSP2,Command Response [47:32]" line.long 0x18 "MMCHS_RSP54,Command Response[95:64] Register (bits [95:64] of the internal RSP register) This 32-bit register holds bits positions [95:64] of command response type R2" hexmask.long.word 0x18 16.--31. 1. "RSP5,Command Response [95:80]" hexmask.long.word 0x18 0.--15. 1. "RSP4,Command Response [79:64]" line.long 0x1C "MMCHS_RSP76,Command Response[127:96] Register (bits [127:96] of the internal RSP register) This 32-bit register holds bits positions [127:96] of command response type R1/R1b(Auto CMD12)/R2" hexmask.long.word 0x1C 16.--31. 1. "RSP7,Command Response [127:112]" hexmask.long.word 0x1C 0.--15. 1. "RSP6,Command Response [111:96]" line.long 0x20 "MMCHS_DATA,Data Register This register is the 32-bit entry point of the buffer for read or write data transfers" line.long 0x24 "MMCHS_PSTATE,Present State Register The Host can get status of the Host Controller from this 32-bit read only register" hexmask.long.byte 0x24 25.--31. 1. "RESERVED," bitfld.long 0x24 24. "CLEV,CMD line signal level This status is used to check the CMD line level to recover from errors and for debugging" "CLEV_0_r,CLEV_1_r" bitfld.long 0x24 20.--23. "DLEV,DAT[3:0] line signal level DAT[3] => bit 23 DAT[2] => bit 22 DAT[1] => bit 21 DAT[0] => bit 20 This status is used to check DAT line level to recover from errors and for debugging" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x24 12.--19. 1. "RESERVED," bitfld.long 0x24 11. "BRE,Buffer read enable This bit is used for non-DMA read transfers" "BRE_0_r,BRE_1_r" bitfld.long 0x24 10. "BWE,Buffer Write enable This status is used for non-DMA write transfers" "BWE_0_r,BWE_1_r" newline bitfld.long 0x24 9. "RTA,Read transfer active This status is used for detecting completion of a read transfer" "RTA_0_r,RTA_1_r" bitfld.long 0x24 8. "WTA,Write transfer active This status indicates a write transfer active" "WTA_0_r,WTA_1_r" bitfld.long 0x24 3.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x24 2. "DLA,DAT line active This status bit indicates whether one of the DAT line is in use" "DLA_0_r,DLA_1_r" bitfld.long 0x24 1. "DATI,Command inhibit(DAT) This status bit is generated if either DAT line is active (MMCHS_PSTATE[DLA]) or Read transfer is active (MMCHS_PSTATE[RTA]) or when a command with busy is issued" "DATI_0_r,DATI_1_r" bitfld.long 0x24 0. "CMDI,Command inhibit(CMD) This status bit indicates that the CMD line is in use" "CMDI_0_r,CMDI_1_r" line.long 0x28 "MMCHS_HCTL,Host Control Register This register defines the host controls to set power. wakeup and transfer parameters" hexmask.long.byte 0x28 25.--31. 1. "RESERVED," bitfld.long 0x28 24. "IWE,Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion" "IWE_0,IWE_1" rbitfld.long 0x28 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 19. "IBG,Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer" "IBG_0,IBG_1" bitfld.long 0x28 18. "RWC,Read wait control The read wait function is optional only for SDIO cards" "RWC_0,RWC_1" bitfld.long 0x28 17. "CR,Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (MMCHS_HCTL[SBGR])" "CR_0,CR_1" newline bitfld.long 0x28 16. "SBGR,Stop at block gap request This bit is used to stop executing a transaction at the next block gap" "SBGR_0,SBGR_1" rbitfld.long 0x28 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x28 9.--11. "SDVS,SD bus voltage select All cards" "?,?,?,?,?,SDVS_5,SDVS_6,SDVS_7" newline bitfld.long 0x28 8. "SDBP,SD bus power Before setting this bit the host driver shall select the SD bus voltage (MMCHS_HCTL[SDVS])" "SDBP_0,SDBP_1" rbitfld.long 0x28 3.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 2. "HSPE,Before setting this bit the Host Driver shall check theMMCHS_CAPA[21] HSS" "HSPE_0,HSPE_1" newline bitfld.long 0x28 1. "DTW,Data transfer width For SD/SDIO cards this bit must be set following a valid SET_BUS_WIDTH command (ACMD6) with the value written in bit 1 of the argument" "DTW_0,DTW_1" rbitfld.long 0x28 0. "RESERVED," "0,1" line.long 0x2C "MMCHS_SYSCTL,SD System Control Register This register defines the system controls to set software resets. clock frequency management and data timeout" rbitfld.long 0x2C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x2C 26. "SRD,Software reset for DAT line This bit is set to 1 for reset and released to 0 when completed" "SRD_0,SRD_1" bitfld.long 0x2C 25. "SRC,Software reset for CMD line For more information about SRC bit manipulation see" "SRC_0,SRC_1" newline bitfld.long 0x2C 24. "SRA,Software reset for all This bit is set to 1 for reset and released to 0 when completed" "SRA_0,SRA_1" rbitfld.long 0x2C 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x2C 16.--19. "DTO,Data timeout counter value and busy timeout" "DTO_0,DTO_1,?,?,?,?,?,?,?,?,?,?,?,?,DTO_14,DTO_15" newline hexmask.long.word 0x2C 6.--15. 1. "CLKD,Clock frequency select These bits define the ratio between MMC_FCLK and the output clock frequency on the mmc_clk pin" rbitfld.long 0x2C 5. "CGS,Clock Generator Select - For SD cards Host Controller Version 3.00 supports this bit" "0,1" rbitfld.long 0x2C 3.--4. "RESERVED," "0,1,2,3" newline bitfld.long 0x2C 2. "CEN,Clock enable This bit controls if the clock is provided to the card or not" "CEN_0,CEN_1" rbitfld.long 0x2C 1. "ICS,Internal clock stable (status) This bit indicates either the internal clock is stable or not" "ICS_0_r,ICS_1_r" bitfld.long 0x2C 0. "ICE,Internal clock enable This register controls the internal clock activity" "ICE_0,ICE_1" line.long 0x30 "MMCHS_STAT,Interrupt Status Register The interrupt status regroups all the status of the module internal events that can generate an interrupt" rbitfld.long 0x30 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x30 29. "BADA,Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register (MMCHS_DATA) while buffer reads are not allowed (MMCHS_PSTATE[BRE] =0) -This bit.." "BADA_0_r,BADA_1_r" bitfld.long 0x30 28. "CERR,Card error This bit is set automatically when there is at least one error in a response of type R1 R1b R6 R5 or R5b" "CERR_0_r,CERR_1_r" newline rbitfld.long 0x30 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x30 24. "ACE,Auto CMD error Auto CMD12 uses this error status" "ACE_0_r,ACE_1_r" rbitfld.long 0x30 23. "RESERVED," "0,1" newline bitfld.long 0x30 22. "DEB,Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode" "DEB_0_r,DEB_1_r" bitfld.long 0x30 21. "DCRC,Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command" "DCRC_0_r,DCRC_1_r" bitfld.long 0x30 20. "DTO,Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout" "DTO_0_r,DTO_1_r" newline bitfld.long 0x30 19. "CIE,Command index error This bit is set automatically when response index differs from corresponding command index previously emitted" "CIE_0_r,CIE_1_r" bitfld.long 0x30 18. "CEB,Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response" "CEB_0_r,CEB_1_r" bitfld.long 0x30 17. "CCRC,Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCHS_CMD[CCCE] register" "CCRC_0_r,CCRC_1_r" newline bitfld.long 0x30 16. "CTO,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command" "CTO_0_r,CTO_1_r" rbitfld.long 0x30 15. "ERRI,Error Interrupt If any of the bits in the Error Interrupt Status register (MMCHS_STAT[31:16]) are set then this bit is set to 1" "ERRI_0_r,ERRI_1_r" rbitfld.long 0x30 9.--14. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x30 8. "CIRQ,Card interrupt This bit is only used for SD and SDIO cards" "CIRQ_0_r,CIRQ_1_r" rbitfld.long 0x30 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x30 5. "BRR,Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by MMCHS_BLK[BLEN] is completely written in the buffer" "BRR_0_r,BRR_1_r" newline bitfld.long 0x30 4. "BWR,Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCHS_BLK[BLEN]" "BWR_0_r,BWR_1_r" rbitfld.long 0x30 3. "RESERVED," "0,1" bitfld.long 0x30 2. "BGE,Block gap event When a stop at block gap is requested (MMCHS_HCTL[SBGR]) this bit is automatically set when transaction is stopped at the block gap during a read or write operation" "BGE_0_r,BGE_1_r" newline bitfld.long 0x30 1. "TC,Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCHS_HCTL[SBGR])" "TC_0_r,TC_1_r" bitfld.long 0x30 0. "CC,Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCHS_PSTATE[CMDI]) If the command is a type for which no response is expected then the command complete interrupt is generated at the end of the command" "CC_0_r,CC_1_r" line.long 0x34 "MMCHS_IE,Interrupt Status Enable Register This register allows to enable/disable the module to set status bits. on an event-by-event basis" rbitfld.long 0x34 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x34 29. "BADA_ENABLE,Bad access to data space Status Enable" "BADA_ENABLE_0,BADA_ENABLE_1" bitfld.long 0x34 28. "CERR_ENABLE,Card Error Status Enable" "CERR_ENABLE_0,CERR_ENABLE_1" newline rbitfld.long 0x34 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x34 24. "ACE_ENABLE,Auto CMD Error Status Enable" "ACE_ENABLE_0,ACE_ENABLE_1" rbitfld.long 0x34 23. "RESERVED," "0,1" newline bitfld.long 0x34 22. "DEB_ENABLE,Data End Bit Error Status Enable" "DEB_ENABLE_0,DEB_ENABLE_1" bitfld.long 0x34 21. "DCRC_ENABLE,Data CRC Error Status Enable" "DCRC_ENABLE_0,DCRC_ENABLE_1" bitfld.long 0x34 20. "DTO_ENABLE,Data Timeout Error Status Enable" "DTO_ENABLE_0,DTO_ENABLE_1" newline bitfld.long 0x34 19. "CIE_ENABLE,Command Index Error Status Enable" "CIE_ENABLE_0,CIE_ENABLE_1" bitfld.long 0x34 18. "CEB_ENABLE,Command End Bit Error Status Enable" "CEB_ENABLE_0,CEB_ENABLE_1" bitfld.long 0x34 17. "CCRC_ENABLE,Command CRC Error Status Enable" "CCRC_ENABLE_0,CCRC_ENABLE_1" newline bitfld.long 0x34 16. "CTO_ENABLE,Command Timeout Error Status Enable" "CTO_ENABLE_0,CTO_ENABLE_1" rbitfld.long 0x34 15. "NULL,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register" "0,1" rbitfld.long 0x34 9.--14. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x34 8. "CIRQ_ENABLE,Card Status Enable A clear of this bit also clears the corresponding status bit" "CIRQ_ENABLE_0,CIRQ_ENABLE_1" rbitfld.long 0x34 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x34 5. "BRR_ENABLE,Buffer Read Ready Status Enable" "BRR_ENABLE_0,BRR_ENABLE_1" newline bitfld.long 0x34 4. "BWR_ENABLE,Buffer Write Ready Status Enable" "BWR_ENABLE_0,BWR_ENABLE_1" rbitfld.long 0x34 3. "RESERVED," "0,1" bitfld.long 0x34 2. "BGE_ENABLE,Block Gap Event Status Enable" "BGE_ENABLE_0,BGE_ENABLE_1" newline bitfld.long 0x34 1. "TC_ENABLE,Transfer Complete Status Enable" "TC_ENABLE_0,TC_ENABLE_1" bitfld.long 0x34 0. "CC_ENABLE,Command Complete Status Enable" "CC_ENABLE_0,CC_ENABLE_1" line.long 0x38 "MMCHS_ISE,Interrupt Signal Enable Register This register allows to enable/disable the module internal sources of status. on an event-by-event basis" rbitfld.long 0x38 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x38 29. "BADA_SIGEN,Bad access to data space Signal Enable" "BADA_SIGEN_0,BADA_SIGEN_1" bitfld.long 0x38 28. "CERR_SIGEN,Card Error Interrupt Signal Enable" "CERR_SIGEN_0,CERR_SIGEN_1" newline rbitfld.long 0x38 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x38 24. "ACE_SIGEN,Auto CMD Error Signal Enable" "ACE_SIGEN_0,ACE_SIGEN_1" rbitfld.long 0x38 23. "RESERVED," "0,1" newline bitfld.long 0x38 22. "DEB_SIGEN,Data End Bit Error Signal Enable" "DEB_SIGEN_0,DEB_SIGEN_1" bitfld.long 0x38 21. "DCRC_SIGEN,Data CRC Error Signal Enable" "DCRC_SIGEN_0,DCRC_SIGEN_1" bitfld.long 0x38 20. "DTO_SIGEN,Data Timeout Error Signal Enable" "DTO_SIGEN_0,DTO_SIGEN_1" newline bitfld.long 0x38 19. "CIE_SIGEN,Command Index Error Signal Enable" "CIE_SIGEN_0,CIE_SIGEN_1" bitfld.long 0x38 18. "CEB_SIGEN,Command End Bit Error Signal Enable" "CEB_SIGEN_0,CEB_SIGEN_1" bitfld.long 0x38 17. "CCRC_SIGEN,Command CRC Error Signal Enable" "CCRC_SIGEN_0,CCRC_SIGEN_1" newline bitfld.long 0x38 16. "CTO_SIGEN,Command timeout Error Signal Enable" "CTO_SIGEN_0,CTO_SIGEN_1" rbitfld.long 0x38 15. "NULL,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register" "0,1" rbitfld.long 0x38 9.--14. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x38 8. "CIRQ_SIGEN,Card Interrupt Signal Enable" "CIRQ_SIGEN_0,CIRQ_SIGEN_1" rbitfld.long 0x38 6.--7. "RESERVED," "0,1,2,3" bitfld.long 0x38 5. "BRR_SIGEN,Buffer Read Ready Signal Enable" "BRR_SIGEN_0,BRR_SIGEN_1" newline bitfld.long 0x38 4. "BWR_SIGEN,Buffer Write Ready Signal Enable" "BWR_SIGEN_0,BWR_SIGEN_1" rbitfld.long 0x38 3. "RESERVED," "0,1" bitfld.long 0x38 2. "BGE_SIGEN,Black Gap Event Signal Enable" "BGE_SIGEN_0,BGE_SIGEN_1" newline bitfld.long 0x38 1. "TC_SIGEN,Transfer Completed Status Enable" "TC_SIGEN_0,TC_SIGEN_1" bitfld.long 0x38 0. "CC_SIGEN,Command Complete Status Enable" "CC_SIGEN_0,CC_SIGEN_1" line.long 0x3C "MMCHS_AC12,Host Control 2 Register and Auto CMD Error Status Register This register is used to indicate CMD12 response error of Auto CMD12" bitfld.long 0x3C 31. "PV_ENABLE,Preset Value Enable Host Controller Version 3.00 supports this bit" "PV_ENABLE_0,PV_ENABLE_1" bitfld.long 0x3C 30. "AI_ENABLE,Asynchronous Interrupt Enable This bit can be set to 1 if a card supports asynchronous interrupts and MMCHS_CAPA[29] AIS is set to 1" "AI_ENABLE_0,AI_ENABLE_1" hexmask.long.byte 0x3C 22.--29. 1. "RESERVED," newline bitfld.long 0x3C 20.--21. "DS_SEL,Driver Strength Select Host Controller output driver in 1.8V signaling is selected by this bit" "DS_SEL_0,DS_SEL_1,DS_SEL_2,DS_SEL_3" bitfld.long 0x3C 19. "V1V8_SIGEN,1.8V Signaling Enable This bit controls voltage regulator for I/O cell" "V1V8_SIGEN_0,V1V8_SIGEN_1" bitfld.long 0x3C 16.--18. "UHSMS,UHS Mode Select This field is used to select one of UHS-I modes and effective when 1.8V Signaling Enable is set to 1" "UHSMS_0,UHSMS_1,?,?,?,?,?,?" newline hexmask.long.byte 0x3C 8.--15. 1. "RESERVED," rbitfld.long 0x3C 7. "CNI,Command Not Issued By Auto CMD12 Error Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register" "CNI_0_r,CNI_1_r" rbitfld.long 0x3C 5.--6. "RESERVED," "0,1,2,3" newline rbitfld.long 0x3C 4. "ACIE,Auto CMD Index Error for Auto CMD12 This bit is set if the Command Index error occurs in response to a command" "ACIE_0_r,ACIE_1_r" rbitfld.long 0x3C 3. "ACEB,Auto CMD End Bit Error for Auto CMD12 This bit is set when detecting that the end bit of command response is 0" "ACEB_0_r,ACEB_1_r" rbitfld.long 0x3C 2. "ACCE,Auto CMD CRC Error for Auto CMD12 This bit is set when detecting a CRC error in the command response" "ACCE_0_r,ACCE_1_r" newline rbitfld.long 0x3C 1. "ACTO,Auto CMD Timeout Error for Auto CMD12 This bit is set if no response is returned within 64 SDCLK cycles from the end bit of command" "ACTO_0_r,ACTO_1_r" rbitfld.long 0x3C 0. "ACNE,Auto CMD12 Not Executed If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12" "ACNE_0_r,ACNE_1_r" line.long 0x40 "MMCHS_CAPA,Capabilities Register This register lists the capabilities of the SDIO host controller" rbitfld.long 0x40 30.--31. "RESERVED," "0,1,2,3" rbitfld.long 0x40 29. "AIS,Asynchronous Interrupt Support Refer to SDIO Specification Version 3.00 about asynchronous interrupt" "AIS_0_r,AIS_1_r" rbitfld.long 0x40 28. "BIT64,64 Bit System Bus Support Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus" "BIT64_0_r,BIT64_1_r" newline rbitfld.long 0x40 27. "RESERVED," "0,1" bitfld.long 0x40 26. "VS18,Voltage support 1.8V Initialization of this register (via a write access to this register) depends on the system capabilities" "VS18_0_r,VS18_1_r" bitfld.long 0x40 25. "VS30,Voltage support 3.0V Initialization of this register (via a write access to this register) depends on the system capabilities" "VS30_0_r,VS30_1_r" newline bitfld.long 0x40 24. "VS33,Voltage support 3.3V Initialization of this register (via a write access to this register) depends on the system capabilities" "VS33_0_r,VS33_1_r" rbitfld.long 0x40 23. "SRS,Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports Suspend/Resume functionality" "SRS_0_r,SRS_1_r" rbitfld.long 0x40 22. "DS,DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly" "DS_0_r,DS_1_r" newline rbitfld.long 0x40 21. "HSS,High speed support This bit indicates that the host controller supports high speed operations and can supply an up-to maximum card frequency" "HSS_0_r,HSS_1_r" rbitfld.long 0x40 20. "RESERVED," "0,1" rbitfld.long 0x40 19. "AD2S,ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2" "AD2S_0_r,AD2S_1_r" newline rbitfld.long 0x40 18. "RESERVED," "0,1" rbitfld.long 0x40 16.--17. "MBL,Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller" "MBL_0_r,MBL_1_r,MBL_2_r,?" abitfld.long 0x40 8.--15. "BCF,Base Clock Frequency For SD Clock This value indicates the base (maximum) clock frequency for the SD Clock" "0x00=Get information via..,0x01=1MHz,0x02=2MHz,0xFF=255MHz" newline rbitfld.long 0x40 7. "TCU,Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCHS_STAT[DTO])" "TCU_0_r,TCU_1_r" rbitfld.long 0x40 6. "RESERVED," "0,1" rbitfld.long 0x40 0.--5. "TCF,Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (MMCHS_STAT[DTO])" "TCF_0_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x44 "MMCHS_CAPA2,Capabilities 2 Register This register provides the Host Driver with information specific to the Host Controller implementation" hexmask.long.byte 0x44 24.--31. 1. "RESERVED," abitfld.long 0x44 16.--23. "CM,Clock Multiplier This field indicates clock multiplier value of programmable clock generator" "0x00=Clock Multiplier is Not Supported,0x01=Clock Multiplier M = 2,0x02=Clock Multiplier M = 3,0xFF=Clock Multiplier M = 256" bitfld.long 0x44 14.--15. "RTM,Re-Tuning Modes This field selects re-tuning method and limits the maximum data length" "RTM_0_r,RTM_1_r,RTM_2_r,RTM_3_r" newline bitfld.long 0x44 13. "TSDR50,Use Tuning for SDR50 If this bit is set to 1 this Host Controller requires tuning to operate SDR50" "TSDR50_0_r,TSDR50_1_r" bitfld.long 0x44 12. "RESERVED," "0,1" bitfld.long 0x44 8.--11. "TCRT,Timer Count for Re-Tuning This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3" "TCRT_0_r,TCRT_1_r,TCRT_2_r,TCRT_3_r,TCRT_4_r,TCRT_5_r,TCRT_6_r,TCRT_7_r,TCRT_8_r,TCRT_9_r,TCRT_10_r,TCRT_11_r,TCRT_12_r,TCRT_13_r,TCRT_14_r,TCRT_15_r" newline bitfld.long 0x44 7. "RESERVED," "0,1" bitfld.long 0x44 6. "DTD,Driver Type D Support This bit indicates support of Driver Type D for 1.8 Signaling" "DTD_0_r,DTD_1_r" bitfld.long 0x44 5. "DTC,Driver Type C Support This bit indicates support of Driver Type C for 1.8 Signaling" "DTC_0_r,DTC_1_r" newline bitfld.long 0x44 4. "DTA,Driver Type A Support This bit indicates support of Driver Type A for 1.8 Signaling" "DTA_0_r,DTA_1_r" bitfld.long 0x44 3. "RESERVED," "0,1" bitfld.long 0x44 2. "DDR50,DDR50 Support" "DDR50_0_r,DDR50_1_r" newline bitfld.long 0x44 1. "SDR104,SDR104 Support" "SDR104_0_r,SDR104_1_r" bitfld.long 0x44 0. "SDR50,SDR50 Support If SDR104 is supported this bit shall be set to 1" "SDR50_0_r,SDR50_1_r" line.long 0x48 "MMCHS_CUR_CAPA,Maximum Current Capabilities Register This register indicates the maximum current capability for each voltage" hexmask.long.byte 0x48 24.--31. 1. "RESERVED," hexmask.long.byte 0x48 16.--23. 1. "CUR_1V8,Maximum current for 1.8V" hexmask.long.byte 0x48 8.--15. 1. "CUR_3V0,Maximum current for 3.0V" newline hexmask.long.byte 0x48 0.--7. 1. "CUR_3V3,Maximum current for 3.3V" group.long 0x250++0x03 line.long 0x00 "MMCHS_FE,Force Event Register for Auto CMD Error Status and Error Interrupt status The Force Event Register is not a physically implemented register" bitfld.long 0x00 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x00 29. "FE_BADA,Force Event Bad access to data space" "FE_BADA_0_w,FE_BADA_1_w" bitfld.long 0x00 28. "FE_CERR,Force Event Card error" "FE_CERR_0_w,FE_CERR_1_w" newline bitfld.long 0x00 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 24. "FE_ACE,Force Event for Auto CMD Error - For Auto CMD12" "FE_ACE_0_w,FE_ACE_1_w" bitfld.long 0x00 23. "RESERVED," "0,1" newline bitfld.long 0x00 22. "FE_DEB,Force Event Data End Bit error" "FE_DEB_0_w,FE_DEB_1_w" bitfld.long 0x00 21. "FE_DCRC,Force Event Data CRC Error" "FE_DCRC_0_w,FE_DCRC_1_w" bitfld.long 0x00 20. "FE_DTO,Force Event Data Timeout Error" "FE_DTO_0_w,FE_DTO_1_w" newline bitfld.long 0x00 19. "FE_CIE,Force Event Command Index Error" "FE_CIE_0_w,FE_CIE_1_w" bitfld.long 0x00 18. "FE_CEB,Force Event Command End Bit Error" "FE_CEB_0_w,FE_CEB_1_w" bitfld.long 0x00 17. "FE_CCRC,Force Event Command CRC Error" "FE_CCRC_0_w,FE_CCRC_1_w" newline bitfld.long 0x00 16. "FE_CTO,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command" "FE_CTO_0_w,FE_CTO_1_w" hexmask.long.byte 0x00 8.--15. 1. "RESERVED," bitfld.long 0x00 7. "FE_CNI,Force Event Command not issued by Auto CMD12 error" "FE_CNI_0_w,FE_CNI_1_w" newline bitfld.long 0x00 5.--6. "RESERVED," "0,1,2,3" bitfld.long 0x00 4. "FE_ACIE,Force Event for Auto CMD Index Error - For Auto CMD12" "FE_ACIE_0_w,FE_ACIE_1_w" bitfld.long 0x00 3. "FE_ACEB,Force Event Auto CMD End Bit Error" "FE_ACEB_0_w,FE_ACEB_1_w" newline bitfld.long 0x00 2. "FE_ACCE,Force Event Auto CMD CRC Error" "FE_ACCE_0_w,FE_ACCE_1_w" bitfld.long 0x00 1. "FE_ACTO,Force Event Auto CMD Timeout Error" "FE_ACTO_0_w,FE_ACTO_1_w" bitfld.long 0x00 0. "FE_ACNE,Force Event Auto CMD12 Not Executed" "FE_ACNE_0_w,FE_ACNE_1_w" rgroup.long 0x260++0x0B line.long 0x00 "MMCHS_PVINITSD,Preset Value for Initialization and Default Speed modes" bitfld.long 0x00 30.--31. "DSDS_SEL,Driver Strength Select Value - Default Speed mode Driver Strength is supported by 1.8V signaling bus speed modes" "DSDS_SEL_0_r,DSDS_SEL_1_r,DSDS_SEL_2_r,DSDS_SEL_3_r" bitfld.long 0x00 27.--29. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x00 26. "DSCLKGEN_SEL,Clock Generator Select Value - Default Speed mode This bit is effective when Host Controller supports programmable clock generator" "DSCLKGEN_SEL_0_r,DSCLKGEN_SEL_1_r" newline hexmask.long.word 0x00 16.--25. 1. "DSSDCLK_SEL,SDCLK Frequency Select Value - Default Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" bitfld.long 0x00 14.--15. "INITDS_SEL,Driver Strength Select Value - Initialization mode Driver Strength is supported by 1.8V signaling bus speed modes" "INITDS_SEL_0_r,INITDS_SEL_1_r,INITDS_SEL_2_r,INITDS_SEL_3_r" bitfld.long 0x00 11.--13. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10. "INITCLKGEN_SEL,Clock Generator Select Value - Initialization mode This bit is effective when Host Controller supports programmable clock generator" "INITCLKGEN_SEL_0_r,INITCLKGEN_SEL_1_r" hexmask.long.word 0x00 0.--9. 1. "INITSDCLK_SEL,SDCLK Frequency Select Value - Initialization mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" line.long 0x04 "MMCHS_PVHSSDR12,Preset Value for High Speed and SDR12 speed modes" bitfld.long 0x04 30.--31. "SDR12DS_SEL,Driver Strength Select Value - SDR12 mode Driver Strength is supported by 1.8V signaling bus speed modes" "SDR12DS_SEL_0_r,SDR12DS_SEL_1_r,SDR12DS_SEL_2_r,SDR12DS_SEL_3_r" bitfld.long 0x04 27.--29. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 26. "SDR12CLKGEN_SEL,Clock Generator Select Value - SDR12 mode This bit is effective when Host Controller supports programmable clock generator" "SDR12CLKGEN_SEL_0_r,SDR12CLKGEN_SEL_1_r" newline hexmask.long.word 0x04 16.--25. 1. "SDR12SDCLK_SEL,SDCLK Frequency Select Value - SDR12 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" bitfld.long 0x04 14.--15. "HSDS_SEL,Driver Strength Select Value - High Speed mode Driver Strength is supported by 1.8V signaling bus speed modes" "HSDS_SEL_0_r,HSDS_SEL_1_r,HSDS_SEL_2_r,HSDS_SEL_3_r" bitfld.long 0x04 11.--13. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 10. "HSCLKGEN_SEL,Clock Generator Select Value - High Speed mode This bit is effective when Host Controller supports programmable clock generator" "HSCLKGEN_SEL_0_r,HSCLKGEN_SEL_1_r" hexmask.long.word 0x04 0.--9. 1. "HSSDCLK_SEL,SDCLK Frequency Select Value - High Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" line.long 0x08 "MMCHS_PVSDR25SDR50,Preset Value for SDR25 speed mode" hexmask.long.word 0x08 16.--31. 1. "RESERVED," bitfld.long 0x08 14.--15. "SDR25DS_SEL,Driver Strength Select Value - SDR25 mode Driver Strength is supported by 1.8V signaling bus speed modes" "SDR25DS_SEL_0_r,SDR25DS_SEL_1_r,SDR25DS_SEL_2_r,SDR25DS_SEL_3_r" bitfld.long 0x08 11.--13. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 10. "SDR25CLKGEN_SEL,Clock Generator Select Value - SDR25 mode This bit is effective when Host Controller supports programmable clock generator" "SDR25CLKGEN_SEL_0_r,SDR25CLKGEN_SEL_1_r" hexmask.long.word 0x08 0.--9. 1. "SDR25SDCLK_SEL,SDCLK Frequency Select Value - SDR25 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" rgroup.long 0x2FC++0x03 line.long 0x00 "MMCHS_REV,Versions Register This register contains the hard coded RTL vendor revision number. the version number of SD specification compliancy and a slot status bit" hexmask.long.byte 0x00 24.--31. 1. "VREV,Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" hexmask.long.byte 0x00 16.--23. 1. "SREV,Specification Version Number This status indicates the Host Controller Spec" hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "SIS,Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module" "0,1" width 0x0B tree.end tree "MMC_TARG" base ad:0x480D2000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MMU_TARG" base ad:0x44002200 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "MMU_TARG" base ad:0x4881D000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MPU_CM_CORE_AON" base ad:0x4A005300 group.long 0x00++0x0B line.long 0x00 "CM_MPU_CLKSTCTRL,This register enables the MPU domain power state transition" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," rbitfld.long 0x00 8. "CLKACTIVITY_MPU_GCLK,This field indicates the state of the MPU_DPLL_CLK clock in the domain" "CLKACTIVITY_MPU_GCLK_0,CLKACTIVITY_MPU_GCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the MPU clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_MPU_STATICDEP,This register controls the static domain depedencies from MPU domain towards 'target' domains" rbitfld.long 0x04 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE clock domain" "PCIE_STATDEP_0,PCIE_STATDEP_1" newline bitfld.long 0x04 28. "ISS_STATDEP,Static dependency towards ISS clock domain" "ISS_STATDEP_0,ISS_STATDEP_1" bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain" "GMAC_STATDEP_0,GMAC_STATDEP_1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain" "IPU_STATDEP_0,IPU_STATDEP_1" bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domain" "EVE4_STATDEP_0,EVE4_STATDEP_1" bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domain" "EVE3_STATDEP_0,EVE3_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain" "EVE2_STATDEP_0,EVE2_STATDEP_1" bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain" "EVE1_STATDEP_0,EVE1_STATDEP_1" newline bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain" "DSP2_STATDEP_0,DSP2_STATDEP_1" rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain" "CUSTEFUSE_STATDEP_0,?" newline rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain" "COREAON_STATDEP_0,?" bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER clock domain" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" rbitfld.long 0x04 11. "SDMA_STATDEP,Static dependency towards SDMA clock domain" "SDMA_STATDEP_0,?" newline bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU clock domain" "GPU_STATDEP_0,GPU_STATDEP_1" bitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain" "CAM_STATDEP_0,CAM_STATDEP_1" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain" "DSS_STATDEP_0,DSS_STATDEP_1" bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline rbitfld.long 0x04 6. "RESERVED," "0,1" bitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN clock domain" "L3MAIN1_STATDEP_0,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain" "EMIF_STATDEP_0,EMIF_STATDEP_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain" "IVA_STATDEP_0,IVA_STATDEP_1" bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP1 clock domain" "DSP1_STATDEP_0,DSP1_STATDEP_1" newline bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_MPU_DYNAMICDEP,This register controls the dynamic domain depedencies from MPU domain towards 'target' domains" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.tbyte 0x08 6.--23. 1. "RESERVED," rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x08 4. "EMIF_DYNDEP,Dynamic dependency towards EMIF clock domain" "?,EMIF_DYNDEP_1" rbitfld.long 0x08 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x03 line.long 0x00 "CM_MPU_MPU_CLKCTRL,This register manages the MPU clocks" rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 26. "CLKSEL_ABE_DIV_MODE,Selects the ratio for MPU - ABE async bridge versus MPU DPLL clock" "CLKSEL_ABE_DIV_MODE_0,CLKSEL_ABE_DIV_MODE_1" newline bitfld.long 0x00 24.--25. "CLKSEL_EMIF_DIV_MODE,Selects the ratio for MPU - L3 async bridge versus MPU DPLL clock" "CLKSEL_EMIF_DIV_MODE_0,CLKSEL_EMIF_DIV_MODE_1,CLKSEL_EMIF_DIV_MODE_2,CLKSEL_EMIF_DIV_MODE_3" rbitfld.long 0x00 19.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," rbitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x28++0x03 line.long 0x00 "CM_MPU_MPU_MPU_DBG_CLKCTRL,This register manages the MPU_MPU_DBG clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" width 0x0B tree.end tree "MPU_PRM" base ad:0x4AE06300 group.long 0x00++0x07 line.long 0x00 "PM_MPU_PWRSTCTRL,This register controls the MPU domain power state to reach upon a domain sleep transition" hexmask.long.word 0x00 22.--31. 1. "RESERVED," rbitfld.long 0x00 20.--21. "MPU_RAM_ONSTATE,MPU_RAM memory state when domain is ON" "?,?,?,MPU_RAM_ONSTATE_3" rbitfld.long 0x00 18.--19. "MPU_L2_ONSTATE,MPU_L2 memory state when domain is ON" "?,?,?,MPU_L2_ONSTATE_3" newline hexmask.long.byte 0x00 11.--17. 1. "RESERVED," rbitfld.long 0x00 10. "MPU_RAM_RETSTATE,MPU_RAM memory state when domain is RETENTION" "?,MPU_RAM_RETSTATE_1" bitfld.long 0x00 9. "MPU_L2_RETSTATE,MPU_L2 memory state when domain is RETENTION" "MPU_L2_RETSTATE_0,MPU_L2_RETSTATE_1" newline rbitfld.long 0x00 5.--8. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,?" rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION" "LOGICRETSTATE_0,LOGICRETSTATE_1" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_MPU_PWRSTST,This register provides a status on the MPU domain current power state" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 20. "INTRANSITION,Domain transition status" "INTRANSITION_0,INTRANSITION_1" hexmask.long.word 0x04 10.--19. 1. "RESERVED," rbitfld.long 0x04 8.--9. "MPU_RAM_STATEST,MPU_RAM memory state status" "MPU_RAM_STATEST_0,MPU_RAM_STATEST_1,MPU_RAM_STATEST_2,MPU_RAM_STATEST_3" newline rbitfld.long 0x04 6.--7. "MPU_L2_STATEST,MPU_L2 memory state status" "MPU_L2_STATEST_0,MPU_L2_STATEST_1,MPU_L2_STATEST_2,MPU_L2_STATEST_3" rbitfld.long 0x04 3.--5. "RESERVED," "0,1,2,3,4,5,6,7" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_MPU_MPU_CONTEXT,This register contains dedicated MPU context statuses" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," bitfld.long 0x00 10. "LOSTMEM_MPU_RAM,Specify if memory-based context in MPU_RAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_MPU_RAM_0,LOSTMEM_MPU_RAM_1" bitfld.long 0x00 9. "LOSTMEM_MPU_L2,Specify if memory-based context in MPU_L2 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_MPU_L2_0,LOSTMEM_MPU_L2_1" newline hexmask.long.byte 0x00 2.--8. 1. "RESERVED," bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "OCMC_RAM" base ad:0x48804000 rgroup.long 0x00++0x0F line.long 0x00 "OCMC_ECC_PID," line.long 0x04 "OCMC_SYSCONFIG_PM," hexmask.long 0x04 4.--31. 1. "RESERVED," newline bitfld.long 0x04 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline rbitfld.long 0x04 0.--1. "RESERVED," "0,1,2,3" line.long 0x08 "OCMC_SYSCONFIG_RST," hexmask.long 0x08 1.--31. 1. "RESERVED," newline bitfld.long 0x08 0. "SW_RST,Software reset of the OCM controller configuration and history logic (does not reset L4 interface)" "SW_RST_0,SW_RST_1" line.long 0x0C "OCMC_MEM_SIZE_READ,This register provides the status of the OCM Controller configuration" hexmask.long.word 0x0C 17.--31. 1. "RESERVED," newline bitfld.long 0x0C 12.--16. "VBUF_ADDR_MSB,This bit field returns the MSB bit of the valid VBUF address range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 9. "MEM_CBUF_ENABLE,Indicates whether CBUF is supported or not" "MEM_CBUF_ENABLE_0,MEM_CBUF_ENABLE_1" newline bitfld.long 0x0C 8. "MEM_ECC_ENABLE,Indicates whether ECC is supported or not" "MEM_ECC_ENABLE_0,MEM_ECC_ENABLE_1" newline bitfld.long 0x0C 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 0.--4. "MEM_SIZE_128K_CNT,This bit field indicates how many 128KiB memory blocks are present in the SRAM" "?,One 128KiB memory block,Two 128KiB memory blocks,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,20 memory blocks of 128KiB,?..." group.long 0x40++0x13 line.long 0x00 "INTR0_STATUS_RAW_SET,This register contains the raw interrupt status" hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED," newline bitfld.long 0x00 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x00 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x00 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x00 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x00 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x00 0. "SEC_ERR_FOUND," "0,1" line.long 0x04 "INTR0_STATUS_ENABLED_CLEAR,Read indicates ENABLED interrupt status (0=inactive. 1=active)" hexmask.long.tbyte 0x04 15.--31. 1. "RESERVED," newline bitfld.long 0x04 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x04 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x04 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x04 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x04 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x04 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x04 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x04 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x04 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x04 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x04 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x04 0. "SEC_ERR_FOUND," "0,1" line.long 0x08 "INTR0_ENABLE_SET,Read indicates interrupt enable (0=disabled. 1=enabled) Writing 1 will set the corresponding interrupt enable bit" hexmask.long.tbyte 0x08 15.--31. 1. "RESERVED," newline bitfld.long 0x08 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x08 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x08 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x08 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x08 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x08 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x08 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x08 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x08 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x08 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x08 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x08 0. "SEC_ERR_FOUND," "0,1" line.long 0x0C "INTR0_ENABLE_CLEAR,Read indicates interrupt enable (0=disabled. 1=enabled) Writing 1 will clear interrupt enabled" hexmask.long.tbyte 0x0C 15.--31. 1. "RESERVED," newline bitfld.long 0x0C 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x0C 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x0C 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x0C 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x0C 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x0C 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x0C 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x0C 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x0C 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x0C 0. "SEC_ERR_FOUND," "0,1" line.long 0x10 "OCMC_INTR0_EOI,This register contains the EOI vector" hexmask.long 0x10 1.--31. 1. "RESERVED," newline bitfld.long 0x10 0. "EOI_VECTOR," "0,1" group.long 0x60++0x13 line.long 0x00 "INTR1_STATUS_RAW_SET,This register contains the raw interrupt status" hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED," newline bitfld.long 0x00 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x00 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x00 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x00 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x00 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x00 0. "SEC_ERR_FOUND," "0,1" line.long 0x04 "INTR1_STATUS_ENABLED_CLEAR,Read indicates ENABLED interrupt status (0=inactive. 1=active)" hexmask.long.tbyte 0x04 15.--31. 1. "RESERVED," newline bitfld.long 0x04 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x04 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x04 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x04 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x04 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x04 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x04 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x04 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x04 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x04 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x04 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x04 0. "SEC_ERR_FOUND," "0,1" line.long 0x08 "INTR1_ENABLE_SET,Read indicates interrupt enable (0=disabled. 1=enabled) Writing 1 will set the corresponding interrupt enable bit" hexmask.long.tbyte 0x08 15.--31. 1. "RESERVED," newline bitfld.long 0x08 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x08 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x08 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x08 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x08 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x08 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x08 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x08 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x08 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x08 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x08 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x08 0. "SEC_ERR_FOUND," "0,1" line.long 0x0C "INTR1_ENABLE_CLEAR,Read indicates interrupt enable (0=disabled. 1=enabled) Writing 1 will clear interrupt enabled" hexmask.long.tbyte 0x0C 15.--31. 1. "RESERVED," newline bitfld.long 0x0C 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x0C 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x0C 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x0C 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x0C 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x0C 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x0C 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x0C 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x0C 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x0C 0. "SEC_ERR_FOUND," "0,1" line.long 0x10 "OCMC_INTR1_EOI,This register contains the EOI vector" hexmask.long 0x10 1.--31. 1. "RESERVED," newline bitfld.long 0x10 0. "EOI_VECTOR," "0,1" group.long 0x80++0x33 line.long 0x00 "CFG_OCMC_ECC," hexmask.long 0x00 6.--31. 1. "RESERVED," newline bitfld.long 0x00 5. "CFG_ECC_OPT_NON_ECC_READ,Optimize read latency for non-ECC" "Disable,Enable" newline bitfld.long 0x00 4. "CFG_ECC_ERR_SRESP_EN,ECC non-correctable error SRESP enable" "Disable,Enable" newline bitfld.long 0x00 3. "CFG_ECC_SEC_AUTO_CORRECT,SEC error auto correction mode" "Disable,Enable (If the OCM.." newline bitfld.long 0x00 0.--2. "CFG_OCMC_MODE,OCM Controller memory access modes" "Non-ECC mode (data access),Non-ECC mode (code access),Full ECC enabled mode,Block ECC enabled mode 0x4-0x7,?..." line.long 0x04 "CFG_OCMC_ECC_MEM_BLK," hexmask.long.word 0x04 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x04 0.--19. 1. "CFG_ECC_ENABLED_128K_BLK,ECC memory block enable bits" line.long 0x08 "CFG_OCMC_ECC_ERROR," hexmask.long.byte 0x08 25.--31. 1. "RESERVED," newline bitfld.long 0x08 24. "CFG_DISCARD_DUP_ADDR,Do not save duplicate error address" "Save the duplicated addresses,Save only the unique addresses" newline bitfld.long 0x08 20.--23. "CFG_ADDR_ERR_CNT_MAX,Number of ADDR errors to trigger an interrupt (The value configured must be > 0 to generate an interrupt)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 16.--19. "CFG_DED_CNT_MAX,Number of DED errors to trigger an interrupt (The value configured must be > 0 to generate an interrupt)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 0.--15. 1. "CFG_SEC_CNT_MAX,Number of SEC error to trigger an interrupt (The value configured must be > 0 to generate an interrupt)" line.long 0x0C "CFG_OCMC_ECC_CLEAR_HIST," hexmask.long 0x0C 4.--31. 1. "RESERVED," newline bitfld.long 0x0C 3. "CLEAR_SEC_BIT_DISTR,Clear stored single error correction (SEC) bit distribution history" "Reserved (not used),Cleares the following registers" newline bitfld.long 0x0C 2. "CLEAR_ADDR_ERR_CNT,Clear stored address error history" "Reserved (not used),Clears" newline bitfld.long 0x0C 1. "CLEAR_DED_ERR_CNT,Clear stored double error detection (DED) history" "Reserved (not used),Clears" newline bitfld.long 0x0C 0. "CLEAR_SEC_ERR_CNT,Clear stored single error correction history" "Reserved (not used),Clears" line.long 0x10 "STATUS_ERROR_CNT,OCM Controller error status" hexmask.long.byte 0x10 24.--31. 1. "RESERVED," newline bitfld.long 0x10 20.--23. "ADDR_ERROR_CNT,Counter for the address errors found" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 16.--19. "DED_ERROR_CNT,Counter for the double error detections" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x10 0.--15. 1. "SEC_ERROR_CNT,Counter for the single errors occured" line.long 0x14 "STATUS_SEC_ERROR_TRACE,SEC error 128-bit memory address" hexmask.long.word 0x14 19.--31. 1. "RESERVED," newline bitfld.long 0x14 18. "VALID,SEC FIFO valid addres indication" "VALID_0,VALID_1" newline hexmask.long.tbyte 0x14 0.--17. 1. "ADDRESS_128BIT,SEC error 128-bit memory address (Read from the SEC error address trace fifo)" line.long 0x18 "STATUS_DED_ERROR_TRACE,DED error 128-bit memory address" hexmask.long.word 0x18 19.--31. 1. "RESERVED," newline bitfld.long 0x18 18. "VALID,DED FIFO valid addres indication" "The DED FIFO is empty,There is a valid address in the DED FIFO" newline hexmask.long.tbyte 0x18 0.--17. 1. "ADDRESS_128BIT,DED error 128-bit memory address (Read from the DED error address trace fifo)" line.long 0x1C "STATUS_ADDR_TRANSLATION_ERROR_TRACE,ADDR error 128-bit memory address" hexmask.long.word 0x1C 19.--31. 1. "RESERVED," newline bitfld.long 0x1C 18. "VALID,ADDRERR FIFO valid addres indication" "The ADDRERR FIFO is empty,There is a valid address in the ADDRERR FIFO" newline hexmask.long.tbyte 0x1C 0.--17. 1. "ADDRESS_128BIT,ADDR error 128-bit memory address (Read from the ADDR error address trace fifo)" line.long 0x20 "STATUS_SEC_ERROR_DISTR_0,SEC data error bit distribution status [31:0]" line.long 0x24 "STATUS_SEC_ERROR_DISTR_1,SEC data error bit distribution status [63:32]" line.long 0x28 "STATUS_SEC_ERROR_DISTR_2,SEC data error bit distribution status [95:64]" line.long 0x2C "STATUS_SEC_ERROR_DISTR_3,SEC data error bit distribution status [127:96]" line.long 0x30 "STATUS_SEC_ERROR_DISTR_4,SEC ecc code error bit distribution status [7:0]" hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED," newline abitfld.long 0x30 0.--7. "SEC_ECC_CODE_ERROR_FOUND,ECC Code (excluding the parity bit) error distribution [7:0]" "0x00=SEC error not found,0x01=SEC error found In the corresponding bit.." group.long 0x200++0x33 line.long 0x00 "CFG_OCMC_CBUF_EN,CBUF mode enable register" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 27. "CBUF_EN_11,CBUF 11 enable" "Disable,Enable" newline bitfld.long 0x00 26. "CBUF_EN_10,CBUF 10 enable" "Disable,Enable" newline bitfld.long 0x00 25. "CBUF_EN_9,CBUF 9 enable" "Disable,Enable" newline bitfld.long 0x00 24. "CBUF_EN_8,CBUF 8 enable" "Disable,Enable" newline bitfld.long 0x00 23. "CBUF_EN_7,CBUF 7 enable" "Disable,Enable" newline bitfld.long 0x00 22. "CBUF_EN_6,CBUF 6 enable" "Disable,Enable" newline bitfld.long 0x00 21. "CBUF_EN_5,CBUF 5 enable" "Disable,Enable" newline bitfld.long 0x00 20. "CBUF_EN_4,CBUF 4 enable" "Disable,Enable" newline bitfld.long 0x00 19. "CBUF_EN_3,CBUF 3 enable" "Disable,Enable" newline bitfld.long 0x00 18. "CBUF_EN_2,CBUF 2 enable" "Disable,Enable" newline bitfld.long 0x00 17. "CBUF_EN_1,CBUF 1 enable" "Disable,Enable" newline bitfld.long 0x00 16. "CBUF_EN_0,CBUF 0 enable" "Disable,Enable" newline hexmask.long.word 0x00 3.--15. 1. "RESERVED," newline bitfld.long 0x00 2. "NEW_FRAME_SEL,CBUF New Frame Event Definition Select" "New frame event flag is set when a VBUF access..,New frame event flag is set when a VBUF access.." newline bitfld.long 0x00 1. "CBUF_DEBUG_EN,CBUF Debug Enable Mode" "Default Normal mode,Debug mode" newline bitfld.long 0x00 0. "CBUF_MODE_EN,CBUF Mode Enable" "Disable all CBUF address translation,Enable CBUF address translation" line.long 0x04 "CFG_OCMC_CBUF_RESET,Writing 1 to bit n will set a reset bit to clear the corresponding CBUF_n address translation logic" hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED," newline bitfld.long 0x04 11. "CBUF_RESET_11,cbuf_reset_11" "0,1" newline bitfld.long 0x04 10. "CBUF_RESET_10,cbuf_reset_10" "0,1" newline bitfld.long 0x04 9. "CBUF_RESET_9,cbuf_reset_9" "0,1" newline bitfld.long 0x04 8. "CBUF_RESET_8,cbuf_reset_8" "0,1" newline bitfld.long 0x04 7. "CBUF_RESET_7,cbuf_reset_7" "0,1" newline bitfld.long 0x04 6. "CBUF_RESET_6,cbuf_reset_6" "0,1" newline bitfld.long 0x04 5. "CBUF_RESET_5,cbuf_reset_5" "0,1" newline bitfld.long 0x04 4. "CBUF_RESET_4,cbuf_reset_4" "0,1" newline bitfld.long 0x04 3. "CBUF_RESET_3,cbuf_reset_3" "0,1" newline bitfld.long 0x04 2. "CBUF_RESET_2,cbuf_reset_2" "0,1" newline bitfld.long 0x04 1. "CBUF_RESET_1,cbuf_reset_1" "0,1" newline bitfld.long 0x04 0. "CBUF_RESET_0,cbuf_reset_0" "0,1" line.long 0x08 "CFG_OCMC_CBUF_ERR_HANDLER," hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," newline bitfld.long 0x08 8. "UNDERFLOW_LAST_CBUF_SLICE_DISABLE," "0,1" newline bitfld.long 0x08 6.--7. "OVERFLOW_CHECK_REENABLE_SEL,Overflow check re-enable selection" "Overflow check is disabled until next wtire to..,Overflow check is disabled until next write to..,Overflow check is disabled until next read from..,Overflow check is re-enabled immediately" newline bitfld.long 0x08 4.--5. "OVERFLOW_WRITE_HANDLER_SEL,Overflow write handler selection" "Writes disabled only on CBUF_overflow_wrap cases..,Writes disabled on all overflow cases until next..,Writes serviced with CBUF pointer updated even..,Reserved" newline bitfld.long 0x08 3. "UNDERFLOW_ERR_CHECK_EN,Underflow chek enable" "UNDERFLOW_ERR_CHECK_EN_0,UNDERFLOW_ERR_CHECK_EN_1" newline bitfld.long 0x08 2. "OVERFLOW_ERR_CHECK_EN,Overflow chek enable" "OVERFLOW_ERR_CHECK_EN_0,OVERFLOW_ERR_CHECK_EN_1" newline bitfld.long 0x08 1. "SHORT_FRAME_PREV_EOF_SEL," "0,1" newline bitfld.long 0x08 0. "SHORT_FRAME_DETECT_CHECK_EN,Short frame detection enable" "SHORT_FRAME_DETECT_CHECK_EN_0,SHORT_FRAME_DETECT_CHECK_EN_1" line.long 0x0C "STATUS_CBUF_WR_OUT_OF_RANGE_ERR," hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--11. 1. "CBUF_ERR,Indicates that the CBUF write address is out of the CBUF range" line.long 0x10 "STATUS_CBUF_WR_VBUF_START_ERR," hexmask.long.tbyte 0x10 12.--31. 1. "RESERVED," newline hexmask.long.word 0x10 0.--11. 1. "CBUF_ERR,CBUF write is not to the base address at vbuf access start" line.long 0x14 "STATUS_CBUF_WR_ADDR_SEQ_ERROR," hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED," newline hexmask.long.word 0x14 0.--11. 1. "CBUF_ERR,CBUF address is not incrementing in raster scan order" line.long 0x18 "STATUS_CBUF_RD_OUT_OF_RANGE_ERROR," hexmask.long.tbyte 0x18 12.--31. 1. "RESERVED," newline hexmask.long.word 0x18 0.--11. 1. "CBUF_ERR,Indicates that the CBUF read address is out of the CBUF range" line.long 0x1C "STATUS_CBUF_VBUF_RD_START_ERROR," hexmask.long.tbyte 0x1C 12.--31. 1. "RESERVED," newline hexmask.long.word 0x1C 0.--11. 1. "CBUF_ERR,CBUF read is not from the base address at VBUF access start" line.long 0x20 "STATUS_CBUF_RD_ADDR_SEQ_ERROR," hexmask.long.tbyte 0x20 12.--31. 1. "RESERVED," newline hexmask.long.word 0x20 0.--11. 1. "CBUF_ERR,CBUF read address is not incrementing in raster scan order" line.long 0x24 "STATUS_CBUF_OVERFLOW_MID," hexmask.long.tbyte 0x24 12.--31. 1. "RESERVED," newline hexmask.long.word 0x24 0.--11. 1. "CBUF_ERR,CBUF overflow condition detected in the middle of a frame" line.long 0x28 "STATUS_CBUF_OVERFLOW_WRAP," hexmask.long.tbyte 0x28 12.--31. 1. "RESERVED," newline hexmask.long.word 0x28 0.--11. 1. "CBUF_ERR,CBUF overflow condition detected during buffer switching" line.long 0x2C "STATUS_CBUF_UNDERFLOW," hexmask.long.tbyte 0x2C 12.--31. 1. "RESERVED," newline hexmask.long.word 0x2C 0.--11. 1. "CBUF_ERR,CBUF underflow condition detected" line.long 0x30 "STATUS_CBUF_SHORT_FRAME_DETECT," hexmask.long.tbyte 0x30 12.--31. 1. "RESERVED," newline hexmask.long.word 0x30 0.--11. 1. "CBUF_ERR,CBUF short frame detected" group.long 0x240++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_0," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x256++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_1," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x26C++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_2," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x282++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_3," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x298++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_4," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2AE++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_5," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2C4++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_6," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2DA++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_7," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2F0++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_8," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x306++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_9," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x31C++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_10," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x332++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_11," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x244++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_0," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x25A++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_1," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x270++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_2," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x286++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_3," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x29C++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_4," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2B2++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_5," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2C8++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_6," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2DE++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_7," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2F4++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_8," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30A++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_9," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x320++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_10," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x336++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_11," hexmask.long.byte 0x00 24.--31. 1. "RESERVED,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field" newline hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x248++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_0," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x25E++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_1," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x274++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_2," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x28A++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_3," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2A0++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_4," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2B6++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_5," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2CC++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_6," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2E2++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_7," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2F8++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_8," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30E++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_9," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x324++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_10," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x33A++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_11," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x24C++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_0," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x262++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_1," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x278++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_2," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x28E++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_3," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2A4++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_4," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2BA++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_5," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2D0++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_6," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2E6++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_7," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2FC++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_8," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x312++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_9," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x328++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_10," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x33E++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_11," hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" newline rbitfld.long 0x00 0.--3. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x300++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_0," rgroup.long 0x308++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_1," rgroup.long 0x310++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_2," rgroup.long 0x318++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_3," rgroup.long 0x320++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_4," rgroup.long 0x328++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_5," rgroup.long 0x330++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_6," rgroup.long 0x338++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_7," rgroup.long 0x340++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_8," rgroup.long 0x348++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_9," rgroup.long 0x350++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_10," rgroup.long 0x358++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_11," rgroup.long 0x304++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_0," rgroup.long 0x30C++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_1," rgroup.long 0x314++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_2," rgroup.long 0x31C++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_3," rgroup.long 0x324++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_4," rgroup.long 0x32C++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_5," rgroup.long 0x334++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_6," rgroup.long 0x33C++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_7," rgroup.long 0x344++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_8," rgroup.long 0x34C++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_9," rgroup.long 0x354++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_10," rgroup.long 0x35C++0x07 line.long 0x00 "CBUF_k_LAST_RD_ADDR_11," line.long 0x04 "LAST_ILLEGAL_OCMC_ADDR," width 0x0B tree.end tree "OCMC_RAM_CFG_TARG" base ad:0x48805000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "OCMC_RAM_FW" base ad:0x4A212000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" newline rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x100++0x03 line.long 0x00 "START_REGION_i_8,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x110++0x03 line.long 0x00 "START_REGION_i_9,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x120++0x03 line.long 0x00 "START_REGION_i_10,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x130++0x03 line.long 0x00 "START_REGION_i_11,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x140++0x03 line.long 0x00 "START_REGION_i_12,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x150++0x03 line.long 0x00 "START_REGION_i_13,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x160++0x03 line.long 0x00 "START_REGION_i_14,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x170++0x03 line.long 0x00 "START_REGION_i_15,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x180++0x03 line.long 0x00 "START_REGION_i_16,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x190++0x03 line.long 0x00 "START_REGION_i_17,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1A0++0x03 line.long 0x00 "START_REGION_i_18,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1B0++0x03 line.long 0x00 "START_REGION_i_19,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1C0++0x03 line.long 0x00 "START_REGION_i_20,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1D0++0x03 line.long 0x00 "START_REGION_i_21,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1E0++0x03 line.long 0x00 "START_REGION_i_22,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x1F0++0x03 line.long 0x00 "START_REGION_i_23,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x104++0x03 line.long 0x00 "END_REGION_i_8,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x114++0x03 line.long 0x00 "END_REGION_i_9,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x124++0x03 line.long 0x00 "END_REGION_i_10,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x134++0x03 line.long 0x00 "END_REGION_i_11,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x144++0x03 line.long 0x00 "END_REGION_i_12,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x154++0x03 line.long 0x00 "END_REGION_i_13,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x164++0x03 line.long 0x00 "END_REGION_i_14,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x174++0x03 line.long 0x00 "END_REGION_i_15,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x184++0x03 line.long 0x00 "END_REGION_i_16,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x194++0x03 line.long 0x00 "END_REGION_i_17,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1A4++0x03 line.long 0x00 "END_REGION_i_18,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1B4++0x03 line.long 0x00 "END_REGION_i_19,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1C4++0x03 line.long 0x00 "END_REGION_i_20,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1D4++0x03 line.long 0x00 "END_REGION_i_21,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1E4++0x03 line.long 0x00 "END_REGION_i_22,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x1F4++0x03 line.long 0x00 "END_REGION_i_23,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x108++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_8,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x118++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_9,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x128++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_10,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x138++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_11,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x148++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_12,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x158++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_13,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x168++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_14,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x178++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_15,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x188++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_16,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x198++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_17,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1A8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_18,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1B8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_19,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_20,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1D8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_21,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_22,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1F8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_23,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x10C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_8,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x11C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_9,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x12C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_10,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x13C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_11,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x14C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_12,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x15C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_13,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x16C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_14,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x17C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_15,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x18C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_16,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x19C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_17,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1AC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_18,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1BC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_19,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1CC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_20,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1DC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_21,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1EC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_22,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x1FC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_23,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "OCMC_RAM_FW_CFG_TARG" base ad:0x4A213000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "OCMC_RAM_TARG" base ad:0x44000F00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "OCP_SOCKET_CM_CORE" base ad:0x4A008000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION_CM_CORE,This register contains the IP revision code for the CM_CORE part of the PRCM" bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3" bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. "R_RTL,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "CUSTOM_0,?,?,?" newline bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision (Y)" "Y_MINOR_0,Y_MINOR_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x40++0x03 line.long 0x00 "CM_CM_CORE_PROFILING_CLKCTRL,This register manages the CM_CORE_PROFILING clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xF0++0x03 line.long 0x00 "CM_CORE_DEBUG_CFG,This register is used to configure the CM_CORE's 32-bit debug output" hexmask.long.byte 0x00 24.--31. 1. "SEL3,Internal signal block select for debug word byte-3" hexmask.long.byte 0x00 16.--23. 1. "SEL2,Internal signal block select for debug word byte-2" hexmask.long.byte 0x00 8.--15. 1. "SEL1,Internal signal block select for debug word byte-1" hexmask.long.byte 0x00 0.--7. 1. "SEL0,Internal signal block select for debug word byte-0" width 0x0B tree.end tree "OCP_SOCKET_CM_CORE_AON" base ad:0x4A005000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION_CM_CORE_AON,This register contains the IP revision code for the CM_CORE_AON part of the PRCM" bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3" bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. "R_RTL,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "CUSTOM_0,?,?,?" newline bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision (Y)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x40++0x03 line.long 0x00 "CM_CM_CORE_AON_PROFILING_CLKCTRL,This register manages the CM_CORE_AON_PROFILING clock" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0xEC++0x03 line.long 0x00 "CM_CORE_AON_DEBUG_OUT,This register is used to monitor the CM_COREAON's 32 bit HEDEBUG BUS [warm reset insensitive]" repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0xF0)++0x03 line.long 0x00 "CM_CORE_AON_DEBUG_CFG$1,This register is used to configure the CM_CORE_AON's 32-bit debug output" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," hexmask.long.word 0x00 0.--9. 1. "SEL0,Internal signal block select for debug word byte-0" repeat.end width 0x0B tree.end tree "OCP_SOCKET_PRM" base ad:0x4AE06000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION_PRM,This register contains the IP revision code for the PRM part of the PRCM" bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3" bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family" newline bitfld.long 0x00 11.--15. "R_RTL,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "CUSTOM_0,?,?,?" newline bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision (Y)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x13 line.long 0x00 "PRM_IRQSTATUS_MPU,This register provides status on MPU interrupt events" rbitfld.long 0x00 31. "RESERVED," "0,1" bitfld.long 0x00 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x00 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x00 13.--27. 1. "RESERVED," bitfld.long 0x00 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x00 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" rbitfld.long 0x00 10. "RESERVED," "0,1" bitfld.long 0x00 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline bitfld.long 0x00 8. "TRANSITION_ST,Software supervised transition completed event interrupt status (any domain)" "TRANSITION_ST_0,TRANSITION_ST_1" bitfld.long 0x00 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x00 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x00 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x00 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x00 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x00 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x00 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x00 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x04 "PRM_IRQSTATUS_MPU_2,This register provides status on MPU interrupt events" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," bitfld.long 0x04 7. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" hexmask.long.byte 0x04 0.--6. 1. "RESERVED," line.long 0x08 "PRM_IRQENABLE_MPU,This register is used to enable or disable MPU interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x08 31. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x08 30. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" bitfld.long 0x08 29. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" newline hexmask.long.tbyte 0x08 12.--28. 1. "RESERVED," bitfld.long 0x08 11. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x08 10. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" newline bitfld.long 0x08 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" bitfld.long 0x08 8. "TRANSITION_EN,Software supervised transition completed event interrupt enable (any domain)" "TRANSITION_EN_0,TRANSITION_EN_1" bitfld.long 0x08 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" newline bitfld.long 0x08 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x08 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x08 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" newline bitfld.long 0x08 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x08 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x08 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" newline bitfld.long 0x08 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x0C "PRM_IRQENABLE_MPU_2,This register is used to enable or disable MPU interrupt activation upon presence of corresponding IRQSTATUS bit" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED," bitfld.long 0x0C 7. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" hexmask.long.byte 0x0C 0.--6. 1. "RESERVED," line.long 0x10 "PRM_IRQSTATUS_IPU2,This register provides status on IPU2 interrupt events" bitfld.long 0x10 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x10 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x10 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x10 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x10 13.--27. 1. "RESERVED," bitfld.long 0x10 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x10 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x10 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x10 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline bitfld.long 0x10 8. "TRANSITION_ST,Software supervised transition completed event interrupt status (any domain)" "TRANSITION_ST_0,TRANSITION_ST_1" bitfld.long 0x10 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x10 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x10 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x10 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x10 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x10 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x10 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x10 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" group.long 0x28++0x03 line.long 0x00 "PRM_IRQENABLE_IPU2,This register is used to enable or disable IPU2 interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x00 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x00 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x00 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" hexmask.long.word 0x00 13.--27. 1. "RESERVED," bitfld.long 0x00 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" newline bitfld.long 0x00 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x00 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x00 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" newline bitfld.long 0x00 8. "TRANSITION_EN,Software supervised transition completed event interrupt enable (any domain)" "TRANSITION_EN_0,TRANSITION_EN_1" bitfld.long 0x00 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x00 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" newline bitfld.long 0x00 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x00 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x00 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" newline bitfld.long 0x00 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x00 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x00 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" group.long 0x30++0x03 line.long 0x00 "PRM_IRQSTATUS_DSP1,This register provides status on DSP1 interrupt events" bitfld.long 0x00 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x00 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x00 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x00 13.--27. 1. "RESERVED," bitfld.long 0x00 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x00 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x00 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x00 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline rbitfld.long 0x00 8. "RESERVED," "0,1" bitfld.long 0x00 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x00 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x00 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x00 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x00 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x00 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x00 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x00 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" group.long 0x38++0x03 line.long 0x00 "PRM_IRQENABLE_DSP1,This register is used to enable or disable DSP1 interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x00 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x00 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x00 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" hexmask.long.word 0x00 14.--27. 1. "RESERVED," bitfld.long 0x00 13. "DPLL_USB_RECAL_EN,USB DPLL recalibration interrupt enable" "DPLL_USB_RECAL_EN_0,DPLL_USB_RECAL_EN_1" newline bitfld.long 0x00 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x00 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x00 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" newline bitfld.long 0x00 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" rbitfld.long 0x00 8. "RESERVED," "0,1" bitfld.long 0x00 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" newline bitfld.long 0x00 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x00 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x00 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" newline bitfld.long 0x00 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x00 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x00 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" newline bitfld.long 0x00 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" group.long 0x40++0x33 line.long 0x00 "CM_PRM_PROFILING_CLKCTRL,This register manages the PRM_PROFILING clock" hexmask.long.word 0x00 18.--31. 1. "RESERVED," rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x04 "PRM_IRQENABLE_DSP2,This register is used to enable or disable DSP2 interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x04 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x04 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x04 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x04 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" hexmask.long.word 0x04 13.--27. 1. "RESERVED," bitfld.long 0x04 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" newline bitfld.long 0x04 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x04 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x04 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" newline rbitfld.long 0x04 8. "RESERVED," "0,1" bitfld.long 0x04 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x04 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" newline bitfld.long 0x04 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x04 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x04 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" newline bitfld.long 0x04 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x04 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x04 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x08 "PRM_IRQENABLE_EVE1,This register is used to enable or disable EVE1 interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x08 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x08 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x08 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x08 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" hexmask.long.word 0x08 13.--27. 1. "RESERVED," bitfld.long 0x08 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" newline bitfld.long 0x08 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x08 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x08 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" newline rbitfld.long 0x08 8. "RESERVED," "0,1" bitfld.long 0x08 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x08 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" newline bitfld.long 0x08 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x08 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x08 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" newline bitfld.long 0x08 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x08 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x08 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x0C "PRM_IRQENABLE_EVE2,This register is used to enable or disable EVE2 interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x0C 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x0C 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x0C 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x0C 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" hexmask.long.word 0x0C 13.--27. 1. "RESERVED," bitfld.long 0x0C 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" newline bitfld.long 0x0C 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x0C 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x0C 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" newline rbitfld.long 0x0C 8. "RESERVED," "0,1" bitfld.long 0x0C 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x0C 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" newline bitfld.long 0x0C 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x0C 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x0C 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" newline bitfld.long 0x0C 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x0C 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x0C 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x10 "PRM_IRQENABLE_EVE3,This register is used to enable or disable EVE3 interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x10 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x10 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x10 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x10 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" hexmask.long.word 0x10 13.--27. 1. "RESERVED," bitfld.long 0x10 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" newline bitfld.long 0x10 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x10 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x10 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" newline rbitfld.long 0x10 8. "RESERVED," "0,1" bitfld.long 0x10 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x10 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" newline bitfld.long 0x10 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x10 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x10 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" newline bitfld.long 0x10 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x10 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x10 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x14 "PRM_IRQENABLE_EVE4,This register is used to enable or disable EVE4 interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x14 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x14 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x14 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x14 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" hexmask.long.word 0x14 13.--27. 1. "RESERVED," bitfld.long 0x14 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" newline bitfld.long 0x14 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x14 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x14 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" newline rbitfld.long 0x14 8. "RESERVED," "0,1" bitfld.long 0x14 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x14 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" newline bitfld.long 0x14 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x14 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x14 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" newline bitfld.long 0x14 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x14 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x14 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x18 "PRM_IRQENABLE_IPU1,This register is used to enable or disable IPU1 interrupt activation upon presence of corresponding IRQSTATUS bit" bitfld.long 0x18 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x18 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x18 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x18 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" hexmask.long.word 0x18 13.--27. 1. "RESERVED," bitfld.long 0x18 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" newline bitfld.long 0x18 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x18 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x18 9. "IO_EN,IO pad event interrupt enable" "IO_EN_0,IO_EN_1" newline bitfld.long 0x18 8. "TRANSITION_EN,Software supervised transition completed event interrupt enable (any domain)" "TRANSITION_EN_0,TRANSITION_EN_1" bitfld.long 0x18 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x18 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" newline bitfld.long 0x18 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x18 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x18 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" newline bitfld.long 0x18 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x18 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x18 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x1C "PRM_IRQSTATUS_DSP2,This register provides status on DSP interrupt events" bitfld.long 0x1C 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x1C 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x1C 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x1C 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x1C 13.--27. 1. "RESERVED," bitfld.long 0x1C 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x1C 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x1C 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x1C 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline rbitfld.long 0x1C 8. "RESERVED," "0,1" bitfld.long 0x1C 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x1C 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x1C 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x1C 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x1C 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x1C 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x1C 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x1C 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x20 "PRM_IRQSTATUS_EVE1,This register provides status on EVE interrupt events" bitfld.long 0x20 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x20 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x20 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x20 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x20 13.--27. 1. "RESERVED," bitfld.long 0x20 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x20 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x20 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x20 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline rbitfld.long 0x20 8. "RESERVED," "0,1" bitfld.long 0x20 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x20 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x20 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x20 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x20 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x20 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x20 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x20 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x24 "PRM_IRQSTATUS_EVE2,This register provides status on EVE interrupt events" bitfld.long 0x24 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x24 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x24 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x24 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x24 13.--27. 1. "RESERVED," bitfld.long 0x24 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x24 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x24 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x24 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline rbitfld.long 0x24 8. "RESERVED," "0,1" bitfld.long 0x24 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x24 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x24 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x24 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x24 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x24 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x24 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x24 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x28 "PRM_IRQSTATUS_EVE3,This register provides status on EVE interrupt events" bitfld.long 0x28 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x28 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x28 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x28 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x28 13.--27. 1. "RESERVED," bitfld.long 0x28 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x28 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x28 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x28 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline rbitfld.long 0x28 8. "RESERVED," "0,1" bitfld.long 0x28 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x28 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x28 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x28 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x28 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x28 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x28 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x28 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x2C "PRM_IRQSTATUS_EVE4,This register provides status on EVE interrupt events" bitfld.long 0x2C 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x2C 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x2C 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x2C 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x2C 13.--27. 1. "RESERVED," bitfld.long 0x2C 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x2C 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x2C 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x2C 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline rbitfld.long 0x2C 8. "RESERVED," "0,1" bitfld.long 0x2C 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x2C 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x2C 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x2C 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x2C 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x2C 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x2C 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x2C 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x30 "PRM_IRQSTATUS_IPU1,This register provides status on IPU1 interrupt events" bitfld.long 0x30 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x30 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x30 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x30 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" hexmask.long.word 0x30 13.--27. 1. "RESERVED," bitfld.long 0x30 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" newline bitfld.long 0x30 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x30 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x30 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline bitfld.long 0x30 8. "TRANSITION_ST,Software supervised transition completed event interrupt status (any domain)" "TRANSITION_ST_0,TRANSITION_ST_1" bitfld.long 0x30 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x30 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x30 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x30 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x30 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x30 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x30 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x30 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" rgroup.long 0xF4++0x03 line.long 0x00 "PRM_DEBUG_OUT,This register is used to monitor the PRM's 32 bit HEDEBUG BUS [warm reset insensitive]" repeat 4. (list 1. 2. 3. 4. )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0xE4)++0x03 line.long 0x00 "PRM_DEBUG_CFG$1,This register is used to configure the PRM's 32-bit debug output" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," hexmask.long.word 0x00 0.--8. 1. "SEL1,Internal signal block select for debug word byte-1" repeat.end width 0x0B tree.end tree "OCP_WP_NOC_TARG" base ad:0x4A103000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_H,Error reporting" line.long 0x14 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x14 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x14 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x14 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x14 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x14 0. "OCP_RESET,L3 Reset" "0,1" width 0x0B tree.end tree "PORT" base ad:0x48484100 group.long 0x00++0x03 line.long 0x00 "P0_CONTROL,CPSW PORT 0 control register" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 28.--30. "P0_DLR_CPDMA_CH,Port 0 DLR CPDMA Channel This field indicates the CPDMA channel that DLR packets will be received on" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 25.--27. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "Priority tagged packets have the zero VID..,Priority tagged packets are processed unchanged" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 21. "P0_VLAN_LTYPE2_EN,Port 0 VLAN LTYPE 2 enable" "disabled,enabled" newline bitfld.long 0x00 20. "P0_VLAN_LTYPE1_EN,Port 0 VLAN LTYPE 1 enable" "disabled,enabled" newline rbitfld.long 0x00 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. "P0_DSCP_PRI_EN,Port 0 DSCP Priority Enable" "DSCP priority disabled,DSCP priority enabled" newline hexmask.long.word 0x00 0.--15. 1. "RESERVED," group.long 0x08++0x1B line.long 0x00 "P0_MAX_BLKS,CPSW PORT 0 maximum FIFO blocks register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 4.--8. "P0_TX_MAX_BLKS,Transmit FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical transmit priority queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--3. "P0_RX_MAX_BLKS,Receive FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical receive queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "P0_BLK_CNT,CPSW PORT 0 FIFO block usage count (read only)" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," newline bitfld.long 0x04 4.--8. "P0_TX_BLK_CNT,Port 0 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--3. "P0_RX_BLK_CNT,Port 0 Receive Block Count Usage - This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "P0_TX_IN_CTL,CPSW PORT 0 transmit FIFO control" hexmask.long.byte 0x08 24.--31. 1. "RESERVED," newline bitfld.long 0x08 20.--23. "TX_RATE_EN,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x08 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 16.--17. "TX_IN_SEL,Transmit FIFO Input Queue Type Select" "Normal priority mode,Dual MAC mode,Rate Limit mode,reserved Note that Dual MAC mode is not.." newline bitfld.long 0x08 12.--15. "TX_BLKS_REM,Transmit FIFO Input Blocks to subtract in dual MAC mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x08 10.--11. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x08 0.--9. 1. "TX_PRI_WDS,Transmit FIFO Words in queue" line.long 0x0C "P0_PORT_VLAN,CPSW PORT 0 VLAN register" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," newline bitfld.long 0x0C 13.--15. "PORT_PRI,Port VLAN Priority (7 is highest priority)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0C 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x10 "P0_TX_PRI_MAP,CPSW PORT 0 TX header priority to switch priority mapping register" rbitfld.long 0x10 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 28.--29. "PRI7,Priority" "0,1,2,3" newline rbitfld.long 0x10 26.--27. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 24.--25. "PRI6,Priority" "0,1,2,3" newline rbitfld.long 0x10 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 20.--21. "PRI5,Priority" "0,1,2,3" newline rbitfld.long 0x10 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 16.--17. "PRI4,Priority" "0,1,2,3" newline rbitfld.long 0x10 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 12.--13. "PRI3,Priority" "0,1,2,3" newline rbitfld.long 0x10 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 8.--9. "PRI2,Priority" "0,1,2,3" newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 4.--5. "PRI1,Priority" "0,1,2,3" newline rbitfld.long 0x10 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRI0,Priority" "0,1,2,3" line.long 0x14 "P0_CPDMA_TX_PRI_MAP,CPSW CPDMA TX (PORT 0 RX) packet priority to header priority" rbitfld.long 0x14 31. "RESERVED," "0,1" newline bitfld.long 0x14 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED," "0,1" newline bitfld.long 0x14 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED," "0,1" newline bitfld.long 0x14 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED," "0,1" newline bitfld.long 0x14 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED," "0,1" newline bitfld.long 0x14 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED," "0,1" newline bitfld.long 0x14 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED," "0,1" newline bitfld.long 0x14 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x18 "P0_CPDMA_RX_CH_MAP,CPSW CPDMA RX (PORT 0 TX) switch priority to DMA channel" rbitfld.long 0x18 31. "RESERVED," "0,1" newline bitfld.long 0x18 28.--30. "P2_PRI3,Port 2 Priority 3 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED," "0,1" newline bitfld.long 0x18 24.--26. "P2_PRI2,Port 2 Priority 2 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED," "0,1" newline bitfld.long 0x18 20.--22. "P2_PRI1,Port 2 Priority 1 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED," "0,1" newline bitfld.long 0x18 16.--18. "P2_PRI0,Port 2 Priority 0 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED," "0,1" newline bitfld.long 0x18 12.--14. "P1_PRI3,Port 1 Priority 3 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED," "0,1" newline bitfld.long 0x18 8.--10. "P1_PRI2,Port 1 Priority 2 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED," "0,1" newline bitfld.long 0x18 4.--6. "P1_PRI1,Port 1 Priority 1 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED," "0,1" newline bitfld.long 0x18 0.--2. "P1_PRI0,Port 1 Priority 0 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" group.long 0x30++0x27 line.long 0x00 "P0_RX_DSCP_PRI_MAP0,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 0" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 27. "RESERVED," "0,1" newline bitfld.long 0x00 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 23. "RESERVED," "0,1" newline bitfld.long 0x00 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED," "0,1" newline bitfld.long 0x00 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. "RESERVED," "0,1" newline bitfld.long 0x00 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED," "0,1" newline bitfld.long 0x00 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x04 "P0_RX_DSCP_PRI_MAP1,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 1" rbitfld.long 0x04 31. "RESERVED," "0,1" newline bitfld.long 0x04 28.--30. "PRI15,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 27. "RESERVED," "0,1" newline bitfld.long 0x04 24.--26. "PRI14,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 23. "RESERVED," "0,1" newline bitfld.long 0x04 20.--22. "PRI13,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED," "0,1" newline bitfld.long 0x04 16.--18. "PRI12,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 15. "RESERVED," "0,1" newline bitfld.long 0x04 12.--14. "PRI11,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 11. "RESERVED," "0,1" newline bitfld.long 0x04 8.--10. "PRI10,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED," "0,1" newline bitfld.long 0x04 4.--6. "PRI9,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 0.--2. "PRI8,Priority" "0,1,2,3,4,5,6,7" line.long 0x08 "P0_RX_DSCP_PRI_MAP2,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 2" rbitfld.long 0x08 31. "RESERVED," "0,1" newline bitfld.long 0x08 28.--30. "PRI23,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 27. "RESERVED," "0,1" newline bitfld.long 0x08 24.--26. "PRI22,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 23. "RESERVED," "0,1" newline bitfld.long 0x08 20.--22. "PRI21,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED," "0,1" newline bitfld.long 0x08 16.--18. "PRI20,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 15. "RESERVED," "0,1" newline bitfld.long 0x08 12.--14. "PRI19,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 11. "RESERVED," "0,1" newline bitfld.long 0x08 8.--10. "PRI18,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED," "0,1" newline bitfld.long 0x08 4.--6. "PRI17,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 0.--2. "PRI16,Priority" "0,1,2,3,4,5,6,7" line.long 0x0C "P0_RX_DSCP_PRI_MAP3,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 3" rbitfld.long 0x0C 31. "RESERVED," "0,1" newline bitfld.long 0x0C 28.--30. "PRI31,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 27. "RESERVED," "0,1" newline bitfld.long 0x0C 24.--26. "PRI30,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 23. "RESERVED," "0,1" newline bitfld.long 0x0C 20.--22. "PRI29,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED," "0,1" newline bitfld.long 0x0C 16.--18. "PRI28,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 15. "RESERVED," "0,1" newline bitfld.long 0x0C 12.--14. "PRI27,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 11. "RESERVED," "0,1" newline bitfld.long 0x0C 8.--10. "PRI26,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED," "0,1" newline bitfld.long 0x0C 4.--6. "PRI25,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 0.--2. "PRI24,Priority" "0,1,2,3,4,5,6,7" line.long 0x10 "P0_RX_DSCP_PRI_MAP4,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 4" rbitfld.long 0x10 31. "RESERVED," "0,1" newline bitfld.long 0x10 28.--30. "PRI39,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED," "0,1" newline bitfld.long 0x10 24.--26. "PRI38,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED," "0,1" newline bitfld.long 0x10 20.--22. "PRI37,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "RESERVED," "0,1" newline bitfld.long 0x10 16.--18. "PRI36,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 15. "RESERVED," "0,1" newline bitfld.long 0x10 12.--14. "PRI35,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 11. "RESERVED," "0,1" newline bitfld.long 0x10 8.--10. "PRI34,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 7. "RESERVED," "0,1" newline bitfld.long 0x10 4.--6. "PRI33,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 3. "RESERVED," "0,1" newline bitfld.long 0x10 0.--2. "PRI32,Priority" "0,1,2,3,4,5,6,7" line.long 0x14 "P0_RX_DSCP_PRI_MAP5,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 5" rbitfld.long 0x14 31. "RESERVED," "0,1" newline bitfld.long 0x14 28.--30. "PRI47,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED," "0,1" newline bitfld.long 0x14 24.--26. "PRI46,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED," "0,1" newline bitfld.long 0x14 20.--22. "PRI45,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED," "0,1" newline bitfld.long 0x14 16.--18. "PRI44,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED," "0,1" newline bitfld.long 0x14 12.--14. "PRI43,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED," "0,1" newline bitfld.long 0x14 8.--10. "PRI42,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED," "0,1" newline bitfld.long 0x14 4.--6. "PRI41,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 0.--2. "PRI40,Priority" "0,1,2,3,4,5,6,7" line.long 0x18 "P0_RX_DSCP_PRI_MAP6,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 6" rbitfld.long 0x18 31. "RESERVED," "0,1" newline bitfld.long 0x18 28.--30. "PRI55,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED," "0,1" newline bitfld.long 0x18 24.--26. "PRI54,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED," "0,1" newline bitfld.long 0x18 20.--22. "PRI53,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED," "0,1" newline bitfld.long 0x18 16.--18. "PRI52,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED," "0,1" newline bitfld.long 0x18 12.--14. "PRI51,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED," "0,1" newline bitfld.long 0x18 8.--10. "PRI50,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED," "0,1" newline bitfld.long 0x18 4.--6. "PRI49,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED," "0,1" newline bitfld.long 0x18 0.--2. "PRI48,Priority" "0,1,2,3,4,5,6,7" line.long 0x1C "P0_RX_DSCP_PRI_MAP7,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 7" rbitfld.long 0x1C 31. "RESERVED," "0,1" newline bitfld.long 0x1C 28.--30. "PRI63,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 27. "RESERVED," "0,1" newline bitfld.long 0x1C 24.--26. "PRI62,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 23. "RESERVED," "0,1" newline bitfld.long 0x1C 20.--22. "PRI61,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 19. "RESERVED," "0,1" newline bitfld.long 0x1C 16.--18. "PRI60,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 15. "RESERVED," "0,1" newline bitfld.long 0x1C 12.--14. "PRI59,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 11. "RESERVED," "0,1" newline bitfld.long 0x1C 8.--10. "PRI58,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 7. "RESERVED," "0,1" newline bitfld.long 0x1C 4.--6. "PRI57,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 3. "RESERVED," "0,1" newline bitfld.long 0x1C 0.--2. "PRI56,Priority" "0,1,2,3,4,5,6,7" line.long 0x20 "P0_IDLE2LPI,Port 0 EEE Idle to LPI Counter Load Value Register" hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x20 0.--19. 1. "P0_IDLE2LPI,Port 0 EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted this value is loaded into the port 0 idle to LPI counter on each clock that the port 0 transmit is not idle" line.long 0x24 "P0_LPI2WAKE,Port 0 EEE LPI to Wake Counter Load Value Register" hexmask.long.word 0x24 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x24 0.--19. 1. "P0_LPI2WAKE,Port 0 EEE LPI to wake counter load value - When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted this value is loaded into the port 0 LPI to wake counter" group.long 0x100++0x03 line.long 0x00 "P1_CONTROL,CPSW PORT 1 control register" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 25. "P1_TX_CLKSTOP_EN,Port 1 Transmit clockstop enable 0 - RGMII transmit clockstop not enabled 1 - RGMII transmit clockstop enabled" "0,1" newline bitfld.long 0x00 24. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "Priority tagged packets have the zero VID..,Priority tagged packets are processed unchanged" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 21. "P1_VLAN_LTYPE2_EN,Port 1 VLAN LTYPE 2 enable" "disabled,VLAN LTYPE2 enabled on.." newline bitfld.long 0x00 20. "P1_VLAN_LTYPE1_EN,Port 1 VLAN LTYPE 1 enable" "disabled,VLAN LTYPE1 enabled on.." newline rbitfld.long 0x00 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. "P1_DSCP_PRI_EN,Port 1 DSCP Priority Enable" "DSCP priority disabled,DSCP priority enabled" newline bitfld.long 0x00 15. "P1_TS_107,Port 1 Time Sync Destination IP Address 107 enable 0 - disabled 1 - destination IP address (dec) 224.0.0.107 is enabled" "0,1" newline bitfld.long 0x00 14. "P1_TS_320,Port 1 Time Sync Destination Port Number 320 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 13. "P1_TS_319,Port 1 Time Sync Destination Port Number 319 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 12. "P1_TS_132,Port 1 Time Sync Destination IP Address 132 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 11. "P1_TS_131,Port 1 Time Sync Destination IP Address 131 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 10. "P1_TS_130,Port 1 Time Sync Destination IP Address 130 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 9. "P1_TS_129,Port 1 Time Sync Destination IP Address 129 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 8. "P1_TS_TTL_NONZERO,Port 1 Time Sync Time To Live Non-zero enable" "TTL must be zero,TTL may be any value" newline bitfld.long 0x00 7. "P1_TS_UNI_EN,Port 1 Time Sync Unicast Enable 0 - Unicast disabled 1 - Unicast enabled" "0,1" newline bitfld.long 0x00 6. "P1_TS_ANNEX_F_EN,Port 1 Time Sync Annex F enable 0 - Annex F disabled 1 - Annex F enabled" "0,1" newline bitfld.long 0x00 5. "P1_TS_ANNEX_E_EN,Port 1 Time Sync Annex E enable 0 - Annex E disabled 1 - Annex E enabled" "0,1" newline bitfld.long 0x00 4. "P1_TS_ANNEX_D_EN,Port 1 Time Sync Annex D enable" "Annex D disabled,Annex D enabled" newline bitfld.long 0x00 3. "P1_TS_LTYPE2_EN,Port 1 Time Sync LTYPE 2 enable" "disabled,enabled" newline bitfld.long 0x00 2. "P1_TS_LTYPE1_EN,Port 1 Time Sync LTYPE 1 enable" "disabled,enabled" newline bitfld.long 0x00 1. "P1_TS_TX_EN,Port 1 Time Sync Transmit Enable" "disabled,enabled" newline bitfld.long 0x00 0. "P1_TS_RX_EN,Port 1 Time Sync Receive Enable" "Port 1 Receive Time Sync disabled,Port 1 Receive Time Sync enabled" group.long 0x108++0x23 line.long 0x00 "P1_MAX_BLKS,CPSW PORT 1 maximum FIFO blocks register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 4.--8. "P1_TX_MAX_BLKS,Transmit FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical transmit priority queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--3. "P1_RX_MAX_BLKS,Receive FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical receive queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "P1_BLK_CNT,CPSW PORT 1 FIFO block usage count (read only)" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," newline bitfld.long 0x04 4.--8. "P1_TX_BLK_CNT,Port 1 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--3. "P1_RX_BLK_CNT,Port 1 Receive Block Count Usage - This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "P1_TX_IN_CTL,CPSW PORT 1 transmit FIFO control" rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPDMA channel can begin sending a packet to the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 20.--23. "TX_RATE_EN,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x08 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 16.--17. "TX_IN_SEL,Transmit FIFO Input Queue Type Select" "Normal priority mode,reserved,Rate Limit mode,reserved" newline bitfld.long 0x08 12.--15. "TX_BLKS_REM,Transmit FIFO Input blocks to subtract on non rate-limited traffic in rate limit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x08 10.--11. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x08 0.--9. 1. "TX_PRI_WDS,Transmit FIFO Words in queue" line.long 0x0C "P1_PORT_VLAN,CPSW PORT 1 VLAN register" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," newline bitfld.long 0x0C 13.--15. "PORT_PRI,Port VLAN Priority (7 is highest priority)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0C 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x10 "P1_TX_PRI_MAP,CPSW PORT 1 TX header priority to switch priority mapping register" rbitfld.long 0x10 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 28.--29. "PRI7,Priority" "0,1,2,3" newline rbitfld.long 0x10 26.--27. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 24.--25. "PRI6,Priority" "0,1,2,3" newline rbitfld.long 0x10 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 20.--21. "PRI5,Priority" "0,1,2,3" newline rbitfld.long 0x10 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 16.--17. "PRI4,Priority" "0,1,2,3" newline rbitfld.long 0x10 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 12.--13. "PRI3,Priority" "0,1,2,3" newline rbitfld.long 0x10 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 8.--9. "PRI2,Priority" "0,1,2,3" newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 4.--5. "PRI1,Priority" "0,1,2,3" newline rbitfld.long 0x10 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRI0,Priority" "0,1,2,3" line.long 0x14 "P1_TS_SEQ_MTYPE,CPSW PORT 1 time sync sequence ID offset and message type" hexmask.long.word 0x14 22.--31. 1. "RESERVED," newline bitfld.long 0x14 16.--21. "P1_TS_SEQ_ID_OFFSET,Port 1 Time Sync Sequence ID Offset This is the number of octets that the sequence ID is offset in the tx and rx time sync message header" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x14 0.--15. 1. "P1_TS_MSG_TYPE_EN,Port 1 Time Sync Message Type Enable - Each bit in this field enables the corresponding message type in receive and transmit time sync messages (Bit 0 enables message type 0 etc.)" line.long 0x18 "P1_SA_LO,CPSW CPGMAC_SL1 source address low register" hexmask.long.word 0x18 16.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits (byte 0)" newline hexmask.long.byte 0x18 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15:8 (byte 1)" line.long 0x1C "P1_SA_HI,CPSW CPGMAC_SL1 source address high register" hexmask.long.byte 0x1C 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23:16 (byte 2)" newline hexmask.long.byte 0x1C 16.--23. 1. "MACSRCADDR_31_24,Source Address bits 31:24 (byte 3)" newline hexmask.long.byte 0x1C 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39:32 (byte 4)" newline hexmask.long.byte 0x1C 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47:40 (byte 5)" line.long 0x20 "P1_SEND_PERCENT,CPSW PORT 1 transmit queue send percentages" hexmask.long.word 0x20 23.--31. 1. "RESERVED," newline hexmask.long.byte 0x20 16.--22. 1. "PRI3_SEND_PERCENT,Priority 3 Transmit Percentage - This percentage value is sent from FIFO priority 3 (maximum) whenCPSW_PTYPE[18] P1_PRI3_SHAPE_EN is set (queue shaping enabled)" newline rbitfld.long 0x20 15. "RESERVED," "0,1" newline hexmask.long.byte 0x20 8.--14. 1. "PRI2_SEND_PERCENT,Priority 2 Transmit Percentage - This percentage value is sent from FIFO priority 2 (maximum) whenCPSW_PTYPE[17] P1_PRI2_SHAPE_EN is set (queue shaping enabled)" newline rbitfld.long 0x20 7. "RESERVED," "0,1" newline hexmask.long.byte 0x20 0.--6. 1. "PRI1_SEND_PERCENT,Priority 1 Transmit Percentage - This percentage value is sent from FIFO priority 1 (maximum) when theCPSW_PTYPE[16] P1_PRI1_SHAPE_EN is set (queue shaping enabled)" group.long 0x130++0x27 line.long 0x00 "P1_RX_DSCP_PRI_MAP0,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 0" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 27. "RESERVED," "0,1" newline bitfld.long 0x00 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 23. "RESERVED," "0,1" newline bitfld.long 0x00 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED," "0,1" newline bitfld.long 0x00 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. "RESERVED," "0,1" newline bitfld.long 0x00 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED," "0,1" newline bitfld.long 0x00 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x04 "P1_RX_DSCP_PRI_MAP1,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 1" rbitfld.long 0x04 31. "RESERVED," "0,1" newline bitfld.long 0x04 28.--30. "PRI15,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 27. "RESERVED," "0,1" newline bitfld.long 0x04 24.--26. "PRI14,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 23. "RESERVED," "0,1" newline bitfld.long 0x04 20.--22. "PRI13,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED," "0,1" newline bitfld.long 0x04 16.--18. "PRI12,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 15. "RESERVED," "0,1" newline bitfld.long 0x04 12.--14. "PRI11,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 11. "RESERVED," "0,1" newline bitfld.long 0x04 8.--10. "PRI10,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED," "0,1" newline bitfld.long 0x04 4.--6. "PRI9,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 0.--2. "PRI8,Priority" "0,1,2,3,4,5,6,7" line.long 0x08 "P1_RX_DSCP_PRI_MAP2,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 2" rbitfld.long 0x08 31. "RESERVED," "0,1" newline bitfld.long 0x08 28.--30. "PRI23,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 27. "RESERVED," "0,1" newline bitfld.long 0x08 24.--26. "PRI22,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 23. "RESERVED," "0,1" newline bitfld.long 0x08 20.--22. "PRI21,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED," "0,1" newline bitfld.long 0x08 16.--18. "PRI20,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 15. "RESERVED," "0,1" newline bitfld.long 0x08 12.--14. "PRI19,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 11. "RESERVED," "0,1" newline bitfld.long 0x08 8.--10. "PRI18,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED," "0,1" newline bitfld.long 0x08 4.--6. "PRI17,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 0.--2. "PRI16,Priority" "0,1,2,3,4,5,6,7" line.long 0x0C "P1_RX_DSCP_PRI_MAP3,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 3" rbitfld.long 0x0C 31. "RESERVED," "0,1" newline bitfld.long 0x0C 28.--30. "PRI31,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 27. "RESERVED," "0,1" newline bitfld.long 0x0C 24.--26. "PRI30,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 23. "RESERVED," "0,1" newline bitfld.long 0x0C 20.--22. "PRI29,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED," "0,1" newline bitfld.long 0x0C 16.--18. "PRI28,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 15. "RESERVED," "0,1" newline bitfld.long 0x0C 12.--14. "PRI27,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 11. "RESERVED," "0,1" newline bitfld.long 0x0C 8.--10. "PRI26,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED," "0,1" newline bitfld.long 0x0C 4.--6. "PRI25,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 0.--2. "PRI24,Priority" "0,1,2,3,4,5,6,7" line.long 0x10 "P1_RX_DSCP_PRI_MAP4,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 4" rbitfld.long 0x10 31. "RESERVED," "0,1" newline bitfld.long 0x10 28.--30. "PRI39,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED," "0,1" newline bitfld.long 0x10 24.--26. "PRI38,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED," "0,1" newline bitfld.long 0x10 20.--22. "PRI37,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "RESERVED," "0,1" newline bitfld.long 0x10 16.--18. "PRI36,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 15. "RESERVED," "0,1" newline bitfld.long 0x10 12.--14. "PRI35,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 11. "RESERVED," "0,1" newline bitfld.long 0x10 8.--10. "PRI34,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 7. "RESERVED," "0,1" newline bitfld.long 0x10 4.--6. "PRI33,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 3. "RESERVED," "0,1" newline bitfld.long 0x10 0.--2. "PRI32,Priority" "0,1,2,3,4,5,6,7" line.long 0x14 "P1_RX_DSCP_PRI_MAP5,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 5" rbitfld.long 0x14 31. "RESERVED," "0,1" newline bitfld.long 0x14 28.--30. "PRI47,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED," "0,1" newline bitfld.long 0x14 24.--26. "PRI46,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED," "0,1" newline bitfld.long 0x14 20.--22. "PRI45,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED," "0,1" newline bitfld.long 0x14 16.--18. "PRI44,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED," "0,1" newline bitfld.long 0x14 12.--14. "PRI43,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED," "0,1" newline bitfld.long 0x14 8.--10. "PRI42,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED," "0,1" newline bitfld.long 0x14 4.--6. "PRI41,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 0.--2. "PRI40,Priority" "0,1,2,3,4,5,6,7" line.long 0x18 "P1_RX_DSCP_PRI_MAP6,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 6" rbitfld.long 0x18 31. "RESERVED," "0,1" newline bitfld.long 0x18 28.--30. "PRI55,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED," "0,1" newline bitfld.long 0x18 24.--26. "PRI54,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED," "0,1" newline bitfld.long 0x18 20.--22. "PRI53,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED," "0,1" newline bitfld.long 0x18 16.--18. "PRI52,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED," "0,1" newline bitfld.long 0x18 12.--14. "PRI51,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED," "0,1" newline bitfld.long 0x18 8.--10. "PRI50,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED," "0,1" newline bitfld.long 0x18 4.--6. "PRI49,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED," "0,1" newline bitfld.long 0x18 0.--2. "PRI48,Priority" "0,1,2,3,4,5,6,7" line.long 0x1C "P1_RX_DSCP_PRI_MAP7,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 7" rbitfld.long 0x1C 31. "RESERVED," "0,1" newline bitfld.long 0x1C 28.--30. "PRI63,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 27. "RESERVED," "0,1" newline bitfld.long 0x1C 24.--26. "PRI62,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 23. "RESERVED," "0,1" newline bitfld.long 0x1C 20.--22. "PRI61,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 19. "RESERVED," "0,1" newline bitfld.long 0x1C 16.--18. "PRI60,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 15. "RESERVED," "0,1" newline bitfld.long 0x1C 12.--14. "PRI59,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 11. "RESERVED," "0,1" newline bitfld.long 0x1C 8.--10. "PRI58,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 7. "RESERVED," "0,1" newline bitfld.long 0x1C 4.--6. "PRI57,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 3. "RESERVED," "0,1" newline bitfld.long 0x1C 0.--2. "PRI56,Priority" "0,1,2,3,4,5,6,7" line.long 0x20 "P1_IDLE2LPI,Port 1 EEE Idle to LPI Counter Load Value Register" hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x20 0.--19. 1. "P1_IDLE2LPI,Port 1 EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted this value is loaded into the port 1 idle to LPI counter on each clock that the port 1 transmit is not idle" line.long 0x24 "P1_LPI2WAKE,Port 1 EEE LPI to Wake Counter Load Value Register" hexmask.long.word 0x24 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x24 0.--19. 1. "P1_LPI2WAKE,Port 1 EEE LPI to wake counter load value - When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted this value is loaded into the port 1 LPI to wake counter" group.long 0x200++0x03 line.long 0x00 "P2_CONTROL,CPSW_3GF PORT 2 control register" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 25. "P2_TX_CLKSTOP_EN,Port 2 Transmit clockstop enable 0 - RGMII transmit clockstop not enabled 1 - RGMII transmit clockstop enabled" "0,1" newline bitfld.long 0x00 24. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged" "Priority tagged packets have the zero VID..,Priority tagged packets are processed unchanged" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 21. "P2_VLAN_LTYPE2_EN,Port 2 VLAN LTYPE 2 enable" "disabled,VLAN LTYPE2 enabled on.." newline bitfld.long 0x00 20. "P2_VLAN_LTYPE1_EN,Port 2 VLAN LTYPE 1 enable" "disabled,VLAN LTYPE1 enabled on.." newline rbitfld.long 0x00 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. "P2_DSCP_PRI_EN,Port 0 DSCP Priority Enable" "DSCP priority disabled,DSCP priority enabled" newline bitfld.long 0x00 15. "P2_TS_107,Port 2 Time Sync Destination IP Address 107 enable 0 - disabled 1 - destination IP address (dec) 224.0.0.107 is enabled" "0,1" newline bitfld.long 0x00 14. "P2_TS_320,Port 2 Time Sync Destination Port Number 320 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 13. "P2_TS_319,Port 2 Time Sync Destination Port Number 319 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 12. "P2_TS_132,Port 2 Time Sync Destination IP Address 132 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 11. "P2_TS_131,Port 2 Time Sync Destination IP Address 131 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 10. "P2_TS_130,Port 2 Time Sync Destination IP Address 130 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 9. "P2_TS_129,Port 2 Time Sync Destination IP Address 129 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 8. "P2_TS_TTL_NONZERO,Port 2 Time Sync Time To Live Non-zero enable" "TTL must be zero,TTL may be any value" newline bitfld.long 0x00 7. "P2_TS_UNI_EN,Port 2 Time Sync Unicast Enable 0 - Unicast disabled 1 - Unicast enabled" "0,1" newline bitfld.long 0x00 6. "P2_TS_ANNEX_F_EN,Port 2 Time Sync Annex F enable 0 - Annex F disabled 1 - Annex F enabled" "0,1" newline bitfld.long 0x00 5. "P2_TS_ANNEX_E_EN,Port 2 Time Sync Annex E enable 0 - Annex E disabled 1 - Annex E enabled" "0,1" newline bitfld.long 0x00 4. "P2_TS_ANNEX_D_EN,Port 2 Time Sync Annex D enable" "Annex D disabled,Annex D enabled" newline bitfld.long 0x00 3. "P2_TS_LTYPE2_EN,Port 2 Time Sync LTYPE 2 enable" "disabled,enabled" newline bitfld.long 0x00 2. "P2_TS_LTYPE1_EN,Port 2 Time Sync LTYPE 1 enable" "disabled,enabled" newline bitfld.long 0x00 1. "P2_TS_TX_EN,Port 2 Time Sync Transmit Enable" "disabled,enabled" newline bitfld.long 0x00 0. "P2_TS_RX_EN,Port 2 Time Sync Receive Enable" "Port 1 Receive Time Sync disabled,Port 1 Receive Time Sync enabled" group.long 0x208++0x23 line.long 0x00 "P2_MAX_BLKS,CPSW PORT 2 maximum FIFO blocks register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 4.--8. "P2_TX_MAX_BLKS,Transmit FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical transmit priority queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--3. "P2_RX_MAX_BLKS,Receive FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical receive queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "P2_BLK_CNT,CPSW PORT 2 FIFO block usage count (read only)" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED," newline bitfld.long 0x04 4.--8. "P2_TX_BLK_CNT,Port 2 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--3. "P2_RX_BLK_CNT,Port 2 Receive Block Count Usage - This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "P2_TX_IN_CTL,CPSW PORT 2 transmit FIFO control" bitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. "HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPDMA channel can begin sending a packet to the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 20.--23. "TX_RATE_EN,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 16.--17. "TX_IN_SEL,Transmit FIFO Input Queue Type Select" "Normal priority mode,reserved,Rate Limit mode,reserved" newline bitfld.long 0x08 12.--15. "TX_BLKS_REM,Transmit FIFO Input blocks to subtract on non rate-limited traffic in rate limit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 10.--11. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x08 0.--9. 1. "TX_PRI_WDS,Transmit FIFO Words in queue" line.long 0x0C "P2_PORT_VLAN,CPSW PORT 2 VLAN register" hexmask.long.word 0x0C 16.--31. 1. "RESERVED," newline bitfld.long 0x0C 13.--15. "PORT_PRI,Port VLAN Priority (7 is highest priority)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0C 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x10 "P2_TX_PRI_MAP,CPSW PORT 2 TX header priority to switch priority mapping register" rbitfld.long 0x10 30.--31. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 28.--29. "PRI7,Priority" "0,1,2,3" newline rbitfld.long 0x10 26.--27. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 24.--25. "PRI6,Priority" "0,1,2,3" newline rbitfld.long 0x10 22.--23. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 20.--21. "PRI5,Priority" "0,1,2,3" newline rbitfld.long 0x10 18.--19. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 16.--17. "PRI4,Priority" "0,1,2,3" newline rbitfld.long 0x10 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 12.--13. "PRI3,Priority" "0,1,2,3" newline rbitfld.long 0x10 10.--11. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 8.--9. "PRI2,Priority" "0,1,2,3" newline rbitfld.long 0x10 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 4.--5. "PRI1,Priority" "0,1,2,3" newline rbitfld.long 0x10 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x10 0.--1. "PRI0,Priority" "0,1,2,3" line.long 0x14 "P2_TS_SEQ_MTYPE,CPSW_3GF PORT 2 time sync sequence ID offset and message type" hexmask.long.word 0x14 22.--31. 1. "RESERVED," newline bitfld.long 0x14 16.--21. "P2_TS_SEQ_ID_OFFSET,Port 2 Time Sync Sequence ID Offset This is the number of octets that the sequence ID is offset in the tx and rx time sync message header" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x14 0.--15. 1. "P2_TS_MSG_TYPE_EN,Port 2 Time Sync Message Type Enable - Each bit in this field enables the corresponding message type in receive and transmit time sync messages (Bit 0 enables message type 0 etc.)" line.long 0x18 "P2_SA_LO,CPSW CPGMAC_SL2 source address low register" hexmask.long.word 0x18 16.--31. 1. "RESERVED," newline hexmask.long.byte 0x18 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits (byte 0)" newline hexmask.long.byte 0x18 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15:8 (byte 1)" line.long 0x1C "P2_SA_HI,CPSW CPGMAC_SL2 source address high register" hexmask.long.byte 0x1C 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23:16 (byte 2)" newline hexmask.long.byte 0x1C 16.--23. 1. "MACSRCADDR_31_23,Source Address bits 31:23 (byte 3)" newline hexmask.long.byte 0x1C 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39:32 (byte 4)" newline hexmask.long.byte 0x1C 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47:40 (byte 5)" line.long 0x20 "P2_SEND_PERCENT,CPSW PORT 2 transmit queue send percentages" hexmask.long.word 0x20 23.--31. 1. "RESERVED," newline hexmask.long.byte 0x20 16.--22. 1. "PRI3_SEND_PERCENT,Priority 3 Transmit Percentage - This percentage value is sent from FIFO priority 3 (maximum) when theCPSW_PTYPE[21] P2_PRI3_SHAPE_EN is set (queue shaping enabled)" newline rbitfld.long 0x20 15. "RESERVED," "0,1" newline hexmask.long.byte 0x20 8.--14. 1. "PRI2_SEND_PERCENT,Priority 2 Transmit Percentage - This percentage value is sent from FIFO priority 2 (maximum) when theCPSW_PTYPE[20] P2_PRI2_SHAPE_EN is set (queue shaping enabled)" newline rbitfld.long 0x20 7. "RESERVED," "0,1" newline hexmask.long.byte 0x20 0.--6. 1. "PRI1_SEND_PERCENT,Priority 1 Transmit Percentage - This percentage value is sent from FIFO priority 1 (maximum) when theCPSW_PTYPE[19] P2_PRI1_SHAPE_EN is set (queue shaping enabled)" group.long 0x230++0x27 line.long 0x00 "P2_RX_DSCP_PRI_MAP0,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 0" rbitfld.long 0x00 31. "RESERVED," "0,1" newline bitfld.long 0x00 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 27. "RESERVED," "0,1" newline bitfld.long 0x00 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 23. "RESERVED," "0,1" newline bitfld.long 0x00 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED," "0,1" newline bitfld.long 0x00 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 15. "RESERVED," "0,1" newline bitfld.long 0x00 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. "RESERVED," "0,1" newline bitfld.long 0x00 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED," "0,1" newline bitfld.long 0x00 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x04 "P2_RX_DSCP_PRI_MAP1,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 1" rbitfld.long 0x04 31. "RESERVED," "0,1" newline bitfld.long 0x04 28.--30. "PRI15,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 27. "RESERVED," "0,1" newline bitfld.long 0x04 24.--26. "PRI14,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 23. "RESERVED," "0,1" newline bitfld.long 0x04 20.--22. "PRI13,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED," "0,1" newline bitfld.long 0x04 16.--18. "PRI12,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 15. "RESERVED," "0,1" newline bitfld.long 0x04 12.--14. "PRI11,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 11. "RESERVED," "0,1" newline bitfld.long 0x04 8.--10. "PRI10,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED," "0,1" newline bitfld.long 0x04 4.--6. "PRI9,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 0.--2. "PRI8,Priority" "0,1,2,3,4,5,6,7" line.long 0x08 "P2_RX_DSCP_PRI_MAP2,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 2" rbitfld.long 0x08 31. "RESERVED," "0,1" newline bitfld.long 0x08 28.--30. "PRI23,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 27. "RESERVED," "0,1" newline bitfld.long 0x08 24.--26. "PRI22,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 23. "RESERVED," "0,1" newline bitfld.long 0x08 20.--22. "PRI21,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED," "0,1" newline bitfld.long 0x08 16.--18. "PRI20,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 15. "RESERVED," "0,1" newline bitfld.long 0x08 12.--14. "PRI19,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 11. "RESERVED," "0,1" newline bitfld.long 0x08 8.--10. "PRI18,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED," "0,1" newline bitfld.long 0x08 4.--6. "PRI17,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED," "0,1" newline bitfld.long 0x08 0.--2. "PRI16,Priority" "0,1,2,3,4,5,6,7" line.long 0x0C "P2_RX_DSCP_PRI_MAP3,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 3" rbitfld.long 0x0C 31. "RESERVED," "0,1" newline bitfld.long 0x0C 28.--30. "PRI31,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 27. "RESERVED," "0,1" newline bitfld.long 0x0C 24.--26. "PRI30,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 23. "RESERVED," "0,1" newline bitfld.long 0x0C 20.--22. "PRI29,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED," "0,1" newline bitfld.long 0x0C 16.--18. "PRI28,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 15. "RESERVED," "0,1" newline bitfld.long 0x0C 12.--14. "PRI27,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 11. "RESERVED," "0,1" newline bitfld.long 0x0C 8.--10. "PRI26,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED," "0,1" newline bitfld.long 0x0C 4.--6. "PRI25,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 0.--2. "PRI24,Priority" "0,1,2,3,4,5,6,7" line.long 0x10 "P2_RX_DSCP_PRI_MAP4,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 4" rbitfld.long 0x10 31. "RESERVED," "0,1" newline bitfld.long 0x10 28.--30. "PRI39,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED," "0,1" newline bitfld.long 0x10 24.--26. "PRI38,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED," "0,1" newline bitfld.long 0x10 20.--22. "PRI37,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "RESERVED," "0,1" newline bitfld.long 0x10 16.--18. "PRI36,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 15. "RESERVED," "0,1" newline bitfld.long 0x10 12.--14. "PRI35,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 11. "RESERVED," "0,1" newline bitfld.long 0x10 8.--10. "PRI34,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 7. "RESERVED," "0,1" newline bitfld.long 0x10 4.--6. "PRI33,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 3. "RESERVED," "0,1" newline bitfld.long 0x10 0.--2. "PRI32,Priority" "0,1,2,3,4,5,6,7" line.long 0x14 "P2_RX_DSCP_PRI_MAP5,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 5" rbitfld.long 0x14 31. "RESERVED," "0,1" newline bitfld.long 0x14 28.--30. "PRI47,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED," "0,1" newline bitfld.long 0x14 24.--26. "PRI46,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED," "0,1" newline bitfld.long 0x14 20.--22. "PRI45,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED," "0,1" newline bitfld.long 0x14 16.--18. "PRI44,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED," "0,1" newline bitfld.long 0x14 12.--14. "PRI43,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED," "0,1" newline bitfld.long 0x14 8.--10. "PRI42,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED," "0,1" newline bitfld.long 0x14 4.--6. "PRI41,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 0.--2. "PRI40,Priority" "0,1,2,3,4,5,6,7" line.long 0x18 "P2_RX_DSCP_PRI_MAP6,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 6" rbitfld.long 0x18 31. "RESERVED," "0,1" newline bitfld.long 0x18 28.--30. "PRI55,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED," "0,1" newline bitfld.long 0x18 24.--26. "PRI54,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED," "0,1" newline bitfld.long 0x18 20.--22. "PRI53,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED," "0,1" newline bitfld.long 0x18 16.--18. "PRI52,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED," "0,1" newline bitfld.long 0x18 12.--14. "PRI51,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED," "0,1" newline bitfld.long 0x18 8.--10. "PRI50,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED," "0,1" newline bitfld.long 0x18 4.--6. "PRI49,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED," "0,1" newline bitfld.long 0x18 0.--2. "PRI48,Priority" "0,1,2,3,4,5,6,7" line.long 0x1C "P2_RX_DSCP_PRI_MAP7,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 7" rbitfld.long 0x1C 31. "RESERVED," "0,1" newline bitfld.long 0x1C 28.--30. "PRI63,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 27. "RESERVED," "0,1" newline bitfld.long 0x1C 24.--26. "PRI62,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 23. "RESERVED," "0,1" newline bitfld.long 0x1C 20.--22. "PRI61,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 19. "RESERVED," "0,1" newline bitfld.long 0x1C 16.--18. "PRI60,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 15. "RESERVED," "0,1" newline bitfld.long 0x1C 12.--14. "PRI59,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 11. "RESERVED," "0,1" newline bitfld.long 0x1C 8.--10. "PRI58,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 7. "RESERVED," "0,1" newline bitfld.long 0x1C 4.--6. "PRI57,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 3. "RESERVED," "0,1" newline bitfld.long 0x1C 0.--2. "PRI56,Priority" "0,1,2,3,4,5,6,7" line.long 0x20 "P2_IDLE2LPI,Port 2 EEE Idle to LPI Counter Load Value Register" hexmask.long.word 0x20 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x20 0.--19. 1. "P2_IDLE2LPI,Port 2 EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted this value is loaded into the port 2 idle to LPI counter on each clock that the port 2 transmit is not idle" line.long 0x24 "P2_LPI2WAKE,Port 2 EEE LPI to Wake Counter Load Value Register" hexmask.long.word 0x24 20.--31. 1. "RESERVED," newline hexmask.long.tbyte 0x24 0.--19. 1. "P2_LPI2WAKE,Port 2 EEE LPI to wake counter load value - When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted this value is loaded into the port 2 LPI to wake counter" width 0x0B tree.end tree "PRM_TARG" base ad:0x4AE08000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "PWMSS_CFG" base ad:0x4843E000 rgroup.long 0x00++0x0F line.long 0x00 "PWMSS_IDVER,IP Revision Register" line.long 0x04 "PWMSS_SYSCONFIG,This register controls the PWMSS local Idle mode clock management and software reset" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline rbitfld.long 0x04 1. "RESERVED," "0,1" bitfld.long 0x04 0. "SOFTRESET,Software reset" "Software reset is completed,Software reset assertion" line.long 0x08 "PWMSS_CLKCONFIG,The clock configuration register is used in the PWMSS for clkstop req and clk_en control to the ePWM/ eHRPWM. eCAP and eQEP submodules.Note: PWMSS Module Local Clock Gating feature is not supported" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "EPWM_CLKSTOP_REQ,This bit controls the clock stop input to the ePWM / eHRPWM module" "No effect,A request to stop.." newline bitfld.long 0x08 8. "EPWM_CLK_EN,This bit controls the interface clock enable (clk_en) input to the ePWM / eHRPWM module" "No effect,Enables the interface.." rbitfld.long 0x08 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x08 5. "EQEP_CLKSTOP_REQ,This bit controls the clock stop input to the eQEP module" "No effect,A request to stop.." bitfld.long 0x08 4. "EQEP_CLK_EN,This bit controls the interface clock enable (clk_en) input to the eQEP module" "No effect,Enables the interface.." newline rbitfld.long 0x08 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x08 1. "ECAP_CLKSTOP_REQ,This bit controls the clock stop input to the eCAP module" "No effect,A request to stop.." newline bitfld.long 0x08 0. "ECAP_CLK_EN,This bit controls the interface clock enable (clk_en) input to the eCAP module" "No effect,Enables the interface.." line.long 0x0C "PWMSS_CLKSTATUS,The clock status register is used in the PWMSS to indicate clock stop acknowledge (clkstop_ack) and clock enable (clk_en) acknowledge status for the ePWM/ eHRPWM. eCAP and eQEP submodules.Note:PWMSS Module Local Clock Gating feature is.." hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED," bitfld.long 0x0C 9. "EPWM_CLKSTOP_ACK,This bit is the clkstop_req_ack status output of the ePWM / eHRPWM module" "No interface clock stop acknowledged,Interface clock stop request is acknowledged for.." newline bitfld.long 0x0C 8. "EPWM_CLK_EN_ACK,This bit is the clk_en status output of the ePWM / eHRPWM module" "No clock enable request acknowledged,Interface clock enable request is acknowledged.." bitfld.long 0x0C 6.--7. "RESERVED," "0,1,2,3" newline bitfld.long 0x0C 5. "EQEP_CLKSTOP_ACK,This bit is the clkstop_req_ack status output of the eQEP module" "No interface clock stop acknowledged,Interface clock stop request is acknowledged for.." bitfld.long 0x0C 4. "EQEP_CLK_EN_ACK,This bit is the clk_en status output of the eQEP module" "No clock enable request acknowledged,Interface clock enable request is acknowledged.." newline bitfld.long 0x0C 2.--3. "RESERVED," "0,1,2,3" bitfld.long 0x0C 1. "ECAP_CLKSTOP_ACK,TThis bit is the clkstop_req_ack status output of the eCAP module" "No interface clock stop acknowledged,Interface clock stop request is acknowledged for.." newline bitfld.long 0x0C 0. "ECAP_CLK_EN_ACK,TThis bit is the clk_en status output of the eCAP module" "No clock enable request acknowledged,Interface clock enable request is acknowledged.." width 0x0B tree.end tree "PWMSS_ECAP" base ad:0x4843E100 group.long 0x00++0x17 line.long 0x00 "PWMSS_ECAP_TSCNT,Time Stamp Counter Register" line.long 0x04 "PWMSS_ECAP_CNTPHS,Counter Phase Control Register" line.long 0x08 "PWMSS_ECAP_CAP1,Capture-1 Register" line.long 0x0C "PWMSS_ECAP_CAP2,Capture-2 Register" line.long 0x10 "PWMSS_ECAP_CAP3,Capture-3 Register" line.long 0x14 "PWMSS_ECAP_CAP4,Capture-4 Register" group.word 0x28++0x0B line.word 0x00 "PWMSS_ECAP_ECCTL1,ECAP Control Register1" bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Control" "TSCNT counter stops immediately on emulation..,TSCNT counter runs until = 0,TSCNT counter is unaffected by emulation suspend..,TSCNT counter is unaffected by emulation suspend.." bitfld.word 0x00 9.--13. "EVTFLTPS,Event Filter prescale select" "Divide by 1 (i.e . no prescale..,Divide by 2,Divide by 4,Divide by 6,Divide by 8,Divide by 10,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 60,Divide by 62" newline bitfld.word 0x00 8. "CAPLDEN,Enable Loading ofPWMSS_ECAP_CAP1 to PWMSS_ECAP_CAP4 registers on a capture event" "Disable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register..,Enable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register.." bitfld.word 0x00 7. "CTRRST4,Counter Reset on Capture Event 4" "Do not reset counter on Capture Event 4..,Reset counter after Capture Event 4 time-stamp.." newline bitfld.word 0x00 6. "CAP4POL,Capture Event 4 Polarity select" "Capture Event 4 triggered on a rising edge (RE),Capture Event 4 triggered on a falling edge (FE)" bitfld.word 0x00 5. "CTRRST3,Counter Reset on Capture Event 3" "Do not reset counter on Capture Event 3..,Reset counter after Event 3 time-stamp has been.." newline bitfld.word 0x00 4. "CAP3POL,Capture Event 3 Polarity select" "Capture Event 3 triggered on a rising edge (RE),Capture Event 3 triggered on a falling edge (FE)" bitfld.word 0x00 3. "CTRRST2,Counter Reset on Capture Event 2" "Do not reset counter on Capture Event 2..,Reset counter after Event 2 time-stamp has been.." newline bitfld.word 0x00 2. "CAP2POL,Capture Event 2 Polarity select" "Capture Event 2 triggered on a rising edge (RE),Capture Event 2 triggered on a falling edge (FE)" bitfld.word 0x00 1. "CTRRST1,Counter Reset on Capture Event 1" "Do not reset counter on Capture Event 1..,Reset counter after Event 1 time-stamp has been.." newline bitfld.word 0x00 0. "CAP1POL,Capture Event 1 Polarity select" "Capture Event 1 triggered on a rising edge (RE),Capture Event 1 triggered on a falling edge (FE)" line.word 0x02 "PWMSS_ECAP_ECCTL2,ECAP Control Register 2" rbitfld.word 0x02 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 10. "APWMPOL,APWM output polarity select" "Output is active high (Compare value defines..,Output is active low (Compare value defines low.." newline bitfld.word 0x02 9. "CAPAPWM,CAP/APWM operating mode select" "0,1" bitfld.word 0x02 8. "SWSYNC,Software-forced Counter (TSCNT) Synchronizing" "Writing a zero has no effect,Writing a one forces a TSCNT shadow load of ECAP.." newline bitfld.word 0x02 6.--7. "SYNCO_SEL,Sync-Out Select" "Select sync-in event to be the sync-out signal..,Select TSCNT = PRD event to be the sync-out signal,Disable sync out signal,Disable sync out signal" bitfld.word 0x02 5. "SYNCI_EN,Counter (TSCNT) Sync-In select mode" "Disable sync-in option,Enable counter (TSCNT) to be loaded from" newline bitfld.word 0x02 4. "TSCNTSTP,Time Stamp (TSCNT) Counter Stop (freeze) Control" "TSCNT stopped,TSCNT free-running" bitfld.word 0x02 3. "REARMRESET,One-Shot Re-Arming Control that is wait for stop trigger" "Has no effect (reading always returns a 0),Arms the one-shot sequence as follows" newline bitfld.word 0x02 1.--2. "STOPVALUE,Stop value for one-shot mode" "Stop after Capture Event 1 in one-shot mode,Stop after Capture Event 2 in one-shot mode,Stop after Capture Event 3 in one-shot mode,Stop after Capture Event 4 in one-shot mode" bitfld.word 0x02 0. "CONTONESHT,Continuous or one-shot mode control (applicable only in capture mode)" "Operate in continuous mode,Operate in one-shot mode" line.word 0x04 "PWMSS_ECAP_ECEINT,ECAP Interrupt Enable Register" hexmask.word.byte 0x04 8.--15. 1. "RESERVED," bitfld.word 0x04 7. "CMPEQ,Counter Equal" "Disable Compare Equal as an Interrupt source,Enable Compare Equal as an Interrupt source" newline bitfld.word 0x04 6. "PRDEQ,Counter Equal" "Disable Period Equal as an Interrupt source,Enable Period Equal as an Interrupt source" bitfld.word 0x04 5. "CNTOVF,Counter Overflow Interrupt Enable" "Disable counter Overflow as an Interrupt source,Enable counter Overflow as an Interrupt source" newline bitfld.word 0x04 4. "CEVT4,Capture Event 4 Interrupt Enable" "Disable Capture Event 4 as an Interrupt source,Enable Capture Event 4 as an Interrupt source" bitfld.word 0x04 3. "CEVT3,Capture Event 3 Interrupt Enable" "Disable Capture Event 3 as an Interrupt source,Enable Capture Event 3 as an Interrupt source" newline bitfld.word 0x04 2. "CEVT2,Capture Event 2 Interrupt Enable" "Disable Capture Event 2 as an Interrupt source,Enable Capture Event 2 as an Interrupt source" bitfld.word 0x04 1. "CEVT1,Capture Event 1 Interrupt Enable" "Disable Capture Event 1 as an Interrupt source,Enable Capture Event 1 as an Interrupt source" newline rbitfld.word 0x04 0. "RESERVED," "0,1" line.word 0x06 "PWMSS_ECAP_ECFLG,ECAP Interrupt Flag Register" hexmask.word.byte 0x06 8.--15. 1. "RESERVED," bitfld.word 0x06 7. "CMPEQ,Compare Equal Compare Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) reached the.." newline bitfld.word 0x06 6. "PRDEQ,Counter Equal Period Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) reached the period.." bitfld.word 0x06 5. "CNTOVF,Counter Overflow Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) has made the.." newline bitfld.word 0x06 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode" "Indicates no event occurred,Indicates the fourth event occurred at ECAP pin" bitfld.word 0x06 3. "CEVT3,Capture Event 3 Status Flag" "Indicates no event occurred,Indicates the third event occurred at ECAP pin" newline bitfld.word 0x06 2. "CEVT2,Capture Event 2 Status Flag" "Indicates no event occurred,Indicates the second event occurred at ECAP pin" bitfld.word 0x06 1. "CEVT1,Capture Event 1 Status Flag" "Indicates no event occurred,Indicates the first event occurred at ECAP pin" newline bitfld.word 0x06 0. "INT,Global Interrupt Status Flag" "Indicates no interrupt generated,Indicates that an interrupt was generated" line.word 0x08 "PWMSS_ECAP_ECCLR,ECAP Interrupt Clear Register" hexmask.word.byte 0x08 8.--15. 1. "RESERVED," bitfld.word 0x08 7. "CMPEQ,Counter Equal Compare Status Flag" "Writing a 0 has no effect,Writing a 1 clears the TSCNT=CMP flag condition" newline bitfld.word 0x08 6. "PRDEQ,Counter Equal Period Status Flag" "Writing a 0 has no effect,Writing a 1 clears the TSCNT=PRD flag condition" bitfld.word 0x08 5. "CNTOVF,Counter Overflow Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CNTOVF flag condition" newline bitfld.word 0x08 4. "CEVT4,Capture Event 4 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT3 flag condition" bitfld.word 0x08 3. "CEVT3,Capture Event 3 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT3 flag condition" newline bitfld.word 0x08 2. "CEVT2,Capture Event 2 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT2 flag condition" bitfld.word 0x08 1. "CEVT1,Capture Event 1 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT1 flag condition" newline bitfld.word 0x08 0. "INT,Global Interrupt Clear Flag" "Writing a 0 has no effect,Writing a 1 clears the INT flag and enable.." line.word 0x0A "PWMSS_ECAP_ECFRC,ECAP Interrupt Forcing Register" hexmask.word.byte 0x0A 8.--15. 1. "RESERVED," bitfld.word 0x0A 7. "CMPEQ,Force Counter Equal Compare Interrupt" "No effect,Writing a 1 sets the TSCNT=CMP flag bit" newline bitfld.word 0x0A 6. "PRDEQ,Force Counter Equal Period Interrupt" "No effect,Writing a 1 sets the TSCNT=PRD flag bit" bitfld.word 0x0A 5. "CNTOVF,Force Counter Overflow" "No effect,Writing a 1 to this bit sets the CNTOVF flag bit" newline bitfld.word 0x0A 4. "CEVT4,Force Capture Event 4" "No effect,Writing a 1 sets the CEVT4 flag bit" bitfld.word 0x0A 3. "CEVT3,Force Capture Event 3" "No effect,Writing a 1 sets the CEVT3 flag bit" newline bitfld.word 0x0A 2. "CEVT2,Force Capture Event 2" "No effect,Writing a 1 sets the CEVT2 flag bit" bitfld.word 0x0A 1. "CEVT1,Always reads back a 0" "No effect,Writing a 1 sets the.." newline rbitfld.word 0x0A 0. "RESERVED," "0,1" rgroup.long 0x5C++0x03 line.long 0x00 "PWMSS_ECAP_PID,ECAP Revision ID" width 0x0B tree.end tree "PWMSS_EPWM" base ad:0x4843E200 group.word 0x00++0x0B line.word 0x00 "EPWM_TBCTL," bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Mode Bits" "Stop after the next time-base counter increment..,Stop when counter completes a whole cycle,Free run,Free run" bitfld.word 0x00 13. "PHSDIR,Phase Direction Bit" "Count down after the synchronization event,Count up after the synchronization event" newline bitfld.word 0x00 10.--12. "CLKDIV,Time-base Clock Prescale Bits" "/1..,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits" "/1,/2..,/4,/6,/8,/10,/12,/14" newline bitfld.word 0x00 6. "SWFSYNC,Software Forced Synchronization Pulse" "Writing a 0 has no effect and reads always..,Writing a 1 forces a one-time synchronization.." bitfld.word 0x00 4.--5. "SYNCOSEL,Synchronization Output Select" "Time-base counter equal to zero (,TBCNT =,TBCNT = CMPB,Disable EPWM_SYNCO signal" newline bitfld.word 0x00 3. "PRDLD,Active Period Register Load From Shadow Register Select" "The period register (,Load" bitfld.word 0x00 2. "PHSEN,Counter Register Load From Phase Register Enable" "Do not load the time-base counter (,Load the time-base counter with the phase.." newline bitfld.word 0x00 0.--1. "CTRMODE,Counter Mode" "Up-count mode,Down-count mode,Up-down-count mode,Stop-freeze counter operation (default on.." line.word 0x02 "EPWM_TBSTS," hexmask.word 0x02 3.--15. 1. "RESERVED," bitfld.word 0x02 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "Reading a 0 indicates the time-base counter..,Reading a 1 on this bit indicates that the.." newline bitfld.word 0x02 1. "SYNCI,Input Synchronization Latched Status Bit" "Writing a 0 will have no effect,Reading a 1 on this bit indicates that an.." bitfld.word 0x02 0. "CTRDIR,Time-Base Counter Direction Status Bit" "Time-Base Counter is currently counting down,Time-Base Counter is currently counting up" line.word 0x04 "HRPWM_TBPHSHR," hexmask.word.byte 0x04 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" hexmask.word.byte 0x04 0.--7. 1. "RESERVED," line.word 0x06 "EPWM_TBPHS," line.word 0x08 "EPWM_TBCNT," line.word 0x0A "EPWM_TBPRD," group.word 0x0E++0x17 line.word 0x00 "EPWM_CMPCTL," rbitfld.word 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 9. "SHDWBFULL,Counter-compare B ( 0x0 = CMPB shadow FIFO not full yet 0x1 = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value" "CMPB shadow FIFO not full yet,Indicates the CMPB shadow FIFO is full" newline bitfld.word 0x00 8. "SHDWAFULL,Counter-compare A ( 0x0 = CMPA shadow FIFO not full yet 0x1 = Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value" "CMPA shadow FIFO not full yet,Indicates the CMPA shadow FIFO is full a CPU.." rbitfld.word 0x00 7. "RESERVED," "0,1" newline bitfld.word 0x00 6. "SHDWBMODE,Counter-compare B ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register.." "Shadow mode,Immediate mode" rbitfld.word 0x00 5. "RESERVED," "0,1" newline bitfld.word 0x00 4. "SHDWAMODE,Counter-compare A ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register .." "Shadow mode,Immediate mode" bitfld.word 0x00 2.--3. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode" "Time-base counter equal to zero (,Load on TBCNT = PRD,Load on either TBCNT = 0 or TBCNT = PRD,Freeze (no loads possible)" newline bitfld.word 0x00 0.--1. "LOADAMODE,Active Counter-Compare A ( 0x0 = Load on TBCNT = 0: Time-base counter equal to zero ( 0x1 = Load on TBCNT = PRD: Time-base counter equal to period ( 0x2 = Load on either TBCNT = 0 or TBCNT = PRD 0x3 = Freeze (no loads possible)" "Time-base counter equal to zero (,Load on TBCNT = PRD,Load on either TBCNT = 0 or TBCNT = PRD,Freeze (no loads possible)" line.word 0x02 "HRPWM_CMPAHR," hexmask.word.byte 0x02 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control" hexmask.word.byte 0x02 0.--7. 1. "RESERVED," line.word 0x04 "EPWM_CMPA," line.word 0x06 "EPWM_CMPB," line.word 0x08 "EPWM_AQCTLA," rbitfld.word 0x08 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x08 10.--11. "CBD,Action when the time-base counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWM1A output" newline bitfld.word 0x08 8.--9. "CBU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWM1A output" bitfld.word 0x08 6.--7. "CAD,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWM1A output" newline bitfld.word 0x08 4.--5. "CAU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWM1A output" bitfld.word 0x08 2.--3. "PRD,Action when the counter equals the period" "Do nothing (action disabled),Clear,Set,Toggle EPWM1A output" newline bitfld.word 0x08 0.--1. "ZRO,Action when counter equals zero" "Do nothing (action disabled),Clear,Set,Toggle EPWM1A output" line.word 0x0A "EPWM_AQCTLB," rbitfld.word 0x0A 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0A 10.--11. "CBD,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWM1B output" newline bitfld.word 0x0A 8.--9. "CBU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWM1B output" bitfld.word 0x0A 6.--7. "CAD,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWM1B output" newline bitfld.word 0x0A 4.--5. "CAU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWM1B output" bitfld.word 0x0A 2.--3. "PRD,Action when the counter equals the period" "Do nothing (action disabled),Clear,Set,Toggle EPWM1B output" newline bitfld.word 0x0A 0.--1. "ZRO,Action when counter equals zero" "Do nothing (action disabled),Clear,Set,Toggle EPWM1B output" line.word 0x0C "EPWM_AQSFRC," hexmask.word.byte 0x0C 8.--15. 1. "RESERVED," bitfld.word 0x0C 6.--7. "RLDCSF," "?,Load on event counter equals period,Load on event counter equals zero or counter..,Load immediately (the active register is.." newline bitfld.word 0x0C 5. "OTSFB,One-Time Software Forced Event on Output B" "Writing a 0 (zero) has no effect,Initiates a single s/w forced event" bitfld.word 0x0C 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "Does nothing (action disabled),Clear (low),Set (high),Toggle (Low -> High High -> Low)" newline bitfld.word 0x0C 2. "OTSFA,One-Time Software Forced Event on Output A" "Writing a 0 (zero) has no effect,Initiates a single software forced event" bitfld.word 0x0C 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "Does nothing (action disabled),Clear (low),Set (high),Toggle (Low -> High High -> Low)" line.word 0x0E "EPWM_AQCSFRC," hexmask.word 0x0E 4.--15. 1. "RESERVED," bitfld.word 0x0E 2.--3. "CSFB,Continuous Software Force on Output B" "Forcing disabled that is has no effect,Forces a continuous low on output B,Forces a continuous high on output B,Software forcing is disabled and has no effect" newline bitfld.word 0x0E 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "Forcing disabled that is has no effect,Forces a continuous low on output A,Forces a continuous high on output A,Software forcing is disabled and has no effect" line.word 0x10 "EPWM_DBCTL," hexmask.word 0x10 6.--15. 1. "RESERVED," bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control" "EPWM1A In (from the action-qualifier) is the..,EPWM1B In (from the action-qualifier) is the..,EPWM1A In (from the action-qualifier) is the..,EPWM1B In (from the action-qualifier) is the.." newline bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control" "Active high (AH) mode,Active low complementary (ALC) mode,Active high complementary (AHC),Active low (AL) mode" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control" "Dead-band generation is bypassed for both output..,Disable rising-edge delay,Disable falling-edge delay,Dead-band is fully enabled for both rising-edge.." line.word 0x12 "EPWM_DBRED," rbitfld.word 0x12 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count" line.word 0x14 "EPWM_DBFED," rbitfld.word 0x14 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count" line.word 0x16 "EPWM_TZSEL," abitfld.word 0x16 8.--15. "OSHTN,Trip-zone n (TZn) select" "0x00=Disable TZn as a one-shot trip source for..,0x01=Enable TZn as a one-shot trip source for.." hexmask.word.byte 0x16 1.--7. 1. "RESERVED," newline bitfld.word 0x16 0. "CBC0,Trip-zone 0 (TZ0) select" "Disable TZ0 as a CBC trip source for this ePWM..,Enable TZ0 as a CBC trip source for this ePWM.." group.word 0x28++0x15 line.word 0x00 "EPWM_TZCTL," hexmask.word 0x00 4.--15. 1. "RESERVED," bitfld.word 0x00 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWM1B" "High impedance (EPWM1B = High-impedance state),Force EPWM1B to a high state,Force EPWM1B to a low state,Do nothing no action is taken on EPWM1B" newline bitfld.word 0x00 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWM1A" "High impedance (EPWM1A = High-impedance state),Force EPWM1A to a high state,Force EPWM1A to a low state,Do nothing no action is taken on EPWM1A" line.word 0x02 "EPWM_TZEINT," hexmask.word 0x02 3.--15. 1. "RESERVED," bitfld.word 0x02 2. "OST,Trip-zone One-Shot Interrupt Enable" "Disable one-shot interrupt generation,Enable Interrupt generation; a one-shot trip.." newline bitfld.word 0x02 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disable cycle-by-cycle interrupt generation,Enable interrupt generation; a cycle-by-cycle.." rbitfld.word 0x02 0. "RESERVED," "0,1" line.word 0x04 "EPWM_TZFLG," hexmask.word 0x04 3.--15. 1. "RESERVED," bitfld.word 0x04 2. "OST,Latched Status Flag for A One-Shot Trip Event" "No one-shot trip event has occurred,Indicates a trip event has occurred on a pin.." newline bitfld.word 0x04 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "No cycle-by-cycle trip event has occurred,Indicates a trip event has occurred on a pin.." bitfld.word 0x04 0. "INT,Latched Trip Interrupt Status Flag" "Indicates no interrupt has been generated,Indicates an ePWM0_TZINT interrupt was generated.." line.word 0x06 "EPWM_TZCLR," hexmask.word 0x06 3.--15. 1. "RESERVED," bitfld.word 0x06 2. "OST,Clear Flag for One-Shot Trip (OST) Latch" "Has no effect,Clears this Trip (set) condition" newline bitfld.word 0x06 1. "CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "Has no effect,Clears this Trip (set) condition" bitfld.word 0x06 0. "INT,Global Interrupt Clear Flag" "Has no effect,Clears the trip-interrupt flag for this ePWM.." line.word 0x08 "EPWM_TZFRC," hexmask.word 0x08 3.--15. 1. "RESERVED," bitfld.word 0x08 2. "OST,Force a One-Shot Trip Event via Software" "Writing of 0 is ignored,Forces a one-shot trip event and sets" newline bitfld.word 0x08 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "Writing of 0 is ignored,Forces a cycle-by-cycle trip event and sets" rbitfld.word 0x08 0. "RESERVED," "0,1" line.word 0x0A "EPWM_ETSEL," hexmask.word 0x0A 4.--15. 1. "RESERVED," bitfld.word 0x0A 3. "INTEN,Enable ePWM Interrupt (ePWM0INT) Generation" "Disable ePWM0INT generation,Enable ePWM0INT generation" newline bitfld.word 0x0A 0.--2. "INTSEL,ePWM Interrupt (ePWM0INT) Selection Options" "Reserved,Enable event time-base counter equal to zero,Enable event time-base counter equal to period..,Reserved,Enable event time-base counter equal to CMPA..,Enable event time-base counter equal to CMPA..,Enable event,Enable event" line.word 0x0C "EPWM_ETPS," hexmask.word 0x0C 4.--15. 1. "RESERVED," bitfld.word 0x0C 2.--3. "INTCNT,ePWM Interrupt Event (ePWM0INT) Counter Register" "No events have occurred,1 event has occurred,2 events have occurred,3 events have occurred" newline bitfld.word 0x0C 0.--1. "INTPRD,ePWM Interrupt (ePWM0INT) Period Select" "Disable the interrupt event counter,Generate an interrupt on the first event INTCNT..,Generate interrupt on,Generate interrupt on" line.word 0x0E "EPWM_ETFLG," hexmask.word 0x0E 1.--15. 1. "RESERVED," bitfld.word 0x0E 0. "INT,Latched ePWM Interrupt (EPWM_INT) Status Flag" "Indicates no event occurred,Indicates that an ePWM interrupt (EWPM_INT) was.." line.word 0x10 "EPWM_ETCLR," hexmask.word 0x10 1.--15. 1. "RESERVED," bitfld.word 0x10 0. "INT,ePWM Interrupt (ePWM0INT) Flag Clear Bit" "Writing a 0 has no effect,Writing 1 clears" line.word 0x12 "EPWM_ETFRC," hexmask.word 0x12 1.--15. 1. "RESERVED," bitfld.word 0x12 0. "INT,INT Force Bit" "Writing 0 to this bit will be ignored,Writing 1 generates an interrupt on ePWM0INT and.." line.word 0x14 "EPWM_PCCTL," rbitfld.word 0x14 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x14 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "Duty = 1/8 (12.5%),Duty = 2/8 (25.0%),Duty = 3/8 (37.5%),Duty = 4/8 (50.0%),Duty = 5/8 (62.5%),Duty = 6/8 (75.0%),Duty = 7/8 (87.5%),Reserved" newline bitfld.word 0x14 5.--7. "CHPFREQ,Chopping Clock Frequency" "Divide by 1 (no prescale),Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7,Divide by 8" bitfld.word 0x14 1.--4. "OSHTWTH,One-Shot Pulse Width" "?,SYSCLKOUT/8 wide,SYSCLKOUT/8 wide,SYSCLKOUT/8 wide,SYSCLKOUT/8 wide,?..." newline bitfld.word 0x14 0. "CHPEN,PWM-chopping Enable" "Disable (bypass) PWM chopping function,Enable chopping function" group.word 0xC0++0x01 line.word 0x00 "HRPWM_HRCTL," hexmask.word 0x00 4.--15. 1. "RESERVED," bitfld.word 0x00 3. "PULSESEL,Pulse select bits" "Select CNT_zero pulse,Select PRD_eq pulse" newline bitfld.word 0x00 2. "DELBUSSEL,Delay Bus Select Bit: Selects which bus is used to select the delay for the PWM pulse" "Select CMPAHR(8) bus from compare module of EPWM..,Select TBPHSHR(8) bus from time base module" bitfld.word 0x00 0.--1. "DELMODE,Delay Mode Bits: Selects which edge of the PWM pulse the delay is inserted" "No delay inserted (default on reset),Delay inserted rising edge,Delay inserted falling edge,Delay inserted on both edges" width 0x0B tree.end tree "PWMSS_EQEP" base ad:0x4843E180 group.long 0x00++0x23 line.long 0x00 "EQEP_QPOSCNT," line.long 0x04 "EQEP_QPOSINIT," line.long 0x08 "EQEP_QPOSMAX," line.long 0x0C "EQEP_QPOSCMP," line.long 0x10 "EQEP_QPOSILAT," line.long 0x14 "EQEP_QPOSSLAT," line.long 0x18 "EQEP_QPOSLAT," line.long 0x1C "EQEP_QUTMR," line.long 0x20 "EQEP_QUPRD," group.word 0x24++0x1D line.word 0x00 "EQEP_QWDTMR," line.word 0x02 "EQEP_QWDPRD," line.word 0x04 "EQEP_QDECCTL," bitfld.word 0x04 14.--15. "QSRC,Position-counter source selection" "Quadrature count mode (QCLK = iCLK QDIR = iDIR),Direction-count mode (QCLK = xCLK QDIR = xDIR),UP count mode for frequency measurement (QCLK =..,DOWN count mode for frequency measurement (QCLK.." bitfld.word 0x04 13. "SOEN,Sync output-enable" "Disable position-compare sync output,Enable position-compare sync output" newline bitfld.word 0x04 12. "SPSEL,Sync output pin selection" "Index pin is used for sync output,Strobe pin is used for sync output" bitfld.word 0x04 11. "XCR,External clock rate" "2x resolution,1x resolution" newline bitfld.word 0x04 10. "SWAP,Swap quadrature clock inputs" "Quadrature-clock inputs are not swapped,Quadrature-clock inputs are swapped" bitfld.word 0x04 9. "IGATE,Index pulse gating option" "Disable gating of Index pulse,Gate the index pin with strobe" newline bitfld.word 0x04 8. "QAP,QEPA input polarity" "No effect,Negates QEPA input" bitfld.word 0x04 7. "QBP,QEPB input polarity" "No effect,Negates QEPB input" newline bitfld.word 0x04 6. "QIP,QEPI input polarity" "No effect,Negates QEPI input" bitfld.word 0x04 5. "QSP,QEPS input polarity" "No effect,Negates QEPS input" newline rbitfld.word 0x04 0.--4. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x06 "EQEP_QEPCTL," bitfld.word 0x06 14.--15. "FREE_SOFT,Emulation Control Bits" "x stops immediately,x continues to count until the rollover,x is unaffected by emulation suspend,x is unaffected by emulation suspend" bitfld.word 0x06 12.--13. "PCRM,Position counter reset mode" "Position counter reset on an index event,Position counter reset on the maximum position,Position counter reset on the first index event,Position counter reset on a unit time event" newline bitfld.word 0x06 10.--11. "SEI,Strobe event initialization of position counter" "Does nothing (action disabled),Does nothing (action disabled),Initializes the position counter on rising edge..,Clockwise Direction" bitfld.word 0x06 8.--9. "IEI,Index event initialization of position counter" "Do nothing (action disabled),Do nothing (action disabled),Initializes the position counter on the rising..,Initializes the position counter on the falling.." newline bitfld.word 0x06 7. "SWI,Software initialization of position counter" "Do nothing (action disabled),Initialize position counter this bit is cleared.." bitfld.word 0x06 6. "SEL,Strobe event latch of position counter" "The position counter is latched on the rising..,Clockwise Direction" newline bitfld.word 0x06 4.--5. "IEL,Index event latch of position counter (software index marker)" "Reserved,Latches position counter on rising edge of the..,Latches position counter on falling edge of the..,Software index marker" bitfld.word 0x06 3. "PHEN,Quadrature position counter enable/software reset" "Reset the eQEP peripheral internal operating..,eQEP position counter is enabled" newline bitfld.word 0x06 2. "QCLM,eQEP capture latch mode" "Latch on position counter read by CPU,Latch on unit time out" bitfld.word 0x06 1. "UTE,eQEP unit timer enable" "Disable eQEP unit timer,Enable unit timer" newline bitfld.word 0x06 0. "WDE,eQEP watchdog enable" "Disable the eQEP watchdog timer,Enable the eQEP watchdog timer" line.word 0x08 "EQEP_QCAPCTL," bitfld.word 0x08 15. "CEN,Enable eQEP capture" "eQEP capture unit is disabled,eQEP capture unit is enabled" hexmask.word.byte 0x08 7.--14. 1. "RESERVED," newline bitfld.word 0x08 4.--6. "CCPS,eQEP capture timer clock prescaler" "CAPCLK = SYSCLKOUT/1,CAPCLK = SYSCLKOUT/2,CAPCLK = SYSCLKOUT/4,CAPCLK = SYSCLKOUT/8,CAPCLK = SYSCLKOUT/16,CAPCLK = SYSCLKOUT/32,CAPCLK = SYSCLKOUT/64,CAPCLK = SYSCLKOUT/128" bitfld.word 0x08 0.--3. "UPPS,Unit position event prescaler" "UPEVNT = QCLK/1,UPEVNT = QCLK/2,UPEVNT = QCLK/4,UPEVNT = QCLK/8,UPEVNT = QCLK/16,UPEVNT = QCLK/32,UPEVNT = QCLK/64,UPEVNT = QCLK/128,UPEVNT = QCLK/256,UPEVNT = QCLK/512,UPEVNT = QCLK/1024,UPEVNT = QCLK/2048,Reserved,Reserved,Reserved,Reserved" line.word 0x0A "EQEP_QPOSCTL," bitfld.word 0x0A 15. "PCSHDW,Position-compare shadow enable" "Shadow disabled load Immediate,Shadow enabled" bitfld.word 0x0A 14. "PCLOAD,Position-compare shadow load mode" "Load on QPOSCNT = 0,Load when QPOSCNT = QPOSCMP" newline bitfld.word 0x0A 13. "PCPOL,Polarity of sync output" "Active HIGH pulse output,Active LOW pulse output" bitfld.word 0x0A 12. "PCE,Position-compare enable/disable" "Disable position compare unit,Enable position compare unit" newline abitfld.word 0x0A 0.--11. "PCSPW,Select-position-compare sync output pulse width" "0x000=1 x 4 x SYSCLKOUT cycles,0x001=2 x 4 x SYSCLKOUT cycles,0x002=3 x 4 x SYSCLKOUT cycles to 4096 x 4 x..,0xFFF=3 x 4 x SYSCLKOUT cycles to 4096 x 4 x.." line.word 0x0C "EQEP_QEINT," rbitfld.word 0x0C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0C 11. "UTO,Unit time out interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 10. "IEL,Index event latch interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 9. "SEL,Strobe event latch interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 8. "PCM,Position-compare match interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 7. "PCR,Position-compare ready interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 6. "PCO,Position counter overflow interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 5. "PCU,Position counter underflow interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 4. "WTO,Watchdog time out interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 3. "QDC,Quadrature direction change interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 2. "PHE,Quadrature phase error interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 1. "PCE,Position counter error interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline rbitfld.word 0x0C 0. "RESERVED," "0,1" line.word 0x0E "EQEP_QFLG," bitfld.word 0x0E 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0E 11. "UTO,Unit time out interrupt flag" "No interrupt generated,Set by eQEP unit timer period match" newline bitfld.word 0x0E 10. "IEL,Index event latch interrupt flag" "No interrupt generated,This bit is set after latching the QPOSCNT to.." bitfld.word 0x0E 9. "SEL,Strobe event latch interrupt flag" "No interrupt generated,This bit is set after latching the QPOSCNT to" newline bitfld.word 0x0E 8. "PCM,eQEP compare match event interrupt flag" "No interrupt generated,This bit is set on position-compare match" bitfld.word 0x0E 7. "PCR,Position-compare ready interrupt flag" "No interrupt generated,This bit is set after transferring the shadow.." newline bitfld.word 0x0E 6. "PCO,Position counter overflow interrupt flag" "No interrupt generated,This bit is set on position counter overflow" bitfld.word 0x0E 5. "PCU,Position counter underflow interrupt flag" "No interrupt generated,This bit is set on position counter underflow" newline bitfld.word 0x0E 4. "WTO,Watchdog timeout interrupt flag" "No interrupt generated,Set by watch dog timeout" bitfld.word 0x0E 3. "QDC,Quadrature direction change interrupt flag" "No interrupt generated,This bit is set during change of direction" newline bitfld.word 0x0E 2. "PHE,Quadrature phase error interrupt flag" "No interrupt generated,Set on simultaneous transition of QEPA and QEPB" bitfld.word 0x0E 1. "PCE,Position counter error interrupt flag" "No interrupt generated,Position counter error" newline bitfld.word 0x0E 0. "INT,Global interrupt status flag" "No interrupt generated,Interrupt was generated" line.word 0x10 "EQEP_QCLR," rbitfld.word 0x10 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x10 11. "UTO,Clear unit time out interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 10. "IEL,Clear index event latch interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 9. "SEL,Clear strobe event latch interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 8. "PCM,Clear eQEP compare match event interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 7. "PCR,Clear position-compare ready interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 6. "PCO,Clear position counter overflow interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 5. "PCU,Clear position counter underflow interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 4. "WTO,Clear watchdog timeout interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 3. "QDC,Clear quadrature direction change interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 2. "PHE,Clear quadrature phase error interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 1. "PCE,Clear position counter error interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 0. "INT,Global interrupt clear flag" "No effect,Clears the interrupt flag.." line.word 0x12 "EQEP_QFRC," rbitfld.word 0x12 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x12 11. "UTO,Force unit time out interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 10. "IEL,Force index event latch interrupt" "No effect,Force the interrupt" bitfld.word 0x12 9. "SEL,Force strobe event latch interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 8. "PCM,Force position-compare match interrupt" "No effect,Force the interrupt" bitfld.word 0x12 7. "PCR,Force position-compare ready interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 6. "PCO,Force position counter overflow interrupt" "No effect,Force the interrupt" bitfld.word 0x12 5. "PCU,Force position counter underflow interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 4. "WTO,Force watchdog time out interrupt" "No effect,Force the interrupt" bitfld.word 0x12 3. "QDC,Force quadrature direction change interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 2. "PHE,Force quadrature phase error interrupt" "No effect,Force the interrupt" bitfld.word 0x12 1. "PCE,Force position counter error interrupt" "No effect,Force the interrupt" newline rbitfld.word 0x12 0. "RESERVED," "0,1" line.word 0x14 "EQEP_QEPSTS," hexmask.word.byte 0x14 8.--15. 1. "RESERVED," bitfld.word 0x14 7. "UPEVNT,Unit position event flag" "No unit position event detected,Unit position event detected" newline bitfld.word 0x14 6. "FDF,Direction on the first index marker" "Counter-clockwise rotation (or reverse movement)..,Clockwise rotation (or forward movement) on the.." bitfld.word 0x14 5. "QDF,Quadrature direction flag" "Counter-clockwise rotation (or reverse movement),Clockwise rotation (or forward movement)" newline bitfld.word 0x14 4. "QDLF,eQEP direction latch flag" "Counter-clockwise rotation (or reverse movement)..,Clockwise rotation (or forward movement) on.." bitfld.word 0x14 3. "COEF,Capture overflow error flag" "Sticky bit cleared by writing 1,Overflow occurred in eQEP Capture timer (QEPCTMR)" newline bitfld.word 0x14 2. "CDEF,Capture direction error flag" "Sticky bit cleared by writing 1,Direction change occurred between the capture.." bitfld.word 0x14 1. "FIMF,First index marker flag" "Sticky bit cleared by writing 1,Set by first occurrence of index pulse" newline bitfld.word 0x14 0. "PCEF,Position counter error flag" "No error occurred during the last index transition,Position counter error" line.word 0x16 "EQEP_QCTMR," line.word 0x18 "EQEP_QCPRD," line.word 0x1A "EQEP_QCTMRLAT," line.word 0x1C "EQEP_QCPRDLAT," rgroup.long 0x5C++0x03 line.long 0x00 "EQEP_REVID," width 0x0B tree.end tree "PWMSS_TARG" base ad:0x4843F000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "QSPI" base ad:0x4B300000 rgroup.long 0x00++0x03 line.long 0x00 "QSPI_PID,Revision register" group.long 0x10++0x03 line.long 0x00 "QSPI_SYSCONFIG," hexmask.long 0x00 4.--31. 1. "RESERVED," bitfld.long 0x00 2.--3. "IDLE_MODE,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Reserved" newline rbitfld.long 0x00 0.--1. "RESERVED," "0,1,2,3" group.long 0x20++0x13 line.long 0x00 "QSPI_INTR_STATUS_RAW_SET,This register contains raw interrupt status flags" hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "WIRQ_RAW,Word Interrupt Status" "WIRQ_RAW_0,WIRQ_RAW_1" newline bitfld.long 0x00 0. "FIRQ_RAW,Frame Interrupt Status" "FIRQ_RAW_0,FIRQ_RAW_1" line.long 0x04 "QSPI_INTR_STATUS_ENABLED_CLEAR,This register contains status flags of the enabled interrupts" hexmask.long 0x04 2.--31. 1. "RESERVED," bitfld.long 0x04 1. "WIRQ_ENA,Word Interrupt Enabled Status" "WIRQ_ENA_0,WIRQ_ENA_1" newline bitfld.long 0x04 0. "FIRQ_ENA,Frame Interrupt Enabled Status" "FIRQ_ENA_0,FIRQ_ENA_1" line.long 0x08 "QSPI_INTR_ENABLE_SET_REG,This register enables the interrupts" hexmask.long 0x08 2.--31. 1. "RESERVED," bitfld.long 0x08 1. "WIRQ_ENA_SET,Word interrupt enable.Read" "WIRQ_ENA_SET_0,WIRQ_ENA_SET_1" newline bitfld.long 0x08 0. "FIRQ_ENA_SET,Frame interrupt enable.Read" "FIRQ_ENA_SET_0,FIRQ_ENA_SET_1" line.long 0x0C "QSPI_INTR_ENABLE_CLEAR_REG,This register disables the interrupts" hexmask.long 0x0C 2.--31. 1. "RESERVED," bitfld.long 0x0C 1. "WIRQ_ENA_CLR,Word interrupt disable.Read" "WIRQ_ENA_CLR_0,WIRQ_ENA_CLR_1" newline bitfld.long 0x0C 0. "FIRQ_ENA_CLR,Frame interrupt disable.Read" "FIRQ_ENA_CLR_0,FIRQ_ENA_CLR_1" line.long 0x10 "QSPI_INTC_EOI_REG,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" group.long 0x40++0x33 line.long 0x00 "QSPI_SPI_CLOCK_CNTRL_REG,This register controls the external SPI clock generation" bitfld.long 0x00 31. "CLKEN,External SPI clock (qspi1_sclk) enable" "CLKEN_0,CLKEN_1" hexmask.long.word 0x00 16.--30. 1. "RESERVED," newline hexmask.long.word 0x00 0.--15. 1. "DCLK_DIV,Divide ratio for the external SPI clock (qspi1_sclk)" line.long 0x04 "QSPI_SPI_DC_REG,This register controls the different modes for each output chip select" rbitfld.long 0x04 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. "DD3,Data delay for chip select 3" "Data is output on the same cycle as the..,Data is output 1 qspi1_sclk cycle after the..,Data is output 2 qspi1_sclk cycles after the..,Data is output 3 qspi1_sclk cycles after the.." newline bitfld.long 0x04 26. "CKPH3,Clock phase for chip select 3" "Data shifted out on rising edge; input on,Data shifted out on falling edge; input on" bitfld.long 0x04 25. "CSP3,Chip select polarity for chip select 3" "CSP3_0,CSP3_1" newline bitfld.long 0x04 24. "CKP3,Clock polarity for chip select 3" "CKP3_0,CKP3_1" rbitfld.long 0x04 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 19.--20. "DD2,Data delay for chip select 2" "Data is output on the same cycle as the..,Data is output 1 qspi1_sclk cycle after the..,Data is output 2 qspi1_sclk cycles after the..,Data is output 3 qspi1_sclk cycles after the.." bitfld.long 0x04 18. "CKPH2,Clock phase for chip select 2" "Data shifted out on rising edge; input on,Data shifted out on falling edge; input on" newline bitfld.long 0x04 17. "CSP2,Chip select polarity for chip select 2" "CSP2_0,CSP2_1" bitfld.long 0x04 16. "CKP2,Clock polarity for chip select 2" "CKP2_0,CKP2_1" newline rbitfld.long 0x04 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 11.--12. "DD1,Data delay for chip select 1" "Data is output on the same cycle as the..,Data is output 1 qspi1_sclk cycle after the..,Data is output 2 qspi1_sclk cycles after the..,Data is output 3 qspi1_sclk cycles after the.." newline bitfld.long 0x04 10. "CKPH1,Clock phase for chip select 1" "Data shifted out on rising edge; input on,Data shifted out on falling edge; input on" bitfld.long 0x04 9. "CSP1,Chip select polarity for chip select 1" "CSP1_0,CSP1_1" newline bitfld.long 0x04 8. "CKP1,Clock polarity for chip select 1" "CKP1_0,CKP1_1" rbitfld.long 0x04 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 3.--4. "DD0,Data delay for chip select 0" "Data is output on the same cycle as the..,Data is output 1 qspi1_sclk cycle after the..,Data is output 2 qspi1_sclk cycles after the..,Data is output 3 qspi1_sclk cycles after the.." bitfld.long 0x04 2. "CKPH0,Clock phase for chip select 0" "Data shifted out on rising edge; input on,Data shifted out on falling edge; input on" newline bitfld.long 0x04 1. "CSP0,Chip select polarity for chip select 0" "CSP0_0,CSP0_1" bitfld.long 0x04 0. "CKP0,Clock polarity for chip select 0" "CKP0_0,CKP0_1" line.long 0x08 "QSPI_SPI_CMD_REG,This register sets up the SPI command" rbitfld.long 0x08 30.--31. "RESERVED," "0,1,2,3" bitfld.long 0x08 28.--29. "CSNUM,Device select" "Chip Select 0 active,Chip Select 1 active,Chip Select 2 active,Chip Select 3 active" newline rbitfld.long 0x08 26.--27. "RESERVED," "0,1,2,3" abitfld.long 0x08 19.--25. "WLEN,Word length" "0x00=1 bit,0x01=2 bits,0x7F=128 bits" newline bitfld.long 0x08 16.--18. "CMD,Transfer command" "Reserved,4-pin Read Single,4-pin Write Single,4-pin Read Dual,Reserved,3-pin Read Single,3-pin Write Single,6-pin Read Quad" bitfld.long 0x08 15. "FIRQ,Frame complete interrupt enable" "FIRQ_0,FIRQ_1" newline bitfld.long 0x08 14. "WIRQ,Word complete interrupt enable" "WIRQ_0,WIRQ_1" rbitfld.long 0x08 12.--13. "RESERVED," "0,1,2,3" newline abitfld.long 0x08 0.--11. "FLEN,Frame Length" "0x000=1 word,0x001=2 words,0xFFF=4096 words" line.long 0x0C "QSPI_SPI_STATUS_REG,This register contains indicators to allow the user to monitor the progression of a frame transfer" bitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0C 16.--27. 1. "WDCNT,Word count" newline hexmask.long.word 0x0C 3.--15. 1. "RESERVED," bitfld.long 0x0C 2. "FC,Frame complete" "FC_0,FC_1" newline bitfld.long 0x0C 1. "WC,Word complete" "WC_0,WC_1" bitfld.long 0x0C 0. "BUSY,Busy bit" "BUSY_0,BUSY_1" line.long 0x10 "QSPI_SPI_DATA_REG,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left" line.long 0x14 "QSPI_SPI_SETUP0_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 0 output)" rbitfld.long 0x14 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.byte 0x14 16.--23. 1. "WCMD,Write command" rbitfld.long 0x14 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x14 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command" "Normal read (all data input on qspi1_d[1]),Dual read (odd bytes input on qspi1_d[1]; even..,Normal read (all data input on qspi1_d[1]),Quad read (uses also qspi1_d[2] and qspi1_d[3])" bitfld.long 0x14 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "No dummy bytes required,Use 8 bits,Use 16 bits,Use 24 bits" newline bitfld.long 0x14 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x14 0.--7. 1. "RCMD,Read Command" line.long 0x18 "QSPI_SPI_SETUP1_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 1 output)" rbitfld.long 0x18 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.byte 0x18 16.--23. 1. "WCMD,Write command" rbitfld.long 0x18 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x18 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command" "Normal read (all data input on qspi1_d[1]),Dual read (odd bytes input on qspi1_d[1]; even..,Normal read (all data input on qspi1_d[1]),Quad read (uses also qspi1_d[2] and qspi1_d[3])" bitfld.long 0x18 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "No dummy bytes required,Use 8 bits,Use 16 bits,Use 24 bits" newline bitfld.long 0x18 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x18 0.--7. 1. "RCMD,Read Command" line.long 0x1C "QSPI_SPI_SETUP2_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 2 output)" rbitfld.long 0x1C 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.byte 0x1C 16.--23. 1. "WCMD,Write command" rbitfld.long 0x1C 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x1C 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command" "Normal read (all data input on qspi1_d[1]),Dual read (odd bytes input on qspi1_d[1]; even..,Normal read (all data input on qspi1_d[1]),Quad read (uses also qspi1_d[2] and qspi1_d[3])" bitfld.long 0x1C 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "No dummy bytes required,Use 8 bits,Use 16 bits,Use 24 bits" newline bitfld.long 0x1C 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x1C 0.--7. 1. "RCMD,Read Command" line.long 0x20 "QSPI_SPI_SETUP3_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 3 output)" rbitfld.long 0x20 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x20 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.byte 0x20 16.--23. 1. "WCMD,Write command" rbitfld.long 0x20 14.--15. "RESERVED," "0,1,2,3" newline bitfld.long 0x20 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command" "Normal read (all data input on qspi1_d[1]),Dual read (odd bytes input on qspi1_d[1]; even..,Normal read (all data input on qspi1_d[1]),Quad read (uses also qspi1_d[2] and qspi1_d[3])" bitfld.long 0x20 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "No dummy bytes required,Use 8 bits,Use 16 bits,Use 24 bits" newline bitfld.long 0x20 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x20 0.--7. 1. "RCMD,Read Command" line.long 0x24 "QSPI_SPI_SWITCH_REG,This register allows initiators to switch control of the SPI core port between the configuration port and the SFI translator" hexmask.long 0x24 2.--31. 1. "RESERVED," bitfld.long 0x24 1. "MM_INT_EN,Memory mapped mode interrupt enable" "MM_INT_EN_0,MM_INT_EN_1" newline bitfld.long 0x24 0. "MMPT_S,MPT select" "MMPT_S_0,MMPT_S_1" line.long 0x28 "QSPI_SPI_DATA_REG_1,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left" line.long 0x2C "QSPI_SPI_DATA_REG_2,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left" line.long 0x30 "QSPI_SPI_DATA_REG_3,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left" width 0x0B tree.end tree "QSPI_FW" base ad:0x4A179000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" newline rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "QSPI_FW_CFG_TARG" base ad:0x4A17A000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "QSPI_TARG" base ad:0x44003900 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "RESTORE_CM_CORE" base ad:0x4A009E18 group.long 0x00++0x03 line.long 0x00 "CM_L3MAIN1_CLKSTCTRL_RESTORE,Second address map for register" group.long 0x08++0x03 line.long 0x00 "CM_L4CFG_CLKSTCTRL_RESTORE,Second address map for register" group.long 0x10++0x17 line.long 0x00 "CM_L4PER_CLKSTCTRL_RESTORE,Second address map for register" line.long 0x04 "CM_L3INIT_CLKSTCTRL_RESTORE,Second address map for register" line.long 0x08 "CM_L3INSTR_L3_MAIN_2_CLKCTRL_RESTORE,Second address map for register" line.long 0x0C "CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,Second address map for register" line.long 0x10 "CM_L3INSTR_OCP_WP_NOC_CLKCTRL_RESTORE,Second address map for register" line.long 0x14 "CM_CM_CORE_PROFILING_CLKCTRL_RESTORE,Second address map for register" group.long 0x30++0x03 line.long 0x00 "CM_L3MAIN1_DYNAMICDEP_RESTORE,Second address map for register" group.long 0x40++0x0B line.long 0x00 "CM_L4CFG_DYNAMICDEP_RESTORE,Second address map for register" line.long 0x04 "CM_L4PER_DYNAMICDEP_RESTORE,Second address map for register" line.long 0x08 "CM_COREAON_IO_SRCOMP_CLKCTRL_RESTORE,Second address map for register CM_COREAON_IO_SRCOMP_CLKCTRL" group.long 0x54++0x03 line.long 0x00 "CM_DMA_STATICDEP_RESTORE,Second address map for register CM_DMA_STATICDEP" width 0x0B tree.end tree "RESTORE_CM_CORE_AON" base ad:0x4A005E00 group.long 0x00++0x53 line.long 0x00 "CM_CLKSEL_CORE_RESTORE,Second address map for register" line.long 0x04 "CM_DIV_M2_DPLL_CORE_RESTORE,Second address map for register" line.long 0x08 "CM_DIV_M3_DPLL_CORE_RESTORE,Second address map for register CM_DIV_M3_DPLL_CORE" line.long 0x0C "CM_DIV_H11_DPLL_CORE_RESTORE,Second address map for register CM_DIV_H11_DPLL_CORE" line.long 0x10 "CM_DIV_H12_DPLL_CORE_RESTORE,Second address map for register" line.long 0x14 "CM_DIV_H13_DPLL_CORE_RESTORE,Second address map for register CM_DIV_H13_DPLL_CORE" line.long 0x18 "CM_DIV_H14_DPLL_CORE_RESTORE,Second address map for register" line.long 0x1C "CM_DIV_H21_DPLL_CORE_RESTORE,Second address map for register CM_DIV_H21_DPLL_CORE" line.long 0x20 "CM_DIV_H22_DPLL_CORE_RESTORE,Second address map for register" line.long 0x24 "CM_DIV_H23_DPLL_CORE_RESTORE,Second address map for register" line.long 0x28 "CM_DIV_H24_DPLL_CORE_RESTORE,Second address map for register" line.long 0x2C "CM_CLKSEL_DPLL_CORE_RESTORE,Second address map for register" line.long 0x30 "CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE,Second address map for register CM_SSC_DELTAMSTEP_DPLL_CORE" line.long 0x34 "CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,Second address map for register CM_SSC_MODFREQDIV_DPLL_CORE" line.long 0x38 "CM_CLKMODE_DPLL_CORE_RESTORE,Second address map for register" line.long 0x3C "CM_SHADOW_FREQ_CONFIG2_RESTORE,Second address map for register" line.long 0x40 "CM_SHADOW_FREQ_CONFIG1_RESTORE,Second address map for register" line.long 0x44 "CM_AUTOIDLE_DPLL_CORE_RESTORE,Second address map for register" line.long 0x48 "CM_MPU_CLKSTCTRL_RESTORE,Second address map for register CM_MPU_CLKSTCTRL" line.long 0x4C "CM_CM_CORE_AON_PROFILING_CLKCTRL_RESTORE,Second address map for register" line.long 0x50 "CM_DYN_DEP_PRESCAL_RESTORE,Second address map for register" width 0x0B tree.end tree "RTC_CM_CORE_AON" base ad:0x4A005740 group.long 0x00++0x07 line.long 0x00 "CM_RTC_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED," rbitfld.long 0x00 10. "CLKACTIVITY_RTC_AUX_CLK,This field indicates the state of the RTC_AUX_CLK in the domain" "CLKACTIVITY_RTC_AUX_CLK_0,CLKACTIVITY_RTC_AUX_CLK_1" newline rbitfld.long 0x00 9. "RESERVED," "0,1" rbitfld.long 0x00 8. "CLKACTIVITY_RTC_L4_GICLK,This field indicates the state of the RTC_L4_GICLK clock in the domain" "CLKACTIVITY_RTC_L4_GICLK_0,CLKACTIVITY_RTC_L4_GICLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the WKUPAON clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_RTC_RTCSS_CLKCTRL,This register manages the RTC clocks" hexmask.long.word 0x04 18.--31. 1. "RESERVED," rbitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x04 2.--15. 1. "RESERVED," bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "RTC_PRM" base ad:0x4AE07C60 group.long 0x00++0x07 line.long 0x00 "PM_RTC_RTCSS_WKDEP,This register controls wakeup dependency based on RTCSS service requests" hexmask.long.word 0x00 20.--31. 1. "RESERVED," bitfld.long 0x00 19. "WKUPDEP_RTC_IRQ2_EVE4,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_EVE4_0,WKUPDEP_RTC_IRQ2_EVE4_1" newline bitfld.long 0x00 18. "WKUPDEP_RTC_IRQ2_EVE3,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_EVE3_0,WKUPDEP_RTC_IRQ2_EVE3_1" bitfld.long 0x00 17. "WKUPDEP_RTC_IRQ2_EVE2,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_EVE2_0,WKUPDEP_RTC_IRQ2_EVE2_1" newline bitfld.long 0x00 16. "WKUPDEP_RTC_IRQ2_EVE1,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_EVE1_0,WKUPDEP_RTC_IRQ2_EVE1_1" bitfld.long 0x00 15. "WKUPDEP_RTC_IRQ2_DSP2,Wakeup dependency from RTCSS module (timer_swakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_DSP2_0,WKUPDEP_RTC_IRQ2_DSP2_1" newline bitfld.long 0x00 14. "WKUPDEP_RTC_IRQ2_IPU1,Wakeup dependency from RTCSS module (timer_swakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_IPU1_0,WKUPDEP_RTC_IRQ2_IPU1_1" rbitfld.long 0x00 13. "RESERVED," "0,1" newline bitfld.long 0x00 12. "WKUPDEP_RTC_IRQ2_DSP1,Wakeup dependency from RTCSS module (timer_swakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_DSP1_0,WKUPDEP_RTC_IRQ2_DSP1_1" bitfld.long 0x00 11. "WKUPDEP_RTC_IRQ2_IPU2,Wakeup dependency from RTCSS module (timer_swakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_IPU2_0,WKUPDEP_RTC_IRQ2_IPU2_1" newline bitfld.long 0x00 10. "WKUPDEP_RTC_IRQ2_MPU,Wakeup dependency from RTCSS module (timer_swakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ2_MPU_0,WKUPDEP_RTC_IRQ2_MPU_1" bitfld.long 0x00 9. "WKUPDEP_RTC_IRQ1_EVE4,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_EVE4_0,WKUPDEP_RTC_IRQ1_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_RTC_IRQ1_EVE3,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_EVE3_0,WKUPDEP_RTC_IRQ1_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_RTC_IRQ1_EVE2,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_EVE2_0,WKUPDEP_RTC_IRQ1_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_RTC_IRQ1_EVE1,Wakeup dependency from RTCSS module ( alarm_swakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_EVE1_0,WKUPDEP_RTC_IRQ1_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_RTC_IRQ1_DSP2,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_DSP2_0,WKUPDEP_RTC_IRQ1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_RTC_IRQ1_IPU1,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_IPU1_0,WKUPDEP_RTC_IRQ1_IPU1_1" rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_RTC_IRQ1_DSP1,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_DSP1_0,WKUPDEP_RTC_IRQ1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_RTC_IRQ1_IPU2,Wakeup dependency from RTCSS module ( alarm_swakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_IPU2_0,WKUPDEP_RTC_IRQ1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_RTC_IRQ1_MPU,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_RTC_IRQ1_MPU_0,WKUPDEP_RTC_IRQ1_MPU_1" line.long 0x04 "RM_RTC_RTCSS_CONTEXT,This register contains dedicated RTCSS context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end repeat 5. (list 1. 2. 3. 4. 5. )(list ad:0x4AE31000 ad:0x4AE33000 ad:0x4AE35000 ad:0x4AE37000 ad:0x4AE39000 ) tree "RTI$1" base $2 group.long 0x00++0x03 line.long 0x00 "RTIGCTRL," hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 16.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. "COS,Continue On Suspend" "stop counters in debug mode,continue counting in debug mode" hexmask.long.word 0x00 2.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "CNT1EN,Counter 1 Enable" "stop counters,start counters" bitfld.long 0x00 0. "CNT0EN,Counter 0 Enable" "stop counters,start counters" group.long 0x08++0x13 line.long 0x00 "RTICAPCTRL," hexmask.long 0x00 2.--31. 1. "RESERVED," bitfld.long 0x00 1. "CAPCNTR1,Capture Counter 0" "0,1" newline bitfld.long 0x00 0. "CAPCNTR0,Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.." line.long 0x04 "RTICOMPCTRL," hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED," bitfld.long 0x04 12. "COMPSEL3,Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1" newline rbitfld.long 0x04 9.--11. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 8. "COMPSEL2,Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1" newline rbitfld.long 0x04 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 4. "COMPSEL1,Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1" newline rbitfld.long 0x04 1.--3. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. "COMPSEL0,Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1" line.long 0x08 "RTIFRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously" line.long 0x0C "RTIUC0," line.long 0x10 "RTICPUC0," rgroup.long 0x20++0x07 line.long 0x00 "RTICAFRC0," line.long 0x04 "RTICAUC0," group.long 0x30++0x0B line.long 0x00 "RTIFRC1," line.long 0x04 "RTIUC1," line.long 0x08 "RTICPUC1," rgroup.long 0x40++0x07 line.long 0x00 "RTICAFRC1," line.long 0x04 "RTICAUC1," group.long 0x50++0x1F line.long 0x00 "RTICOMP0," line.long 0x04 "RTIUDCP0," line.long 0x08 "RTICOMP1," line.long 0x0C "RTIUDCP1," line.long 0x10 "RTICOMP2," line.long 0x14 "RTIUDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches" line.long 0x18 "RTICOMP3," line.long 0x1C "RTIUDCP3," group.long 0x80++0x0B line.long 0x00 "RTISETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled" hexmask.long.word 0x00 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt" newline bitfld.long 0x00 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt" bitfld.long 0x00 16. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x00 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. "SETDMA3,Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request" newline bitfld.long 0x00 10. "SETDMA2,Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request" bitfld.long 0x00 9. "SETDMA1,Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request" newline bitfld.long 0x00 8. "SETDMA0,Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request" rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. "SETINT3,Set Compare Interrupt 3" "leaves the corresponding bit unchanged,enable interrupt" bitfld.long 0x00 2. "SETINT2,Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt" newline bitfld.long 0x00 1. "SETINT1,Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt" bitfld.long 0x00 0. "SETINT0,Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt" line.long 0x04 "RTICLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled" hexmask.long.word 0x04 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt" newline bitfld.long 0x04 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt" bitfld.long 0x04 16. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 12.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 11. "CLEARDMA3,Clear Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request" newline bitfld.long 0x04 10. "CLEARDMA2,Clear Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request" bitfld.long 0x04 9. "CLEARDMA1,Clear Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request" newline bitfld.long 0x04 8. "CLEARDMA0,Clear Compare DMA Request 0" "0,1" rbitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 3. "CLEARINT3,Clear Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt" bitfld.long 0x04 2. "CLEARINT2,Clear Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt" newline bitfld.long 0x04 1. "CLEARINT1,Clear Compare Interrupt 1" "0,1" bitfld.long 0x04 0. "CLEARINT0,Clear Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt" line.long 0x08 "RTIINTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not" hexmask.long.word 0x08 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0" newline bitfld.long 0x08 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0" bitfld.long 0x08 16. "RESERVED,Reserved" "0,1" newline hexmask.long.word 0x08 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x08 3. "INT3,Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0" newline bitfld.long 0x08 2. "INT2,Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0" bitfld.long 0x08 1. "INT1,Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0" newline bitfld.long 0x08 0. "INT0,Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0" group.long 0x90++0x17 line.long 0x00 "RTIDWDCTRL,This register s functionality is dependent on whether the DWD is implemented to be always enabled or not" hexmask.long.word 0x00 16.--31. 1. "DWDCTRL_31_16,Digital Watchdog Control" hexmask.long.word 0x00 0.--15. 1. "DWDCTRL_15_0,Digital Watchdog Control" line.long 0x04 "RTIDWDPRLD," hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED," hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value" line.long 0x08 "RTIWDSTATUS,The values of the following status bits will not be affected by a system reset" hexmask.long 0x08 6.--31. 1. "RESERVED," bitfld.long 0x08 5. "DWWD_ST,Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0" newline bitfld.long 0x08 4. "END_TIME_VIOL,Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0" bitfld.long 0x08 3. "START_TIME_VIOL,Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0" newline bitfld.long 0x08 2. "KEYST,Watchdog KeyStatus" "0,1" bitfld.long 0x08 1. "DWDST,Digital Watchdog Status" "0,1" newline bitfld.long 0x08 0. "AWDST,Analog Watchdog Status" "0,1" line.long 0x0C "RTIWDKEY," hexmask.long.word 0x0C 16.--31. 1. "RESERVED," hexmask.long.word 0x0C 0.--15. 1. "WDKEY,Watchdog Key" line.long 0x10 "RTIDWDCNTR," hexmask.long.byte 0x10 25.--31. 1. "RESERVED," hexmask.long.word 0x10 16.--24. 1. "DWDCNTR_24_16,Digital Watchdog Down Counter" newline hexmask.long.word 0x10 0.--15. 1. "DWDCNTR_15_0,Digital Watchdog Down Counter" line.long 0x14 "RTIWWDRXNCTRL," hexmask.long 0x14 4.--31. 1. "RESERVED," bitfld.long 0x14 0.--3. "WWDRXN,Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..." group.word 0xA8++0x01 line.word 0x00 "RTIWWDSIZECTRL," group.long 0xAC++0x13 line.long 0x00 "RTIINTCLRENABLE," rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 20.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "RTICOMP0CLR," line.long 0x08 "RTICOMP1CLR," line.long 0x0C "RTICOMP2CLR," line.long 0x10 "RTICOMP3CLR," width 0x0B tree.end repeat.end tree "RTI1_TARG" base ad:0x4AE32000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "RTI2_TARG" base ad:0x4AE34000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "RTI3_TARG" base ad:0x4AE36000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "RTI4_TARG" base ad:0x4AE38000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "RTI5_TARG" base ad:0x4AE3A000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end repeat 2. (list 1. 2. )(list ad:0x48484D80 ad:0x48484DC0 ) tree "SL$1" base $2 rgroup.long 0x00++0x2B line.long 0x00 "SL_IDVER,CPGMAC_SL revision register" line.long 0x04 "SL_MACCONTROL,CPGMAC_SL MAC control register" hexmask.long.byte 0x04 25.--31. 1. "RESERVED," bitfld.long 0x04 24. "RX_CMF_EN,RX Copy MAC Control Frames Enable - Enables MAC control frames to be transferred to memory" "MAC control frames are filtered (but acted upon..,MAC control frames are transferred to memory" newline bitfld.long 0x04 23. "RX_CSF_EN,RX Copy Short Frames Enable - Enables frames or fragments shorter than 64 bytes to be copied to memory" "Short frames are filtered,Short frames are transferred to memory" bitfld.long 0x04 22. "RX_CEF_EN,RX Copy Error Frames Enable - Enables frames containing errors to be transferred to memory" "Frames containing errors are filtered,Frames containing errors are transferred to memory" newline bitfld.long 0x04 21. "TX_SHORT_GAP_LIM_EN,Transmit Short Gap Limit Enable When set this bit limits the number of short gap packets transmitted to 100ppm" "0,1" rbitfld.long 0x04 19.--20. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 18. "EXT_EN,Control Enable - Enables the fullduplex and gigabit mode to be selected from the FULLDUPLEX_IN and GIG_IN input signals and not from the FULLDUPLEX and GIG bits in this register" "Use this setting for RMII/GMII mode,Use this setting for RGMII mode" bitfld.long 0x04 17. "GIG_FORCE,Gigabit Mode Force - This bit is used to force the CPGMAC_SL into gigabit mode if the input GMII_MTCLK has been stopped by the PHY" "0,1" newline bitfld.long 0x04 16. "IFCTL_B,Interface Control B (NOT FUNCTIONAL)" "0,1" bitfld.long 0x04 15. "IFCTL_A,Interface Control A" "0,1" newline rbitfld.long 0x04 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x04 11. "CMD_IDLE,Command Idle" "Idle not commanded,Idle Commanded (read IDLE in SL_MACSTATUS)" newline bitfld.long 0x04 10. "TX_SHORT_GAP_EN,Transmit Short Gap Enable" "Transmit with a short IPG is disabled,Transmit with a short IPG (when TX_SHORT_GAP.." rbitfld.long 0x04 8.--9. "RESERVED," "0,1,2,3" newline bitfld.long 0x04 7. "GIG,Gigabit Mode" "0,1" bitfld.long 0x04 6. "TX_PACE,Transmit Pacing Enable" "Transmit Pacing Disabled,Transmit Pacing Enabled" newline bitfld.long 0x04 5. "GMII_EN,GMII Enable" "GMII RX and TX held in reset,GMII RX and TX released from reset" bitfld.long 0x04 4. "TX_FLOW_EN,Transmit Flow Control Enable - Determines if incoming pause frames are acted upon in full-duplex mode" "Transmit Flow Control Disabled,Transmit Flow Control Enabled" newline bitfld.long 0x04 3. "RX_FLOW_EN,Receive Flow Control Enable" "Receive Flow Control Disabled Half-duplex mode -..,Receive Flow Control Enabled Half-duplex mode -.." bitfld.long 0x04 2. "MTEST,Manufacturing Test mode - This bit must be set to allow writes to theSL_BOFFTEST and SL_RX_PAUSE/SL_TX_PAUSE registers" "0,1" newline bitfld.long 0x04 1. "LOOPBACK,Loop Back Mode - Loopback mode forces internal fullduplex mode regardless of whether the FULLDUPLEX bit is set or not" "Not looped back,Loop Back Mode enabled" bitfld.long 0x04 0. "FULLDUPLEX,Full Duplex mode - Gigabit mode forces fullduplex mode regardless of whether the FULLDUPLEX bit is set or not" "half duplex mode,full duplex mode" line.long 0x08 "SL_MACSTATUS,CPGMAC_SL MAC status register" bitfld.long 0x08 31. "IDLE,CPGMAC_SL IDLE - The CPGMAC_SL is in the idle state (valid after an idle command)" "The CPGMAC_SL is not in the idle state,The CPGMAC_SL is in the idle state" hexmask.long 0x08 5.--30. 1. "RESERVED," newline bitfld.long 0x08 4. "EXT_GIG,External GIG - This is the value of the EXT_GIG input bit" "0,1" bitfld.long 0x08 3. "EXT_FULLDUPLEX,External Fullduplex - This is the value of the EXT_FULLDUPLEX input bit" "0,1" newline bitfld.long 0x08 2. "RESERVED," "0,1" bitfld.long 0x08 1. "RX_FLOW_ACT,Receive Flow Control Active - When asserted indicates that receive flow control is enabled and triggered" "0,1" newline bitfld.long 0x08 0. "TX_FLOW_ACT,Transmit Flow Control Active - When asserted this bit indicates that the pause time period is being observed for a received pause frame" "0,1" line.long 0x0C "SL_SOFT_RESET,CPGMAC_SL soft reset register" hexmask.long 0x0C 1.--31. 1. "RESERVED," bitfld.long 0x0C 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the CPGMAC_SL logic to be reset" "0,1" line.long 0x10 "SL_RX_MAXLEN,CPGMAC_SL RX Maximum length register" hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED," hexmask.long.word 0x10 0.--13. 1. "RX_MAXLEN,RX Maximum Frame Length - This field determines the maximum length of a received frame" line.long 0x14 "SL_BOFFTEST,CPGMAC_SL backoff test register" rbitfld.long 0x14 31. "RESERVED," "0,1" bitfld.long 0x14 26.--30. "PACEVAL,Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x14 16.--25. 1. "RNDNUM,Backoff Random Number Generator - This field allows the Backoff Random Number Generator to be read (or written in test mode only)" rbitfld.long 0x14 12.--15. "COLL_COUNT,Collision Count - The number of collisions the current frame has experienced" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x14 10.--11. "RESERVED," "0,1,2,3" hexmask.long.word 0x14 0.--9. 1. "TX_BACKOFF,Backoff Count - This field allows the current value of the backoff counter to be observed for test purposes" line.long 0x18 "SL_RX_PAUSE,CPGMAC_SL receive pause timer register" hexmask.long.word 0x18 16.--31. 1. "RESERVED," hexmask.long.word 0x18 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value - This field allows the contents of the receive pause timer to be observed (and written in test mode)" line.long 0x1C "SL_TX_PAUSE,CPGMAC_SL transmit pause timer register" hexmask.long.word 0x1C 16.--31. 1. "RESERVED," hexmask.long.word 0x1C 0.--15. 1. "TX_PAUSETIMER,TX Pause Timer Value - This field allows the contents of the transmit pause timer to be observed (and written in test mode)" line.long 0x20 "SL_EMCONTROL,CPGMAC_SL emulation control register" hexmask.long 0x20 2.--31. 1. "RESERVED," bitfld.long 0x20 1. "SOFT,Emulation Soft Bit" "0,1" newline bitfld.long 0x20 0. "FREE,Emulation Free Bit" "0,1" line.long 0x24 "SL_RX_PRI_MAP,CPGMAC_SL RX packet priority to header priority mapping register" rbitfld.long 0x24 31. "RESERVED," "0,1" bitfld.long 0x24 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 27. "RESERVED," "0,1" bitfld.long 0x24 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 23. "RESERVED," "0,1" bitfld.long 0x24 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 19. "RESERVED," "0,1" bitfld.long 0x24 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 15. "RESERVED," "0,1" bitfld.long 0x24 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 11. "RESERVED," "0,1" bitfld.long 0x24 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 7. "RESERVED," "0,1" bitfld.long 0x24 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 3. "RESERVED," "0,1" bitfld.long 0x24 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x28 "SL_TX_GAP,Transmit inter-packet gap register" hexmask.long.tbyte 0x28 9.--31. 1. "RESERVED," hexmask.long.word 0x28 0.--8. 1. "TX_GAP,Transmit Inter-Packet Gap" width 0x0B tree.end repeat.end tree "SMARTREFLEX_CORE" base ad:0x4A0DD000 group.long 0x00++0x3B line.long 0x00 "SRCONFIG,Configuration bits for the Sensor Core and the Digital Processing" hexmask.long.word 0x00 22.--31. 1. "ACCUMDATA,Number of values to accumulate" hexmask.long.word 0x00 12.--21. 1. "SRCLKLENGTH,Determines the frequency of SRClk" newline bitfld.long 0x00 11. "SRENABLE," "0,1" bitfld.long 0x00 10. "SENENABLE," "0,1" newline bitfld.long 0x00 9. "ERRORGENERATORENABLE," "0,1" bitfld.long 0x00 8. "MINMAXAVGENABLE," "0,1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1. "SENNENABLE," "0,1" newline bitfld.long 0x00 0. "SENPENABLE," "0,1" line.long 0x04 "SRSTATUS,Status bits that indicate that the values in the register are valid or events have occurred" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "AVGERRVALID," "0,1" newline bitfld.long 0x04 2. "MINMAXAVGVALID," "0,1" bitfld.long 0x04 1. "ERRORGENERATORVALID," "0,1" newline bitfld.long 0x04 0. "MINMAXAVGACCUMVALID," "0,1" line.long 0x08 "SENVAL,The current sensor values from the Sensor Core(SVT)" hexmask.long.word 0x08 16.--31. 1. "SENPVAL,The latest value of the SenPVal from the SVT sensor core" hexmask.long.word 0x08 0.--15. 1. "SENNVAL,The latest value of the SenNVal from the SVT sensor core" line.long 0x0C "SENMIN,The minimum sensor values(SVT)" hexmask.long.word 0x0C 16.--31. 1. "SENPMIN,The minimum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x0C 0.--15. 1. "SENNMIN,The minimum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x10 "SENMAX,The maximum sensor values(SVT)" hexmask.long.word 0x10 16.--31. 1. "SENPMAX,The maximum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x10 0.--15. 1. "SENNMAX,The maximum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x14 "SENAVG,The average sensor values(SVT)" hexmask.long.word 0x14 16.--31. 1. "SENPAVG,The running average of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x14 0.--15. 1. "SENNAVG,The running average of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x18 "AVGWEIGHT,The weighting factor in the average computation" hexmask.long.word 0x18 16.--31. 1. "SENPAVGWEIGHT1,The weighting factor for the SenP averager" hexmask.long.word 0x18 0.--15. 1. "SENNAVGWEIGHT,The weighting factor for the SenN averager" line.long 0x1C "NVALUERECIPROCAL,The reciprocal of the SenN and SenP values used in error generation(SVT)" hexmask.long.byte 0x1C 24.--31. 1. "RESERVED," bitfld.long 0x1C 20.--23. "SENPGAIN,The gain value for the SVT SenP reciprocal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 16.--19. "SENNGAIN,The gain value for the SVT SenN reciprocal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x1C 8.--15. 1. "SENPRN,The scale value for the SVT SenP reciprocal" newline hexmask.long.byte 0x1C 0.--7. 1. "SENNRN,The scale value for the SVT SenN reciprocal" line.long 0x20 "IRQ_EOI,EOI protocol re-trigger" hexmask.long 0x20 1.--31. 1. "RESERVED," bitfld.long 0x20 0. "EOI,The value read is always '0' Write" "re-evaluate pending sources re-send intr*,No change to interrupt" line.long 0x24 "IRQSTATUS_RAW,MCU raw interrupt raw status and set" hexmask.long 0x24 4.--31. 1. "RESERVED," bitfld.long 0x24 3. "MCUACCUMINTSTATRAW,Read:Accum interrupt status Write" "Accum interrupt status is unchanged,Accum interrupt status is set" newline bitfld.long 0x24 2. "MCUVALIDINTSTATRAW,Read:Valid interrupt status Write" "Valid status is unchanged,Valid status is set" bitfld.long 0x24 1. "MCUBOUNDSINTSTATRAW,Read:Bounds interrupt status Write" "Bounds interrupt status is unchanged,Bounds interrupt status is set" newline bitfld.long 0x24 0. "MCUDISABLEACKINTSTATRAW,Read:MCUDisable acknowledge interrupt status Write" "MCUDisable acknowledge status is unchanged,MCUDisable acknowledge status is set" line.long 0x28 "IRQSTATUS,MCU masked interrupt status and clear" hexmask.long 0x28 4.--31. 1. "RESERVED," bitfld.long 0x28 3. "MCUACCUMINTSTATENA,Read:Accum interrupt status if enabled Write" "Accum interrupt status is unchanged,Accum interrupt status is cleared" newline bitfld.long 0x28 2. "MCUVALIDINTSTATENA,Read:Valid interrupt status if enabled Write" "Valid interrupt status is unchanged,Valid interrupt status is cleared" bitfld.long 0x28 1. "MCUBOUNDSINTSTATENA,Read:Bounds interrupt status if enabled Write" "Bounds interrupt status is unchanged,Bounds interrupt status is cleared" newline bitfld.long 0x28 0. "MCUDISABLEACKINTSTATENA,Read:MCUDisable acknowledge interrupt status if enabled Write" "MCUDisable acknowledge status is unchanged,MCUDisable acknowledge status is cleared" line.long 0x2C "IRQENABLE_SET,MCU interrupt enable flag set" hexmask.long 0x2C 4.--31. 1. "RESERVED," bitfld.long 0x2C 3. "MCUACCUMINTENASET,Read" "No change to Accum interrupt enable,Enable Accum interrupt generation" newline bitfld.long 0x2C 2. "MCUVALIDINTENASET,Read" "No change to Valid interrupt enable,Enable Valid interrupt generation" bitfld.long 0x2C 1. "MCUBOUNDSINTENASET,Read" "No change to Bounds interrupt enable,Enable Bounds interrupt generation" newline bitfld.long 0x2C 0. "MCUDISABLEACKINTENASET,Read" "No change to MCUDisAck interrupt enable,Enable MCUDisableAck interrupt generation" line.long 0x30 "IRQENABLE_CLR,MCU interrupt enable flag clear" hexmask.long 0x30 4.--31. 1. "RESERVED," bitfld.long 0x30 3. "MCUACCUMINTENACLR,Read" "No change to Disable Accum interrupt enable,Disable Accum interrupt generation" newline bitfld.long 0x30 2. "MCUVALIDINTENACLR,Read" "No change to Disable Valid interrupt enable,Disable Valid interrupt generation" bitfld.long 0x30 1. "MCUBOUNDSINTENACLR,Read" "No change to Bounds interrupt enable,Disable Bounds interrupt generation" newline bitfld.long 0x30 0. "MCUDISABLEACKINTENACLR,Read" "No change to MCUDisAck interrupt enable,Disable MCUDisableAck interrupt generation" line.long 0x34 "SENERROR,The sensor error from the error generator" hexmask.long.word 0x34 16.--31. 1. "RESERVED," hexmask.long.byte 0x34 8.--15. 1. "AVGERROR,The average sensor error" newline hexmask.long.byte 0x34 0.--7. 1. "SENERROR,The percentage of sensor error" line.long 0x38 "ERRCONFIG,The sensor error configuration" rbitfld.long 0x38 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 26. "WAKEUPENABLE,Wakeup from MCU Interrupts enable" "0,1" newline bitfld.long 0x38 24.--25. "IDLEMODE," "0,1,2,3" bitfld.long 0x38 23. "VPBOUNDSINTSTATENA,Read: Bounds interrupt status if enabled Write" "Bounds interrupt status is unchanged,Bounds interrupt status is cleared" newline bitfld.long 0x38 22. "VPBOUNDSINTENABLE," "0,1" rbitfld.long 0x38 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 16.--18. "ERRWEIGHT,The AvgSenError weight" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 8.--15. 1. "ERRMAXLIMIT,The upper limit of SenError for interrupt generation" newline hexmask.long.byte 0x38 0.--7. 1. "ERRMINLIMIT,The lower limit of SenError for interrupt generation" width 0x0B tree.end tree "SMARTREFLEX_DSPEVE" base ad:0x4A183000 group.long 0x00++0x3B line.long 0x00 "SRCONFIG,Configuration bits for the Sensor Core and the Digital Processing" hexmask.long.word 0x00 22.--31. 1. "ACCUMDATA,Number of values to accumulate" hexmask.long.word 0x00 12.--21. 1. "SRCLKLENGTH,Determines the frequency of SRClk" newline bitfld.long 0x00 11. "SRENABLE," "0,1" bitfld.long 0x00 10. "SENENABLE," "0,1" newline bitfld.long 0x00 9. "ERRORGENERATORENABLE," "0,1" bitfld.long 0x00 8. "MINMAXAVGENABLE," "0,1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1. "SENNENABLE," "0,1" newline bitfld.long 0x00 0. "SENPENABLE," "0,1" line.long 0x04 "SRSTATUS,Status bits that indicate that the values in the register are valid or events have occurred" hexmask.long 0x04 4.--31. 1. "RESERVED," bitfld.long 0x04 3. "AVGERRVALID," "0,1" newline bitfld.long 0x04 2. "MINMAXAVGVALID," "0,1" bitfld.long 0x04 1. "ERRORGENERATORVALID," "0,1" newline bitfld.long 0x04 0. "MINMAXAVGACCUMVALID," "0,1" line.long 0x08 "SENVAL,The current sensor values from the Sensor Core(SVT)" hexmask.long.word 0x08 16.--31. 1. "SENPVAL,The latest value of the SenPVal from the SVT sensor core" hexmask.long.word 0x08 0.--15. 1. "SENNVAL,The latest value of the SenNVal from the SVT sensor core" line.long 0x0C "SENMIN,The minimum sensor values(SVT)" hexmask.long.word 0x0C 16.--31. 1. "SENPMIN,The minimum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x0C 0.--15. 1. "SENNMIN,The minimum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x10 "SENMAX,The maximum sensor values(SVT)" hexmask.long.word 0x10 16.--31. 1. "SENPMAX,The maximum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x10 0.--15. 1. "SENNMAX,The maximum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x14 "SENAVG,The average sensor values(SVT)" hexmask.long.word 0x14 16.--31. 1. "SENPAVG,The running average of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x14 0.--15. 1. "SENNAVG,The running average of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x18 "AVGWEIGHT,The weighting factor in the average computation" hexmask.long.word 0x18 16.--31. 1. "SENPAVGWEIGHT1,The weighting factor for the SenP averager" hexmask.long.word 0x18 0.--15. 1. "SENNAVGWEIGHT,The weighting factor for the SenN averager" line.long 0x1C "NVALUERECIPROCAL,The reciprocal of the SenN and SenP values used in error generation(SVT)" hexmask.long.byte 0x1C 24.--31. 1. "RESERVED," bitfld.long 0x1C 20.--23. "SENPGAIN,The gain value for the SVT SenP reciprocal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 16.--19. "SENNGAIN,The gain value for the SVT SenN reciprocal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x1C 8.--15. 1. "SENPRN,The scale value for the SVT SenP reciprocal" newline hexmask.long.byte 0x1C 0.--7. 1. "SENNRN,The scale value for the SVT SenN reciprocal" line.long 0x20 "IRQ_EOI,EOI protocol re-trigger" hexmask.long 0x20 1.--31. 1. "RESERVED," bitfld.long 0x20 0. "EOI,The value read is always '0' Write" "re-evaluate pending sources re-send intr*,No change to interrupt" line.long 0x24 "IRQSTATUS_RAW,MCU raw interrupt raw status and set" hexmask.long 0x24 4.--31. 1. "RESERVED," bitfld.long 0x24 3. "MCUACCUMINTSTATRAW,Read:Accum interrupt status Write" "Accum interrupt status is unchanged,Accum interrupt status is set" newline bitfld.long 0x24 2. "MCUVALIDINTSTATRAW,Read:Valid interrupt status Write" "Valid status is unchanged,Valid status is set" bitfld.long 0x24 1. "MCUBOUNDSINTSTATRAW,Read:Bounds interrupt status Write" "Bounds interrupt status is unchanged,Bounds interrupt status is set" newline bitfld.long 0x24 0. "MCUDISABLEACKINTSTATRAW,Read:MCUDisable acknowledge interrupt status Write" "MCUDisable acknowledge status is unchanged,MCUDisable acknowledge status is set" line.long 0x28 "IRQSTATUS,MCU masked interrupt status and clear" hexmask.long 0x28 4.--31. 1. "RESERVED," bitfld.long 0x28 3. "MCUACCUMINTSTATENA,Read:Accum interrupt status if enabled Write" "Accum interrupt status is unchanged,Accum interrupt status is cleared" newline bitfld.long 0x28 2. "MCUVALIDINTSTATENA,Read:Valid interrupt status if enabled Write" "Valid interrupt status is unchanged,Valid interrupt status is cleared" bitfld.long 0x28 1. "MCUBOUNDSINTSTATENA,Read:Bounds interrupt status if enabled Write" "Bounds interrupt status is unchanged,Bounds interrupt status is cleared" newline bitfld.long 0x28 0. "MCUDISABLEACKINTSTATENA,Read:MCUDisable acknowledge interrupt status if enabled Write" "MCUDisable acknowledge status is unchanged,MCUDisable acknowledge status is cleared" line.long 0x2C "IRQENABLE_SET,MCU interrupt enable flag set" hexmask.long 0x2C 4.--31. 1. "RESERVED," bitfld.long 0x2C 3. "MCUACCUMINTENASET,Read" "No change to Accum interrupt enable,Enable Accum interrupt generation" newline bitfld.long 0x2C 2. "MCUVALIDINTENASET,Read" "No change to Valid interrupt enable,Enable Valid interrupt generation" bitfld.long 0x2C 1. "MCUBOUNDSINTENASET,Read" "No change to Bounds interrupt enable,Enable Bounds interrupt generation" newline bitfld.long 0x2C 0. "MCUDISABLEACKINTENASET,Read" "No change to MCUDisAck interrupt enable,Enable MCUDisableAck interrupt generation" line.long 0x30 "IRQENABLE_CLR,MCU interrupt enable flag clear" hexmask.long 0x30 4.--31. 1. "RESERVED," bitfld.long 0x30 3. "MCUACCUMINTENACLR,Read" "No change to Disable Accum interrupt enable,Disable Accum interrupt generation" newline bitfld.long 0x30 2. "MCUVALIDINTENACLR,Read" "No change to Disable Valid interrupt enable,Disable Valid interrupt generation" bitfld.long 0x30 1. "MCUBOUNDSINTENACLR,Read" "No change to Bounds interrupt enable,Disable Bounds interrupt generation" newline bitfld.long 0x30 0. "MCUDISABLEACKINTENACLR,Read" "No change to MCUDisAck interrupt enable,Disable MCUDisableAck interrupt generation" line.long 0x34 "SENERROR,The sensor error from the error generator" hexmask.long.word 0x34 16.--31. 1. "RESERVED," hexmask.long.byte 0x34 8.--15. 1. "AVGERROR,The average sensor error" newline hexmask.long.byte 0x34 0.--7. 1. "SENERROR,The percentage of sensor error" line.long 0x38 "ERRCONFIG,The sensor error configuration" rbitfld.long 0x38 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 26. "WAKEUPENABLE,Wakeup from MCU Interrupts enable" "0,1" newline bitfld.long 0x38 24.--25. "IDLEMODE," "0,1,2,3" bitfld.long 0x38 23. "VPBOUNDSINTSTATENA,Read: Bounds interrupt status if enabled Write" "Bounds interrupt status is unchanged,Bounds interrupt status is cleared" newline bitfld.long 0x38 22. "VPBOUNDSINTENABLE," "0,1" rbitfld.long 0x38 19.--21. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 16.--18. "ERRWEIGHT,The AvgSenError weight" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 8.--15. 1. "ERRMAXLIMIT,The upper limit of SenError for interrupt generation" newline hexmask.long.byte 0x38 0.--7. 1. "ERRMINLIMIT,The lower limit of SenError for interrupt generation" width 0x0B tree.end repeat 2. (list 1. 2. )(list ad:0x48485C00 ad:0x48485E00 ) tree "SPF$1" base $2 rgroup.long 0x00++0x27 line.long 0x00 "SPF_IDVER,SPF revision register" line.long 0x04 "SPF_STATUS,Status register" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "SPF_BUSY,SPF is Busy/Idle Busy Packet processing or logging in progress" "0,1" line.long 0x08 "SPF_CONTROL,SPF control register" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "SPF_LOGOW_EN,SPF Log Overwrite Enable" "0,1" bitfld.long 0x08 8. "SPF_LOG_EN,SPF Log Enable" "0,1" rbitfld.long 0x08 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 3. "SPF_RULE_LOG,SPF Rule Engine Log Enable" "0,1" bitfld.long 0x08 2. "SPF_EXT_BYPASS,SPF Extractor Bypass Enable" "0,1" newline bitfld.long 0x08 1. "SPF_DROP,SPF Drop Enable" "0,1" bitfld.long 0x08 0. "SPF_ENABLE,SPF Enable" "0,1" line.long 0x0C "SPF_DROPCOUNT,Drop Count Register" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," hexmask.long.tbyte 0x0C 0.--23. 1. "SPF_DROPCNT,SPF Drop counter indicates the number of packets dropped so far" line.long 0x10 "SPF_SWRESET,Software Reset Register" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "SPF_SWRST,SPF Software reset bit can be set to initiate a software reset" "0,1" line.long 0x14 "SPF_PRESCALE,Rate Limit Prescale Register" hexmask.long.word 0x14 20.--31. 1. "RESERVED," hexmask.long.tbyte 0x14 0.--19. 1. "SPF_PRESCALE,The MAIN clock is divided by this value for use in Rate Limiters" line.long 0x18 "SPF_RATELIMi_0,Rate Limit Register" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," hexmask.long.byte 0x18 0.--7. 1. "SPF_RATELIM,SPF Rate Limit Register" line.long 0x1C "SPF_RATELIMi_1,Rate Limit Register" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED," hexmask.long.byte 0x1C 0.--7. 1. "SPF_RATELIM,SPF Rate Limit Register" line.long 0x20 "SPF_RATELIMi_2,Rate Limit Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED," hexmask.long.byte 0x20 0.--7. 1. "SPF_RATELIM,SPF Rate Limit Register" line.long 0x24 "SPF_RATELIMi_3,Rate Limit Register" hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED," hexmask.long.byte 0x24 0.--7. 1. "SPF_RATELIM,SPF Rate Limit Register" group.long 0x1C++0x1F line.long 0x00 "SPF_CONSTj_0,Constant Register" line.long 0x04 "SPF_CONSTj_1,Constant Register" line.long 0x08 "SPF_CONSTj_2,Constant Register" line.long 0x0C "SPF_CONSTj_3,Constant Register" line.long 0x10 "SPF_CONSTj_4,Constant Register" line.long 0x14 "SPF_CONSTj_5,Constant Register" line.long 0x18 "SPF_CONSTj_6,Constant Register" line.long 0x1C "SPF_CONSTj_7,Constant Register" group.long 0x50++0x5F line.long 0x00 "SPF_INSTRW2,Instruction Word 2 Register" hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED," hexmask.long.word 0x00 0.--13. 1. "SPF_INSTR_W2,SPF Rule Engine Instruction Word [75:64] is read from or written to this field" line.long 0x04 "SPF_INSTRW1,Instruction Word 1 Register" line.long 0x08 "SPF_INSTRW0,Instruction Word 0 Register" line.long 0x0C "SPF_INSTR_CTL,Instruction Control Register" bitfld.long 0x0C 31. "SPF_INSTR_WEN,SPF Write enable bit specifies whether a write operation is to be performed" "0,1" bitfld.long 0x0C 30. "SPF_INSTR_REN,SPF Read enable bit specifies whether a read operation is to be performed" "0,1" hexmask.long.tbyte 0x0C 6.--29. 1. "RESERVED," bitfld.long 0x0C 0.--5. "SPF_INSTR_PTR,The address in the instruction memory that is to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "SPF_LOG_BEGIN,Log Begin Address Register" line.long 0x14 "SPF_LOG_END,Log End Address Register" line.long 0x18 "SPF_LOG_HWPTR,Log Hardware Pointer Register" line.long 0x1C "SPF_LOG_SWPTR,Log Software Pointer Register" line.long 0x20 "SPF_LOG_MAP0,Filter Code Map Register 0" hexmask.long.byte 0x20 24.--31. 1. "SPF_LOGMAP3,Mapping of drop code 3 to log threshold 3" hexmask.long.byte 0x20 16.--23. 1. "SPF_LOGMAP2,Mapping of drop code 2 to log threshold 2" hexmask.long.byte 0x20 8.--15. 1. "SPF_LOGMAP1,Mapping of drop code 1 to log threshold 1" hexmask.long.byte 0x20 0.--7. 1. "SPF_LOGMAP0,Mapping of drop code 0 to log threshold 0" line.long 0x24 "SPF_LOG_MAP1,Filter Code Map Register 1" hexmask.long.byte 0x24 24.--31. 1. "SPF_LOGMAP7,Mapping of drop code 7 to log threshold 7" hexmask.long.byte 0x24 16.--23. 1. "SPF_LOGMAP6,Mapping of drop code 6 to log threshold 6" hexmask.long.byte 0x24 8.--15. 1. "SPF_LOGMAP5,Mapping of drop code 5 to log threshold 5" hexmask.long.byte 0x24 0.--7. 1. "SPF_LOGMAP4,Mapping of drop code 4 to log threshold 4" line.long 0x28 "SPF_LOG_THRESHk_0,Log Threshold and Count Register" hexmask.long.word 0x28 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x28 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x2C "SPF_LOG_THRESHk_1,Log Threshold and Count Register" hexmask.long.word 0x2C 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x2C 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x30 "SPF_LOG_THRESHk_2,Log Threshold and Count Register" hexmask.long.word 0x30 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x30 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x34 "SPF_LOG_THRESHk_3,Log Threshold and Count Register" hexmask.long.word 0x34 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x34 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x38 "SPF_LOG_THRESHk_4,Log Threshold and Count Register" hexmask.long.word 0x38 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x38 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x3C "SPF_LOG_THRESHk_5,Log Threshold and Count Register" hexmask.long.word 0x3C 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x3C 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x40 "SPF_LOG_THRESHk_6,Log Threshold and Count Register" hexmask.long.word 0x40 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x40 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x44 "SPF_LOG_THRESHk_7,Log Threshold and Count Register" hexmask.long.word 0x44 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x44 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x48 "SPF_LOG_THRESHk_8,Log Threshold and Count Register" hexmask.long.word 0x48 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x48 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x4C "SPF_INTCNT,Interrupt Frequency Control Register" hexmask.long 0x4C 5.--31. 1. "RESERVED," bitfld.long 0x4C 0.--4. "SPF_INTCNT,Number of time thresholds must be met before a drop interrupt is triggered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "SPF_INT_RAW,Raw Interrupt Status register" hexmask.long 0x50 1.--31. 1. "RESERVED," bitfld.long 0x50 0. "SPF_INT_RAW,Status of Raw interrupt signal" "0,1" line.long 0x54 "SPF_INT_MASKED,Interrupt Status register" hexmask.long 0x54 1.--31. 1. "RESERVED," bitfld.long 0x54 0. "SPF_INT_MASKED,Status of interrupt signal with mask" "0,1" line.long 0x58 "SPF_MASK_SET,Interrupt Mask Set Register" hexmask.long 0x58 1.--31. 1. "RESERVED," bitfld.long 0x58 0. "SPF_MASKSET,Write a 1 to this bit to enable the interrupt" "0,1" line.long 0x5C "SPF_MASK_CLR,Interrupt Mask Clear Register" hexmask.long 0x5C 1.--31. 1. "RESERVED," bitfld.long 0x5C 0. "SPF_MASKCLR,Write a 1 to this bit to disable the interrupt" "0,1" width 0x0B tree.end repeat.end tree "Spinlock" base ad:0x4A0F6000 rgroup.long 0x00++0x03 line.long 0x00 "SPINLOCK_REVISION,This register contains the IP revision code" group.long 0x10++0x07 line.long 0x00 "SPINLOCK_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 3.--4. "SIDLEMODE,Slave interface power management (IDLE request/acknowledgement control)" "SIDLEMODE_0_r,SIDLEMODE_1_r,SIDLEMODE_2_r,SIDLEMODE_3_r" rbitfld.long 0x00 2. "ENWAKEUP,Asynchronous wakeup gereration" "ENWAKEUP_0_r,ENWAKEUP_1_r" bitfld.long 0x00 1. "SOFTRESET,Module software reset" "SOFTRESET_0_w,SOFTRESET_1_w" rbitfld.long 0x00 0. "AUTOGATING,Internal interface clock gating strategy" "AUTOGATING_0_r,AUTOGATING_1_r" line.long 0x04 "SPINLOCK_SYSTATUS,This register provides status information about this instance of the Spinlock module" hexmask.long.byte 0x04 24.--31. 1. "NUMLOCKS,Number of lock registers implemeted" hexmask.long.byte 0x04 16.--23. 1. "RESERVED,Reserved" bitfld.long 0x04 15. "IU7,In-Use flag 0 covering lock registers" "IU7_0_r,IU7_1_r" bitfld.long 0x04 14. "IU6,In-Use flag 0 covering lock registers" "IU6_0_r,IU6_1_r" bitfld.long 0x04 13. "IU5,In-Use flag 0 covering lock registers" "IU5_0_r,IU5_1_r" newline bitfld.long 0x04 12. "IU4,In-Use flag 0 covering lock registers" "IU4_0_r,IU4_1_r" bitfld.long 0x04 11. "IU3,In-Use flag 0 covering lock registers" "IU3_0_r,IU3_1_r" bitfld.long 0x04 10. "IU2,In-Use flag 0 covering lock registers" "IU2_0_r,IU2_1_r" bitfld.long 0x04 9. "IU1,In-Use flag 0 covering lock registers" "IU1_0_r,IU1_1_r" bitfld.long 0x04 8. "IU0,In-Use flag 0 covering lock registers" "IU0_0_r,IU0_1_r" newline hexmask.long.byte 0x04 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x04 0. "RESETDONE,Reset done status" "RESETDONE_0_r,RESETDONE_1_r" group.long 0x800++0x3FF line.long 0x00 "SPINLOCK_LOCK_REG_i_0,This register contains the state of one lock" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x04 "SPINLOCK_LOCK_REG_i_1,This register contains the state of one lock" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x08 "SPINLOCK_LOCK_REG_i_2,This register contains the state of one lock" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x0C "SPINLOCK_LOCK_REG_i_3,This register contains the state of one lock" hexmask.long 0x0C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x10 "SPINLOCK_LOCK_REG_i_4,This register contains the state of one lock" hexmask.long 0x10 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x14 "SPINLOCK_LOCK_REG_i_5,This register contains the state of one lock" hexmask.long 0x14 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x18 "SPINLOCK_LOCK_REG_i_6,This register contains the state of one lock" hexmask.long 0x18 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1C "SPINLOCK_LOCK_REG_i_7,This register contains the state of one lock" hexmask.long 0x1C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x20 "SPINLOCK_LOCK_REG_i_8,This register contains the state of one lock" hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x24 "SPINLOCK_LOCK_REG_i_9,This register contains the state of one lock" hexmask.long 0x24 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x28 "SPINLOCK_LOCK_REG_i_10,This register contains the state of one lock" hexmask.long 0x28 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2C "SPINLOCK_LOCK_REG_i_11,This register contains the state of one lock" hexmask.long 0x2C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x30 "SPINLOCK_LOCK_REG_i_12,This register contains the state of one lock" hexmask.long 0x30 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x30 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x34 "SPINLOCK_LOCK_REG_i_13,This register contains the state of one lock" hexmask.long 0x34 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x38 "SPINLOCK_LOCK_REG_i_14,This register contains the state of one lock" hexmask.long 0x38 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x38 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3C "SPINLOCK_LOCK_REG_i_15,This register contains the state of one lock" hexmask.long 0x3C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x40 "SPINLOCK_LOCK_REG_i_16,This register contains the state of one lock" hexmask.long 0x40 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x40 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x44 "SPINLOCK_LOCK_REG_i_17,This register contains the state of one lock" hexmask.long 0x44 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x44 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x48 "SPINLOCK_LOCK_REG_i_18,This register contains the state of one lock" hexmask.long 0x48 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x48 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x4C "SPINLOCK_LOCK_REG_i_19,This register contains the state of one lock" hexmask.long 0x4C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x50 "SPINLOCK_LOCK_REG_i_20,This register contains the state of one lock" hexmask.long 0x50 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x50 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x54 "SPINLOCK_LOCK_REG_i_21,This register contains the state of one lock" hexmask.long 0x54 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x54 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x58 "SPINLOCK_LOCK_REG_i_22,This register contains the state of one lock" hexmask.long 0x58 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x58 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x5C "SPINLOCK_LOCK_REG_i_23,This register contains the state of one lock" hexmask.long 0x5C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x5C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x60 "SPINLOCK_LOCK_REG_i_24,This register contains the state of one lock" hexmask.long 0x60 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x60 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x64 "SPINLOCK_LOCK_REG_i_25,This register contains the state of one lock" hexmask.long 0x64 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x64 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x68 "SPINLOCK_LOCK_REG_i_26,This register contains the state of one lock" hexmask.long 0x68 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x68 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x6C "SPINLOCK_LOCK_REG_i_27,This register contains the state of one lock" hexmask.long 0x6C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x6C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x70 "SPINLOCK_LOCK_REG_i_28,This register contains the state of one lock" hexmask.long 0x70 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x70 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x74 "SPINLOCK_LOCK_REG_i_29,This register contains the state of one lock" hexmask.long 0x74 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x74 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x78 "SPINLOCK_LOCK_REG_i_30,This register contains the state of one lock" hexmask.long 0x78 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x78 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x7C "SPINLOCK_LOCK_REG_i_31,This register contains the state of one lock" hexmask.long 0x7C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x7C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x80 "SPINLOCK_LOCK_REG_i_32,This register contains the state of one lock" hexmask.long 0x80 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x80 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x84 "SPINLOCK_LOCK_REG_i_33,This register contains the state of one lock" hexmask.long 0x84 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x84 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x88 "SPINLOCK_LOCK_REG_i_34,This register contains the state of one lock" hexmask.long 0x88 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x88 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x8C "SPINLOCK_LOCK_REG_i_35,This register contains the state of one lock" hexmask.long 0x8C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x8C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x90 "SPINLOCK_LOCK_REG_i_36,This register contains the state of one lock" hexmask.long 0x90 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x90 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x94 "SPINLOCK_LOCK_REG_i_37,This register contains the state of one lock" hexmask.long 0x94 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x94 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x98 "SPINLOCK_LOCK_REG_i_38,This register contains the state of one lock" hexmask.long 0x98 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x98 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x9C "SPINLOCK_LOCK_REG_i_39,This register contains the state of one lock" hexmask.long 0x9C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x9C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xA0 "SPINLOCK_LOCK_REG_i_40,This register contains the state of one lock" hexmask.long 0xA0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xA0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xA4 "SPINLOCK_LOCK_REG_i_41,This register contains the state of one lock" hexmask.long 0xA4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xA4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xA8 "SPINLOCK_LOCK_REG_i_42,This register contains the state of one lock" hexmask.long 0xA8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xA8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xAC "SPINLOCK_LOCK_REG_i_43,This register contains the state of one lock" hexmask.long 0xAC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xAC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xB0 "SPINLOCK_LOCK_REG_i_44,This register contains the state of one lock" hexmask.long 0xB0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xB0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xB4 "SPINLOCK_LOCK_REG_i_45,This register contains the state of one lock" hexmask.long 0xB4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xB4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xB8 "SPINLOCK_LOCK_REG_i_46,This register contains the state of one lock" hexmask.long 0xB8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xB8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xBC "SPINLOCK_LOCK_REG_i_47,This register contains the state of one lock" hexmask.long 0xBC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xBC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xC0 "SPINLOCK_LOCK_REG_i_48,This register contains the state of one lock" hexmask.long 0xC0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xC4 "SPINLOCK_LOCK_REG_i_49,This register contains the state of one lock" hexmask.long 0xC4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xC8 "SPINLOCK_LOCK_REG_i_50,This register contains the state of one lock" hexmask.long 0xC8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xCC "SPINLOCK_LOCK_REG_i_51,This register contains the state of one lock" hexmask.long 0xCC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xCC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xD0 "SPINLOCK_LOCK_REG_i_52,This register contains the state of one lock" hexmask.long 0xD0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xD0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xD4 "SPINLOCK_LOCK_REG_i_53,This register contains the state of one lock" hexmask.long 0xD4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xD4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xD8 "SPINLOCK_LOCK_REG_i_54,This register contains the state of one lock" hexmask.long 0xD8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xD8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xDC "SPINLOCK_LOCK_REG_i_55,This register contains the state of one lock" hexmask.long 0xDC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xDC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xE0 "SPINLOCK_LOCK_REG_i_56,This register contains the state of one lock" hexmask.long 0xE0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xE0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xE4 "SPINLOCK_LOCK_REG_i_57,This register contains the state of one lock" hexmask.long 0xE4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xE4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xE8 "SPINLOCK_LOCK_REG_i_58,This register contains the state of one lock" hexmask.long 0xE8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xE8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xEC "SPINLOCK_LOCK_REG_i_59,This register contains the state of one lock" hexmask.long 0xEC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xEC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xF0 "SPINLOCK_LOCK_REG_i_60,This register contains the state of one lock" hexmask.long 0xF0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xF0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xF4 "SPINLOCK_LOCK_REG_i_61,This register contains the state of one lock" hexmask.long 0xF4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xF4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xF8 "SPINLOCK_LOCK_REG_i_62,This register contains the state of one lock" hexmask.long 0xF8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xF8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0xFC "SPINLOCK_LOCK_REG_i_63,This register contains the state of one lock" hexmask.long 0xFC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xFC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x100 "SPINLOCK_LOCK_REG_i_64,This register contains the state of one lock" hexmask.long 0x100 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x100 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x104 "SPINLOCK_LOCK_REG_i_65,This register contains the state of one lock" hexmask.long 0x104 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x104 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x108 "SPINLOCK_LOCK_REG_i_66,This register contains the state of one lock" hexmask.long 0x108 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x108 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x10C "SPINLOCK_LOCK_REG_i_67,This register contains the state of one lock" hexmask.long 0x10C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x10C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x110 "SPINLOCK_LOCK_REG_i_68,This register contains the state of one lock" hexmask.long 0x110 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x110 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x114 "SPINLOCK_LOCK_REG_i_69,This register contains the state of one lock" hexmask.long 0x114 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x114 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x118 "SPINLOCK_LOCK_REG_i_70,This register contains the state of one lock" hexmask.long 0x118 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x118 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x11C "SPINLOCK_LOCK_REG_i_71,This register contains the state of one lock" hexmask.long 0x11C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x11C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x120 "SPINLOCK_LOCK_REG_i_72,This register contains the state of one lock" hexmask.long 0x120 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x120 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x124 "SPINLOCK_LOCK_REG_i_73,This register contains the state of one lock" hexmask.long 0x124 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x124 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x128 "SPINLOCK_LOCK_REG_i_74,This register contains the state of one lock" hexmask.long 0x128 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x128 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x12C "SPINLOCK_LOCK_REG_i_75,This register contains the state of one lock" hexmask.long 0x12C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x12C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x130 "SPINLOCK_LOCK_REG_i_76,This register contains the state of one lock" hexmask.long 0x130 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x130 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x134 "SPINLOCK_LOCK_REG_i_77,This register contains the state of one lock" hexmask.long 0x134 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x134 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x138 "SPINLOCK_LOCK_REG_i_78,This register contains the state of one lock" hexmask.long 0x138 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x138 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x13C "SPINLOCK_LOCK_REG_i_79,This register contains the state of one lock" hexmask.long 0x13C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x13C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x140 "SPINLOCK_LOCK_REG_i_80,This register contains the state of one lock" hexmask.long 0x140 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x140 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x144 "SPINLOCK_LOCK_REG_i_81,This register contains the state of one lock" hexmask.long 0x144 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x144 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x148 "SPINLOCK_LOCK_REG_i_82,This register contains the state of one lock" hexmask.long 0x148 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x148 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x14C "SPINLOCK_LOCK_REG_i_83,This register contains the state of one lock" hexmask.long 0x14C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x14C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x150 "SPINLOCK_LOCK_REG_i_84,This register contains the state of one lock" hexmask.long 0x150 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x150 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x154 "SPINLOCK_LOCK_REG_i_85,This register contains the state of one lock" hexmask.long 0x154 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x154 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x158 "SPINLOCK_LOCK_REG_i_86,This register contains the state of one lock" hexmask.long 0x158 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x158 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x15C "SPINLOCK_LOCK_REG_i_87,This register contains the state of one lock" hexmask.long 0x15C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x15C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x160 "SPINLOCK_LOCK_REG_i_88,This register contains the state of one lock" hexmask.long 0x160 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x160 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x164 "SPINLOCK_LOCK_REG_i_89,This register contains the state of one lock" hexmask.long 0x164 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x164 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x168 "SPINLOCK_LOCK_REG_i_90,This register contains the state of one lock" hexmask.long 0x168 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x168 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x16C "SPINLOCK_LOCK_REG_i_91,This register contains the state of one lock" hexmask.long 0x16C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x16C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x170 "SPINLOCK_LOCK_REG_i_92,This register contains the state of one lock" hexmask.long 0x170 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x170 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x174 "SPINLOCK_LOCK_REG_i_93,This register contains the state of one lock" hexmask.long 0x174 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x174 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x178 "SPINLOCK_LOCK_REG_i_94,This register contains the state of one lock" hexmask.long 0x178 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x178 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x17C "SPINLOCK_LOCK_REG_i_95,This register contains the state of one lock" hexmask.long 0x17C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x17C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x180 "SPINLOCK_LOCK_REG_i_96,This register contains the state of one lock" hexmask.long 0x180 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x180 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x184 "SPINLOCK_LOCK_REG_i_97,This register contains the state of one lock" hexmask.long 0x184 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x184 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x188 "SPINLOCK_LOCK_REG_i_98,This register contains the state of one lock" hexmask.long 0x188 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x188 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x18C "SPINLOCK_LOCK_REG_i_99,This register contains the state of one lock" hexmask.long 0x18C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x18C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x190 "SPINLOCK_LOCK_REG_i_100,This register contains the state of one lock" hexmask.long 0x190 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x190 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x194 "SPINLOCK_LOCK_REG_i_101,This register contains the state of one lock" hexmask.long 0x194 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x194 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x198 "SPINLOCK_LOCK_REG_i_102,This register contains the state of one lock" hexmask.long 0x198 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x198 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x19C "SPINLOCK_LOCK_REG_i_103,This register contains the state of one lock" hexmask.long 0x19C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x19C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1A0 "SPINLOCK_LOCK_REG_i_104,This register contains the state of one lock" hexmask.long 0x1A0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1A0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1A4 "SPINLOCK_LOCK_REG_i_105,This register contains the state of one lock" hexmask.long 0x1A4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1A4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1A8 "SPINLOCK_LOCK_REG_i_106,This register contains the state of one lock" hexmask.long 0x1A8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1A8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1AC "SPINLOCK_LOCK_REG_i_107,This register contains the state of one lock" hexmask.long 0x1AC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1AC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1B0 "SPINLOCK_LOCK_REG_i_108,This register contains the state of one lock" hexmask.long 0x1B0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1B0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1B4 "SPINLOCK_LOCK_REG_i_109,This register contains the state of one lock" hexmask.long 0x1B4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1B4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1B8 "SPINLOCK_LOCK_REG_i_110,This register contains the state of one lock" hexmask.long 0x1B8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1B8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1BC "SPINLOCK_LOCK_REG_i_111,This register contains the state of one lock" hexmask.long 0x1BC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1BC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1C0 "SPINLOCK_LOCK_REG_i_112,This register contains the state of one lock" hexmask.long 0x1C0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1C4 "SPINLOCK_LOCK_REG_i_113,This register contains the state of one lock" hexmask.long 0x1C4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1C8 "SPINLOCK_LOCK_REG_i_114,This register contains the state of one lock" hexmask.long 0x1C8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1CC "SPINLOCK_LOCK_REG_i_115,This register contains the state of one lock" hexmask.long 0x1CC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1CC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1D0 "SPINLOCK_LOCK_REG_i_116,This register contains the state of one lock" hexmask.long 0x1D0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1D0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1D4 "SPINLOCK_LOCK_REG_i_117,This register contains the state of one lock" hexmask.long 0x1D4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1D4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1D8 "SPINLOCK_LOCK_REG_i_118,This register contains the state of one lock" hexmask.long 0x1D8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1D8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1DC "SPINLOCK_LOCK_REG_i_119,This register contains the state of one lock" hexmask.long 0x1DC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1DC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1E0 "SPINLOCK_LOCK_REG_i_120,This register contains the state of one lock" hexmask.long 0x1E0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1E0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1E4 "SPINLOCK_LOCK_REG_i_121,This register contains the state of one lock" hexmask.long 0x1E4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1E4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1E8 "SPINLOCK_LOCK_REG_i_122,This register contains the state of one lock" hexmask.long 0x1E8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1E8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1EC "SPINLOCK_LOCK_REG_i_123,This register contains the state of one lock" hexmask.long 0x1EC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1EC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1F0 "SPINLOCK_LOCK_REG_i_124,This register contains the state of one lock" hexmask.long 0x1F0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1F0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1F4 "SPINLOCK_LOCK_REG_i_125,This register contains the state of one lock" hexmask.long 0x1F4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1F4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1F8 "SPINLOCK_LOCK_REG_i_126,This register contains the state of one lock" hexmask.long 0x1F8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1F8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x1FC "SPINLOCK_LOCK_REG_i_127,This register contains the state of one lock" hexmask.long 0x1FC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x1FC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x200 "SPINLOCK_LOCK_REG_i_128,This register contains the state of one lock" hexmask.long 0x200 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x200 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x204 "SPINLOCK_LOCK_REG_i_129,This register contains the state of one lock" hexmask.long 0x204 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x204 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x208 "SPINLOCK_LOCK_REG_i_130,This register contains the state of one lock" hexmask.long 0x208 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x208 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x20C "SPINLOCK_LOCK_REG_i_131,This register contains the state of one lock" hexmask.long 0x20C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x20C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x210 "SPINLOCK_LOCK_REG_i_132,This register contains the state of one lock" hexmask.long 0x210 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x210 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x214 "SPINLOCK_LOCK_REG_i_133,This register contains the state of one lock" hexmask.long 0x214 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x214 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x218 "SPINLOCK_LOCK_REG_i_134,This register contains the state of one lock" hexmask.long 0x218 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x218 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x21C "SPINLOCK_LOCK_REG_i_135,This register contains the state of one lock" hexmask.long 0x21C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x21C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x220 "SPINLOCK_LOCK_REG_i_136,This register contains the state of one lock" hexmask.long 0x220 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x220 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x224 "SPINLOCK_LOCK_REG_i_137,This register contains the state of one lock" hexmask.long 0x224 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x224 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x228 "SPINLOCK_LOCK_REG_i_138,This register contains the state of one lock" hexmask.long 0x228 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x228 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x22C "SPINLOCK_LOCK_REG_i_139,This register contains the state of one lock" hexmask.long 0x22C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x22C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x230 "SPINLOCK_LOCK_REG_i_140,This register contains the state of one lock" hexmask.long 0x230 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x230 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x234 "SPINLOCK_LOCK_REG_i_141,This register contains the state of one lock" hexmask.long 0x234 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x234 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x238 "SPINLOCK_LOCK_REG_i_142,This register contains the state of one lock" hexmask.long 0x238 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x238 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x23C "SPINLOCK_LOCK_REG_i_143,This register contains the state of one lock" hexmask.long 0x23C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x23C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x240 "SPINLOCK_LOCK_REG_i_144,This register contains the state of one lock" hexmask.long 0x240 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x240 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x244 "SPINLOCK_LOCK_REG_i_145,This register contains the state of one lock" hexmask.long 0x244 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x244 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x248 "SPINLOCK_LOCK_REG_i_146,This register contains the state of one lock" hexmask.long 0x248 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x248 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x24C "SPINLOCK_LOCK_REG_i_147,This register contains the state of one lock" hexmask.long 0x24C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x24C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x250 "SPINLOCK_LOCK_REG_i_148,This register contains the state of one lock" hexmask.long 0x250 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x250 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x254 "SPINLOCK_LOCK_REG_i_149,This register contains the state of one lock" hexmask.long 0x254 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x254 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x258 "SPINLOCK_LOCK_REG_i_150,This register contains the state of one lock" hexmask.long 0x258 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x258 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x25C "SPINLOCK_LOCK_REG_i_151,This register contains the state of one lock" hexmask.long 0x25C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x25C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x260 "SPINLOCK_LOCK_REG_i_152,This register contains the state of one lock" hexmask.long 0x260 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x260 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x264 "SPINLOCK_LOCK_REG_i_153,This register contains the state of one lock" hexmask.long 0x264 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x264 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x268 "SPINLOCK_LOCK_REG_i_154,This register contains the state of one lock" hexmask.long 0x268 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x268 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x26C "SPINLOCK_LOCK_REG_i_155,This register contains the state of one lock" hexmask.long 0x26C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x26C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x270 "SPINLOCK_LOCK_REG_i_156,This register contains the state of one lock" hexmask.long 0x270 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x270 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x274 "SPINLOCK_LOCK_REG_i_157,This register contains the state of one lock" hexmask.long 0x274 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x274 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x278 "SPINLOCK_LOCK_REG_i_158,This register contains the state of one lock" hexmask.long 0x278 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x278 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x27C "SPINLOCK_LOCK_REG_i_159,This register contains the state of one lock" hexmask.long 0x27C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x27C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x280 "SPINLOCK_LOCK_REG_i_160,This register contains the state of one lock" hexmask.long 0x280 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x280 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x284 "SPINLOCK_LOCK_REG_i_161,This register contains the state of one lock" hexmask.long 0x284 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x284 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x288 "SPINLOCK_LOCK_REG_i_162,This register contains the state of one lock" hexmask.long 0x288 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x288 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x28C "SPINLOCK_LOCK_REG_i_163,This register contains the state of one lock" hexmask.long 0x28C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x28C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x290 "SPINLOCK_LOCK_REG_i_164,This register contains the state of one lock" hexmask.long 0x290 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x290 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x294 "SPINLOCK_LOCK_REG_i_165,This register contains the state of one lock" hexmask.long 0x294 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x294 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x298 "SPINLOCK_LOCK_REG_i_166,This register contains the state of one lock" hexmask.long 0x298 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x298 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x29C "SPINLOCK_LOCK_REG_i_167,This register contains the state of one lock" hexmask.long 0x29C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x29C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2A0 "SPINLOCK_LOCK_REG_i_168,This register contains the state of one lock" hexmask.long 0x2A0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2A0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2A4 "SPINLOCK_LOCK_REG_i_169,This register contains the state of one lock" hexmask.long 0x2A4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2A4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2A8 "SPINLOCK_LOCK_REG_i_170,This register contains the state of one lock" hexmask.long 0x2A8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2A8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2AC "SPINLOCK_LOCK_REG_i_171,This register contains the state of one lock" hexmask.long 0x2AC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2AC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2B0 "SPINLOCK_LOCK_REG_i_172,This register contains the state of one lock" hexmask.long 0x2B0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2B0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2B4 "SPINLOCK_LOCK_REG_i_173,This register contains the state of one lock" hexmask.long 0x2B4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2B4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2B8 "SPINLOCK_LOCK_REG_i_174,This register contains the state of one lock" hexmask.long 0x2B8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2B8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2BC "SPINLOCK_LOCK_REG_i_175,This register contains the state of one lock" hexmask.long 0x2BC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2BC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2C0 "SPINLOCK_LOCK_REG_i_176,This register contains the state of one lock" hexmask.long 0x2C0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2C4 "SPINLOCK_LOCK_REG_i_177,This register contains the state of one lock" hexmask.long 0x2C4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2C8 "SPINLOCK_LOCK_REG_i_178,This register contains the state of one lock" hexmask.long 0x2C8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2CC "SPINLOCK_LOCK_REG_i_179,This register contains the state of one lock" hexmask.long 0x2CC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2CC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2D0 "SPINLOCK_LOCK_REG_i_180,This register contains the state of one lock" hexmask.long 0x2D0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2D0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2D4 "SPINLOCK_LOCK_REG_i_181,This register contains the state of one lock" hexmask.long 0x2D4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2D4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2D8 "SPINLOCK_LOCK_REG_i_182,This register contains the state of one lock" hexmask.long 0x2D8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2D8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2DC "SPINLOCK_LOCK_REG_i_183,This register contains the state of one lock" hexmask.long 0x2DC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2DC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2E0 "SPINLOCK_LOCK_REG_i_184,This register contains the state of one lock" hexmask.long 0x2E0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2E0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2E4 "SPINLOCK_LOCK_REG_i_185,This register contains the state of one lock" hexmask.long 0x2E4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2E4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2E8 "SPINLOCK_LOCK_REG_i_186,This register contains the state of one lock" hexmask.long 0x2E8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2E8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2EC "SPINLOCK_LOCK_REG_i_187,This register contains the state of one lock" hexmask.long 0x2EC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2EC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2F0 "SPINLOCK_LOCK_REG_i_188,This register contains the state of one lock" hexmask.long 0x2F0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2F0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2F4 "SPINLOCK_LOCK_REG_i_189,This register contains the state of one lock" hexmask.long 0x2F4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2F4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2F8 "SPINLOCK_LOCK_REG_i_190,This register contains the state of one lock" hexmask.long 0x2F8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2F8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x2FC "SPINLOCK_LOCK_REG_i_191,This register contains the state of one lock" hexmask.long 0x2FC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x2FC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x300 "SPINLOCK_LOCK_REG_i_192,This register contains the state of one lock" hexmask.long 0x300 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x300 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x304 "SPINLOCK_LOCK_REG_i_193,This register contains the state of one lock" hexmask.long 0x304 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x304 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x308 "SPINLOCK_LOCK_REG_i_194,This register contains the state of one lock" hexmask.long 0x308 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x308 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x30C "SPINLOCK_LOCK_REG_i_195,This register contains the state of one lock" hexmask.long 0x30C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x30C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x310 "SPINLOCK_LOCK_REG_i_196,This register contains the state of one lock" hexmask.long 0x310 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x310 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x314 "SPINLOCK_LOCK_REG_i_197,This register contains the state of one lock" hexmask.long 0x314 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x314 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x318 "SPINLOCK_LOCK_REG_i_198,This register contains the state of one lock" hexmask.long 0x318 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x318 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x31C "SPINLOCK_LOCK_REG_i_199,This register contains the state of one lock" hexmask.long 0x31C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x31C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x320 "SPINLOCK_LOCK_REG_i_200,This register contains the state of one lock" hexmask.long 0x320 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x320 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x324 "SPINLOCK_LOCK_REG_i_201,This register contains the state of one lock" hexmask.long 0x324 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x324 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x328 "SPINLOCK_LOCK_REG_i_202,This register contains the state of one lock" hexmask.long 0x328 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x328 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x32C "SPINLOCK_LOCK_REG_i_203,This register contains the state of one lock" hexmask.long 0x32C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x32C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x330 "SPINLOCK_LOCK_REG_i_204,This register contains the state of one lock" hexmask.long 0x330 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x330 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x334 "SPINLOCK_LOCK_REG_i_205,This register contains the state of one lock" hexmask.long 0x334 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x334 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x338 "SPINLOCK_LOCK_REG_i_206,This register contains the state of one lock" hexmask.long 0x338 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x338 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x33C "SPINLOCK_LOCK_REG_i_207,This register contains the state of one lock" hexmask.long 0x33C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x33C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x340 "SPINLOCK_LOCK_REG_i_208,This register contains the state of one lock" hexmask.long 0x340 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x340 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x344 "SPINLOCK_LOCK_REG_i_209,This register contains the state of one lock" hexmask.long 0x344 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x344 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x348 "SPINLOCK_LOCK_REG_i_210,This register contains the state of one lock" hexmask.long 0x348 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x348 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x34C "SPINLOCK_LOCK_REG_i_211,This register contains the state of one lock" hexmask.long 0x34C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x34C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x350 "SPINLOCK_LOCK_REG_i_212,This register contains the state of one lock" hexmask.long 0x350 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x350 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x354 "SPINLOCK_LOCK_REG_i_213,This register contains the state of one lock" hexmask.long 0x354 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x354 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x358 "SPINLOCK_LOCK_REG_i_214,This register contains the state of one lock" hexmask.long 0x358 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x358 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x35C "SPINLOCK_LOCK_REG_i_215,This register contains the state of one lock" hexmask.long 0x35C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x35C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x360 "SPINLOCK_LOCK_REG_i_216,This register contains the state of one lock" hexmask.long 0x360 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x360 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x364 "SPINLOCK_LOCK_REG_i_217,This register contains the state of one lock" hexmask.long 0x364 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x364 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x368 "SPINLOCK_LOCK_REG_i_218,This register contains the state of one lock" hexmask.long 0x368 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x368 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x36C "SPINLOCK_LOCK_REG_i_219,This register contains the state of one lock" hexmask.long 0x36C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x36C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x370 "SPINLOCK_LOCK_REG_i_220,This register contains the state of one lock" hexmask.long 0x370 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x370 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x374 "SPINLOCK_LOCK_REG_i_221,This register contains the state of one lock" hexmask.long 0x374 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x374 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x378 "SPINLOCK_LOCK_REG_i_222,This register contains the state of one lock" hexmask.long 0x378 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x378 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x37C "SPINLOCK_LOCK_REG_i_223,This register contains the state of one lock" hexmask.long 0x37C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x37C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x380 "SPINLOCK_LOCK_REG_i_224,This register contains the state of one lock" hexmask.long 0x380 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x380 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x384 "SPINLOCK_LOCK_REG_i_225,This register contains the state of one lock" hexmask.long 0x384 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x384 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x388 "SPINLOCK_LOCK_REG_i_226,This register contains the state of one lock" hexmask.long 0x388 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x388 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x38C "SPINLOCK_LOCK_REG_i_227,This register contains the state of one lock" hexmask.long 0x38C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x38C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x390 "SPINLOCK_LOCK_REG_i_228,This register contains the state of one lock" hexmask.long 0x390 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x390 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x394 "SPINLOCK_LOCK_REG_i_229,This register contains the state of one lock" hexmask.long 0x394 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x394 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x398 "SPINLOCK_LOCK_REG_i_230,This register contains the state of one lock" hexmask.long 0x398 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x398 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x39C "SPINLOCK_LOCK_REG_i_231,This register contains the state of one lock" hexmask.long 0x39C 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x39C 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3A0 "SPINLOCK_LOCK_REG_i_232,This register contains the state of one lock" hexmask.long 0x3A0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3A0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3A4 "SPINLOCK_LOCK_REG_i_233,This register contains the state of one lock" hexmask.long 0x3A4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3A4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3A8 "SPINLOCK_LOCK_REG_i_234,This register contains the state of one lock" hexmask.long 0x3A8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3A8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3AC "SPINLOCK_LOCK_REG_i_235,This register contains the state of one lock" hexmask.long 0x3AC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3AC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3B0 "SPINLOCK_LOCK_REG_i_236,This register contains the state of one lock" hexmask.long 0x3B0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3B0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3B4 "SPINLOCK_LOCK_REG_i_237,This register contains the state of one lock" hexmask.long 0x3B4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3B4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3B8 "SPINLOCK_LOCK_REG_i_238,This register contains the state of one lock" hexmask.long 0x3B8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3B8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3BC "SPINLOCK_LOCK_REG_i_239,This register contains the state of one lock" hexmask.long 0x3BC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3BC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3C0 "SPINLOCK_LOCK_REG_i_240,This register contains the state of one lock" hexmask.long 0x3C0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3C4 "SPINLOCK_LOCK_REG_i_241,This register contains the state of one lock" hexmask.long 0x3C4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3C8 "SPINLOCK_LOCK_REG_i_242,This register contains the state of one lock" hexmask.long 0x3C8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3CC "SPINLOCK_LOCK_REG_i_243,This register contains the state of one lock" hexmask.long 0x3CC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3CC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3D0 "SPINLOCK_LOCK_REG_i_244,This register contains the state of one lock" hexmask.long 0x3D0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3D0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3D4 "SPINLOCK_LOCK_REG_i_245,This register contains the state of one lock" hexmask.long 0x3D4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3D4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3D8 "SPINLOCK_LOCK_REG_i_246,This register contains the state of one lock" hexmask.long 0x3D8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3D8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3DC "SPINLOCK_LOCK_REG_i_247,This register contains the state of one lock" hexmask.long 0x3DC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3DC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3E0 "SPINLOCK_LOCK_REG_i_248,This register contains the state of one lock" hexmask.long 0x3E0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3E0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3E4 "SPINLOCK_LOCK_REG_i_249,This register contains the state of one lock" hexmask.long 0x3E4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3E4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3E8 "SPINLOCK_LOCK_REG_i_250,This register contains the state of one lock" hexmask.long 0x3E8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3E8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3EC "SPINLOCK_LOCK_REG_i_251,This register contains the state of one lock" hexmask.long 0x3EC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3EC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3F0 "SPINLOCK_LOCK_REG_i_252,This register contains the state of one lock" hexmask.long 0x3F0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3F0 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3F4 "SPINLOCK_LOCK_REG_i_253,This register contains the state of one lock" hexmask.long 0x3F4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3F4 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3F8 "SPINLOCK_LOCK_REG_i_254,This register contains the state of one lock" hexmask.long 0x3F8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3F8 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" line.long 0x3FC "SPINLOCK_LOCK_REG_i_255,This register contains the state of one lock" hexmask.long 0x3FC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x3FC 0. "TAKEN,Lock State" "TAKEN_0_w,TAKEN_1_w" width 0x0B tree.end tree "SPINLOCK_TARG" base ad:0x4A0F7000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_H,Error reporting" line.long 0x14 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x14 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x14 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x14 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x14 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x14 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x14 0. "OCP_RESET,L3 Reset" "0,1" width 0x0B tree.end tree "SS" base ad:0x48484000 rgroup.long 0x00++0x37 line.long 0x00 "CPSW_ID_VER,CPSW_3G ID version register" line.long 0x04 "CPSW_CONTROL,Switch control register" hexmask.long 0x04 5.--31. 1. "RESERVED," bitfld.long 0x04 4. "EEE_EN,EEE (Energy Efficient Ethernet) enable 0 - EEE is disabled" "0,1" newline bitfld.long 0x04 3. "DLR_EN,DLR enable" "DLR is disabled,DLR is disabled" bitfld.long 0x04 2. "RX_VLAN_ENCAP,Port 0 VLAN Encapsulation (egress)" "Port 0 receive packets (from CPSW_3G) are not..,Port 0 receive packets (from CPSW_3G) are VLAN.." newline bitfld.long 0x04 1. "VLAN_AWARE,VLAN Aware Mode" "CPSW_3G is in the VLAN unaware mode,CPSW_3G is in the VLAN aware mode" bitfld.long 0x04 0. "FIFO_LOOPBACK,FIFO Loopback Mode" "Loopback is disabled,FIFO Loopback mode enabled" line.long 0x08 "CPSW_SOFT_RESET,Soft reset register" hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the 3G logic (INT REGS CPPI and SPF modules) to be reset" "0,1" line.long 0x0C "CPSW_STAT_PORT_EN,Statistics port enable register" hexmask.long 0x0C 3.--31. 1. "RESERVED," bitfld.long 0x0C 2. "P2_STAT_EN,Port 2 (GMII2 and Port 2 FIFO) Statistics Enable" "Port 2 statistics are not enabled,Port 2 statistics are enabled" newline bitfld.long 0x0C 1. "P1_STAT_EN,Port 1 (GMII1 and Port 1 FIFO) Statistics Enable" "Port 1 statistics are not enabled,Port 1 statistics are enabled" bitfld.long 0x0C 0. "P0_STAT_EN,Port 0 Statistics Enable" "Port 0 statistics are not enabled,Port 0 statistics are enabled" line.long 0x10 "CPSW_PTYPE,Transmit priority type register" hexmask.long.word 0x10 22.--31. 1. "RESERVED," bitfld.long 0x10 21. "P2_PRI3_SHAPE_EN,Port 2 Queue Priority 3 Transmit Shape Enable - If there is only one shaping queue then it must be priority 3" "0,1" newline bitfld.long 0x10 20. "P2_PRI2_SHAPE_EN,Port 2 Queue Priority 2 Transmit Shape Enable - If there are two shaping queues then they must be priorities 3 and 2" "0,1" bitfld.long 0x10 19. "P2_PRI1_SHAPE_EN,Port 2 Queue Priority 1 Transmit Shape Enable - If there are three shaping queues all three bits should be set" "0,1" newline bitfld.long 0x10 18. "P1_PRI3_SHAPE_EN,Port 1 Queue Priority 3 Transmit Shape Enable - If there is only one shaping queue then it must be priority 3" "0,1" bitfld.long 0x10 17. "P1_PRI2_SHAPE_EN,Port 1 Queue Priority 2 Transmit Shape Enable- If there are two shaping queues then they must be priorities 3 and 2" "0,1" newline bitfld.long 0x10 16. "P1_PRI1_SHAPE_EN,Port 1 Queue Priority 1 Transmit Shape Enable- If there are three shaping queues all three bits should be set" "0,1" rbitfld.long 0x10 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x10 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate" "Port 2 priority type fixed,Port 2 priority type escalate Escalate should.." bitfld.long 0x10 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate" "Port 1 priority type fixed,Port 1 priority type escalate Escalate should.." newline bitfld.long 0x10 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate" "Port 0 priority type fixed,Port 0 priority type escalate Escalate should.." rbitfld.long 0x10 5.--7. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--4. "ESC_PRI_LD_VAL,Escalate Priority Load Value When a port is in escalate priority this is the number of higher priority packets sent before the next lower priority is allowed to send a packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "CPSW_SOFT_IDLE,Software idle" hexmask.long 0x14 1.--31. 1. "RESERVED," bitfld.long 0x14 0. "SOFT_IDLE,Software Idle - Setting this bit causes the switch fabric to stop forwarding packets at the next start of packet" "0,1" line.long 0x18 "CPSW_THRU_RATE,Throughput rate" hexmask.long.word 0x18 16.--31. 1. "RESERVED," bitfld.long 0x18 12.--15. "SL_RX_THRU_RATE,CPGMAC_SL Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x18 4.--11. 1. "RESERVED," bitfld.long 0x18 0.--3. "CPDMA_THRU_RATE,CPDMA Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "CPSW_GAP_THRESH,CPGMAC_SL short gap threshold" hexmask.long 0x1C 5.--31. 1. "RESERVED," bitfld.long 0x1C 0.--4. "GAP_THRESH,CPGMAC_SL Short Gap Threshold - This is the CPGMAC_SL associated FIFO transmit block usage value for triggering TX_SHORT_GAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "CPSW_TX_START_WDS,Transmit start words" hexmask.long.tbyte 0x20 11.--31. 1. "RESERVED," hexmask.long.word 0x20 0.--10. 1. "TX_START_WDS,FIFO Packet Transmit (egress) Start Words" line.long 0x24 "CPSW_FLOW_CONTROL,Flow control" hexmask.long 0x24 3.--31. 1. "RESERVED," bitfld.long 0x24 2. "P2_FLOW_EN,Port 2 Receive flow control enable" "0,1" newline bitfld.long 0x24 1. "P1_FLOW_EN,Port 1 Receive flow control enable" "0,1" bitfld.long 0x24 0. "P0_FLOW_EN,Port 0 Receive flow control enable" "0,1" line.long 0x28 "CPSW_VLAN_LTYPE,LTYPE1 and LTYPE 2 Register" hexmask.long.word 0x28 16.--31. 1. "VLAN_LTYPE2,Time Sync VLAN LTYPE2 This VLAN LTYPE value is used for tx and rx" hexmask.long.word 0x28 0.--15. 1. "VLAN_LTYPE1,Time Sync VLAN LTYPE1 This VLAN LTYPE value is used for tx and rx" line.long 0x2C "CPSW_TS_LTYPE,VLAN_LTYPE1 and VLAN_LTYPE2 Register" hexmask.long.word 0x2C 16.--31. 1. "TS_LTYPE2,Time Sync LTYPE2 This is an Ethertype value to match for tx and rx time sync packets" hexmask.long.word 0x2C 0.--15. 1. "TS_LTYPE1,Time Sync LTYPE1 This is an ethertype value to match for tx and rx time sync packets" line.long 0x30 "CPSW_DLR_LTYPE,DLR LTYPE register" hexmask.long.word 0x30 16.--31. 1. "RESERVED," hexmask.long.word 0x30 0.--15. 1. "DLR_LTYPE,DLR LTYPE" line.long 0x34 "CPSW_EEE_PRESCALE,EEE Pre-scale Counter Load Value Register" hexmask.long.tbyte 0x34 12.--31. 1. "RESERVED," hexmask.long.word 0x34 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value - This value is loaded into the EEE pre-scale counter each time the pre-scale count decrements to zero" width 0x0B tree.end tree "STATERAM" base ad:0x48484A00 group.long 0x00++0x7F line.long 0x00 "TX0_HDP,CPDMA_STATERAM TX channel 0 head descriptor pointer" line.long 0x04 "TX1_HDP,CPDMA_STATERAM TX channel 1 head descriptor pointer" line.long 0x08 "TX2_HDP,CPDMA_STATERAM TX channel 2 head descriptor pointer" line.long 0x0C "TX3_HDP,CPDMA_STATERAM TX channel 3 head descriptor pointer" line.long 0x10 "TX4_HDP,CPDMA_STATERAM TX channel 4 head descriptor pointer" line.long 0x14 "TX5_HDP,CPDMA_STATERAM TX channel 5 head descriptor pointer" line.long 0x18 "TX6_HDP,CPDMA_STATERAM TX channel 6 head descriptor pointer" line.long 0x1C "TX7_HDP,CPDMA_STATERAM TX channel 7 head descriptor pointer" line.long 0x20 "RX0_HDP,CPDMA_STATERAM RX 0 channel 0 head descriptor pointer" line.long 0x24 "RX1_HDP,CPDMA_STATERAM RX 1 channel 1 head descriptor pointer" line.long 0x28 "RX2_HDP,CPDMA_STATERAM RX 2 channel 2 head descriptor pointer" line.long 0x2C "RX3_HDP,CPDMA_STATERAM RX 3 channel 3 head descriptor pointer" line.long 0x30 "RX4_HDP,CPDMA_STATERAM RX 4 channel 4 head descriptor pointer" line.long 0x34 "RX5_HDP,CPDMA_STATERAM RX 5 channel 5 head descriptor pointer" line.long 0x38 "RX6_HDP,CPDMA_STATERAM RX 6 channel 6 head desc pointer" line.long 0x3C "RX7_HDP,CPDMA_STATERAM RX 7 channel 7 head desc pointer" line.long 0x40 "TX0_CP,CPDMA_STATERAM TX channel 0 completion pointer register" line.long 0x44 "TX1_CP,CPDMA_STATERAM TX channel 1 completion pointer register" line.long 0x48 "TX2_CP,CPDMA_STATERAM TX channel 2 completion pointer register" line.long 0x4C "TX3_CP,CPDMA_STATERAM TX channel 3 completion pointer register" line.long 0x50 "TX4_CP,CPDMA_STATERAM TX channel 4 completion pointer register" line.long 0x54 "TX5_CP,CPDMA_STATERAM TX channel 5 completion pointer register" line.long 0x58 "TX6_CP,CPDMA_STATERAM TX channel 6 completion pointer register" line.long 0x5C "TX7_CP,CPDMA_STATERAM TX channel 7 completion pointer register" line.long 0x60 "RX0_CP,CPDMA_STATERAM RX channel 0 completion pointer register" line.long 0x64 "RX1_CP,CPDMA_STATERAM RX channel 1 completion pointer register" line.long 0x68 "RX2_CP,CPDMA_STATERAM RX channel 2 completion pointer register" line.long 0x6C "RX3_CP,CPDMA_STATERAM RX channel 3 completion pointer register" line.long 0x70 "RX4_CP,CPDMA_STATERAM RX channel 4 completion pointer register" line.long 0x74 "RX5_CP,CPDMA_STATERAM RX channel 5 completion pointer register" line.long 0x78 "RX6_CP,CPDMA_STATERAM RX channel 6 completion pointer register" line.long 0x7C "RX7_CP,CPDMA_STATERAM RX channel 7 completion pointer register" width 0x0B tree.end tree "STATS" base ad:0x48484900 group.long 0x00++0x27 line.long 0x00 "GOOD_RX_FRAMES,The total number of good frames received on the port" line.long 0x04 "BROADCAST_RX_FRAMES,The total number of good broadcast frames received on the port" line.long 0x08 "MULTICAST_RX_FRAMES,The total number of good multicast frames received on the port" line.long 0x0C "PAUSE_RX_FRAMES,The total number of IEEE 802.3X pause frames received by the port (whether acted upon or not)" line.long 0x10 "RX_CRC_ERRORS,The total number of frames received on the port that experienced a CRC error" line.long 0x14 "RX_ALIGN_CODE_ERRORS,The total number of frames received on the port that experienced an alignment error or code error" line.long 0x18 "OVERSIZE_RX_FRAMES,The total number of oversized frames received on the port" line.long 0x1C "RX_JABBERS,The total number of jabber frames received on the port" line.long 0x20 "UNDERSIZE_RX_FRAMES,The total number of undersized frames received on the port" line.long 0x24 "RX_FRAGMENTS,The total number of frame fragments received on the port" group.long 0x30++0x5F line.long 0x00 "RX_OCTETS,The total number of bytes in all good frames received on the port" line.long 0x04 "GOOD_TX_FRAMES,The total number of good frames received on the port" line.long 0x08 "BROADCAST_TX_FRAMES,The total number of good broadcast frames received on the port" line.long 0x0C "MULTICAST_TX_FRAMES,The total number of good multicast frames received on the port" line.long 0x10 "PAUSE_TX_FRAMES,This statistic indicates the number of IEEE 802.3X pause frames transmitted by the port" line.long 0x14 "DEFERRED_TX_FRAMES,The total number of frames transmitted on the port that first experienced deferment" line.long 0x18 "COLLISIONS,This statistic records the total number of times that the port experienced a collision" line.long 0x1C "SINGLE_COLLISION_TX_FRAMES,The total number of frames transmitted on the port that experienced exactly one collision" line.long 0x20 "MULTIPLE_COLLISION_TX_FRAMES,The total number of frames transmitted on the port that experienced multiple collisions" line.long 0x24 "EXCESSIVE_COLLISIONS,The total number of frames for which transmission was abandoned due to excessive collisions" line.long 0x28 "LATE_COLLISIONS,The total number of frames on the port for which transmission was abandoned because they experienced a late collision" line.long 0x2C "TX_UNDERRUN,There should be no transmitted frames that experience underrun" line.long 0x30 "CARRIER_SENSE_ERRORS,The total number of frames received on the port that had a CPDMA middle of frame (MOF) overrun" line.long 0x34 "TX_OCTETS,The total number of bytes in all good frames transmitted on the port" line.long 0x38 "RX_TX_64_OCTET_FRAMES,The total number of 64-byte frames received and transmitted on the port" line.long 0x3C "RX_TX_65_127_OCTET_FRAMES,The total number of frames of size 65 to 127 bytes received and transmitted on the port" line.long 0x40 "RX_TX_128_255_OCTET_FRAMES,The total number of frames of size 128 to 255 bytes received and transmitted on the port" line.long 0x44 "RX_TX_256_511_OCTET_FRAMES,The total number of frames of size 256 to 511 bytes received and transmitted on the port" line.long 0x48 "RX_TX_512_1023_OCTET_FRAMES,The total number of frames of size 512 to 1023 bytes received and transmitted on the port" line.long 0x4C "RX_TX_1024_UP_OCTET_FRAMES,The total number of frames of size 1024 to[13:0] RX_MAXLEN bytes for receive or 1024 up for transmit on the port" line.long 0x50 "NET_OCTETS,The total number of bytes of frame data received and transmitted on the port" line.long 0x54 "RX_START_OF_FRAME_OVERRUNS,The total number of frames received on the port that had a CPDMA start of frame (SOF) overrun or were dropped by due to FIFO resource limitations. or were dropped by the SPF" line.long 0x58 "RX_MIDDLE_OF_FRAME_OVERRUNS,The total number of frames received on the port that had a CPDMA middle of frame (MOF) overrun" line.long 0x5C "RX_DMA_OVERRUNS,The total number of frames received on the port that had either a DMA start of frame (SOF) overrun or a DMA MOF overrun" width 0x0B tree.end tree "SYS_EDMA_TPCC" base ad:0x43300000 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x04 26.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x04 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" newline rbitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x04 22.--23. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x04 19. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x04 15. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x04 11. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7" group.long 0xFC++0x113 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" line.long 0x04 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x04 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x08 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x08 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x0C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x10 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x14 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x18 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x1C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" hexmask.long.tbyte 0x20 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x20 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" hexmask.long.tbyte 0x24 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x24 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" hexmask.long.tbyte 0x28 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x28 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x28 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x2C "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.tbyte 0x2C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x2C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x2C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" hexmask.long.tbyte 0x30 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x30 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x30 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" hexmask.long.tbyte 0x34 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x34 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x34 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x38 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" hexmask.long.tbyte 0x38 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x38 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x38 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x3C "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" hexmask.long.tbyte 0x3C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x3C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x3C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" hexmask.long.tbyte 0x40 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x40 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x40 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x44 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" hexmask.long.tbyte 0x44 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x44 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x44 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x48 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" hexmask.long.tbyte 0x48 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x48 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x48 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x4C "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" hexmask.long.tbyte 0x4C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x4C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" hexmask.long.tbyte 0x50 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x50 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x50 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x54 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" hexmask.long.tbyte 0x54 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x54 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x54 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x58 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" hexmask.long.tbyte 0x58 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x58 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x58 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x5C "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" hexmask.long.tbyte 0x5C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x5C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x5C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x60 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" hexmask.long.tbyte 0x60 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x60 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x60 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x64 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" hexmask.long.tbyte 0x64 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x64 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x64 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x68 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" hexmask.long.tbyte 0x68 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x68 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x68 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x6C "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" hexmask.long.tbyte 0x6C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x6C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x6C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x70 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" hexmask.long.tbyte 0x70 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x70 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x70 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x74 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" hexmask.long.tbyte 0x74 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x74 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x74 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x78 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" hexmask.long.tbyte 0x78 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x78 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x78 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x7C "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" hexmask.long.tbyte 0x7C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x7C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x7C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x80 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" hexmask.long.tbyte 0x80 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x80 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x80 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x84 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" hexmask.long.tbyte 0x84 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x84 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x84 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x88 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" hexmask.long.tbyte 0x88 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x88 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x88 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x8C "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" hexmask.long.tbyte 0x8C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x8C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x8C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x90 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" hexmask.long.tbyte 0x90 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x90 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x90 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x94 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" hexmask.long.tbyte 0x94 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x94 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x94 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x98 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" hexmask.long.tbyte 0x98 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x98 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x98 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x9C "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" hexmask.long.tbyte 0x9C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x9C 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x9C 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA0 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA4 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xA8 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" hexmask.long.tbyte 0xA8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xA8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xA8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xAC "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" hexmask.long.tbyte 0xAC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xAC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xAC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB0 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB4 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xB8 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" hexmask.long.tbyte 0xB8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xB8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xB8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xBC "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" hexmask.long.tbyte 0xBC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xBC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xBC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC0 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC4 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xC8 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" hexmask.long.tbyte 0xC8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xC8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xCC "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" hexmask.long.tbyte 0xCC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xCC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xCC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD0 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD4 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xD8 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" hexmask.long.tbyte 0xD8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xD8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xD8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xDC "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" hexmask.long.tbyte 0xDC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xDC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xDC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE0 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE4 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xE8 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" hexmask.long.tbyte 0xE8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xE8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xE8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xEC "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" hexmask.long.tbyte 0xEC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xEC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xEC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF0 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF0 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF0 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF4 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF4 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF4 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF4 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xF8 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" hexmask.long.tbyte 0xF8 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xF8 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xF8 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0xFC "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" hexmask.long.tbyte 0xFC 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xFC 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0xFC 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x100 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" hexmask.long.tbyte 0x100 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x100 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" newline rbitfld.long 0x100 0.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x104 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x104 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x104 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x104 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x104 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x108 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x108 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x108 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x108 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x108 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x10C "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x10C 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10C 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x10C 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x10C 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x110 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x110 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x110 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" newline bitfld.long 0x110 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" rbitfld.long 0x110 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x240++0x23 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x00 31. "RESERVED,Reserved" "0,1" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 27. "RESERVED,Reserved" "0,1" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 23. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 19. "RESERVED,Reserved" "0,1" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 15. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x04 31. "RESERVED,Reserved" "0,1" bitfld.long 0x04 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 27. "RESERVED,Reserved" "0,1" bitfld.long 0x04 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 23. "RESERVED,Reserved" "0,1" bitfld.long 0x04 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 19. "RESERVED,Reserved" "0,1" bitfld.long 0x04 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 15. "RESERVED,Reserved" "0,1" bitfld.long 0x04 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 11. "RESERVED,Reserved" "0,1" bitfld.long 0x04 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 7. "RESERVED,Reserved" "0,1" bitfld.long 0x04 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x08 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x08 31. "RESERVED,Reserved" "0,1" bitfld.long 0x08 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 27. "RESERVED,Reserved" "0,1" bitfld.long 0x08 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 23. "RESERVED,Reserved" "0,1" bitfld.long 0x08 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 19. "RESERVED,Reserved" "0,1" bitfld.long 0x08 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 15. "RESERVED,Reserved" "0,1" bitfld.long 0x08 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 11. "RESERVED,Reserved" "0,1" bitfld.long 0x08 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 7. "RESERVED,Reserved" "0,1" bitfld.long 0x08 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 3. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x0C "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x0C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x0C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x10 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x10 31. "RESERVED,Reserved" "0,1" bitfld.long 0x10 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED,Reserved" "0,1" bitfld.long 0x10 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED,Reserved" "0,1" bitfld.long 0x10 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "RESERVED,Reserved" "0,1" bitfld.long 0x10 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 15. "RESERVED,Reserved" "0,1" bitfld.long 0x10 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 11. "RESERVED,Reserved" "0,1" bitfld.long 0x10 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" bitfld.long 0x10 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 3. "RESERVED,Reserved" "0,1" bitfld.long 0x10 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x14 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x14 31. "RESERVED,Reserved" "0,1" bitfld.long 0x14 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 27. "RESERVED,Reserved" "0,1" bitfld.long 0x14 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED,Reserved" "0,1" bitfld.long 0x14 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "RESERVED,Reserved" "0,1" bitfld.long 0x14 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RESERVED,Reserved" "0,1" bitfld.long 0x14 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" bitfld.long 0x14 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 3. "RESERVED,Reserved" "0,1" bitfld.long 0x14 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x18 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x18 31. "RESERVED,Reserved" "0,1" bitfld.long 0x18 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 27. "RESERVED,Reserved" "0,1" bitfld.long 0x18 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 23. "RESERVED,Reserved" "0,1" bitfld.long 0x18 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 19. "RESERVED,Reserved" "0,1" bitfld.long 0x18 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 15. "RESERVED,Reserved" "0,1" bitfld.long 0x18 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 11. "RESERVED,Reserved" "0,1" bitfld.long 0x18 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 7. "RESERVED,Reserved" "0,1" bitfld.long 0x18 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 3. "RESERVED,Reserved" "0,1" bitfld.long 0x18 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x1C "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" rbitfld.long 0x1C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 27. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 3. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" line.long 0x20 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" rbitfld.long 0x20 31. "RESERVED," "0,1" bitfld.long 0x20 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 27. "RESERVED," "0,1" bitfld.long 0x20 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 23. "RESERVED," "0,1" bitfld.long 0x20 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 19. "RESERVED," "0,1" bitfld.long 0x20 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 15. "RESERVED," "0,1" bitfld.long 0x20 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 11. "RESERVED," "0,1" bitfld.long 0x20 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 7. "RESERVED," "0,1" bitfld.long 0x20 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 3. "RESERVED," "0,1" bitfld.long 0x20 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x280++0x07 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 3. "RESERVED,Reserved" "0,1" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_QUEPRI,Queue Priority" hexmask.long 0x04 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 3. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" rgroup.long 0x300++0x23 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" newline bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" newline bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" newline bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" newline bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" newline bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" newline bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" newline bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" newline bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" newline bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" newline bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" newline bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" newline bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" newline bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" newline bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" newline bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" newline bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" newline bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" newline bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" newline bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" newline bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" line.long 0x08 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1" newline bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1" bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1" newline bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1" newline bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1" bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1" newline bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1" newline bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1" bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1" newline bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1" newline bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1" bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1" newline bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1" newline bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1" bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1" newline bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1" line.long 0x0C "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1" bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1" bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1" bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1" bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1" bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1" line.long 0x10 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,Event Missed #7" "0,1" newline bitfld.long 0x10 6. "E6,Event Missed #6" "0,1" bitfld.long 0x10 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x10 4. "E4,Event Missed #4" "0,1" bitfld.long 0x10 3. "E3,Event Missed #3" "0,1" newline bitfld.long 0x10 2. "E2,Event Missed #2" "0,1" bitfld.long 0x10 1. "E1,Event Missed #1" "0,1" newline bitfld.long 0x10 0. "E0,Event Missed #0" "0,1" line.long 0x14 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1" newline bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1" newline bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1" bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1" newline bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1" line.long 0x18 "EDMA_TPCC_CCERR,CC Error Register" hexmask.long.word 0x18 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 16. "TCERR,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register" "TCERR_0,TCERR_1" newline hexmask.long.byte 0x18 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD7_0,QTHRXCD7_1" newline bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD6_0,QTHRXCD6_1" bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD5_0,QTHRXCD5_1" newline bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD4_0,QTHRXCD4_1" bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD3_0,QTHRXCD3_1" newline bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD1_0,QTHRXCD1_1" newline bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x1C "EDMA_TPCC_CCERRCLR,CC Error Clear Register" hexmask.long.word 0x1C 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR" "0,1" newline hexmask.long.byte 0x1C 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect" "0,1" bitfld.long 0x1C 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect" "0,1" bitfld.long 0x1C 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" newline bitfld.long 0x1C 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect" "0,1" bitfld.long 0x1C 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" newline bitfld.long 0x1C 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect" "0,1" line.long 0x20 "EDMA_TPCC_EEVAL,Error Eval Register" hexmask.long 0x20 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 1. "SET,Error Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x20 0. "EVAL,Error Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x348++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x350++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x358++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x360++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x368++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x370++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x378++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x344++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x34C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x354++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x35C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x364++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x36C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x374++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x37C++0x23 line.long 0x00 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" line.long 0x04 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x04 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x04 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x04 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x04 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x04 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x04 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x04 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x08 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x08 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x08 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x08 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x08 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x08 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x08 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x08 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x0C "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x0C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x0C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x0C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x0C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x0C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x0C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x0C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x10 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x10 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x10 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x10 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x10 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x10 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x10 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x10 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x14 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x14 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x14 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x14 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x14 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x14 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x14 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x14 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x18 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x18 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x18 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x18 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x18 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x18 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x18 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x18 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x1C "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x1C 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x1C 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x1C 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x1C 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x1C 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x1C 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x1C 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" line.long 0x20 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En =" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x20 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x20 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x20 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x20 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x20 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x20 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x20 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" rgroup.long 0x400++0x7F line.long 0x00 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x04 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x08 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x10 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x14 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x18 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x1C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x20 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x24 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x28 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x2C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x30 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x30 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x30 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x34 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x34 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x38 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x38 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x3C "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x3C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x40 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x40 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x44 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x44 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x44 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x48 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x48 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x48 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x4C "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x4C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x4C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x50 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x50 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x50 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x54 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x54 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x54 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x54 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x58 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x58 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x58 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x58 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x5C "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x5C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x5C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x5C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x60 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x60 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x60 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x60 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x64 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x64 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x64 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x64 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x68 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x68 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x68 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x68 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x6C "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x6C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x6C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x6C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x70 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x70 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x70 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x70 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x74 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x74 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x74 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x74 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x78 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x78 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x78 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x78 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x7C "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue" hexmask.long.tbyte 0x7C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x7C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" newline bitfld.long 0x7C 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x600++0x07 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" hexmask.long.byte 0x00 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" line.long 0x04 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" hexmask.long.byte 0x04 25.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 24. "THRXCD,Threshold ExceededTHRXCD is cleared via" "THRXCD_0,THRXCD_1" newline bitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" rbitfld.long 0x00 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" rbitfld.long 0x04 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x04 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,reads return 0's" rbitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" newline rbitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" rbitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" newline rbitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" rbitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" newline bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2" rbitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" newline rbitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 14.--15. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" rbitfld.long 0x00 5.--7. "RESERVED,reads return 0's" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" rbitfld.long 0x00 3. "RESERVED,reads return 0's" "0,1" newline bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.." rbitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" newline rbitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" group.long 0x700++0x0B line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" hexmask.long.tbyte 0x00 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" line.long 0x08 "EDMA_TPCC_AETCMD,AET Command" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "CLR,AET Clear commandCPU writes 0x0 has no effect" "0,1" rgroup.long 0x800++0x2F line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" line.long 0x04 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" newline rbitfld.long 0x04 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" rbitfld.long 0x04 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" newline rbitfld.long 0x04 2. "URE,User Read Error" "URE_0,URE_1" rbitfld.long 0x04 1. "UWE,User Write Error" "UWE_0,UWE_1" newline rbitfld.long 0x04 0. "UXE,User Execute Error" "UXE_0,UXE_1" line.long 0x08 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" hexmask.long 0x08 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" line.long 0x0C "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" hexmask.long.word 0x0C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x0C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x0C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x0C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x0C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x0C 10. "AID0,Allowed ID 0" "AID0_0,AID0_1" bitfld.long 0x0C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x0C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x0C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x0C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x0C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x0C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x0C 0. "UX,User Execute permission" "UX_0,UX_1" line.long 0x10 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x10 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x10 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x10 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x10 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x10 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x10 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x10 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x10 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x10 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x10 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x10 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x10 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x10 0. "UX,User Execute permission" "UX_0,?" line.long 0x14 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x14 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x14 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x14 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x14 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x14 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x14 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x14 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x14 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x14 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x14 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x14 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x14 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x14 0. "UX,User Execute permission" "UX_0,?" line.long 0x18 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x18 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x18 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x18 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x18 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x18 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x18 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x18 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x18 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x18 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x18 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x18 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x18 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x18 0. "UX,User Execute permission" "UX_0,?" line.long 0x1C "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x1C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x1C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x1C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x1C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x1C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x1C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x1C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x1C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x1C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x1C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x1C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x1C 0. "UX,User Execute permission" "UX_0,?" line.long 0x20 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x20 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x20 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x20 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x20 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x20 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x20 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x20 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x20 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x20 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x20 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x20 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x20 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x20 0. "UX,User Execute permission" "UX_0,?" line.long 0x24 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x24 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x24 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x24 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x24 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x24 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x24 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x24 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x24 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x24 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x24 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x24 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x24 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x24 0. "UX,User Execute permission" "UX_0,?" line.long 0x28 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" hexmask.long.word 0x28 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x28 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x28 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x28 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x28 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x28 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x28 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x28 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x28 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x28 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x28 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x28 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x28 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x28 0. "UX,User Execute permission" "UX_0,?" line.long 0x2C "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" hexmask.long.word 0x2C 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 15. "AID5,Allowed ID 5" "AID5_0,AID5_1" newline bitfld.long 0x2C 14. "AID4,Allowed ID 4" "AID4_0,AID4_1" bitfld.long 0x2C 13. "AID3,Allowed ID 3" "AID3_0,AID3_1" newline bitfld.long 0x2C 12. "AID2,Allowed ID 2" "AID2_0,AID2_1" bitfld.long 0x2C 11. "AID1,Allowed ID 1" "AID1_0,AID1_1" newline bitfld.long 0x2C 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x2C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" newline rbitfld.long 0x2C 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x2C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x2C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x2C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x2C 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x2C 0. "UX,User Execute permission" "UX_0,?" rgroup.long 0x1000++0x47 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" newline bitfld.long 0x04 29. "E61,Event #61" "0,1" bitfld.long 0x04 28. "E60,Event #60" "0,1" newline bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" newline bitfld.long 0x04 23. "E55,Event #55" "0,1" bitfld.long 0x04 22. "E54,Event #54" "0,1" newline bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" newline bitfld.long 0x04 17. "E49,Event #49" "0,1" bitfld.long 0x04 16. "E48,Event #48" "0,1" newline bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" newline bitfld.long 0x04 11. "E43,Event #43" "0,1" bitfld.long 0x04 10. "E42,Event #42" "0,1" newline bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" newline bitfld.long 0x04 5. "E37,Event #37" "0,1" bitfld.long 0x04 4. "E36,Event #36" "0,1" newline bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" line.long 0x08 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event #31" "0,1" bitfld.long 0x08 30. "E30,Event #30" "0,1" newline bitfld.long 0x08 29. "E29,Event #29" "0,1" bitfld.long 0x08 28. "E28,Event #28" "0,1" newline bitfld.long 0x08 27. "E27,Event #27" "0,1" bitfld.long 0x08 26. "E26,Event #26" "0,1" newline bitfld.long 0x08 25. "E25,Event #25" "0,1" bitfld.long 0x08 24. "E24,Event #24" "0,1" newline bitfld.long 0x08 23. "E23,Event #23" "0,1" bitfld.long 0x08 22. "E22,Event #22" "0,1" newline bitfld.long 0x08 21. "E21,Event #21" "0,1" bitfld.long 0x08 20. "E20,Event #20" "0,1" newline bitfld.long 0x08 19. "E19,Event #19" "0,1" bitfld.long 0x08 18. "E18,Event #18" "0,1" newline bitfld.long 0x08 17. "E17,Event #17" "0,1" bitfld.long 0x08 16. "E16,Event #16" "0,1" newline bitfld.long 0x08 15. "E15,Event #15" "0,1" bitfld.long 0x08 14. "E14,Event #14" "0,1" newline bitfld.long 0x08 13. "E13,Event #13" "0,1" bitfld.long 0x08 12. "E12,Event #12" "0,1" newline bitfld.long 0x08 11. "E11,Event #11" "0,1" bitfld.long 0x08 10. "E10,Event #10" "0,1" newline bitfld.long 0x08 9. "E9,Event #9" "0,1" bitfld.long 0x08 8. "E8,Event #8" "0,1" newline bitfld.long 0x08 7. "E7,Event #7" "0,1" bitfld.long 0x08 6. "E6,Event #6" "0,1" newline bitfld.long 0x08 5. "E5,Event #5" "0,1" bitfld.long 0x08 4. "E4,Event #4" "0,1" newline bitfld.long 0x08 3. "E3,Event #3" "0,1" bitfld.long 0x08 2. "E2,Event #2" "0,1" newline bitfld.long 0x08 1. "E1,Event #1" "0,1" bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event #63" "0,1" bitfld.long 0x0C 30. "E62,Event #62" "0,1" newline bitfld.long 0x0C 29. "E61,Event #61" "0,1" bitfld.long 0x0C 28. "E60,Event #60" "0,1" newline bitfld.long 0x0C 27. "E59,Event #59" "0,1" bitfld.long 0x0C 26. "E58,Event #58" "0,1" newline bitfld.long 0x0C 25. "E57,Event #57" "0,1" bitfld.long 0x0C 24. "E56,Event #56" "0,1" newline bitfld.long 0x0C 23. "E55,Event #55" "0,1" bitfld.long 0x0C 22. "E54,Event #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event #53" "0,1" bitfld.long 0x0C 20. "E52,Event #52" "0,1" newline bitfld.long 0x0C 19. "E51,Event #51" "0,1" bitfld.long 0x0C 18. "E50,Event #50" "0,1" newline bitfld.long 0x0C 17. "E49,Event #49" "0,1" bitfld.long 0x0C 16. "E48,Event #48" "0,1" newline bitfld.long 0x0C 15. "E47,Event #47" "0,1" bitfld.long 0x0C 14. "E46,Event #46" "0,1" newline bitfld.long 0x0C 13. "E45,Event #45" "0,1" bitfld.long 0x0C 12. "E44,Event #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event #43" "0,1" bitfld.long 0x0C 10. "E42,Event #42" "0,1" newline bitfld.long 0x0C 9. "E41,Event #41" "0,1" bitfld.long 0x0C 8. "E40,Event #40" "0,1" newline bitfld.long 0x0C 7. "E39,Event #39" "0,1" bitfld.long 0x0C 6. "E38,Event #38" "0,1" newline bitfld.long 0x0C 5. "E37,Event #37" "0,1" bitfld.long 0x0C 4. "E36,Event #36" "0,1" newline bitfld.long 0x0C 3. "E35,Event #35" "0,1" bitfld.long 0x0C 2. "E34,Event #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event #33" "0,1" bitfld.long 0x0C 0. "E32,Event #32" "0,1" line.long 0x10 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x10 31. "E31,Event #31" "0,1" bitfld.long 0x10 30. "E30,Event #30" "0,1" newline bitfld.long 0x10 29. "E29,Event #29" "0,1" bitfld.long 0x10 28. "E28,Event #28" "0,1" newline bitfld.long 0x10 27. "E27,Event #27" "0,1" bitfld.long 0x10 26. "E26,Event #26" "0,1" newline bitfld.long 0x10 25. "E25,Event #25" "0,1" bitfld.long 0x10 24. "E24,Event #24" "0,1" newline bitfld.long 0x10 23. "E23,Event #23" "0,1" bitfld.long 0x10 22. "E22,Event #22" "0,1" newline bitfld.long 0x10 21. "E21,Event #21" "0,1" bitfld.long 0x10 20. "E20,Event #20" "0,1" newline bitfld.long 0x10 19. "E19,Event #19" "0,1" bitfld.long 0x10 18. "E18,Event #18" "0,1" newline bitfld.long 0x10 17. "E17,Event #17" "0,1" bitfld.long 0x10 16. "E16,Event #16" "0,1" newline bitfld.long 0x10 15. "E15,Event #15" "0,1" bitfld.long 0x10 14. "E14,Event #14" "0,1" newline bitfld.long 0x10 13. "E13,Event #13" "0,1" bitfld.long 0x10 12. "E12,Event #12" "0,1" newline bitfld.long 0x10 11. "E11,Event #11" "0,1" bitfld.long 0x10 10. "E10,Event #10" "0,1" newline bitfld.long 0x10 9. "E9,Event #9" "0,1" bitfld.long 0x10 8. "E8,Event #8" "0,1" newline bitfld.long 0x10 7. "E7,Event #7" "0,1" bitfld.long 0x10 6. "E6,Event #6" "0,1" newline bitfld.long 0x10 5. "E5,Event #5" "0,1" bitfld.long 0x10 4. "E4,Event #4" "0,1" newline bitfld.long 0x10 3. "E3,Event #3" "0,1" bitfld.long 0x10 2. "E2,Event #2" "0,1" newline bitfld.long 0x10 1. "E1,Event #1" "0,1" bitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x14 31. "E63,Event #63" "0,1" bitfld.long 0x14 30. "E62,Event #62" "0,1" newline bitfld.long 0x14 29. "E61,Event #61" "0,1" bitfld.long 0x14 28. "E60,Event #60" "0,1" newline bitfld.long 0x14 27. "E59,Event #59" "0,1" bitfld.long 0x14 26. "E58,Event #58" "0,1" newline bitfld.long 0x14 25. "E57,Event #57" "0,1" bitfld.long 0x14 24. "E56,Event #56" "0,1" newline bitfld.long 0x14 23. "E55,Event #55" "0,1" bitfld.long 0x14 22. "E54,Event #54" "0,1" newline bitfld.long 0x14 21. "E53,Event #53" "0,1" bitfld.long 0x14 20. "E52,Event #52" "0,1" newline bitfld.long 0x14 19. "E51,Event #51" "0,1" bitfld.long 0x14 18. "E50,Event #50" "0,1" newline bitfld.long 0x14 17. "E49,Event #49" "0,1" bitfld.long 0x14 16. "E48,Event #48" "0,1" newline bitfld.long 0x14 15. "E47,Event #47" "0,1" bitfld.long 0x14 14. "E46,Event #46" "0,1" newline bitfld.long 0x14 13. "E45,Event #45" "0,1" bitfld.long 0x14 12. "E44,Event #44" "0,1" newline bitfld.long 0x14 11. "E43,Event #43" "0,1" bitfld.long 0x14 10. "E42,Event #42" "0,1" newline bitfld.long 0x14 9. "E41,Event #41" "0,1" bitfld.long 0x14 8. "E40,Event #40" "0,1" newline bitfld.long 0x14 7. "E39,Event #39" "0,1" bitfld.long 0x14 6. "E38,Event #38" "0,1" newline bitfld.long 0x14 5. "E37,Event #37" "0,1" bitfld.long 0x14 4. "E36,Event #36" "0,1" newline bitfld.long 0x14 3. "E35,Event #35" "0,1" bitfld.long 0x14 2. "E34,Event #34" "0,1" newline bitfld.long 0x14 1. "E33,Event #33" "0,1" bitfld.long 0x14 0. "E32,Event #32" "0,1" line.long 0x18 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x18 31. "E31,Event #31" "0,1" bitfld.long 0x18 30. "E30,Event #30" "0,1" newline bitfld.long 0x18 29. "E29,Event #29" "0,1" bitfld.long 0x18 28. "E28,Event #28" "0,1" newline bitfld.long 0x18 27. "E27,Event #27" "0,1" bitfld.long 0x18 26. "E26,Event #26" "0,1" newline bitfld.long 0x18 25. "E25,Event #25" "0,1" bitfld.long 0x18 24. "E24,Event #24" "0,1" newline bitfld.long 0x18 23. "E23,Event #23" "0,1" bitfld.long 0x18 22. "E22,Event #22" "0,1" newline bitfld.long 0x18 21. "E21,Event #21" "0,1" bitfld.long 0x18 20. "E20,Event #20" "0,1" newline bitfld.long 0x18 19. "E19,Event #19" "0,1" bitfld.long 0x18 18. "E18,Event #18" "0,1" newline bitfld.long 0x18 17. "E17,Event #17" "0,1" bitfld.long 0x18 16. "E16,Event #16" "0,1" newline bitfld.long 0x18 15. "E15,Event #15" "0,1" bitfld.long 0x18 14. "E14,Event #14" "0,1" newline bitfld.long 0x18 13. "E13,Event #13" "0,1" bitfld.long 0x18 12. "E12,Event #12" "0,1" newline bitfld.long 0x18 11. "E11,Event #11" "0,1" bitfld.long 0x18 10. "E10,Event #10" "0,1" newline bitfld.long 0x18 9. "E9,Event #9" "0,1" bitfld.long 0x18 8. "E8,Event #8" "0,1" newline bitfld.long 0x18 7. "E7,Event #7" "0,1" bitfld.long 0x18 6. "E6,Event #6" "0,1" newline bitfld.long 0x18 5. "E5,Event #5" "0,1" bitfld.long 0x18 4. "E4,Event #4" "0,1" newline bitfld.long 0x18 3. "E3,Event #3" "0,1" bitfld.long 0x18 2. "E2,Event #2" "0,1" newline bitfld.long 0x18 1. "E1,Event #1" "0,1" bitfld.long 0x18 0. "E0,Event #0" "0,1" line.long 0x1C "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x1C 31. "E63,Event #63" "0,1" bitfld.long 0x1C 30. "E62,Event #62" "0,1" newline bitfld.long 0x1C 29. "E61,Event #61" "0,1" bitfld.long 0x1C 28. "E60,Event #60" "0,1" newline bitfld.long 0x1C 27. "E59,Event #59" "0,1" bitfld.long 0x1C 26. "E58,Event #58" "0,1" newline bitfld.long 0x1C 25. "E57,Event #57" "0,1" bitfld.long 0x1C 24. "E56,Event #56" "0,1" newline bitfld.long 0x1C 23. "E55,Event #55" "0,1" bitfld.long 0x1C 22. "E54,Event #54" "0,1" newline bitfld.long 0x1C 21. "E53,Event #53" "0,1" bitfld.long 0x1C 20. "E52,Event #52" "0,1" newline bitfld.long 0x1C 19. "E51,Event #51" "0,1" bitfld.long 0x1C 18. "E50,Event #50" "0,1" newline bitfld.long 0x1C 17. "E49,Event #49" "0,1" bitfld.long 0x1C 16. "E48,Event #48" "0,1" newline bitfld.long 0x1C 15. "E47,Event #47" "0,1" bitfld.long 0x1C 14. "E46,Event #46" "0,1" newline bitfld.long 0x1C 13. "E45,Event #45" "0,1" bitfld.long 0x1C 12. "E44,Event #44" "0,1" newline bitfld.long 0x1C 11. "E43,Event #43" "0,1" bitfld.long 0x1C 10. "E42,Event #42" "0,1" newline bitfld.long 0x1C 9. "E41,Event #41" "0,1" bitfld.long 0x1C 8. "E40,Event #40" "0,1" newline bitfld.long 0x1C 7. "E39,Event #39" "0,1" bitfld.long 0x1C 6. "E38,Event #38" "0,1" newline bitfld.long 0x1C 5. "E37,Event #37" "0,1" bitfld.long 0x1C 4. "E36,Event #36" "0,1" newline bitfld.long 0x1C 3. "E35,Event #35" "0,1" bitfld.long 0x1C 2. "E34,Event #34" "0,1" newline bitfld.long 0x1C 1. "E33,Event #33" "0,1" bitfld.long 0x1C 0. "E32,Event #32" "0,1" line.long 0x20 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x20 31. "E31,Event #31" "0,1" bitfld.long 0x20 30. "E30,Event #30" "0,1" newline bitfld.long 0x20 29. "E29,Event #29" "0,1" bitfld.long 0x20 28. "E28,Event #28" "0,1" newline bitfld.long 0x20 27. "E27,Event #27" "0,1" bitfld.long 0x20 26. "E26,Event #26" "0,1" newline bitfld.long 0x20 25. "E25,Event #25" "0,1" bitfld.long 0x20 24. "E24,Event #24" "0,1" newline bitfld.long 0x20 23. "E23,Event #23" "0,1" bitfld.long 0x20 22. "E22,Event #22" "0,1" newline bitfld.long 0x20 21. "E21,Event #21" "0,1" bitfld.long 0x20 20. "E20,Event #20" "0,1" newline bitfld.long 0x20 19. "E19,Event #19" "0,1" bitfld.long 0x20 18. "E18,Event #18" "0,1" newline bitfld.long 0x20 17. "E17,Event #17" "0,1" bitfld.long 0x20 16. "E16,Event #16" "0,1" newline bitfld.long 0x20 15. "E15,Event #15" "0,1" bitfld.long 0x20 14. "E14,Event #14" "0,1" newline bitfld.long 0x20 13. "E13,Event #13" "0,1" bitfld.long 0x20 12. "E12,Event #12" "0,1" newline bitfld.long 0x20 11. "E11,Event #11" "0,1" bitfld.long 0x20 10. "E10,Event #10" "0,1" newline bitfld.long 0x20 9. "E9,Event #9" "0,1" bitfld.long 0x20 8. "E8,Event #8" "0,1" newline bitfld.long 0x20 7. "E7,Event #7" "0,1" bitfld.long 0x20 6. "E6,Event #6" "0,1" newline bitfld.long 0x20 5. "E5,Event #5" "0,1" bitfld.long 0x20 4. "E4,Event #4" "0,1" newline bitfld.long 0x20 3. "E3,Event #3" "0,1" bitfld.long 0x20 2. "E2,Event #2" "0,1" newline bitfld.long 0x20 1. "E1,Event #1" "0,1" bitfld.long 0x20 0. "E0,Event #0" "0,1" line.long 0x24 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x24 31. "E63,Event #63" "0,1" bitfld.long 0x24 30. "E62,Event #62" "0,1" newline bitfld.long 0x24 29. "E61,Event #61" "0,1" bitfld.long 0x24 28. "E60,Event #60" "0,1" newline bitfld.long 0x24 27. "E59,Event #59" "0,1" bitfld.long 0x24 26. "E58,Event #58" "0,1" newline bitfld.long 0x24 25. "E57,Event #57" "0,1" bitfld.long 0x24 24. "E56,Event #56" "0,1" newline bitfld.long 0x24 23. "E55,Event #55" "0,1" bitfld.long 0x24 22. "E54,Event #54" "0,1" newline bitfld.long 0x24 21. "E53,Event #53" "0,1" bitfld.long 0x24 20. "E52,Event #52" "0,1" newline bitfld.long 0x24 19. "E51,Event #51" "0,1" bitfld.long 0x24 18. "E50,Event #50" "0,1" newline bitfld.long 0x24 17. "E49,Event #49" "0,1" bitfld.long 0x24 16. "E48,Event #48" "0,1" newline bitfld.long 0x24 15. "E47,Event #47" "0,1" bitfld.long 0x24 14. "E46,Event #46" "0,1" newline bitfld.long 0x24 13. "E45,Event #45" "0,1" bitfld.long 0x24 12. "E44,Event #44" "0,1" newline bitfld.long 0x24 11. "E43,Event #43" "0,1" bitfld.long 0x24 10. "E42,Event #42" "0,1" newline bitfld.long 0x24 9. "E41,Event #41" "0,1" bitfld.long 0x24 8. "E40,Event #40" "0,1" newline bitfld.long 0x24 7. "E39,Event #39" "0,1" bitfld.long 0x24 6. "E38,Event #38" "0,1" newline bitfld.long 0x24 5. "E37,Event #37" "0,1" bitfld.long 0x24 4. "E36,Event #36" "0,1" newline bitfld.long 0x24 3. "E35,Event #35" "0,1" bitfld.long 0x24 2. "E34,Event #34" "0,1" newline bitfld.long 0x24 1. "E33,Event #33" "0,1" bitfld.long 0x24 0. "E32,Event #32" "0,1" line.long 0x28 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x28 31. "E31,Event #31" "0,1" bitfld.long 0x28 30. "E30,Event #30" "0,1" newline bitfld.long 0x28 29. "E29,Event #29" "0,1" bitfld.long 0x28 28. "E28,Event #28" "0,1" newline bitfld.long 0x28 27. "E27,Event #27" "0,1" bitfld.long 0x28 26. "E26,Event #26" "0,1" newline bitfld.long 0x28 25. "E25,Event #25" "0,1" bitfld.long 0x28 24. "E24,Event #24" "0,1" newline bitfld.long 0x28 23. "E23,Event #23" "0,1" bitfld.long 0x28 22. "E22,Event #22" "0,1" newline bitfld.long 0x28 21. "E21,Event #21" "0,1" bitfld.long 0x28 20. "E20,Event #20" "0,1" newline bitfld.long 0x28 19. "E19,Event #19" "0,1" bitfld.long 0x28 18. "E18,Event #18" "0,1" newline bitfld.long 0x28 17. "E17,Event #17" "0,1" bitfld.long 0x28 16. "E16,Event #16" "0,1" newline bitfld.long 0x28 15. "E15,Event #15" "0,1" bitfld.long 0x28 14. "E14,Event #14" "0,1" newline bitfld.long 0x28 13. "E13,Event #13" "0,1" bitfld.long 0x28 12. "E12,Event #12" "0,1" newline bitfld.long 0x28 11. "E11,Event #11" "0,1" bitfld.long 0x28 10. "E10,Event #10" "0,1" newline bitfld.long 0x28 9. "E9,Event #9" "0,1" bitfld.long 0x28 8. "E8,Event #8" "0,1" newline bitfld.long 0x28 7. "E7,Event #7" "0,1" bitfld.long 0x28 6. "E6,Event #6" "0,1" newline bitfld.long 0x28 5. "E5,Event #5" "0,1" bitfld.long 0x28 4. "E4,Event #4" "0,1" newline bitfld.long 0x28 3. "E3,Event #3" "0,1" bitfld.long 0x28 2. "E2,Event #2" "0,1" newline bitfld.long 0x28 1. "E1,Event #1" "0,1" bitfld.long 0x28 0. "E0,Event #0" "0,1" line.long 0x2C "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x2C 31. "E63,Event #63" "0,1" bitfld.long 0x2C 30. "E62,Event #62" "0,1" newline bitfld.long 0x2C 29. "E61,Event #61" "0,1" bitfld.long 0x2C 28. "E60,Event #60" "0,1" newline bitfld.long 0x2C 27. "E59,Event #59" "0,1" bitfld.long 0x2C 26. "E58,Event #58" "0,1" newline bitfld.long 0x2C 25. "E57,Event #57" "0,1" bitfld.long 0x2C 24. "E56,Event #56" "0,1" newline bitfld.long 0x2C 23. "E55,Event #55" "0,1" bitfld.long 0x2C 22. "E54,Event #54" "0,1" newline bitfld.long 0x2C 21. "E53,Event #53" "0,1" bitfld.long 0x2C 20. "E52,Event #52" "0,1" newline bitfld.long 0x2C 19. "E51,Event #51" "0,1" bitfld.long 0x2C 18. "E50,Event #50" "0,1" newline bitfld.long 0x2C 17. "E49,Event #49" "0,1" bitfld.long 0x2C 16. "E48,Event #48" "0,1" newline bitfld.long 0x2C 15. "E47,Event #47" "0,1" bitfld.long 0x2C 14. "E46,Event #46" "0,1" newline bitfld.long 0x2C 13. "E45,Event #45" "0,1" bitfld.long 0x2C 12. "E44,Event #44" "0,1" newline bitfld.long 0x2C 11. "E43,Event #43" "0,1" bitfld.long 0x2C 10. "E42,Event #42" "0,1" newline bitfld.long 0x2C 9. "E41,Event #41" "0,1" bitfld.long 0x2C 8. "E40,Event #40" "0,1" newline bitfld.long 0x2C 7. "E39,Event #39" "0,1" bitfld.long 0x2C 6. "E38,Event #38" "0,1" newline bitfld.long 0x2C 5. "E37,Event #37" "0,1" bitfld.long 0x2C 4. "E36,Event #36" "0,1" newline bitfld.long 0x2C 3. "E35,Event #35" "0,1" bitfld.long 0x2C 2. "E34,Event #34" "0,1" newline bitfld.long 0x2C 1. "E33,Event #33" "0,1" bitfld.long 0x2C 0. "E32,Event #32" "0,1" line.long 0x30 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x30 31. "E31,Event #31" "0,1" bitfld.long 0x30 30. "E30,Event #30" "0,1" newline bitfld.long 0x30 29. "E29,Event #29" "0,1" bitfld.long 0x30 28. "E28,Event #28" "0,1" newline bitfld.long 0x30 27. "E27,Event #27" "0,1" bitfld.long 0x30 26. "E26,Event #26" "0,1" newline bitfld.long 0x30 25. "E25,Event #25" "0,1" bitfld.long 0x30 24. "E24,Event #24" "0,1" newline bitfld.long 0x30 23. "E23,Event #23" "0,1" bitfld.long 0x30 22. "E22,Event #22" "0,1" newline bitfld.long 0x30 21. "E21,Event #21" "0,1" bitfld.long 0x30 20. "E20,Event #20" "0,1" newline bitfld.long 0x30 19. "E19,Event #19" "0,1" bitfld.long 0x30 18. "E18,Event #18" "0,1" newline bitfld.long 0x30 17. "E17,Event #17" "0,1" bitfld.long 0x30 16. "E16,Event #16" "0,1" newline bitfld.long 0x30 15. "E15,Event #15" "0,1" bitfld.long 0x30 14. "E14,Event #14" "0,1" newline bitfld.long 0x30 13. "E13,Event #13" "0,1" bitfld.long 0x30 12. "E12,Event #12" "0,1" newline bitfld.long 0x30 11. "E11,Event #11" "0,1" bitfld.long 0x30 10. "E10,Event #10" "0,1" newline bitfld.long 0x30 9. "E9,Event #9" "0,1" bitfld.long 0x30 8. "E8,Event #8" "0,1" newline bitfld.long 0x30 7. "E7,Event #7" "0,1" bitfld.long 0x30 6. "E6,Event #6" "0,1" newline bitfld.long 0x30 5. "E5,Event #5" "0,1" bitfld.long 0x30 4. "E4,Event #4" "0,1" newline bitfld.long 0x30 3. "E3,Event #3" "0,1" bitfld.long 0x30 2. "E2,Event #2" "0,1" newline bitfld.long 0x30 1. "E1,Event #1" "0,1" bitfld.long 0x30 0. "E0,Event #0" "0,1" line.long 0x34 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x34 31. "E63,Event #63" "0,1" bitfld.long 0x34 30. "E62,Event #62" "0,1" newline bitfld.long 0x34 29. "E61,Event #61" "0,1" bitfld.long 0x34 28. "E60,Event #60" "0,1" newline bitfld.long 0x34 27. "E59,Event #59" "0,1" bitfld.long 0x34 26. "E58,Event #58" "0,1" newline bitfld.long 0x34 25. "E57,Event #57" "0,1" bitfld.long 0x34 24. "E56,Event #56" "0,1" newline bitfld.long 0x34 23. "E55,Event #55" "0,1" bitfld.long 0x34 22. "E54,Event #54" "0,1" newline bitfld.long 0x34 21. "E53,Event #53" "0,1" bitfld.long 0x34 20. "E52,Event #52" "0,1" newline bitfld.long 0x34 19. "E51,Event #51" "0,1" bitfld.long 0x34 18. "E50,Event #50" "0,1" newline bitfld.long 0x34 17. "E49,Event #49" "0,1" bitfld.long 0x34 16. "E48,Event #48" "0,1" newline bitfld.long 0x34 15. "E47,Event #47" "0,1" bitfld.long 0x34 14. "E46,Event #46" "0,1" newline bitfld.long 0x34 13. "E45,Event #45" "0,1" bitfld.long 0x34 12. "E44,Event #44" "0,1" newline bitfld.long 0x34 11. "E43,Event #43" "0,1" bitfld.long 0x34 10. "E42,Event #42" "0,1" newline bitfld.long 0x34 9. "E41,Event #41" "0,1" bitfld.long 0x34 8. "E40,Event #40" "0,1" newline bitfld.long 0x34 7. "E39,Event #39" "0,1" bitfld.long 0x34 6. "E38,Event #38" "0,1" newline bitfld.long 0x34 5. "E37,Event #37" "0,1" bitfld.long 0x34 4. "E36,Event #36" "0,1" newline bitfld.long 0x34 3. "E35,Event #35" "0,1" bitfld.long 0x34 2. "E34,Event #34" "0,1" newline bitfld.long 0x34 1. "E33,Event #33" "0,1" bitfld.long 0x34 0. "E32,Event #32" "0,1" line.long 0x38 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x38 31. "E31,Event #31" "0,1" bitfld.long 0x38 30. "E30,Event #30" "0,1" newline bitfld.long 0x38 29. "E29,Event #29" "0,1" bitfld.long 0x38 28. "E28,Event #28" "0,1" newline bitfld.long 0x38 27. "E27,Event #27" "0,1" bitfld.long 0x38 26. "E26,Event #26" "0,1" newline bitfld.long 0x38 25. "E25,Event #25" "0,1" bitfld.long 0x38 24. "E24,Event #24" "0,1" newline bitfld.long 0x38 23. "E23,Event #23" "0,1" bitfld.long 0x38 22. "E22,Event #22" "0,1" newline bitfld.long 0x38 21. "E21,Event #21" "0,1" bitfld.long 0x38 20. "E20,Event #20" "0,1" newline bitfld.long 0x38 19. "E19,Event #19" "0,1" bitfld.long 0x38 18. "E18,Event #18" "0,1" newline bitfld.long 0x38 17. "E17,Event #17" "0,1" bitfld.long 0x38 16. "E16,Event #16" "0,1" newline bitfld.long 0x38 15. "E15,Event #15" "0,1" bitfld.long 0x38 14. "E14,Event #14" "0,1" newline bitfld.long 0x38 13. "E13,Event #13" "0,1" bitfld.long 0x38 12. "E12,Event #12" "0,1" newline bitfld.long 0x38 11. "E11,Event #11" "0,1" bitfld.long 0x38 10. "E10,Event #10" "0,1" newline bitfld.long 0x38 9. "E9,Event #9" "0,1" bitfld.long 0x38 8. "E8,Event #8" "0,1" newline bitfld.long 0x38 7. "E7,Event #7" "0,1" bitfld.long 0x38 6. "E6,Event #6" "0,1" newline bitfld.long 0x38 5. "E5,Event #5" "0,1" bitfld.long 0x38 4. "E4,Event #4" "0,1" newline bitfld.long 0x38 3. "E3,Event #3" "0,1" bitfld.long 0x38 2. "E2,Event #2" "0,1" newline bitfld.long 0x38 1. "E1,Event #1" "0,1" bitfld.long 0x38 0. "E0,Event #0" "0,1" line.long 0x3C "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x3C 31. "E63,Event #63" "0,1" bitfld.long 0x3C 30. "E62,Event #62" "0,1" newline bitfld.long 0x3C 29. "E61,Event #61" "0,1" bitfld.long 0x3C 28. "E60,Event #60" "0,1" newline bitfld.long 0x3C 27. "E59,Event #59" "0,1" bitfld.long 0x3C 26. "E58,Event #58" "0,1" newline bitfld.long 0x3C 25. "E57,Event #57" "0,1" bitfld.long 0x3C 24. "E56,Event #56" "0,1" newline bitfld.long 0x3C 23. "E55,Event #55" "0,1" bitfld.long 0x3C 22. "E54,Event #54" "0,1" newline bitfld.long 0x3C 21. "E53,Event #53" "0,1" bitfld.long 0x3C 20. "E52,Event #52" "0,1" newline bitfld.long 0x3C 19. "E51,Event #51" "0,1" bitfld.long 0x3C 18. "E50,Event #50" "0,1" newline bitfld.long 0x3C 17. "E49,Event #49" "0,1" bitfld.long 0x3C 16. "E48,Event #48" "0,1" newline bitfld.long 0x3C 15. "E47,Event #47" "0,1" bitfld.long 0x3C 14. "E46,Event #46" "0,1" newline bitfld.long 0x3C 13. "E45,Event #45" "0,1" bitfld.long 0x3C 12. "E44,Event #44" "0,1" newline bitfld.long 0x3C 11. "E43,Event #43" "0,1" bitfld.long 0x3C 10. "E42,Event #42" "0,1" newline bitfld.long 0x3C 9. "E41,Event #41" "0,1" bitfld.long 0x3C 8. "E40,Event #40" "0,1" newline bitfld.long 0x3C 7. "E39,Event #39" "0,1" bitfld.long 0x3C 6. "E38,Event #38" "0,1" newline bitfld.long 0x3C 5. "E37,Event #37" "0,1" bitfld.long 0x3C 4. "E36,Event #36" "0,1" newline bitfld.long 0x3C 3. "E35,Event #35" "0,1" bitfld.long 0x3C 2. "E34,Event #34" "0,1" newline bitfld.long 0x3C 1. "E33,Event #33" "0,1" bitfld.long 0x3C 0. "E32,Event #32" "0,1" line.long 0x40 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x40 31. "E31,Event #31" "0,1" bitfld.long 0x40 30. "E30,Event #30" "0,1" newline bitfld.long 0x40 29. "E29,Event #29" "0,1" bitfld.long 0x40 28. "E28,Event #28" "0,1" newline bitfld.long 0x40 27. "E27,Event #27" "0,1" bitfld.long 0x40 26. "E26,Event #26" "0,1" newline bitfld.long 0x40 25. "E25,Event #25" "0,1" bitfld.long 0x40 24. "E24,Event #24" "0,1" newline bitfld.long 0x40 23. "E23,Event #23" "0,1" bitfld.long 0x40 22. "E22,Event #22" "0,1" newline bitfld.long 0x40 21. "E21,Event #21" "0,1" bitfld.long 0x40 20. "E20,Event #20" "0,1" newline bitfld.long 0x40 19. "E19,Event #19" "0,1" bitfld.long 0x40 18. "E18,Event #18" "0,1" newline bitfld.long 0x40 17. "E17,Event #17" "0,1" bitfld.long 0x40 16. "E16,Event #16" "0,1" newline bitfld.long 0x40 15. "E15,Event #15" "0,1" bitfld.long 0x40 14. "E14,Event #14" "0,1" newline bitfld.long 0x40 13. "E13,Event #13" "0,1" bitfld.long 0x40 12. "E12,Event #12" "0,1" newline bitfld.long 0x40 11. "E11,Event #11" "0,1" bitfld.long 0x40 10. "E10,Event #10" "0,1" newline bitfld.long 0x40 9. "E9,Event #9" "0,1" bitfld.long 0x40 8. "E8,Event #8" "0,1" newline bitfld.long 0x40 7. "E7,Event #7" "0,1" bitfld.long 0x40 6. "E6,Event #6" "0,1" newline bitfld.long 0x40 5. "E5,Event #5" "0,1" bitfld.long 0x40 4. "E4,Event #4" "0,1" newline bitfld.long 0x40 3. "E3,Event #3" "0,1" bitfld.long 0x40 2. "E2,Event #2" "0,1" newline bitfld.long 0x40 1. "E1,Event #1" "0,1" bitfld.long 0x40 0. "E0,Event #0" "0,1" line.long 0x44 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x44 31. "E63,Event #63" "0,1" bitfld.long 0x44 30. "E62,Event #62" "0,1" newline bitfld.long 0x44 29. "E61,Event #61" "0,1" bitfld.long 0x44 28. "E60,Event #60" "0,1" newline bitfld.long 0x44 27. "E59,Event #59" "0,1" bitfld.long 0x44 26. "E58,Event #58" "0,1" newline bitfld.long 0x44 25. "E57,Event #57" "0,1" bitfld.long 0x44 24. "E56,Event #56" "0,1" newline bitfld.long 0x44 23. "E55,Event #55" "0,1" bitfld.long 0x44 22. "E54,Event #54" "0,1" newline bitfld.long 0x44 21. "E53,Event #53" "0,1" bitfld.long 0x44 20. "E52,Event #52" "0,1" newline bitfld.long 0x44 19. "E51,Event #51" "0,1" bitfld.long 0x44 18. "E50,Event #50" "0,1" newline bitfld.long 0x44 17. "E49,Event #49" "0,1" bitfld.long 0x44 16. "E48,Event #48" "0,1" newline bitfld.long 0x44 15. "E47,Event #47" "0,1" bitfld.long 0x44 14. "E46,Event #46" "0,1" newline bitfld.long 0x44 13. "E45,Event #45" "0,1" bitfld.long 0x44 12. "E44,Event #44" "0,1" newline bitfld.long 0x44 11. "E43,Event #43" "0,1" bitfld.long 0x44 10. "E42,Event #42" "0,1" newline bitfld.long 0x44 9. "E41,Event #41" "0,1" bitfld.long 0x44 8. "E40,Event #40" "0,1" newline bitfld.long 0x44 7. "E39,Event #39" "0,1" bitfld.long 0x44 6. "E38,Event #38" "0,1" newline bitfld.long 0x44 5. "E37,Event #37" "0,1" bitfld.long 0x44 4. "E36,Event #36" "0,1" newline bitfld.long 0x44 3. "E35,Event #35" "0,1" bitfld.long 0x44 2. "E34,Event #34" "0,1" newline bitfld.long 0x44 1. "E33,Event #33" "0,1" bitfld.long 0x44 0. "E32,Event #32" "0,1" rgroup.long 0x1050++0x2B line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x08 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x0C "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x10 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x14 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x18 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x1C "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x20 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x24 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x28 "EDMA_TPCC_IEVAL,Interrupt Eval Register" hexmask.long 0x28 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" newline bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1080++0x17 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 7. "E7,Event #7" "0,1" newline rbitfld.long 0x04 6. "E6,Event #6" "0,1" rbitfld.long 0x04 5. "E5,Event #5" "0,1" newline rbitfld.long 0x04 4. "E4,Event #4" "0,1" rbitfld.long 0x04 3. "E3,Event #3" "0,1" newline rbitfld.long 0x04 2. "E2,Event #2" "0,1" rbitfld.long 0x04 1. "E1,Event #1" "0,1" newline rbitfld.long 0x04 0. "E0,Event #0" "0,1" line.long 0x08 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 7. "E7,Event #7" "0,1" newline bitfld.long 0x08 6. "E6,Event #6" "0,1" bitfld.long 0x08 5. "E5,Event #5" "0,1" newline bitfld.long 0x08 4. "E4,Event #4" "0,1" bitfld.long 0x08 3. "E3,Event #3" "0,1" newline bitfld.long 0x08 2. "E2,Event #2" "0,1" bitfld.long 0x08 1. "E1,Event #1" "0,1" newline bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 7. "E7,Event #7" "0,1" newline bitfld.long 0x0C 6. "E6,Event #6" "0,1" bitfld.long 0x0C 5. "E5,Event #5" "0,1" newline bitfld.long 0x0C 4. "E4,Event #4" "0,1" bitfld.long 0x0C 3. "E3,Event #3" "0,1" newline bitfld.long 0x0C 2. "E2,Event #2" "0,1" bitfld.long 0x0C 1. "E1,Event #1" "0,1" newline bitfld.long 0x0C 0. "E0,Event #0" "0,1" line.long 0x10 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 7. "E7,Event #7" "0,1" newline rbitfld.long 0x10 6. "E6,Event #6" "0,1" rbitfld.long 0x10 5. "E5,Event #5" "0,1" newline rbitfld.long 0x10 4. "E4,Event #4" "0,1" rbitfld.long 0x10 3. "E3,Event #3" "0,1" newline rbitfld.long 0x10 2. "E2,Event #2" "0,1" rbitfld.long 0x10 1. "E1,Event #1" "0,1" newline rbitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 7. "E7,Event #7" "0,1" newline bitfld.long 0x14 6. "E6,Event #6" "0,1" bitfld.long 0x14 5. "E5,Event #5" "0,1" newline bitfld.long 0x14 4. "E4,Event #4" "0,1" bitfld.long 0x14 3. "E3,Event #3" "0,1" newline bitfld.long 0x14 2. "E2,Event #2" "0,1" bitfld.long 0x14 1. "E1,Event #1" "0,1" newline bitfld.long 0x14 0. "E0,Event #0" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2200++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2600++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2204++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2604++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2208++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2608++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x220C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x260C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2210++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2610++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2214++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2614++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2218++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2618++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x221C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x261C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2220++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2620++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2224++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2624++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2228++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2628++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x222C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x262C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2230++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2630++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2234++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2634++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2238++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2638++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x223C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x263C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2240++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2640++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" newline bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" newline bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" newline bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" newline bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2244++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2644++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" newline bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" newline bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" newline bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" newline bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" newline bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2250++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2650++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2254++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2654++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2258++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2658++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x225C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x265C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2260++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2660++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2264++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2664++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2268++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2668++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x226C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x266C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2270++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2670++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2274++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2674++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2278++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2678++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2A78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2C78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2E78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "SET,Interrupt SetCPU writes 0x0 has no effect" "0,1" newline bitfld.long 0x00 0. "EVAL,Interrupt EvaluateCPU writes 0x0 has no effect" "0,1" group.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2280++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2680++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2284++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2684++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2288++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2688++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x228C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x268C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2290++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2690++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 7. "E7,Event #7" "0,1" newline rbitfld.long 0x00 6. "E6,Event #6" "0,1" rbitfld.long 0x00 5. "E5,Event #5" "0,1" newline rbitfld.long 0x00 4. "E4,Event #4" "0,1" rbitfld.long 0x00 3. "E3,Event #3" "0,1" newline rbitfld.long 0x00 2. "E2,Event #2" "0,1" rbitfld.long 0x00 1. "E1,Event #1" "0,1" newline rbitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2294++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2694++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,write 0's for future compatibility" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" newline bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4020++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_1,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4060++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_3,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_5,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_6,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x40E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_7,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4100++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_8,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4120++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_9,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4140++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4160++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_11,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4180++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_12,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_13,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_14,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x41E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_15,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4200++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4220++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_17,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4240++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_18,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4260++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_19,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4280++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_20,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_21,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_22,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x42E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_23,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4300++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_24,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4320++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_25,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4340++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_26,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4360++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_27,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4380++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_28,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_29,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_30,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x43E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_31,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4400++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4420++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_33,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4440++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_34,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4460++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_35,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4480++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_36,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_37,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_38,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x44E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_39,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4500++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_40,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4520++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_41,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4540++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_42,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4560++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_43,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4580++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_44,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_45,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_46,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x45E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_47,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4600++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4620++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_49,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4640++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_50,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4660++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_51,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4680++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_52,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_53,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_54,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x46E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_55,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4700++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_56,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4720++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_57,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4740++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_58,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4760++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_59,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4780++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_60,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_61,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_62,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x47E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_63,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4800++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4820++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_65,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4840++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_66,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4860++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_67,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4880++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_68,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_69,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_70,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x48E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_71,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4900++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_72,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4920++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_73,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4940++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_74,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4960++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_75,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4980++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_76,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_77,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_78,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x49E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_79,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_81,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_82,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_83,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4A80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_84,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_85,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_86,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4AE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_87,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_88,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_89,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_90,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_91,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4B80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_92,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_93,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_94,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4BE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_95,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_96,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_97,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_98,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_99,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4C80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_101,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_102,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4CE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_103,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_104,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_105,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_106,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_107,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4D80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_108,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_109,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_110,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4DE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_111,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_113,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_114,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_115,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4E80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_116,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_117,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_118,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4EE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_119,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F00++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_120,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F20++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_121,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F40++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_122,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F60++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_123,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4F80++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_124,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FA0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_125,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FC0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_126,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4FE0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_127,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" newline bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" newline bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" newline rbitfld.long 0x00 18. "RESERVED,Reserved" "0,1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" newline bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" newline bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" group.long 0x4024++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_1,Source Address" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" group.long 0x4064++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_3,Source Address" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" group.long 0x40A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_5,Source Address" group.long 0x40C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_6,Source Address" group.long 0x40E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_7,Source Address" group.long 0x4104++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_8,Source Address" group.long 0x4124++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_9,Source Address" group.long 0x4144++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_10,Source Address" group.long 0x4164++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_11,Source Address" group.long 0x4184++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_12,Source Address" group.long 0x41A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_13,Source Address" group.long 0x41C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_14,Source Address" group.long 0x41E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_15,Source Address" group.long 0x4204++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_16,Source Address" group.long 0x4224++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_17,Source Address" group.long 0x4244++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_18,Source Address" group.long 0x4264++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_19,Source Address" group.long 0x4284++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_20,Source Address" group.long 0x42A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_21,Source Address" group.long 0x42C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_22,Source Address" group.long 0x42E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_23,Source Address" group.long 0x4304++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_24,Source Address" group.long 0x4324++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_25,Source Address" group.long 0x4344++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_26,Source Address" group.long 0x4364++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_27,Source Address" group.long 0x4384++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_28,Source Address" group.long 0x43A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_29,Source Address" group.long 0x43C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_30,Source Address" group.long 0x43E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_31,Source Address" group.long 0x4404++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_32,Source Address" group.long 0x4424++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_33,Source Address" group.long 0x4444++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_34,Source Address" group.long 0x4464++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_35,Source Address" group.long 0x4484++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_36,Source Address" group.long 0x44A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_37,Source Address" group.long 0x44C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_38,Source Address" group.long 0x44E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_39,Source Address" group.long 0x4504++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_40,Source Address" group.long 0x4524++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_41,Source Address" group.long 0x4544++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_42,Source Address" group.long 0x4564++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_43,Source Address" group.long 0x4584++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_44,Source Address" group.long 0x45A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_45,Source Address" group.long 0x45C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_46,Source Address" group.long 0x45E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_47,Source Address" group.long 0x4604++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_48,Source Address" group.long 0x4624++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_49,Source Address" group.long 0x4644++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_50,Source Address" group.long 0x4664++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_51,Source Address" group.long 0x4684++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_52,Source Address" group.long 0x46A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_53,Source Address" group.long 0x46C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_54,Source Address" group.long 0x46E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_55,Source Address" group.long 0x4704++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_56,Source Address" group.long 0x4724++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_57,Source Address" group.long 0x4744++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_58,Source Address" group.long 0x4764++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_59,Source Address" group.long 0x4784++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_60,Source Address" group.long 0x47A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_61,Source Address" group.long 0x47C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_62,Source Address" group.long 0x47E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_63,Source Address" group.long 0x4804++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_64,Source Address" group.long 0x4824++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_65,Source Address" group.long 0x4844++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_66,Source Address" group.long 0x4864++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_67,Source Address" group.long 0x4884++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_68,Source Address" group.long 0x48A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_69,Source Address" group.long 0x48C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_70,Source Address" group.long 0x48E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_71,Source Address" group.long 0x4904++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_72,Source Address" group.long 0x4924++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_73,Source Address" group.long 0x4944++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_74,Source Address" group.long 0x4964++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_75,Source Address" group.long 0x4984++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_76,Source Address" group.long 0x49A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_77,Source Address" group.long 0x49C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_78,Source Address" group.long 0x49E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_79,Source Address" group.long 0x4A04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_80,Source Address" group.long 0x4A24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_81,Source Address" group.long 0x4A44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_82,Source Address" group.long 0x4A64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_83,Source Address" group.long 0x4A84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_84,Source Address" group.long 0x4AA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_85,Source Address" group.long 0x4AC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_86,Source Address" group.long 0x4AE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_87,Source Address" group.long 0x4B04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_88,Source Address" group.long 0x4B24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_89,Source Address" group.long 0x4B44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_90,Source Address" group.long 0x4B64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_91,Source Address" group.long 0x4B84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_92,Source Address" group.long 0x4BA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_93,Source Address" group.long 0x4BC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_94,Source Address" group.long 0x4BE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_95,Source Address" group.long 0x4C04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_96,Source Address" group.long 0x4C24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_97,Source Address" group.long 0x4C44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_98,Source Address" group.long 0x4C64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_99,Source Address" group.long 0x4C84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_100,Source Address" group.long 0x4CA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_101,Source Address" group.long 0x4CC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_102,Source Address" group.long 0x4CE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_103,Source Address" group.long 0x4D04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_104,Source Address" group.long 0x4D24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_105,Source Address" group.long 0x4D44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_106,Source Address" group.long 0x4D64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_107,Source Address" group.long 0x4D84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_108,Source Address" group.long 0x4DA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_109,Source Address" group.long 0x4DC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_110,Source Address" group.long 0x4DE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_111,Source Address" group.long 0x4E04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_112,Source Address" group.long 0x4E24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_113,Source Address" group.long 0x4E44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_114,Source Address" group.long 0x4E64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_115,Source Address" group.long 0x4E84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_116,Source Address" group.long 0x4EA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_117,Source Address" group.long 0x4EC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_118,Source Address" group.long 0x4EE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_119,Source Address" group.long 0x4F04++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_120,Source Address" group.long 0x4F24++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_121,Source Address" group.long 0x4F44++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_122,Source Address" group.long 0x4F64++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_123,Source Address" group.long 0x4F84++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_124,Source Address" group.long 0x4FA4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_125,Source Address" group.long 0x4FC4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_126,Source Address" group.long 0x4FE4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_127,Source Address" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x402C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_1,Destination Address" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x406C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_3,Destination Address" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x40AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_5,Destination Address" group.long 0x40CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_6,Destination Address" group.long 0x40EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_7,Destination Address" group.long 0x410C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_8,Destination Address" group.long 0x412C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_9,Destination Address" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x416C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_11,Destination Address" group.long 0x418C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_12,Destination Address" group.long 0x41AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_13,Destination Address" group.long 0x41CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_14,Destination Address" group.long 0x41EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_15,Destination Address" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x422C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_17,Destination Address" group.long 0x424C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_18,Destination Address" group.long 0x426C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_19,Destination Address" group.long 0x428C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_20,Destination Address" group.long 0x42AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_21,Destination Address" group.long 0x42CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_22,Destination Address" group.long 0x42EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_23,Destination Address" group.long 0x430C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_24,Destination Address" group.long 0x432C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_25,Destination Address" group.long 0x434C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_26,Destination Address" group.long 0x436C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_27,Destination Address" group.long 0x438C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_28,Destination Address" group.long 0x43AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_29,Destination Address" group.long 0x43CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_30,Destination Address" group.long 0x43EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_31,Destination Address" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x442C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_33,Destination Address" group.long 0x444C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_34,Destination Address" group.long 0x446C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_35,Destination Address" group.long 0x448C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_36,Destination Address" group.long 0x44AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_37,Destination Address" group.long 0x44CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_38,Destination Address" group.long 0x44EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_39,Destination Address" group.long 0x450C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_40,Destination Address" group.long 0x452C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_41,Destination Address" group.long 0x454C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_42,Destination Address" group.long 0x456C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_43,Destination Address" group.long 0x458C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_44,Destination Address" group.long 0x45AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_45,Destination Address" group.long 0x45CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_46,Destination Address" group.long 0x45EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_47,Destination Address" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x462C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_49,Destination Address" group.long 0x464C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_50,Destination Address" group.long 0x466C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_51,Destination Address" group.long 0x468C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_52,Destination Address" group.long 0x46AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_53,Destination Address" group.long 0x46CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_54,Destination Address" group.long 0x46EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_55,Destination Address" group.long 0x470C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_56,Destination Address" group.long 0x472C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_57,Destination Address" group.long 0x474C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_58,Destination Address" group.long 0x476C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_59,Destination Address" group.long 0x478C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_60,Destination Address" group.long 0x47AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_61,Destination Address" group.long 0x47CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_62,Destination Address" group.long 0x47EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_63,Destination Address" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x482C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_65,Destination Address" group.long 0x484C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_66,Destination Address" group.long 0x486C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_67,Destination Address" group.long 0x488C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_68,Destination Address" group.long 0x48AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_69,Destination Address" group.long 0x48CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_70,Destination Address" group.long 0x48EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_71,Destination Address" group.long 0x490C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_72,Destination Address" group.long 0x492C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_73,Destination Address" group.long 0x494C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_74,Destination Address" group.long 0x496C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_75,Destination Address" group.long 0x498C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_76,Destination Address" group.long 0x49AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_77,Destination Address" group.long 0x49CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_78,Destination Address" group.long 0x49EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_79,Destination Address" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_81,Destination Address" group.long 0x4A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_82,Destination Address" group.long 0x4A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_83,Destination Address" group.long 0x4A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_84,Destination Address" group.long 0x4AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_85,Destination Address" group.long 0x4ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_86,Destination Address" group.long 0x4AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_87,Destination Address" group.long 0x4B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_88,Destination Address" group.long 0x4B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_89,Destination Address" group.long 0x4B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_90,Destination Address" group.long 0x4B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_91,Destination Address" group.long 0x4B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_92,Destination Address" group.long 0x4BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_93,Destination Address" group.long 0x4BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_94,Destination Address" group.long 0x4BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_95,Destination Address" group.long 0x4C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_96,Destination Address" group.long 0x4C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_97,Destination Address" group.long 0x4C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_98,Destination Address" group.long 0x4C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_99,Destination Address" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_101,Destination Address" group.long 0x4CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_102,Destination Address" group.long 0x4CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_103,Destination Address" group.long 0x4D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_104,Destination Address" group.long 0x4D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_105,Destination Address" group.long 0x4D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_106,Destination Address" group.long 0x4D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_107,Destination Address" group.long 0x4D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_108,Destination Address" group.long 0x4DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_109,Destination Address" group.long 0x4DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_110,Destination Address" group.long 0x4DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_111,Destination Address" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_113,Destination Address" group.long 0x4E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_114,Destination Address" group.long 0x4E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_115,Destination Address" group.long 0x4E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_116,Destination Address" group.long 0x4EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_117,Destination Address" group.long 0x4ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_118,Destination Address" group.long 0x4EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_119,Destination Address" group.long 0x4F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_120,Destination Address" group.long 0x4F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_121,Destination Address" group.long 0x4F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_122,Destination Address" group.long 0x4F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_123,Destination Address" group.long 0x4F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_124,Destination Address" group.long 0x4FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_125,Destination Address" group.long 0x4FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_126,Destination Address" group.long 0x4FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_127,Destination Address" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_1," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_3," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_5," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_6," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_7," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_8," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_9," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_11," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_12," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_13," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_14," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_15," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_17," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_18," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_19," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_20," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_21," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_22," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_23," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_24," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_25," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_26," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_27," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_28," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_29," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_30," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_31," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_33," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_34," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_35," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_36," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_37," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_38," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_39," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_40," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_41," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_42," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_43," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_44," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_45," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_46," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_47," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_49," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_50," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_51," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_52," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_53," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_54," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_55," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_56," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_57," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_58," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_59," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_60," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_61," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_62," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_63," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_65," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_66," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_67," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_68," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_69," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_70," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_71," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_72," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_73," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_74," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_75," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_76," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_77," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_78," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_79," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_81," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_82," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_83," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_84," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_85," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_86," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_87," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_88," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_89," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_90," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_91," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_92," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_93," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_94," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_95," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_96," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_97," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_98," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_99," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_101," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_102," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_103," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_104," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_105," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_106," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_107," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_108," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_109," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_110," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_111," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_113," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_114," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_115," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_116," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_117," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_118," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_119," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_120," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_121," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_122," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_123," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_124," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_125," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_126," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_127," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x40F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x40F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x41F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x403C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x407C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x40FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x411C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x413C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x417C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x419C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x423C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x425C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x427C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x429C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x431C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x433C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x435C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x437C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x439C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x443C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x445C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x447C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x449C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x451C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x453C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x455C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x457C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x459C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x463C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x465C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x467C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x469C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x471C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x473C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x475C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x477C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x479C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x483C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x485C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x487C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x489C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x491C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x493C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x495C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x497C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x499C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x43400000 ad:0x43500000 ) tree "SYS_EDMA_TPTC$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPTCn_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPTCn_TCCFG,TC Configuration Register" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 8.--9. "DREGDEPTH,Destination Register FIFO Depth Parameterization" "0,1,2,3" bitfld.long 0x04 6.--7. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x04 3. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" group.long 0x100++0x13 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 11.--12. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" newline rbitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" rbitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" rbitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" line.long 0x04 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" rbitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x08 "EDMA_TPTCn_INTEN,Interrupt Enable Register" hexmask.long 0x08 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x0C "EDMA_TPTCn_INTCLR,Interrupt Clear Register" hexmask.long 0x0C 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x10 "EDMA_TPTCn_INTCMD,Interrupt Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" group.long 0x120++0x13 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" rbitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 1. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" line.long 0x04 "EDMA_TPTCn_ERREN,Error Enable Register" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x04 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x04 1. "RESERVED,Reserved" "0,1" bitfld.long 0x04 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" line.long 0x08 "EDMA_TPTCn_ERRCLR,Error Clear Register" hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x08 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x08 1. "RESERVED,Reserved" "0,1" bitfld.long 0x08 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" line.long 0x0C "EDMA_TPTCn_ERRDET,Error Details Register" hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0C 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" rbitfld.long 0x0C 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 14.--15. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EDMA_TPTCn_ERRCMD,Error Command Register" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" group.long 0x200++0x17 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" rbitfld.long 0x00 21. "RESERVED,Reserved" "0,1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" rbitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 11. "RESERVED,Reserved" "0,1" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 7. "RESERVED,Reserved" "0,1" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "Highest priority,Priority 1,?,?,?,?,?,Lowest priority" newline rbitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" line.long 0x08 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count" line.long 0x0C "EDMA_TPTCn_PDST,Program Set Destination Address" line.long 0x10 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" line.long 0x14 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x240++0x23 line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" line.long 0x08 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" line.long 0x0C "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved. return 0x0 w/o AERROR" line.long 0x10 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" line.long 0x14 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x14 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" line.long 0x1C "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" line.long 0x20 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" group.long 0x280++0x0B line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" line.long 0x04 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" line.long 0x08 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" group.long 0x300++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" hexmask.long.word 0x00 23.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 18.--19. "RESERVED,Reserved" "0,1,2,3" newline rbitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "RESERVED,Reserved" "0,1" rbitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 2.--3. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" rbitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x304++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x344++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" rgroup.long 0x308++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x348++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" rgroup.long 0x30C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x34C++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x350++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" group.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x354++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end repeat.end tree "System_MMU" base ad:0x4881C000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Write 0's for future compatibility" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" rbitfld.long 0x00 5.--7. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x00 2. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" hexmask.long 0x04 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" hexmask.long 0x08 5.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" newline bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0_w,EMUMISS_1_r" bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" hexmask.long 0x0C 5.--31. 1. "RESERVED,Write 0's for future compatibility Read returns 0" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" newline bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled)" "EMUMISS_0,EMUMISS_1" bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault)" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled)" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" hexmask.long 0x00 1.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" hexmask.long 0x04 4.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable" "TWLENABLE_0,TWLENABLE_1" newline bitfld.long 0x04 1. "MMUENABLE,MMU enable" "MMUENABLE_0,MMUENABLE_1" rbitfld.long 0x04 0. "RESERVED,Write 0's for future compatibility" "0,1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" hexmask.long.byte 0x0C 0.--6. 1. "RESERVED,Write 0's for future compatibility" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 9. "RESERVED,Write 0's for future compatibility" "0,1" newline bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x10 0.--3. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" hexmask.long 0x14 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x18 4.--11. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x18 3. "P,Preserved bit" "P_0,P_1" newline bitfld.long 0x18 2. "V,Valid bit" "V_0,V_1" bitfld.long 0x18 0.--1. "PAGESIZE,Page size" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x1C 0.--11. 1. "RESERVED,Write 0's for future compatibility" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" hexmask.long 0x20 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" hexmask.long 0x24 1.--31. 1. "RESERVED,Write 0's for future compatibility" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" hexmask.long.byte 0x28 4.--11. 1. "RESERVED,Reads return 0" bitfld.long 0x28 3. "P,Preserved bit" "P_0_r,P_1_r" newline bitfld.long 0x28 2. "V,Valid bit" "V_0_r,V_1_r" bitfld.long 0x28 0.--1. "PAGESIZE,Page size" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" hexmask.long.word 0x2C 0.--11. 1. "RESERVED,Reads return 0" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED,Reserved" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" newline rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "0,1,2,3" bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "0,1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" hexmask.long.word 0x08 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 0.--15. 1. "RESERVED,Reserved" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 0.--15. 1. "RESERVED,Reserved" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 0.--15. 1. "RESERVED,Reserved" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the fourth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 0.--15. 1. "RESERVED,Reserved" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of fourth NO TRANSLATION REGION for 2D bursts" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" width 0x0B tree.end tree "TESOC" base ad:0x4B800000 rgroup.long 0x00++0x03 line.long 0x00 "TESOC_IP_REVISION,IP Revision Information" rgroup.long 0x10++0x03 line.long 0x00 "TESOC_IP_HWINFO,IP Hardware Information" group.long 0x20++0x03 line.long 0x00 "TESOC_IP_SYSCONFIG," group.long 0x80++0x03 line.long 0x00 "TESOC_INTR_EOI,End Of Interrupt register - Interrupt handler" group.long 0x90++0x03 line.long 0x00 "TESOC_INTR_STATUS_RAW_SET,Set Interrupt Status Raw register" group.long 0xA0++0x03 line.long 0x00 "TESOC_INTR_STATUS_ENABLED_CLEAR,This register contains status flags of the enabled interrupts" group.long 0xB0++0x03 line.long 0x00 "TESOC_INTR_ENABLE_SET,Interrupt enable register" group.long 0xC0++0x03 line.long 0x00 "TESOC_INTR_ENABLE_CLEAR,Interrupt clear register" group.long 0xD0++0x03 line.long 0x00 "TESOC_LOCK,LOCK Register" hexmask.long 0x00 4.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "LOCK,Lock feature prevents unintentional updates to TESOC registers" "?,?,?,?,?,Locked,?,?,?,?,Unlocked,?..." group.long 0xE0++0x03 line.long 0x00 "TESOC_ABORT,ABORT Register" hexmask.long 0x00 4.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "ABORT,This has to be written into by the software to abort field-test immediately and transfer control on test module to application" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xF0++0x03 line.long 0x00 "TESOC_BUSY,BUSY Register" hexmask.long 0x00 4.--31. 1. "RESERVED," newline bitfld.long 0x00 0.--3. "BUSY,During BUSY state" "Not busy..,?,?,?,?,Busy,?..." group.long 0x110++0x103 line.long 0x00 "TESOC_DIAG_INFO_0_i_0,Error Diagnostics Information Register bank" line.long 0x04 "TESOC_DIAG_INFO_0_i_1,Error Diagnostics Information Register bank" line.long 0x08 "TESOC_DIAG_INFO_0_i_2,Error Diagnostics Information Register bank" line.long 0x0C "TESOC_DIAG_INFO_0_i_3,Error Diagnostics Information Register bank" line.long 0x10 "TESOC_DIAG_INFO_1_i_0,Error Diagnostics Information Register bank" line.long 0x14 "TESOC_DIAG_INFO_1_i_1,Error Diagnostics Information Register bank" line.long 0x18 "TESOC_DIAG_INFO_1_i_2,Error Diagnostics Information Register bank" line.long 0x1C "TESOC_DIAG_INFO_1_i_3,Error Diagnostics Information Register bank" line.long 0x20 "TESOC_DIAG_INFO_2_i_0,Error Diagnostics Information Register bank" line.long 0x24 "TESOC_DIAG_INFO_2_i_1,Error Diagnostics Information Register bank" line.long 0x28 "TESOC_DIAG_INFO_2_i_2,Error Diagnostics Information Register bank" line.long 0x2C "TESOC_DIAG_INFO_2_i_3,Error Diagnostics Information Register bank" line.long 0x30 "TESOC_DIAG_INFO_3_i_0,Error Diagnostics Information Register bank" line.long 0x34 "TESOC_DIAG_INFO_3_i_1,Error Diagnostics Information Register bank" line.long 0x38 "TESOC_DIAG_INFO_3_i_2,Error Diagnostics Information Register bank" line.long 0x3C "TESOC_DIAG_INFO_3_i_3,Error Diagnostics Information Register bank" line.long 0x40 "TESOC_DIAG_INFO_4_i_0,Error Diagnostics Information Register bank" line.long 0x44 "TESOC_DIAG_INFO_4_i_1,Error Diagnostics Information Register bank" line.long 0x48 "TESOC_DIAG_INFO_4_i_2,Error Diagnostics Information Register bank" line.long 0x4C "TESOC_DIAG_INFO_4_i_3,Error Diagnostics Information Register bank" line.long 0x50 "TESOC_DIAG_INFO_5_i_0,Error Diagnostics Information Register bank" line.long 0x54 "TESOC_DIAG_INFO_5_i_1,Error Diagnostics Information Register bank" line.long 0x58 "TESOC_DIAG_INFO_5_i_2,Error Diagnostics Information Register bank" line.long 0x5C "TESOC_DIAG_INFO_5_i_3,Error Diagnostics Information Register bank" line.long 0x60 "TESOC_DIAG_INFO_6_i_0,Error Diagnostics Information Register bank" line.long 0x64 "TESOC_DIAG_INFO_6_i_1,Error Diagnostics Information Register bank" line.long 0x68 "TESOC_DIAG_INFO_6_i_2,Error Diagnostics Information Register bank" line.long 0x6C "TESOC_DIAG_INFO_6_i_3,Error Diagnostics Information Register bank" line.long 0x70 "TESOC_DIAG_INFO_7_i_0,Error Diagnostics Information Register bank" line.long 0x74 "TESOC_DIAG_INFO_7_i_1,Error Diagnostics Information Register bank" line.long 0x78 "TESOC_DIAG_INFO_7_i_2,Error Diagnostics Information Register bank" line.long 0x7C "TESOC_DIAG_INFO_7_i_3,Error Diagnostics Information Register bank" line.long 0x80 "TESOC_DIAG_INFO_8_i_0,Error Diagnostics Information Register bank" line.long 0x84 "TESOC_DIAG_INFO_8_i_1,Error Diagnostics Information Register bank" line.long 0x88 "TESOC_DIAG_INFO_8_i_2,Error Diagnostics Information Register bank" line.long 0x8C "TESOC_DIAG_INFO_8_i_3,Error Diagnostics Information Register bank" line.long 0x90 "TESOC_DIAG_INFO_9_i_0,Error Diagnostics Information Register bank" line.long 0x94 "TESOC_DIAG_INFO_9_i_1,Error Diagnostics Information Register bank" line.long 0x98 "TESOC_DIAG_INFO_9_i_2,Error Diagnostics Information Register bank" line.long 0x9C "TESOC_DIAG_INFO_9_i_3,Error Diagnostics Information Register bank" line.long 0xA0 "TESOC_DIAG_INFO_10_i_0,Error Diagnostics Information Register bank" line.long 0xA4 "TESOC_DIAG_INFO_10_i_1,Error Diagnostics Information Register bank" line.long 0xA8 "TESOC_DIAG_INFO_10_i_2,Error Diagnostics Information Register bank" line.long 0xAC "TESOC_DIAG_INFO_10_i_3,Error Diagnostics Information Register bank" line.long 0xB0 "TESOC_DIAG_INFO_11_i_0,Error Diagnostics Information Register bank" line.long 0xB4 "TESOC_DIAG_INFO_11_i_1,Error Diagnostics Information Register bank" line.long 0xB8 "TESOC_DIAG_INFO_11_i_2,Error Diagnostics Information Register bank" line.long 0xBC "TESOC_DIAG_INFO_11_i_3,Error Diagnostics Information Register bank" line.long 0xC0 "TESOC_DIAG_INFO_12_i_0,Error Diagnostics Information Register bank" line.long 0xC4 "TESOC_DIAG_INFO_12_i_1,Error Diagnostics Information Register bank" line.long 0xC8 "TESOC_DIAG_INFO_12_i_2,Error Diagnostics Information Register bank" line.long 0xCC "TESOC_DIAG_INFO_12_i_3,Error Diagnostics Information Register bank" line.long 0xD0 "TESOC_DIAG_INFO_13_i_0,Error Diagnostics Information Register bank" line.long 0xD4 "TESOC_DIAG_INFO_13_i_1,Error Diagnostics Information Register bank" line.long 0xD8 "TESOC_DIAG_INFO_13_i_2,Error Diagnostics Information Register bank" line.long 0xDC "TESOC_DIAG_INFO_13_i_3,Error Diagnostics Information Register bank" line.long 0xE0 "TESOC_DIAG_INFO_14_i_0,Error Diagnostics Information Register bank" line.long 0xE4 "TESOC_DIAG_INFO_14_i_1,Error Diagnostics Information Register bank" line.long 0xE8 "TESOC_DIAG_INFO_14_i_2,Error Diagnostics Information Register bank" line.long 0xEC "TESOC_DIAG_INFO_14_i_3,Error Diagnostics Information Register bank" line.long 0xF0 "TESOC_DIAG_INFO_15_i_0,Error Diagnostics Information Register bank" line.long 0xF4 "TESOC_DIAG_INFO_15_i_1,Error Diagnostics Information Register bank" line.long 0xF8 "TESOC_DIAG_INFO_15_i_2,Error Diagnostics Information Register bank" line.long 0xFC "TESOC_DIAG_INFO_15_i_3,Error Diagnostics Information Register bank" line.long 0x100 "TESOC_DOMAIN_EN_DOM0,Start Domain Register for domain PD_IPU" hexmask.long 0x100 1.--31. 1. "RESERVED," newline bitfld.long 0x100 0. "START_DOMAIN,This bitfield indicates that a particular processor can be moved into field-test mode" "Field test for domain PD_IPU is disabled,Field test for domain PD_IPU is enabled This.." group.long 0x220++0x03 line.long 0x00 "TESOC_DOMAIN_EN_DOM1,Start Domain Register for domain PD_EVE1" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "START_DOMAIN,This bitfield indicates that a particular processor can be moved into field-test mode" "Field test for domain PD_EVE1 is disabled,Field test for domain PD_EVE1 is enabled This.." group.long 0x230++0x03 line.long 0x00 "TESOC_DOMAIN_EN_DOM2,Start Domain Register for domain PD_DSP1" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "START_DOMAIN,This bitfield indicates that a particular processor can be moved into field-test mode" "Field test for domain PD_DSP1 is disabled,Field test for domain PD_DSP1 is enabled This.." group.long 0x240++0x03 line.long 0x00 "TESOC_DOMAIN_EN_DOM3,Start Domain Register for domain PD_DSP2" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "START_DOMAIN,This bitfield indicates that a particular processor can be moved into field-test mode" "Field test for domain PD_DSP2 is disabled,Field test for domain PD_DSP2 is enabled This.." group.long 0x250++0x03 line.long 0x00 "TESOC_DOMAIN_EN_DOM4,Start Domain Register for domains PD_ISS and PD_DSS" hexmask.long 0x00 1.--31. 1. "RESERVED," newline bitfld.long 0x00 0. "START_DOMAIN,This bitfield indicates that a particular processor can be moved into field-test mode" "Field test for domains PD_ISS and PD_DSS is..,Field test for domains PD_ISS and PD_DSS is.." group.long 0x260++0x1DF line.long 0x00 "TESOC_SLICE_CONFIG_DOM0_n_0,Slice Configuration Register" line.long 0x04 "TESOC_SLICE_CONFIG_DOM0_n_1,Slice Configuration Register" line.long 0x08 "TESOC_SLICE_CONFIG_DOM0_n_2,Slice Configuration Register" line.long 0x0C "TESOC_SLICE_CONFIG_DOM0_n_3,Slice Configuration Register" line.long 0x10 "TESOC_SLICE_CONFIG_DOM0_n_4,Slice Configuration Register" line.long 0x14 "TESOC_SLICE_CONFIG_DOM0_n_5,Slice Configuration Register" line.long 0x18 "TESOC_SLICE_CONFIG_DOM0_n_6,Slice Configuration Register" line.long 0x1C "TESOC_SLICE_CONFIG_DOM0_n_7,Slice Configuration Register" line.long 0x20 "TESOC_SLICE_CONFIG_DOM1_n_0,Slice Configuration Register" line.long 0x24 "TESOC_SLICE_CONFIG_DOM1_n_1,Slice Configuration Register" line.long 0x28 "TESOC_SLICE_CONFIG_DOM1_n_2,Slice Configuration Register" line.long 0x2C "TESOC_SLICE_CONFIG_DOM1_n_3,Slice Configuration Register" line.long 0x30 "TESOC_SLICE_CONFIG_DOM1_n_4,Slice Configuration Register" line.long 0x34 "TESOC_SLICE_CONFIG_DOM1_n_5,Slice Configuration Register" line.long 0x38 "TESOC_SLICE_CONFIG_DOM1_n_6,Slice Configuration Register" line.long 0x3C "TESOC_SLICE_CONFIG_DOM1_n_7,Slice Configuration Register" line.long 0x40 "TESOC_SLICE_CONFIG_DOM2_n_0,Slice Configuration Register" line.long 0x44 "TESOC_SLICE_CONFIG_DOM2_n_1,Slice Configuration Register" line.long 0x48 "TESOC_SLICE_CONFIG_DOM2_n_2,Slice Configuration Register" line.long 0x4C "TESOC_SLICE_CONFIG_DOM2_n_3,Slice Configuration Register" line.long 0x50 "TESOC_SLICE_CONFIG_DOM2_n_4,Slice Configuration Register" line.long 0x54 "TESOC_SLICE_CONFIG_DOM2_n_5,Slice Configuration Register" line.long 0x58 "TESOC_SLICE_CONFIG_DOM2_n_6,Slice Configuration Register" line.long 0x5C "TESOC_SLICE_CONFIG_DOM2_n_7,Slice Configuration Register" line.long 0x60 "TESOC_SLICE_CONFIG_DOM3_n_0,Slice Configuration Register" line.long 0x64 "TESOC_SLICE_CONFIG_DOM3_n_1,Slice Configuration Register" line.long 0x68 "TESOC_SLICE_CONFIG_DOM3_n_2,Slice Configuration Register" line.long 0x6C "TESOC_SLICE_CONFIG_DOM3_n_3,Slice Configuration Register" line.long 0x70 "TESOC_SLICE_CONFIG_DOM3_n_4,Slice Configuration Register" line.long 0x74 "TESOC_SLICE_CONFIG_DOM3_n_5,Slice Configuration Register" line.long 0x78 "TESOC_SLICE_CONFIG_DOM3_n_6,Slice Configuration Register" line.long 0x7C "TESOC_SLICE_CONFIG_DOM3_n_7,Slice Configuration Register" line.long 0x80 "TESOC_SLICE_CONFIG_DOM4_n_0,Slice Configuration Register" line.long 0x84 "TESOC_SLICE_CONFIG_DOM4_n_1,Slice Configuration Register" line.long 0x88 "TESOC_SLICE_CONFIG_DOM4_n_2,Slice Configuration Register" line.long 0x8C "TESOC_SLICE_CONFIG_DOM4_n_3,Slice Configuration Register" line.long 0x90 "TESOC_SLICE_CONFIG_DOM4_n_4,Slice Configuration Register" line.long 0x94 "TESOC_SLICE_CONFIG_DOM4_n_5,Slice Configuration Register" line.long 0x98 "TESOC_SLICE_CONFIG_DOM4_n_6,Slice Configuration Register" line.long 0x9C "TESOC_SLICE_CONFIG_DOM4_n_7,Slice Configuration Register" line.long 0xA0 "TESOC_SLICE_STATUS_DOM0_n_0,Slice Completion Status Register" line.long 0xA4 "TESOC_SLICE_STATUS_DOM0_n_1,Slice Completion Status Register" line.long 0xA8 "TESOC_SLICE_STATUS_DOM0_n_2,Slice Completion Status Register" line.long 0xAC "TESOC_SLICE_STATUS_DOM0_n_3,Slice Completion Status Register" line.long 0xB0 "TESOC_SLICE_STATUS_DOM0_n_4,Slice Completion Status Register" line.long 0xB4 "TESOC_SLICE_STATUS_DOM0_n_5,Slice Completion Status Register" line.long 0xB8 "TESOC_SLICE_STATUS_DOM0_n_6,Slice Completion Status Register" line.long 0xBC "TESOC_SLICE_STATUS_DOM0_n_7,Slice Completion Status Register" line.long 0xC0 "TESOC_SLICE_STATUS_DOM1_n_0,Slice Completion Status Register" line.long 0xC4 "TESOC_SLICE_STATUS_DOM1_n_1,Slice Completion Status Register" line.long 0xC8 "TESOC_SLICE_STATUS_DOM1_n_2,Slice Completion Status Register" line.long 0xCC "TESOC_SLICE_STATUS_DOM1_n_3,Slice Completion Status Register" line.long 0xD0 "TESOC_SLICE_STATUS_DOM1_n_4,Slice Completion Status Register" line.long 0xD4 "TESOC_SLICE_STATUS_DOM1_n_5,Slice Completion Status Register" line.long 0xD8 "TESOC_SLICE_STATUS_DOM1_n_6,Slice Completion Status Register" line.long 0xDC "TESOC_SLICE_STATUS_DOM1_n_7,Slice Completion Status Register" line.long 0xE0 "TESOC_SLICE_STATUS_DOM2_n_0,Slice Completion Status Register" line.long 0xE4 "TESOC_SLICE_STATUS_DOM2_n_1,Slice Completion Status Register" line.long 0xE8 "TESOC_SLICE_STATUS_DOM2_n_2,Slice Completion Status Register" line.long 0xEC "TESOC_SLICE_STATUS_DOM2_n_3,Slice Completion Status Register" line.long 0xF0 "TESOC_SLICE_STATUS_DOM2_n_4,Slice Completion Status Register" line.long 0xF4 "TESOC_SLICE_STATUS_DOM2_n_5,Slice Completion Status Register" line.long 0xF8 "TESOC_SLICE_STATUS_DOM2_n_6,Slice Completion Status Register" line.long 0xFC "TESOC_SLICE_STATUS_DOM2_n_7,Slice Completion Status Register" line.long 0x100 "TESOC_SLICE_STATUS_DOM3_n_0,Slice Completion Status Register" line.long 0x104 "TESOC_SLICE_STATUS_DOM3_n_1,Slice Completion Status Register" line.long 0x108 "TESOC_SLICE_STATUS_DOM3_n_2,Slice Completion Status Register" line.long 0x10C "TESOC_SLICE_STATUS_DOM3_n_3,Slice Completion Status Register" line.long 0x110 "TESOC_SLICE_STATUS_DOM3_n_4,Slice Completion Status Register" line.long 0x114 "TESOC_SLICE_STATUS_DOM3_n_5,Slice Completion Status Register" line.long 0x118 "TESOC_SLICE_STATUS_DOM3_n_6,Slice Completion Status Register" line.long 0x11C "TESOC_SLICE_STATUS_DOM3_n_7,Slice Completion Status Register" line.long 0x120 "TESOC_SLICE_STATUS_DOM4_n_0,Slice Completion Status Register" line.long 0x124 "TESOC_SLICE_STATUS_DOM4_n_1,Slice Completion Status Register" line.long 0x128 "TESOC_SLICE_STATUS_DOM4_n_2,Slice Completion Status Register" line.long 0x12C "TESOC_SLICE_STATUS_DOM4_n_3,Slice Completion Status Register" line.long 0x130 "TESOC_SLICE_STATUS_DOM4_n_4,Slice Completion Status Register" line.long 0x134 "TESOC_SLICE_STATUS_DOM4_n_5,Slice Completion Status Register" line.long 0x138 "TESOC_SLICE_STATUS_DOM4_n_6,Slice Completion Status Register" line.long 0x13C "TESOC_SLICE_STATUS_DOM4_n_7,Slice Completion Status Register" line.long 0x140 "TESOC_SLICE_RESULT_DOM0_n_0,Slice Result Register" line.long 0x144 "TESOC_SLICE_RESULT_DOM0_n_1,Slice Result Register" line.long 0x148 "TESOC_SLICE_RESULT_DOM0_n_2,Slice Result Register" line.long 0x14C "TESOC_SLICE_RESULT_DOM0_n_3,Slice Result Register" line.long 0x150 "TESOC_SLICE_RESULT_DOM0_n_4,Slice Result Register" line.long 0x154 "TESOC_SLICE_RESULT_DOM0_n_5,Slice Result Register" line.long 0x158 "TESOC_SLICE_RESULT_DOM0_n_6,Slice Result Register" line.long 0x15C "TESOC_SLICE_RESULT_DOM0_n_7,Slice Result Register" line.long 0x160 "TESOC_SLICE_RESULT_DOM1_n_0,Slice Result Register" line.long 0x164 "TESOC_SLICE_RESULT_DOM1_n_1,Slice Result Register" line.long 0x168 "TESOC_SLICE_RESULT_DOM1_n_2,Slice Result Register" line.long 0x16C "TESOC_SLICE_RESULT_DOM1_n_3,Slice Result Register" line.long 0x170 "TESOC_SLICE_RESULT_DOM1_n_4,Slice Result Register" line.long 0x174 "TESOC_SLICE_RESULT_DOM1_n_5,Slice Result Register" line.long 0x178 "TESOC_SLICE_RESULT_DOM1_n_6,Slice Result Register" line.long 0x17C "TESOC_SLICE_RESULT_DOM1_n_7,Slice Result Register" line.long 0x180 "TESOC_SLICE_RESULT_DOM2_n_0,Slice Result Register" line.long 0x184 "TESOC_SLICE_RESULT_DOM2_n_1,Slice Result Register" line.long 0x188 "TESOC_SLICE_RESULT_DOM2_n_2,Slice Result Register" line.long 0x18C "TESOC_SLICE_RESULT_DOM2_n_3,Slice Result Register" line.long 0x190 "TESOC_SLICE_RESULT_DOM2_n_4,Slice Result Register" line.long 0x194 "TESOC_SLICE_RESULT_DOM2_n_5,Slice Result Register" line.long 0x198 "TESOC_SLICE_RESULT_DOM2_n_6,Slice Result Register" line.long 0x19C "TESOC_SLICE_RESULT_DOM2_n_7,Slice Result Register" line.long 0x1A0 "TESOC_SLICE_RESULT_DOM3_n_0,Slice Result Register" line.long 0x1A4 "TESOC_SLICE_RESULT_DOM3_n_1,Slice Result Register" line.long 0x1A8 "TESOC_SLICE_RESULT_DOM3_n_2,Slice Result Register" line.long 0x1AC "TESOC_SLICE_RESULT_DOM3_n_3,Slice Result Register" line.long 0x1B0 "TESOC_SLICE_RESULT_DOM3_n_4,Slice Result Register" line.long 0x1B4 "TESOC_SLICE_RESULT_DOM3_n_5,Slice Result Register" line.long 0x1B8 "TESOC_SLICE_RESULT_DOM3_n_6,Slice Result Register" line.long 0x1BC "TESOC_SLICE_RESULT_DOM3_n_7,Slice Result Register" line.long 0x1C0 "TESOC_SLICE_RESULT_DOM4_n_0,Slice Result Register" line.long 0x1C4 "TESOC_SLICE_RESULT_DOM4_n_1,Slice Result Register" line.long 0x1C8 "TESOC_SLICE_RESULT_DOM4_n_2,Slice Result Register" line.long 0x1CC "TESOC_SLICE_RESULT_DOM4_n_3,Slice Result Register" line.long 0x1D0 "TESOC_SLICE_RESULT_DOM4_n_4,Slice Result Register" line.long 0x1D4 "TESOC_SLICE_RESULT_DOM4_n_5,Slice Result Register" line.long 0x1D8 "TESOC_SLICE_RESULT_DOM4_n_6,Slice Result Register" line.long 0x1DC "TESOC_SLICE_RESULT_DOM4_n_7,Slice Result Register" rgroup.long 0x10500++0x07 line.long 0x00 "TESOC_TESOC_ROM_k_0,This MMR space maps to TESOC ROM TESOC ROM is logically 64 bit wide" line.long 0x04 "TESOC_TESOC_ROM_k_1,This MMR space maps to TESOC ROM TESOC ROM is logically 64 bit wide" width 0x0B tree.end tree "TESOC_FW" base ad:0x4A240000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" newline rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x00 1.--11. 1. "RESERVED,Reads return 0s" newline bitfld.long 0x00 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" newline bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" newline rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "TESOC_FW_CFG_TARG" base ad:0x4A241000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TESOC_TARG" base ad:0x44001300 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "TIMER1_L4_WKUPInterconnect" base ad:0x4AE18000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 1. "EMUFREE,Emulation mode" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x4F line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" hexmask.long 0x04 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" newline bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQSTATUS_SET,Component interrupt-request enable" hexmask.long 0x0C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQSTATUS_CLR,Component interrupt-request enable" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" newline bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" newline bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "TCM_0,TCM_1,TCM_2,TCM_3" newline bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable" "CE_0,CE_1" newline bitfld.long 0x18 5. "PRE,Prescaler enable" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 1. "AR,Autoreload mode" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" newline bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" newline bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "0,1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "0,1" newline bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "0,1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "0,1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "0,1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode(POSTED = '1') this bit is not used" "READ_MODE_0,READ_MODE_1" newline bitfld.long 0x34 2. "POSTED,Posted mode selection" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" newline rbitfld.long 0x34 0. "RESERVED,Reserved" "0,1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" line.long 0x3C "TPIR,This register is used for 1-ms tick generation" line.long 0x40 "TNIR,This register is used for 1-ms tick generation" line.long 0x44 "TCVR,This register is used for 1-ms tick generation" line.long 0x48 "TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.byte 0x48 24.--31. 1. "RESERVED,Reads return 0" hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x4C "TOWR,This register holds the number of masked overflow interrupts" hexmask.long.byte 0x4C 24.--31. 1. "RESERVED,Reads return 0" hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" width 0x0B tree.end tree "TIMER1_TARG" base ad:0x4AE19000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER2_L4_PER1Interconnect" base ad:0x48032000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" hexmask.long 0x04 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" hexmask.long 0x0C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "TCM_0,TCM_1,TCM_2,TCM_3" newline bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" newline bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "0,1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "0,1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "0,1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "0,1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "0,1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode(POSTED = '1') this bit is not used" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" rbitfld.long 0x34 0. "RESERVED,Reserved" "0,1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER2_TARG" base ad:0x48033000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER3_L4_PER1Interconnect" base ad:0x48034000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" hexmask.long 0x04 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" hexmask.long 0x0C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "TCM_0,TCM_1,TCM_2,TCM_3" newline bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" newline bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "0,1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "0,1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "0,1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "0,1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "0,1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode(POSTED = '1') this bit is not used" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" rbitfld.long 0x34 0. "RESERVED,Reserved" "0,1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER3_TARG" base ad:0x48035000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER4_L4_PER1Interconnect" base ad:0x48036000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" hexmask.long 0x04 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" hexmask.long 0x0C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "TCM_0,TCM_1,TCM_2,TCM_3" newline bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" newline bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "0,1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "0,1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "0,1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "0,1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "0,1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode(POSTED = '1') this bit is not used" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" rbitfld.long 0x34 0. "RESERVED,Reserved" "0,1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER4_TARG" base ad:0x48037000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER5_L4_PER3Interconnect" base ad:0x48820000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" hexmask.long 0x04 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" hexmask.long 0x0C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "TCM_0,TCM_1,TCM_2,TCM_3" newline bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" newline bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "0,1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "0,1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "0,1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "0,1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "0,1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode(POSTED = '1') this bit is not used" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" rbitfld.long 0x34 0. "RESERVED,Reserved" "0,1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER5_TARG" base ad:0x48821000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER6_L4_PER3Interconnect" base ad:0x48822000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" hexmask.long 0x04 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" hexmask.long 0x0C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "TCM_0,TCM_1,TCM_2,TCM_3" newline bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" newline bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "0,1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "0,1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "0,1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "0,1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "0,1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode(POSTED = '1') this bit is not used" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" rbitfld.long 0x34 0. "RESERVED,Reserved" "0,1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER6_TARG" base ad:0x48823000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER7_L4_PER3Interconnect" base ad:0x48824000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" hexmask.long 0x04 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" hexmask.long 0x0C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "TCM_0,TCM_1,TCM_2,TCM_3" newline bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" newline bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "0,1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "0,1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "0,1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "0,1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "0,1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode(POSTED = '1') this bit is not used" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" rbitfld.long 0x34 0. "RESERVED,Reserved" "0,1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER7_TARG" base ad:0x48825000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER8_L4_PER3Interconnect" base ad:0x48826000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" hexmask.long 0x04 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" hexmask.long 0x08 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" hexmask.long 0x0C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "TCM_0,TCM_1,TCM_2,TCM_3" newline bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" hexmask.long.tbyte 0x28 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" newline bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "0,1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "0,1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "0,1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "0,1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "0,1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode(POSTED = '1') this bit is not used" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" rbitfld.long 0x34 0. "RESERVED,Reserved" "0,1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER8_TARG" base ad:0x48827000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TPTC1_TARG" base ad:0x44002E00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "TPTC2_TARG" base ad:0x44002B00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline rbitfld.long 0x08 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," hexmask.long 0x04 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline hexmask.long.word 0x08 20.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline hexmask.long.word 0x08 2.--17. 1. "RESERVED,Reserved" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," bitfld.long 0x0C 28.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 4.--5. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," hexmask.long 0x20 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," hexmask.long 0x00 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "TPTC_FW" base ad:0x4A163000 group.long 0x00++0x03 line.long 0x00 "ERROR_LOG_k_0,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" group.long 0x10++0x03 line.long 0x00 "ERROR_LOG_k_1,Error log register for port k" hexmask.long.byte 0x00 24.--31. 1. "RESERVED,Reads return 0s" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" rbitfld.long 0x00 22. "RESERVED,Reads return 0s" "0,1" newline bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" rgroup.long 0x04++0x03 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k_0,Logical Physical Address Error log register for port k" rgroup.long 0x14++0x03 line.long 0x00 "LOGICAL_ADDR_ERRLOG_k_1,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" hexmask.long.word 0x00 20.--31. 1. "RESERVED,Reads return 0s" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "0,1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x90++0x07 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 12.--31. 1. "START_REGION_i,Physical target start address of firewall region i" hexmask.long.word 0x00 0.--11. 1. "RESERVED,Reads return 0s" line.long 0x04 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x04 12.--31. 1. "END_REGION_i,Physical target end address of firewall region i" hexmask.long.word 0x04 1.--11. 1. "RESERVED,Reads return 0s" bitfld.long 0x04 0. "END_REGION_i_ENABLE,Enable this region" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" hexmask.long.word 0x00 16.--31. 1. "RESERVED,RESERVED" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline rbitfld.long 0x00 12.--13. "RESERVED,RESERVED" "0,1,2,3" bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" rbitfld.long 0x00 0.--5. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" newline bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" newline bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" newline bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "TSC_ADC_CFG_TARG" base ad:0x4A265000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TSC_ADC_FW_CFG_TARG" base ad:0x4A16E000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end repeat 3. (list 3. 1. 2. )(list ad:0x48020000 ad:0x4806A000 ad:0x4806C000 ) tree "UART$1" base $2 group.long 0x00++0x03 line.long 0x00 "UART_DLL,This register. with. stores the 14-bit divisor for generation of the baud clock in the baud rate generator" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x00 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value" rgroup.long 0x00++0x03 line.long 0x00 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x00 0.--7. 1. "RHR,Receive holding register" group.long 0x00++0x07 line.long 0x00 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Write has no effect" newline hexmask.long.byte 0x00 0.--7. 1. "THR,Transmit holding register" line.long 0x04 "UART_DLH,This register. with. stores the 14-bit divisor for generating the baud clock in the baud rate generator" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x04 6.--7. "RESERVED,Read returns 0" "0,1,2,3" newline bitfld.long 0x04 0.--5. "CLOCK_MSB,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x04++0x07 line.long 0x00 "UART_IER,Interrupt enable register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 7. "CTS_IT," "CTS_IT_0,CTS_IT_1" newline bitfld.long 0x00 6. "RTS_IT," "RTS_IT_0,RTS_IT_1" newline bitfld.long 0x00 5. "XOFF_IT," "XOFF_IT_0,XOFF_IT_1" newline bitfld.long 0x00 4. "SLEEP_MODE," "SLEEP_MODE_0,SLEEP_MODE_1" newline bitfld.long 0x00 3. "MODEM_STS_IT," "MODEM_STS_IT_0,MODEM_STS_IT_1" newline bitfld.long 0x00 2. "LINE_STS_IT," "LINE_STS_IT_0,LINE_STS_IT_1" newline bitfld.long 0x00 1. "THR_IT," "THR_IT_0,THR_IT_1" newline bitfld.long 0x00 0. "RHR_IT," "RHR_IT_0,RHR_IT_1" line.long 0x04 "UART_EFR,Enhanced feature register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x04 7. "AUTO_CTS_EN,Auto-CTS enable bit" "AUTO_CTS_EN_0,AUTO_CTS_EN_1" newline bitfld.long 0x04 6. "AUTO_RTS_EN,Auto-RTS enable bit" "AUTO_RTS_EN_0,AUTO_RTS_EN_1" newline bitfld.long 0x04 5. "SPECIAL_CHAR_DETECT," "SPECIAL_CHAR_DETECT_0,SPECIAL_CHAR_DETECT_1" newline bitfld.long 0x04 4. "ENHANCED_EN,Enhanced functions write enable bit" "ENHANCED_EN_0,ENHANCED_EN_1" newline bitfld.long 0x04 0.--3. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x08++0x03 line.long 0x00 "UART_FCR,FIFO control register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Write has no effect" newline bitfld.long 0x00 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If UART_SCR[7] = 0 and UART_TLR[7:4] =" "8 characters,16 characters,56 characters,60 characters If UART_SCR[7] = 0 and.." newline bitfld.long 0x00 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If UART_SCR[6] = 0 and UART_TLR[3:0] =" "8 spaces,16 spaces,32 spaces,56 spaces If UART_SCR[6].." newline bitfld.long 0x00 3. "DMA_MODE,This register is considered ifUART_SCR[0] = 0" "DMA_MODE_0_w,DMA_MODE_1_w" newline bitfld.long 0x00 2. "TX_FIFO_CLEAR," "TX_FIFO_CLEAR_0_w,TX_FIFO_CLEAR_1_w" newline bitfld.long 0x00 1. "RX_FIFO_CLEAR," "RX_FIFO_CLEAR_0_w,RX_FIFO_CLEAR_1_w" newline bitfld.long 0x00 0. "FIFO_EN," "FIFO_EN_0_w,FIFO_EN_1_w" rgroup.long 0x08++0x0B line.long 0x00 "UART_IIR,Interrupt identification register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 6.--7. "FCR_MIRROR,Mirror the contents ofUART_FCR[0] on both bits" "0,1,2,3" newline bitfld.long 0x00 1.--5. "IT_TYPE," "?,IT_TYPE_1_r,IT_TYPE_2_r,IT_TYPE_3_r,?,?,IT_TYPE_6_r,?,IT_TYPE_8_r,?,?,?,?,?,?,?,IT_TYPE_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 0. "IT_PENDING," "?,IT_PENDING_1_r" line.long 0x04 "UART_LCR,Line control register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x04 7. "DIV_EN," "DIV_EN_0,DIV_EN_1" newline bitfld.long 0x04 6. "BREAK_EN,Break control bit" "BREAK_EN_0,BREAK_EN_1" newline bitfld.long 0x04 5. "PARITY_TYPE2,Selects the forced parity format (ifUART_LCR[3] = 1)" "0,1" newline bitfld.long 0x04 4. "PARITY_TYPE1," "PARITY_TYPE1_0,PARITY_TYPE1_1" newline bitfld.long 0x04 3. "PARITY_EN," "?,PARITY_EN_1" newline bitfld.long 0x04 2. "NB_STOP,Specifies the number of stop-bits" "NB_STOP_0,NB_STOP_1" newline bitfld.long 0x04 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "CHAR_LENGTH_0,CHAR_LENGTH_1,CHAR_LENGTH_2,CHAR_LENGTH_3" line.long 0x08 "UART_MCR,Modem control register" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 7. "RESERVED,Read returns 0" "0,1" newline bitfld.long 0x08 6. "TCR_TLR," "?,TCR_TLR_1" newline bitfld.long 0x08 5. "XON_EN," "?,XON_EN_1" newline bitfld.long 0x08 4. "LOOPBACK_EN," "?,LOOPBACK_EN_1" newline bitfld.long 0x08 3. "CD_STS_CH," "?,CD_STS_CH_1" newline bitfld.long 0x08 2. "RI_STS_CH," "?,RI_STS_CH_1" newline bitfld.long 0x08 1. "RTS,In loopback controls theUART_MSR[4] bit" "RTS_0,RTS_1" newline bitfld.long 0x08 0. "DTR," "?,DTR_1" group.long 0x10++0x07 line.long 0x00 "UART_XON1_ADDR1,UART mode: XON1 character" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x00 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes" line.long 0x04 "UART_LSR,Line status register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x04 7. "RX_FIFO_STS," "?,RX_FIFO_STS_1_r" newline bitfld.long 0x04 6. "TX_SR_E," "?,TX_SR_E_1_r" newline bitfld.long 0x04 5. "TX_FIFO_E," "?,TX_FIFO_E_1_r" newline bitfld.long 0x04 4. "RX_BI," "?,RX_BI_1_r" newline bitfld.long 0x04 3. "RX_FE," "?,RX_FE_1_r" newline bitfld.long 0x04 2. "RX_PE," "?,RX_PE_1_r" newline bitfld.long 0x04 1. "RX_OE," "?,RX_OE_1_r" newline bitfld.long 0x04 0. "RX_FIFO_E," "?,RX_FIFO_E_1_r" group.long 0x14++0x07 line.long 0x00 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x00 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes" line.long 0x04 "UART_MSR,Modem status register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x04 7. "NCD_STS,This bit is the complement of the DCD* input" "0,1" newline bitfld.long 0x04 6. "NRI_STS,This bit is the complement of the RI* input" "0,1" newline bitfld.long 0x04 5. "NDSR_STS,This bit is the complement of the DSR* input" "0,1" newline bitfld.long 0x04 4. "NCTS_STS,This bit is the complement of the CTS* input" "0,1" newline bitfld.long 0x04 3. "DCD_STS,Indicates that DCD* input (orUART_MCR[3] in loopback) changed" "0,1" newline bitfld.long 0x04 2. "RI_STS,Indicates that RI* input (orUART_MCR[2] in loopback) changed state from low to high" "0,1" newline bitfld.long 0x04 1. "DSR_STS," "?,DSR_STS_1_r" newline bitfld.long 0x04 0. "CTS_STS," "?,CTS_STS_1_r" group.long 0x18++0x03 line.long 0x00 "UART_TCR,Transmission control register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x07 line.long 0x00 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes" line.long 0x04 "UART_SPR,Scratchpad register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x04 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x03 line.long 0x00 "UART_TLR,Trigger level register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x07 line.long 0x00 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes" line.long 0x04 "UART_MDR1,Mode definition register 1" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x04 7. "FRAME_END_MODE,Reserved" "0,1" newline bitfld.long 0x04 6. "SIP_MODE,Reserved" "0,1" newline bitfld.long 0x04 5. "SCT,Reserved" "0,1" newline bitfld.long 0x04 4. "SET_TXIR,Reserved" "0,1" newline bitfld.long 0x04 3. "IR_SLEEP,Reserved" "0,1" newline bitfld.long 0x04 0.--2. "MODE_SELECT," "?,MODE_SELECT_1,MODE_SELECT_2,MODE_SELECT_3,MODE_SELECT_4,MODE_SELECT_5,MODE_SELECT_6,MODE_SELECT_7" rgroup.long 0x38++0x03 line.long 0x00 "UART_UASR,UART autobauding status register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 6.--7. "PARITY_TYPE," "?,PARITY_TYPE_1_r,PARITY_TYPE_2_r,PARITY_TYPE_3_r" newline bitfld.long 0x00 5. "BIT_BY_CHAR," "?,BIT_BY_CHAR_1_r" newline bitfld.long 0x00 0.--4. "SPEED,Used to report the speed identified" "SPEED_0_r,SPEED_1_r,SPEED_2_r,SPEED_3_r,SPEED_4_r,SPEED_5_r,SPEED_6_r,SPEED_7_r,SPEED_8_r,SPEED_9_r,SPEED_10_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x40++0x07 line.long 0x00 "UART_SCR,Supplementary control register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 7. "RX_TRIG_GRANU1," "?,RX_TRIG_GRANU1_1" newline bitfld.long 0x00 6. "TX_TRIG_GRANU1," "?,TX_TRIG_GRANU1_1" newline bitfld.long 0x00 5. "DSR_IT,NOT USED IN THIS DEVICE" "0,1" newline bitfld.long 0x00 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "?,RX_CTS_DSR_WAKE_UP_ENABLE_1" newline bitfld.long 0x00 3. "TX_EMPTY_CTL_IT," "?,TX_EMPTY_CTL_IT_1" newline bitfld.long 0x00 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if theUART_SCR[0] bit = 1" "DMA_MODE_2_0,DMA_MODE_2_1,DMA_MODE_2_2,DMA_MODE_2_3" newline bitfld.long 0x00 0. "DMA_MODE_CTL," "?,DMA_MODE_CTL_1" line.long 0x04 "UART_SSR,Supplementary status register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline rbitfld.long 0x04 3.--7. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 2. "DMA_COUNTER_RST," "?,DMA_COUNTER_RST_1" newline rbitfld.long 0x04 1. "RX_CTS_DSR_WAKE_UP_STS," "?,RX_CTS_DSR_WAKE_UP_STS_1_r" newline rbitfld.long 0x04 0. "TX_FIFO_FULL," "?,TX_FIFO_FULL_1_r" rgroup.long 0x50++0x0F line.long 0x00 "UART_MVR,Module version register" line.long 0x04 "UART_SYSC,System configuration register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline rbitfld.long 0x04 5.--7. "RESERVED,Read returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 3.--4. "IDLEMODE,Power management req/ack control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x04 2. "ENAWAKEUP,Wake-up feature control" "ENAWAKEUP_0,ENAWAKEUP_1" newline bitfld.long 0x04 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x04 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x08 "UART_SYSS,System status register" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x0C "UART_WER,Wake-up enable register" hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x0C 7. "TX_WAKEUP_EN," "?,TX_WAKEUP_EN_1" newline bitfld.long 0x0C 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "?,EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_1" newline bitfld.long 0x0C 5. "EVENT_5_RHR_INTERRUPT," "?,EVENT_5_RHR_INTERRUPT_1" newline bitfld.long 0x0C 4. "EVENT_4_RX_ACTIVITY," "?,EVENT_4_RX_ACTIVITY_1" newline bitfld.long 0x0C 3. "EVENT_3_DCD_CD_ACTIVITY," "?,EVENT_3_DCD_CD_ACTIVITY_1" newline bitfld.long 0x0C 2. "EVENT_2_RI_ACTIVITY," "?,EVENT_2_RI_ACTIVITY_1" newline bitfld.long 0x0C 1. "EVENT_1_DSR_ACTIVITY," "?,EVENT_1_DSR_ACTIVITY_1" newline bitfld.long 0x0C 0. "EVENT_0_CTS_ACTIVITY," "?,EVENT_0_CTS_ACTIVITY_1" rgroup.long 0x64++0x13 line.long 0x00 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x00 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO" line.long 0x04 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x04 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO" line.long 0x08 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" hexmask.long 0x08 2.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "EN_TXFIFO_EMPTY_0,EN_TXFIFO_EMPTY_1" newline bitfld.long 0x08 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "EN_RXFIFO_EMPTY_0,EN_RXFIFO_EMPTY_1" line.long 0x0C "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" hexmask.long 0x0C 2.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x0C 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "TXFIFO_EMPTY_STS_0,TXFIFO_EMPTY_STS_1" newline bitfld.long 0x0C 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "RXFIFO_EMPTY_STS_0,RXFIFO_EMPTY_STS_1" line.long 0x10 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Read returns 0" newline hexmask.long.byte 0x10 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used.UART_MDR3[1] must be set to 1 after this value is set" group.long 0x80++0x07 line.long 0x00 "UART_MDR3,Mode definition register 3" hexmask.long 0x00 3.--31. 1. "RESERVED,Read returns 0" newline bitfld.long 0x00 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold inUART_TX_DMA_THRESHOLD register" "0,1" newline bitfld.long 0x00 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies" "NONDEFAULT_FREQ_0,NONDEFAULT_FREQ_1" newline bitfld.long 0x00 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation" "DISABLE_CIR_RX_DEMOD_0,DISABLE_CIR_RX_DEMOD_1" line.long 0x04 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level" hexmask.long 0x04 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0.--5. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end repeat.end tree "UART1_TARG" base ad:0x4806B000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "UART2_TARG" base ad:0x4806D000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "UART3_TARG" base ad:0x48021000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "VENC" base ad:0x58005000 rgroup.long 0x00++0x0B line.long 0x00 "VENC_REV_ID,Revision ID for the encoder" line.long 0x04 "VENC_STATUS,STATUS" hexmask.long 0x04 5.--31. 1. "RESERVED," bitfld.long 0x04 4. "CCE,Closed Caption Status for Even Field" "0,1" bitfld.long 0x04 3. "CCO,Closed Caption Status for Odd Field" "0,1" newline bitfld.long 0x04 0.--2. "FSQ,Field Sequence ID" "FSQ_0_r,FSQ_1_r,?,?,?,?,?,?" line.long 0x08 "VENC_F_CONTROL,This register specifies the input video source and format" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED," bitfld.long 0x08 8. "RESET,RESET the encoder" "RESET_0,RESET_1" bitfld.long 0x08 6.--7. "SVDS,Select Video Data Source" "SVDS_0,SVDS_1,SVDS_2,SVDS_3" newline bitfld.long 0x08 5. "RGBF,RGB /YCrCb input coding range" "RGBF_0,RGBF_1" bitfld.long 0x08 2.--4. "BCOLOR,Background color select" "BCOLOR_0,BCOLOR_1,BCOLOR_2,BCOLOR_3,BCOLOR_4,BCOLOR_5,BCOLOR_6,BCOLOR_7" bitfld.long 0x08 0.--1. "FMT,These two bits specify the video input data stream format and timing" "FMT_0,FMT_1,FMT_2,FMT_3" group.long 0x10++0x07 line.long 0x00 "VENC_VIDOUT_CTRL,Encoder output clock" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "MHZ_27_54,Encoder output clock" "MHZ_27_54_0,MHZ_27_54_1" line.long 0x04 "VENC_SYNC_CTRL,SYNC Control register" hexmask.long.word 0x04 16.--31. 1. "RESERVED,reserved_5" bitfld.long 0x04 15. "FREE,Free running" "FREE_0,FREE_1" bitfld.long 0x04 14. "ESAV,Enable to detect F and V bits only on EAV in ITU-R 656 input mode" "ESAV_0,ESAV_1" newline bitfld.long 0x04 13. "IGNP,Ignore protection bits in ITU-R 656 input mode" "IGNP_0,IGNP_1" bitfld.long 0x04 12. "NBLNKS,Blank shaping" "NBLNKS_0,NBLNKS_1" bitfld.long 0x04 10.--11. "VBLKM,Vertical blanking mode" "VBLKM_0,VBLKM_1,VBLKM_2,VBLKM_3" newline bitfld.long 0x04 8.--9. "HBLKM,Horizontal blanking mode" "HBLKM_0,HBLKM_1,HBLKM_2,HBLKM_3" bitfld.long 0x04 7. "M_S,Encoder is master or slave of external sync" "M_S_0,M_S_1" bitfld.long 0x04 6. "FID_POL,FID output polarity" "FID_POL_0,FID_POL_1" newline rbitfld.long 0x04 4.--5. "RESERVED," "0,1,2,3" bitfld.long 0x04 3. "VS_POL,VS input polarity" "VS_POL_0,VS_POL_1" bitfld.long 0x04 2. "HS_POL,HS input polarity" "HS_POL_0,HS_POL_1" newline rbitfld.long 0x04 1. "RESERVED," "0,1" bitfld.long 0x04 0. "FHVMOD,FID extracted from external FID or HSYNC and VSYNC" "FHVMOD_0,FHVMOD_1" group.long 0x1C++0x6F line.long 0x00 "VENC_LLEN,LLEN" hexmask.long.word 0x00 16.--31. 1. "RESERVED," bitfld.long 0x00 15. "LLEN_EN,LLEN_EN" "LLEN_EN_0,LLEN_EN_1" rbitfld.long 0x00 11.--14. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. "LLEN,LLEN[10:0] Line length or total number of pixels in a scan line including active video and blanking" line.long 0x04 "VENC_FLENS,FLENS" hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED," hexmask.long.word 0x04 0.--10. 1. "FLENS,The frame length or total number of lines in a frame including active video and blanking from the source image" line.long 0x08 "VENC_HFLTR_CTRL,HFLTR_CTRL" hexmask.long 0x08 3.--31. 1. "RESERVED," bitfld.long 0x08 1.--2. "CINTP,Chrominance interpolation filter control" "CINTP_0,CINTP_1,CINTP_2,CINTP_3" bitfld.long 0x08 0. "YINTP,Luminance interpolation filter control" "YINTP_0,YINTP_1" line.long 0x0C "VENC_CC_CARR_WSS_CARR,Frequencie code control" hexmask.long.word 0x0C 16.--31. 1. "FWSS,Wide screen signaling run-in code frequency control" hexmask.long.word 0x0C 0.--15. 1. "FCC,Close caption run-in code frequency control" line.long 0x10 "VENC_C_PHASE,C_PHASE" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED," hexmask.long.byte 0x10 0.--7. 1. "CPHS,Phase of the encoded video color subcarrier (including the color burst) relative to H-sync" line.long 0x14 "VENC_GAIN_U,Gain control for Cb signal" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED," hexmask.long.word 0x14 0.--8. 1. "GU,Gain control for Cb signal" line.long 0x18 "VENC_GAIN_V,Gain control of Cr signal" hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED," hexmask.long.word 0x18 0.--8. 1. "GV,Gain control of Cr signal" line.long 0x1C "VENC_GAIN_Y,Gain control of Y signal" hexmask.long.tbyte 0x1C 9.--31. 1. "RESERVED," hexmask.long.word 0x1C 0.--8. 1. "GY,Gain control of Y signal" line.long 0x20 "VENC_BLACK_LEVEL,BLACK LEVEL" hexmask.long 0x20 7.--31. 1. "RESERVED," hexmask.long.byte 0x20 0.--6. 1. "BLACK,Black level setting" line.long 0x24 "VENC_BLANK_LEVEL,BLANK LEVEL" hexmask.long 0x24 7.--31. 1. "RESERVED," hexmask.long.byte 0x24 0.--6. 1. "BLANK,Blank level setting" line.long 0x28 "VENC_X_COLOR,Cross-Colour Control register" hexmask.long 0x28 7.--31. 1. "RESERVED," bitfld.long 0x28 6. "XCE,Cross color reduction enable for composite video output" "XCE_0,XCE_1" rbitfld.long 0x28 5. "RESERVED," "0,1" newline bitfld.long 0x28 3.--4. "XCBW,Cross color reduction filter selection" "XCBW_0,XCBW_1,XCBW_2,XCBW_3" bitfld.long 0x28 0.--2. "LCD,These three bits can be used for chroma channel delay compensation" "LCD_0,LCD_1,LCD_2,LCD_3,LCD_4,LCD_5,LCD_6,LCD_7" line.long 0x2C "VENC_M_CONTROL,M_CONTROL" hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 7. "PALI,PAL I enable" "PALI_0,PALI_1" bitfld.long 0x2C 6. "PALN,PAL N Enable" "PALN_0,PALN_1" newline bitfld.long 0x2C 5. "PALPHS,PAL switch phase setting" "PALPHS_0,PALPHS_1" bitfld.long 0x2C 2.--4. "CBW,Chrominance lowpass filter bandwidth control" "CBW_0,CBW_1,CBW_2,CBW_3,CBW_4,CBW_5,CBW_6,CBW_7" bitfld.long 0x2C 1. "PAL,Phase alternation line encoding selection" "PAL_0,PAL_1" newline bitfld.long 0x2C 0. "FFRQ,The value of this field and the SQP bit in the BSTAMP_WSS_DATA register control the number of horizontal pixels displayed per scan line # OF MODE SQP FFRQ PIXEL PER LINE ITU-R 601 NTSC 0 1 858 Square pixel NTSC 1 1 780 ITU-R 601 PAL 0 0 864 Square.." "0,1" line.long 0x30 "VENC_BSTAMP_WSS_DATA,BSTAMP and WSS_DATA" rbitfld.long 0x30 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x30 8.--27. 1. "WSS_D,Wide Screen Signaling data NTSC: WORD 0 D0 D1 WORD 1 D2 D3 D4 D5 WORD 2 D6 D7 D8 D9 D10 D11 D12 D13 CRC D14 D15 D16 D17 D18 D19 PAL: GROUP A D0 D1 D2 D3 GROUP B D4 D5 D6 D7 GROUP C D8 D9 D10 GROUP D D11 D12 D13" bitfld.long 0x30 7. "SQP,Square-pixel sampling rate" "SQP_0,SQP_1" newline hexmask.long.byte 0x30 0.--6. 1. "BSTAP,Setting of amplitude of color burst" line.long 0x34 "VENC_S_CARR,Color Subcarrier Frequency Registers" line.long 0x38 "VENC_LINE21,LINE 21" hexmask.long.word 0x38 16.--31. 1. "L21E,The two bytes of the closed caption data in the even field.For the data stream content see" hexmask.long.word 0x38 0.--15. 1. "L21O,The two bytes of the closed caption data in the odd fieldFor the data stream content see" line.long 0x3C "VENC_LN_SEL,LN_SEL" rbitfld.long 0x3C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x3C 16.--25. 1. "LN21_RUNIN,The two Bytes of the closed caption runin code position from the HSYNC" hexmask.long.word 0x3C 5.--15. 1. "RESERVED," newline bitfld.long 0x3C 0.--4. "SLINE,Selects the line where closed caption or extended service data are encoded.PAL mode: Because there is a one-line offset program the desired line number - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "VENC_L21_WC_CTL,L21 and WC_CTL registers" hexmask.long.word 0x40 16.--31. 1. "RESERVED," bitfld.long 0x40 15. "INV,WSS inverter" "INV_0,INV_1" bitfld.long 0x40 13.--14. "EVEN_ODD_EN,This bit controls the WSS encoding" "EVEN_ODD_EN_0,EVEN_ODD_EN_1,EVEN_ODD_EN_2,EVEN_ODD_EN_3" newline bitfld.long 0x40 8.--12. "LINE,Selects the line where WSS data are encoded.PAL mode: Because there is a one-line offset program the desired line number - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x40 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 0.--1. "L21EN,Those bits controls the Line21 closed caption encoding according to the mode" "L21EN_0,L21EN_1,L21EN_2,L21EN_3" line.long 0x44 "VENC_HTRIGGER_VTRIGGER,HTRIGGER and VTRIGGER" rbitfld.long 0x44 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x44 16.--25. 1. "VTRIG,Vertical trigger reference for VSYNC" rbitfld.long 0x44 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x44 0.--10. 1. "HTRIG,Horizontal trigger phase which sets HSYNC" line.long 0x48 "VENC_SAVID_EAVID,SAVID and EAVID" rbitfld.long 0x48 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x48 16.--26. 1. "EAVID,End of active video" rbitfld.long 0x48 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 0.--10. 1. "SAVID,Start of active video" line.long 0x4C "VENC_FLEN_FAL,FLEN and FAL" hexmask.long.byte 0x4C 25.--31. 1. "RESERVED," hexmask.long.word 0x4C 16.--24. 1. "FAL,First Active Line of Field" rbitfld.long 0x4C 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x4C 0.--9. 1. "FLEN,Field length" line.long 0x50 "VENC_LAL_PHASE_RESET,LAL and PHASE_RESET" hexmask.long.word 0x50 19.--31. 1. "RESERVED," bitfld.long 0x50 17.--18. "PRES,Phase reset mode" "PRES_0,PRES_1,PRES_2,PRES_3" bitfld.long 0x50 16. "SBLANK,Vertical blanking setting" "SBLANK_0,SBLANK_1" newline hexmask.long.byte 0x50 9.--15. 1. "RESERVED," hexmask.long.word 0x50 0.--8. 1. "LAL,Last Active Line of Field" line.long 0x54 "VENC_HS_INT_START_STOP_X,HS_INT_START_STOP_X" rbitfld.long 0x54 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x54 16.--25. 1. "HS_INT_STOP_X,HSYNC internal stop" rbitfld.long 0x54 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x54 0.--9. 1. "HS_INT_START_X,HSYNC internal start" line.long 0x58 "VENC_HS_EXT_START_STOP_X,HS_EXT_START_STOP_X" rbitfld.long 0x58 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x58 16.--25. 1. "HS_EXT_STOP_X,HSYNC external stop" rbitfld.long 0x58 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x58 0.--9. 1. "HS_EXT_START_X,HSYNC external start" line.long 0x5C "VENC_VS_INT_START_X,VS_INT_START_X" rbitfld.long 0x5C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x5C 16.--25. 1. "VS_INT_START_X,VSYNC internal start" hexmask.long.word 0x5C 0.--15. 1. "RESERVED," line.long 0x60 "VENC_VS_INT_STOP_X_VS_INT_START_Y,VS_INT_STOP_X and VS_INT_START_Y" rbitfld.long 0x60 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x60 16.--25. 1. "VS_INT_START_Y,VSYNC internal start" rbitfld.long 0x60 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x60 0.--9. 1. "VS_INT_STOP_X,VSYNC internal stop" line.long 0x64 "VENC_VS_INT_STOP_Y_VS_EXT_START_X,VS_INT_STOP_Y and VS_EXT_START_X" rbitfld.long 0x64 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x64 16.--25. 1. "VS_EXT_START_X,VSYNC external start" rbitfld.long 0x64 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x64 0.--9. 1. "VS_INT_STOP_Y,VSYNC internal stop" line.long 0x68 "VENC_VS_EXT_STOP_X_VS_EXT_START_Y,VS_EXT_STOP_X and VS_EXT_START_Y" rbitfld.long 0x68 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x68 16.--25. 1. "VS_EXT_START_Y,VSYNC external start" rbitfld.long 0x68 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x68 0.--9. 1. "VS_EXT_STOP_X,VSYNC external stop" line.long 0x6C "VENC_VS_EXT_STOP_Y,VS_EXT_STOP_Y" hexmask.long.tbyte 0x6C 10.--31. 1. "RESERVED," hexmask.long.word 0x6C 0.--9. 1. "VS_EXT_STOP_Y,VSYNC external stop" group.long 0x90++0x07 line.long 0x00 "VENC_AVID_START_STOP_X,AVID_START_STOP_X" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "AVID_STOP_X,AVID stop" rbitfld.long 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--9. 1. "AVID_START_X,AVID start" line.long 0x04 "VENC_AVID_START_STOP_Y,AVID_START_STOP_Y" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x04 16.--25. 1. "AVID_STOP_Y,AVID stop" rbitfld.long 0x04 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x04 0.--9. 1. "AVID_START_Y,AVID start" group.long 0xA0++0x0B line.long 0x00 "VENC_FID_INT_START_X_FID_INT_START_Y,FID_INT_START_X and FID_INT_START_Y" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "FID_INT_START_Y,FID internal stop" rbitfld.long 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--9. 1. "FID_INT_START_X,FID internal start" line.long 0x04 "VENC_FID_INT_OFFSET_Y_FID_EXT_START_X,FID_INT_OFFSET_Y and FID_EXT_START_X" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x04 16.--25. 1. "FID_EXT_START_X,FID external start" rbitfld.long 0x04 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x04 0.--9. 1. "FID_INT_OFFSET_Y,FID internal offset" line.long 0x08 "VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y,FID_EXT_START_Y and FID_EXT_OFFSET_Y" rbitfld.long 0x08 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x08 16.--25. 1. "FID_EXT_OFFSET_Y,FID external offset" rbitfld.long 0x08 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x08 0.--9. 1. "FID_EXT_START_Y,FID external start" group.long 0xB0++0x0B line.long 0x00 "VENC_TVDETGP_INT_START_STOP_X,TVDETGP_INT_START_STOP_X" rbitfld.long 0x00 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "TVDETGP_INT_STOP_X,TVDETGP internal stop" rbitfld.long 0x00 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--9. 1. "TVDETGP_INT_START_X,TVDETGP internal start" line.long 0x04 "VENC_TVDETGP_INT_START_STOP_Y,TVDETGP_INT_START_STOP_Y" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x04 16.--25. 1. "TVDETGP_INT_STOP_Y,TVDETGP internal stop" rbitfld.long 0x04 10.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x04 0.--9. 1. "TVDETGP_INT_START_Y,TVDETGP internal start" line.long 0x08 "VENC_GEN_CTRL,TVDETGP enable and SYNC_POLARITY and UVPHASE_POL" rbitfld.long 0x08 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 26. "MS,UVPHASE_POL MS mode UV phase" "MS_0,MS_1" bitfld.long 0x08 25. "UVPHASE_POL_656,UVPHASE_POL 656 input mode UV phase" "UVPHASE_POL_656_0,UVPHASE_POL_656_1" newline bitfld.long 0x08 24. "CBAR,UVPHASE_POL CBAR mode UV phase" "CBAR_0,CBAR_1" bitfld.long 0x08 23. "HIP,HSYNC internal polarity" "HIP_0,HIP_1" bitfld.long 0x08 22. "VIP,VSYNC internal polarity" "VIP_0,VIP_1" newline bitfld.long 0x08 21. "HEP,HSYNC external polarity" "HEP_0,HEP_1" bitfld.long 0x08 20. "VEP,VSYNC externall polarity" "VEP_0,VEP_1" bitfld.long 0x08 19. "AVIDP,AVID polarity" "AVIDP_0,AVIDP_1" newline bitfld.long 0x08 18. "FIP,FID internal polarity" "FIP_0,FIP_1" bitfld.long 0x08 17. "FEP,FID external polarity" "FEP_0,FEP_1" bitfld.long 0x08 16. "TVDP,TVDETGP polarity" "TVDP_0,TVDP_1" newline hexmask.long.word 0x08 1.--15. 1. "RESERVED," bitfld.long 0x08 0. "EN,TVDETGP generation enable" "EN_0,EN_1" group.long 0xC4++0x07 line.long 0x00 "VENC_OUTPUT_CONTROL,Output channel control register Also contains some test control features" hexmask.long 0x00 7.--31. 1. "RESERVED," bitfld.long 0x00 6. "COMPOSITE_SOURCE,Source of composite video data in test mode" "COMPOSITE_SOURCE_0,COMPOSITE_SOURCE_1" bitfld.long 0x00 5. "RESERVED," "0,1" newline bitfld.long 0x00 4. "TEST_MODE,This enables the video DACs to be tested" "TEST_MODE_0,TEST_MODE_1" bitfld.long 0x00 3. "VIDEO_INVERT,Controls the video output polarity" "VIDEO_INVERT_0,VIDEO_INVERT_1" bitfld.long 0x00 2. "RESERVED," "0,1" newline bitfld.long 0x00 1. "COMPOSITE_ENABLE,Enable the Composite output channel" "COMPOSITE_ENABLE_0,COMPOSITE_ENABLE_1" bitfld.long 0x00 0. "RESERVED," "0,1" line.long 0x04 "VENC_OUTPUT_TEST,Test values for the Luma/Composite Video DAC" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," hexmask.long.word 0x04 0.--9. 1. "COMPOSITE_TEST,In test mode DAC input value (if composite video is selected)" width 0x0B tree.end tree "VIP_Slice0_csc" base ad:0x48975700 group.long 0x00++0x17 line.long 0x00 "VIP_CSC00," bitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "B0,Coefficients of color space converter" bitfld.long 0x00 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--12. 1. "A0,Coefficients of color space converter" line.long 0x04 "VIP_CSC01," bitfld.long 0x04 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 16.--28. 1. "A1,Coefficients of color space converter" bitfld.long 0x04 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 0.--12. 1. "C0,Coefficients of color space converter" line.long 0x08 "VIP_CSC02," bitfld.long 0x08 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 16.--28. 1. "C1,Coefficients of color space converter" bitfld.long 0x08 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--12. 1. "B1,Coefficients of color space converter" line.long 0x0C "VIP_CSC03," bitfld.long 0x0C 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 16.--28. 1. "B2,Coefficients of color space converter" bitfld.long 0x0C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 0.--12. 1. "A2,Coefficients of color space converter" line.long 0x10 "VIP_CSC04," bitfld.long 0x10 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x10 16.--27. 1. "D0,Coefficients of color space converter" bitfld.long 0x10 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--12. 1. "C2,Coefficients of color space converter" line.long 0x14 "VIP_CSC05," bitfld.long 0x14 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x14 28. "BYPASS,Full CSC bypass mode" "0,1" hexmask.long.word 0x14 16.--27. 1. "D2,Coefficients of color space converter" bitfld.long 0x14 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x14 0.--11. 1. "D1,Coefficients of color space converter" width 0x0B tree.end tree "VIP_Slice0_parser" base ad:0x48975500 group.long 0x00++0xE7 line.long 0x00 "VIP_MAIN,ain Configuration for VIP Parser" hexmask.long 0x00 6.--31. 1. "RESERVED," newline bitfld.long 0x00 5. "CLIP_ACTIVE,Discrete Sync Only" "Do not clip active pixels,Clip Active Pixels as follows" newline bitfld.long 0x00 4. "CLIP_BLNK,Discrete Sync Only" "Do not clip Blanking Data,Clip Blanking Data as follows" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 0.--1. "DATA_INTERFACE_MODE," "?,16b data interface,Dual independent 8b data interfaces,Undefined" line.long 0x04 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x04 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "Ignore the protection bits in the XV (fvh)..,Use the protection bits in an attempt to do.." newline bitfld.long 0x04 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "For 2x/4x mux mode srcnum is in the least..,For 2x/4x mux mode srcnum is in the least.." newline bitfld.long 0x04 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. "SW_RESET," "0,1" newline bitfld.long 0x04 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "Normal Discrete Mode,Basic Discrete Mode" newline bitfld.long 0x04 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "Use HSYNC style line capture,Use ACTVID style line capture" newline bitfld.long 0x04 14. "FID_DETECT_MODE,Discrete Sync Only" "Take FID from pin,FID is determined by VSYNC skew" newline bitfld.long 0x04 13. "ACTVID_POLARITY,Discrete Sync Only" "ACTVID is active low,ACTVID is active high" newline bitfld.long 0x04 12. "VSYNC_POLARITY,Discrete Sync Only" "VSYNC is active low,VSYNC is active high" newline bitfld.long 0x04 11. "HSYNC_POLARITY,Discrete Sync Only" "HSYNC is active low,HSYNC is active high" newline bitfld.long 0x04 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x04 9. "FID_POLARITY," "0,1" newline bitfld.long 0x04 8. "ENABLE," "0,1" newline bitfld.long 0x04 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x04 6. "CLR_ASYNC_FIFO_WR," "0,1" newline bitfld.long 0x04 4.--5. "CTRL_CHAN_SEL,Embedded Sync Only In 8b mode" "Use data[7:0] to extract control codes,Use data[15:8] to extract control codes,Use data[23:16] to extract control codes,Undefined In 16b and 24b modes" newline bitfld.long 0x04 0.--3. "SYNC_TYPE," "?,embedded sync 2x multiplexed 4:2:2 YUV stream,embedded sync 4x multiplexed 4:2:2 YUV stream,embedded sync line multiplexed 4:2:2 YUV stream,discrete sync single 4:2:2 YUV stream,embedded sync single RGB stream or single 444..,reserved,reserved,reserved,reserved,discrete sync single 24b RGB stream,?..." line.long 0x08 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" rbitfld.long 0x08 31. "RESERVED," "0,1" newline bitfld.long 0x08 28.--30. "REPACK_SEL," "?,Cross Swap,Left Center Swap,Center Right Swap,Right Rotate,Left Rotate,RAW16 to RGB565 Mapping,RAW12 Swap" newline hexmask.long.word 0x08 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" newline rbitfld.long 0x08 15. "RESERVED," "0,1" newline bitfld.long 0x08 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "Extract 8b Mode Vertical Ancillary Data from..,Extract 8b Mode Vertical Ancillary Data from..,?,Extract every single sample of vertical.." newline rbitfld.long 0x08 12. "RESERVED," "0,1" newline hexmask.long.word 0x08 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x0C "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0C 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "Ignore the protection bits in the XV (fvh)..,Use the protection bits in an attempt to do.." newline bitfld.long 0x0C 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "For 2x/4x mux mode srcnum is in the least..,For 2x/4x mux mode srcnum is in the least.." newline bitfld.long 0x0C 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 23. "SW_RESET," "0,1" newline bitfld.long 0x0C 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "Normal Discrete Mode,Basic Discrete Mode" newline bitfld.long 0x0C 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "Use HSYNC style line capture,Use ACTVID style line capture" newline bitfld.long 0x0C 14. "FID_DETECT_MODE,Discrete Sync Only" "Take FID from pin,FID is determined by VSYNC skew" newline bitfld.long 0x0C 13. "ACTVID_POLARITY,Discrete Sync Only" "ACTVID is active low,ACTVID is active high" newline bitfld.long 0x0C 12. "VSYNC_POLARITY,Discrete Sync Only" "VSYNC is active low,VSYNC is active high" newline bitfld.long 0x0C 11. "HSYNC_POLARITY,Discrete Sync Only" "HSYNC is active low,HSYNC is active high" newline bitfld.long 0x0C 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x0C 9. "FID_POLARITY," "0,1" newline bitfld.long 0x0C 8. "ENABLE," "0,1" newline bitfld.long 0x0C 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x0C 6. "CLR_ASYNC_FIFO_WR," "0,1" newline bitfld.long 0x0C 4.--5. "CTRL_CHAN_SEL,PORT B supports on 8b mode" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "SYNC_TYPE," "?,embedded sync 2x multiplexed YUV stream,embedded sync 4x multiplexed YUV stream,embedded sync line multiplexed YUV stream,discrete sync single YUV stream,embedded sync single RGB stream,reserved,reserved,reserved,reserved,discrete sync single 24b RGB stream,?..." line.long 0x10 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" rbitfld.long 0x10 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x10 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" newline rbitfld.long 0x10 15. "RESERVED," "0,1" newline bitfld.long 0x10 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "Extract 8b Mode Vertical Ancillary Data from..,Extract 8b Mode Vertical Ancillary Data from..,?,Extract every single sample of vertical.." newline rbitfld.long 0x10 12. "RESERVED," "0,1" newline hexmask.long.word 0x10 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x14 "VIP_FIQ_MASK,ask Bits for ARM FIQs" hexmask.long.word 0x14 22.--31. 1. "RESERVED," newline bitfld.long 0x14 21. "PORT_B_CFG_DISABLE_COMPLETE_MASK,Port B Cfg Disable Complete Mask" "0,1" newline bitfld.long 0x14 20. "PORT_A_CFG_DISABLE_COMPLETE_MASK,Port A Cfg Disable Complete Mask" "0,1" newline bitfld.long 0x14 19. "PORT_B_ANC_PROTOCOL_VIOLATION_MASK,Port B ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 18. "PORT_B_YUV_PROTOCOL_VIOLATION_MASK,Port B YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 17. "PORT_A_ANC_PROTOCOL_VIOLATION_MASK,Port A ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 16. "PORT_A_YUV_PROTOCOL_VIOLATION_MASK,Port A YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 15. "PORT_B_SRC0_SIZE,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" newline bitfld.long 0x14 14. "PORT_A_SRC0_SIZE,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" newline bitfld.long 0x14 13. "PORT_B_DISCONN,Port B Link Disconnect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 12. "PORT_B_CONN,Port B Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 11. "PORT_A_DISCONN,Port A Link Disconnect Scrnum 0 Mask" "0,1" newline bitfld.long 0x14 10. "PORT_A_CONN,Port A Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 9. "OUTPUT_FIFO_PRTB_ANC_OF,Output FIFO Port B Ancillary Overflow Mask" "0,1" newline rbitfld.long 0x14 8. "RESERVED," "0,1" newline bitfld.long 0x14 7. "OUTPUT_FIFO_PRTB_YUV_OF,Output FIFO Port B Luma Overflow Mask" "0,1" newline bitfld.long 0x14 6. "OUTPUT_FIFO_PRTA_ANC_OF,Output FIFO Port A Ancillary Overflow Mask" "0,1" newline rbitfld.long 0x14 5. "RESERVED," "0,1" newline bitfld.long 0x14 4. "OUTPUT_FIFO_PRTA_YUV_OF,Output FIFO Port A Luma Overflow Mask" "0,1" newline bitfld.long 0x14 3. "ASYNC_FIFO_PRTB_OF,Port B Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 2. "ASYNC_FIFO_PRTA_OF,Port A Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 1. "PRTB_VDET_MASK,Port B Video Detect FIQ Mask" "0,1" newline bitfld.long 0x14 0. "PRTA_VDET_MASK,Port A Video Detect FIQ Mask" "0,1" line.long 0x18 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" hexmask.long.word 0x18 22.--31. 1. "RESERVED," newline bitfld.long 0x18 21. "PORT_A_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x18 20. "PORT_A_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x18 19. "PORT_B_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 18. "PORT_B_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 17. "PORT_A_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 16. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 15. "PORT_B_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" newline bitfld.long 0x18 14. "PORT_A_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" newline bitfld.long 0x18 13. "PORT_B_DISCONN_CLR,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 12. "PORT_B_CONN_CLR,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" newline bitfld.long 0x18 11. "PORT_A_DISCONN_CLR,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 10. "PORT_A_CONN_CLR,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" newline bitfld.long 0x18 9. "OUTPUT_FIFO_PRTB_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" newline rbitfld.long 0x18 8. "RESERVED," "0,1" newline bitfld.long 0x18 7. "OUTPUT_FIFO_PRTB_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" newline bitfld.long 0x18 6. "OUTPUT_FIFO_PRTA_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" newline rbitfld.long 0x18 5. "RESERVED," "0,1" newline bitfld.long 0x18 4. "OUTPUT_FIFO_PRTA_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" newline bitfld.long 0x18 3. "ASYNC_FIFO_PRTB_CLR,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" newline bitfld.long 0x18 2. "ASYNC_FIFO_PRTA_CLR,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" newline bitfld.long 0x18 1. "PRTB_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" newline bitfld.long 0x18 0. "PRTA_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" line.long 0x1C "VIP_FIQ_STATUS,FIQ Status values" hexmask.long.word 0x1C 22.--31. 1. "RESERVED," newline bitfld.long 0x1C 21. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Port B Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x1C 20. "PORT_A_CFG_DISABLE_COMPLETE,Port A Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x1C 19. "PORT_B_ANC_PROTOCOL_VIOLATION,Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 18. "PORT_B_YUV_PROTOCOL_VIOLATION,Port B YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 17. "PORT_A_ANC_PROTOCOL_VIOLATION,Port A ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 16. "PORT_A_YUV_PROTOCOL_VIOLATION,Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 15. "PORT_B_SRC0_SIZE_STATUS,Port B Source 0 Size FIQ" "0,1" newline bitfld.long 0x1C 14. "PORT_A_SRC0_SIZE_STATUS,Port A Source 0 Size FIQ" "0,1" newline bitfld.long 0x1C 13. "PORT_B_DISCONN_STATUS,Port B Disconnect FIQ" "0,1" newline bitfld.long 0x1C 12. "PORT_B_CONN_STATUS,Port B Connect FIQ" "0,1" newline bitfld.long 0x1C 11. "PORT_A_DISCONN_STATUS,Port A Disconnect FIQ" "0,1" newline bitfld.long 0x1C 10. "PORT_A_CONN_STATUS,Port A Connect FIQ" "0,1" newline bitfld.long 0x1C 9. "OUTPUT_FIFO_PRTB_ANC_STATUS,Output FIFO Port B Ancillary Overflow Status" "0,1" newline bitfld.long 0x1C 8. "OUTPUT_FIFO_PRTB_CHROMA_STATUS,Output FIFO Port B Chroma Overflow Status" "0,1" newline bitfld.long 0x1C 7. "OUTPUT_FIFO_PRTB_LUMA_STATUS,Output FIFO Port B Luma Overflow Status" "0,1" newline bitfld.long 0x1C 6. "OUTPUT_FIFO_PRTA_ANC_STATUS,Output FIFO Port A Ancillary Overflow Status" "0,1" newline bitfld.long 0x1C 5. "OUTPUT_FIFO_PRTA_CHROMA_STATUS,Output FIFO Port A Chroma Overflow Status" "0,1" newline bitfld.long 0x1C 4. "OUTPUT_FIFO_PRTA_LUMA_STATUS,Output FIFO Port A Luma Overflow Status" "0,1" newline bitfld.long 0x1C 3. "ASYNC_FIFO_PRTB_STATUS,Async FIFO Port B Overflow Status" "0,1" newline bitfld.long 0x1C 2. "ASYNC_FIFO_PRTA_STATUS,Async FIFO Port A Overflow Status" "0,1" newline bitfld.long 0x1C 1. "PRTB_VDET_STATUS,VDET Status for Port B" "0,1" newline bitfld.long 0x1C 0. "PRTA_VDET_STATUS,VDET Status for Port A" "0,1" line.long 0x20 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x20 31. "PRTA_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x20 30. "PRTA_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x20 29. "PRTA_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 28. "PRTA_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 27. "PRTA_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 26. "PRTA_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 25. "PRTA_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x20 24. "PRTA_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x20 23. "PRTA_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 22. "PRTA_SRC11_PREV_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 21. "PRTA_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 20. "PRTA_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 19. "PRTA_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x20 18. "PRTA_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x20 17. "PRTA_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 16. "PRTA_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 15. "PRTA_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 14. "PRTA_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 13. "PRTA_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x20 12. "PRTA_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x20 11. "PRTA_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 10. "PRTA_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 9. "PRTA_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 8. "PRTA_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 7. "PRTA_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x20 6. "PRTA_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x20 5. "PRTA_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 4. "PRTA_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 3. "PRTA_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 2. "PRTA_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 1. "PRTA_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port A" "0,1" newline bitfld.long 0x20 0. "PRTA_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port A" "0,1" line.long 0x24 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x24 31. "PRTA_SRC15_CURR_ENC_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x24 30. "PRTA_SRC15_PREV_ENC_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x24 29. "PRTA_SRC14_CURR_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 28. "PRTA_SRC14_PREV_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 27. "PRTA_SRC13_CURR_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 26. "PRTA_SRC13_PREV_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 25. "PRTA_SRC12_CURR_ENC_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x24 24. "PRTA_SRC12_PREV_ENC_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x24 23. "PRTA_SRC11_CURR_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 22. "PRTA_SRC11_PREV_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 21. "PRTA_SRC10_CURR_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 20. "PRTA_SRC10_PREV_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 19. "PRTA_SRC9_CURR_ENC_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x24 18. "PRTA_SRC9_PREV_ENC_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x24 17. "PRTA_SRC8_CURR_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 16. "PRTA_SRC8_PREV_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 15. "PRTA_SRC7_CURR_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 14. "PRTA_SRC7_PREV_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 13. "PRTA_SRC6_CURR_ENC_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x24 12. "PRTA_SRC6_PREV_ENC_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x24 11. "PRTA_SRC5_CURR_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 10. "PRTA_SRC5_PREV_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 9. "PRTA_SRC4_CURR_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 8. "PRTA_SRC4_PREV_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 7. "PRTA_SRC3_CURR_ENC_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x24 6. "PRTA_SRC3_PREV_ENC_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x24 5. "PRTA_SRC2_CURR_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 4. "PRTA_SRC2_PREV_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 3. "PRTA_SRC1_CURR_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 2. "PRTA_SRC1_PREV_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 1. "PRTA_SRC0_CURR_ENC_FID,For Source ID 0 from Port A" "0,1" newline bitfld.long 0x24 0. "PRTA_SRC0_PREV_ENC_FID,For Source ID 0 from Port A" "0,1" line.long 0x28 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x28 31. "PRTB_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x28 30. "PRTB_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x28 29. "PRTB_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 28. "PRTB_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 27. "PRTB_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 26. "PRTB_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 25. "PRTB_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x28 24. "PRTB_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x28 23. "PRTB_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x28 22. "PRTB_SRC11_PREV_SOURCE_FID,For Source ID 11" "0,1" newline bitfld.long 0x28 21. "PRTB_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 20. "PRTB_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 19. "PRTB_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x28 18. "PRTB_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x28 17. "PRTB_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 16. "PRTB_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 15. "PRTB_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 14. "PRTB_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 13. "PRTB_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x28 12. "PRTB_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x28 11. "PRTB_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 10. "PRTB_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 9. "PRTB_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 8. "PRTB_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 7. "PRTB_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x28 6. "PRTB_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x28 5. "PRTB_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 4. "PRTB_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 3. "PRTB_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 2. "PRTB_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 1. "PRTB_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port B" "0,1" newline bitfld.long 0x28 0. "PRTB_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port B" "0,1" line.long 0x2C "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x2C 31. "PRTB_SRC15_CURR_ENC_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x2C 30. "PRTB_SRC15_PREV_ENC_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x2C 29. "PRTB_SRC14_CURR_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 28. "PRTB_SRC14_PREV_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 27. "PRTB_SRC13_CURR_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 26. "PRTB_SRC13_PREV_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 25. "PRTB_SRC12_CURR_ENC_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x2C 24. "PRTB_SRC12_PREV_ENC_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x2C 23. "PRTB_SRC11_CURR_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 22. "PRTB_SRC11_PREV_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 21. "PRTB_SRC10_CURR_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 20. "PRTB_SRC10_PREV_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 19. "PRTB_SRC9_CURR_ENC_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x2C 18. "PRTB_SRC9_PREV_ENC_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x2C 17. "PRTB_SRC8_CURR_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 16. "PRTB_SRC8_PREV_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 15. "PRTB_SRC7_CURR_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 14. "PRTB_SRC7_PREV_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 13. "PRTB_SRC6_CURR_ENC_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x2C 12. "PRTB_SRC6_PREV_ENC_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x2C 11. "PRTB_SRC5_CURR_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 10. "PRTB_SRC5_PREV_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 9. "PRTB_SRC4_CURR_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 8. "PRTB_SRC4_PREV_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 7. "PRTB_SRC3_CURR_ENC_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x2C 6. "PRTB_SRC3_PREV_ENC_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x2C 5. "PRTB_SRC2_CURR_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 4. "PRTB_SRC2_PREV_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 3. "PRTB_SRC1_CURR_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 2. "PRTB_SRC1_PREV_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 1. "PRTB_SRC0_CURR_ENC_FID,For Source ID 0 from Port B" "0,1" newline bitfld.long 0x2C 0. "PRTB_SRC0_PREV_ENC_FID,For Source ID 0 from Port B" "0,1" line.long 0x30 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" bitfld.long 0x30 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x30 16.--26. 1. "PRTA_SRC0_WIDTH,On Port A" newline bitfld.long 0x30 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x30 0.--10. 1. "PRTA_SRC0_HEIGHT,On Port A" line.long 0x34 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" bitfld.long 0x34 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x34 16.--26. 1. "PRTA_SRC1_WIDTH,On Port A" newline bitfld.long 0x34 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x34 0.--10. 1. "PRTA_SRC1_HEIGHT,On Port A" line.long 0x38 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" bitfld.long 0x38 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x38 16.--26. 1. "PRTA_SRC2_WIDTH,On Port A" newline bitfld.long 0x38 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x38 0.--10. 1. "PRTA_SRC2_HEIGHT,On Port A" line.long 0x3C "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" bitfld.long 0x3C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x3C 16.--26. 1. "PRTA_SRC3_WIDTH,On Port A" newline bitfld.long 0x3C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x3C 0.--10. 1. "PRTA_SRC3_HEIGHT,On Port A" line.long 0x40 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" bitfld.long 0x40 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x40 16.--26. 1. "PRTA_SRC4_WIDTH,On Port A" newline bitfld.long 0x40 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x40 0.--10. 1. "PRTA_SRC4_HEIGHT,On Port A" line.long 0x44 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" bitfld.long 0x44 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x44 16.--26. 1. "PRTA_SRC5_WIDTH,On Port A" newline bitfld.long 0x44 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x44 0.--10. 1. "PRTA_SRC5_HEIGHT,On Port A" line.long 0x48 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" bitfld.long 0x48 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 16.--26. 1. "PRTA_SRC6_WIDTH,On Port A" newline bitfld.long 0x48 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 0.--10. 1. "PRTA_SRC6_HEIGHT,On Port A" line.long 0x4C "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" bitfld.long 0x4C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x4C 16.--26. 1. "PRTA_SRC7_WIDTH,On Port A" newline bitfld.long 0x4C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x4C 0.--10. 1. "PRTA_SRC7_HEIGHT,On Port A" line.long 0x50 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" bitfld.long 0x50 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x50 16.--26. 1. "PRTA_SRC8_WIDTH,On Port A" newline bitfld.long 0x50 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x50 0.--10. 1. "PRTA_SRC8_HEIGHT,On Port A" line.long 0x54 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" bitfld.long 0x54 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x54 16.--26. 1. "PRTA_SRC9_WIDTH,On Port A" newline bitfld.long 0x54 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x54 0.--10. 1. "PRTA_SRC9_HEIGHT,On Port A" line.long 0x58 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" bitfld.long 0x58 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x58 16.--26. 1. "PRTA_SRC10_WIDTH,On Port A" newline bitfld.long 0x58 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x58 0.--10. 1. "PRTA_SRC10_HEIGHT,On Port A" line.long 0x5C "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" bitfld.long 0x5C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x5C 16.--26. 1. "PRTA_SRC11_WIDTH,On Port A" newline bitfld.long 0x5C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x5C 0.--10. 1. "PRTA_SRC11_HEIGHT,On Port A" line.long 0x60 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" bitfld.long 0x60 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x60 16.--26. 1. "PRTA_SRC12_WIDTH,On Port A" newline bitfld.long 0x60 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x60 0.--10. 1. "PRTA_SRC12_HEIGHT,On Port A" line.long 0x64 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" bitfld.long 0x64 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x64 16.--26. 1. "PRTA_SRC13_WIDTH,On Port A" newline bitfld.long 0x64 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x64 0.--10. 1. "PRTA_SRC13_HEIGHT,On Port A" line.long 0x68 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" bitfld.long 0x68 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x68 16.--26. 1. "PRTA_SRC14_WIDTH,On Port A" newline bitfld.long 0x68 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x68 0.--10. 1. "PRTA_SRC14_HEIGHT,On Port A" line.long 0x6C "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" bitfld.long 0x6C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x6C 16.--26. 1. "PRTA_SRC15_WIDTH,On Port A" newline bitfld.long 0x6C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x6C 0.--10. 1. "PRTA_SRC15_HEIGHT,On Port A" line.long 0x70 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" bitfld.long 0x70 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x70 16.--26. 1. "PRTB_SRC0_WIDTH,On Port B" newline bitfld.long 0x70 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x70 0.--10. 1. "PRTB_SRC0_HEIGHT,On Port B" line.long 0x74 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" bitfld.long 0x74 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x74 16.--26. 1. "PRTB_SRC1_WIDTH,On Port B" newline bitfld.long 0x74 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x74 0.--10. 1. "PRTB_SRC1_HEIGHT,On Port B" line.long 0x78 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" bitfld.long 0x78 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x78 16.--26. 1. "PRTB_SRC2_WIDTH,On Port B" newline bitfld.long 0x78 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x78 0.--10. 1. "PRTB_SRC2_HEIGHT,On Port B" line.long 0x7C "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" bitfld.long 0x7C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x7C 16.--26. 1. "PRTB_SRC3_WIDTH,On Port B" newline bitfld.long 0x7C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x7C 0.--10. 1. "PRTB_SRC3_HEIGHT,On Port B" line.long 0x80 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" bitfld.long 0x80 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x80 16.--26. 1. "PRTB_SRC4_WIDTH,On Port B" newline bitfld.long 0x80 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x80 0.--10. 1. "PRTB_SRC4_HEIGHT,On Port B" line.long 0x84 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" bitfld.long 0x84 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x84 16.--26. 1. "PRTB_SRC5_WIDTH,On Port B" newline bitfld.long 0x84 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x84 0.--10. 1. "PRTB_SRC5_HEIGHT,On Port B" line.long 0x88 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" bitfld.long 0x88 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x88 16.--26. 1. "PRTB_SRC6_WIDTH,On Port B" newline bitfld.long 0x88 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x88 0.--10. 1. "PRTB_SRC6_HEIGHT,On Port B" line.long 0x8C "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" bitfld.long 0x8C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x8C 16.--26. 1. "PRTB_SRC7_WIDTH,On Port B" newline bitfld.long 0x8C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x8C 0.--10. 1. "PRTB_SRC7_HEIGHT,On Port B" line.long 0x90 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" bitfld.long 0x90 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x90 16.--26. 1. "PRTB_SRC8_WIDTH,On Port B" newline bitfld.long 0x90 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x90 0.--10. 1. "PRTB_SRC8_HEIGHT,On Port B" line.long 0x94 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" bitfld.long 0x94 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x94 16.--26. 1. "PRTB_SRC9_WIDTH,On Port B" newline bitfld.long 0x94 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x94 0.--10. 1. "PRTB_SRC9_HEIGHT,On Port B" line.long 0x98 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" bitfld.long 0x98 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x98 16.--26. 1. "PRTB_SRC10_WIDTH,On Port B" newline bitfld.long 0x98 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x98 0.--10. 1. "PRTB_SRC10_HEIGHT,On Port B" line.long 0x9C "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" bitfld.long 0x9C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x9C 16.--26. 1. "PRTB_SRC11_WIDTH,On Port B" newline bitfld.long 0x9C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x9C 0.--10. 1. "PRTB_SRC11_HEIGHT,On Port B" line.long 0xA0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" bitfld.long 0xA0 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA0 16.--26. 1. "PRTB_SRC12_WIDTH,On Port B" newline bitfld.long 0xA0 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA0 0.--10. 1. "PRTB_SRC12_HEIGHT,On Port B" line.long 0xA4 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" bitfld.long 0xA4 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA4 16.--26. 1. "PRTB_SRC13_WIDTH,On Port B" newline bitfld.long 0xA4 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA4 0.--10. 1. "PRTB_SRC13_HEIGHT,On Port B" line.long 0xA8 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" bitfld.long 0xA8 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA8 16.--26. 1. "PRTB_SRC14_WIDTH,On Port B" newline bitfld.long 0xA8 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA8 0.--10. 1. "PRTB_SRC14_HEIGHT,On Port B" line.long 0xAC "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" bitfld.long 0xAC 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xAC 16.--26. 1. "PRTB_SRC15_WIDTH,On Port B" newline bitfld.long 0xAC 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xAC 0.--10. 1. "PRTB_SRC15_HEIGHT,On Port B" line.long 0xB0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB4 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB8 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" bitfld.long 0xB8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xB8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xB8 15. "ANC_BYPASS_N," "0,1" newline rbitfld.long 0xB8 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xB8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xBC "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" rbitfld.long 0xBC 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xBC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline rbitfld.long 0xBC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xBC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xC0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" bitfld.long 0xC0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xC0 15. "ACT_BYPASS_N," "0,1" newline rbitfld.long 0xC0 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xC4 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" rbitfld.long 0xC4 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC4 16.--27. 1. "ACT_USE_NUMLINES,When cropping" newline rbitfld.long 0xC4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xC8 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" bitfld.long 0xC8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xC8 15. "ANC_BYPASS_N," "0,1" newline rbitfld.long 0xC8 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xCC "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" rbitfld.long 0xCC 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xCC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline rbitfld.long 0xCC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xCC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xD0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" bitfld.long 0xD0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xD0 15. "ACT_BYPASS_N," "0,1" newline rbitfld.long 0xD0 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xD0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xD4 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" rbitfld.long 0xD4 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD4 16.--27. 1. "ACT_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline rbitfld.long 0xD4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xD8 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0xD8 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" newline hexmask.long.word 0xD8 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xDC "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0xDC 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" newline hexmask.long.word 0xDC 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xE0 "VIP_XTRA8_PORT_A,Reserved Register for Port A" line.long 0xE4 "VIP_XTRA9_PORT_B,Reserved Register for Port B" width 0x0B tree.end tree "VIP_Slice0_sc" base ad:0x48975800 group.long 0x00++0x1B line.long 0x00 "VIP_CFG_SC0," hexmask.long.word 0x00 17.--31. 1. "RESERVED," newline bitfld.long 0x00 16. "CFG_FID_SELFGEN,FID self generate enable" "0,1" newline bitfld.long 0x00 15. "CFG_TRIM,Trimming enable" "disable trimming,enable trimming" newline bitfld.long 0x00 14. "CFG_Y_PK_EN,This parameter is used by peaking block" "disable luma peaking,enable luma peaking" newline rbitfld.long 0x00 11.--13. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10. "CFG_INTERLACE_I,This parameter is used by both horizontal and vertical scaling" "the input video format is progressive,the input video format is interlace" newline bitfld.long 0x00 9. "CFG_HP_BYPASS,This parameter is used by horizontal scaling" "The polyphase scaler is always used regardless..,The polyphase scaler is bypassed only when.." newline bitfld.long 0x00 8. "CFG_DCM_4X,This parameter is used by horizontal scaling" "the 4X decimation filter is disabled,the 4X decimation filter is enabled" newline bitfld.long 0x00 7. "CFG_DCM_2X,This parameter is used by horizontal scaling" "the 2X decimation filter is disabled,the 2X decimation filter is enabled" newline bitfld.long 0x00 6. "CFG_AUTO_HS,This parameter is used by horizontal scaling" "the cfg_dcm_2x and cfg_dcm_4x bits will enable..,HW will decide whether up-scaling or.." newline bitfld.long 0x00 5. "CFG_ENABLE_EV,This parameter is used by the edge-detection block" "The output of edge-detection block will be force..,The calculation results of edge-detection block.." newline bitfld.long 0x00 4. "CFG_USE_RAV,This parameter is used by vertical scaling" "Poly-phase filter will be used for the vertical..,Running average filter will be used for the.." newline bitfld.long 0x00 3. "CFG_INVT_FID,This parameter is used by vertical scaling" "Progressive input,Interlaced input Must be set to 1 when.." newline bitfld.long 0x00 2. "CFG_SC_BYPASS,This parameter is a general purpose" "Scaling module will engaged,Scaling module will be bypassed" newline bitfld.long 0x00 1. "CFG_LINEAR,This parameter is used by horizontal scaling" "Anamorphic scaling,Linear scaling" newline bitfld.long 0x00 0. "CFG_INTERLACE_O,This parameter is used by vertical scaling" "The output format of SC is progressive,The output format of SC is interlace" line.long 0x04 "VIP_CFG_SC1," rbitfld.long 0x04 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long 0x04 0.--26. 1. "CFG_ROW_ACC_INC,This parameter is used by vertical scaling" line.long 0x08 "VIP_CFG_SC2," rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x08 0.--27. 1. "CFG_ROW_ACC_OFFSET,This parameter is used by vertical scaling" line.long 0x0C "VIP_CFG_SC3," rbitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x0C 0.--27. 1. "CFG_ROW_ACC_OFFSET_B,This parameter is used by vertical scaling" line.long 0x10 "VIP_CFG_SC4," rbitfld.long 0x10 31. "RESERVED," "0,1" newline bitfld.long 0x10 28.--30. "CFG_NLIN_ACC_INIT_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED," "0,1" newline bitfld.long 0x10 24.--26. "CFG_LIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED," "0,1" newline hexmask.long.word 0x10 12.--22. 1. "CFG_TAR_W,This parameter is a general purpose" newline rbitfld.long 0x10 11. "RESERVED," "0,1" newline hexmask.long.word 0x10 0.--10. 1. "CFG_TAR_H,This parameter is a general purpose" line.long 0x14 "VIP_CFG_SC5," rbitfld.long 0x14 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 24.--26. "CFG_NLIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED," "0,1" newline hexmask.long.word 0x14 12.--22. 1. "CFG_SRC_W,This parameter is a general purpose" newline rbitfld.long 0x14 11. "RESERVED," "0,1" newline hexmask.long.word 0x14 0.--10. 1. "CFG_SRC_H,This parameter is a general purpose" line.long 0x18 "VIP_CFG_SC6," hexmask.long.word 0x18 20.--31. 1. "RESERVED," newline hexmask.long.word 0x18 10.--19. 1. "CFG_ROW_ACC_INIT_RAV_B,This parameter is used by vertical scaling" newline hexmask.long.word 0x18 0.--9. 1. "CFG_ROW_ACC_INIT_RAV,This parameter is used by vertical scaling" group.long 0x20++0x17 line.long 0x00 "VIP_CFG_SC8," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.word 0x00 12.--22. 1. "CFG_NLIN_RIGHT,This parameter is used by horizontal scaling" newline rbitfld.long 0x00 11. "RESERVED," "0,1" newline hexmask.long.word 0x00 0.--10. 1. "CFG_NLIN_LEFT,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC9," line.long 0x08 "VIP_CFG_SC10," line.long 0x0C "VIP_CFG_SC11," line.long 0x10 "VIP_CFG_SC12," hexmask.long.byte 0x10 25.--31. 1. "RESERVED," newline hexmask.long 0x10 0.--24. 1. "CFG_COL_ACC_OFFSET,This parameter is used in horizontal scaling" line.long 0x14 "VIP_CFG_SC13," hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," newline hexmask.long.word 0x14 0.--9. 1. "CFG_SC_FACTOR_RAV,This parameter is used by vertical scaling" group.long 0x48++0x13 line.long 0x00 "VIP_CFG_SC18," hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--9. 1. "CFG_HS_FACTOR,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC19," hexmask.long.byte 0x04 24.--31. 1. "CFG_HPF_COEF3,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 16.--23. 1. "CFG_HPF_COEF2,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 8.--15. 1. "CFG_HPF_COEF1,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 0.--7. 1. "CFG_HPF_COEF0,This parameter is used by the peaking block" line.long 0x08 "VIP_CFG_SC20," rbitfld.long 0x08 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x08 20.--28. 1. "CFG_NL_LIMIT,This parameter is used by the peaking block" newline rbitfld.long 0x08 19. "RESERVED," "0,1" newline bitfld.long 0x08 16.--18. "CFG_HPF_NORM_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 8.--15. 1. "CFG_HPF_COEF5,This parameter is used by the peaking block" newline hexmask.long.byte 0x08 0.--7. 1. "CFG_HPF_COEF4,This parameter is used by the peaking block" line.long 0x0C "VIP_CFG_SC21," hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x0C 16.--23. 1. "CFG_NL_LO_SLOPE,This parameter is used by the peaking block" newline hexmask.long.byte 0x0C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--8. 1. "CFG_NL_LO_THR,This parameter is used by the peaking block" line.long 0x10 "VIP_CFG_SC22," hexmask.long.word 0x10 19.--31. 1. "RESERVED," newline bitfld.long 0x10 16.--18. "CFG_NL_HI_SLOPE_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED," newline hexmask.long.word 0x10 0.--8. 1. "CFG_NL_HI_THR,This parameter is used by the peaking block" group.long 0x60++0x07 line.long 0x00 "VIP_CFG_SC24," rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 16.--26. 1. "CFG_ORG_W,This parameter is used by the trimmer" newline rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--10. 1. "CFG_ORG_H,This parameter is used by the trimmer" line.long 0x04 "VIP_CFG_SC25," rbitfld.long 0x04 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x04 16.--26. 1. "CFG_OFF_W,This parameter is used by the trimmer" newline rbitfld.long 0x04 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x04 0.--10. 1. "CFG_OFF_H,This parameter is used by the trimmer" width 0x0B tree.end tree "VIP_Slice1_csc" base ad:0x48975C00 group.long 0x00++0x17 line.long 0x00 "VIP_CSC00," bitfld.long 0x00 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "B0,Coefficients of color space converter" bitfld.long 0x00 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--12. 1. "A0,Coefficients of color space converter" line.long 0x04 "VIP_CSC01," bitfld.long 0x04 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 16.--28. 1. "A1,Coefficients of color space converter" bitfld.long 0x04 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 0.--12. 1. "C0,Coefficients of color space converter" line.long 0x08 "VIP_CSC02," bitfld.long 0x08 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 16.--28. 1. "C1,Coefficients of color space converter" bitfld.long 0x08 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--12. 1. "B1,Coefficients of color space converter" line.long 0x0C "VIP_CSC03," bitfld.long 0x0C 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 16.--28. 1. "B2,Coefficients of color space converter" bitfld.long 0x0C 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 0.--12. 1. "A2,Coefficients of color space converter" line.long 0x10 "VIP_CSC04," bitfld.long 0x10 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x10 16.--27. 1. "D0,Coefficients of color space converter" bitfld.long 0x10 13.--15. "RESERVED," "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--12. 1. "C2,Coefficients of color space converter" line.long 0x14 "VIP_CSC05," bitfld.long 0x14 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x14 28. "BYPASS,Full CSC bypass mode" "0,1" hexmask.long.word 0x14 16.--27. 1. "D2,Coefficients of color space converter" bitfld.long 0x14 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x14 0.--11. 1. "D1,Coefficients of color space converter" width 0x0B tree.end tree "VIP_Slice1_parser" base ad:0x48975A00 group.long 0x00++0xE7 line.long 0x00 "VIP_MAIN,ain Configuration for VIP Parser" hexmask.long 0x00 6.--31. 1. "RESERVED," newline bitfld.long 0x00 5. "CLIP_ACTIVE,Discrete Sync Only" "Do not clip active pixels,Clip Active Pixels as follows" newline bitfld.long 0x00 4. "CLIP_BLNK,Discrete Sync Only" "Do not clip Blanking Data,Clip Blanking Data as follows" newline rbitfld.long 0x00 2.--3. "RESERVED," "0,1,2,3" newline bitfld.long 0x00 0.--1. "DATA_INTERFACE_MODE," "?,16b data interface,Dual independent 8b data interfaces,Undefined" line.long 0x04 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x04 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "Ignore the protection bits in the XV (fvh)..,Use the protection bits in an attempt to do.." newline bitfld.long 0x04 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "For 2x/4x mux mode srcnum is in the least..,For 2x/4x mux mode srcnum is in the least.." newline bitfld.long 0x04 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. "SW_RESET," "0,1" newline bitfld.long 0x04 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "Normal Discrete Mode,Basic Discrete Mode" newline bitfld.long 0x04 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "Use HSYNC style line capture,Use ACTVID style line capture" newline bitfld.long 0x04 14. "FID_DETECT_MODE,Discrete Sync Only" "Take FID from pin,FID is determined by VSYNC skew" newline bitfld.long 0x04 13. "ACTVID_POLARITY,Discrete Sync Only" "ACTVID is active low,ACTVID is active high" newline bitfld.long 0x04 12. "VSYNC_POLARITY,Discrete Sync Only" "VSYNC is active low,VSYNC is active high" newline bitfld.long 0x04 11. "HSYNC_POLARITY,Discrete Sync Only" "HSYNC is active low,HSYNC is active high" newline bitfld.long 0x04 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x04 9. "FID_POLARITY," "0,1" newline bitfld.long 0x04 8. "ENABLE," "0,1" newline bitfld.long 0x04 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x04 6. "CLR_ASYNC_FIFO_WR," "0,1" newline bitfld.long 0x04 4.--5. "CTRL_CHAN_SEL,Embedded Sync Only In 8b mode" "Use data[7:0] to extract control codes,Use data[15:8] to extract control codes,Use data[23:16] to extract control codes,Undefined In 16b and 24b modes" newline bitfld.long 0x04 0.--3. "SYNC_TYPE," "?,embedded sync 2x multiplexed 4:2:2 YUV stream,embedded sync 4x multiplexed 4:2:2 YUV stream,embedded sync line multiplexed 4:2:2 YUV stream,discrete sync single 4:2:2 YUV stream,embedded sync single RGB stream or single 444..,reserved,reserved,reserved,reserved,discrete sync single 24b RGB stream,?..." line.long 0x08 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" rbitfld.long 0x08 31. "RESERVED," "0,1" newline bitfld.long 0x08 28.--30. "REPACK_SEL," "?,Cross Swap,Left Center Swap,Center Right Swap,Right Rotate,Left Rotate,RAW16 to RGB565 Mapping,RAW12 Swap" newline hexmask.long.word 0x08 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" newline rbitfld.long 0x08 15. "RESERVED," "0,1" newline bitfld.long 0x08 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "Extract 8b Mode Vertical Ancillary Data from..,Extract 8b Mode Vertical Ancillary Data from..,?,Extract every single sample of vertical.." newline rbitfld.long 0x08 12. "RESERVED," "0,1" newline hexmask.long.word 0x08 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x0C "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0C 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "Ignore the protection bits in the XV (fvh)..,Use the protection bits in an attempt to do.." newline bitfld.long 0x0C 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "For 2x/4x mux mode srcnum is in the least..,For 2x/4x mux mode srcnum is in the least.." newline bitfld.long 0x0C 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 23. "SW_RESET," "0,1" newline bitfld.long 0x0C 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "Normal Discrete Mode,Basic Discrete Mode" newline bitfld.long 0x0C 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "Use HSYNC style line capture,Use ACTVID style line capture" newline bitfld.long 0x0C 14. "FID_DETECT_MODE,Discrete Sync Only" "Take FID from pin,FID is determined by VSYNC skew" newline bitfld.long 0x0C 13. "ACTVID_POLARITY,Discrete Sync Only" "ACTVID is active low,ACTVID is active high" newline bitfld.long 0x0C 12. "VSYNC_POLARITY,Discrete Sync Only" "VSYNC is active low,VSYNC is active high" newline bitfld.long 0x0C 11. "HSYNC_POLARITY,Discrete Sync Only" "HSYNC is active low,HSYNC is active high" newline bitfld.long 0x0C 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x0C 9. "FID_POLARITY," "0,1" newline bitfld.long 0x0C 8. "ENABLE," "0,1" newline bitfld.long 0x0C 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x0C 6. "CLR_ASYNC_FIFO_WR," "0,1" newline bitfld.long 0x0C 4.--5. "CTRL_CHAN_SEL,PORT B supports on 8b mode" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "SYNC_TYPE," "?,embedded sync 2x multiplexed YUV stream,embedded sync 4x multiplexed YUV stream,embedded sync line multiplexed YUV stream,discrete sync single YUV stream,embedded sync single RGB stream,reserved,reserved,reserved,reserved,discrete sync single 24b RGB stream,?..." line.long 0x10 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" rbitfld.long 0x10 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x10 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" newline rbitfld.long 0x10 15. "RESERVED," "0,1" newline bitfld.long 0x10 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "Extract 8b Mode Vertical Ancillary Data from..,Extract 8b Mode Vertical Ancillary Data from..,?,Extract every single sample of vertical.." newline rbitfld.long 0x10 12. "RESERVED," "0,1" newline hexmask.long.word 0x10 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x14 "VIP_FIQ_MASK,ask Bits for ARM FIQs" hexmask.long.word 0x14 22.--31. 1. "RESERVED," newline bitfld.long 0x14 21. "PORT_B_CFG_DISABLE_COMPLETE_MASK,Port B Cfg Disable Complete Mask" "0,1" newline bitfld.long 0x14 20. "PORT_A_CFG_DISABLE_COMPLETE_MASK,Port A Cfg Disable Complete Mask" "0,1" newline bitfld.long 0x14 19. "PORT_B_ANC_PROTOCOL_VIOLATION_MASK,Port B ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 18. "PORT_B_YUV_PROTOCOL_VIOLATION_MASK,Port B YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 17. "PORT_A_ANC_PROTOCOL_VIOLATION_MASK,Port A ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 16. "PORT_A_YUV_PROTOCOL_VIOLATION_MASK,Port A YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 15. "PORT_B_SRC0_SIZE,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" newline bitfld.long 0x14 14. "PORT_A_SRC0_SIZE,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" newline bitfld.long 0x14 13. "PORT_B_DISCONN,Port B Link Disconnect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 12. "PORT_B_CONN,Port B Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 11. "PORT_A_DISCONN,Port A Link Disconnect Scrnum 0 Mask" "0,1" newline bitfld.long 0x14 10. "PORT_A_CONN,Port A Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 9. "OUTPUT_FIFO_PRTB_ANC_OF,Output FIFO Port B Ancillary Overflow Mask" "0,1" newline rbitfld.long 0x14 8. "RESERVED," "0,1" newline bitfld.long 0x14 7. "OUTPUT_FIFO_PRTB_YUV_OF,Output FIFO Port B Luma Overflow Mask" "0,1" newline bitfld.long 0x14 6. "OUTPUT_FIFO_PRTA_ANC_OF,Output FIFO Port A Ancillary Overflow Mask" "0,1" newline rbitfld.long 0x14 5. "RESERVED," "0,1" newline bitfld.long 0x14 4. "OUTPUT_FIFO_PRTA_YUV_OF,Output FIFO Port A Luma Overflow Mask" "0,1" newline bitfld.long 0x14 3. "ASYNC_FIFO_PRTB_OF,Port B Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 2. "ASYNC_FIFO_PRTA_OF,Port A Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 1. "PRTB_VDET_MASK,Port B Video Detect FIQ Mask" "0,1" newline bitfld.long 0x14 0. "PRTA_VDET_MASK,Port A Video Detect FIQ Mask" "0,1" line.long 0x18 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" hexmask.long.word 0x18 22.--31. 1. "RESERVED," newline bitfld.long 0x18 21. "PORT_A_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x18 20. "PORT_A_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x18 19. "PORT_B_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 18. "PORT_B_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 17. "PORT_A_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 16. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 15. "PORT_B_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" newline bitfld.long 0x18 14. "PORT_A_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" newline bitfld.long 0x18 13. "PORT_B_DISCONN_CLR,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 12. "PORT_B_CONN_CLR,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" newline bitfld.long 0x18 11. "PORT_A_DISCONN_CLR,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 10. "PORT_A_CONN_CLR,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" newline bitfld.long 0x18 9. "OUTPUT_FIFO_PRTB_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" newline rbitfld.long 0x18 8. "RESERVED," "0,1" newline bitfld.long 0x18 7. "OUTPUT_FIFO_PRTB_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" newline bitfld.long 0x18 6. "OUTPUT_FIFO_PRTA_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" newline rbitfld.long 0x18 5. "RESERVED," "0,1" newline bitfld.long 0x18 4. "OUTPUT_FIFO_PRTA_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" newline bitfld.long 0x18 3. "ASYNC_FIFO_PRTB_CLR,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" newline bitfld.long 0x18 2. "ASYNC_FIFO_PRTA_CLR,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" newline bitfld.long 0x18 1. "PRTB_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" newline bitfld.long 0x18 0. "PRTA_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" line.long 0x1C "VIP_FIQ_STATUS,FIQ Status values" hexmask.long.word 0x1C 22.--31. 1. "RESERVED," newline bitfld.long 0x1C 21. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Port B Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x1C 20. "PORT_A_CFG_DISABLE_COMPLETE,Port A Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x1C 19. "PORT_B_ANC_PROTOCOL_VIOLATION,Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 18. "PORT_B_YUV_PROTOCOL_VIOLATION,Port B YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 17. "PORT_A_ANC_PROTOCOL_VIOLATION,Port A ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 16. "PORT_A_YUV_PROTOCOL_VIOLATION,Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 15. "PORT_B_SRC0_SIZE_STATUS,Port B Source 0 Size FIQ" "0,1" newline bitfld.long 0x1C 14. "PORT_A_SRC0_SIZE_STATUS,Port A Source 0 Size FIQ" "0,1" newline bitfld.long 0x1C 13. "PORT_B_DISCONN_STATUS,Port B Disconnect FIQ" "0,1" newline bitfld.long 0x1C 12. "PORT_B_CONN_STATUS,Port B Connect FIQ" "0,1" newline bitfld.long 0x1C 11. "PORT_A_DISCONN_STATUS,Port A Disconnect FIQ" "0,1" newline bitfld.long 0x1C 10. "PORT_A_CONN_STATUS,Port A Connect FIQ" "0,1" newline bitfld.long 0x1C 9. "OUTPUT_FIFO_PRTB_ANC_STATUS,Output FIFO Port B Ancillary Overflow Status" "0,1" newline bitfld.long 0x1C 8. "OUTPUT_FIFO_PRTB_CHROMA_STATUS,Output FIFO Port B Chroma Overflow Status" "0,1" newline bitfld.long 0x1C 7. "OUTPUT_FIFO_PRTB_LUMA_STATUS,Output FIFO Port B Luma Overflow Status" "0,1" newline bitfld.long 0x1C 6. "OUTPUT_FIFO_PRTA_ANC_STATUS,Output FIFO Port A Ancillary Overflow Status" "0,1" newline bitfld.long 0x1C 5. "OUTPUT_FIFO_PRTA_CHROMA_STATUS,Output FIFO Port A Chroma Overflow Status" "0,1" newline bitfld.long 0x1C 4. "OUTPUT_FIFO_PRTA_LUMA_STATUS,Output FIFO Port A Luma Overflow Status" "0,1" newline bitfld.long 0x1C 3. "ASYNC_FIFO_PRTB_STATUS,Async FIFO Port B Overflow Status" "0,1" newline bitfld.long 0x1C 2. "ASYNC_FIFO_PRTA_STATUS,Async FIFO Port A Overflow Status" "0,1" newline bitfld.long 0x1C 1. "PRTB_VDET_STATUS,VDET Status for Port B" "0,1" newline bitfld.long 0x1C 0. "PRTA_VDET_STATUS,VDET Status for Port A" "0,1" line.long 0x20 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x20 31. "PRTA_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x20 30. "PRTA_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x20 29. "PRTA_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 28. "PRTA_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 27. "PRTA_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 26. "PRTA_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 25. "PRTA_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x20 24. "PRTA_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x20 23. "PRTA_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 22. "PRTA_SRC11_PREV_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 21. "PRTA_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 20. "PRTA_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 19. "PRTA_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x20 18. "PRTA_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x20 17. "PRTA_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 16. "PRTA_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 15. "PRTA_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 14. "PRTA_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 13. "PRTA_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x20 12. "PRTA_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x20 11. "PRTA_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 10. "PRTA_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 9. "PRTA_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 8. "PRTA_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 7. "PRTA_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x20 6. "PRTA_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x20 5. "PRTA_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 4. "PRTA_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 3. "PRTA_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 2. "PRTA_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 1. "PRTA_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port A" "0,1" newline bitfld.long 0x20 0. "PRTA_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port A" "0,1" line.long 0x24 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x24 31. "PRTA_SRC15_CURR_ENC_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x24 30. "PRTA_SRC15_PREV_ENC_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x24 29. "PRTA_SRC14_CURR_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 28. "PRTA_SRC14_PREV_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 27. "PRTA_SRC13_CURR_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 26. "PRTA_SRC13_PREV_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 25. "PRTA_SRC12_CURR_ENC_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x24 24. "PRTA_SRC12_PREV_ENC_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x24 23. "PRTA_SRC11_CURR_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 22. "PRTA_SRC11_PREV_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 21. "PRTA_SRC10_CURR_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 20. "PRTA_SRC10_PREV_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 19. "PRTA_SRC9_CURR_ENC_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x24 18. "PRTA_SRC9_PREV_ENC_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x24 17. "PRTA_SRC8_CURR_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 16. "PRTA_SRC8_PREV_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 15. "PRTA_SRC7_CURR_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 14. "PRTA_SRC7_PREV_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 13. "PRTA_SRC6_CURR_ENC_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x24 12. "PRTA_SRC6_PREV_ENC_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x24 11. "PRTA_SRC5_CURR_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 10. "PRTA_SRC5_PREV_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 9. "PRTA_SRC4_CURR_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 8. "PRTA_SRC4_PREV_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 7. "PRTA_SRC3_CURR_ENC_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x24 6. "PRTA_SRC3_PREV_ENC_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x24 5. "PRTA_SRC2_CURR_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 4. "PRTA_SRC2_PREV_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 3. "PRTA_SRC1_CURR_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 2. "PRTA_SRC1_PREV_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 1. "PRTA_SRC0_CURR_ENC_FID,For Source ID 0 from Port A" "0,1" newline bitfld.long 0x24 0. "PRTA_SRC0_PREV_ENC_FID,For Source ID 0 from Port A" "0,1" line.long 0x28 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x28 31. "PRTB_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x28 30. "PRTB_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x28 29. "PRTB_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 28. "PRTB_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 27. "PRTB_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 26. "PRTB_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 25. "PRTB_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x28 24. "PRTB_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x28 23. "PRTB_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x28 22. "PRTB_SRC11_PREV_SOURCE_FID,For Source ID 11" "0,1" newline bitfld.long 0x28 21. "PRTB_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 20. "PRTB_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 19. "PRTB_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x28 18. "PRTB_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x28 17. "PRTB_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 16. "PRTB_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 15. "PRTB_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 14. "PRTB_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 13. "PRTB_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x28 12. "PRTB_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x28 11. "PRTB_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 10. "PRTB_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 9. "PRTB_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 8. "PRTB_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 7. "PRTB_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x28 6. "PRTB_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x28 5. "PRTB_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 4. "PRTB_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 3. "PRTB_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 2. "PRTB_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 1. "PRTB_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port B" "0,1" newline bitfld.long 0x28 0. "PRTB_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port B" "0,1" line.long 0x2C "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x2C 31. "PRTB_SRC15_CURR_ENC_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x2C 30. "PRTB_SRC15_PREV_ENC_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x2C 29. "PRTB_SRC14_CURR_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 28. "PRTB_SRC14_PREV_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 27. "PRTB_SRC13_CURR_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 26. "PRTB_SRC13_PREV_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 25. "PRTB_SRC12_CURR_ENC_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x2C 24. "PRTB_SRC12_PREV_ENC_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x2C 23. "PRTB_SRC11_CURR_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 22. "PRTB_SRC11_PREV_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 21. "PRTB_SRC10_CURR_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 20. "PRTB_SRC10_PREV_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 19. "PRTB_SRC9_CURR_ENC_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x2C 18. "PRTB_SRC9_PREV_ENC_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x2C 17. "PRTB_SRC8_CURR_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 16. "PRTB_SRC8_PREV_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 15. "PRTB_SRC7_CURR_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 14. "PRTB_SRC7_PREV_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 13. "PRTB_SRC6_CURR_ENC_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x2C 12. "PRTB_SRC6_PREV_ENC_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x2C 11. "PRTB_SRC5_CURR_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 10. "PRTB_SRC5_PREV_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 9. "PRTB_SRC4_CURR_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 8. "PRTB_SRC4_PREV_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 7. "PRTB_SRC3_CURR_ENC_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x2C 6. "PRTB_SRC3_PREV_ENC_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x2C 5. "PRTB_SRC2_CURR_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 4. "PRTB_SRC2_PREV_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 3. "PRTB_SRC1_CURR_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 2. "PRTB_SRC1_PREV_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 1. "PRTB_SRC0_CURR_ENC_FID,For Source ID 0 from Port B" "0,1" newline bitfld.long 0x2C 0. "PRTB_SRC0_PREV_ENC_FID,For Source ID 0 from Port B" "0,1" line.long 0x30 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" bitfld.long 0x30 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x30 16.--26. 1. "PRTA_SRC0_WIDTH,On Port A" newline bitfld.long 0x30 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x30 0.--10. 1. "PRTA_SRC0_HEIGHT,On Port A" line.long 0x34 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" bitfld.long 0x34 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x34 16.--26. 1. "PRTA_SRC1_WIDTH,On Port A" newline bitfld.long 0x34 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x34 0.--10. 1. "PRTA_SRC1_HEIGHT,On Port A" line.long 0x38 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" bitfld.long 0x38 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x38 16.--26. 1. "PRTA_SRC2_WIDTH,On Port A" newline bitfld.long 0x38 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x38 0.--10. 1. "PRTA_SRC2_HEIGHT,On Port A" line.long 0x3C "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" bitfld.long 0x3C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x3C 16.--26. 1. "PRTA_SRC3_WIDTH,On Port A" newline bitfld.long 0x3C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x3C 0.--10. 1. "PRTA_SRC3_HEIGHT,On Port A" line.long 0x40 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" bitfld.long 0x40 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x40 16.--26. 1. "PRTA_SRC4_WIDTH,On Port A" newline bitfld.long 0x40 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x40 0.--10. 1. "PRTA_SRC4_HEIGHT,On Port A" line.long 0x44 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" bitfld.long 0x44 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x44 16.--26. 1. "PRTA_SRC5_WIDTH,On Port A" newline bitfld.long 0x44 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x44 0.--10. 1. "PRTA_SRC5_HEIGHT,On Port A" line.long 0x48 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" bitfld.long 0x48 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 16.--26. 1. "PRTA_SRC6_WIDTH,On Port A" newline bitfld.long 0x48 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x48 0.--10. 1. "PRTA_SRC6_HEIGHT,On Port A" line.long 0x4C "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" bitfld.long 0x4C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x4C 16.--26. 1. "PRTA_SRC7_WIDTH,On Port A" newline bitfld.long 0x4C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x4C 0.--10. 1. "PRTA_SRC7_HEIGHT,On Port A" line.long 0x50 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" bitfld.long 0x50 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x50 16.--26. 1. "PRTA_SRC8_WIDTH,On Port A" newline bitfld.long 0x50 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x50 0.--10. 1. "PRTA_SRC8_HEIGHT,On Port A" line.long 0x54 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" bitfld.long 0x54 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x54 16.--26. 1. "PRTA_SRC9_WIDTH,On Port A" newline bitfld.long 0x54 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x54 0.--10. 1. "PRTA_SRC9_HEIGHT,On Port A" line.long 0x58 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" bitfld.long 0x58 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x58 16.--26. 1. "PRTA_SRC10_WIDTH,On Port A" newline bitfld.long 0x58 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x58 0.--10. 1. "PRTA_SRC10_HEIGHT,On Port A" line.long 0x5C "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" bitfld.long 0x5C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x5C 16.--26. 1. "PRTA_SRC11_WIDTH,On Port A" newline bitfld.long 0x5C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x5C 0.--10. 1. "PRTA_SRC11_HEIGHT,On Port A" line.long 0x60 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" bitfld.long 0x60 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x60 16.--26. 1. "PRTA_SRC12_WIDTH,On Port A" newline bitfld.long 0x60 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x60 0.--10. 1. "PRTA_SRC12_HEIGHT,On Port A" line.long 0x64 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" bitfld.long 0x64 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x64 16.--26. 1. "PRTA_SRC13_WIDTH,On Port A" newline bitfld.long 0x64 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x64 0.--10. 1. "PRTA_SRC13_HEIGHT,On Port A" line.long 0x68 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" bitfld.long 0x68 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x68 16.--26. 1. "PRTA_SRC14_WIDTH,On Port A" newline bitfld.long 0x68 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x68 0.--10. 1. "PRTA_SRC14_HEIGHT,On Port A" line.long 0x6C "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" bitfld.long 0x6C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x6C 16.--26. 1. "PRTA_SRC15_WIDTH,On Port A" newline bitfld.long 0x6C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x6C 0.--10. 1. "PRTA_SRC15_HEIGHT,On Port A" line.long 0x70 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" bitfld.long 0x70 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x70 16.--26. 1. "PRTB_SRC0_WIDTH,On Port B" newline bitfld.long 0x70 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x70 0.--10. 1. "PRTB_SRC0_HEIGHT,On Port B" line.long 0x74 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" bitfld.long 0x74 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x74 16.--26. 1. "PRTB_SRC1_WIDTH,On Port B" newline bitfld.long 0x74 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x74 0.--10. 1. "PRTB_SRC1_HEIGHT,On Port B" line.long 0x78 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" bitfld.long 0x78 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x78 16.--26. 1. "PRTB_SRC2_WIDTH,On Port B" newline bitfld.long 0x78 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x78 0.--10. 1. "PRTB_SRC2_HEIGHT,On Port B" line.long 0x7C "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" bitfld.long 0x7C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x7C 16.--26. 1. "PRTB_SRC3_WIDTH,On Port B" newline bitfld.long 0x7C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x7C 0.--10. 1. "PRTB_SRC3_HEIGHT,On Port B" line.long 0x80 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" bitfld.long 0x80 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x80 16.--26. 1. "PRTB_SRC4_WIDTH,On Port B" newline bitfld.long 0x80 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x80 0.--10. 1. "PRTB_SRC4_HEIGHT,On Port B" line.long 0x84 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" bitfld.long 0x84 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x84 16.--26. 1. "PRTB_SRC5_WIDTH,On Port B" newline bitfld.long 0x84 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x84 0.--10. 1. "PRTB_SRC5_HEIGHT,On Port B" line.long 0x88 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" bitfld.long 0x88 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x88 16.--26. 1. "PRTB_SRC6_WIDTH,On Port B" newline bitfld.long 0x88 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x88 0.--10. 1. "PRTB_SRC6_HEIGHT,On Port B" line.long 0x8C "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" bitfld.long 0x8C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x8C 16.--26. 1. "PRTB_SRC7_WIDTH,On Port B" newline bitfld.long 0x8C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x8C 0.--10. 1. "PRTB_SRC7_HEIGHT,On Port B" line.long 0x90 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" bitfld.long 0x90 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x90 16.--26. 1. "PRTB_SRC8_WIDTH,On Port B" newline bitfld.long 0x90 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x90 0.--10. 1. "PRTB_SRC8_HEIGHT,On Port B" line.long 0x94 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" bitfld.long 0x94 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x94 16.--26. 1. "PRTB_SRC9_WIDTH,On Port B" newline bitfld.long 0x94 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x94 0.--10. 1. "PRTB_SRC9_HEIGHT,On Port B" line.long 0x98 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" bitfld.long 0x98 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x98 16.--26. 1. "PRTB_SRC10_WIDTH,On Port B" newline bitfld.long 0x98 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x98 0.--10. 1. "PRTB_SRC10_HEIGHT,On Port B" line.long 0x9C "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" bitfld.long 0x9C 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x9C 16.--26. 1. "PRTB_SRC11_WIDTH,On Port B" newline bitfld.long 0x9C 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x9C 0.--10. 1. "PRTB_SRC11_HEIGHT,On Port B" line.long 0xA0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" bitfld.long 0xA0 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA0 16.--26. 1. "PRTB_SRC12_WIDTH,On Port B" newline bitfld.long 0xA0 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA0 0.--10. 1. "PRTB_SRC12_HEIGHT,On Port B" line.long 0xA4 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" bitfld.long 0xA4 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA4 16.--26. 1. "PRTB_SRC13_WIDTH,On Port B" newline bitfld.long 0xA4 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA4 0.--10. 1. "PRTB_SRC13_HEIGHT,On Port B" line.long 0xA8 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" bitfld.long 0xA8 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA8 16.--26. 1. "PRTB_SRC14_WIDTH,On Port B" newline bitfld.long 0xA8 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xA8 0.--10. 1. "PRTB_SRC14_HEIGHT,On Port B" line.long 0xAC "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" bitfld.long 0xAC 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xAC 16.--26. 1. "PRTB_SRC15_WIDTH,On Port B" newline bitfld.long 0xAC 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0xAC 0.--10. 1. "PRTB_SRC15_HEIGHT,On Port B" line.long 0xB0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB4 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB8 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" bitfld.long 0xB8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xB8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xB8 15. "ANC_BYPASS_N," "0,1" newline rbitfld.long 0xB8 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xB8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xBC "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" rbitfld.long 0xBC 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xBC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline rbitfld.long 0xBC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xBC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xC0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" bitfld.long 0xC0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xC0 15. "ACT_BYPASS_N," "0,1" newline rbitfld.long 0xC0 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xC4 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" rbitfld.long 0xC4 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC4 16.--27. 1. "ACT_USE_NUMLINES,When cropping" newline rbitfld.long 0xC4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xC8 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" bitfld.long 0xC8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xC8 15. "ANC_BYPASS_N," "0,1" newline rbitfld.long 0xC8 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xCC "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" rbitfld.long 0xCC 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xCC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline rbitfld.long 0xCC 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xCC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xD0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" bitfld.long 0xD0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xD0 15. "ACT_BYPASS_N," "0,1" newline rbitfld.long 0xD0 12.--14. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xD0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xD4 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" rbitfld.long 0xD4 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD4 16.--27. 1. "ACT_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline rbitfld.long 0xD4 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xD8 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0xD8 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" newline hexmask.long.word 0xD8 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xDC "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0xDC 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" newline hexmask.long.word 0xDC 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xE0 "VIP_XTRA8_PORT_A,Reserved Register for Port A" line.long 0xE4 "VIP_XTRA9_PORT_B,Reserved Register for Port B" width 0x0B tree.end tree "VIP_Slice1_sc" base ad:0x48975D00 group.long 0x00++0x1B line.long 0x00 "VIP_CFG_SC0," hexmask.long.word 0x00 17.--31. 1. "RESERVED," newline bitfld.long 0x00 16. "CFG_FID_SELFGEN,FID self generate enable" "0,1" newline bitfld.long 0x00 15. "CFG_TRIM,Trimming enable" "disable trimming,enable trimming" newline bitfld.long 0x00 14. "CFG_Y_PK_EN,This parameter is used by peaking block" "disable luma peaking,enable luma peaking" newline rbitfld.long 0x00 11.--13. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10. "CFG_INTERLACE_I,This parameter is used by both horizontal and vertical scaling" "the input video format is progressive,the input video format is interlace" newline bitfld.long 0x00 9. "CFG_HP_BYPASS,This parameter is used by horizontal scaling" "The polyphase scaler is always used regardless..,The polyphase scaler is bypassed only when.." newline bitfld.long 0x00 8. "CFG_DCM_4X,This parameter is used by horizontal scaling" "the 4X decimation filter is disabled,the 4X decimation filter is enabled" newline bitfld.long 0x00 7. "CFG_DCM_2X,This parameter is used by horizontal scaling" "the 2X decimation filter is disabled,the 2X decimation filter is enabled" newline bitfld.long 0x00 6. "CFG_AUTO_HS,This parameter is used by horizontal scaling" "the cfg_dcm_2x and cfg_dcm_4x bits will enable..,HW will decide whether up-scaling or.." newline bitfld.long 0x00 5. "CFG_ENABLE_EV,This parameter is used by the edge-detection block" "The output of edge-detection block will be force..,The calculation results of edge-detection block.." newline bitfld.long 0x00 4. "CFG_USE_RAV,This parameter is used by vertical scaling" "Poly-phase filter will be used for the vertical..,Running average filter will be used for the.." newline bitfld.long 0x00 3. "CFG_INVT_FID,This parameter is used by vertical scaling" "Progressive input,Interlaced input Must be set to 1 when.." newline bitfld.long 0x00 2. "CFG_SC_BYPASS,This parameter is a general purpose" "Scaling module will engaged,Scaling module will be bypassed" newline bitfld.long 0x00 1. "CFG_LINEAR,This parameter is used by horizontal scaling" "Anamorphic scaling,Linear scaling" newline bitfld.long 0x00 0. "CFG_INTERLACE_O,This parameter is used by vertical scaling" "The output format of SC is progressive,The output format of SC is interlace" line.long 0x04 "VIP_CFG_SC1," rbitfld.long 0x04 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long 0x04 0.--26. 1. "CFG_ROW_ACC_INC,This parameter is used by vertical scaling" line.long 0x08 "VIP_CFG_SC2," rbitfld.long 0x08 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x08 0.--27. 1. "CFG_ROW_ACC_OFFSET,This parameter is used by vertical scaling" line.long 0x0C "VIP_CFG_SC3," rbitfld.long 0x0C 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long 0x0C 0.--27. 1. "CFG_ROW_ACC_OFFSET_B,This parameter is used by vertical scaling" line.long 0x10 "VIP_CFG_SC4," rbitfld.long 0x10 31. "RESERVED," "0,1" newline bitfld.long 0x10 28.--30. "CFG_NLIN_ACC_INIT_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 27. "RESERVED," "0,1" newline bitfld.long 0x10 24.--26. "CFG_LIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 23. "RESERVED," "0,1" newline hexmask.long.word 0x10 12.--22. 1. "CFG_TAR_W,This parameter is a general purpose" newline rbitfld.long 0x10 11. "RESERVED," "0,1" newline hexmask.long.word 0x10 0.--10. 1. "CFG_TAR_H,This parameter is a general purpose" line.long 0x14 "VIP_CFG_SC5," rbitfld.long 0x14 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 24.--26. "CFG_NLIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 23. "RESERVED," "0,1" newline hexmask.long.word 0x14 12.--22. 1. "CFG_SRC_W,This parameter is a general purpose" newline rbitfld.long 0x14 11. "RESERVED," "0,1" newline hexmask.long.word 0x14 0.--10. 1. "CFG_SRC_H,This parameter is a general purpose" line.long 0x18 "VIP_CFG_SC6," hexmask.long.word 0x18 20.--31. 1. "RESERVED," newline hexmask.long.word 0x18 10.--19. 1. "CFG_ROW_ACC_INIT_RAV_B,This parameter is used by vertical scaling" newline hexmask.long.word 0x18 0.--9. 1. "CFG_ROW_ACC_INIT_RAV,This parameter is used by vertical scaling" group.long 0x20++0x17 line.long 0x00 "VIP_CFG_SC8," hexmask.long.word 0x00 23.--31. 1. "RESERVED," newline hexmask.long.word 0x00 12.--22. 1. "CFG_NLIN_RIGHT,This parameter is used by horizontal scaling" newline rbitfld.long 0x00 11. "RESERVED," "0,1" newline hexmask.long.word 0x00 0.--10. 1. "CFG_NLIN_LEFT,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC9," line.long 0x08 "VIP_CFG_SC10," line.long 0x0C "VIP_CFG_SC11," line.long 0x10 "VIP_CFG_SC12," hexmask.long.byte 0x10 25.--31. 1. "RESERVED," newline hexmask.long 0x10 0.--24. 1. "CFG_COL_ACC_OFFSET,This parameter is used in horizontal scaling" line.long 0x14 "VIP_CFG_SC13," hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED," newline hexmask.long.word 0x14 0.--9. 1. "CFG_SC_FACTOR_RAV,This parameter is used by vertical scaling" group.long 0x48++0x13 line.long 0x00 "VIP_CFG_SC18," hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline hexmask.long.word 0x00 0.--9. 1. "CFG_HS_FACTOR,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC19," hexmask.long.byte 0x04 24.--31. 1. "CFG_HPF_COEF3,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 16.--23. 1. "CFG_HPF_COEF2,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 8.--15. 1. "CFG_HPF_COEF1,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 0.--7. 1. "CFG_HPF_COEF0,This parameter is used by the peaking block" line.long 0x08 "VIP_CFG_SC20," rbitfld.long 0x08 29.--31. "RESERVED," "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x08 20.--28. 1. "CFG_NL_LIMIT,This parameter is used by the peaking block" newline rbitfld.long 0x08 19. "RESERVED," "0,1" newline bitfld.long 0x08 16.--18. "CFG_HPF_NORM_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 8.--15. 1. "CFG_HPF_COEF5,This parameter is used by the peaking block" newline hexmask.long.byte 0x08 0.--7. 1. "CFG_HPF_COEF4,This parameter is used by the peaking block" line.long 0x0C "VIP_CFG_SC21," hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," newline hexmask.long.byte 0x0C 16.--23. 1. "CFG_NL_LO_SLOPE,This parameter is used by the peaking block" newline hexmask.long.byte 0x0C 9.--15. 1. "RESERVED," newline hexmask.long.word 0x0C 0.--8. 1. "CFG_NL_LO_THR,This parameter is used by the peaking block" line.long 0x10 "VIP_CFG_SC22," hexmask.long.word 0x10 19.--31. 1. "RESERVED," newline bitfld.long 0x10 16.--18. "CFG_NL_HI_SLOPE_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED," newline hexmask.long.word 0x10 0.--8. 1. "CFG_NL_HI_THR,This parameter is used by the peaking block" group.long 0x60++0x07 line.long 0x00 "VIP_CFG_SC24," rbitfld.long 0x00 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 16.--26. 1. "CFG_ORG_W,This parameter is used by the trimmer" newline rbitfld.long 0x00 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--10. 1. "CFG_ORG_H,This parameter is used by the trimmer" line.long 0x04 "VIP_CFG_SC25," rbitfld.long 0x04 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x04 16.--26. 1. "CFG_OFF_W,This parameter is used by the trimmer" newline rbitfld.long 0x04 11.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x04 0.--10. 1. "CFG_OFF_H,This parameter is used by the trimmer" width 0x0B tree.end tree "VIP_TARG" base ad:0x48980000 rgroup.long 0x00++0x07 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" line.long 0x04 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x17 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" hexmask.long.byte 0x08 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" hexmask.long.word 0x08 11.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" newline hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,Read returns 0" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" hexmask.long.byte 0x10 25.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" hexmask.long.word 0x10 9.--23. 1. "RESERVED,Read returns 0" newline bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" hexmask.long.byte 0x10 1.--7. 1. "RESERVED,Read returns 0" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" line.long 0x14 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "VIP_top_level" base ad:0x48970000 rgroup.long 0x00++0x03 line.long 0x00 "VIP_CLKC_PID,This register follows the format described in PDR3.5" bitfld.long 0x00 30.--31. "SCHEME,The scheme of the register used" "0,1,2,3" newline bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. "FUNC,The function of the module being used" newline bitfld.long 0x00 11.--15. "RTL,RTL Release Version The PDR release number of this IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "MAJOR,ajor Release Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6.--7. "CUSTOM,Custom IP" "0,1,2,3" newline bitfld.long 0x00 0.--5. "MINOR,inor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "VIP_SYSCONFIG," hexmask.long 0x00 6.--31. 1. "RESERVED," newline bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "Force-standby mode,No-standby mode,Same behavior as bit-field value of 0x1,Reserved" newline bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" newline rbitfld.long 0x00 0.--1. "RESERVED," "0,1,2,3" group.long 0x20++0x3F line.long 0x00 "VIP_INTC_INTR0_STATUS_RAW0,INTC INTR0 Interrupt Status Raw/Set Register 0" hexmask.long.word 0x00 22.--31. 1. "RESERVED," newline bitfld.long 0x00 21. "VIP2_PARSER_INT_RAW,VIP2 Parser Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 20. "VIP1_PARSER_INT_RAW,VIP1 Parser Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline rbitfld.long 0x00 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. "VPDMA_INT0_DESCRIPTOR_RAW,VPDMA INT0 Descriptor Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 15. "VPDMA_INT0_LIST7_NOTIFY_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 14. "VPDMA_INT0_LIST7_COMPLETE_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 13. "VPDMA_INT0_LIST6_NOTIFY_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 12. "VPDMA_INT0_LIST6_COMPLETE_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 11. "VPDMA_INT0_LIST5_NOTIFY_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 10. "VPDMA_INT0_LIST5_COMPLETE_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 9. "VPDMA_INT0_LIST4_NOTIFY_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 8. "VPDMA_INT0_LIST4_COMPLETE_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 7. "VPDMA_INT0_LIST3_NOTIFY_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 6. "VPDMA_INT0_LIST3_COMPLETE_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 5. "VPDMA_INT0_LIST2_NOTIFY_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 4. "VPDMA_INT0_LIST2_COMPLETE_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 3. "VPDMA_INT0_LIST1_NOTIFY_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 2. "VPDMA_INT0_LIST1_COMPLETE_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 1. "VPDMA_INT0_LIST0_NOTIFY_RAW,VPDMA INT0 List0 Notify Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 0. "VPDMA_INT0_LIST0_COMPLETE_RAW,VPDMA INT0 List0 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x04 "VIP_INTC_INTR0_STATUS_RAW1,INTC INTR0 Interrupt Status Raw/Set Register 1" rbitfld.long 0x04 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 25. "VIP2_CHR_DS_2_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 24. "VIP2_CHR_DS_1_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 23. "VIP1_CHR_DS_2_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 22. "VIP1_CHR_DS_1_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline hexmask.long.word 0x04 8.--21. 1. "RESERVED," newline bitfld.long 0x04 7. "VPDMA_INT0_CLIENT_RAW,VPDMA INT0 Client Status Read indicates raw status" "inactive,active Writing 1 will.." newline rbitfld.long 0x04 6. "RESERVED," "0,1" newline bitfld.long 0x04 5. "VPDMA_INT0_CHANNEL_GROUP5_RAW,VPDMA INT0 Channel Group5 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 4. "VPDMA_INT0_CHANNEL_GROUP4_RAW,VPDMA INT0 Channel Group4 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 3. "VPDMA_INT0_CHANNEL_GROUP3_RAW,VPDMA INT0 Channel Group3 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 2. "VPDMA_INT0_CHANNEL_GROUP2_RAW,VPDMA INT0 Channel Group2 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 1. "VPDMA_INT0_CHANNEL_GROUP1_RAW,VPDMA INT0 Channel Group1 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 0. "VPDMA_INT0_CHANNEL_GROUP0_RAW,VPDMA INT0 Channel Group0 Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x08 "VIP_INTC_INTR0_STATUS_ENA0,INTC INTR0 Interrupt Status Enabled/Clear Register 0" hexmask.long.word 0x08 22.--31. 1. "RESERVED," newline bitfld.long 0x08 21. "VIP2_PARSER_INT_ENA,VIP2 Parser Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x08 20. "VIP1_PARSER_INT_ENA,VIP1 Parser Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline rbitfld.long 0x08 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 16. "VPDMA_INT0_DESCRIPTOR_ENA,VPDMA INT0 Descriptor Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 15. "VPDMA_INT0_LIST7_NOTIFY_ENA,VPDMA INT0 List7 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 14. "VPDMA_INT0_LIST7_COMPLETE_ENA,VPDMA INT0 List7 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 13. "VPDMA_INT0_LIST6_NOTIFY_ENA,VPDMA INT0 List6 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 12. "VPDMA_INT0_LIST6_COMPLETE_ENA,VPDMA INT0 List6 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 11. "VPDMA_INT0_LIST5_NOTIFY_ENA,VPDMA INT0 List5 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 10. "VPDMA_INT0_LIST5_COMPLETE_ENA,VPDMA INT0 List5 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 9. "VPDMA_INT0_LIST4_NOTIFY_ENA,VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 8. "VPDMA_INT0_LIST4_COMPLETE_ENA,VPDMA INT0 List4 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 7. "VPDMA_INT0_LIST3_NOTIFY_ENA,VPDMA INT0 List3 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 6. "VPDMA_INT0_LIST3_COMPLETE_ENA,VPDMA INT0 List3 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 5. "VPDMA_INT0_LIST2_NOTIFY_ENA,VPDMA INT0 List2 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 4. "VPDMA_INT0_LIST2_COMPLETE_ENA,VPDMA INT0 List2 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 3. "VPDMA_INT0_LIST1_NOTIFY_ENA,VPDMA INT0 List1 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 2. "VPDMA_INT0_LIST1_COMPLETE_ENA,VPDMA INT0 List1 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 1. "VPDMA_INT0_LIST0_NOTIFY_ENA,VPDMA INT0 List0 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 0. "VPDMA_INT0_LIST0_COMPLETE_ENA,VPDMA INT0 List0 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x0C "VIP_INTC_INTR0_STATUS_ENA1,INTC INTR0 Interrupt Status Enabled/Clear Register 1" rbitfld.long 0x0C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline hexmask.long.word 0x0C 8.--21. 1. "RESERVED," newline bitfld.long 0x0C 7. "VPDMA_INT0_CLIENT_ENA,VPDMA INT0 Client Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline rbitfld.long 0x0C 6. "RESERVED," "0,1" newline bitfld.long 0x0C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA,VPDMA INT0 Channel Group5 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA,VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA,VPDMA INT0 Channel Group1 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA,VPDMA INT0 Channel Group0 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x10 "VIP_INTC_INTR0_ENA_SET0,INTC INTR0 Interrupt Enable/Set Register 0" hexmask.long.word 0x10 22.--31. 1. "RESERVED," newline bitfld.long 0x10 21. "VIP2_PARSER_INT_ENA_SET,VIP2 Parser Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 20. "VIP1_PARSER_INT_ENA_SET,VIP1 Parser Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline rbitfld.long 0x10 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 16. "VPDMA_INT0_DESCRIPTOR_ENA_SET,VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_SET,VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_SET,VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_SET,VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_SET,VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_SET,VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_SET,VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_SET,VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_SET,VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_SET,VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_SET,VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_SET,VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_SET,VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_SET,VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_SET,VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_SET,VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_SET,VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x14 "VIP_INTC_INTR0_ENA_SET1,INTC INTR0 Interrupt Enable/Set Register 1" rbitfld.long 0x14 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x14 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline hexmask.long.word 0x14 8.--21. 1. "RESERVED," newline bitfld.long 0x14 7. "VPDMA_INT0_CLIENT_ENA_SET,VPDMA INT0 Client Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_SET,VPDMA INT0 Channel Group6 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_SET,VPDMA INT0 Channel Group5 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_SET,VPDMA INT0 Channel Group4 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_SET,VPDMA INT0 Channel Group3 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_SET,VPDMA INT0 Channel Group2 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_SET,VPDMA INT0 Channel Group1 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_SET,VPDMA INT0 Channel Group0 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x18 "VIP_INTC_INTR0_ENA_CLR0,INTC INTR0 Interrupt Enable/Clear Register 0" hexmask.long.word 0x18 22.--31. 1. "RESERVED," newline bitfld.long 0x18 21. "VIP2_PARSER_INT_ENA_CLR,VIP2 Parser Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 20. "VIP1_PARSER_INT_ENA_CLR,VIP1 Parser Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline rbitfld.long 0x18 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 16. "VPDMA_INT0_DESCRIPTOR_ENA_CLR,VPDMA INT0 Descriptor Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_CLR,VPDMA INT0 List7 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_CLR,VPDMA INT0 List7 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_CLR,VPDMA INT0 List6 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_CLR,VPDMA INT0 List6 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_CLR,VPDMA INT0 List5 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_CLR,VPDMA INT0 List5 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_CLR,VPDMA INT0 List4 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_CLR,VPDMA INT0 List4 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_CLR,VPDMA INT0 List3 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_CLR,VPDMA INT0 List3 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_CLR,VPDMA INT0 List2 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_CLR,VPDMA INT0 List2 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_CLR,VPDMA INT0 List1 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_CLR,VPDMA INT0 List1 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_CLR,VPDMA INT0 List0 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_CLR,VPDMA INT0 List0 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x1C "VIP_INTC_INTR0_ENA_CLR1,INTC INTR0 Interrupt Enable/Clear Register 1" rbitfld.long 0x1C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x1C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline hexmask.long.word 0x1C 8.--21. 1. "RESERVED," newline bitfld.long 0x1C 7. "VPDMA_INT0_CLIENT_ENA_CLR,VPDMA INT0 Client Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_CLR,VPDMA INT0 Channel Group6 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR,VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR,VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR,VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR,VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR,VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR,VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x20 "VIP_INTC_INTR1_STATUS_RAW0,INTC intr1 Interrupt Status Raw/Set Register 0" hexmask.long.word 0x20 22.--31. 1. "RESERVED," newline bitfld.long 0x20 21. "VIP2_PARSER_INT_RAW,VIP2 Parser Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 20. "VIP1_PARSER_INT_RAW,VIP1 Parser Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline rbitfld.long 0x20 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 16. "VPDMA_INT1_DESCRIPTOR_RAW,VPDMA INT1 Descriptor Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 15. "VPDMA_INT1_LIST7_NOTIFY_RAW,VPDMA INT1 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 14. "VPDMA_INT1_LIST7_COMPLETE_RAW,VPDMA INT1 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 13. "VPDMA_INT1_LIST6_NOTIFY_RAW,VPDMA INT1 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 12. "VPDMA_INT1_LIST6_COMPLETE_RAW,VPDMA INT1 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 11. "VPDMA_INT1_LIST5_NOTIFY_RAW,VPDMA INT1 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 10. "VPDMA_INT1_LIST5_COMPLETE_RAW,VPDMA INT1 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 9. "VPDMA_INT1_LIST4_NOTIFY_RAW,VPDMA INT1 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 8. "VPDMA_INT1_LIST4_COMPLETE_RAW,VPDMA INT1 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 7. "VPDMA_INT1_LIST3_NOTIFY_RAW,VPDMA INT1 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 6. "VPDMA_INT1_LIST3_COMPLETE_RAW,VPDMA INT1 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 5. "VPDMA_INT1_LIST2_NOTIFY_RAW,VPDMA INT1 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 4. "VPDMA_INT1_LIST2_COMPLETE_RAW,VPDMA INT1 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 3. "VPDMA_INT1_LIST1_NOTIFY_RAW,VPDMA INT1 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 2. "VPDMA_INT1_LIST1_COMPLETE_RAW,VPDMA INT1 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 1. "VPDMA_INT1_LIST0_NOTIFY_RAW,VPDMA INT1 List0 Notify Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 0. "VPDMA_INT1_LIST0_COMPLETE_RAW,VPDMA INT1 List0 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x24 "VIP_INTC_INTR1_STATUS_RAW1,INTC intr1 Interrupt Status Raw/Set Register 1" rbitfld.long 0x24 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x24 25. "VIP2_CHR_DS_2_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 24. "VIP2_CHR_DS_1_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 23. "VIP1_CHR_DS_2_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 22. "VIP1_CHR_DS_1_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline hexmask.long.word 0x24 8.--21. 1. "RESERVED," newline bitfld.long 0x24 7. "VPDMA_INT1_CLIENT_RAW,VPDMA INT1 Client Status Read indicates raw status" "inactive,active Writing 1 will.." newline rbitfld.long 0x24 6. "RESERVED," "0,1" newline bitfld.long 0x24 5. "VPDMA_INT1_CHANNEL_GROUP5_RAW,VPDMA INT1 Channel Group5 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 4. "VPDMA_INT1_CHANNEL_GROUP4_RAW,VPDMA INT1 Channel Group4 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 3. "VPDMA_INT1_CHANNEL_GROUP3_RAW,VPDMA INT1 Channel Group3 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 2. "VPDMA_INT1_CHANNEL_GROUP2_RAW,VPDMA INT1 Channel Group2 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 1. "VPDMA_INT1_CHANNEL_GROUP1_RAW,VPDMA INT1 Channel Group1 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 0. "VPDMA_INT1_CHANNEL_GROUP0_RAW,VPDMA INT1 Channel Group0 Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x28 "VIP_INTC_INTR1_STATUS_ENA0,INTC intr1 Interrupt Status Enabled/Clear Register 0" hexmask.long.word 0x28 22.--31. 1. "RESERVED," newline bitfld.long 0x28 21. "VIP2_PARSER_INT_ENA,VIP2 Parser Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x28 20. "VIP1_PARSER_INT_ENA,VIP1 Parser Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline rbitfld.long 0x28 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 16. "VPDMA_INT1_DESCRIPTOR_ENA,VPDMA INT1 Descriptor Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 15. "VPDMA_INT1_LIST7_NOTIFY_ENA,VPDMA INT1 List7 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 14. "VPDMA_INT1_LIST7_COMPLETE_ENA,VPDMA INT1 List7 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 13. "VPDMA_INT1_LIST6_NOTIFY_ENA,VPDMA INT1 List6 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 12. "VPDMA_INT1_LIST6_COMPLETE_ENA,VPDMA INT1 List6 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 11. "VPDMA_INT1_LIST5_NOTIFY_ENA,VPDMA INT1 List5 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 10. "VPDMA_INT1_LIST5_COMPLETE_ENA,VPDMA INT1 List5 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 9. "VPDMA_INT1_LIST4_NOTIFY_ENA,VPDMA INT1 List4 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 8. "VPDMA_INT1_LIST4_COMPLETE_ENA,VPDMA INT1 List4 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 7. "VPDMA_INT1_LIST3_NOTIFY_ENA,VPDMA INT1 List3 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 6. "VPDMA_INT1_LIST3_COMPLETE_ENA,VPDMA INT1 List3 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 5. "VPDMA_INT1_LIST2_NOTIFY_ENA,VPDMA INT1 List2 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 4. "VPDMA_INT1_LIST2_COMPLETE_ENA,VPDMA INT1 List2 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 3. "VPDMA_INT1_LIST1_NOTIFY_ENA,VPDMA INT1 List1 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 2. "VPDMA_INT1_LIST1_COMPLETE_ENA,VPDMA INT1 List1 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 1. "VPDMA_INT1_LIST0_NOTIFY_ENA,VPDMA INT1 List0 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 0. "VPDMA_INT1_LIST0_COMPLETE_ENA,VPDMA INT1 List0 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x2C "VIP_INTC_INTR1_STATUS_ENA1,INTC intr1 Interrupt Status Enabled/Clear Register 1" rbitfld.long 0x2C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x2C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline hexmask.long.word 0x2C 8.--21. 1. "RESERVED," newline bitfld.long 0x2C 7. "VPDMA_INT1_CLIENT_ENA,VPDMA INT1 Client Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline rbitfld.long 0x2C 6. "RESERVED," "0,1" newline bitfld.long 0x2C 5. "VPDMA_INT1_CHANNEL_GROUP5_ENA,VPDMA INT1 Channel Group5 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 4. "VPDMA_INT1_CHANNEL_GROUP4_ENA,VPDMA INT1 Channel Group4 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 3. "VPDMA_INT1_CHANNEL_GROUP3_ENA,VPDMA INT1 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 2. "VPDMA_INT1_CHANNEL_GROUP2_ENA,VPDMA INT1 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 1. "VPDMA_INT1_CHANNEL_GROUP1_ENA,VPDMA INT1 Channel Group1 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 0. "VPDMA_INT1_CHANNEL_GROUP0_ENA,VPDMA INT1 Channel Group0 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x30 "VIP_INTC_INTR1_ENA_SET0,INTC intr1 Interrupt Enable/Set Register 0" hexmask.long.word 0x30 22.--31. 1. "RESERVED," newline bitfld.long 0x30 21. "VIP2_PARSER_INT_ENA_SET,VIP2 Parser Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 20. "VIP1_PARSER_INT_ENA_SET,VIP1 Parser Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline rbitfld.long 0x30 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 16. "VPDMA_INT1_DESCRIPTOR_ENA_SET,VPDMA INT1 Descriptor Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 15. "VPDMA_INT1_LIST7_NOTIFY_ENA_SET,VPDMA INT1 List7 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 14. "VPDMA_INT1_LIST7_COMPLETE_ENA_SET,VPDMA INT1 List7 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 13. "VPDMA_INT1_LIST6_NOTIFY_ENA_SET,VPDMA INT1 List6 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 12. "VPDMA_INT1_LIST6_COMPLETE_ENA_SET,VPDMA INT1 List6 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 11. "VPDMA_INT1_LIST5_NOTIFY_ENA_SET,VPDMA INT1 List5 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 10. "VPDMA_INT1_LIST5_COMPLETE_ENA_SET,VPDMA INT1 List5 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 9. "VPDMA_INT1_LIST4_NOTIFY_ENA_SET,VPDMA INT1 List4 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 8. "VPDMA_INT1_LIST4_COMPLETE_ENA_SET,VPDMA INT1 List4 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 7. "VPDMA_INT1_LIST3_NOTIFY_ENA_SET,VPDMA INT1 List3 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 6. "VPDMA_INT1_LIST3_COMPLETE_ENA_SET,VPDMA INT1 List3 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 5. "VPDMA_INT1_LIST2_NOTIFY_ENA_SET,VPDMA INT1 List2 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 4. "VPDMA_INT1_LIST2_COMPLETE_ENA_SET,VPDMA INT1 List2 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 3. "VPDMA_INT1_LIST1_NOTIFY_ENA_SET,VPDMA INT1 List1 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 2. "VPDMA_INT1_LIST1_COMPLETE_ENA_SET,VPDMA INT1 List1 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 1. "VPDMA_INT1_LIST0_NOTIFY_ENA_SET,VPDMA INT1 List0 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 0. "VPDMA_INT1_LIST0_COMPLETE_ENA_SET,VPDMA INT1 List0 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x34 "VIP_INTC_INTR1_ENA_SET1,INTC intr1 Interrupt Enable/Set Register 1" rbitfld.long 0x34 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x34 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline hexmask.long.word 0x34 8.--21. 1. "RESERVED," newline bitfld.long 0x34 7. "VPDMA_INT1_CLIENT_ENA_SET,VPDMA INT1 Client Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 6. "VPDMA_INT1_CHANNEL_GROUP6_ENA_SET,VPDMA INT1 Channel Group6 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 5. "VPDMA_INT1_CHANNEL_GROUP5_ENA_SET,VPDMA INT1 Channel Group5 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 4. "VPDMA_INT1_CHANNEL_GROUP4_ENA_SET,VPDMA INT1 Channel Group4 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 3. "VPDMA_INT1_CHANNEL_GROUP3_ENA_SET,VPDMA INT1 Channel Group3 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 2. "VPDMA_INT1_CHANNEL_GROUP2_ENA_SET,VPDMA INT1 Channel Group2 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 1. "VPDMA_INT1_CHANNEL_GROUP1_ENA_SET,VPDMA INT1 Channel Group1 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 0. "VPDMA_INT1_CHANNEL_GROUP0_ENA_SET,VPDMA INT1 Channel Group0 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x38 "VIP_INTC_INTR1_ENA_CLR0,INTC intr1 Interrupt Enable/Clear Register 0" hexmask.long.word 0x38 22.--31. 1. "RESERVED," newline bitfld.long 0x38 21. "VIP2_PARSER_INT_ENA_CLR,VIP2 Parser Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 20. "VIP1_PARSER_INT_ENA_CLR,VIP1 Parser Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline rbitfld.long 0x38 17.--19. "RESERVED," "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 16. "VPDMA_INT1_DESCRIPTOR_ENA_CLR,VPDMA INT1 Descriptor Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 15. "VPDMA_INT1_LIST7_NOTIFY_ENA_CLR,VPDMA INT1 List7 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 14. "VPDMA_INT1_LIST7_COMPLETE_ENA_CLR,VPDMA INT1 List7 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 13. "VPDMA_INT1_LIST6_NOTIFY_ENA_CLR,VPDMA INT1 List6 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 12. "VPDMA_INT1_LIST6_COMPLETE_ENA_CLR,VPDMA INT1 List6 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 11. "VPDMA_INT1_LIST5_NOTIFY_ENA_CLR,VPDMA INT1 List5 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 10. "VPDMA_INT1_LIST5_COMPLETE_ENA_CLR,VPDMA INT1 List5 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 9. "VPDMA_INT1_LIST4_NOTIFY_ENA_CLR,VPDMA INT1 List4 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 8. "VPDMA_INT1_LIST4_COMPLETE_ENA_CLR,VPDMA INT1 List4 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 7. "VPDMA_INT1_LIST3_NOTIFY_ENA_CLR,VPDMA INT1 List3 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 6. "VPDMA_INT1_LIST3_COMPLETE_ENA_CLR,VPDMA INT1 List3 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 5. "VPDMA_INT1_LIST2_NOTIFY_ENA_CLR,VPDMA INT1 List2 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 4. "VPDMA_INT1_LIST2_COMPLETE_ENA_CLR,VPDMA INT1 List2 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 3. "VPDMA_INT1_LIST1_NOTIFY_ENA_CLR,VPDMA INT1 List1 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 2. "VPDMA_INT1_LIST1_COMPLETE_ENA_CLR,VPDMA INT1 List1 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 1. "VPDMA_INT1_LIST0_NOTIFY_ENA_CLR,VPDMA INT1 List0 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 0. "VPDMA_INT1_LIST0_COMPLETE_ENA_CLR,VPDMA INT1 List0 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x3C "VIP_INTC_INTR1_ENA_CLR1,INTC intr1 Interrupt Enable/Clear Register 1" rbitfld.long 0x3C 26.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x3C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline hexmask.long.word 0x3C 8.--21. 1. "RESERVED," newline bitfld.long 0x3C 7. "VPDMA_INT1_CLIENT_ENA_CLR,VPDMA INT1 Client Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 6. "VPDMA_INT1_CHANNEL_GROUP6_ENA_CLR,VPDMA INT1 Channel Group6 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 5. "VPDMA_INT1_CHANNEL_GROUP5_ENA_CLR,VPDMA INT1 Channel Group5 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 4. "VPDMA_INT1_CHANNEL_GROUP4_ENA_CLR,VPDMA INT1 Channel Group4 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 3. "VPDMA_INT1_CHANNEL_GROUP3_ENA_CLR,VPDMA INT1 Channel Group3 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 2. "VPDMA_INT1_CHANNEL_GROUP2_ENA_CLR,VPDMA INT1 Channel Group2 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 1. "VPDMA_INT1_CHANNEL_GROUP1_ENA_CLR,VPDMA INT1 Channel Group1 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 0. "VPDMA_INT1_CHANNEL_GROUP0_ENA_CLR,VPDMA INT1 Channel Group0 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." group.long 0xA0++0x03 line.long 0x00 "VIP_INTC_EOI,INTC EOI Register" group.long 0x100++0x13 line.long 0x00 "VIP_CLKC_CLKEN,CLKC Module Clock Enable Register" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 17. "VIP2_DP_EN,VIP Slice1 Data Path Clock Enable " "Clock Disabled,Clock Enabled" newline bitfld.long 0x00 16. "VIP1_DP_EN,VIP Slice0 Data Path Clock Enable " "Clock Disabled,Clock Enabled" newline hexmask.long.word 0x00 1.--15. 1. "RESERVED," newline bitfld.long 0x00 0. "VPDMA_EN,VPDMA Clock Enable " "Clock Disabled,Clock Enabled" line.long 0x04 "VIP_CLKC_RST,CLKC Module Reset Register" bitfld.long 0x04 31. "MAIN_RST,Reset for all modules in VIP Main Data Path" "0,1" newline rbitfld.long 0x04 29.--30. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x04 28. "S1_CHR_DS_1_RST,VIP Slice1 CHRDS1 reset" "0,1" newline bitfld.long 0x04 27. "S0_CHR_DS_1_RST,VIP Slice0 CHRDS1 reset" "0,1" newline bitfld.long 0x04 26. "S1_CHR_DS_0_RST,VIP Slice1 CHRDS0 reset" "0,1" newline bitfld.long 0x04 25. "S0_CHR_DS_0_RST,VIP Slice0 CHRDS0 reset" "0,1" newline bitfld.long 0x04 24. "RESERVED,Reserved" "0,1" newline bitfld.long 0x04 23. "S1_SC_RST,VIP Slice1 SC reset" "0,1" newline bitfld.long 0x04 22. "S0_SC_RST,VIP Slice0 SC reset" "0,1" newline bitfld.long 0x04 21. "S1_CSC_RST,VIP Slice1 CSC reset" "0,1" newline bitfld.long 0x04 20. "S0_CSC_RST,VIP Slice0 CSC reset" "0,1" newline bitfld.long 0x04 19. "S1_PARSER_RST,VIP Slice1 parser reset" "0,1" newline bitfld.long 0x04 18. "S0_PARSER_RST,VIP Slice0 parser reset" "0,1" newline bitfld.long 0x04 17. "VIP2_DP_RST,VIP Slice1 Data Path Reset" "0,1" newline bitfld.long 0x04 16. "VIP1_DP_RST,VIP Slice0 Data Path Reset" "0,1" newline hexmask.long.word 0x04 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x04 0. "VPDMA_RST,VPDMA Reset" "0,1" line.long 0x08 "VIP_CLKC_DPS,CLKC Main Data Path Select Register" bitfld.long 0x08 31. "MAIN_RST,Reset for all modules in DSS Main Data Path" "0,1" newline hexmask.long.word 0x08 18.--30. 1. "RESERVED," newline bitfld.long 0x08 17. "VIP2_DP_RST,Video Input Port 2 Data Path Reset" "0,1" newline bitfld.long 0x08 16. "VIP1_DP_RST,Video Input Port 1 Data Path Reset" "0,1" newline hexmask.long.word 0x08 1.--15. 1. "RESERVED," newline bitfld.long 0x08 0. "VPDMA_RST,VPDMA Reset" "0,1" line.long 0x0C "VIP_CLKC_VIP0DPS,CLKC Video Input Port 1 Data Path Select Register" bitfld.long 0x0C 28.--31. "VIP1_DATAPATH_SELECT,VIP1 Datapath Register Field Enable" "All fields written,Only vip1_csc_src_select written,Only vip1_sc_src_select written,Only vip1_rgb_src_select written,Only vip1_rgb_out_lo_select written,Only vip1_rgb_out_hi_select written,Only vip1_chr_ds_1_src_select written,Only vip1_chr_ds_2_src_select written,Only vip1_multi_channel_select written,Only vip1_chr_ds_1_bypass written,Only vip1_chr_ds_2_bypass written,Reserved,Reserved,Reserved,Reserved,Reserved" newline bitfld.long 0x0C 27. "VIP1_TESTPORT_A_SELECT," "0,1" newline bitfld.long 0x0C 26. "VIP1_TESTPORT_B_SELECT," "0,1" newline hexmask.long.byte 0x0C 18.--25. 1. "RESERVED," newline bitfld.long 0x0C 17. "VIP1_CHR_DS_2_BYPASS,Video Input Port 1 Chroma Downsampler 2 Bypass" "VIP Chroma Downsampler 1 selected,VIP Chroma Downsampler 1 Bypassed Chroma.." newline bitfld.long 0x0C 16. "VIP1_CHR_DS_1_BYPASS,Video Input Port 1 Chroma Downsampler 1 Bypass" "VIP Chroma Downsampler 1 selected,VIP Chroma Downsampler 1 Bypassed Chroma.." newline bitfld.long 0x0C 15. "VIP1_MULTI_CHANNEL_SELECT,Video Input Port 1 Multi Channel Select" "VIP_PARSER A and B channels operate in single..,VIP_PARSER A and B channels directly drive VPDMA.." newline bitfld.long 0x0C 12.--14. "VIP1_CHR_DS_2_SRC_SELECT,Video Input Port 1 Chroma Downsampler 2 Source Select" "Path Disabled (no input to CHR_DS),Source from Scaler (SC_M),Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved" newline bitfld.long 0x0C 9.--11. "VIP1_CHR_DS_1_SRC_SELECT,Video Input Port 1 Chroma Downsampler 1 Source Select" "Path Disabled (no input to CHR_DS),Source from Scaler (SC_M),Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved" newline bitfld.long 0x0C 8. "VIP1_RGB_OUT_HI_SELECT,Video Input Port 1 HI RGB Output Select" "Output Type is 420/422,Output Type is RGB" newline bitfld.long 0x0C 7. "VIP1_RGB_OUT_LO_SELECT,Video Input Port 1 LO RGB Output Select" "Output Type is 420/422,Output Type is RGB" newline bitfld.long 0x0C 6. "VIP1_RGB_SRC_SELECT,Video Input Port 1 RGB Output Path Select" "Source from Compositor RGB input,Source from CSC" newline bitfld.long 0x0C 3.--5. "VIP1_SC_SRC_SELECT,Video Input Port 1 SC_M Source Select" "Path Disabled,Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved,Reserved" newline bitfld.long 0x0C 0.--2. "VIP1_CSC_SRC_SELECT,Video Input Port 1 CSC Source Select" "Path Disabled,Source from VIP_PARSER A (422) port,Source from VIP_PARSER B port,Source from Transcode (422),Source from VIP_PARSER A (RGB) port,Source from Compositor (RGB),Reserved,Reserved" line.long 0x10 "VIP_CLKC_VIP1DPS,CLKC Video Input Port 2 Data Path Select Register" bitfld.long 0x10 28.--31. "VIP2_DATAPATH_SELECT,VIP2 Datapath Register Field Enable" "All fields written,Only vip2_csc_src_select written,Only vip2_sc_src_select written,Only vip2_rgb_src_select written,Only vip2_rgb_out_lo_select written,Only vip2_rgb_out_hi_select written,Only vip2_chr_ds_1_src_select written,Only vip2_chr_ds_2_src_select written,Only vip2_multi_channel_select written,Only vip2_chr_ds_1_bypass written,Only vip2_chr_ds_2_bypass written,Reserved,Reserved,Reserved,Reserved,Reserved" newline bitfld.long 0x10 27. "VIP2_TESTPORT_A_SELECT," "0,1" newline bitfld.long 0x10 26. "VIP2_TESTPORT_B_SELECT," "0,1" newline hexmask.long.byte 0x10 18.--25. 1. "RESERVED," newline bitfld.long 0x10 17. "VIP2_CHR_DS_2_BYPASS,Video Input Port 2 Chroma Downsampler 2 Bypass" "VIP Chroma Downsampler 1 selected,VIP Chroma Downsampler 1 Bypassed Chroma.." newline bitfld.long 0x10 16. "VIP2_CHR_DS_1_BYPASS,Video Input Port 2 Chroma Downsampler 1 Bypass" "VIP Chroma Downsampler 1 selected,VIP Chroma Downsampler 1 Bypassed Chroma.." newline bitfld.long 0x10 15. "VIP2_MULTI_CHANNEL_SELECT,Video Input Port 2 Multi Channel Select" "VIP_PARSER A and B channels operate in single..,VIP_PARSER A and B channels directly drive VPDMA.." newline bitfld.long 0x10 12.--14. "VIP2_CHR_DS_2_SRC_SELECT,Video Input Port 2 Chroma Downsampler 2 Source Select" "Path Disabled (no input to CHR_DS),Source from Scaler (SC_M),Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved" newline bitfld.long 0x10 9.--11. "VIP2_CHR_DS_1_SRC_SELECT,Video Input Port 2 Chroma Downsampler 1 Source Select" "Path Disabled (no input to CHR_DS),Source from Scaler (SC_M),Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved" newline bitfld.long 0x10 8. "VIP2_RGB_OUT_HI_SELECT,Video Input Port 2 HI RGB Output Select" "Output Type is 420/422,Output Type is RGB" newline bitfld.long 0x10 7. "VIP2_RGB_OUT_LO_SELECT,Video Input Port 2 LO RGB Output Select" "Output Type is 420/422,Output Type is RGB" newline bitfld.long 0x10 6. "VIP2_RGB_SRC_SELECT,Video Input Port 2 RGB Output Path Select" "Source from Compositor RGB input,Source from CSC" newline bitfld.long 0x10 3.--5. "VIP2_SC_SRC_SELECT,Video Input Port 2 SC_M Source Select" "Path Disabled,Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved,Reserved" newline bitfld.long 0x10 0.--2. "VIP2_CSC_SRC_SELECT,Video Input Port 2 CSC Source Select" "Path Disabled,Source from VIP_PARSER A (422) port,Source from VIP_PARSER B port,Source from Transcode (422),Source from VIP_PARSER A (RGB) port,Source from Compositor (RGB),Reserved,Reserved" width 0x0B tree.end tree "VIP_VPDMA" base ad:0x4897D000 rgroup.long 0x00++0x0F line.long 0x00 "VIP_PID,PID VIP VPDMA register" line.long 0x04 "VIP_LIST_ADDR,The location of a new list to begin processing" line.long 0x08 "VIP_LIST_ATTR,The attributes of a new list" rbitfld.long 0x08 27.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 24.--26. "LIST_NUM,The list number that should be assigned to the list located atVIP_LIST_ADDR" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x08 21.--23. "RESERVED," "0,1,2,3,4,5,6,7" bitfld.long 0x08 20. "STOP,This bit is written with the LIST_NUMBER field to stop a self-modifying list" "0,1" newline rbitfld.long 0x08 19. "RDY,This bit is low when a new list cannot be written to theVIP_LIST_ADDR register" "0,1" bitfld.long 0x08 16.--18. "LIST_TYPE,The type of list that has been generated.\\n0: Normal List\\n1: Self-Modifying List\\n2: List Doorbell\\nOthers Reserved for future use" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x08 0.--15. 1. "LIST_SIZE,Number of 128 bit word in the new list of descriptors" line.long 0x0C "VIP_LIST_STAT_SYNC,The register is used for processor to List Manager syncronization and status registers for the list" hexmask.long.byte 0x0C 24.--31. 1. "RESERVED," rbitfld.long 0x0C 23. "LIST7_BUSY,The list 7 is currently running" "0,1" newline rbitfld.long 0x0C 22. "LIST6_BUSY,The list 6 is currently running" "0,1" rbitfld.long 0x0C 21. "LIST5_BUSY,The list 5 is currently running" "0,1" newline rbitfld.long 0x0C 20. "LIST4_BUSY,The list 4 is currently running" "0,1" rbitfld.long 0x0C 19. "LIST3_BUSY,The list 3 is currently running" "0,1" newline rbitfld.long 0x0C 18. "LIST2_BUSY,The list 2 is currently running" "0,1" rbitfld.long 0x0C 17. "LIST1_BUSY,The list 1 is currently running" "0,1" newline rbitfld.long 0x0C 16. "LIST0_BUSY,The list 0 is currently running" "0,1" hexmask.long.byte 0x0C 8.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0C 7. "SYNC_LISTS7,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 7 waiting on it" "0,1" bitfld.long 0x0C 6. "SYNC_LISTS6,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 6 waiting on it" "0,1" newline bitfld.long 0x0C 5. "SYNC_LISTS5,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 5 waiting on it" "0,1" bitfld.long 0x0C 4. "SYNC_LISTS4,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 4 waiting on it" "0,1" newline bitfld.long 0x0C 3. "SYNC_LISTS3,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 3 waiting on it" "0,1" bitfld.long 0x0C 2. "SYNC_LISTS2,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 2 waiting on it" "0,1" newline bitfld.long 0x0C 1. "SYNC_LISTS1,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 1 waiting on it" "0,1" bitfld.long 0x0C 0. "SYNC_LISTS0,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 0 waiting on it" "0,1" group.long 0x18++0x07 line.long 0x00 "VIP_BG_RGB,The registers used to set the background color for RGB" hexmask.long.byte 0x00 24.--31. 1. "RED,The red value to give on an RGB data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x00 16.--23. 1. "GREEN,The green value to give on an RGB data port for a blank pixel when using virtual video buffering" newline hexmask.long.byte 0x00 8.--15. 1. "BLUE,The blue value to give on an RGB data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x00 0.--7. 1. "BLEND,The blend value to give on an RGB data port for a blank pixel when using virtual video buffering" line.long 0x04 "VIP_BG_YUV,The registers used to set the background color for YUV" hexmask.long.byte 0x04 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x04 16.--23. 1. "Y,The Y value to give on a YUV data port for a blank pixel when using virtual video buffering" newline hexmask.long.byte 0x04 8.--15. 1. "CR,The Cr value to give on a YUV data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x04 0.--7. 1. "CB,The Cb value to give on a YUV data port for a blank pixel when using virtual video buffering" group.long 0x30++0x3F line.long 0x00 "VIP_VPDMA_SETUP,Configures global parameters that are shared by all clients" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "SEC_BASE_CH,Use Secondary Channels for Mosaic mode" "0,1" line.long 0x04 "VIP_MAX_SIZE1,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 1 in write descriptor" hexmask.long.word 0x04 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 1 in a write descriptor" hexmask.long.word 0x04 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 1 in a write descriptor" line.long 0x08 "VIP_MAX_SIZE2,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 2 in write descriptor" hexmask.long.word 0x08 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 2 in a write descriptor" hexmask.long.word 0x08 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 2 in a write descriptor" line.long 0x0C "VIP_MAX_SIZE3,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 3 in write descriptor" hexmask.long.word 0x0C 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 3 in a write descriptor" hexmask.long.word 0x0C 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 3 in a write descriptor" line.long 0x10 "VIP_INT0_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x10 31. "INT_STAT_GRPX3,The last read DMA transaction has occurred for channel grpx3 and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x10 30. "INT_STAT_GRPX2,The last read DMA transaction has occurred for channel grpx2 and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x10 29. "INT_STAT_GRPX1,The last read DMA transaction has occurred for channel grpx1 and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x10 28. "INT_STAT_SCALER_OUT,The last write DMA transaction has completed for channel scaler_out" "0,1" newline hexmask.long.byte 0x10 20.--27. 1. "RESERVED,Reserved" bitfld.long 0x10 19. "INT_STAT_SCALER_CHROMA,The last write DMA transaction has completed for channel scaler_chroma" "0,1" newline bitfld.long 0x10 18. "INT_STAT_SCALER_LUMA,The last write DMA transaction has completed for channel scaler_luma" "0,1" bitfld.long 0x10 17. "INT_STAT_HQ_SCALER,The last write DMA transaction has completed for channel hq_scaler" "0,1" newline rbitfld.long 0x10 16. "RESERVED,Reserved" "0,1" bitfld.long 0x10 15. "INT_STAT_HQ_MV_OUT,The last write DMA transaction has completed for channel hq_mv_out" "0,1" newline rbitfld.long 0x10 13.--14. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x10 12. "INT_STAT_HQ_MV,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer" "0,1" newline rbitfld.long 0x10 6.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 5. "INT_STAT_HQ_VID3_CHROMA,The last write DMA transaction has completed for channel hq_vid3_chroma" "0,1" newline bitfld.long 0x10 4. "INT_STAT_HQ_VID3_LUMA,The last write DMA transaction has completed for channel hq_vid3_luma" "0,1" bitfld.long 0x10 3. "INT_STAT_HQ_VID2_CHROMA,The last write DMA transaction has completed for channel hq_vid2_chroma" "0,1" newline bitfld.long 0x10 2. "INT_STAT_HQ_VID2_LUMA,The last write DMA transaction has completed for channel hq_vid2_luma" "0,1" bitfld.long 0x10 1. "INT_STAT_HQ_VID1_CHROMA,The last write DMA transaction has completed for channel hq_vid1_chroma" "0,1" newline bitfld.long 0x10 0. "INT_STAT_HQ_VID1_LUMA,The last write DMA transaction has completed for channel hq_vid1_luma" "0,1" line.long 0x14 "VIP_INT0_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x14 31. "INT_MASK_GRPX3,The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 30. "INT_MASK_GRPX2,The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 29. "INT_MASK_GRPX1,The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 28. "INT_MASK_SCALER_OUT,The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int0" "0,1" newline hexmask.long.byte 0x14 20.--27. 1. "RESERVED,Reserved" bitfld.long 0x14 19. "INT_MASK_SCALER_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 18. "INT_MASK_SCALER_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 17. "INT_MASK_HQ_SCALER,The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int0" "0,1" newline rbitfld.long 0x14 16. "RESERVED,Reserved" "0,1" bitfld.long 0x14 15. "INT_MASK_HQ_MV_OUT,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int0" "0,1" newline rbitfld.long 0x14 13.--14. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x14 12. "INT_MASK_HQ_MV,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int0" "0,1" newline rbitfld.long 0x14 6.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 5. "INT_MASK_HQ_VID3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 4. "INT_MASK_HQ_VID3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 3. "INT_MASK_HQ_VID2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 2. "INT_MASK_HQ_VID2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 1. "INT_MASK_HQ_VID1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 0. "INT_MASK_HQ_VID1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x18 "VIP_INT0_CHANNEL1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x18 31. "INT_STAT_VIP1_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip1_mult_portb_src9" "0,1" bitfld.long 0x18 30. "INT_STAT_VIP1_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip1_mult_portb_src8" "0,1" newline bitfld.long 0x18 29. "INT_STAT_VIP1_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip1_mult_portb_src7" "0,1" bitfld.long 0x18 28. "INT_STAT_VIP1_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip1_mult_portb_src6" "0,1" newline bitfld.long 0x18 27. "INT_STAT_VIP1_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip1_mult_portb_src5" "0,1" bitfld.long 0x18 26. "INT_STAT_VIP1_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip1_mult_portb_src4" "0,1" newline bitfld.long 0x18 25. "INT_STAT_VIP1_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip1_mult_portb_src3" "0,1" bitfld.long 0x18 24. "INT_STAT_VIP1_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip1_mult_portb_src2" "0,1" newline bitfld.long 0x18 23. "INT_STAT_VIP1_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip1_mult_portb_src1" "0,1" bitfld.long 0x18 22. "INT_STAT_VIP1_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip1_mult_portb_src0" "0,1" newline bitfld.long 0x18 21. "INT_STAT_VIP1_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip1_mult_porta_src15" "0,1" bitfld.long 0x18 20. "INT_STAT_VIP1_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip1_mult_porta_src14" "0,1" newline bitfld.long 0x18 19. "INT_STAT_VIP1_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip1_mult_porta_src13" "0,1" bitfld.long 0x18 18. "INT_STAT_VIP1_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip1_mult_porta_src12" "0,1" newline bitfld.long 0x18 17. "INT_STAT_VIP1_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip1_mult_porta_src11" "0,1" bitfld.long 0x18 16. "INT_STAT_VIP1_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip1_mult_porta_src10" "0,1" newline bitfld.long 0x18 15. "INT_STAT_VIP1_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip1_mult_porta_src9" "0,1" bitfld.long 0x18 14. "INT_STAT_VIP1_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip1_mult_porta_src8" "0,1" newline bitfld.long 0x18 13. "INT_STAT_VIP1_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip1_mult_porta_src7" "0,1" bitfld.long 0x18 12. "INT_STAT_VIP1_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip1_mult_porta_src6" "0,1" newline bitfld.long 0x18 11. "INT_STAT_VIP1_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip1_mult_porta_src5" "0,1" bitfld.long 0x18 10. "INT_STAT_VIP1_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip1_mult_porta_src4" "0,1" newline bitfld.long 0x18 9. "INT_STAT_VIP1_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip1_mult_porta_src3" "0,1" bitfld.long 0x18 8. "INT_STAT_VIP1_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip1_mult_porta_src2" "0,1" newline bitfld.long 0x18 7. "INT_STAT_VIP1_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip1_mult_porta_src1" "0,1" bitfld.long 0x18 6. "INT_STAT_VIP1_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip1_mult_porta_src0" "0,1" newline rbitfld.long 0x18 0.--5. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "VIP_INT0_CHANNEL1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x1C 31. "INT_MASK_VIP1_MULT_PORTB_SRC9,The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 30. "INT_MASK_VIP1_MULT_PORTB_SRC8,The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 29. "INT_MASK_VIP1_MULT_PORTB_SRC7,The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 28. "INT_MASK_VIP1_MULT_PORTB_SRC6,The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 27. "INT_MASK_VIP1_MULT_PORTB_SRC5,The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 26. "INT_MASK_VIP1_MULT_PORTB_SRC4,The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 25. "INT_MASK_VIP1_MULT_PORTB_SRC3,The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 24. "INT_MASK_VIP1_MULT_PORTB_SRC2,The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 23. "INT_MASK_VIP1_MULT_PORTB_SRC1,The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 22. "INT_MASK_VIP1_MULT_PORTB_SRC0,The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 21. "INT_MASK_VIP1_MULT_PORTA_SRC15,The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 20. "INT_MASK_VIP1_MULT_PORTA_SRC14,The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 19. "INT_MASK_VIP1_MULT_PORTA_SRC13,The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 18. "INT_MASK_VIP1_MULT_PORTA_SRC12,The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 17. "INT_MASK_VIP1_MULT_PORTA_SRC11,The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 16. "INT_MASK_VIP1_MULT_PORTA_SRC10,The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 15. "INT_MASK_VIP1_MULT_PORTA_SRC9,The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 14. "INT_MASK_VIP1_MULT_PORTA_SRC8,The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 13. "INT_MASK_VIP1_MULT_PORTA_SRC7,The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 12. "INT_MASK_VIP1_MULT_PORTA_SRC6,The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 11. "INT_MASK_VIP1_MULT_PORTA_SRC5,The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 10. "INT_MASK_VIP1_MULT_PORTA_SRC4,The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 9. "INT_MASK_VIP1_MULT_PORTA_SRC3,The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 8. "INT_MASK_VIP1_MULT_PORTA_SRC2,The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 7. "INT_MASK_VIP1_MULT_PORTA_SRC1,The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 6. "INT_MASK_VIP1_MULT_PORTA_SRC0,The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline rbitfld.long 0x1C 0.--5. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "VIP_INT0_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x20 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x20 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" newline bitfld.long 0x20 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" bitfld.long 0x20 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" newline bitfld.long 0x20 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x20 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x20 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x20 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" newline bitfld.long 0x20 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" bitfld.long 0x20 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" newline bitfld.long 0x20 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x20 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x20 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x20 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" newline bitfld.long 0x20 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" bitfld.long 0x20 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" newline bitfld.long 0x20 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x20 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x20 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x20 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" newline bitfld.long 0x20 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" bitfld.long 0x20 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" newline bitfld.long 0x20 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x20 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x20 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x20 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" newline bitfld.long 0x20 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" bitfld.long 0x20 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" newline bitfld.long 0x20 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x20 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x20 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x20 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x24 "VIP_INT0_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x24 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x28 "VIP_INT0_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x28 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x28 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" newline bitfld.long 0x28 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" bitfld.long 0x28 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" newline bitfld.long 0x28 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x28 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x28 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x28 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" newline bitfld.long 0x28 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" bitfld.long 0x28 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" newline bitfld.long 0x28 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x28 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x28 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x28 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" newline bitfld.long 0x28 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" bitfld.long 0x28 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" newline bitfld.long 0x28 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x28 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x28 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x28 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" newline bitfld.long 0x28 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" bitfld.long 0x28 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" newline bitfld.long 0x28 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x28 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x28 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x28 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" newline bitfld.long 0x28 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" bitfld.long 0x28 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" newline bitfld.long 0x28 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x28 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x28 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x28 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x2C "VIP_INT0_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x2C 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x30 "VIP_INT0_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x30 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x30 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" newline bitfld.long 0x30 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" bitfld.long 0x30 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" newline bitfld.long 0x30 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x30 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x30 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x30 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" newline bitfld.long 0x30 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" bitfld.long 0x30 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" newline bitfld.long 0x30 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x30 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x30 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x30 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" newline bitfld.long 0x30 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" bitfld.long 0x30 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" newline bitfld.long 0x30 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x30 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x30 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x30 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" newline bitfld.long 0x30 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" bitfld.long 0x30 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" newline bitfld.long 0x30 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x30 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x30 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x30 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" newline bitfld.long 0x30 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" bitfld.long 0x30 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" newline bitfld.long 0x30 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x30 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x30 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x30 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x34 "VIP_INT0_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x34 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x38 "VIP_INT0_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x38 31. "INT_STAT_TRANSCODE2_CHROMA,The last write DMA transaction has completed for channel transcode2_chroma" "0,1" bitfld.long 0x38 30. "INT_STAT_TRANSCODE2_LUMA,The last write DMA transaction has completed for channel transcode2_luma" "0,1" newline bitfld.long 0x38 29. "INT_STAT_TRANSCODE1_CHROMA,The last write DMA transaction has completed for channel transcode1_luma" "0,1" bitfld.long 0x38 28. "INT_STAT_TRANSCODE1_LUMA,The last write DMA transaction has completed for channel transcode1_luma" "0,1" newline bitfld.long 0x38 27. "INT_STAT_AUX_IN,The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x38 26. "INT_STAT_PIP_FRAME,The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x38 25. "INT_STAT_POST_COMP_WR,The last write DMA transaction has completed for channel post_comp_wr" "0,1" bitfld.long 0x38 24. "INT_STAT_VBI_SD_VENC,The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer" "0,1" newline rbitfld.long 0x38 23. "RESERVED,Reserved" "0,1" bitfld.long 0x38 22. "INT_STAT_NF_LAST_CHROMA,The last write DMA transaction has completed for channel nf_last_chroma" "0,1" newline bitfld.long 0x38 21. "INT_STAT_NF_LAST_LUMA,The last write DMA transaction has completed for channel nf_last_luma" "0,1" bitfld.long 0x38 20. "INT_STAT_NF_WRITE_CHROMA,The last write DMA transaction has completed for channel nf_write_chroma" "0,1" newline bitfld.long 0x38 19. "INT_STAT_NF_WRITE_LUMA,The last write DMA transaction has completed for channel nf_write_luma" "0,1" bitfld.long 0x38 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" newline bitfld.long 0x38 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x38 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x38 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x38 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" newline bitfld.long 0x38 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" bitfld.long 0x38 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" newline bitfld.long 0x38 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x38 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x38 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x38 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" newline bitfld.long 0x38 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" bitfld.long 0x38 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" newline bitfld.long 0x38 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x38 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x38 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x38 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" newline bitfld.long 0x38 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" bitfld.long 0x38 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x3C "VIP_INT0_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x3C 31. "INT_MASK_TRANSCODE2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 30. "INT_MASK_TRANSCODE2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 29. "INT_MASK_TRANSCODE1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 28. "INT_MASK_TRANSCODE1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 27. "INT_MASK_AUX_IN,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 26. "INT_MASK_PIP_FRAME,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 25. "INT_MASK_POST_COMP_WR,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 24. "INT_MASK_VBI_SD_VENC,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline rbitfld.long 0x3C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x3C 22. "INT_MASK_NF_LAST_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 21. "INT_MASK_NF_LAST_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 20. "INT_MASK_NF_WRITE_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 19. "INT_MASK_NF_WRITE_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" group.long 0x78++0x47 line.long 0x00 "VIP_INT0_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x00 31. "INT_STAT_GRPX1_DATA,The client interface grpx1_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 30. "INT_STAT_COMP_WRBK,The client interface comp_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 29. "INT_STAT_SC_OUT,The client interface sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" hexmask.long.byte 0x00 21.--28. 1. "RESERVED,Reserved" newline bitfld.long 0x00 20. "INT_STAT_SC_IN_LUMA,The client interface sc_in_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 19. "INT_STAT_SC_IN_CHROMA,The client interface sc_in_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 18. "INT_STAT_PIP_WRBK,The client interface pip_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 17. "INT_STAT_DEI_SC_OUT,The client interface dei_sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline rbitfld.long 0x00 16. "RESERVED,Reserved" "0,1" bitfld.long 0x00 15. "INT_STAT_DEI_HQ_MV_OUT,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline rbitfld.long 0x00 13.--14. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x00 12. "INT_STAT_DEI_HQ_MV_IN,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline rbitfld.long 0x00 6.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 5. "INT_STAT_DEI_HQ_3_CHROMA,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 4. "INT_STAT_DEI_HQ_3_LUMA,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 3. "INT_STAT_DEI_HQ_2_CHROMA,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 2. "INT_STAT_DEI_HQ_2_LUMA,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 1. "INT_STAT_DEI_HQ_1_LUMA,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 0. "INT_STAT_DEI_HQ_1_CHROMA,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x04 "VIP_INT0_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x04 31. "INT_MASK_GRPX1_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 30. "INT_MASK_COMP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 29. "INT_MASK_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" hexmask.long.byte 0x04 21.--28. 1. "RESERVED,Reserved" newline bitfld.long 0x04 20. "INT_MASK_SC_IN_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 19. "INT_MASK_SC_IN_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 18. "INT_MASK_PIP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 17. "INT_MASK_DEI_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline rbitfld.long 0x04 16. "RESERVED,Reserved" "0,1" bitfld.long 0x04 15. "INT_MASK_DEI_HQ_MV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline rbitfld.long 0x04 13.--14. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x04 12. "INT_MASK_DEI_HQ_MV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline rbitfld.long 0x04 6.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 5. "INT_MASK_DEI_HQ_3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 4. "INT_MASK_DEI_HQ_3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 3. "INT_MASK_DEI_HQ_2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 2. "INT_MASK_DEI_HQ_2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 1. "INT_MASK_DEI_HQ_1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 0. "INT_MASK_DEI_HQ_1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x08 "VIP_INT0_CLIENT1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" rbitfld.long 0x08 31. "RESERVED,Reserved" "0,1" rbitfld.long 0x08 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 29. "INT_STAT_VIP2_ANC_B,The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 28. "INT_STAT_VIP2_ANC_A,The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 27. "INT_STAT_VIP1_ANC_B,The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 26. "INT_STAT_VIP1_ANC_A,The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 25. "INT_STAT_TRANS2_LUMA,The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 24. "INT_STAT_TRANS2_CHROMA,The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 23. "INT_STAT_TRANS1_LUMA,The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 22. "INT_STAT_TRANS1_CHROMA,The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 21. "INT_STAT_HDMI_WRBK_OUT,The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 20. "INT_STAT_VPI_CTL,The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 19. "INT_STAT_VBI_SDVENC,The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" rbitfld.long 0x08 18. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 17. "INT_STAT_NF_420_UV_OUT,The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 16. "INT_STAT_NF_420_Y_OUT,The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 15. "INT_STAT_NF_420_UV_IN,The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 14. "INT_STAT_NF_420_Y_IN,The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 13. "INT_STAT_NF_422_IN,The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 12. "INT_STAT_GRPX3_ST,The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 11. "INT_STAT_GRPX2_ST,The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 10. "INT_STAT_GRPX1_ST,The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 9. "INT_STAT_VIP2_UP_UV,The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 8. "INT_STAT_VIP2_UP_Y,The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 7. "INT_STAT_VIP2_LO_UV,The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 6. "INT_STAT_VIP2_LO_Y,The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 5. "INT_STAT_VIP1_UP_UV,The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 4. "INT_STAT_VIP1_UP_Y,The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 3. "INT_STAT_VIP1_LO_UV,The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 2. "INT_STAT_VIP1_LO_Y,The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 1. "INT_STAT_GRPX3_DATA,The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 0. "INT_STAT_GRPX2_DATA,The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x0C "VIP_INT0_CLIENT1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" rbitfld.long 0x0C 31. "RESERVED,Reserved" "0,1" rbitfld.long 0x0C 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 29. "INT_MASK_VIP2_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 28. "INT_MASK_VIP2_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 27. "INT_MASK_VIP1_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 26. "INT_MASK_VIP1_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 25. "INT_MASK_TRANS2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 24. "INT_MASK_TRANS2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 23. "INT_MASK_TRANS1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 22. "INT_MASK_TRANS1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 21. "INT_MASK_HDMI_WRBK_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 20. "INT_MASK_VPI_CTL,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 19. "INT_MASK_VBI_SDVENC,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" rbitfld.long 0x0C 18. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 17. "INT_MASK_NF_420_UV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 16. "INT_MASK_NF_420_Y_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 15. "INT_MASK_NF_420_UV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 14. "INT_MASK_NF_420_Y_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 13. "INT_MASK_NF_422_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 12. "INT_MASK_GRPX3_ST,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 11. "INT_MASK_GRPX2_ST,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 10. "INT_MASK_GRPX1_ST,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 9. "INT_MASK_VIP2_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 8. "INT_MASK_VIP2_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 7. "INT_MASK_VIP2_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 6. "INT_MASK_VIP2_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 5. "INT_MASK_VIP1_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 4. "INT_MASK_VIP1_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 3. "INT_MASK_VIP1_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 2. "INT_MASK_VIP1_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 1. "INT_MASK_GRPX3_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 0. "INT_MASK_GRPX2_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x10 "VIP_INT0_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x10 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x10 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" newline bitfld.long 0x10 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" bitfld.long 0x10 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" newline bitfld.long 0x10 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x10 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x10 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x10 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" newline bitfld.long 0x10 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" bitfld.long 0x10 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" newline bitfld.long 0x10 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x10 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x10 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x10 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" newline bitfld.long 0x10 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" bitfld.long 0x10 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" newline bitfld.long 0x10 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x14 "VIP_INT0_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x14 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x18 "VIP_INT1_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x18 31. "INT_STAT_GRPX3,The last write DMA transaction has completed for channel scaler_out" "0,1" bitfld.long 0x18 30. "INT_STAT_GRPX2,The last write DMA transaction has completed for channel scaler_out" "0,1" newline bitfld.long 0x18 29. "INT_STAT_GRPX1,The last write DMA transaction has completed for channel scaler_out" "0,1" bitfld.long 0x18 28. "INT_STAT_SCALER_OUT,The last write DMA transaction has completed for channel scaler_out" "0,1" newline hexmask.long.byte 0x18 20.--27. 1. "RESERVED,Reserved" bitfld.long 0x18 19. "INT_STAT_SCALER_CHROMA,The last write DMA transaction has completed for channel scaler_luma" "0,1" newline bitfld.long 0x18 18. "INT_STAT_SCALER_LUMA,The last write DMA transaction has completed for channel scaler_luma" "0,1" bitfld.long 0x18 17. "INT_STAT_HQ_SCALER,The last write DMA transaction has completed for channel hq_scaler" "0,1" newline rbitfld.long 0x18 16. "RESERVED,Reserved" "0,1" bitfld.long 0x18 15. "INT_STAT_HQ_MV_OUT,The last write DMA transaction has completed for channel hq_mv_out" "0,1" newline rbitfld.long 0x18 13.--14. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x18 12. "INT_STAT_HQ_MV,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer" "0,1" newline rbitfld.long 0x18 6.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 5. "INT_STAT_HQ_VID3_CHROMA,The last write DMA transaction has completed for channel hq_vid3_chroma" "0,1" newline bitfld.long 0x18 4. "INT_STAT_HQ_VID3_LUMA,The last write DMA transaction has completed for channel hq_vid3_luma" "0,1" bitfld.long 0x18 3. "INT_STAT_HQ_VID2_CHROMA,The last write DMA transaction has completed for channel hq_vid2_chroma" "0,1" newline bitfld.long 0x18 2. "INT_STAT_HQ_VID2_LUMA,The last write DMA transaction has completed for channel hq_vid2_luma" "0,1" bitfld.long 0x18 1. "INT_STAT_HQ_VID1_CHROMA,The last write DMA transaction has completed for channel hq_vid1_chroma" "0,1" newline bitfld.long 0x18 0. "INT_STAT_HQ_VID1_LUMA,The last write DMA transaction has completed for channel hq_vid1_luma" "0,1" line.long 0x1C "VIP_INT1_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x1C 31. "INT_MASK_GRPX3,The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 30. "INT_MASK_GRPX2,The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 29. "INT_MASK_GRPX1,The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 28. "INT_MASK_SCALER_OUT,The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int1" "0,1" newline hexmask.long.byte 0x1C 20.--27. 1. "RESERVED,Reserved" bitfld.long 0x1C 19. "INT_MASK_SCALER_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 18. "INT_MASK_SCALER_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 17. "INT_MASK_HQ_SCALER,The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x1C 16. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 15. "INT_MASK_HQ_MV_OUT,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x1C 13.--14. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x1C 12. "INT_MASK_HQ_MV,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x1C 6.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 5. "INT_MASK_HQ_VID3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 4. "INT_MASK_HQ_VID3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 3. "INT_MASK_HQ_VID2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 2. "INT_MASK_HQ_VID2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 1. "INT_MASK_HQ_VID1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 0. "INT_MASK_HQ_VID1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x20 "VIP_INT1_CHANNEL1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x20 31. "INT_STAT_VIP1_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip1_mult_portb_src9" "0,1" bitfld.long 0x20 30. "INT_STAT_VIP1_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip1_mult_portb_src8" "0,1" newline bitfld.long 0x20 29. "INT_STAT_VIP1_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip1_mult_portb_src7" "0,1" bitfld.long 0x20 28. "INT_STAT_VIP1_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip1_mult_portb_src6" "0,1" newline bitfld.long 0x20 27. "INT_STAT_VIP1_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip1_mult_portb_src5" "0,1" bitfld.long 0x20 26. "INT_STAT_VIP1_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip1_mult_portb_src4" "0,1" newline bitfld.long 0x20 25. "INT_STAT_VIP1_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip1_mult_portb_src3" "0,1" bitfld.long 0x20 24. "INT_STAT_VIP1_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip1_mult_portb_src2" "0,1" newline bitfld.long 0x20 23. "INT_STAT_VIP1_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip1_mult_portb_src1" "0,1" bitfld.long 0x20 22. "INT_STAT_VIP1_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip1_mult_portb_src0" "0,1" newline bitfld.long 0x20 21. "INT_STAT_VIP1_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip1_mult_porta_src15" "0,1" bitfld.long 0x20 20. "INT_STAT_VIP1_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip1_mult_porta_src14" "0,1" newline bitfld.long 0x20 19. "INT_STAT_VIP1_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip1_mult_porta_src13" "0,1" bitfld.long 0x20 18. "INT_STAT_VIP1_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip1_mult_porta_src12" "0,1" newline bitfld.long 0x20 17. "INT_STAT_VIP1_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip1_mult_porta_src11" "0,1" bitfld.long 0x20 16. "INT_STAT_VIP1_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip1_mult_porta_src10" "0,1" newline bitfld.long 0x20 15. "INT_STAT_VIP1_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip1_mult_porta_src9" "0,1" bitfld.long 0x20 14. "INT_STAT_VIP1_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip1_mult_porta_src8" "0,1" newline bitfld.long 0x20 13. "INT_STAT_VIP1_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip1_mult_porta_src7" "0,1" bitfld.long 0x20 12. "INT_STAT_VIP1_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip1_mult_porta_src6" "0,1" newline bitfld.long 0x20 11. "INT_STAT_VIP1_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip1_mult_porta_src5" "0,1" bitfld.long 0x20 10. "INT_STAT_VIP1_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip1_mult_porta_src4" "0,1" newline bitfld.long 0x20 9. "INT_STAT_VIP1_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip1_mult_porta_src3" "0,1" bitfld.long 0x20 8. "INT_STAT_VIP1_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip1_mult_porta_src2" "0,1" newline bitfld.long 0x20 7. "INT_STAT_VIP1_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip1_mult_porta_src1" "0,1" bitfld.long 0x20 6. "INT_STAT_VIP1_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip1_mult_porta_src0" "0,1" newline rbitfld.long 0x20 0.--5. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "VIP_INT1_CHANNEL1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x24 31. "INT_MASK_VIP1_MULT_PORTB_SRC9,The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 30. "INT_MASK_VIP1_MULT_PORTB_SRC8,The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 29. "INT_MASK_VIP1_MULT_PORTB_SRC7,The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 28. "INT_MASK_VIP1_MULT_PORTB_SRC6,The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 27. "INT_MASK_VIP1_MULT_PORTB_SRC5,The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 26. "INT_MASK_VIP1_MULT_PORTB_SRC4,The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 25. "INT_MASK_VIP1_MULT_PORTB_SRC3,The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 24. "INT_MASK_VIP1_MULT_PORTB_SRC2,The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 23. "INT_MASK_VIP1_MULT_PORTB_SRC1,The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 22. "INT_MASK_VIP1_MULT_PORTB_SRC0,The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 21. "INT_MASK_VIP1_MULT_PORTA_SRC15,The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 20. "INT_MASK_VIP1_MULT_PORTA_SRC14,The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 19. "INT_MASK_VIP1_MULT_PORTA_SRC13,The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 18. "INT_MASK_VIP1_MULT_PORTA_SRC12,The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 17. "INT_MASK_VIP1_MULT_PORTA_SRC11,The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 16. "INT_MASK_VIP1_MULT_PORTA_SRC10,The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 15. "INT_MASK_VIP1_MULT_PORTA_SRC9,The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 14. "INT_MASK_VIP1_MULT_PORTA_SRC8,The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 13. "INT_MASK_VIP1_MULT_PORTA_SRC7,The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 12. "INT_MASK_VIP1_MULT_PORTA_SRC6,The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 11. "INT_MASK_VIP1_MULT_PORTA_SRC5,The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 10. "INT_MASK_VIP1_MULT_PORTA_SRC4,The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 9. "INT_MASK_VIP1_MULT_PORTA_SRC3,The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 8. "INT_MASK_VIP1_MULT_PORTA_SRC2,The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 7. "INT_MASK_VIP1_MULT_PORTA_SRC1,The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 6. "INT_MASK_VIP1_MULT_PORTA_SRC0,The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x24 0.--5. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "VIP_INT1_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x28 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x28 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" newline bitfld.long 0x28 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" bitfld.long 0x28 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" newline bitfld.long 0x28 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x28 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x28 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x28 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" newline bitfld.long 0x28 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" bitfld.long 0x28 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" newline bitfld.long 0x28 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x28 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x28 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x28 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" newline bitfld.long 0x28 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" bitfld.long 0x28 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" newline bitfld.long 0x28 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x28 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x28 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x28 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" newline bitfld.long 0x28 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" bitfld.long 0x28 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" newline bitfld.long 0x28 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x28 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x28 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x28 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" newline bitfld.long 0x28 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" bitfld.long 0x28 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" newline bitfld.long 0x28 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x28 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x28 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x28 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x2C "VIP_INT1_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x2C 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x30 "VIP_INT1_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x30 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x30 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" newline bitfld.long 0x30 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" bitfld.long 0x30 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" newline bitfld.long 0x30 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x30 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x30 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x30 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" newline bitfld.long 0x30 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" bitfld.long 0x30 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" newline bitfld.long 0x30 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x30 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x30 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x30 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" newline bitfld.long 0x30 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" bitfld.long 0x30 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" newline bitfld.long 0x30 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x30 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x30 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x30 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" newline bitfld.long 0x30 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" bitfld.long 0x30 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" newline bitfld.long 0x30 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x30 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x30 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x30 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" newline bitfld.long 0x30 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" bitfld.long 0x30 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" newline bitfld.long 0x30 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x30 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x30 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x30 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x34 "VIP_INT1_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x34 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x38 "VIP_INT1_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x38 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x38 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" newline bitfld.long 0x38 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" bitfld.long 0x38 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" newline bitfld.long 0x38 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x38 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x38 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x38 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" newline bitfld.long 0x38 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" bitfld.long 0x38 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" newline bitfld.long 0x38 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x38 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x38 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x38 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" newline bitfld.long 0x38 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" bitfld.long 0x38 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" newline bitfld.long 0x38 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x38 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x38 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x38 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" newline bitfld.long 0x38 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" bitfld.long 0x38 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" newline bitfld.long 0x38 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x38 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x38 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x38 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" newline bitfld.long 0x38 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" bitfld.long 0x38 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" newline bitfld.long 0x38 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x38 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x38 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x38 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x3C "VIP_INT1_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x3C 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x40 "VIP_INT1_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x40 31. "INT_STAT_TRANSCODE2_CHROMA,The last write DMA transaction has completed for channel transcode2_chroma" "0,1" bitfld.long 0x40 30. "INT_STAT_TRANSCODE2_LUMA,The last write DMA transaction has completed for channel transcode2_luma" "0,1" newline bitfld.long 0x40 29. "INT_STAT_TRANSCODE1_CHROMA,The last write DMA transaction has completed for channel transcode1_chroma" "0,1" bitfld.long 0x40 28. "INT_STAT_TRANSCODE1_LUMA,The last write DMA transaction has completed for channel transcode1_luma" "0,1" newline bitfld.long 0x40 27. "INT_STAT_AUX_IN,The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x40 26. "INT_STAT_PIP_FRAME,The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x40 25. "INT_STAT_POST_COMP_WR,The last write DMA transaction has completed for channel post_comp_wr" "0,1" bitfld.long 0x40 24. "INT_STAT_VBI_SD_VENC,The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer" "0,1" newline rbitfld.long 0x40 23. "RESERVED,Reserved" "0,1" bitfld.long 0x40 22. "INT_STAT_NF_LAST_CHROMA,The last write DMA transaction has completed for channel nf_last_chroma" "0,1" newline bitfld.long 0x40 21. "INT_STAT_NF_LAST_LUMA,The last write DMA transaction has completed for channel nf_last_luma" "0,1" bitfld.long 0x40 20. "INT_STAT_NF_WRITE_CHROMA,The last write DMA transaction has completed for channel nf_write_chroma" "0,1" newline bitfld.long 0x40 19. "INT_STAT_NF_WRITE_LUMA,The last write DMA transaction has completed for channel nf_write_luma" "0,1" bitfld.long 0x40 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" newline bitfld.long 0x40 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x40 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x40 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x40 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" newline bitfld.long 0x40 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" bitfld.long 0x40 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" newline bitfld.long 0x40 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x40 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x40 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x40 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" newline bitfld.long 0x40 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" bitfld.long 0x40 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" newline bitfld.long 0x40 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x40 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x40 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x40 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" newline bitfld.long 0x40 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" bitfld.long 0x40 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x44 "VIP_INT1_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x44 31. "INT_MASK_TRANSCODE2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 30. "INT_MASK_TRANSCODE2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 29. "INT_MASK_TRANSCODE1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 28. "INT_MASK_TRANSCODE1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 27. "INT_MASK_AUX_IN,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 26. "INT_MASK_PIP_FRAME,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 25. "INT_MASK_POST_COMP_WR,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 24. "INT_MASK_VBI_SD_VENC,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x44 23. "RESERVED,Reserved" "0,1" bitfld.long 0x44 22. "INT_MASK_NF_LAST_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 21. "INT_MASK_NF_LAST_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 20. "INT_MASK_NF_WRITE_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 19. "INT_MASK_NF_WRITE_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" group.long 0xC8++0x17 line.long 0x00 "VIP_INT1_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x00 31. "INT_MASK_TRANSCODE2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 30. "INT_MASK_TRANSCODE2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 29. "INT_MASK_TRANSCODE1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 28. "INT_MASK_TRANSCODE1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 27. "INT_MASK_AUX_IN,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 26. "INT_MASK_PIP_FRAME,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 25. "INT_MASK_POST_COMP_WR,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 24. "INT_MASK_VBI_SD_VENC,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x00 23. "RESERVED,Reserved" "0,1" bitfld.long 0x00 22. "INT_MASK_NF_LAST_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 21. "INT_MASK_NF_LAST_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 20. "INT_MASK_NF_WRITE_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 19. "INT_MASK_NF_WRITE_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 18. "INT_MASK_NF_READ,The interrupt for Noise Filter Input Data 422 Interleaved should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 15. "INT_STAT_DEI_HQ_MV_OUT,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" rbitfld.long 0x00 13.--14. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x00 12. "INT_STAT_DEI_HQ_MV_IN,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" rbitfld.long 0x00 6.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5. "INT_STAT_DEI_HQ_3_CHROMA,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 4. "INT_STAT_DEI_HQ_3_LUMA,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 3. "INT_STAT_DEI_HQ_2_CHROMA,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 2. "INT_STAT_DEI_HQ_2_LUMA,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 1. "INT_STAT_DEI_HQ_1_LUMA,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 0. "INT_STAT_DEI_HQ_1_CHROMA,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x04 "VIP_INT1_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x04 31. "INT_MASK_GRPX1_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 30. "INT_MASK_COMP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 29. "INT_MASK_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" hexmask.long.byte 0x04 21.--28. 1. "RESERVED,Reserved" newline bitfld.long 0x04 20. "INT_MASK_SC_IN_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 19. "INT_MASK_SC_IN_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 18. "INT_MASK_PIP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 17. "INT_MASK_DEI_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x04 16. "RESERVED,Reserved" "0,1" bitfld.long 0x04 15. "INT_MASK_DEI_HQ_MV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x04 13.--14. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x04 12. "INT_MASK_DEI_HQ_MV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline rbitfld.long 0x04 6.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 5. "INT_MASK_DEI_HQ_3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 4. "INT_MASK_DEI_HQ_3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 3. "INT_MASK_DEI_HQ_2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 2. "INT_MASK_DEI_HQ_2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 1. "INT_MASK_DEI_HQ_1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 0. "INT_MASK_DEI_HQ_1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x08 "VIP_INT1_CLIENT1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" rbitfld.long 0x08 31. "RESERVED,Reserved" "0,1" rbitfld.long 0x08 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 29. "INT_STAT_VIP2_ANC_B,The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 28. "INT_STAT_VIP2_ANC_A,The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 27. "INT_STAT_VIP1_ANC_B,The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 26. "INT_STAT_VIP1_ANC_A,The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 25. "INT_STAT_TRANS2_LUMA,The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 24. "INT_STAT_TRANS2_CHROMA,The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 23. "INT_STAT_TRANS1_LUMA,The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 22. "INT_STAT_TRANS1_CHROMA,The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 21. "INT_STAT_HDMI_WRBK_OUT,The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 20. "INT_STAT_VPI_CTL,The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 19. "INT_STAT_VBI_SDVENC,The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" rbitfld.long 0x08 18. "RESERVED,Reserved" "0,1" newline bitfld.long 0x08 17. "INT_STAT_NF_420_UV_OUT,The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 16. "INT_STAT_NF_420_Y_OUT,The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 15. "INT_STAT_NF_420_UV_IN,The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 14. "INT_STAT_NF_420_Y_IN,The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 13. "INT_STAT_NF_422_IN,The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 12. "INT_STAT_GRPX3_ST,The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 11. "INT_STAT_GRPX2_ST,The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 10. "INT_STAT_GRPX1_ST,The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 9. "INT_STAT_VIP2_UP_UV,The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 8. "INT_STAT_VIP2_UP_Y,The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 7. "INT_STAT_VIP2_LO_UV,The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 6. "INT_STAT_VIP2_LO_Y,The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 5. "INT_STAT_VIP1_UP_UV,The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 4. "INT_STAT_VIP1_UP_Y,The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 3. "INT_STAT_VIP1_LO_UV,The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 2. "INT_STAT_VIP1_LO_Y,The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 1. "INT_STAT_GRPX3_DATA,The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 0. "INT_STAT_GRPX2_DATA,The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x0C "VIP_INT1_CLIENT1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" rbitfld.long 0x0C 31. "RESERVED,Reserved" "0,1" rbitfld.long 0x0C 30. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 29. "INT_MASK_VIP2_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 28. "INT_MASK_VIP2_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 27. "INT_MASK_VIP1_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 26. "INT_MASK_VIP1_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 25. "INT_MASK_TRANS2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 24. "INT_MASK_TRANS2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 23. "INT_MASK_TRANS1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 22. "INT_MASK_TRANS1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 21. "INT_MASK_HDMI_WRBK_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 20. "INT_MASK_VPI_CTL,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 19. "INT_MASK_VBI_SDVENC,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" rbitfld.long 0x0C 18. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0C 17. "INT_MASK_NF_420_UV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 16. "INT_MASK_NF_420_Y_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 15. "INT_MASK_NF_420_UV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 14. "INT_MASK_NF_420_Y_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 13. "INT_MASK_NF_422_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 12. "INT_MASK_GRPX3_ST,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 11. "INT_MASK_GRPX2_ST,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 10. "INT_MASK_GRPX1_ST,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 9. "INT_MASK_VIP2_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 8. "INT_MASK_VIP2_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 7. "INT_MASK_VIP2_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 6. "INT_MASK_VIP2_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 5. "INT_MASK_VIP1_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 4. "INT_MASK_VIP1_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 3. "INT_MASK_VIP1_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 2. "INT_MASK_VIP1_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 1. "INT_MASK_GRPX3_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 0. "INT_MASK_GRPX2_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x10 "VIP_INT1_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x10 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x10 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" newline bitfld.long 0x10 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" bitfld.long 0x10 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" newline bitfld.long 0x10 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x10 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x10 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x10 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" newline bitfld.long 0x10 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" bitfld.long 0x10 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" newline bitfld.long 0x10 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x10 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x10 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x10 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" newline bitfld.long 0x10 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" bitfld.long 0x10 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" newline bitfld.long 0x10 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x14 "VIP_INT1_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x14 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" group.long 0x388++0x1F line.long 0x00 "VIP0_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--9. 1. "RESERVED," line.long 0x04 "VIP0_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--9. 1. "RESERVED," line.long 0x08 "VIP0_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x08 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x08 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x08 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x08 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x08 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x08 0.--9. 1. "RESERVED," line.long 0x0C "VIP0_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x0C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x0C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x0C 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x0C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x0C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0C 0.--9. 1. "RESERVED," line.long 0x10 "VIP1_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x10 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x10 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x10 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x10 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x10 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x10 0.--9. 1. "RESERVED," line.long 0x14 "VIP1_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x14 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x14 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x14 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x14 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x14 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x14 0.--9. 1. "RESERVED," line.long 0x18 "VIP1_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x18 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x18 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x18 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x18 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x18 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x18 0.--9. 1. "RESERVED," line.long 0x1C "VIP1_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x1C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x1C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x1C 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x1C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x1C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 0.--9. 1. "RESERVED," group.long 0x3D0++0x03 line.long 0x00 "VPI_CTL_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--9. 1. "RESERVED," group.long 0x3E8++0x0F line.long 0x00 "VIP0_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--9. 1. "RESERVED," line.long 0x04 "VIP0_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--9. 1. "RESERVED," line.long 0x08 "VIP1_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x08 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x08 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x08 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x08 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x08 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x08 0.--9. 1. "RESERVED," line.long 0x0C "VIP1_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x0C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x0C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x0C 15. "BUSY,Signals if the client is currently active" "0,1" rbitfld.long 0x0C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x0C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0C 0.--9. 1. "RESERVED," repeat 14. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 ) group.long ($2+0x2C0)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline rbitfld.long 0x00 27. "RESERVED," "0,1" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline rbitfld.long 0x00 19. "RESERVED," "0,1" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" newline hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x280)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline rbitfld.long 0x00 27. "RESERVED," "0,1" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline rbitfld.long 0x00 19. "RESERVED," "0,1" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" newline hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x240)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline rbitfld.long 0x00 27. "RESERVED," "0,1" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline rbitfld.long 0x00 19. "RESERVED," "0,1" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" newline hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x200)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline rbitfld.long 0x00 27. "RESERVED," "0,1" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" newline rbitfld.long 0x00 22.--23. "RESERVED," "0,1,2,3" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline rbitfld.long 0x00 19. "RESERVED," "0,1" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" newline hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end width 0x0B tree.end tree "WKUPAON_CM" base ad:0x4AE07800 group.long 0x00++0x03 line.long 0x00 "CM_WKUPAON_CLKSTCTRL,This register enables the domain power state transition" hexmask.long.word 0x00 20.--31. 1. "RESERVED," newline rbitfld.long 0x00 19. "CLKACTIVITY_ADC_L3_GICLK,This field indicates the state of the ADC_L3_GICLK clock in the domain(it includes profiling EMU_SYS_GCLK and all functional SYS_CLK. [warm reset insensitive]" "CLKACTIVITY_ADC_L3_GICLK_0,CLKACTIVITY_ADC_L3_GICLK_1" newline rbitfld.long 0x00 18. "CLKACTIVITY_UART10_GFCLK,This field indicates the state of the UART10_GFCLK clock in the domain" "CLKACTIVITY_UART10_GFCLK_0,CLKACTIVITY_UART10_GFCLK_1" newline rbitfld.long 0x00 17. "CLKACTIVITY_TIMER1_GFCLK,This field indicates the state of the TIMER1_GFCLK clock in the domain" "CLKACTIVITY_TIMER1_GFCLK_0,CLKACTIVITY_TIMER1_GFCLK_1" newline rbitfld.long 0x00 16. "CLKACTIVITY_DCAN1_SYS_CLK,This field indicates the state of the DCAN1_SYS_CLK clock in the domain" "CLKACTIVITY_DCAN1_SYS_CLK_0,CLKACTIVITY_DCAN1_SYS_CLK_1" newline rbitfld.long 0x00 15. "CLKACTIVITY_SYS_CLK_ALL,This field indicates the state of the SYS_CLK runing at SCRM level because of any SCRM clock request" "CLKACTIVITY_SYS_CLK_ALL_0,CLKACTIVITY_SYS_CLK_ALL_1" newline rbitfld.long 0x00 14. "CLKACTIVITY_SYS_CLK_FUNC,This field indicates the state of the functional SYS_CLK clocks in the domain (this exclude activity of EMU_GCLK clock)" "CLKACTIVITY_SYS_CLK_FUNC_0,CLKACTIVITY_SYS_CLK_FUNC_1" newline rbitfld.long 0x00 13. "CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK,This field indicates the state of the WKUPAON_IO_SRCOMP_GFCLK clock in the domain" "CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_0,CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_WKUPAON_GICLK,This field indicates the state of the WKUPAON_GICLK clock in the domain" "CLKACTIVITY_WKUPAON_GICLK_0,CLKACTIVITY_WKUPAON_GICLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_WKUPAON_SYS_GFCLK,This field indicates the state of the WKUPAON_SYS_GFCLK clock in the domain" "CLKACTIVITY_WKUPAON_SYS_GFCLK_0,CLKACTIVITY_WKUPAON_SYS_GFCLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_ADC_GFCLK,This field indicates the state of the ADC_GFCLK clock in the domain" "CLKACTIVITY_ADC_GFCLK_0,CLKACTIVITY_ADC_GFCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_ABE_LP_CLK,This field indicates the state of the ABE_LP_CLK clock in the domain" "CLKACTIVITY_ABE_LP_CLK_0,CLKACTIVITY_ABE_LP_CLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_SYS_CLK,This field indicates the state of the SYS_CLK clock in the domain(it includes profiling EMU_SYS_GCLK and all functional SYS_CLK. [warm reset insensitive]" "CLKACTIVITY_SYS_CLK_0,CLKACTIVITY_SYS_CLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the WKUPAON clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" rgroup.long 0x20++0x03 line.long 0x00 "CM_WKUPAON_L4_WKUP_CLKCTRL,This register manages the WKUPAON clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x28++0x03 line.long 0x00 "CM_WKUPAON_WD_TIMER1_CLKCTRL,This register manages the WD_TIMER1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x30++0x03 line.long 0x00 "CM_WKUPAON_WD_TIMER2_CLKCTRL,This register manages the WD_TIMER2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x38++0x03 line.long 0x00 "CM_WKUPAON_GPIO1_CLKCTRL,This register manages the GPIO1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.byte 0x00 9.--15. 1. "RESERVED," newline bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline rbitfld.long 0x00 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_WKUPAON_TIMER1_CLKCTRL,This register manages the TIMER1 clocks" rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x48++0x03 line.long 0x00 "CM_WKUPAON_TIMER12_CLKCTRL,This register manages the TIMER12 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x50++0x03 line.long 0x00 "CM_WKUPAON_COUNTER_32K_CLKCTRL,This register manages the COUNTER_32K clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x60++0x03 line.long 0x00 "CM_WKUPAON_SAR_RAM_CLKCTRL,This register manages the SAR_RAM clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x78++0x03 line.long 0x00 "CM_WKUPAON_KBD_CLKCTRL,This register manages the KBD clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x80++0x03 line.long 0x00 "CM_WKUPAON_UART10_CLKCTRL,This register manages the UART10 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," newline bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x88++0x03 line.long 0x00 "CM_WKUPAON_DCAN1_CLKCTRL,This register manages the DCAN1 clocks" hexmask.long.byte 0x00 25.--31. 1. "RESERVED," newline bitfld.long 0x00 24. "CLKSEL,Selects functional clock for DCAN1" "CLKSEL_0,CLKSEL_1" newline rbitfld.long 0x00 18.--23. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x90++0x03 line.long 0x00 "CM_WKUPAON_SCRM_CLKCTRL,This register manages the SCRM clocks" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," newline bitfld.long 0x00 9. "OPTFCLKEN_SCRM_PER,Optional functional clock control" "OPTFCLKEN_SCRM_PER_0,OPTFCLKEN_SCRM_PER_1" newline bitfld.long 0x00 8. "OPTFCLKEN_SCRM_CORE,Optional functional clock control" "OPTFCLKEN_SCRM_CORE_0,OPTFCLKEN_SCRM_CORE_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0x98++0x03 line.long 0x00 "CM_WKUPAON_IO_SRCOMP_CLKCTRL,This register manages the clock delivered to the IO Slew rate compensation cells" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," newline bitfld.long 0x00 8. "CLKEN_SRCOMP_FCLK,Functional clock control" "CLKEN_SRCOMP_FCLK_0,CLKEN_SRCOMP_FCLK_1" newline hexmask.long.byte 0x00 0.--7. 1. "RESERVED," group.long 0xA0++0x03 line.long 0x00 "CM_WKUPAON_ADC_CLKCTRL,This register manages the ADC clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0xB0++0x03 line.long 0x00 "CM_WKUPAON_SPARE_SAFETY1_CLKCTRL,This register manages the SPARE_SAFETY1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xB8++0x03 line.long 0x00 "CM_WKUPAON_RTI1_CLKCTRL,This register manages the RTI1 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xC0++0x03 line.long 0x00 "CM_WKUPAON_RTI2_CLKCTRL,This register manages the RTI2 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xC8++0x03 line.long 0x00 "CM_WKUPAON_RTI3_CLKCTRL,This register manages the RTI3 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xD0++0x03 line.long 0x00 "CM_WKUPAON_RTI4_CLKCTRL,This register manages the RTI4 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0xD8++0x03 line.long 0x00 "CM_WKUPAON_RTI5_CLKCTRL,This register manages the RTI5 clocks" hexmask.long.word 0x00 18.--31. 1. "RESERVED," newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline hexmask.long.word 0x00 2.--15. 1. "RESERVED," newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" width 0x0B tree.end tree "WKUPAON_PRM" base ad:0x4AE07724 group.long 0x00++0x2B line.long 0x00 "RM_WKUPAON_L4_WKUP_CONTEXT,This register contains dedicated L4_WKUP context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_WKUPAON_WD_TIMER1_WKDEP,This register controls wakeup dependency based on WD_TIMER1 service requests" hexmask.long.tbyte 0x04 10.--31. 1. "RESERVED," bitfld.long 0x04 9. "WKUPDEP_WD_TIMER1_EVE4,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER1_EVE4_0,WKUPDEP_WD_TIMER1_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_WD_TIMER1_EVE3,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER1_EVE3_0,WKUPDEP_WD_TIMER1_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_WD_TIMER1_EVE2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER1_EVE2_0,WKUPDEP_WD_TIMER1_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_WD_TIMER1_EVE1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER1_EVE1_0,WKUPDEP_WD_TIMER1_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_WD_TIMER1_DSP2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER1_DSP2_0,WKUPDEP_WD_TIMER1_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_WD_TIMER1_IPU1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER1_IPU1_0,WKUPDEP_WD_TIMER1_IPU1_1" rbitfld.long 0x04 3. "RESERVED," "0,1" newline bitfld.long 0x04 2. "WKUPDEP_WD_TIMER1_DSP1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER1_DSP1_0,WKUPDEP_WD_TIMER1_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_WD_TIMER1_IPU2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER1_IPU2_0,WKUPDEP_WD_TIMER1_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_WD_TIMER1_MPU,Wakeup dependency from WDT1 module (SWakeup signal) towards MPU + L3MAIN1 + L4CFG domains" "WKUPDEP_WD_TIMER1_MPU_0,WKUPDEP_WD_TIMER1_MPU_1" line.long 0x08 "RM_WKUPAON_WD_TIMER1_CONTEXT,This register contains dedicated WD_TIMER1 context statuses" hexmask.long 0x08 1.--31. 1. "RESERVED," bitfld.long 0x08 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x0C "PM_WKUPAON_WD_TIMER2_WKDEP,This register controls wakeup dependency based on WD_TIMER2 service requests" hexmask.long.tbyte 0x0C 10.--31. 1. "RESERVED," bitfld.long 0x0C 9. "WKUPDEP_WD_TIMER2_EVE4,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_EVE4_0,WKUPDEP_WD_TIMER2_EVE4_1" newline bitfld.long 0x0C 8. "WKUPDEP_WD_TIMER2_EVE3,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_EVE3_0,WKUPDEP_WD_TIMER2_EVE3_1" bitfld.long 0x0C 7. "WKUPDEP_WD_TIMER2_EVE2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_EVE2_0,WKUPDEP_WD_TIMER2_EVE2_1" newline bitfld.long 0x0C 6. "WKUPDEP_WD_TIMER2_EVE1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_EVE1_0,WKUPDEP_WD_TIMER2_EVE1_1" bitfld.long 0x0C 5. "WKUPDEP_WD_TIMER2_DSP2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_DSP2_0,WKUPDEP_WD_TIMER2_DSP2_1" newline bitfld.long 0x0C 4. "WKUPDEP_WD_TIMER2_IPU1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_IPU1_0,WKUPDEP_WD_TIMER2_IPU1_1" rbitfld.long 0x0C 3. "RESERVED," "0,1" newline bitfld.long 0x0C 2. "WKUPDEP_WD_TIMER2_DSP1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_DSP1_0,WKUPDEP_WD_TIMER2_DSP1_1" bitfld.long 0x0C 1. "WKUPDEP_WD_TIMER2_IPU2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_IPU2_0,WKUPDEP_WD_TIMER2_IPU2_1" newline bitfld.long 0x0C 0. "WKUPDEP_WD_TIMER2_MPU,Wakeup dependency from WDT2 module (SWakeup signal) towards MPU + L3MAIN1 + L4CFG domains" "WKUPDEP_WD_TIMER2_MPU_0,WKUPDEP_WD_TIMER2_MPU_1" line.long 0x10 "RM_WKUPAON_WD_TIMER2_CONTEXT,This register contains dedicated WD_TIMER2 context statuses" hexmask.long 0x10 1.--31. 1. "RESERVED," bitfld.long 0x10 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x14 "PM_WKUPAON_GPIO1_WKDEP,This register controls wakeup dependency based on GPIO1 service requests" hexmask.long.word 0x14 20.--31. 1. "RESERVED," bitfld.long 0x14 19. "WKUPDEP_GPIO1_IRQ2_EVE4,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_EVE4_0,WKUPDEP_GPIO1_IRQ2_EVE4_1" newline bitfld.long 0x14 18. "WKUPDEP_GPIO1_IRQ2_EVE3,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_EVE3_0,WKUPDEP_GPIO1_IRQ2_EVE3_1" bitfld.long 0x14 17. "WKUPDEP_GPIO1_IRQ2_EVE2,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_EVE2_0,WKUPDEP_GPIO1_IRQ2_EVE2_1" newline bitfld.long 0x14 16. "WKUPDEP_GPIO1_IRQ2_EVE1,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_EVE1_0,WKUPDEP_GPIO1_IRQ2_EVE1_1" bitfld.long 0x14 15. "WKUPDEP_GPIO1_IRQ2_DSP2,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_DSP2_0,WKUPDEP_GPIO1_IRQ2_DSP2_1" newline bitfld.long 0x14 14. "WKUPDEP_GPIO1_IRQ2_IPU1,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_IPU1_0,WKUPDEP_GPIO1_IRQ2_IPU1_1" rbitfld.long 0x14 13. "RESERVED," "0,1" newline bitfld.long 0x14 12. "WKUPDEP_GPIO1_IRQ2_DSP1,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_DSP1_0,WKUPDEP_GPIO1_IRQ2_DSP1_1" bitfld.long 0x14 11. "WKUPDEP_GPIO1_IRQ2_IPU2,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_IPU2_0,WKUPDEP_GPIO1_IRQ2_IPU2_1" newline bitfld.long 0x14 10. "WKUPDEP_GPIO1_IRQ2_MPU,Wakeup dependency from GPIO1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_MPU_0,WKUPDEP_GPIO1_IRQ2_MPU_1" bitfld.long 0x14 9. "WKUPDEP_GPIO1_IRQ1_EVE4,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_EVE4_0,WKUPDEP_GPIO1_IRQ1_EVE4_1" newline bitfld.long 0x14 8. "WKUPDEP_GPIO1_IRQ1_EVE3,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_EVE3_0,WKUPDEP_GPIO1_IRQ1_EVE3_1" bitfld.long 0x14 7. "WKUPDEP_GPIO1_IRQ1_EVE2,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_EVE2_0,WKUPDEP_GPIO1_IRQ1_EVE2_1" newline bitfld.long 0x14 6. "WKUPDEP_GPIO1_IRQ1_EVE1,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_EVE1_0,WKUPDEP_GPIO1_IRQ1_EVE1_1" bitfld.long 0x14 5. "WKUPDEP_GPIO1_IRQ1_DSP2,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_DSP2_0,WKUPDEP_GPIO1_IRQ1_DSP2_1" newline bitfld.long 0x14 4. "WKUPDEP_GPIO1_IRQ1_IPU1,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_IPU1_0,WKUPDEP_GPIO1_IRQ1_IPU1_1" rbitfld.long 0x14 3. "RESERVED," "0,1" newline bitfld.long 0x14 2. "WKUPDEP_GPIO1_IRQ1_DSP1,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_DSP1_0,WKUPDEP_GPIO1_IRQ1_DSP1_1" bitfld.long 0x14 1. "WKUPDEP_GPIO1_IRQ1_IPU2,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_IPU2_0,WKUPDEP_GPIO1_IRQ1_IPU2_1" newline bitfld.long 0x14 0. "WKUPDEP_GPIO1_IRQ1_MPU,Wakeup dependency from GPIO1 module (SWakeup signal for POROCPSINTERRUPT1 ) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_MPU_0,WKUPDEP_GPIO1_IRQ1_MPU_1" line.long 0x18 "RM_WKUPAON_GPIO1_CONTEXT,This register contains dedicated GPIO1 context statuses" hexmask.long 0x18 1.--31. 1. "RESERVED," bitfld.long 0x18 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x1C "PM_WKUPAON_TIMER1_WKDEP,This register controls wakeup dependency based on TIMER1 service requests" hexmask.long.tbyte 0x1C 10.--31. 1. "RESERVED," bitfld.long 0x1C 9. "WKUPDEP_TIMER1_EVE4,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_EVE4_0,WKUPDEP_TIMER1_EVE4_1" newline bitfld.long 0x1C 8. "WKUPDEP_TIMER1_EVE3,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_EVE3_0,WKUPDEP_TIMER1_EVE3_1" bitfld.long 0x1C 7. "WKUPDEP_TIMER1_EVE2,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_EVE2_0,WKUPDEP_TIMER1_EVE2_1" newline bitfld.long 0x1C 6. "WKUPDEP_TIMER1_EVE1,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_EVE1_0,WKUPDEP_TIMER1_EVE1_1" bitfld.long 0x1C 5. "WKUPDEP_TIMER1_DSP2,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_DSP2_0,WKUPDEP_TIMER1_DSP2_1" newline bitfld.long 0x1C 4. "WKUPDEP_TIMER1_IPU1,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_IPU1_0,WKUPDEP_TIMER1_IPU1_1" rbitfld.long 0x1C 3. "RESERVED," "0,1" newline bitfld.long 0x1C 2. "WKUPDEP_TIMER1_DSP1,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_DSP1_0,WKUPDEP_TIMER1_DSP1_1" bitfld.long 0x1C 1. "WKUPDEP_TIMER1_IPU2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_IPU2_0,WKUPDEP_TIMER1_IPU2_1" newline bitfld.long 0x1C 0. "WKUPDEP_TIMER1_MPU,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_MPU_0,WKUPDEP_TIMER1_MPU_1" line.long 0x20 "RM_WKUPAON_TIMER1_CONTEXT,This register contains dedicated TIMER1 context statuses" hexmask.long 0x20 1.--31. 1. "RESERVED," bitfld.long 0x20 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x24 "PM_WKUPAON_TIMER12_WKDEP,This register controls wakeup dependency based on TIMER12 service requests" hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED," bitfld.long 0x24 9. "WKUPDEP_TIMER12_EVE4,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_EVE4_0,WKUPDEP_TIMER12_EVE4_1" newline bitfld.long 0x24 8. "WKUPDEP_TIMER12_EVE3,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_EVE3_0,WKUPDEP_TIMER12_EVE3_1" bitfld.long 0x24 7. "WKUPDEP_TIMER12_EVE2,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_EVE2_0,WKUPDEP_TIMER12_EVE2_1" newline bitfld.long 0x24 6. "WKUPDEP_TIMER12_EVE1,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_EVE1_0,WKUPDEP_TIMER12_EVE1_1" bitfld.long 0x24 5. "WKUPDEP_TIMER12_DSP2,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_DSP2_0,WKUPDEP_TIMER12_DSP2_1" newline bitfld.long 0x24 4. "WKUPDEP_TIMER12_IPU1,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_IPU1_0,WKUPDEP_TIMER12_IPU1_1" rbitfld.long 0x24 3. "RESERVED," "0,1" newline bitfld.long 0x24 2. "WKUPDEP_TIMER12_DSP1,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_DSP1_0,WKUPDEP_TIMER12_DSP1_1" bitfld.long 0x24 1. "WKUPDEP_TIMER12_IPU2,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_IPU2_0,WKUPDEP_TIMER12_IPU2_1" newline bitfld.long 0x24 0. "WKUPDEP_TIMER12_MPU,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_MPU_0,WKUPDEP_TIMER12_MPU_1" line.long 0x28 "RM_WKUPAON_TIMER12_CONTEXT,This register contains dedicated TIMER12 context statuses" hexmask.long 0x28 1.--31. 1. "RESERVED," bitfld.long 0x28 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x30++0x03 line.long 0x00 "RM_WKUPAON_COUNTER_32K_CONTEXT,This register contains dedicated COUNTER_32K context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x40++0x03 line.long 0x00 "RM_WKUPAON_SAR_RAM_CONTEXT,This register contains dedicated SAR_RAM context statuses" hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED," bitfld.long 0x00 8. "LOSTMEM_WKUP_BANK,Specify if memory-based context in WKUP_BANK memory bank has been lost due to a previous global cold reset" "LOSTMEM_WKUP_BANK_0,LOSTMEM_WKUP_BANK_1" newline hexmask.long.byte 0x00 1.--7. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x54++0x17 line.long 0x00 "PM_WKUPAON_KBD_WKDEP,This register controls wakeup dependency based on KBD service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_KBD_EVE4,Wakeup dependency from KBD module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_EVE4_0,WKUPDEP_KBD_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_KBD_EVE3,Wakeup dependency from KBD module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_EVE3_0,WKUPDEP_KBD_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_KBD_EVE2,Wakeup dependency from KBD module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_EVE2_0,WKUPDEP_KBD_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_KBD_EVE1,Wakeup dependency from KBD module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_EVE1_0,WKUPDEP_KBD_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_KBD_DSP2,Wakeup dependency from KBD module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_DSP2_0,WKUPDEP_KBD_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_KBD_IPU1,Wakeup dependency from KBD module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_IPU1_0,WKUPDEP_KBD_IPU1_1" rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_KBD_DSP1,Wakeup dependency from KBD module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_DSP1_0,WKUPDEP_KBD_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_KBD_IPU2,Wakeup dependency from KBD module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_IPU2_0,WKUPDEP_KBD_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_KBD_MPU,Wakeup dependency from KBD module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_KBD_MPU_0,WKUPDEP_KBD_MPU_1" line.long 0x04 "RM_WKUPAON_KBD_CONTEXT,This register contains dedicated KBD context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_WKUPAON_UART10_WKDEP,This register controls wakeup dependency based on UART10 service requests" hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED," bitfld.long 0x08 9. "WKUPDEP_UART10_EVE4,Wakeup dependency from UART10 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_EVE4_0,WKUPDEP_UART10_EVE4_1" newline bitfld.long 0x08 8. "WKUPDEP_UART10_EVE3,Wakeup dependency from UART10 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_EVE3_0,WKUPDEP_UART10_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_UART10_EVE2,Wakeup dependency from UART10 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_EVE2_0,WKUPDEP_UART10_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_UART10_EVE1,Wakeup dependency from UART10 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_EVE1_0,WKUPDEP_UART10_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_UART10_DSP2,Wakeup dependency from UART10 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_DSP2_0,WKUPDEP_UART10_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_UART10_IPU1,Wakeup dependency from UART10 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_IPU1_0,WKUPDEP_UART10_IPU1_1" bitfld.long 0x08 3. "WKUPDEP_UART10_SDMA,Wakeup dependency from UART10 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_SDMA_0,WKUPDEP_UART10_SDMA_1" newline bitfld.long 0x08 2. "WKUPDEP_UART10_DSP1,Wakeup dependency from UART10 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_DSP1_0,WKUPDEP_UART10_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_UART10_IPU2,Wakeup dependency from UART10 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_IPU2_0,WKUPDEP_UART10_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_UART10_MPU,Wakeup dependency from UART10 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_MPU_0,WKUPDEP_UART10_MPU_1" line.long 0x0C "RM_WKUPAON_UART10_CONTEXT,This register contains dedicated UART10 context statuses" hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED," bitfld.long 0x0C 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in UART memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" newline hexmask.long.byte 0x0C 1.--7. 1. "RESERVED," bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_WKUPAON_DCAN1_WKDEP,This register controls wakeup dependency based on DCAN1 service requests" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED," bitfld.long 0x10 9. "WKUPDEP_DCAN1_EVE4,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_EVE4_0,WKUPDEP_DCAN1_EVE4_1" newline bitfld.long 0x10 8. "WKUPDEP_DCAN1_EVE3,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_EVE3_0,WKUPDEP_DCAN1_EVE3_1" bitfld.long 0x10 7. "WKUPDEP_DCAN1_EVE2,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_EVE2_0,WKUPDEP_DCAN1_EVE2_1" newline bitfld.long 0x10 6. "WKUPDEP_DCAN1_EVE1,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_EVE1_0,WKUPDEP_DCAN1_EVE1_1" bitfld.long 0x10 5. "WKUPDEP_DCAN1_DSP2,Wakeup dependency from DCAN1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_DSP2_0,WKUPDEP_DCAN1_DSP2_1" newline bitfld.long 0x10 4. "WKUPDEP_DCAN1_IPU1,Wakeup dependency from DCAN1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_IPU1_0,WKUPDEP_DCAN1_IPU1_1" bitfld.long 0x10 3. "WKUPDEP_DCAN1_SDMA,Wakeup dependency from DCAN1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_SDMA_0,WKUPDEP_DCAN1_SDMA_1" newline bitfld.long 0x10 2. "WKUPDEP_DCAN1_DSP1,Wakeup dependency from DCAN1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_DSP1_0,WKUPDEP_DCAN1_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_DCAN1_IPU2,Wakeup dependency from DCAN1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_IPU2_0,WKUPDEP_DCAN1_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_DCAN1_MPU,Wakeup dependency from DCAN1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_MPU_0,WKUPDEP_DCAN1_MPU_1" line.long 0x14 "RM_WKUPAON_DCAN1_CONTEXT,This register contains dedicated DCAN1 context statuses" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED," bitfld.long 0x14 8. "LOSTMEM_DCAN_MEM,Specify if memory-based context in DCAN memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DCAN_MEM_0,LOSTMEM_DCAN_MEM_1" newline hexmask.long.byte 0x14 1.--7. 1. "RESERVED," bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x7C++0x07 line.long 0x00 "PM_WKUPAON_ADC_WKDEP,This register controls wakeup dependency based on ADC service requests" hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED," bitfld.long 0x00 9. "WKUPDEP_ADC_EVE4,Wakeup dependency from ADC module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_EVE4_0,WKUPDEP_ADC_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_ADC_EVE3,Wakeup dependency from ADC module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_EVE3_0,WKUPDEP_ADC_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_ADC_EVE2,Wakeup dependency from ADC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_EVE2_0,WKUPDEP_ADC_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_ADC_EVE1,Wakeup dependency from ADC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_EVE1_0,WKUPDEP_ADC_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_ADC_DSP2,Wakeup dependency from ADC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_DSP2_0,WKUPDEP_ADC_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_ADC_IPU1,Wakeup dependency from ADC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IPU1_0,WKUPDEP_ADC_IPU1_1" rbitfld.long 0x00 3. "RESERVED," "0,1" newline bitfld.long 0x00 2. "WKUPDEP_ADC_DSP1,Wakeup dependency from ADC module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_DSP1_0,WKUPDEP_ADC_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_ADC_IPU2,Wakeup dependency from ADC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_IPU2_0,WKUPDEP_ADC_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_ADC_MPU,Wakeup dependency from ADC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_ADC_MPU_0,WKUPDEP_ADC_MPU_1" line.long 0x04 "RM_WKUPAON_ADC_CONTEXT,This register contains dedicated ADC context statuses" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x90++0x03 line.long 0x00 "RM_WKUPAON_SPARE_SAFETY1_CONTEXT,This register contains dedicated SPARE_SAFETY1 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x98++0x03 line.long 0x00 "RM_WKUPAON_RTI1_CONTEXT,This register contains dedicated RTI1 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xA0++0x03 line.long 0x00 "RM_WKUPAON_RTI2_CONTEXT,This register contains dedicated RTI2 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xA8++0x03 line.long 0x00 "RM_WKUPAON_RTI3_CONTEXT,This register contains dedicated RTI3 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xB0++0x03 line.long 0x00 "RM_WKUPAON_RTI4_CONTEXT,This register contains dedicated RTI4 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xB8++0x03 line.long 0x00 "RM_WKUPAON_RTI5_CONTEXT,This register contains dedicated RTI5 context statuses" hexmask.long 0x00 1.--31. 1. "RESERVED," bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "WR" base ad:0x48485200 rgroup.long 0x00++0x1F line.long 0x00 "WR_IDVER,Subsystem wrapper revision register" line.long 0x04 "WR_SOFT_RESET,Subsystem soft reset register" hexmask.long 0x04 1.--31. 1. "RESERVED," bitfld.long 0x04 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the CPGMACSS_R logic to be reset (INT REGS CPPI)" "0,1" line.long 0x08 "WR_CONTROL,Subsystem control register" hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x08 8. "SS_EEE_EN,Subsystem Energy Efficient Ethernet enable" "EEE disabled,EEE enabled" rbitfld.long 0x08 4.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 2.--3. "MMR_STDBYMODE,Configuration of the local initiator state management mode" "MMR_STDBYMODE_0,MMR_STDBYMODE_1,MMR_STDBYMODE_2,MMR_STDBYMODE_3" bitfld.long 0x08 0.--1. "MMR_IDLEMODE,Configuration of the local initiator state management mode" "MMR_IDLEMODE_0,MMR_IDLEMODE_1,MMR_IDLEMODE_2,MMR_IDLEMODE_3" line.long 0x0C "WR_INT_CONTROL,Subsystem interrupt control" bitfld.long 0x0C 31. "INT_TEST,Interrupt Test - Test bit to the interrupt pacing blocks" "0,1" hexmask.long.word 0x0C 22.--30. 1. "RESERVED," bitfld.long 0x0C 16.--21. "INT_PACE_EN,Interrupt Pacing Enable INT_PACE_EN[0] - Enables RX_PULSE Pacing (0 is pacing bypass) INT_PACE_EN[1] - Enables TX_PULSE Pacing (0 is pacing bypass)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x0C 12.--15. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0C 0.--11. 1. "INT_PRESCALE,Interrupt Counter Prescaler - The number of MAIN_CLK periods in 4us" line.long 0x10 "WR_C0_RX_THRESH_EN,Subsystem core 0 receive threshold int enable register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED," hexmask.long.byte 0x10 0.--7. 1. "C0_RX_THRESH_EN,Core 0 Receive Threshold Enable - Each bit in this register corresponds to the bit in the receive threshold interrupt that is enabled to generate an interrupt on RX_THRESH_PULSE" line.long 0x14 "WR_C0_RX_EN,Subsystem core 0 receive interrupt enable register" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED," hexmask.long.byte 0x14 0.--7. 1. "C0_RX_EN,Core 0 Receive Enable - Each bit in this register corresponds to the bit in the rx interrupt that is enabled to generate an interrupt on RX_PULSE" line.long 0x18 "WR_C0_TX_EN,Subsystem core 0 transmit interrupt enable register" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED," hexmask.long.byte 0x18 0.--7. 1. "C0_TX_EN,Core 0 Transmit Enable - Each bit in this register corresponds to the bit in the tx interrupt that is enabled to generate an interrupt on TX_PULSE" line.long 0x1C "WR_C0_MISC_EN,Subsystem core 0 misc interrupt enable register" hexmask.long 0x1C 5.--31. 1. "RESERVED," bitfld.long 0x1C 0.--4. "C0_MISC_EN,Core 0 Misc Enable - Each bit in this register corresponds to the miscellaneous interrupt (SPF2_PEND SPF1_PEND EVNT_PEND STAT_PEND HOST_PEND MDIO_LINKINT MDIO_USERINT) that is enabled to generate an interrupt on MISC_PULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x40++0x0F line.long 0x00 "WR_C0_RX_THRESH_STAT,Subsystem core 0 rx threshold masked int status register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," hexmask.long.byte 0x00 0.--7. 1. "C0_RX_THRESH_STAT,Core 0 Receive Threshold Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the receive threshold interrupt that is enabled and generating an interrupt on RX_THRESH_PULSE" line.long 0x04 "WR_C0_RX_STAT,Subsystem core 0 rx interrupt masked int status register" hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED," hexmask.long.byte 0x04 0.--7. 1. "C0_RX_STAT,Core 0 Receive Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the Rx interrupt that is enabled and generating an interrupt on RX_PULSE" line.long 0x08 "WR_C0_TX_STAT,Subsystem core 0 tx interrupt masked int status register" hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED," hexmask.long.byte 0x08 0.--7. 1. "C0_TX_STAT,Core 0 Transmit Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the Tx interrupt that is enabled and generating an interrupt on TX_PULSE" line.long 0x0C "WR_C0_MISC_STAT,Subsystem core 0 misc interrupt masked int status register" hexmask.long 0x0C 5.--31. 1. "RESERVED," bitfld.long 0x0C 0.--4. "C0_MISC_STAT,Core 0 Misc Masked Interrupt Status - Each bit corresponds to the miscellaneous interrupt (SPF2_PEND SPF1_PEND EVNT_PEND STAT_PEND HOST_PEND MDIO_LINKINT MDIO_USERINT) that is enabled and generating an interrupt on MISC_PULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x70++0x07 line.long 0x00 "WR_C0_RX_IMAX,Subsystem core 0 receive interrupts per millisecond" hexmask.long 0x00 6.--31. 1. "RESERVED," bitfld.long 0x00 0.--5. "C0_RX_IMAX,Core 0 Receive Interrupts per Millisecond - The maximum number of interrupts per millisecond generated on RX_PULSE if pacing is enabled for this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "WR_C0_TX_IMAX,Subsystem core 0 transmit interrupts per millisecond" hexmask.long 0x04 6.--31. 1. "RESERVED," bitfld.long 0x04 0.--5. "C0_TX_IMAX,Core 0 Transmit Interrupts per Millisecond - The maximum number of interrupts per millisecond generated on TX_PULSE if pacing is enabled for this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x88++0x07 line.long 0x00 "WR_RGMII_CTL,RGMII control signal register" hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED," bitfld.long 0x00 7. "RGMII2_FULLDUPLEX,RGMII 2 Fullduplex - This is the CPRGMII fullduplex output signal" "Half-duplex mode,Full-duplex mode" bitfld.long 0x00 5.--6. "RGMII2_SPEED,RGMII2 Speed - This is the CPRGMII speed output signal" "0,1,2,3" newline bitfld.long 0x00 4. "RGMII2_LINK,RGMII2 Link Indicator - This is the CPRGMII link output signal" "RGMII2 link is down,RGMII2 link is up" bitfld.long 0x00 3. "RGMII1_FULLDUPLEX,RGMII1 Fullduplex - This is the CPRGMII fullduplex output signal" "Half-duplex mode,Full-duplex mode" bitfld.long 0x00 1.--2. "RGMII1_SPEED,RGMII1 Speed - This is the CPRGMII speed output signal" "0,1,2,3" newline bitfld.long 0x00 0. "RGMII1_LINK,RGMII1 Link Indicator - This is the CPRGMII link output signal" "RGMII1 link is down,RGMII1 link is up" line.long 0x04 "WR_STATUS,Subsystem Status register" hexmask.long 0x04 3.--31. 1. "RESERVED," bitfld.long 0x04 2. "SPF2_CLKSTOP_ACK,SPF2 Clockstop Acknowledge - When asserted the subsystem gated clock is not turned on due to SPF2" "0,1" bitfld.long 0x04 1. "SPF1_CLKSTOP_ACK,SPF1 Clockstop Acknowledge - When asserted the subsystem gated clock is not turned on due to SPF1" "0,1" newline bitfld.long 0x04 0. "EEE_CLKSTOP_ACK,CPSW_3G Clockstop Acknowledge - When asserted the subsystem gated clock is not turned on due to the CPSW_3G" "0,1" width 0x0B tree.end endif autoindent.off newline